arm64: dts: rockchip: add usb2-phy support for rk3399

Add usb2-phy nodes and specify phys phandle for ehci.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4c84229789efedc05b6db985750b87e5e32f83d8..62d450935a576f0b199effeffe6908c1eaae3d99 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -248,6 +248,8 @@
                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
                clock-names = "hclk_host0", "hclk_host0_arb";
+               phys = <&u2phy0_host>;
+               phy-names = "usb";
                status = "disabled";
        };
 
@@ -266,6 +268,8 @@
                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
                clock-names = "hclk_host1", "hclk_host1_arb";
+               phys = <&u2phy1_host>;
+               phy-names = "usb";
                status = "disabled";
        };
 
@@ -942,6 +946,40 @@
                        status = "disabled";
                };
 
+               u2phy0: usb2-phy@e450 {
+                       compatible = "rockchip,rk3399-usb2phy";
+                       reg = <0xe450 0x10>;
+                       clocks = <&cru SCLK_USB2PHY0_REF>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       clock-output-names = "clk_usbphy0_480m";
+                       status = "disabled";
+
+                       u2phy0_host: host-port {
+                               #phy-cells = <0>;
+                               interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "linestate";
+                               status = "disabled";
+                       };
+               };
+
+               u2phy1: usb2-phy@e460 {
+                       compatible = "rockchip,rk3399-usb2phy";
+                       reg = <0xe460 0x10>;
+                       clocks = <&cru SCLK_USB2PHY1_REF>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       clock-output-names = "clk_usbphy1_480m";
+                       status = "disabled";
+
+                       u2phy1_host: host-port {
+                               #phy-cells = <0>;
+                               interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "linestate";
+                               status = "disabled";
+                       };
+               };
+
                emmc_phy: phy@f780 {
                        compatible = "rockchip,rk3399-emmc-phy";
                        reg = <0xf780 0x24>;