i960 cgen simulator support.

	* Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c.
	(ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo.
start-sanitize-cygnus
	(CLEANFILES): Add stamp-i960.
	(I960_DEPS): Define.
	(i960c-opc.h, i960c-opc.c, i960c-asm.c, i960c-dis.c, stamp-i960):
	New makefile rules.
end-sanitize-cygnus
	(i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules.
	* Makefile.in: Rebuilt.
	* configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o,
	i960-dis.c to ta.
	* i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig.
	* i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files.

diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize
index 944a219cfdef441e1505c44e7e272d2950cdd93e..49b8a025f3afe17f310df6b7c76322cd0230a729 100644 (file)
--- a/opcodes/.Sanitize
+++ b/opcodes/.Sanitize
@@ -88,6 +88,10 @@ h8500-opc.h
 hppa-dis.c
 i386-dis.c
 i960-dis.c
+i960c-asm.c
+i960c-dis.c
+i960c-opc.c
+i960c-opc.h
 m32r-asm.c
 m32r-dis.c
 m32r-opc.c

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6acd6ecb81484d76e5f0fb6d2eca673ed7b29d78..77f0ab2ac7dfb8a5d45ddde702dd88d26626b089 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,20 @@
+1998-12-07  James E Wilson  <wilson@wilson-pc.cygnus.com>
+
+       * Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c.
+       (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo.
+start-sanitize-cygnus
+       (CLEANFILES): Add stamp-i960.
+       (I960_DEPS): Define.
+       (i960c-opc.h, i960c-opc.c, i960c-asm.c, i960c-dis.c, stamp-i960):
+       New makefile rules.
+end-sanitize-cygnus
+       (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules.
+       * Makefile.in: Rebuilt.
+       * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o,
+       i960-dis.c to ta.
+       * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig.
+       * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files.
+       
 start-sanitize-fr30
 Mon Dec  7 14:33:44 1998  Dave Brolley  <brolley@cygnus.com>
 

diff --git a/opcodes/i960c-asm.c b/opcodes/i960c-asm.c
new file mode 100644 (file)
index 0000000..10a0e5c
--- /dev/null
+++ b/opcodes/i960c-asm.c
@@ -0,0 +1,739 @@
+/* Assembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+THIS FILE IS USED TO GENERATE i960c-asm.c.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sysdep.h"
+#include <ctype.h>
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "i960c-opc.h"
+#include "opintl.h"
+
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+#undef INLINE
+#ifdef __GNUC__
+#define INLINE __inline__
+#else
+#define INLINE
+#endif
+
+/* Used by the ifield rtx function.  */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+     PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, unsigned int, unsigned int,
+             unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
+static const char * parse_insn_normal
+     PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *,
+             const char **, CGEN_FIELDS *));
+static const char * insert_insn_normal
+     PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *,
+             CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
+\f
+/* -- assembler routines inserted here */
+
+/* Main entry point for operand parsing.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.
+*/
+
+const char *
+i960_cgen_parse_operand (od, opindex, strp, fields)
+     CGEN_OPCODE_DESC od;
+     int opindex;
+     const char ** strp;
+     CGEN_FIELDS * fields;
+{
+  const char * errmsg;
+
+  switch (opindex)
+    {
+    case I960_OPERAND_SRC1 :
+      errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_src1);
+      break;
+    case I960_OPERAND_SRC2 :
+      errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_src2);
+      break;
+    case I960_OPERAND_DST :
+      errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_srcdst);
+      break;
+    case I960_OPERAND_LIT1 :
+      errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_LIT1, &fields->f_src1);
+      break;
+    case I960_OPERAND_LIT2 :
+      errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_LIT2, &fields->f_src2);
+      break;
+    case I960_OPERAND_ST_SRC :
+      errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_srcdst);
+      break;
+    case I960_OPERAND_ABASE :
+      errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_abase);
+      break;
+    case I960_OPERAND_OFFSET :
+      errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_OFFSET, &fields->f_offset);
+      break;
+    case I960_OPERAND_SCALE :
+      errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_SCALE, &fields->f_scale);
+      break;
+    case I960_OPERAND_INDEX :
+      errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_index);
+      break;
+    case I960_OPERAND_OPTDISP :
+      errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_OPTDISP, &fields->f_optdisp);
+      break;
+    case I960_OPERAND_BR_SRC1 :
+      errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_br_src1);
+      break;
+    case I960_OPERAND_BR_SRC2 :
+      errmsg = cgen_parse_keyword (od, strp, & i960_cgen_opval_h_gr, & fields->f_br_src2);
+      break;
+    case I960_OPERAND_BR_DISP :
+      {
+        bfd_vma value;
+        errmsg = cgen_parse_address (od, strp, I960_OPERAND_BR_DISP, 0, NULL,  & value);
+        fields->f_br_disp = value;
+      }
+      break;
+    case I960_OPERAND_BR_LIT1 :
+      errmsg = cgen_parse_unsigned_integer (od, strp, I960_OPERAND_BR_LIT1, &fields->f_br_src1);
+      break;
+    case I960_OPERAND_CTRL_DISP :
+      {
+        bfd_vma value;
+        errmsg = cgen_parse_address (od, strp, I960_OPERAND_CTRL_DISP, 0, NULL,  & value);
+        fields->f_ctrl_disp = value;
+      }
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+/* Main entry point for operand insertion.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  It's also needed by GAS to insert operands that couldn't be
+   resolved during parsing.
+*/
+
+const char *
+i960_cgen_insert_operand (od, opindex, fields, buffer, pc)
+     CGEN_OPCODE_DESC od;
+     int opindex;
+     CGEN_FIELDS * fields;
+     CGEN_INSN_BYTES_PTR buffer;
+     bfd_vma pc;
+{
+  const char * errmsg;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case I960_OPERAND_SRC1 :
+      errmsg = insert_normal (od, fields->f_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_SRC2 :
+      errmsg = insert_normal (od, fields->f_src2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_DST :
+      errmsg = insert_normal (od, fields->f_srcdst, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_LIT1 :
+      errmsg = insert_normal (od, fields->f_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_LIT2 :
+      errmsg = insert_normal (od, fields->f_src2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_ST_SRC :
+      errmsg = insert_normal (od, fields->f_srcdst, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_ABASE :
+      errmsg = insert_normal (od, fields->f_abase, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_OFFSET :
+      errmsg = insert_normal (od, fields->f_offset, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 20, 12, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_SCALE :
+      errmsg = insert_normal (od, fields->f_scale, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 22, 3, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_INDEX :
+      errmsg = insert_normal (od, fields->f_index, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_OPTDISP :
+      errmsg = insert_normal (od, fields->f_optdisp, 0|(1<<CGEN_OPERAND_UNSIGNED), 32, 0, 32, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_BR_SRC1 :
+      errmsg = insert_normal (od, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_BR_SRC2 :
+      errmsg = insert_normal (od, fields->f_br_src2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_BR_DISP :
+      {
+        long value = fields->f_br_disp;
+        value = ((int) (((value) - (pc))) >> (2));
+        errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 19, 11, 32, total_length, buffer);
+      }
+      break;
+    case I960_OPERAND_BR_LIT1 :
+      errmsg = insert_normal (od, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, buffer);
+      break;
+    case I960_OPERAND_CTRL_DISP :
+      {
+        long value = fields->f_ctrl_disp;
+        value = ((int) (((value) - (pc))) >> (2));
+        errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 22, 32, total_length, buffer);
+      }
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
+              opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+cgen_parse_fn * const i960_cgen_parse_handlers[] = 
+{
+  0, /* default */
+  parse_insn_normal,
+};
+
+cgen_insert_fn * const i960_cgen_insert_handlers[] = 
+{
+  0, /* default */
+  insert_insn_normal,
+};
+
+void
+i960_cgen_init_asm (od)
+     CGEN_OPCODE_DESC od;
+{
+}
+
+\f
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal.  */
+
+static INLINE void
+insert_1 (od, value, start, length, word_length, bufp)
+     CGEN_OPCODE_DESC od;
+     unsigned long value;
+     int start,length,word_length;
+     unsigned char *bufp;
+{
+  unsigned long x,mask;
+  int shift;
+  int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG;
+
+  switch (word_length)
+    {
+    case 8:
+      x = *bufp;
+      break;
+    case 16:
+      if (big_p)
+       x = bfd_getb16 (bufp);
+      else
+       x = bfd_getl16 (bufp);
+      break;
+    case 24:
+      /* ??? This may need reworking as these cases don't necessarily
+        want the first byte and the last two bytes handled like this.  */
+      if (big_p)
+       x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
+      else
+       x = bfd_getl16 (bufp) | (bufp[2] << 16);
+      break;
+    case 32:
+      if (big_p)
+       x = bfd_getb32 (bufp);
+      else
+       x = bfd_getl32 (bufp);
+      break;
+    default :
+      abort ();
+    }
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+  switch (word_length)
+    {
+    case 8:
+      *bufp = x;
+      break;
+    case 16:
+      if (big_p)
+       bfd_putb16 (x, bufp);
+      else
+       bfd_putl16 (x, bufp);
+      break;
+    case 24:
+      /* ??? This may need reworking as these cases don't necessarily
+        want the first byte and the last two bytes handled like this.  */
+      if (big_p)
+       {
+         bufp[0] = x >> 16;
+         bfd_putb16 (x, bufp + 1);
+       }
+      else
+       {
+         bfd_putl16 (x, bufp);
+         bufp[2] = x >> 16;
+       }
+      break;
+    case 32:
+      if (big_p)
+       bfd_putb32 (x, bufp);
+      else
+       bfd_putl32 (x, bufp);
+      break;
+    default :
+      abort ();
+    }
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+   ATTRS is a mask of the boolean attributes.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   The result is an error message or NULL if success.  */
+
+/* ??? This duplicates functionality with bfd's howto table and
+   bfd_install_relocation.  */
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static const char *
+insert_normal (od, value, attrs, word_offset, start, length, word_length,
+              total_length, buffer)
+     CGEN_OPCODE_DESC od;
+     long value;
+     unsigned int attrs;
+     unsigned int word_offset, start, length, word_length, total_length;
+     CGEN_INSN_BYTES_PTR buffer;
+{
+  static char errbuf[100];
+  /* Written this way to avoid undefined behaviour.  */
+  unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value.  */
+  if (length == 0)
+    return NULL;
+
+  if (CGEN_INT_INSN_P
+      && word_offset != 0)
+    abort ();
+
+  if (word_length > 32)
+    abort ();
+
+  /* For architectures with insns smaller than the insn-base-bitsize,
+     word_length may be too big.  */
+#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE
+  if (word_offset == 0
+      && word_length > total_length)
+    word_length = total_length;
+#endif
+
+  /* Ensure VALUE will fit.  */
+  if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0)
+    {
+      unsigned long maxval = mask;
+      if ((unsigned long) value > maxval)
+       {
+         /* xgettext:c-format */
+         sprintf (errbuf,
+                  _("operand out of range (%lu not between 0 and %lu)"),
+                  value, maxval);
+         return errbuf;
+       }
+    }
+  else
+    {
+      long minval = - (1L << (length - 1));
+      long maxval = (1L << (length - 1)) - 1;
+      if (value < minval || value > maxval)
+       {
+         sprintf
+           /* xgettext:c-format */
+           (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+            value, minval, maxval);
+         return errbuf;
+       }
+    }
+
+#if CGEN_INT_INSN_P
+
+  {
+    int shift;
+
+    if (CGEN_INSN_LSB0_P)
+      shift = (start + 1) - length;
+    else
+      shift = word_length - (start + length);
+    *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+  }
+
+#else /* ! CGEN_INT_INSN_P */
+
+  {
+    unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+    insert_1 (od, value, start, length, word_length, bufp);
+  }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  return NULL;
+}
+\f
+/* Default insn parser.
+
+   The syntax string is scanned and operands are parsed and stored in FIELDS.
+   Relocs are queued as we go via other callbacks.
+
+   ??? Note that this is currently an all-or-nothing parser.  If we fail to
+   parse the instruction, we return 0 and the caller will start over from
+   the beginning.  Backtracking will be necessary in parsing subexpressions,
+   but that can be handled there.  Not handling backtracking here may get
+   expensive in the case of the m68k.  Deal with later.
+
+   Returns NULL for success, an error message for failure.
+*/
+
+static const char *
+parse_insn_normal (od, insn, strp, fields)
+     CGEN_OPCODE_DESC od;
+     const CGEN_INSN * insn;
+     const char ** strp;
+     CGEN_FIELDS * fields;
+{
+  const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
+  const char * str = *strp;
+  const char * errmsg;
+  const char * p;
+  const unsigned char * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+  /* FIXME: wip */
+  int past_opcode_p;
+#endif
+
+  /* For now we assume the mnemonic is first (there are no leading operands).
+     We can parse it without needing to set up operand parsing.
+     GAS's input scrubber will ensure mnemonics are lowercase, but we may
+     not be called from GAS.  */
+  p = CGEN_INSN_MNEMONIC (insn);
+  while (*p && tolower (*p) == tolower (*str))
+    ++p, ++str;
+  
+  if (* p || (* str && !isspace (* str)))
+    return _("unrecognized instruction");
+
+  CGEN_INIT_PARSE (od);
+  cgen_init_parse_operand (od);
+#ifdef CGEN_MNEMONIC_OPERANDS
+  past_opcode_p = 0;
+#endif
+
+  /* We don't check for (*str != '\0') here because we want to parse
+     any trailing fake arguments in the syntax string.  */
+  syn = CGEN_SYNTAX_STRING (syntax);
+
+  /* Mnemonics come first for now, ensure valid string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    abort ();
+
+  ++syn;
+
+  while (* syn != 0)
+    {
+      /* Non operand chars must match exactly.  */
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+       {
+         if (*str == CGEN_SYNTAX_CHAR (* syn))
+           {
+#ifdef CGEN_MNEMONIC_OPERANDS
+             if (* syn == ' ')
+               past_opcode_p = 1;
+#endif
+             ++ syn;
+             ++ str;
+           }
+         else
+           {
+             /* Syntax char didn't match.  Can't be this insn.  */
+             /* FIXME: would like to return something like
+                "expected char `c'" */
+             return _("syntax error");
+           }
+         continue;
+       }
+
+      /* We have an operand of some sort.  */
+      errmsg = i960_cgen_parse_operand (od, CGEN_SYNTAX_FIELD (*syn),
+                                         &str, fields);
+      if (errmsg)
+       return errmsg;
+
+      /* Done with this operand, continue with next one.  */
+      ++ syn;
+    }
+
+  /* If we're at the end of the syntax string, we're done.  */
+  if (* syn == '\0')
+    {
+      /* FIXME: For the moment we assume a valid `str' can only contain
+        blanks now.  IE: We needn't try again with a longer version of
+        the insn and it is assumed that longer versions of insns appear
+        before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
+      while (isspace (* str))
+       ++ str;
+
+      if (* str != '\0')
+       return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+      return NULL;
+    }
+
+  /* We couldn't parse it.  */
+  return _("unrecognized instruction");
+}
+
+/* Default insn builder (insert handler).
+   The instruction is recorded in CGEN_INT_INSN_P byte order
+   (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is
+   recorded in host byte order, otherwise BUFFER is an array of bytes and the
+   value is recorded in target byte order).
+   The result is an error message or NULL if success.  */
+
+static const char *
+insert_insn_normal (od, insn, fields, buffer, pc)
+     CGEN_OPCODE_DESC od;
+     const CGEN_INSN * insn;
+     CGEN_FIELDS * fields;
+     CGEN_INSN_BYTES_PTR buffer;
+     bfd_vma pc;
+{
+  const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
+  unsigned long value;
+  const unsigned char * syn;
+
+  CGEN_INIT_INSERT (od);
+  value = CGEN_INSN_BASE_VALUE (insn);
+
+  /* If we're recording insns as numbers (rather than a string of bytes),
+     target byte order handling is deferred until later.  */
+
+#if CGEN_INT_INSN_P
+
+  *buffer = value;
+
+#else
+
+  cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE,
+                                       CGEN_FIELDS_BITSIZE (fields)),
+                      value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* ??? It would be better to scan the format's fields.
+     Still need to be able to insert a value based on the operand though;
+     e.g. storing a branch displacement that got resolved later.
+     Needs more thought first.  */
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn)
+    {
+      const char *errmsg;
+
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+       continue;
+
+      errmsg = i960_cgen_insert_operand (od, CGEN_SYNTAX_FIELD (*syn),
+                                          fields, buffer, pc);
+      if (errmsg)
+       return errmsg;
+    }
+
+  return NULL;
+}
+\f
+/* Main entry point.
+   This routine is called for each instruction to be assembled.
+   STR points to the insn to be assembled.
+   We assume all necessary tables have been initialized.
+   The assembled instruction, less any fixups, is stored in BUF.
+   Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+   still needs to be converted to target byte order, otherwise BUF is an array
+   of bytes in target byte order.
+   The result is a pointer to the insn's entry in the opcode table,
+   or NULL if an error occured (an error message will have already been
+   printed).
+
+   Note that when processing (non-alias) macro-insns,
+   this function recurses.  */
+
+const CGEN_INSN *
+i960_cgen_assemble_insn (od, str, fields, buf, errmsg)
+     CGEN_OPCODE_DESC od;
+     const char * str;
+     CGEN_FIELDS * fields;
+     CGEN_INSN_BYTES_PTR buf;
+     char ** errmsg;
+{
+  const char * start;
+  CGEN_INSN_LIST * ilist;
+
+  /* Skip leading white space.  */
+  while (isspace (* str))
+    ++ str;
+
+  /* The instructions are stored in hashed lists.
+     Get the first in the list.  */
+  ilist = CGEN_ASM_LOOKUP_INSN (od, str);
+
+  /* Keep looking until we find a match.  */
+
+  start = str;
+  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+    {
+      const CGEN_INSN *insn = ilist->insn;
+
+#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */
+      /* Is this insn supported by the selected cpu?  */
+      if (! i960_cgen_insn_supported (od, insn))
+       continue;
+#endif
+
+      /* If the RELAX attribute is set, this is an insn that shouldn't be
+        chosen immediately.  Instead, it is used during assembler/linker
+        relaxation if possible.  */
+      if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0)
+       continue;
+
+      str = start;
+
+      /* Allow parse/insert handlers to obtain length of insn.  */
+      CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+      if (! CGEN_PARSE_FN (insn) (od, insn, & str, fields))
+       {
+         /* ??? 0 is passed for `pc' */
+         if (CGEN_INSERT_FN (insn) (od, insn, fields, buf, (bfd_vma) 0) != NULL)
+           continue;
+         /* It is up to the caller to actually output the insn and any
+            queued relocs.  */
+         return insn;
+       }
+
+      /* Try the next entry.  */
+    }
+
+  /* FIXME: We can return a better error message than this.
+     Need to track why it failed and pick the right one.  */
+  {
+    static char errbuf[100];
+    if (strlen (start) > 50)
+      /* xgettext:c-format */
+      sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+    else 
+      /* xgettext:c-format */
+      sprintf (errbuf, _("bad instruction `%.50s'"), start);
+      
+    *errmsg = errbuf;
+    return NULL;
+  }
+}
+\f
+#if 0 /* This calls back to GAS which we can't do without care.  */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+   This lets GAS parse registers for us.
+   ??? Interesting idea but not currently used.  */
+
+/* Record each member of OPVALS in the assembler's symbol table.
+   FIXME: Not currently used.  */
+
+void
+i960_cgen_asm_hash_keywords (od, opvals)
+     CGEN_OPCODE_DESC od;
+     CGEN_KEYWORD * opvals;
+{
+  CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
+  const CGEN_KEYWORD_ENTRY * ke;
+
+  while ((ke = cgen_keyword_search_next (& search)) != NULL)
+    {
+#if 0 /* Unnecessary, should be done in the search routine.  */
+      if (! i960_cgen_opval_supported (ke))
+       continue;
+#endif
+      cgen_asm_record_register (od, ke->name, ke->value);
+    }
+}
+
+#endif /* 0 */

diff --git a/opcodes/i960c-dis.c b/opcodes/i960c-dis.c
new file mode 100644 (file)
index 0000000..4985fec
--- /dev/null
+++ b/opcodes/i960c-dis.c
@@ -0,0 +1,782 @@
+/* Disassembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+THIS FILE IS USED TO GENERATE i960c-dis.c.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "i960c-opc.h"
+#include "opintl.h"
+
+#undef INLINE
+#ifdef __GNUC__
+#define INLINE __inline__
+#else
+#define INLINE
+#endif
+
+/* Default text to print if an instruction isn't recognized.  */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+/* Used by the ifield rtx function.  */
+#define FLD(f) (fields->f)
+
+static int extract_normal
+     PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+             unsigned int, unsigned int, unsigned int, unsigned int,
+             unsigned int, unsigned int, bfd_vma, long *));
+static void print_normal
+     PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int));
+static void print_address
+     PARAMS ((CGEN_OPCODE_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
+static void print_keyword
+     PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
+static int extract_insn_normal
+     PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+             CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
+static void print_insn_normal
+     PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
+             bfd_vma, int));
+static int print_insn PARAMS ((CGEN_OPCODE_DESC, bfd_vma,
+                              disassemble_info *, char *, int));
+static int default_print_insn
+     PARAMS ((CGEN_OPCODE_DESC, bfd_vma, disassemble_info *));
+\f
+/* -- disassembler routines inserted here */
+
+/* Main entry point for operand extraction.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.
+*/
+
+int
+i960_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc)
+     CGEN_OPCODE_DESC od;
+     int opindex;
+     CGEN_EXTRACT_INFO *ex_info;
+     CGEN_INSN_INT insn_value;
+     CGEN_FIELDS * fields;
+     bfd_vma pc;
+{
+  int length;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case I960_OPERAND_SRC1 :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, pc, & fields->f_src1);
+      break;
+    case I960_OPERAND_SRC2 :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, pc, & fields->f_src2);
+      break;
+    case I960_OPERAND_DST :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, pc, & fields->f_srcdst);
+      break;
+    case I960_OPERAND_LIT1 :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, pc, & fields->f_src1);
+      break;
+    case I960_OPERAND_LIT2 :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, pc, & fields->f_src2);
+      break;
+    case I960_OPERAND_ST_SRC :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, pc, & fields->f_srcdst);
+      break;
+    case I960_OPERAND_ABASE :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, pc, & fields->f_abase);
+      break;
+    case I960_OPERAND_OFFSET :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 20, 12, 32, total_length, pc, & fields->f_offset);
+      break;
+    case I960_OPERAND_SCALE :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 22, 3, 32, total_length, pc, & fields->f_scale);
+      break;
+    case I960_OPERAND_INDEX :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 27, 5, 32, total_length, pc, & fields->f_index);
+      break;
+    case I960_OPERAND_OPTDISP :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 32, 0, 32, 32, total_length, pc, & fields->f_optdisp);
+      break;
+    case I960_OPERAND_BR_SRC1 :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, pc, & fields->f_br_src1);
+      break;
+    case I960_OPERAND_BR_SRC2 :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 13, 5, 32, total_length, pc, & fields->f_br_src2);
+      break;
+    case I960_OPERAND_BR_DISP :
+      {
+        long value;
+        length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 19, 11, 32, total_length, pc, & value);
+        value = ((((value) << (2))) + (pc));
+        fields->f_br_disp = value;
+      }
+      break;
+    case I960_OPERAND_BR_LIT1 :
+      length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 5, 32, total_length, pc, & fields->f_br_src1);
+      break;
+    case I960_OPERAND_CTRL_DISP :
+      {
+        long value;
+        length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 22, 32, total_length, pc, & value);
+        value = ((((value) << (2))) + (pc));
+        fields->f_ctrl_disp = value;
+      }
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
+              opindex);
+      abort ();
+    }
+
+  return length;
+}
+
+/* Main entry point for printing operands.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.
+*/
+
+void
+i960_cgen_print_operand (od, opindex, info, fields, attrs, pc, length)
+     CGEN_OPCODE_DESC od;
+     int opindex;
+     disassemble_info * info;
+     CGEN_FIELDS * fields;
+     void const * attrs;
+     bfd_vma pc;
+     int length;
+{
+  switch (opindex)
+    {
+    case I960_OPERAND_SRC1 :
+      print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_src1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case I960_OPERAND_SRC2 :
+      print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_src2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case I960_OPERAND_DST :
+      print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_srcdst, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case I960_OPERAND_LIT1 :
+      print_normal (od, info, fields->f_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case I960_OPERAND_LIT2 :
+      print_normal (od, info, fields->f_src2, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case I960_OPERAND_ST_SRC :
+      print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_srcdst, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case I960_OPERAND_ABASE :
+      print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_abase, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case I960_OPERAND_OFFSET :
+      print_normal (od, info, fields->f_offset, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case I960_OPERAND_SCALE :
+      print_normal (od, info, fields->f_scale, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case I960_OPERAND_INDEX :
+      print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_index, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case I960_OPERAND_OPTDISP :
+      print_normal (od, info, fields->f_optdisp, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case I960_OPERAND_BR_SRC1 :
+      print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case I960_OPERAND_BR_SRC2 :
+      print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_br_src2, 0|(1<<CGEN_OPERAND_UNSIGNED));
+      break;
+    case I960_OPERAND_BR_DISP :
+      print_address (od, info, fields->f_br_disp, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case I960_OPERAND_BR_LIT1 :
+      print_normal (od, info, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+      break;
+    case I960_OPERAND_CTRL_DISP :
+      print_address (od, info, fields->f_ctrl_disp, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
+              opindex);
+    abort ();
+  }
+}
+
+cgen_extract_fn * const i960_cgen_extract_handlers[] = 
+{
+  0, /* default */
+  extract_insn_normal,
+};
+
+cgen_print_fn * const i960_cgen_print_handlers[] = 
+{
+  0, /* default */
+  print_insn_normal,
+};
+
+
+void
+i960_cgen_init_dis (od)
+     CGEN_OPCODE_DESC od;
+{
+}
+
+\f
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+   Ensure sufficient bytes are cached in EX_INFO.
+   OFFSET is the offset in bytes from the start of the insn of the value.
+   BYTES is the length of the needed value.
+   Returns 1 for success, 0 for failure.  */
+
+static INLINE int
+fill_cache (od, ex_info, offset, bytes, pc)
+     CGEN_OPCODE_DESC od;
+     CGEN_EXTRACT_INFO *ex_info;
+     int offset, bytes;
+     bfd_vma pc;
+{
+  /* It's doubtful that the middle part has already been fetched so
+     we don't optimize that case.  kiss.  */
+  int mask;
+  disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+  /* First do a quick check.  */
+  mask = (1 << bytes) - 1;
+  if (((ex_info->valid >> offset) & mask) == mask)
+    return 1;
+
+  /* Search for the first byte we need to read.  */
+  for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+    if (! (mask & ex_info->valid))
+      break;
+
+  if (bytes)
+    {
+      int status;
+
+      pc += offset;
+      status = (*info->read_memory_func)
+       (pc, ex_info->insn_bytes + offset, bytes, info);
+
+      if (status != 0)
+       {
+         (*info->memory_error_func) (status, pc, info);
+         return 0;
+       }
+
+      ex_info->valid |= ((1 << bytes) - 1) << offset;
+    }
+
+  return 1;
+}
+
+/* Subroutine of extract_normal.  */
+
+static INLINE long
+extract_1 (od, ex_info, start, length, word_length, bufp, pc)
+     CGEN_OPCODE_DESC od;
+     CGEN_EXTRACT_INFO *ex_info;
+     int start,length,word_length;
+     unsigned char *bufp;
+     bfd_vma pc;
+{
+  unsigned long x,mask;
+  int shift;
+  int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG;
+
+  switch (word_length)
+    {
+    case 8:
+      x = *bufp;
+      break;
+    case 16:
+      if (big_p)
+       x = bfd_getb16 (bufp);
+      else
+       x = bfd_getl16 (bufp);
+      break;
+    case 24:
+      /* ??? This may need reworking as these cases don't necessarily
+        want the first byte and the last two bytes handled like this.  */
+      if (big_p)
+       x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
+      else
+       x = bfd_getl16 (bufp) | (bufp[2] << 16);
+      break;
+    case 32:
+      if (big_p)
+       x = bfd_getb32 (bufp);
+      else
+       x = bfd_getl32 (bufp);
+      break;
+    default :
+      abort ();
+    }
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  return (x >> shift) & mask;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+   INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order,
+   or sometimes less for cases like the m32r where the base insn size is 32
+   but some insns are 16 bits.
+   ATTRS is a mask of the boolean attributes.  We only need `UNSIGNED',
+   but for generality we take a bitmask of all of them.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   Returns 1 for success, 0 for failure.  */
+
+/* ??? The return code isn't properly used.  wip.  */
+
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static int
+extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length,
+               word_length, total_length, pc, valuep)
+     CGEN_OPCODE_DESC od;
+     CGEN_EXTRACT_INFO *ex_info;
+     CGEN_INSN_INT insn_value;
+     unsigned int attrs;
+     unsigned int word_offset, start, length, word_length, total_length;
+     bfd_vma pc;
+     long *valuep;
+{
+  CGEN_INSN_INT value;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value
+     so give it a standard value of zero.  */
+  if (length == 0)
+    {
+      *valuep = 0;
+      return 1;
+    }
+
+  if (CGEN_INT_INSN_P
+      && word_offset != 0)
+    abort ();
+
+  if (word_length > 32)
+    abort ();
+
+  /* For architectures with insns smaller than the insn-base-bitsize,
+     word_length may be too big.  */
+#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE
+  if (word_offset == 0
+      && word_length > total_length)
+    word_length = total_length;
+#endif
+
+  /* Does the value reside in INSN_VALUE?  */
+
+  if (word_offset == 0)
+    {
+      /* Written this way to avoid undefined behaviour.  */
+      CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+      if (CGEN_INSN_LSB0_P)
+       value = insn_value >> ((start + 1) - length);
+      else
+       value = insn_value >> (word_length - (start + length));
+      value &= mask;
+      /* sign extend? */
+      if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
+         && (value & (1L << (length - 1))))
+       value |= ~mask;
+    }
+
+#if ! CGEN_INT_INSN_P
+
+  else
+    {
+      unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+      if (word_length > 32)
+       abort ();
+
+      if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+       return 0;
+
+      value = extract_1 (od, ex_info, start, length, word_length, bufp, pc);
+    }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  *valuep = value;
+
+  return 1;
+}
+
+/* Default print handler.  */
+
+static void
+print_normal (od, dis_info, value, attrs, pc, length)
+     CGEN_OPCODE_DESC od;
+     PTR dis_info;
+     long value;
+     unsigned int attrs;
+     bfd_vma pc;
+     int length;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_NORMAL
+  CGEN_PRINT_NORMAL (od, info, value, attrs, pc, length);
+#endif
+
+  /* Print the operand as directed by the attributes.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+    ; /* nothing to do */
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
+    (*info->fprintf_func) (info->stream, "0x%lx", value);
+  else
+    (*info->fprintf_func) (info->stream, "%ld", value);
+}
+
+/* Default address handler.  */
+
+static void
+print_address (od, dis_info, value, attrs, pc, length)
+     CGEN_OPCODE_DESC od;
+     PTR dis_info;
+     bfd_vma value;
+     unsigned int attrs;
+     bfd_vma pc;
+     int length;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_ADDRESS
+  CGEN_PRINT_ADDRESS (od, info, value, attrs, pc, length);
+#endif
+
+  /* Print the operand as directed by the attributes.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+    ; /* nothing to do */
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+    (*info->print_address_func) (value, info);
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+    (*info->print_address_func) (value, info);
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
+    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+  else
+    (*info->fprintf_func) (info->stream, "%ld", (long) value);
+}
+
+/* Keyword print handler.  */
+
+static void
+print_keyword (od, dis_info, keyword_table, value, attrs)
+     CGEN_OPCODE_DESC od;
+     PTR dis_info;
+     CGEN_KEYWORD *keyword_table;
+     long value;
+     unsigned int attrs;
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const CGEN_KEYWORD_ENTRY *ke;
+
+  ke = cgen_keyword_lookup_value (keyword_table, value);
+  if (ke != NULL)
+    (*info->fprintf_func) (info->stream, "%s", ke->name);
+  else
+    (*info->fprintf_func) (info->stream, "???");
+}
+\f
+/* Default insn extractor.
+
+   INSN_VALUE is the first CGEN_BASE_INSN_SIZE bytes, translated to host order.
+   The extracted fields are stored in FIELDS.
+   EX_INFO is used to handle reading variable length insns.
+   Return the length of the insn in bits, or 0 if no match,
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+extract_insn_normal (od, insn, ex_info, insn_value, fields, pc)
+     CGEN_OPCODE_DESC od;
+     const CGEN_INSN *insn;
+     CGEN_EXTRACT_INFO *ex_info;
+     CGEN_INSN_INT insn_value;
+     CGEN_FIELDS *fields;
+     bfd_vma pc;
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const unsigned char *syn;
+
+  CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+  CGEN_INIT_EXTRACT (od);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      int length;
+
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+       continue;
+
+      length = i960_cgen_extract_operand (od, CGEN_SYNTAX_FIELD (*syn),
+                                           ex_info, insn_value, fields, pc);
+      if (length <= 0)
+       return length;
+    }
+
+  /* We recognized and successfully extracted this insn.  */
+  return CGEN_INSN_BITSIZE (insn);
+}
+
+/* Default insn printer.
+
+   DIS_INFO is defined as `PTR' so the disassembler needn't know anything
+   about disassemble_info.  */
+
+static void
+print_insn_normal (od, dis_info, insn, fields, pc, length)
+     CGEN_OPCODE_DESC od;
+     PTR dis_info;
+     const CGEN_INSN *insn;
+     CGEN_FIELDS *fields;
+     bfd_vma pc;
+     int length;
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const unsigned char *syn;
+
+  CGEN_INIT_PRINT (od);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+       {
+         (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+         continue;
+       }
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+       {
+         (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+         continue;
+       }
+
+      /* We have an operand.  */
+      i960_cgen_print_operand (od, CGEN_SYNTAX_FIELD (*syn), info,
+                                fields, CGEN_INSN_ATTRS (insn), pc, length);
+    }
+}
+\f
+/* Utility to print an insn.
+   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+   The result is the size of the insn in bytes or zero for an unknown insn
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+print_insn (od, pc, info, buf, buflen)
+     CGEN_OPCODE_DESC od;
+     bfd_vma pc;
+     disassemble_info *info;
+     char *buf;
+     int buflen;
+{
+  unsigned long insn_value;
+  const CGEN_INSN_LIST *insn_list;
+  CGEN_EXTRACT_INFO ex_info;
+
+  ex_info.dis_info = info;
+  ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1;
+  ex_info.insn_bytes = buf;
+
+  switch (buflen)
+    {
+    case 1:
+      insn_value = buf[0];
+      break;
+    case 2:
+      insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
+      break;
+    case 4:
+      insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
+      break;
+    default:
+      abort ();
+    }
+
+  /* The instructions are stored in hash lists.
+     Pick the first one and keep trying until we find the right one.  */
+
+  insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value);
+  while (insn_list != NULL)
+    {
+      const CGEN_INSN *insn = insn_list->insn;
+      CGEN_FIELDS fields;
+      int length;
+
+#if 0 /* not needed as insn shouldn't be in hash lists if not supported */
+      /* Supported by this cpu?  */
+      if (! i960_cgen_insn_supported (od, insn))
+       continue;
+#endif
+
+      /* Basic bit mask must be correct.  */
+      /* ??? May wish to allow target to defer this check until the extract
+        handler.  */
+      if ((insn_value & CGEN_INSN_BASE_MASK (insn))
+         == CGEN_INSN_BASE_VALUE (insn))
+       {
+         /* Printing is handled in two passes.  The first pass parses the
+            machine insn and extracts the fields.  The second pass prints
+            them.  */
+
+         length = (*CGEN_EXTRACT_FN (insn)) (od, insn, &ex_info, insn_value,
+                                             &fields, pc);
+         /* length < 0 -> error */
+         if (length < 0)
+           return length;
+         if (length > 0)
+           {
+             (*CGEN_PRINT_FN (insn)) (od, info, insn, &fields, pc, length);
+             /* length is in bits, result is in bytes */
+             return length / 8;
+           }
+       }
+
+      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+    }
+
+  return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+   The result is the size of the insn in bytes or zero for an unknown insn
+   or -1 if an error occured fetching bytes.  */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (od, pc, info)
+     CGEN_OPCODE_DESC od;
+     bfd_vma pc;
+     disassemble_info *info;
+{
+  char buf[CGEN_MAX_INSN_SIZE];
+  int status;
+
+  /* Read the base part of the insn.  */
+
+  status = (*info->read_memory_func) (pc, buf, CGEN_BASE_INSN_SIZE, info);
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  return print_insn (od, pc, info, buf, CGEN_BASE_INSN_SIZE);
+}
+
+/* Main entry point.
+   Print one instruction from PC on INFO->STREAM.
+   Return the size of the instruction (in bytes).  */
+
+int
+print_insn_i960 (pc, info)
+     bfd_vma pc;
+     disassemble_info *info;
+{
+  int length;
+  static CGEN_OPCODE_DESC od = 0;
+  int mach = info->mach;
+  int big_p = info->endian == BFD_ENDIAN_BIG;
+
+  /* If we haven't initialized yet, initialize the opcode table.  */
+  if (! od)
+    {
+      od = i960_cgen_opcode_open (mach,
+                                   big_p ?
+                                   CGEN_ENDIAN_BIG
+                                   : CGEN_ENDIAN_LITTLE);
+      i960_cgen_init_dis (od);
+    }
+  /* If we've switched cpu's, re-initialize.  */
+  /* ??? Perhaps we should use BFD_ENDIAN.  */
+  else if (mach != CGEN_OPCODE_MACH (od)
+          || (CGEN_OPCODE_ENDIAN (od)
+              != (big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE)))
+    {
+      cgen_set_cpu (od, mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
+    }
+
+  /* We try to have as much common code as possible.
+     But at this point some targets need to take over.  */
+  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
+     but if not possible try to move this hook elsewhere rather than
+     have two hooks.  */
+  length = CGEN_PRINT_INSN (od, pc, info);
+  if (length > 0)
+    return length;
+  if (length < 0)
+    return -1;
+
+  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+  return CGEN_DEFAULT_INSN_SIZE;
+}

diff --git a/opcodes/i960c-opc.c b/opcodes/i960c-opc.c
new file mode 100644 (file)
index 0000000..e8b4c01
--- /dev/null
+++ b/opcodes/i960c-opc.c
@@ -0,0 +1,5829 @@
+/* Generic opcode table support for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+THIS FILE IS USED TO GENERATE i960c-opc.c.
+
+Copyright (C) 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "libiberty.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "i960c-opc.h"
+#include "opintl.h"
+
+/* Used by the ifield rtx function.  */
+#define FLD(f) (fields->f)
+
+/* The hash functions are recorded here to help keep assembler code out of
+   the disassembler and vice versa.  */
+
+static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int asm_hash_insn PARAMS ((const char *));
+static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
+
+/* Look up instruction INSN_VALUE and extract its fields.
+   INSN, if non-null, is the insn table entry.
+   Otherwise INSN_VALUE is examined to compute it.
+   LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
+   0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
+   If INSN != NULL, LENGTH must be valid.
+   ALIAS_P is non-zero if alias insns are to be included in the search.
+
+   The result is a pointer to the insn table entry, or NULL if the instruction
+   wasn't recognized.  */
+
+const CGEN_INSN *
+i960_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
+     CGEN_OPCODE_DESC od;
+     const CGEN_INSN *insn;
+     CGEN_INSN_BYTES insn_value;
+     int length;
+     CGEN_FIELDS *fields;
+     int alias_p;
+{
+  unsigned char buf[CGEN_MAX_INSN_SIZE];
+  unsigned char *bufp;
+  CGEN_INSN_INT base_insn;
+#if CGEN_INT_INSN_P
+  CGEN_EXTRACT_INFO *info = NULL;
+#else
+  CGEN_EXTRACT_INFO ex_info;
+  CGEN_EXTRACT_INFO *info = &ex_info;
+#endif
+
+#if CGEN_INT_INSN_P
+  cgen_put_insn_value (od, buf, length, insn_value);
+  bufp = buf;
+  base_insn = insn_value; /*???*/
+#else
+  ex_info.dis_info = NULL;
+  ex_info.insn_bytes = insn_value;
+  ex_info.valid = -1;
+  base_insn = cgen_get_insn_value (od, buf, length);
+  bufp = insn_value;
+#endif
+
+  if (!insn)
+    {
+      const CGEN_INSN_LIST *insn_list;
+
+      /* The instructions are stored in hash lists.
+        Pick the first one and keep trying until we find the right one.  */
+
+      insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
+      while (insn_list != NULL)
+       {
+         insn = insn_list->insn;
+
+         if (alias_p
+             || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
+           {
+             /* Basic bit mask must be correct.  */
+             /* ??? May wish to allow target to defer this check until the
+                extract handler.  */
+             if ((base_insn & CGEN_INSN_BASE_MASK (insn))
+                 == CGEN_INSN_BASE_VALUE (insn))
+               {
+                 /* ??? 0 is passed for `pc' */
+                 int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
+                                                          base_insn, fields,
+                                                          (bfd_vma) 0);
+                 if (elength > 0)
+                   {
+                     /* sanity check */
+                     if (length != 0 && length != elength)
+                       abort ();
+                     return insn;
+                   }
+               }
+           }
+
+         insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+       }
+    }
+  else
+    {
+      /* Sanity check: can't pass an alias insn if ! alias_p.  */
+      if (! alias_p
+         && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
+       abort ();
+      /* Sanity check: length must be correct.  */
+      if (length != CGEN_INSN_BITSIZE (insn))
+       abort ();
+
+      /* ??? 0 is passed for `pc' */
+      length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
+                                         (bfd_vma) 0);
+      /* Sanity check: must succeed.
+        Could relax this later if it ever proves useful.  */
+      if (length == 0)
+       abort ();
+      return insn;
+    }
+
+  return NULL;
+}
+
+/* Fill in the operand instances used by INSN whose operands are FIELDS.
+   INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
+   in.  */
+
+void
+i960_cgen_get_insn_operands (od, insn, fields, indices)
+     CGEN_OPCODE_DESC od;
+     const CGEN_INSN * insn;
+     const CGEN_FIELDS * fields;
+     int *indices;
+{
+  const CGEN_OPERAND_INSTANCE *opinst;
+  int i;
+
+  for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
+       opinst != NULL
+        && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
+       ++i, ++opinst)
+    {
+      const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
+      if (op == NULL)
+       indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
+      else
+       indices[i] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
+                                                 fields);
+    }
+}
+
+/* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS
+   isn't known.
+   The INSN, INSN_VALUE, and LENGTH arguments are passed to
+   i960_cgen_lookup_insn unchanged.
+
+   The result is the insn table entry or NULL if the instruction wasn't
+   recognized.  */
+
+const CGEN_INSN *
+i960_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
+     CGEN_OPCODE_DESC od;
+     const CGEN_INSN *insn;
+     CGEN_INSN_BYTES insn_value;
+     int length;
+     int *indices;
+{
+  CGEN_FIELDS fields;
+
+  /* Pass non-zero for ALIAS_P only if INSN != NULL.
+     If INSN == NULL, we want a real insn.  */
+  insn = i960_cgen_lookup_insn (od, insn, insn_value, length, &fields,
+                                 insn != NULL);
+  if (! insn)
+    return NULL;
+
+  i960_cgen_get_insn_operands (od, insn, &fields, indices);
+  return insn;
+}
+/* Attributes.  */
+
+static const CGEN_ATTR_ENTRY MACH_attr[] =
+{
+  { "base", MACH_BASE },
+  { "i960_ka_sa", MACH_I960_KA_SA },
+  { "i960_ca", MACH_I960_CA },
+  { "max", MACH_MAX },
+  { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
+{
+  { "CACHE-ADDR", NULL },
+  { "PC", NULL },
+  { "PROFILE", NULL },
+  { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
+{
+  { "ABS-ADDR", NULL },
+  { "NEGATIVE", NULL },
+  { "PCREL-ADDR", NULL },
+  { "RELAX", NULL },
+  { "RELOC", NULL },
+  { "SEM-ONLY", NULL },
+  { "SIGN-OPT", NULL },
+  { "UNSIGNED", NULL },
+  { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
+{
+  { "ALIAS", NULL },
+  { "COND-CTI", NULL },
+  { "DELAY-SLOT", NULL },
+  { "NO-DIS", NULL },
+  { "RELAX", NULL },
+  { "RELAXABLE", NULL },
+  { "SKIP-CTI", NULL },
+  { "UNCOND-CTI", NULL },
+  { "VIRTUAL", NULL },
+  { 0, 0 }
+};
+
+CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] = 
+{
+  { "fp", 31 },
+  { "sp", 1 },
+  { "r0", 0 },
+  { "r1", 1 },
+  { "r2", 2 },
+  { "r3", 3 },
+  { "r4", 4 },
+  { "r5", 5 },
+  { "r6", 6 },
+  { "r7", 7 },
+  { "r8", 8 },
+  { "r9", 9 },
+  { "r10", 10 },
+  { "r11", 11 },
+  { "r12", 12 },
+  { "r13", 13 },
+  { "r14", 14 },
+  { "r15", 15 },
+  { "g0", 16 },
+  { "g1", 17 },
+  { "g2", 18 },
+  { "g3", 19 },
+  { "g4", 20 },
+  { "g5", 21 },
+  { "g6", 22 },
+  { "g7", 23 },
+  { "g8", 24 },
+  { "g9", 25 },
+  { "g10", 26 },
+  { "g11", 27 },
+  { "g12", 28 },
+  { "g13", 29 },
+  { "g14", 30 },
+  { "g15", 31 }
+};
+
+CGEN_KEYWORD i960_cgen_opval_h_gr = 
+{
+  & i960_cgen_opval_h_gr_entries[0],
+  34
+};
+
+CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] = 
+{
+  { "cc", 0 }
+};
+
+CGEN_KEYWORD i960_cgen_opval_h_cc = 
+{
+  & i960_cgen_opval_h_cc_entries[0],
+  1
+};
+
+
+/* The hardware table.  */
+
+#define HW_ENT(n) i960_cgen_hw_entries[n]
+static const CGEN_HW_ENTRY i960_cgen_hw_entries[] =
+{
+  { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
+  { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
+  { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
+  { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
+  { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
+  { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
+  { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
+  { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
+  { 0 }
+};
+
+/* The instruction field table.  */
+
+static const CGEN_IFLD i960_cgen_ifld_table[] =
+{
+  { I960_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } }  },
+  { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_M3, "f-m3", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_M2, "f-m2", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_M1, "f-m1", 0, 32, 20, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_INDEX, "f-index", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { 0, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { 0 } }  },
+  { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { 0, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { 0 } }  },
+  { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } }  },
+  { 0 }
+};
+
+/* The operand table.  */
+
+#define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
+#define OP_ENT(op) i960_cgen_operand_table[OPERAND (op)]
+
+const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] =
+{
+/* pc: program counter */
+  { "pc", & HW_ENT (HW_H_PC), 0, 0,
+    { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } }  },
+/* src1: source register 1 */
+  { "src1", & HW_ENT (HW_H_GR), 27, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* src2: source register 2 */
+  { "src2", & HW_ENT (HW_H_GR), 13, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* dst: source/dest register */
+  { "dst", & HW_ENT (HW_H_GR), 8, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* lit1: literal 1 */
+  { "lit1", & HW_ENT (HW_H_UINT), 27, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* lit2: literal 2 */
+  { "lit2", & HW_ENT (HW_H_UINT), 13, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* st_src: store src */
+  { "st_src", & HW_ENT (HW_H_GR), 8, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* abase: abase */
+  { "abase", & HW_ENT (HW_H_GR), 13, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* offset: offset */
+  { "offset", & HW_ENT (HW_H_UINT), 20, 12,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* scale: scale */
+  { "scale", & HW_ENT (HW_H_UINT), 22, 3,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* index: index */
+  { "index", & HW_ENT (HW_H_GR), 27, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* optdisp: optional displacement */
+  { "optdisp", & HW_ENT (HW_H_UINT), 0, 32,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* br_src1: branch src1 */
+  { "br_src1", & HW_ENT (HW_H_GR), 8, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* br_src2: branch src2 */
+  { "br_src2", & HW_ENT (HW_H_GR), 13, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* br_disp: branch displacement */
+  { "br_disp", & HW_ENT (HW_H_IADDR), 19, 11,
+    { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
+/* br_lit1: branch literal 1 */
+  { "br_lit1", & HW_ENT (HW_H_UINT), 8, 5,
+    { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
+/* ctrl_disp: ctrl branch disp */
+  { "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22,
+    { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
+};
+
+/* Operand references.  */
+
+#define INPUT CGEN_OPERAND_INSTANCE_INPUT
+#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
+#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
+
+static const CGEN_OPERAND_INSTANCE fmt_mulo_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_mulo1_ops[] = {
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_mulo2_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_mulo3_ops[] = {
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_remo_ops[] = {
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_remo1_ops[] = {
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_remo2_ops[] = {
+  { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_remo3_ops[] = {
+  { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_not_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_not1_ops[] = {
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_not2_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_not3_ops[] = {
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_emul_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_emul1_ops[] = {
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_emul2_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_emul3_ops[] = {
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_movl_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_movl1_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_movt_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_movt1_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_movq_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_src1_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_movq1_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_modpc_ops[] = {
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lda_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lda_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lda_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldob_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldob_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldob_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldos_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldos_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldos_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldib_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldib_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldib_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldis_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldis_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldis_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldl_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldl_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldl_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldt_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldt_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldt_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldq_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldq_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldq_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stob_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stob_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stob_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stos_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stos_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stos_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stl_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stl_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stl_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stt_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stt_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stt_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stq_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_offset_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stq_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stq_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_disp_ops[] = {
+  { INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpobe_reg_ops[] = {
+  { INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 },
+  { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
+  { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpobe_lit_ops[] = {
+  { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (BR_LIT1), 0, 0 },
+  { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
+  { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpobl_reg_ops[] = {
+  { INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC1), 0, 0 },
+  { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 },
+  { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpobl_lit_ops[] = {
+  { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 },
+  { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 },
+  { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bbc_lit_ops[] = {
+  { INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 },
+  { INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
+  { INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpi1_ops[] = {
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 },
+  { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+  { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpi2_ops[] = {
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 },
+  { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_cmpi3_ops[] = {
+  { INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 },
+  { INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 },
+  { OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_testno_reg_ops[] = {
+  { INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bno_ops[] = {
+  { INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, COND_REF },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_b_ops[] = {
+  { INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_offset_ops[] = {
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_index_ops[] = {
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
+  { INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bx_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_disp_ops[] = {
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_callx_disp_ops[] = {
+  { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
+  { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
+  { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
+  { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
+  { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
+  { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
+  { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
+  { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
+  { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
+  { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
+  { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
+  { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
+  { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
+  { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
+  { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
+  { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
+  { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
+  { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
+  { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
+  { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
+  { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
+  { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
+  { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
+  { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
+  { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_ops[] = {
+  { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
+  { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
+  { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
+  { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
+  { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
+  { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
+  { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
+  { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
+  { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
+  { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
+  { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
+  { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
+  { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
+  { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
+  { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
+  { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
+  { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
+  { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
+  { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
+  { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
+  { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
+  { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
+  { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
+  { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_offset_ops[] = {
+  { INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
+  { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
+  { INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
+  { INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
+  { INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
+  { INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
+  { INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
+  { INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
+  { INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
+  { INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
+  { INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
+  { INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
+  { INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
+  { INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
+  { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
+  { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
+  { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
+  { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
+  { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
+  { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
+  { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
+  { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
+  { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
+  { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
+  { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
+  { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
+  { INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
+  { OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
+  { OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
+  { OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
+  { OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
+  { OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
+  { OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
+  { OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
+  { OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
+  { OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
+  { OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
+  { OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
+  { OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
+  { OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
+  { OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
+  { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+  { OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_calls_ops[] = {
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_fmark_ops[] = {
+  { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
+  { 0 }
+};
+
+static const CGEN_OPERAND_INSTANCE fmt_flushreg_ops[] = {
+  { INPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
+  { 0 }
+};
+
+#undef INPUT
+#undef OUTPUT
+#undef COND_REF
+
+/* Instruction formats.  */
+
+#define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
+
+static const CGEN_IFMT fmt_mulo = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_mulo1 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_mulo2 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_mulo3 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_remo = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_remo1 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_remo2 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_remo3 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_not = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_not1 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_not2 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_not3 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_emul = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_emul1 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_emul2 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_emul3 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_movl = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_movl1 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_movt = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_movt1 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_movq = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_movq1 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_modpc = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_lda_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_lda_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_lda_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_lda_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_lda_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_lda_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_lda_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_lda_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldob_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldob_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldob_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldob_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldob_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldob_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldob_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldob_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldos_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldos_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldos_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldos_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldos_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldos_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldos_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldos_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldib_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldib_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldib_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldib_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldib_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldib_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldib_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldib_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldis_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldis_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldis_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldis_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldis_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldis_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldis_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldis_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldl_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldl_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldl_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldl_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldl_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldl_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldl_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldl_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldt_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldt_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldt_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldt_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldt_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldt_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldt_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldt_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldq_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldq_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ldq_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldq_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldq_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldq_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldq_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_ldq_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_st_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_st_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_st_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_st_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_st_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_st_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_st_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_st_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stob_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stob_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stob_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stob_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stob_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stob_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stob_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stob_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stos_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stos_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stos_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stos_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stos_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stos_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stos_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stos_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stl_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stl_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stl_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stl_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stl_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stl_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stl_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stl_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stt_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stt_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stt_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stt_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stt_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stt_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stt_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stt_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stq_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stq_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_stq_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stq_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stq_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stq_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stq_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_stq_indirect_index_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpobe_reg = {
+  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpobe_lit = {
+  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpobl_reg = {
+  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpobl_lit = {
+  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_bbc_lit = {
+  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpi = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpi1 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpi2 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpi3 = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_testno_reg = {
+  32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_bno = {
+  32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_b = {
+  32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_bx_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_bx_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_bx_indirect_index = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_bx_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_bx_indirect_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_callx_disp = {
+  32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_callx_indirect = {
+  32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
+};
+
+static const CGEN_IFMT fmt_callx_indirect_offset = {
+  32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
+};
+
+static const CGEN_IFMT fmt_ret = {
+  32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
+};
+
+static const CGEN_IFMT fmt_calls = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_fmark = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+static const CGEN_IFMT fmt_flushreg = {
+  32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
+};
+
+#undef F
+
+#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table.
+   This is currently non-static because the simulator accesses it
+   directly.  */
+
+const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { { 0 }, 0 },
+/* mulo $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MULO, "mulo", "mulo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo, { 0x70000080 },
+    (PTR) & fmt_mulo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* mulo $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MULO1, "mulo1", "mulo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo1, { 0x70000880 },
+    (PTR) & fmt_mulo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* mulo $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MULO2, "mulo2", "mulo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo2, { 0x70001080 },
+    (PTR) & fmt_mulo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* mulo $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MULO3, "mulo3", "mulo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo3, { 0x70001880 },
+    (PTR) & fmt_mulo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* remo $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_REMO, "remo", "remo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x70000400 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* remo $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_REMO1, "remo1", "remo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x70000c00 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* remo $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_REMO2, "remo2", "remo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x70001400 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* remo $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_REMO3, "remo3", "remo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x70001c00 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* divo $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_DIVO, "divo", "divo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x70000580 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* divo $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_DIVO1, "divo1", "divo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x70000d80 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* divo $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_DIVO2, "divo2", "divo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x70001580 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* divo $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_DIVO3, "divo3", "divo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x70001d80 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* remi $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_REMI, "remi", "remi",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x74000400 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* remi $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_REMI1, "remi1", "remi",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x74000c00 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* remi $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_REMI2, "remi2", "remi",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x74001400 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* remi $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_REMI3, "remi3", "remi",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x74001c00 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* divi $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_DIVI, "divi", "divi",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x74000580 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* divi $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_DIVI1, "divi1", "divi",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x74000d80 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* divi $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_DIVI2, "divi2", "divi",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x74001580 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* divi $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_DIVI3, "divi3", "divi",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x74001d80 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* addo $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ADDO, "addo", "addo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo, { 0x59000000 },
+    (PTR) & fmt_mulo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* addo $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ADDO1, "addo1", "addo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo1, { 0x59000800 },
+    (PTR) & fmt_mulo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* addo $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ADDO2, "addo2", "addo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo2, { 0x59001000 },
+    (PTR) & fmt_mulo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* addo $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ADDO3, "addo3", "addo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo3, { 0x59001800 },
+    (PTR) & fmt_mulo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* subo $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SUBO, "subo", "subo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x59000100 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* subo $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SUBO1, "subo1", "subo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x59000900 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* subo $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SUBO2, "subo2", "subo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x59001100 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* subo $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SUBO3, "subo3", "subo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x59001900 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* notbit $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOTBIT, "notbit", "notbit",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo, { 0x58000000 },
+    (PTR) & fmt_mulo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* notbit $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOTBIT1, "notbit1", "notbit",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo1, { 0x58000800 },
+    (PTR) & fmt_mulo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* notbit $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOTBIT2, "notbit2", "notbit",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo2, { 0x58001000 },
+    (PTR) & fmt_mulo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* notbit $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOTBIT3, "notbit3", "notbit",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo3, { 0x58001800 },
+    (PTR) & fmt_mulo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* and $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_AND, "and", "and",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo, { 0x58000080 },
+    (PTR) & fmt_mulo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* and $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_AND1, "and1", "and",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo1, { 0x58000880 },
+    (PTR) & fmt_mulo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* and $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_AND2, "and2", "and",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo2, { 0x58001080 },
+    (PTR) & fmt_mulo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* and $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_AND3, "and3", "and",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo3, { 0x58001880 },
+    (PTR) & fmt_mulo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* andnot $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ANDNOT, "andnot", "andnot",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x58000100 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* andnot $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ANDNOT1, "andnot1", "andnot",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x58000900 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* andnot $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ANDNOT2, "andnot2", "andnot",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x58001100 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* andnot $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ANDNOT3, "andnot3", "andnot",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x58001900 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* setbit $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SETBIT, "setbit", "setbit",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo, { 0x58000180 },
+    (PTR) & fmt_mulo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* setbit $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SETBIT1, "setbit1", "setbit",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo1, { 0x58000980 },
+    (PTR) & fmt_mulo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* setbit $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SETBIT2, "setbit2", "setbit",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo2, { 0x58001180 },
+    (PTR) & fmt_mulo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* setbit $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SETBIT3, "setbit3", "setbit",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo3, { 0x58001980 },
+    (PTR) & fmt_mulo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* notand $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOTAND, "notand", "notand",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x58000200 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* notand $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOTAND1, "notand1", "notand",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x58000a00 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* notand $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOTAND2, "notand2", "notand",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x58001200 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* notand $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOTAND3, "notand3", "notand",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x58001a00 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* xor $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_XOR, "xor", "xor",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo, { 0x58000300 },
+    (PTR) & fmt_mulo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* xor $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_XOR1, "xor1", "xor",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo1, { 0x58000b00 },
+    (PTR) & fmt_mulo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* xor $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_XOR2, "xor2", "xor",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo2, { 0x58001300 },
+    (PTR) & fmt_mulo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* xor $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_XOR3, "xor3", "xor",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo3, { 0x58001b00 },
+    (PTR) & fmt_mulo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* or $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_OR, "or", "or",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo, { 0x58000380 },
+    (PTR) & fmt_mulo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* or $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_OR1, "or1", "or",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo1, { 0x58000b80 },
+    (PTR) & fmt_mulo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* or $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_OR2, "or2", "or",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo2, { 0x58001380 },
+    (PTR) & fmt_mulo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* or $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_OR3, "or3", "or",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo3, { 0x58001b80 },
+    (PTR) & fmt_mulo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* nor $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOR, "nor", "nor",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x58000400 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* nor $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOR1, "nor1", "nor",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x58000c00 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* nor $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOR2, "nor2", "nor",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x58001400 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* nor $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOR3, "nor3", "nor",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x58001c00 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* not $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOT, "not", "not",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_not, { 0x58000500 },
+    (PTR) & fmt_not_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* not $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOT1, "not1", "not",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_not1, { 0x58000d00 },
+    (PTR) & fmt_not1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* not $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOT2, "not2", "not",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_not2, { 0x58001500 },
+    (PTR) & fmt_not2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* not $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_NOT3, "not3", "not",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_not3, { 0x58001d00 },
+    (PTR) & fmt_not3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* clrbit $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CLRBIT, "clrbit", "clrbit",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo, { 0x58000600 },
+    (PTR) & fmt_mulo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* clrbit $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CLRBIT1, "clrbit1", "clrbit",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo1, { 0x58000e00 },
+    (PTR) & fmt_mulo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* clrbit $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CLRBIT2, "clrbit2", "clrbit",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo2, { 0x58001600 },
+    (PTR) & fmt_mulo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* clrbit $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CLRBIT3, "clrbit3", "clrbit",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_mulo3, { 0x58001e00 },
+    (PTR) & fmt_mulo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shlo $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHLO, "shlo", "shlo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x59000600 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shlo $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHLO1, "shlo1", "shlo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x59000e00 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shlo $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHLO2, "shlo2", "shlo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x59001600 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shlo $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHLO3, "shlo3", "shlo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x59001e00 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shro $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHRO, "shro", "shro",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x59000400 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shro $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHRO1, "shro1", "shro",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x59000c00 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shro $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHRO2, "shro2", "shro",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x59001400 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shro $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHRO3, "shro3", "shro",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x59001c00 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shli $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHLI, "shli", "shli",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x59000700 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shli $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHLI1, "shli1", "shli",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x59000f00 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shli $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHLI2, "shli2", "shli",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x59001700 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shli $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHLI3, "shli3", "shli",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x59001f00 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shri $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHRI, "shri", "shri",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo, { 0x59000580 },
+    (PTR) & fmt_remo_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shri $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHRI1, "shri1", "shri",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo1, { 0x59000d80 },
+    (PTR) & fmt_remo1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shri $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHRI2, "shri2", "shri",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo2, { 0x59001580 },
+    (PTR) & fmt_remo2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* shri $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_SHRI3, "shri3", "shri",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_remo3, { 0x59001d80 },
+    (PTR) & fmt_remo3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* emul $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_EMUL, "emul", "emul",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_emul, { 0x67000000 },
+    (PTR) & fmt_emul_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* emul $lit1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_EMUL1, "emul1", "emul",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_emul1, { 0x67000800 },
+    (PTR) & fmt_emul1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* emul $src1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_EMUL2, "emul2", "emul",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_emul2, { 0x67001000 },
+    (PTR) & fmt_emul2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* emul $lit1, $lit2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_EMUL3, "emul3", "emul",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
+    & fmt_emul3, { 0x67001800 },
+    (PTR) & fmt_emul3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* mov $src1, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MOV, "mov", "mov",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
+    & fmt_not2, { 0x5c001600 },
+    (PTR) & fmt_not2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* mov $lit1, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MOV1, "mov1", "mov",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
+    & fmt_not3, { 0x5c001e00 },
+    (PTR) & fmt_not3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* movl $src1, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MOVL, "movl", "movl",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
+    & fmt_movl, { 0x5d001600 },
+    (PTR) & fmt_movl_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* movl $lit1, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MOVL1, "movl1", "movl",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
+    & fmt_movl1, { 0x5d001e00 },
+    (PTR) & fmt_movl1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* movt $src1, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MOVT, "movt", "movt",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
+    & fmt_movt, { 0x5e001600 },
+    (PTR) & fmt_movt_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* movt $lit1, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MOVT1, "movt1", "movt",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
+    & fmt_movt1, { 0x5e001e00 },
+    (PTR) & fmt_movt1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* movq $src1, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MOVQ, "movq", "movq",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
+    & fmt_movq, { 0x5f001600 },
+    (PTR) & fmt_movq_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* movq $lit1, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MOVQ1, "movq1", "movq",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
+    & fmt_movq1, { 0x5f001e00 },
+    (PTR) & fmt_movq1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* modpc $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MODPC, "modpc", "modpc",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_modpc, { 0x65000280 },
+    (PTR) & fmt_modpc_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* modac $src1, $src2, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_MODAC, "modac", "modac",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
+    & fmt_modpc, { 0x64000280 },
+    (PTR) & fmt_modpc_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* lda $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDA_OFFSET, "lda-offset", "lda",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_lda_offset, { 0x8c000000 },
+    (PTR) & fmt_lda_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* lda $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_lda_indirect_offset, { 0x8c002000 },
+    (PTR) & fmt_lda_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* lda ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDA_INDIRECT, "lda-indirect", "lda",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_lda_indirect, { 0x8c001000 },
+    (PTR) & fmt_lda_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* lda ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_lda_indirect_index, { 0x8c001c00 },
+    (PTR) & fmt_lda_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* lda $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDA_DISP, "lda-disp", "lda",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_lda_disp, { 0x8c003000 },
+    (PTR) & fmt_lda_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* lda $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_lda_indirect_disp, { 0x8c003400 },
+    (PTR) & fmt_lda_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* lda $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_lda_index_disp, { 0x8c003800 },
+    (PTR) & fmt_lda_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* lda $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_lda_indirect_index_disp, { 0x8c003c00 },
+    (PTR) & fmt_lda_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ld $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LD_OFFSET, "ld-offset", "ld",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_ld_offset, { 0x90000000 },
+    (PTR) & fmt_ld_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ld $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ld_indirect_offset, { 0x90002000 },
+    (PTR) & fmt_ld_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ld ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LD_INDIRECT, "ld-indirect", "ld",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ld_indirect, { 0x90001000 },
+    (PTR) & fmt_ld_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ld ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ld_indirect_index, { 0x90001c00 },
+    (PTR) & fmt_ld_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ld $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LD_DISP, "ld-disp", "ld",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_ld_disp, { 0x90003000 },
+    (PTR) & fmt_ld_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ld $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ld_indirect_disp, { 0x90003400 },
+    (PTR) & fmt_ld_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ld $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ld_index_disp, { 0x90003800 },
+    (PTR) & fmt_ld_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ld $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ld_indirect_index_disp, { 0x90003c00 },
+    (PTR) & fmt_ld_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldob $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_ldob_offset, { 0x80000000 },
+    (PTR) & fmt_ldob_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldob $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldob_indirect_offset, { 0x80002000 },
+    (PTR) & fmt_ldob_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldob ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldob_indirect, { 0x80001000 },
+    (PTR) & fmt_ldob_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldob ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldob_indirect_index, { 0x80001c00 },
+    (PTR) & fmt_ldob_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldob $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOB_DISP, "ldob-disp", "ldob",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_ldob_disp, { 0x80003000 },
+    (PTR) & fmt_ldob_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldob $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldob_indirect_disp, { 0x80003400 },
+    (PTR) & fmt_ldob_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldob $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldob_index_disp, { 0x80003800 },
+    (PTR) & fmt_ldob_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldob $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldob_indirect_index_disp, { 0x80003c00 },
+    (PTR) & fmt_ldob_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldos $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_ldos_offset, { 0x88000000 },
+    (PTR) & fmt_ldos_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldos $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldos_indirect_offset, { 0x88002000 },
+    (PTR) & fmt_ldos_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldos ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldos_indirect, { 0x88001000 },
+    (PTR) & fmt_ldos_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldos ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldos_indirect_index, { 0x88001c00 },
+    (PTR) & fmt_ldos_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldos $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOS_DISP, "ldos-disp", "ldos",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_ldos_disp, { 0x88003000 },
+    (PTR) & fmt_ldos_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldos $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldos_indirect_disp, { 0x88003400 },
+    (PTR) & fmt_ldos_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldos $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldos_index_disp, { 0x88003800 },
+    (PTR) & fmt_ldos_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldos $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldos_indirect_index_disp, { 0x88003c00 },
+    (PTR) & fmt_ldos_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldib $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_ldib_offset, { 0xc0000000 },
+    (PTR) & fmt_ldib_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldib $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldib_indirect_offset, { 0xc0002000 },
+    (PTR) & fmt_ldib_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldib ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldib_indirect, { 0xc0001000 },
+    (PTR) & fmt_ldib_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldib ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldib_indirect_index, { 0xc0001c00 },
+    (PTR) & fmt_ldib_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldib $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIB_DISP, "ldib-disp", "ldib",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_ldib_disp, { 0xc0003000 },
+    (PTR) & fmt_ldib_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldib $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldib_indirect_disp, { 0xc0003400 },
+    (PTR) & fmt_ldib_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldib $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldib_index_disp, { 0xc0003800 },
+    (PTR) & fmt_ldib_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldib $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldib_indirect_index_disp, { 0xc0003c00 },
+    (PTR) & fmt_ldib_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldis $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_ldis_offset, { 0xc8000000 },
+    (PTR) & fmt_ldis_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldis $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldis_indirect_offset, { 0xc8002000 },
+    (PTR) & fmt_ldis_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldis ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldis_indirect, { 0xc8001000 },
+    (PTR) & fmt_ldis_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldis ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldis_indirect_index, { 0xc8001c00 },
+    (PTR) & fmt_ldis_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldis $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIS_DISP, "ldis-disp", "ldis",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_ldis_disp, { 0xc8003000 },
+    (PTR) & fmt_ldis_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldis $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldis_indirect_disp, { 0xc8003400 },
+    (PTR) & fmt_ldis_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldis $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldis_index_disp, { 0xc8003800 },
+    (PTR) & fmt_ldis_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldis $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldis_indirect_index_disp, { 0xc8003c00 },
+    (PTR) & fmt_ldis_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldl $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDL_OFFSET, "ldl-offset", "ldl",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_ldl_offset, { 0x98000000 },
+    (PTR) & fmt_ldl_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldl $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldl_indirect_offset, { 0x98002000 },
+    (PTR) & fmt_ldl_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldl ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldl_indirect, { 0x98001000 },
+    (PTR) & fmt_ldl_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldl ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldl_indirect_index, { 0x98001c00 },
+    (PTR) & fmt_ldl_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldl $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDL_DISP, "ldl-disp", "ldl",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_ldl_disp, { 0x98003000 },
+    (PTR) & fmt_ldl_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldl $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldl_indirect_disp, { 0x98003400 },
+    (PTR) & fmt_ldl_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldl $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldl_index_disp, { 0x98003800 },
+    (PTR) & fmt_ldl_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldl $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldl_indirect_index_disp, { 0x98003c00 },
+    (PTR) & fmt_ldl_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldt $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDT_OFFSET, "ldt-offset", "ldt",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_ldt_offset, { 0xa0000000 },
+    (PTR) & fmt_ldt_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldt $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldt_indirect_offset, { 0xa0002000 },
+    (PTR) & fmt_ldt_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldt ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldt_indirect, { 0xa0001000 },
+    (PTR) & fmt_ldt_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldt ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldt_indirect_index, { 0xa0001c00 },
+    (PTR) & fmt_ldt_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldt $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDT_DISP, "ldt-disp", "ldt",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_ldt_disp, { 0xa0003000 },
+    (PTR) & fmt_ldt_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldt $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldt_indirect_disp, { 0xa0003400 },
+    (PTR) & fmt_ldt_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldt $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldt_index_disp, { 0xa0003800 },
+    (PTR) & fmt_ldt_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldt $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldt_indirect_index_disp, { 0xa0003c00 },
+    (PTR) & fmt_ldt_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldq $offset, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq",
+    { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
+    & fmt_ldq_offset, { 0xb0000000 },
+    (PTR) & fmt_ldq_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldq $offset($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldq_indirect_offset, { 0xb0002000 },
+    (PTR) & fmt_ldq_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldq ($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq",
+    { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldq_indirect, { 0xb0001000 },
+    (PTR) & fmt_ldq_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldq ($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldq_indirect_index, { 0xb0001c00 },
+    (PTR) & fmt_ldq_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldq $optdisp, $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDQ_DISP, "ldq-disp", "ldq",
+    { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
+    & fmt_ldq_disp, { 0xb0003000 },
+    (PTR) & fmt_ldq_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldq $optdisp($abase), $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
+    & fmt_ldq_indirect_disp, { 0xb0003400 },
+    (PTR) & fmt_ldq_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldq $optdisp[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq",
+    { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldq_index_disp, { 0xb0003800 },
+    (PTR) & fmt_ldq_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* ldq $optdisp($abase)[$index*S$scale], $dst */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
+    & fmt_ldq_indirect_index_disp, { 0xb0003c00 },
+    (PTR) & fmt_ldq_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* st $st_src, $offset */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ST_OFFSET, "st-offset", "st",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
+    & fmt_st_offset, { 0x92000000 },
+    (PTR) & fmt_st_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* st $st_src, $offset($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
+    & fmt_st_indirect_offset, { 0x92002000 },
+    (PTR) & fmt_st_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* st $st_src, ($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ST_INDIRECT, "st-indirect", "st",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
+    & fmt_st_indirect, { 0x92001000 },
+    (PTR) & fmt_st_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* st $st_src, ($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_st_indirect_index, { 0x92001c00 },
+    (PTR) & fmt_st_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* st $st_src, $optdisp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ST_DISP, "st-disp", "st",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
+    & fmt_st_disp, { 0x92003000 },
+    (PTR) & fmt_st_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* st $st_src, $optdisp($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
+    & fmt_st_indirect_disp, { 0x92003400 },
+    (PTR) & fmt_st_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* st $st_src, $optdisp[$index*S$scale */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ST_INDEX_DISP, "st-index-disp", "st",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
+    & fmt_st_index_disp, { 0x92003800 },
+    (PTR) & fmt_st_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* st $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_st_indirect_index_disp, { 0x92003c00 },
+    (PTR) & fmt_st_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stob $st_src, $offset */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOB_OFFSET, "stob-offset", "stob",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
+    & fmt_stob_offset, { 0x82000000 },
+    (PTR) & fmt_stob_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stob $st_src, $offset($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
+    & fmt_stob_indirect_offset, { 0x82002000 },
+    (PTR) & fmt_stob_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stob $st_src, ($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOB_INDIRECT, "stob-indirect", "stob",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
+    & fmt_stob_indirect, { 0x82001000 },
+    (PTR) & fmt_stob_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stob $st_src, ($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stob_indirect_index, { 0x82001c00 },
+    (PTR) & fmt_stob_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stob $st_src, $optdisp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOB_DISP, "stob-disp", "stob",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
+    & fmt_stob_disp, { 0x82003000 },
+    (PTR) & fmt_stob_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stob $st_src, $optdisp($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
+    & fmt_stob_indirect_disp, { 0x82003400 },
+    (PTR) & fmt_stob_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stob $st_src, $optdisp[$index*S$scale */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
+    & fmt_stob_index_disp, { 0x82003800 },
+    (PTR) & fmt_stob_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stob $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stob_indirect_index_disp, { 0x82003c00 },
+    (PTR) & fmt_stob_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stos $st_src, $offset */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOS_OFFSET, "stos-offset", "stos",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
+    & fmt_stos_offset, { 0x8a000000 },
+    (PTR) & fmt_stos_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stos $st_src, $offset($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
+    & fmt_stos_indirect_offset, { 0x8a002000 },
+    (PTR) & fmt_stos_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stos $st_src, ($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOS_INDIRECT, "stos-indirect", "stos",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
+    & fmt_stos_indirect, { 0x8a001000 },
+    (PTR) & fmt_stos_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stos $st_src, ($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stos_indirect_index, { 0x8a001c00 },
+    (PTR) & fmt_stos_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stos $st_src, $optdisp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOS_DISP, "stos-disp", "stos",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
+    & fmt_stos_disp, { 0x8a003000 },
+    (PTR) & fmt_stos_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stos $st_src, $optdisp($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
+    & fmt_stos_indirect_disp, { 0x8a003400 },
+    (PTR) & fmt_stos_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stos $st_src, $optdisp[$index*S$scale */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
+    & fmt_stos_index_disp, { 0x8a003800 },
+    (PTR) & fmt_stos_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stos $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stos_indirect_index_disp, { 0x8a003c00 },
+    (PTR) & fmt_stos_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stl $st_src, $offset */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STL_OFFSET, "stl-offset", "stl",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
+    & fmt_stl_offset, { 0x9a000000 },
+    (PTR) & fmt_stl_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stl $st_src, $offset($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
+    & fmt_stl_indirect_offset, { 0x9a002000 },
+    (PTR) & fmt_stl_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stl $st_src, ($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STL_INDIRECT, "stl-indirect", "stl",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
+    & fmt_stl_indirect, { 0x9a001000 },
+    (PTR) & fmt_stl_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stl $st_src, ($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stl_indirect_index, { 0x9a001c00 },
+    (PTR) & fmt_stl_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stl $st_src, $optdisp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STL_DISP, "stl-disp", "stl",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
+    & fmt_stl_disp, { 0x9a003000 },
+    (PTR) & fmt_stl_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stl $st_src, $optdisp($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
+    & fmt_stl_indirect_disp, { 0x9a003400 },
+    (PTR) & fmt_stl_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stl $st_src, $optdisp[$index*S$scale */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
+    & fmt_stl_index_disp, { 0x9a003800 },
+    (PTR) & fmt_stl_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stl $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stl_indirect_index_disp, { 0x9a003c00 },
+    (PTR) & fmt_stl_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stt $st_src, $offset */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STT_OFFSET, "stt-offset", "stt",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
+    & fmt_stt_offset, { 0xa2000000 },
+    (PTR) & fmt_stt_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stt $st_src, $offset($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
+    & fmt_stt_indirect_offset, { 0xa2002000 },
+    (PTR) & fmt_stt_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stt $st_src, ($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STT_INDIRECT, "stt-indirect", "stt",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
+    & fmt_stt_indirect, { 0xa2001000 },
+    (PTR) & fmt_stt_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stt $st_src, ($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stt_indirect_index, { 0xa2001c00 },
+    (PTR) & fmt_stt_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stt $st_src, $optdisp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STT_DISP, "stt-disp", "stt",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
+    & fmt_stt_disp, { 0xa2003000 },
+    (PTR) & fmt_stt_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stt $st_src, $optdisp($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
+    & fmt_stt_indirect_disp, { 0xa2003400 },
+    (PTR) & fmt_stt_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stt $st_src, $optdisp[$index*S$scale */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
+    & fmt_stt_index_disp, { 0xa2003800 },
+    (PTR) & fmt_stt_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stt $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stt_indirect_index_disp, { 0xa2003c00 },
+    (PTR) & fmt_stt_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stq $st_src, $offset */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STQ_OFFSET, "stq-offset", "stq",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
+    & fmt_stq_offset, { 0xb2000000 },
+    (PTR) & fmt_stq_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stq $st_src, $offset($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
+    & fmt_stq_indirect_offset, { 0xb2002000 },
+    (PTR) & fmt_stq_indirect_offset_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stq $st_src, ($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STQ_INDIRECT, "stq-indirect", "stq",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
+    & fmt_stq_indirect, { 0xb2001000 },
+    (PTR) & fmt_stq_indirect_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stq $st_src, ($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stq_indirect_index, { 0xb2001c00 },
+    (PTR) & fmt_stq_indirect_index_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stq $st_src, $optdisp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STQ_DISP, "stq-disp", "stq",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
+    & fmt_stq_disp, { 0xb2003000 },
+    (PTR) & fmt_stq_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stq $st_src, $optdisp($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
+    & fmt_stq_indirect_disp, { 0xb2003400 },
+    (PTR) & fmt_stq_indirect_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stq $st_src, $optdisp[$index*S$scale */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
+    & fmt_stq_index_disp, { 0xb2003800 },
+    (PTR) & fmt_stq_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* stq $st_src, $optdisp($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq",
+    { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_stq_indirect_index_disp, { 0xb2003c00 },
+    (PTR) & fmt_stq_indirect_index_disp_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* cmpobe $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x32000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobe $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_lit, { 0x32002000 },
+    (PTR) & fmt_cmpobe_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobne $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x35000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobne $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_lit, { 0x35002000 },
+    (PTR) & fmt_cmpobe_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobl $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobl_reg, { 0x34000000 },
+    (PTR) & fmt_cmpobl_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobl $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobl_lit, { 0x34002000 },
+    (PTR) & fmt_cmpobl_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpoble $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobl_reg, { 0x36000000 },
+    (PTR) & fmt_cmpobl_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpoble $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobl_lit, { 0x36002000 },
+    (PTR) & fmt_cmpobl_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobg $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobl_reg, { 0x31000000 },
+    (PTR) & fmt_cmpobl_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobg $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobl_lit, { 0x31002000 },
+    (PTR) & fmt_cmpobl_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobge $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobl_reg, { 0x33000000 },
+    (PTR) & fmt_cmpobl_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpobge $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobl_lit, { 0x33002000 },
+    (PTR) & fmt_cmpobl_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibe $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x3a000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibe $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_lit, { 0x3a002000 },
+    (PTR) & fmt_cmpobe_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibne $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x3d000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibne $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_lit, { 0x3d002000 },
+    (PTR) & fmt_cmpobe_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibl $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x3c000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibl $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_lit, { 0x3c002000 },
+    (PTR) & fmt_cmpobe_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpible $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x3e000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpible $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_lit, { 0x3e002000 },
+    (PTR) & fmt_cmpobe_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibg $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x39000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibg $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_lit, { 0x39002000 },
+    (PTR) & fmt_cmpobe_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibge $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x3b000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpibge $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_lit, { 0x3b002000 },
+    (PTR) & fmt_cmpobe_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bbc $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BBC_REG, "bbc-reg", "bbc",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x30000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bbc $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BBC_LIT, "bbc-lit", "bbc",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_bbc_lit, { 0x30002000 },
+    (PTR) & fmt_bbc_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bbs $br_src1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BBS_REG, "bbs-reg", "bbs",
+    { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_cmpobe_reg, { 0x37000000 },
+    (PTR) & fmt_cmpobe_reg_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bbs $br_lit1, $br_src2, $br_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BBS_LIT, "bbs-lit", "bbs",
+    { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
+    & fmt_bbc_lit, { 0x37002000 },
+    (PTR) & fmt_bbc_lit_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* cmpi $src1, $src2 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPI, "cmpi", "cmpi",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
+    & fmt_cmpi, { 0x5a002080 },
+    (PTR) & fmt_cmpi_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* cmpi $lit1, $src2 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPI1, "cmpi1", "cmpi",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
+    & fmt_cmpi1, { 0x5a002880 },
+    (PTR) & fmt_cmpi1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* cmpi $src1, $lit2 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPI2, "cmpi2", "cmpi",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
+    & fmt_cmpi2, { 0x5a003080 },
+    (PTR) & fmt_cmpi2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* cmpi $lit1, $lit2 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPI3, "cmpi3", "cmpi",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
+    & fmt_cmpi3, { 0x5a003880 },
+    (PTR) & fmt_cmpi3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* cmpo $src1, $src2 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPO, "cmpo", "cmpo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
+    & fmt_cmpi, { 0x5a002000 },
+    (PTR) & fmt_cmpi_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* cmpo $lit1, $src2 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPO1, "cmpo1", "cmpo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
+    & fmt_cmpi1, { 0x5a002800 },
+    (PTR) & fmt_cmpi1_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* cmpo $src1, $lit2 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPO2, "cmpo2", "cmpo",
+    { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
+    & fmt_cmpi2, { 0x5a003000 },
+    (PTR) & fmt_cmpi2_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* cmpo $lit1, $lit2 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CMPO3, "cmpo3", "cmpo",
+    { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
+    & fmt_cmpi3, { 0x5a003800 },
+    (PTR) & fmt_cmpi3_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* testno $br_src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_TESTNO_REG, "testno-reg", "testno",
+    { { MNEM, ' ', OP (BR_SRC1), 0 } },
+    & fmt_testno_reg, { 0x20000000 },
+    (PTR) & fmt_testno_reg_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* testg $br_src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_TESTG_REG, "testg-reg", "testg",
+    { { MNEM, ' ', OP (BR_SRC1), 0 } },
+    & fmt_testno_reg, { 0x21000000 },
+    (PTR) & fmt_testno_reg_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* teste $br_src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_TESTE_REG, "teste-reg", "teste",
+    { { MNEM, ' ', OP (BR_SRC1), 0 } },
+    & fmt_testno_reg, { 0x22000000 },
+    (PTR) & fmt_testno_reg_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* testge $br_src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_TESTGE_REG, "testge-reg", "testge",
+    { { MNEM, ' ', OP (BR_SRC1), 0 } },
+    & fmt_testno_reg, { 0x23000000 },
+    (PTR) & fmt_testno_reg_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* testl $br_src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_TESTL_REG, "testl-reg", "testl",
+    { { MNEM, ' ', OP (BR_SRC1), 0 } },
+    & fmt_testno_reg, { 0x24000000 },
+    (PTR) & fmt_testno_reg_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* testne $br_src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_TESTNE_REG, "testne-reg", "testne",
+    { { MNEM, ' ', OP (BR_SRC1), 0 } },
+    & fmt_testno_reg, { 0x25000000 },
+    (PTR) & fmt_testno_reg_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* testle $br_src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_TESTLE_REG, "testle-reg", "testle",
+    { { MNEM, ' ', OP (BR_SRC1), 0 } },
+    & fmt_testno_reg, { 0x26000000 },
+    (PTR) & fmt_testno_reg_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* testo $br_src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_TESTO_REG, "testo-reg", "testo",
+    { { MNEM, ' ', OP (BR_SRC1), 0 } },
+    & fmt_testno_reg, { 0x27000000 },
+    (PTR) & fmt_testno_reg_ops[0],
+    { 0, 0, { 0 } }
+  },
+/* bno $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BNO, "bno", "bno",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_bno, { 0x10000000 },
+    (PTR) & fmt_bno_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bg $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BG, "bg", "bg",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_bno, { 0x11000000 },
+    (PTR) & fmt_bno_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* be $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BE, "be", "be",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_bno, { 0x12000000 },
+    (PTR) & fmt_bno_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bge $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BGE, "bge", "bge",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_bno, { 0x13000000 },
+    (PTR) & fmt_bno_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bl $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BL, "bl", "bl",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_bno, { 0x14000000 },
+    (PTR) & fmt_bno_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bne $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BNE, "bne", "bne",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_bno, { 0x15000000 },
+    (PTR) & fmt_bno_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* ble $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BLE, "ble", "ble",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_bno, { 0x16000000 },
+    (PTR) & fmt_bno_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* bo $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BO, "bo", "bo",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_bno, { 0x17000000 },
+    (PTR) & fmt_bno_ops[0],
+    { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+  },
+/* b $ctrl_disp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_B, "b", "b",
+    { { MNEM, ' ', OP (CTRL_DISP), 0 } },
+    & fmt_b, { 0x8000000 },
+    (PTR) & fmt_b_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* bx $offset($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
+    & fmt_bx_indirect_offset, { 0x84002000 },
+    (PTR) & fmt_bx_indirect_offset_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* bx ($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BX_INDIRECT, "bx-indirect", "bx",
+    { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
+    & fmt_bx_indirect, { 0x84001000 },
+    (PTR) & fmt_bx_indirect_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* bx ($abase)[$index*S$scale] */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx",
+    { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
+    & fmt_bx_indirect_index, { 0x84001c00 },
+    (PTR) & fmt_bx_indirect_index_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* bx $optdisp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BX_DISP, "bx-disp", "bx",
+    { { MNEM, ' ', OP (OPTDISP), 0 } },
+    & fmt_bx_disp, { 0x84003000 },
+    (PTR) & fmt_bx_disp_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* bx $optdisp($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx",
+    { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
+    & fmt_bx_indirect_disp, { 0x84003400 },
+    (PTR) & fmt_bx_indirect_disp_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* callx $optdisp */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CALLX_DISP, "callx-disp", "callx",
+    { { MNEM, ' ', OP (OPTDISP), 0 } },
+    & fmt_callx_disp, { 0x86003000 },
+    (PTR) & fmt_callx_disp_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* callx ($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx",
+    { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
+    & fmt_callx_indirect, { 0x86001000 },
+    (PTR) & fmt_callx_indirect_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* callx $offset($abase) */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx",
+    { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
+    & fmt_callx_indirect_offset, { 0x86002000 },
+    (PTR) & fmt_callx_indirect_offset_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* ret */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_RET, "ret", "ret",
+    { { MNEM, 0 } },
+    & fmt_ret, { 0xa000000 },
+    (PTR) & fmt_ret_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* calls $src1 */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_CALLS, "calls", "calls",
+    { { MNEM, ' ', OP (SRC1), 0 } },
+    & fmt_calls, { 0x66003000 },
+    (PTR) & fmt_calls_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* fmark */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_FMARK, "fmark", "fmark",
+    { { MNEM, 0 } },
+    & fmt_fmark, { 0x66003e00 },
+    (PTR) & fmt_fmark_ops[0],
+    { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+  },
+/* flushreg */
+  {
+    { 1, 1, 1, 1 },
+    I960_INSN_FLUSHREG, "flushreg", "flushreg",
+    { { MNEM, 0 } },
+    & fmt_flushreg, { 0x66003e80 },
+    (PTR) & fmt_flushreg_ops[0],
+    { 0, 0, { 0 } }
+  },
+};
+
+#undef A
+#undef MNEM
+#undef OP
+
+static const CGEN_INSN_TABLE insn_table =
+{
+  & i960_cgen_insn_table_entries[0],
+  sizeof (CGEN_INSN),
+  MAX_INSNS,
+  NULL
+};
+
+/* Formats for ALIAS macro-insns.  */
+
+#define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
+
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities.  */
+
+#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table.  */
+
+static const CGEN_INSN macro_insn_table_entries[] =
+{
+};
+
+#undef A
+#undef MNEM
+#undef OP
+
+static const CGEN_INSN_TABLE macro_insn_table =
+{
+  & macro_insn_table_entries[0],
+  sizeof (CGEN_INSN),
+  (sizeof (macro_insn_table_entries) /
+   sizeof (macro_insn_table_entries[0])),
+  NULL
+};
+
+static void
+init_tables ()
+{
+}
+
+/* Return non-zero if INSN is to be added to the hash table.
+   Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
+
+static int
+asm_hash_insn_p (insn)
+     const CGEN_INSN * insn;
+{
+  return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (insn)
+     const CGEN_INSN * insn;
+{
+  /* If building the hash table and the NO-DIS attribute is present,
+     ignore.  */
+  if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
+    return 0;
+  return CGEN_DIS_HASH_P (insn);
+}
+
+/* The result is the hash value of the insn.
+   Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
+
+static unsigned int
+asm_hash_insn (mnem)
+     const char * mnem;
+{
+  return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the insn's bytes in target order.
+   VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
+   host order.  */
+
+static unsigned int
+dis_hash_insn (buf, value)
+     const char * buf;
+     CGEN_INSN_INT value;
+{
+  return CGEN_DIS_HASH (buf, value);
+}
+
+/* Initialize an opcode table and return a descriptor.
+   It's much like opening a file, and must be the first function called.  */
+
+CGEN_OPCODE_DESC
+i960_cgen_opcode_open (mach, endian)
+     int mach;
+     enum cgen_endian endian;
+{
+  CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
+  static int init_p;
+
+  if (! init_p)
+    {
+      init_tables ();
+      init_p = 1;
+    }
+
+  memset (table, 0, sizeof (*table));
+
+  CGEN_OPCODE_MACH (table) = mach;
+  CGEN_OPCODE_ENDIAN (table) = endian;
+  /* FIXME: for the sparc case we can determine insn-endianness statically.
+     The worry here is where both data and insn endian can be independently
+     chosen, in which case this function will need another argument.
+     Actually, will want to allow for more arguments in the future anyway.  */
+  CGEN_OPCODE_INSN_ENDIAN (table) = endian;
+
+  CGEN_OPCODE_HW_LIST (table) = & i960_cgen_hw_entries[0];
+
+  CGEN_OPCODE_IFLD_TABLE (table) = & i960_cgen_ifld_table[0];
+
+  CGEN_OPCODE_OPERAND_TABLE (table) = & i960_cgen_operand_table[0];
+
+  * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
+
+  * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
+
+  CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
+  CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
+  CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
+
+  CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
+  CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
+  CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
+
+  return (CGEN_OPCODE_DESC) table;
+}
+
+/* Close an opcode table.  */
+
+void
+i960_cgen_opcode_close (desc)
+     CGEN_OPCODE_DESC desc;
+{
+  free (desc);
+}
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they return.
+   TODO: floating point, inlining support, remove cases where result type
+   not appropriate.  */
+
+int
+i960_cgen_get_int_operand (opindex, fields)
+     int opindex;
+     const CGEN_FIELDS * fields;
+{
+  int value;
+
+  switch (opindex)
+    {
+    case I960_OPERAND_SRC1 :
+      value = fields->f_src1;
+      break;
+    case I960_OPERAND_SRC2 :
+      value = fields->f_src2;
+      break;
+    case I960_OPERAND_DST :
+      value = fields->f_srcdst;
+      break;
+    case I960_OPERAND_LIT1 :
+      value = fields->f_src1;
+      break;
+    case I960_OPERAND_LIT2 :
+      value = fields->f_src2;
+      break;
+    case I960_OPERAND_ST_SRC :
+      value = fields->f_srcdst;
+      break;
+    case I960_OPERAND_ABASE :
+      value = fields->f_abase;
+      break;
+    case I960_OPERAND_OFFSET :
+      value = fields->f_offset;
+      break;
+    case I960_OPERAND_SCALE :
+      value = fields->f_scale;
+      break;
+    case I960_OPERAND_INDEX :
+      value = fields->f_index;
+      break;
+    case I960_OPERAND_OPTDISP :
+      value = fields->f_optdisp;
+      break;
+    case I960_OPERAND_BR_SRC1 :
+      value = fields->f_br_src1;
+      break;
+    case I960_OPERAND_BR_SRC2 :
+      value = fields->f_br_src2;
+      break;
+    case I960_OPERAND_BR_DISP :
+      value = fields->f_br_disp;
+      break;
+    case I960_OPERAND_BR_LIT1 :
+      value = fields->f_br_src1;
+      break;
+    case I960_OPERAND_CTRL_DISP :
+      value = fields->f_ctrl_disp;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
+                      opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+bfd_vma
+i960_cgen_get_vma_operand (opindex, fields)
+     int opindex;
+     const CGEN_FIELDS * fields;
+{
+  bfd_vma value;
+
+  switch (opindex)
+    {
+    case I960_OPERAND_SRC1 :
+      value = fields->f_src1;
+      break;
+    case I960_OPERAND_SRC2 :
+      value = fields->f_src2;
+      break;
+    case I960_OPERAND_DST :
+      value = fields->f_srcdst;
+      break;
+    case I960_OPERAND_LIT1 :
+      value = fields->f_src1;
+      break;
+    case I960_OPERAND_LIT2 :
+      value = fields->f_src2;
+      break;
+    case I960_OPERAND_ST_SRC :
+      value = fields->f_srcdst;
+      break;
+    case I960_OPERAND_ABASE :
+      value = fields->f_abase;
+      break;
+    case I960_OPERAND_OFFSET :
+      value = fields->f_offset;
+      break;
+    case I960_OPERAND_SCALE :
+      value = fields->f_scale;
+      break;
+    case I960_OPERAND_INDEX :
+      value = fields->f_index;
+      break;
+    case I960_OPERAND_OPTDISP :
+      value = fields->f_optdisp;
+      break;
+    case I960_OPERAND_BR_SRC1 :
+      value = fields->f_br_src1;
+      break;
+    case I960_OPERAND_BR_SRC2 :
+      value = fields->f_br_src2;
+      break;
+    case I960_OPERAND_BR_DISP :
+      value = fields->f_br_disp;
+      break;
+    case I960_OPERAND_BR_LIT1 :
+      value = fields->f_br_src1;
+      break;
+    case I960_OPERAND_CTRL_DISP :
+      value = fields->f_ctrl_disp;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
+                      opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they accept.
+   TODO: floating point, inlining support, remove cases where argument type
+   not appropriate.  */
+
+void
+i960_cgen_set_int_operand (opindex, fields, value)
+     int opindex;
+     CGEN_FIELDS * fields;
+     int value;
+{
+  switch (opindex)
+    {
+    case I960_OPERAND_SRC1 :
+      fields->f_src1 = value;
+      break;
+    case I960_OPERAND_SRC2 :
+      fields->f_src2 = value;
+      break;
+    case I960_OPERAND_DST :
+      fields->f_srcdst = value;
+      break;
+    case I960_OPERAND_LIT1 :
+      fields->f_src1 = value;
+      break;
+    case I960_OPERAND_LIT2 :
+      fields->f_src2 = value;
+      break;
+    case I960_OPERAND_ST_SRC :
+      fields->f_srcdst = value;
+      break;
+    case I960_OPERAND_ABASE :
+      fields->f_abase = value;
+      break;
+    case I960_OPERAND_OFFSET :
+      fields->f_offset = value;
+      break;
+    case I960_OPERAND_SCALE :
+      fields->f_scale = value;
+      break;
+    case I960_OPERAND_INDEX :
+      fields->f_index = value;
+      break;
+    case I960_OPERAND_OPTDISP :
+      fields->f_optdisp = value;
+      break;
+    case I960_OPERAND_BR_SRC1 :
+      fields->f_br_src1 = value;
+      break;
+    case I960_OPERAND_BR_SRC2 :
+      fields->f_br_src2 = value;
+      break;
+    case I960_OPERAND_BR_DISP :
+      fields->f_br_disp = value;
+      break;
+    case I960_OPERAND_BR_LIT1 :
+      fields->f_br_src1 = value;
+      break;
+    case I960_OPERAND_CTRL_DISP :
+      fields->f_ctrl_disp = value;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+                      opindex);
+      abort ();
+  }
+}
+
+void
+i960_cgen_set_vma_operand (opindex, fields, value)
+     int opindex;
+     CGEN_FIELDS * fields;
+     bfd_vma value;
+{
+  switch (opindex)
+    {
+    case I960_OPERAND_SRC1 :
+      fields->f_src1 = value;
+      break;
+    case I960_OPERAND_SRC2 :
+      fields->f_src2 = value;
+      break;
+    case I960_OPERAND_DST :
+      fields->f_srcdst = value;
+      break;
+    case I960_OPERAND_LIT1 :
+      fields->f_src1 = value;
+      break;
+    case I960_OPERAND_LIT2 :
+      fields->f_src2 = value;
+      break;
+    case I960_OPERAND_ST_SRC :
+      fields->f_srcdst = value;
+      break;
+    case I960_OPERAND_ABASE :
+      fields->f_abase = value;
+      break;
+    case I960_OPERAND_OFFSET :
+      fields->f_offset = value;
+      break;
+    case I960_OPERAND_SCALE :
+      fields->f_scale = value;
+      break;
+    case I960_OPERAND_INDEX :
+      fields->f_index = value;
+      break;
+    case I960_OPERAND_OPTDISP :
+      fields->f_optdisp = value;
+      break;
+    case I960_OPERAND_BR_SRC1 :
+      fields->f_br_src1 = value;
+      break;
+    case I960_OPERAND_BR_SRC2 :
+      fields->f_br_src2 = value;
+      break;
+    case I960_OPERAND_BR_DISP :
+      fields->f_br_disp = value;
+      break;
+    case I960_OPERAND_BR_LIT1 :
+      fields->f_br_src1 = value;
+      break;
+    case I960_OPERAND_CTRL_DISP :
+      fields->f_ctrl_disp = value;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+                      opindex);
+      abort ();
+  }
+}
+

diff --git a/opcodes/i960c-opc.h b/opcodes/i960c-opc.h
new file mode 100644 (file)
index 0000000..7b62ced
--- /dev/null
+++ b/opcodes/i960c-opc.h
@@ -0,0 +1,454 @@
+/* Instruction description for i960.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef I960_OPC_H
+#define I960_OPC_H
+
+#define CGEN_ARCH i960
+
+/* Given symbol S, return i960_cgen_<S>.  */
+#define CGEN_SYM(s) CONCAT3 (i960,_cgen_,s)
+
+/* Selected cpu families.  */
+#define HAVE_CPU_I960BASE
+
+#define CGEN_INSN_LSB0_P 0
+#define CGEN_WORD_BITSIZE 32
+#define CGEN_DEFAULT_INSN_BITSIZE 32
+#define CGEN_BASE_INSN_BITSIZE 32
+#define CGEN_MIN_INSN_BITSIZE 32
+#define CGEN_MAX_INSN_BITSIZE 64
+#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
+#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
+#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
+#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
+#define CGEN_INT_INSN_P 0
+
+/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES.  */
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
+   we can't hash on everything up to the space.  */
+#define CGEN_MNEMONIC_OPERANDS
+/* Maximum number of operands any insn or macro-insn has.  */
+#define CGEN_MAX_INSN_OPERANDS 16
+
+/* Maximum number of fields in an instruction.  */
+#define CGEN_MAX_IFMT_OPERANDS 9
+
+/* Enums.  */
+
+/* Enum declaration for insn opcode enums.  */
+typedef enum insn_opcode {
+  OPCODE_00, OPCODE_01, OPCODE_02, OPCODE_03
+ , OPCODE_04, OPCODE_05, OPCODE_06, OPCODE_07
+ , OPCODE_08, OPCODE_09, OPCODE_0A, OPCODE_0B
+ , OPCODE_0C, OPCODE_0D, OPCODE_0E, OPCODE_0F
+ , OPCODE_10, OPCODE_11, OPCODE_12, OPCODE_13
+ , OPCODE_14, OPCODE_15, OPCODE_16, OPCODE_17
+ , OPCODE_18, OPCODE_19, OPCODE_1A, OPCODE_1B
+ , OPCODE_1C, OPCODE_1D, OPCODE_1E, OPCODE_1F
+ , OPCODE_20, OPCODE_21, OPCODE_22, OPCODE_23
+ , OPCODE_24, OPCODE_25, OPCODE_26, OPCODE_27
+ , OPCODE_28, OPCODE_29, OPCODE_2A, OPCODE_2B
+ , OPCODE_2C, OPCODE_2D, OPCODE_2E, OPCODE_2F
+ , OPCODE_30, OPCODE_31, OPCODE_32, OPCODE_33
+ , OPCODE_34, OPCODE_35, OPCODE_36, OPCODE_37
+ , OPCODE_38, OPCODE_39, OPCODE_3A, OPCODE_3B
+ , OPCODE_3C, OPCODE_3D, OPCODE_3E, OPCODE_3F
+ , OPCODE_40, OPCODE_41, OPCODE_42, OPCODE_43
+ , OPCODE_44, OPCODE_45, OPCODE_46, OPCODE_47
+ , OPCODE_48, OPCODE_49, OPCODE_4A, OPCODE_4B
+ , OPCODE_4C, OPCODE_4D, OPCODE_4E, OPCODE_4F
+ , OPCODE_50, OPCODE_51, OPCODE_52, OPCODE_53
+ , OPCODE_54, OPCODE_55, OPCODE_56, OPCODE_57
+ , OPCODE_58, OPCODE_59, OPCODE_5A, OPCODE_5B
+ , OPCODE_5C, OPCODE_5D, OPCODE_5E, OPCODE_5F
+ , OPCODE_60, OPCODE_61, OPCODE_62, OPCODE_63
+ , OPCODE_64, OPCODE_65, OPCODE_66, OPCODE_67
+ , OPCODE_68, OPCODE_69, OPCODE_6A, OPCODE_6B
+ , OPCODE_6C, OPCODE_6D, OPCODE_6E, OPCODE_6F
+ , OPCODE_70, OPCODE_71, OPCODE_72, OPCODE_73
+ , OPCODE_74, OPCODE_75, OPCODE_76, OPCODE_77
+ , OPCODE_78, OPCODE_79, OPCODE_7A, OPCODE_7B
+ , OPCODE_7C, OPCODE_7D, OPCODE_7E, OPCODE_7F
+ , OPCODE_80, OPCODE_81, OPCODE_82, OPCODE_83
+ , OPCODE_84, OPCODE_85, OPCODE_86, OPCODE_87
+ , OPCODE_88, OPCODE_89, OPCODE_8A, OPCODE_8B
+ , OPCODE_8C, OPCODE_8D, OPCODE_8E, OPCODE_8F
+ , OPCODE_90, OPCODE_91, OPCODE_92, OPCODE_93
+ , OPCODE_94, OPCODE_95, OPCODE_96, OPCODE_97
+ , OPCODE_98, OPCODE_99, OPCODE_9A, OPCODE_9B
+ , OPCODE_9C, OPCODE_9D, OPCODE_9E, OPCODE_9F
+ , OPCODE_A0, OPCODE_A1, OPCODE_A2, OPCODE_A3
+ , OPCODE_A4, OPCODE_A5, OPCODE_A6, OPCODE_A7
+ , OPCODE_A8, OPCODE_A9, OPCODE_AA, OPCODE_AB
+ , OPCODE_AC, OPCODE_AD, OPCODE_AE, OPCODE_AF
+ , OPCODE_B0, OPCODE_B1, OPCODE_B2, OPCODE_B3
+ , OPCODE_B4, OPCODE_B5, OPCODE_B6, OPCODE_B7
+ , OPCODE_B8, OPCODE_B9, OPCODE_BA, OPCODE_BB
+ , OPCODE_BC, OPCODE_BD, OPCODE_BE, OPCODE_BF
+ , OPCODE_C0, OPCODE_C1, OPCODE_C2, OPCODE_C3
+ , OPCODE_C4, OPCODE_C5, OPCODE_C6, OPCODE_C7
+ , OPCODE_C8, OPCODE_C9, OPCODE_CA, OPCODE_CB
+ , OPCODE_CC, OPCODE_CD, OPCODE_CE, OPCODE_CF
+ , OPCODE_D0, OPCODE_D1, OPCODE_D2, OPCODE_D3
+ , OPCODE_D4, OPCODE_D5, OPCODE_D6, OPCODE_D7
+ , OPCODE_D8, OPCODE_D9, OPCODE_DA, OPCODE_DB
+ , OPCODE_DC, OPCODE_DD, OPCODE_DE, OPCODE_DF
+ , OPCODE_E0, OPCODE_E1, OPCODE_E2, OPCODE_E3
+ , OPCODE_E4, OPCODE_E5, OPCODE_E6, OPCODE_E7
+ , OPCODE_E8, OPCODE_E9, OPCODE_EA, OPCODE_EB
+ , OPCODE_EC, OPCODE_ED, OPCODE_EE, OPCODE_EF
+ , OPCODE_F0, OPCODE_F1, OPCODE_F2, OPCODE_F3
+ , OPCODE_F4, OPCODE_F5, OPCODE_F6, OPCODE_F7
+ , OPCODE_F8, OPCODE_F9, OPCODE_FA, OPCODE_FB
+ , OPCODE_FC, OPCODE_FD, OPCODE_FE, OPCODE_FF
+} INSN_OPCODE;
+
+/* Enum declaration for insn opcode2 enums.  */
+typedef enum insn_opcode2 {
+  OPCODE2_0, OPCODE2_1, OPCODE2_2, OPCODE2_3
+ , OPCODE2_4, OPCODE2_5, OPCODE2_6, OPCODE2_7
+ , OPCODE2_8, OPCODE2_9, OPCODE2_A, OPCODE2_B
+ , OPCODE2_C, OPCODE2_D, OPCODE2_E, OPCODE2_F
+} INSN_OPCODE2;
+
+/* Enum declaration for insn m3 enums.  */
+typedef enum insn_m3 {
+  M3_0, M3_1
+} INSN_M3;
+
+/* Enum declaration for insn m3 enums.  */
+typedef enum insn_m2 {
+  M2_0, M2_1
+} INSN_M2;
+
+/* Enum declaration for insn m1 enums.  */
+typedef enum insn_m1 {
+  M1_0, M1_1
+} INSN_M1;
+
+/* Enum declaration for insn zero enums.  */
+typedef enum insn_zero {
+  ZERO_0
+} INSN_ZERO;
+
+/* Enum declaration for insn mode a enums.  */
+typedef enum insn_modea {
+  MODEA_OFFSET, MODEA_INDIRECT_OFFSET
+} INSN_MODEA;
+
+/* Enum declaration for insn zero a enums.  */
+typedef enum insn_zeroa {
+  ZEROA_0
+} INSN_ZEROA;
+
+/* Enum declaration for insn mode b enums.  */
+typedef enum insn_modeb {
+  MODEB_ILL0, MODEB_ILL1, MODEB_ILL2, MODEB_ILL3
+ , MODEB_INDIRECT, MODEB_IP_DISP, MODEB_RES6, MODEB_INDIRECT_INDEX
+ , MODEB_ILL8, MODEB_ILL9, MODEB_ILL10, MODEB_ILL11
+ , MODEB_DISP, MODEB_INDIRECT_DISP, MODEB_INDEX_DISP, MODEB_INDIRECT_INDEX_DISP
+} INSN_MODEB;
+
+/* Enum declaration for insn zero b enums.  */
+typedef enum insn_zerob {
+  ZEROB_0
+} INSN_ZEROB;
+
+/* Enum declaration for insn branch m1 enums.  */
+typedef enum insn_br_m1 {
+  BR_M1_0, BR_M1_1
+} INSN_BR_M1;
+
+/* Enum declaration for insn branch zero enums.  */
+typedef enum insn_br_zero {
+  BR_ZERO_0
+} INSN_BR_ZERO;
+
+/* Enum declaration for insn ctrl zero enums.  */
+typedef enum insn_ctrl_zero {
+  CTRL_ZERO_0
+} INSN_CTRL_ZERO;
+
+/* Enum declaration for general registers.  */
+typedef enum h_gr {
+  H_GR_FP = 31, H_GR_SP = 1, H_GR_R0 = 0, H_GR_R1 = 1
+ , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
+ , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
+ , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
+ , H_GR_R14 = 14, H_GR_R15 = 15, H_GR_G0 = 16, H_GR_G1 = 17
+ , H_GR_G2 = 18, H_GR_G3 = 19, H_GR_G4 = 20, H_GR_G5 = 21
+ , H_GR_G6 = 22, H_GR_G7 = 23, H_GR_G8 = 24, H_GR_G9 = 25
+ , H_GR_G10 = 26, H_GR_G11 = 27, H_GR_G12 = 28, H_GR_G13 = 29
+ , H_GR_G14 = 30, H_GR_G15 = 31
+} H_GR;
+
+/* Enum declaration for condition code.  */
+typedef enum h_cc {
+  H_CC_CC
+} H_CC;
+
+/* Enum declaration for i960 operand types.  */
+typedef enum cgen_operand_type {
+  I960_OPERAND_PC, I960_OPERAND_SRC1, I960_OPERAND_SRC2, I960_OPERAND_DST
+ , I960_OPERAND_LIT1, I960_OPERAND_LIT2, I960_OPERAND_ST_SRC, I960_OPERAND_ABASE
+ , I960_OPERAND_OFFSET, I960_OPERAND_SCALE, I960_OPERAND_INDEX, I960_OPERAND_OPTDISP
+ , I960_OPERAND_BR_SRC1, I960_OPERAND_BR_SRC2, I960_OPERAND_BR_DISP, I960_OPERAND_BR_LIT1
+ , I960_OPERAND_CTRL_DISP, I960_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Non-boolean attributes.  */
+
+/* Enum declaration for machine type selection.  */
+typedef enum mach_attr {
+  MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX
+} MACH_ATTR;
+
+/* Number of architecture variants.  */
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Number of operands types.  */
+#define MAX_OPERANDS ((int) I960_OPERAND_MAX)
+
+/* Maximum number of operands referenced by any insn.  */
+#define MAX_OPERAND_INSTANCES 54
+
+/* Hardware, operand and instruction attribute indices.  */
+
+/* Enum declaration for cgen_hw attrs.  */
+typedef enum cgen_hw_attr {
+  CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw.  */
+#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
+
+/* Hardware, operand and instruction attribute indices.  */
+
+/* Enum declaration for cgen_ifld attrs.  */
+typedef enum cgen_ifld_attr {
+  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_RELOC, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_UNSIGNED, CGEN_IFLD_VIRTUAL
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld.  */
+#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_ABS_ADDR)
+
+/* Enum declaration for i960 ifield types.  */
+typedef enum ifield_type {
+  I960_F_NIL, I960_F_OPCODE, I960_F_SRCDST, I960_F_SRC2
+ , I960_F_M3, I960_F_M2, I960_F_M1, I960_F_OPCODE2
+ , I960_F_ZERO, I960_F_SRC1, I960_F_ABASE, I960_F_MODEA
+ , I960_F_ZEROA, I960_F_OFFSET, I960_F_MODEB, I960_F_SCALE
+ , I960_F_ZEROB, I960_F_INDEX, I960_F_OPTDISP, I960_F_BR_SRC1
+ , I960_F_BR_SRC2, I960_F_BR_M1, I960_F_BR_DISP, I960_F_BR_ZERO
+ , I960_F_CTRL_DISP, I960_F_CTRL_ZERO, I960_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) I960_F_MAX)
+
+/* Enum declaration for cgen_operand attrs.  */
+typedef enum cgen_operand_attr {
+  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX
+ , CGEN_OPERAND_RELOC, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand.  */
+#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
+
+/* Enum declaration for cgen_insn attrs.  */
+typedef enum cgen_insn_attr {
+  CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_NO_DIS
+ , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI, CGEN_INSN_UNCOND_CTI
+ , CGEN_INSN_VIRTUAL
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn.  */
+#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
+
+/* Enum declaration for i960 instruction types.  */
+typedef enum cgen_insn_type {
+  I960_INSN_INVALID, I960_INSN_MULO, I960_INSN_MULO1, I960_INSN_MULO2
+ , I960_INSN_MULO3, I960_INSN_REMO, I960_INSN_REMO1, I960_INSN_REMO2
+ , I960_INSN_REMO3, I960_INSN_DIVO, I960_INSN_DIVO1, I960_INSN_DIVO2
+ , I960_INSN_DIVO3, I960_INSN_REMI, I960_INSN_REMI1, I960_INSN_REMI2
+ , I960_INSN_REMI3, I960_INSN_DIVI, I960_INSN_DIVI1, I960_INSN_DIVI2
+ , I960_INSN_DIVI3, I960_INSN_ADDO, I960_INSN_ADDO1, I960_INSN_ADDO2
+ , I960_INSN_ADDO3, I960_INSN_SUBO, I960_INSN_SUBO1, I960_INSN_SUBO2
+ , I960_INSN_SUBO3, I960_INSN_NOTBIT, I960_INSN_NOTBIT1, I960_INSN_NOTBIT2
+ , I960_INSN_NOTBIT3, I960_INSN_AND, I960_INSN_AND1, I960_INSN_AND2
+ , I960_INSN_AND3, I960_INSN_ANDNOT, I960_INSN_ANDNOT1, I960_INSN_ANDNOT2
+ , I960_INSN_ANDNOT3, I960_INSN_SETBIT, I960_INSN_SETBIT1, I960_INSN_SETBIT2
+ , I960_INSN_SETBIT3, I960_INSN_NOTAND, I960_INSN_NOTAND1, I960_INSN_NOTAND2
+ , I960_INSN_NOTAND3, I960_INSN_XOR, I960_INSN_XOR1, I960_INSN_XOR2
+ , I960_INSN_XOR3, I960_INSN_OR, I960_INSN_OR1, I960_INSN_OR2
+ , I960_INSN_OR3, I960_INSN_NOR, I960_INSN_NOR1, I960_INSN_NOR2
+ , I960_INSN_NOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2
+ , I960_INSN_NOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2
+ , I960_INSN_CLRBIT3, I960_INSN_SHLO, I960_INSN_SHLO1, I960_INSN_SHLO2
+ , I960_INSN_SHLO3, I960_INSN_SHRO, I960_INSN_SHRO1, I960_INSN_SHRO2
+ , I960_INSN_SHRO3, I960_INSN_SHLI, I960_INSN_SHLI1, I960_INSN_SHLI2
+ , I960_INSN_SHLI3, I960_INSN_SHRI, I960_INSN_SHRI1, I960_INSN_SHRI2
+ , I960_INSN_SHRI3, I960_INSN_EMUL, I960_INSN_EMUL1, I960_INSN_EMUL2
+ , I960_INSN_EMUL3, I960_INSN_MOV, I960_INSN_MOV1, I960_INSN_MOVL
+ , I960_INSN_MOVL1, I960_INSN_MOVT, I960_INSN_MOVT1, I960_INSN_MOVQ
+ , I960_INSN_MOVQ1, I960_INSN_MODPC, I960_INSN_MODAC, I960_INSN_LDA_OFFSET
+ , I960_INSN_LDA_INDIRECT_OFFSET, I960_INSN_LDA_INDIRECT, I960_INSN_LDA_INDIRECT_INDEX, I960_INSN_LDA_DISP
+ , I960_INSN_LDA_INDIRECT_DISP, I960_INSN_LDA_INDEX_DISP, I960_INSN_LDA_INDIRECT_INDEX_DISP, I960_INSN_LD_OFFSET
+ , I960_INSN_LD_INDIRECT_OFFSET, I960_INSN_LD_INDIRECT, I960_INSN_LD_INDIRECT_INDEX, I960_INSN_LD_DISP
+ , I960_INSN_LD_INDIRECT_DISP, I960_INSN_LD_INDEX_DISP, I960_INSN_LD_INDIRECT_INDEX_DISP, I960_INSN_LDOB_OFFSET
+ , I960_INSN_LDOB_INDIRECT_OFFSET, I960_INSN_LDOB_INDIRECT, I960_INSN_LDOB_INDIRECT_INDEX, I960_INSN_LDOB_DISP
+ , I960_INSN_LDOB_INDIRECT_DISP, I960_INSN_LDOB_INDEX_DISP, I960_INSN_LDOB_INDIRECT_INDEX_DISP, I960_INSN_LDOS_OFFSET
+ , I960_INSN_LDOS_INDIRECT_OFFSET, I960_INSN_LDOS_INDIRECT, I960_INSN_LDOS_INDIRECT_INDEX, I960_INSN_LDOS_DISP
+ , I960_INSN_LDOS_INDIRECT_DISP, I960_INSN_LDOS_INDEX_DISP, I960_INSN_LDOS_INDIRECT_INDEX_DISP, I960_INSN_LDIB_OFFSET
+ , I960_INSN_LDIB_INDIRECT_OFFSET, I960_INSN_LDIB_INDIRECT, I960_INSN_LDIB_INDIRECT_INDEX, I960_INSN_LDIB_DISP
+ , I960_INSN_LDIB_INDIRECT_DISP, I960_INSN_LDIB_INDEX_DISP, I960_INSN_LDIB_INDIRECT_INDEX_DISP, I960_INSN_LDIS_OFFSET
+ , I960_INSN_LDIS_INDIRECT_OFFSET, I960_INSN_LDIS_INDIRECT, I960_INSN_LDIS_INDIRECT_INDEX, I960_INSN_LDIS_DISP
+ , I960_INSN_LDIS_INDIRECT_DISP, I960_INSN_LDIS_INDEX_DISP, I960_INSN_LDIS_INDIRECT_INDEX_DISP, I960_INSN_LDL_OFFSET
+ , I960_INSN_LDL_INDIRECT_OFFSET, I960_INSN_LDL_INDIRECT, I960_INSN_LDL_INDIRECT_INDEX, I960_INSN_LDL_DISP
+ , I960_INSN_LDL_INDIRECT_DISP, I960_INSN_LDL_INDEX_DISP, I960_INSN_LDL_INDIRECT_INDEX_DISP, I960_INSN_LDT_OFFSET
+ , I960_INSN_LDT_INDIRECT_OFFSET, I960_INSN_LDT_INDIRECT, I960_INSN_LDT_INDIRECT_INDEX, I960_INSN_LDT_DISP
+ , I960_INSN_LDT_INDIRECT_DISP, I960_INSN_LDT_INDEX_DISP, I960_INSN_LDT_INDIRECT_INDEX_DISP, I960_INSN_LDQ_OFFSET
+ , I960_INSN_LDQ_INDIRECT_OFFSET, I960_INSN_LDQ_INDIRECT, I960_INSN_LDQ_INDIRECT_INDEX, I960_INSN_LDQ_DISP
+ , I960_INSN_LDQ_INDIRECT_DISP, I960_INSN_LDQ_INDEX_DISP, I960_INSN_LDQ_INDIRECT_INDEX_DISP, I960_INSN_ST_OFFSET
+ , I960_INSN_ST_INDIRECT_OFFSET, I960_INSN_ST_INDIRECT, I960_INSN_ST_INDIRECT_INDEX, I960_INSN_ST_DISP
+ , I960_INSN_ST_INDIRECT_DISP, I960_INSN_ST_INDEX_DISP, I960_INSN_ST_INDIRECT_INDEX_DISP, I960_INSN_STOB_OFFSET
+ , I960_INSN_STOB_INDIRECT_OFFSET, I960_INSN_STOB_INDIRECT, I960_INSN_STOB_INDIRECT_INDEX, I960_INSN_STOB_DISP
+ , I960_INSN_STOB_INDIRECT_DISP, I960_INSN_STOB_INDEX_DISP, I960_INSN_STOB_INDIRECT_INDEX_DISP, I960_INSN_STOS_OFFSET
+ , I960_INSN_STOS_INDIRECT_OFFSET, I960_INSN_STOS_INDIRECT, I960_INSN_STOS_INDIRECT_INDEX, I960_INSN_STOS_DISP
+ , I960_INSN_STOS_INDIRECT_DISP, I960_INSN_STOS_INDEX_DISP, I960_INSN_STOS_INDIRECT_INDEX_DISP, I960_INSN_STL_OFFSET
+ , I960_INSN_STL_INDIRECT_OFFSET, I960_INSN_STL_INDIRECT, I960_INSN_STL_INDIRECT_INDEX, I960_INSN_STL_DISP
+ , I960_INSN_STL_INDIRECT_DISP, I960_INSN_STL_INDEX_DISP, I960_INSN_STL_INDIRECT_INDEX_DISP, I960_INSN_STT_OFFSET
+ , I960_INSN_STT_INDIRECT_OFFSET, I960_INSN_STT_INDIRECT, I960_INSN_STT_INDIRECT_INDEX, I960_INSN_STT_DISP
+ , I960_INSN_STT_INDIRECT_DISP, I960_INSN_STT_INDEX_DISP, I960_INSN_STT_INDIRECT_INDEX_DISP, I960_INSN_STQ_OFFSET
+ , I960_INSN_STQ_INDIRECT_OFFSET, I960_INSN_STQ_INDIRECT, I960_INSN_STQ_INDIRECT_INDEX, I960_INSN_STQ_DISP
+ , I960_INSN_STQ_INDIRECT_DISP, I960_INSN_STQ_INDEX_DISP, I960_INSN_STQ_INDIRECT_INDEX_DISP, I960_INSN_CMPOBE_REG
+ , I960_INSN_CMPOBE_LIT, I960_INSN_CMPOBNE_REG, I960_INSN_CMPOBNE_LIT, I960_INSN_CMPOBL_REG
+ , I960_INSN_CMPOBL_LIT, I960_INSN_CMPOBLE_REG, I960_INSN_CMPOBLE_LIT, I960_INSN_CMPOBG_REG
+ , I960_INSN_CMPOBG_LIT, I960_INSN_CMPOBGE_REG, I960_INSN_CMPOBGE_LIT, I960_INSN_CMPIBE_REG
+ , I960_INSN_CMPIBE_LIT, I960_INSN_CMPIBNE_REG, I960_INSN_CMPIBNE_LIT, I960_INSN_CMPIBL_REG
+ , I960_INSN_CMPIBL_LIT, I960_INSN_CMPIBLE_REG, I960_INSN_CMPIBLE_LIT, I960_INSN_CMPIBG_REG
+ , I960_INSN_CMPIBG_LIT, I960_INSN_CMPIBGE_REG, I960_INSN_CMPIBGE_LIT, I960_INSN_BBC_REG
+ , I960_INSN_BBC_LIT, I960_INSN_BBS_REG, I960_INSN_BBS_LIT, I960_INSN_CMPI
+ , I960_INSN_CMPI1, I960_INSN_CMPI2, I960_INSN_CMPI3, I960_INSN_CMPO
+ , I960_INSN_CMPO1, I960_INSN_CMPO2, I960_INSN_CMPO3, I960_INSN_TESTNO_REG
+ , I960_INSN_TESTG_REG, I960_INSN_TESTE_REG, I960_INSN_TESTGE_REG, I960_INSN_TESTL_REG
+ , I960_INSN_TESTNE_REG, I960_INSN_TESTLE_REG, I960_INSN_TESTO_REG, I960_INSN_BNO
+ , I960_INSN_BG, I960_INSN_BE, I960_INSN_BGE, I960_INSN_BL
+ , I960_INSN_BNE, I960_INSN_BLE, I960_INSN_BO, I960_INSN_B
+ , I960_INSN_BX_INDIRECT_OFFSET, I960_INSN_BX_INDIRECT, I960_INSN_BX_INDIRECT_INDEX, I960_INSN_BX_DISP
+ , I960_INSN_BX_INDIRECT_DISP, I960_INSN_CALLX_DISP, I960_INSN_CALLX_INDIRECT, I960_INSN_CALLX_INDIRECT_OFFSET
+ , I960_INSN_RET, I960_INSN_CALLS, I960_INSN_FMARK, I960_INSN_FLUSHREG
+ , I960_INSN_MAX
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder.  */
+#define CGEN_INSN_INVALID I960_INSN_INVALID
+/* Total number of insns in table.  */
+#define MAX_INSNS ((int) I960_INSN_MAX)
+
+/* cgen.h uses things we just defined.  */
+#include "opcode/cgen.h"
+
+/* This struct records data prior to insertion or after extraction.  */
+struct cgen_fields 
+{
+  long f_nil;
+  long f_opcode;
+  long f_srcdst;
+  long f_src2;
+  long f_m3;
+  long f_m2;
+  long f_m1;
+  long f_opcode2;
+  long f_zero;
+  long f_src1;
+  long f_abase;
+  long f_modea;
+  long f_zeroa;
+  long f_offset;
+  long f_modeb;
+  long f_scale;
+  long f_zerob;
+  long f_index;
+  long f_optdisp;
+  long f_br_src1;
+  long f_br_src2;
+  long f_br_m1;
+  long f_br_disp;
+  long f_br_zero;
+  long f_ctrl_disp;
+  long f_ctrl_zero;
+  int length;
+};
+
+/* Attributes.  */
+extern const CGEN_ATTR_TABLE i960_cgen_hw_attr_table[];
+extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
+
+/* Enum declaration for i960 hardware types.  */
+typedef enum hw_type {
+  HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
+ , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC
+ , HW_MAX
+} HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Hardware decls.  */
+
+extern CGEN_KEYWORD i960_cgen_opval_h_gr;
+extern CGEN_KEYWORD i960_cgen_opval_h_cc;
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+/* -- opc.h */
+
+#undef CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 256
+#undef CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value) ((unsigned char *) (buffer))[3]
+
+/* ??? Until cgen disassembler complete and functioning well, redirect back
+   to old disassembler.  */
+#define CGEN_PRINT_INSN(od, pc, info) print_insn_i960_orig (pc, info)
+
+/* -- */
+
+
+#endif /* I960_OPC_H */