drm/radeon/kms: add some missing semaphore init
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 20 Jan 2012 19:47:43 +0000 (14:47 -0500)
committerDave Airlie <airlied@redhat.com>
Mon, 23 Jan 2012 11:03:26 +0000 (11:03 +0000)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/evergreend.h
drivers/gpu/drm/radeon/ni.c
drivers/gpu/drm/radeon/nid.h

index 636660fca8c246f9e65205fcae1ca379e180131c..ae09fe82afbc76702504a0ac74eda5eed7e05917 100644 (file)
@@ -1455,6 +1455,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
 #endif
        WREG32(CP_RB_CNTL, tmp);
        WREG32(CP_SEM_WAIT_TIMER, 0x0);
+       WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
 
        /* Set the write pointer delay */
        WREG32(CP_RB_WPTR_DELAY, 0);
index b502216d42afdc4638362bceec578adfdf998720..74713d42df296d32db965c7398d47bc8edc566c4 100644 (file)
 #define        CP_RB_WPTR_ADDR_HI                              0xC11C
 #define        CP_RB_WPTR_DELAY                                0x8704
 #define        CP_SEM_WAIT_TIMER                               0x85BC
+#define        CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
 #define        CP_DEBUG                                        0xC1FC
 
 
index 32113729540069f22ce31ffa18e23c7ccc290159..db09065e68fd60ee488da280199a382c5b19efb8 100644 (file)
@@ -1219,6 +1219,7 @@ int cayman_cp_resume(struct radeon_device *rdev)
        RREG32(GRBM_SOFT_RESET);
 
        WREG32(CP_SEM_WAIT_TIMER, 0x0);
+       WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
 
        /* Set the write pointer delay */
        WREG32(CP_RB_WPTR_DELAY, 0);
index f9df2a645e79caeeab62396e71222b89026e6f8e..9a7f3b6e02de38acc1655b9e74fae3d5dac91448 100644 (file)
 #define        SCRATCH_UMSK                                    0x8540
 #define        SCRATCH_ADDR                                    0x8544
 #define        CP_SEM_WAIT_TIMER                               0x85BC
+#define        CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
 #define        CP_COHER_CNTL2                                  0x85E8
 #define CP_ME_CNTL                                     0x86D8
 #define                CP_ME_HALT                                      (1 << 28)
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