+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
+ (arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
+ (arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
+ shared with a non M profile architecture.
+ (do_rn): New function.
+ (known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
+ than arm_ext_v8m.
+ (v7m_psrs): Add ARMv8-M security extensions new special registers.
+ (insns): Add ARMv8-M Security Extensions instructions.
+ (aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
+ arm_ext_v8m_m to decide the profile and the Thumb ISA.
+ * testsuite/gas/arm/archv8m-cmse.s: New file.
+ * testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
+ * testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
+ * testsuite/gas/arm/any-cmse.d: Likewise.
+ * testsuite/gas/arm/any-cmse-main.d: Likewise.
+ * testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
+ * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
+ * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
+ * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
+ * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
+
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
static const arm_feature_set arm_ext_m =
- ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, ARM_EXT2_V8M);
+ ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M,
+ ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
+static const arm_feature_set arm_ext_v8m_main =
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
+/* Instructions in ARMv8-M only found in M profile architectures. */
+static const arm_feature_set arm_ext_v8m_m_only =
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
static const arm_feature_set arm_ext_v6t2_v8m =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
/* Instructions shared between ARMv8-A and ARMv8-M. */
inst.instruction |= inst.operands[0].reg << 12;
}
+static void
+do_rn (void)
+{
+ inst.instruction |= inst.operands[0].reg << 16;
+}
+
static void
do_rd_rm (void)
{
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
return TRUE;
- /* Wide-only instruction added to ARMv8-M. */
- if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m)
+ /* Wide-only instruction added to ARMv8-M Baseline. */
+ if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
{"ipsr", 5 }, {"IPSR", 5 },
{"epsr", 6 }, {"EPSR", 6 },
{"iepsr", 7 }, {"IEPSR", 7 },
- {"msp", 8 }, {"MSP", 8 },
- {"psp", 9 }, {"PSP", 9 },
+ {"msp", 8 }, {"MSP", 8 }, {"msp_s", 8 }, {"MSP_S", 8 },
+ {"psp", 9 }, {"PSP", 9 }, {"psp_s", 9 }, {"PSP_S", 9 },
{"primask", 16}, {"PRIMASK", 16},
{"basepri", 17}, {"BASEPRI", 17},
{"basepri_max", 18}, {"BASEPRI_MAX", 18},
{"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
{"faultmask", 19}, {"FAULTMASK", 19},
- {"control", 20}, {"CONTROL", 20}
+ {"control", 20}, {"CONTROL", 20},
+ {"msp_ns", 0x88}, {"MSP_NS", 0x88},
+ {"psp_ns", 0x89}, {"PSP_NS", 0x89}
};
/* Table of all shift-in-operand names. */
cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
+ /* ARMv8-M instructions. */
#undef ARM_VARIANT
#define ARM_VARIANT NULL
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_v8m
+ TUE("sg", 0, e97fe97f, 0, (), 0, noargs),
+ TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
+ TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
+ TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
+ TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
+
+ /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
+ instructions behave as nop if no VFP is present. */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_v8m_main
+ TUEc("vlldm", 0, ec300a00, 1, (RRnpc), rn),
+ TUEc("vlstm", 0, ec200a00, 1, (RRnpc), rn),
};
#undef ARM_VARIANT
#undef THUMB_VARIANT
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
|| ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
|| (ARM_CPU_HAS_FEATURE (flags, arm_ext_atomics)
- && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)))
+ && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)))
profile = 'A';
else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
profile = 'R';
int thumb_isa_use;
if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
- && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
+ && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
thumb_isa_use = 3;
else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
thumb_isa_use = 2;
--- /dev/null
+#name: attributes for 'any' CPU with ARMv8-M Mainline Security Extensions instructions
+#source: archv8m-cmse-main.s
+#as:
+#readelf: -A
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_arch: v8-M.mainline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
--- /dev/null
+#name: attributes for 'any' CPU with ARMv8-M Security Extensions instructions
+#source: archv8m-cmse.s
+#as:
+#readelf: -A
+# target: *-*-*eabi* *-*-nacl*
+
+Attribute Section: aeabi
+File Attributes
+ Tag_CPU_arch: v8-M.baseline
+ Tag_CPU_arch_profile: Microcontroller
+ Tag_THUMB_ISA_use: Yes
--- /dev/null
+#name: ARMv8-M Baseline Security Extensions instructions
+#source: archv8m-cmse.s
+#as: -march=armv8-m.base
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+.* <[^>]*> e97f e97f sg
+0+.* <[^>]*> 47a4 blxns r4
+0+.* <[^>]*> 47cc blxns r9
+0+.* <[^>]*> 4724 bxns r4
+0+.* <[^>]*> 474c bxns r9
+0+.* <[^>]*> e841 f080 tta r0, r1
+0+.* <[^>]*> e849 f880 tta r8, r9
+0+.* <[^>]*> e841 f0c0 ttat r0, r1
+0+.* <[^>]*> e849 f8c0 ttat r8, r9
--- /dev/null
+#name: ARMv8-M Mainline Security Extensions instructions (1)
+#source: archv8m-cmse.s
+#as: -march=armv8-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+.* <[^>]*> e97f e97f sg
+0+.* <[^>]*> 47a4 blxns r4
+0+.* <[^>]*> 47cc blxns r9
+0+.* <[^>]*> 4724 bxns r4
+0+.* <[^>]*> 474c bxns r9
+0+.* <[^>]*> e841 f080 tta r0, r1
+0+.* <[^>]*> e849 f880 tta r8, r9
+0+.* <[^>]*> e841 f0c0 ttat r0, r1
+0+.* <[^>]*> e849 f8c0 ttat r8, r9
--- /dev/null
+#name: ARMv8-M Mainline Security Extensions instructions (2)
+#source: archv8m-cmse-main.s
+#as: -march=armv8-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+.* <[^>]*> ec31 0a00 vlldm r1
+0+.* <[^>]*> ec22 0a00 vlstm r2
--- /dev/null
+.thumb
+.syntax unified
+
+vlldm r1
+vlstm r2
--- /dev/null
+#name: ARMv8-M Baseline Security Extensions MSR/MRS instructions
+#source: archv8m-cmse-msr.s
+#as: -march=armv8-m.base
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+.* <[^>]*> f380 8808 msr MSP, r0
+0+.* <[^>]*> f380 8808 msr MSP, r0
+0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+0+.* <[^>]*> f380 8809 msr PSP, r0
+0+.* <[^>]*> f380 8809 msr PSP, r0
+0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+0+.* <[^>]*> f380 8808 msr MSP, r0
+0+.* <[^>]*> f380 8808 msr MSP, r0
+0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+0+.* <[^>]*> f380 8809 msr PSP, r0
+0+.* <[^>]*> f380 8809 msr PSP, r0
+0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
+0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
--- /dev/null
+#name: ARMv8-M Mainline Security Extensions MSR/MRS instructions
+#source: archv8m-cmse-msr.s
+#as: -march=armv8-m.main
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+.* <[^>]*> f380 8808 msr MSP, r0
+0+.* <[^>]*> f380 8808 msr MSP, r0
+0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+0+.* <[^>]*> f380 8809 msr PSP, r0
+0+.* <[^>]*> f380 8809 msr PSP, r0
+0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+0+.* <[^>]*> f380 8808 msr MSP, r0
+0+.* <[^>]*> f380 8808 msr MSP, r0
+0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+0+.* <[^>]*> f380 8809 msr PSP, r0
+0+.* <[^>]*> f380 8809 msr PSP, r0
+0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
+0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
--- /dev/null
+msr MSP, r0
+msr MSP_S, r0
+msr MSP_NS, r0
+msr PSP, r0
+msr PSP_S, r0
+msr PSP_NS, r0
+msr msp, r0
+msr msp_s, r0
+msr msp_ns, r0
+msr psp, r0
+msr psp_s, r0
+msr psp_ns, r0
+mrs r0, MSP
+mrs r0, MSP_S
+mrs r0, MSP_NS
+mrs r0, PSP
+mrs r0, PSP_S
+mrs r0, PSP_NS
+mrs r0, msp
+mrs r0, msp_s
+mrs r0, msp_ns
+mrs r0, psp
+mrs r0, psp_s
+mrs r0, psp_ns
--- /dev/null
+.thumb
+.syntax unified
+
+sg
+blxns r4
+blxns r9
+bxns r4
+bxns r9
+tta r0, r1
+tta r8, r9
+ttat r0, r1
+ttat r8, r9
+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
+ (ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
+ (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
+ for the high core bits.
+
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (ARC_SYNTAX_1OP): Declare
#define ARM_EXT2_ATOMICS 0x00000008 /* ARMv8 atomics. */
#define ARM_EXT2_V6T2_V8M 0x00000010 /* V8M Baseline from V6T2. */
#define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */
+#define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
#define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV)
#define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M
#define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M)
+#define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN)
/* Processors with specific extensions in the co-processor space. */
#define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
#define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \
CRC_EXT_ARMV8)
#define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)
-#define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, ARM_AEXT2_V8M)
+#define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \
+ ARM_AEXT2_V8M_MAIN)
/* Some useful combinations: */
#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0)
+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
+ Mainline Security Extensions instructions.
+ (thumb_opcodes): Add entries for narrow ARMv8-M Security
+ Extensions instructions.
+ (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
+ instructions.
+ (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
+ special registers.
+
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
+ /* ARMv8-M Mainline Security Extensions instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
+
/* Register load/store. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
{
/* Thumb instructions. */
+ /* ARMv8-M Security Extensions instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
+
/* ARM V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
- /* V8-M instructions. */
+ /* ARMv8-M and ARMv8-M Security Extensions instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+ 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+ 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
/* ARM V8.2 RAS extension instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
case 18: return "BASEPRI_MAX";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
+ case 0x88: return "MSP_NS";
+ case 0x89: return "PSP_NS";
default: return "<unknown>";
}
}
projects / deliverable / binutils-gdb.git / commitdiff
