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usb: dwc3: core: define bit 10 of GCTL register
author
Felipe Balbi
<balbi@ti.com>
Tue, 25 Feb 2014 20:08:51 +0000
(14:08 -0600)
committer
Felipe Balbi
<balbi@ti.com>
Wed, 5 Mar 2014 15:44:49 +0000
(09:44 -0600)
This bit is necessary for implemeting workaround
for known issue with some revisions of this core.
Signed-off-by: Felipe Balbi <balbi@ti.com>
drivers/usb/dwc3/core.h
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diff --git
a/drivers/usb/dwc3/core.h
b/drivers/usb/dwc3/core.h
index 69c4583933d1eb512d9207e7bd88e1d4fd7f70b7..f2693b63b710ff77fffe806f7752093fb2ea5547 100644
(file)
--- a/
drivers/usb/dwc3/core.h
+++ b/
drivers/usb/dwc3/core.h
@@
-157,6
+157,7
@@
#define DWC3_GCTL_PRTCAP_OTG 3
#define DWC3_GCTL_CORESOFTRESET (1 << 11)
+#define DWC3_GCTL_SOFITPSYNC (1 << 10)
#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
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