+2016-12-13 Jiong Wang <jiong.wang@arm.com>
+
+ * gas/testsuite/gas/aarch64/addsub.d: Support ILP32 mode.
+ * gas/testsuite/gas/aarch64/advsimd-across.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsimd-fp16.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsimd-misc.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsisd-copy.d: Likewise.
+ * gas/testsuite/gas/aarch64/advsisd-misc.d: Likewise.
+ * gas/testsuite/gas/aarch64/alias.d: Likewise.
+ * gas/testsuite/gas/aarch64/armv8-ras-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/b_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/beq_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/bitfield-dump: Likewise.
+ * gas/testsuite/gas/aarch64/bitfield-no-aliases.d: Likewise.
+ * gas/testsuite/gas/aarch64/codealign.d: Likewise.
+ * gas/testsuite/gas/aarch64/codealign_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/crc32-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/crc32.d: Likewise.
+ * gas/testsuite/gas/aarch64/crypto-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/crypto.d: Likewise.
+ * gas/testsuite/gas/aarch64/dwarf.d: Likewise.
+ * gas/testsuite/gas/aarch64/float-fp16.d: Likewise.
+ * gas/testsuite/gas/aarch64/floatdp2.d: Likewise.
+ * gas/testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
+ * gas/testsuite/gas/aarch64/fp-const0-parse.d: Likewise.
+ * gas/testsuite/gas/aarch64/fp_cvt_int.d: Likewise.
+ * gas/testsuite/gas/aarch64/fpmov.d: Likewise.
+ * gas/testsuite/gas/aarch64/inst-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldr_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-exclusive.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-pair.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-uns-imm.d: Likewise.
+ * gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.d: Likewise.
+ * gas/testsuite/gas/aarch64/lor-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/lor.d: Likewise.
+ * gas/testsuite/gas/aarch64/lse-atomic.d: Likewise.
+ * gas/testsuite/gas/aarch64/mapmisc.d: Likewise.
+ * gas/testsuite/gas/aarch64/mov-no-aliases.d: Likewise.
+ * gas/testsuite/gas/aarch64/mov.d: Likewise.
+ * gas/testsuite/gas/aarch64/movi.d: Likewise.
+ * gas/testsuite/gas/aarch64/movw_label.d: Likewise.
+ * gas/testsuite/gas/aarch64/msr.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-fp-cvt-int.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-frint.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-ins.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-not.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d: Likewise.
+ * gas/testsuite/gas/aarch64/neon-vfp-reglist.d: Likewise.
+ * gas/testsuite/gas/aarch64/no-aliases.d: Likewise.
+ * gas/testsuite/gas/aarch64/optional.d: Likewise.
+ * gas/testsuite/gas/aarch64/pac.d: Likewise.
+ * gas/testsuite/gas/aarch64/pan-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/pan.d: Likewise.
+ * gas/testsuite/gas/aarch64/rdma-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/rdma.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g0.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_hi12.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsldm-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsldm-page-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsldm_lo12_nc-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/shifted.d: Likewise.
+ * gas/testsuite/gas/aarch64/sve.d: Likewise.
+ * gas/testsuite/gas/aarch64/symbol.d: Likewise.
+ * gas/testsuite/gas/aarch64/sysreg-1.d: Likewise.
+ * gas/testsuite/gas/aarch64/sysreg-2.d: Likewise.
+ * gas/testsuite/gas/aarch64/sysreg-3.d: Likewise.
+ * gas/testsuite/gas/aarch64/sysreg.d: Likewise.
+ * gas/testsuite/gas/aarch64/system-2.d: Likewise.
+ * gas/testsuite/gas/aarch64/system-3.d: Likewise.
+ * gas/testsuite/gas/aarch64/system.d: Likewise.
+ * gas/testsuite/gas/aarch64/tbz_1.d: Likewise.
+ * gas/testsuite/gas/aarch64/tlbi_op.d: Likewise.
+ * gas/testsuite/gas/aarch64/tls.d: Likewise.
+ * gas/testsuite/gas/aarch64/uao-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/uao.d: Likewise.
+ * gas/testsuite/gas/aarch64/virthostext-directive.d: Likewise.
+ * gas/testsuite/gas/aarch64/virthostext.d: Likewise.
+ * gas/testsuite/gas/aarch64/adr_1.d: Restrict test under -mabi=lp64.
+ * gas/testsuite/gas/aarch64/int-insns.d: Likewise.
+ * gas/testsuite/gas/aarch64/programmer-friendly.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-data.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g1_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_g2.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst16.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst32.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst64.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12-ldst8.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst16.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst32.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst64.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-dtprel_lo12_nc-ldst8.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-gotoff_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-gotoff_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-gottprel_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-gottprel_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-insn.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsdesc_off_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsgd_g0_nc.d: Likewise.
+ * gas/testsuite/gas/aarch64/reloc-tlsgd_g1.d: Likewise.
+ * gas/testsuite/gas/aarch64/tail_padding.d: Likewise.
+ * gas/testsuite/gas/aarch64/tls-desc.d: Likewise.
+
2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
* config/tc-mips.c (mips16_macro_build) <'>'>: Remove case.
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 0b0100f0 add w16, w7, w1
4: 0b2100f0 add w16, w7, w1, uxtb
8: 0b2100f0 add w16, w7, w1, uxtb
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 0e303be7 saddlv h7, v31.8b
4: 4e303be7 saddlv h7, v31.16b
8: 0e703be7 saddlv s7, v31.4h
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
[^:]+: 6ec3c441 fcmla v1.2d, v2.2d, v3.2d, #0
[^:]+: 6ec3cc41 fcmla v1.2d, v2.2d, v3.2d, #90
[^:]+: 6ec3d441 fcmla v1.2d, v2.2d, v3.2d, #180
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
[0-9a-f]+: 4e63c441 fmaxnm v1.2d, v2.2d, v3.2d
[0-9a-f]+: 0e23c441 fmaxnm v1.2s, v2.2s, v3.2s
[0-9a-f]+: 4e23c441 fmaxnm v1.4s, v2.4s, v3.4s
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 0e20bbe0 abs v0.8b, v31.8b
4: 4e20bbe0 abs v0.16b, v31.16b
8: 0e60bbe0 abs v0.4h, v31.4h
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 5e0104ff mov b31, v7.b\[0\]
4: 5e0304ff mov b31, v7.b\[1\]
8: 5e0504ff mov b31, v7.b\[2\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 5ee0bbe0 abs d0, d31
4: 7ee0bbe0 neg d0, d31
8: 5e207be0 sqabs b0, b31
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 13823c20 extr w0, w1, w2, #15
4: 93c23c20 extr x0, x1, x2, #15
8: 13831c60 ror w0, w3, #7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
[^:]+: d503221f esb
[^:]+: d503221f esb
[^:]+: d5385305 mrs x5, erridr_el1
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 14000000 b 0 <bar>
- 0: R_AARCH64_JUMP26 bar\+0x8000000
+ 0: R_AARCH64_(P32_|)JUMP26 bar\+0x8000000
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 54000000 b\.eq 0 <bar> // b\.none
- 0: R_AARCH64_CONDBR19 bar\+0x100000
+ 0: R_AARCH64_(P32_|)CONDBR19 bar\+0x100000
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 13001cff sxtb wzr, w7
4: 93401cff sxtb xzr, w7
8: 13003cff sxth wzr, w7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 13001cff sbfm wzr, w7, #0, #7
4: 93401cff sbfm xzr, x7, #0, #7
8: 13003cff sbfm wzr, w7, #0, #15
.*: +file format.*aarch64.*
Sections:
-Idx Name Size VMA LMA File off Algn
+Idx Name[]+Size[ ]+VMA[ ]+LMA[ ]+File off[ ]+Algn
0 \.text .* .* .* .* 2\*\*2
.*CODE.*
1 \.data .* .* .* .* 2\*\*0
.*: +file format.*aarch64.*
Sections:
-Idx Name Size VMA LMA File off Algn
+Idx Name[ ]+Size[ ]+VMA[ ]+LMA[ ]+File off[ ]+Algn
0 \.text .* .* .* .* 2\*\*2
.*CODE.*
1 \.data .* .* .* .* 2\*\*0
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 1acf40e3 crc32b w3, w7, w15
4: 1ac345e7 crc32h w7, w15, w3
8: 1ac7486f crc32w w15, w3, w7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 1acf40e3 crc32b w3, w7, w15
4: 1ac345e7 crc32h w7, w15, w3
8: 1ac7486f crc32w w15, w3, w7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 4e284be7 aese v7.16b, v31.16b
4: 4e285be7 aesd v7.16b, v31.16b
8: 4e286be7 aesmc v7.16b, v31.16b
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 4e284be7 aese v7.16b, v31.16b
4: 4e285be7 aesd v7.16b, v31.16b
8: 4e286be7 aesmc v7.16b, v31.16b
#as: -g
Symbol table '.symtab' contains 10 entries:
- Num: Value Size Type Bind Vis Ndx Name
- 0: 0000000000000000 0 NOTYPE LOCAL DEFAULT UND
- 1: 0000000000000000 0 SECTION LOCAL DEFAULT 1
- 2: 0000000000000000 0 SECTION LOCAL DEFAULT 2
- 3: 0000000000000000 0 SECTION LOCAL DEFAULT 3
- 4: 0000000000000000 0 NOTYPE LOCAL DEFAULT 1 \$x
- 5: 0000000000000000 0 SECTION LOCAL DEFAULT 6
- 6: 0000000000000000 0 SECTION LOCAL DEFAULT 8
- 7: 0000000000000000 0 SECTION LOCAL DEFAULT 4
- 8: 0000000000000000 0 SECTION LOCAL DEFAULT 9
- 9: 0000000000000000 8 FUNC GLOBAL DEFAULT 1 testfunc
+ Num:[ ]+Value[ ]+Size[ ]+Type[ ]+Bind[ ]+Vis[ ]+Ndx[ ]+Name
+ 0: 0+ 0 NOTYPE LOCAL DEFAULT UND[ ]+
+ 1: 0+ 0 SECTION LOCAL DEFAULT 1[ ]+
+ 2: 0+ 0 SECTION LOCAL DEFAULT 2[ ]+
+ 3: 0+ 0 SECTION LOCAL DEFAULT 3[ ]+
+ 4: 0+ 0 NOTYPE LOCAL DEFAULT 1 \$x
+ 5: 0+ 0 SECTION LOCAL DEFAULT 6[ ]+
+ 6: 0+ 0 SECTION LOCAL DEFAULT 8[ ]+
+ 7: 0+ 0 SECTION LOCAL DEFAULT 4[ ]+
+ 8: 0+ 0 SECTION LOCAL DEFAULT 9[ ]+
+ 9: 0+ 8 FUNC GLOBAL DEFAULT 1 testfunc
Contents of the .debug_aranges section:
- Length: 44
+ Length: (44|28)
Version: 2
Offset into .debug_info: 0x0
- Pointer Size: 8
+ Pointer Size: (8|4)
Segment Size: 0
- Address Length
- 0000000000000000 0000000000000008
- 0000000000000000 0000000000000000
+ Address[ ]+Length
+ 0+ 0+8[ ]+
+ 0+ 0+[ ]+
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
[0-9a-f]+: 1e200400 fccmp s0, s0, #0x0, eq // eq = none
[0-9a-f]+: 1ee00400 fccmp h0, h0, #0x0, eq // eq = none
[0-9a-f]+: 1e22d420 fccmp s1, s2, #0x0, le
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 1e2f08e0 fmul s0, s7, s15
4: 1e2f18e0 fdiv s0, s7, s15
8: 1e2f28e0 fadd s0, s7, s15
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 1e7e0041 fjcvtzs w1, d2
4: 1e7e00e7 fjcvtzs w7, d7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 5ea0dbc0 fcmeq s0, s30, #0.0
4: 7ea0cba1 fcmge s1, s29, #0.0
8: 5ea0cb82 fcmgt s2, s28, #0.0
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 1e2000e7 fcvtns w7, s7
4: 9e2000e7 fcvtns x7, s7
8: 1e2100e7 fcvtnu w7, s7
Disassembly of section .*:
-0000000000000000 <.*>:
+0+ <.*>:
0: 1e251000 fmov s0, #1\.200000000000000000e\+01
4: 1e251000 fmov s0, #1\.200000000000000000e\+01
8: 1e251000 fmov s0, #1\.200000000000000000e\+01
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 3619194c tbz w12, #3, 2328 <\.text\+0x2328>
#objdump: -dr
-#as: -march=armv8-a
+#as: -march=armv8-a -mabi=lp64
.*: file format .*
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 58000001 ldr x1, 0 <bar>
- 0: R_AARCH64_LD_PREL_LO19 bar\+0x100000
+ 0: R_AARCH64_(P32_|)LD_PREL_LO19 bar\+0x100000
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 38bfc0e1 ldaprb w1, \[x7\]
4: 38bfc0e1 ldaprb w1, \[x7\]
8: 38bfc0e1 ldaprb w1, \[x7\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 080f7ce1 stxrb w15, w1, \[x7\]
4: 080f7ce1 stxrb w15, w1, \[x7\]
8: 080f7ce1 stxrb w15, w1, \[x7\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 3c1007e7 str b7, \[sp\], #-256
4: 3c1557e7 str b7, \[sp\], #-171
8: 3c0007e7 str b7, \[sp\], #0
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 3c100fe7 str b7, \[sp, #-256\]!
4: 3c155fe7 str b7, \[sp, #-171\]!
8: 3c000fe7 str b7, \[sp, #0\]!
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 29203fe7 stp w7, w15, \[sp, #-256\]
4: 2930bfe7 stp w7, w15, \[sp, #-124\]
8: 293fbfe7 stp w7, w15, \[sp, #-4\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 3c274be7 str b7, \[sp, w7, uxtw\]
4: 3c275be7 str b7, \[sp, w7, uxtw #0\]
8: 7c274be7 str h7, \[sp, w7, uxtw\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 3c1003e7 stur b7, \[sp, #-256\]
4: 3c1553e7 stur b7, \[sp, #-171\]
8: 3d0003e7 str b7, \[sp\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 3c1003e7 stur b7, \[sp, #-256\]
4: 3c1553e7 stur b7, \[sp, #-171\]
8: 3c0003e7 stur b7, \[sp\]
Disassembly of section \.text:
-0000000000000000 <.text>:
+0+ <.text>:
0: 889f7c00 stllr w0, \[x0\]
4: c89f7c00 stllr x0, \[x0\]
8: 889f7c01 stllr w1, \[x0\]
Disassembly of section \.text:
-0000000000000000 <.text>:
+0+ <.text>:
0: 889f7c00 stllr w0, \[x0\]
4: c89f7c00 stllr x0, \[x0\]
8: 889f7c01 stllr w1, \[x0\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 88a07c41 cas w0, w1, \[x2\]
4: 88a27fe3 cas w2, w3, \[sp\]
8: 88e07c41 casa w0, w1, \[x2\]
.*: +file format .*aarch64.*
SYMBOL TABLE:
-0+00 l d .text 0000000000000000 .text
-0+00 l d .data 0000000000000000 .data
-0+00 l d .bss 0000000000000000 .bss
-0+00 l F .text 0000000000000000 foo
-0+00 l .text 0000000000000000 \$x
-0+04 l .text 0000000000000000 \$d
-0+08 l .text 0000000000000000 \$x
-0+0c l .text 0000000000000000 \$d
-0+10 l .text 0000000000000000 \$x
-0+14 l .text 0000000000000000 \$d
-0+18 l .text 0000000000000000 \$x
-0+1c l .text 0000000000000000 \$d
-0+20 l .text 0000000000000000 \$x
-0+24 l .text 0000000000000000 \$d
-0+28 l .text 0000000000000000 \$x
-0+2c l .text 0000000000000000 \$d
-0+34 l .text 0000000000000000 \$x
-0+38 l .text 0000000000000000 \$d
-0+48 l .text 0000000000000000 \$x
-0+4c l .text 0000000000000000 \$d
-0+50 l .text 0000000000000000 \$x
-0+54 l .text 0000000000000000 \$d
-0+58 l .text 0000000000000000 \$x
-0+5c l .text 0000000000000000 \$d
-0+64 l .text 0000000000000000 \$x
-0+68 l .text 0000000000000000 \$d
-0+70 l .text 0000000000000000 \$x
-0+74 l .text 0000000000000000 \$d
-0+84 l .text 0000000000000000 \$x
-0+88 l .text 0000000000000000 \$d
-0+8c l .text 0000000000000000 \$x
-0+90 l .text 0000000000000000 \$d
-0+94 l .text 0000000000000000 \$x
-0+98 l .text 0000000000000000 \$d
-0+9c l .text 0000000000000000 \$x
-0+a0 l .text 0000000000000000 \$d
-0+a4 l .text 0000000000000000 \$x
-0+a8 l .text 0000000000000000 \$x
+0+00 l d .text 0+ .text
+0+00 l d .data 0+ .data
+0+00 l d .bss 0+ .bss
+0+00 l F .text 0+ foo
+0+00 l .text 0+ \$x
+0+04 l .text 0+ \$d
+0+08 l .text 0+ \$x
+0+0c l .text 0+ \$d
+0+10 l .text 0+ \$x
+0+14 l .text 0+ \$d
+0+18 l .text 0+ \$x
+0+1c l .text 0+ \$d
+0+20 l .text 0+ \$x
+0+24 l .text 0+ \$d
+0+28 l .text 0+ \$x
+0+2c l .text 0+ \$d
+0+34 l .text 0+ \$x
+0+38 l .text 0+ \$d
+0+48 l .text 0+ \$x
+0+4c l .text 0+ \$d
+0+50 l .text 0+ \$x
+0+54 l .text 0+ \$d
+0+58 l .text 0+ \$x
+0+5c l .text 0+ \$d
+0+64 l .text 0+ \$x
+0+68 l .text 0+ \$d
+0+70 l .text 0+ \$x
+0+74 l .text 0+ \$d
+0+84 l .text 0+ \$x
+0+88 l .text 0+ \$d
+0+8c l .text 0+ \$x
+0+90 l .text 0+ \$d
+0+94 l .text 0+ \$x
+0+98 l .text 0+ \$d
+0+9c l .text 0+ \$x
+0+a0 l .text 0+ \$d
+0+a4 l .text 0+ \$x
+0+a8 l .text 0+ \$x
Disassembly of section .text:
-0000000000000000 <foo>:
+0+ <foo>:
0: d503201f nop
4: 64636261 .word 0x64636261
8: d503201f nop
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 110003ef add w15, wsp, #0x0
4: 910003ef add x15, sp, #0x0
8: 110000ff add wsp, w7, #0x0
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 110003ef mov w15, wsp
4: 910003ef mov x15, sp
8: 110000ff mov wsp, w7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 2f00e41f movi d31, #0x0
4: 2f00e43f movi d31, #0xff
8: 2f00e45f movi d31, #0xff00
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: f2800002 movk x2, #0x0
- 0: R_AARCH64_MOVW_UABS_G0_NC x3.22
+ 0: R_AARCH64_(P32_|)MOVW_UABS_G0_NC x3.22
4: f2800002 movk x2, #0x0
- 4: R_AARCH64_MOVW_UABS_G0_NC x8
+ 4: R_AARCH64_(P32_|)MOVW_UABS_G0_NC x8
8: f2800002 movk x2, #0x0
- 8: R_AARCH64_MOVW_UABS_G0_NC w3
+ 8: R_AARCH64_(P32_|)MOVW_UABS_G0_NC w3
c: f2800002 movk x2, #0x0
- c: R_AARCH64_MOVW_UABS_G0_NC w8.22
+ c: R_AARCH64_(P32_|)MOVW_UABS_G0_NC w8.22
10: f2800002 movk x2, #0x0
- 10: R_AARCH64_MOVW_UABS_G0_NC sp
+ 10: R_AARCH64_(P32_|)MOVW_UABS_G0_NC sp
14: f2800002 movk x2, #0x0
- 14: R_AARCH64_MOVW_UABS_G0_NC wzr
+ 14: R_AARCH64_(P32_|)MOVW_UABS_G0_NC wzr
18: f2800002 movk x2, #0x0
- 18: R_AARCH64_MOVW_UABS_G0_NC xzr
+ 18: R_AARCH64_(P32_|)MOVW_UABS_G0_NC xzr
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d50340df msr daifset, #0x0
4: d50341df msr daifset, #0x1
8: d5034fdf msr daifset, #0xf
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 0e21a8e7 fcvtns v7.2s, v7.2s
4: 2e21a8e7 fcvtnu v7.2s, v7.2s
8: 0ea1a8e7 fcvtps v7.2s, v7.2s
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 0e2188e7 frintn v7.2s, v7.2s
4: 4e2188e7 frintn v7.4s, v7.4s
8: 4e6188e7 frintn v7.2d, v7.2d
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 4e011c21 mov v1.b\[0\], w1
4: 4e011c21 mov v1.b\[0\], w1
8: 4e011c42 mov v2.b\[0\], w2
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 2e205821 mvn v1.8b, v1.8b
4: 2e205821 mvn v1.8b, v1.8b
8: 6e205821 mvn v1.16b, v1.16b
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 0cdf7000 ld1 {v0.8b}, \[x0\], #8
4: 0cdfa000 ld1 {v0.8b, v1.8b}, \[x0\], #16
8: 0cdf6000 ld1 {v0.8b-v2.8b}, \[x0\], #24
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 0c407000 ld1 {v0.8b}, \[x0\]
4: 0c40a000 ld1 {v0.8b, v1.8b}, \[x0\]
8: 0c406000 ld1 {v0.8b-v2.8b}, \[x0\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 13823c20 extr w0, w1, w2, #15
4: 93c23c20 extr x0, x1, x2, #15
8: 13831c60 extr w0, w3, w3, #7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d4a001e1 dcps1 #0xf
4: d4a00001 dcps1
8: d4a00001 dcps1
3c: d5033f5f clrex
40: d508001f sys #0, C0, C0, #0
44: 10000000 adr x0, 0 <sym>
- 44: R_AARCH64_ADR_PREL_LO21 sym
+ 44: R_AARCH64_(P32_|)ADR_PREL_LO21 sym
48: f9400001 ldr x1, \[x0\]
- 48: R_AARCH64_LDST64_ABS_LO12_NC sym
+ 48: R_AARCH64_(P32_|)LDST64_ABS_LO12_NC sym
4c: f9400001 ldr x1, \[x0\]
- 4c: R_AARCH64_LDST64_ABS_LO12_NC sym
+ 4c: R_AARCH64_(P32_|)LDST64_ABS_LO12_NC sym
50: f9000001 str x1, \[x0\]
- 50: R_AARCH64_LDST64_ABS_LO12_NC sym
+ 50: R_AARCH64_(P32_|)LDST64_ABS_LO12_NC sym
54: f9000001 str x1, \[x0\]
- 54: R_AARCH64_LDST64_ABS_LO12_NC sym
+ 54: R_AARCH64_(P32_|)LDST64_ABS_LO12_NC sym
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: dac10083 pacia x3, x4
4: dac103e5 pacia x5, sp
8: dac10483 pacib x3, x4
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d500419f msr pan, #0x1
4: d500409f msr pan, #0x0
8: d5184260 msr pan, x0
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d500419f msr pan, #0x1
4: d500409f msr pan, #0x0
8: d5184260 msr pan, x0
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
+#as: -mabi=lp64
#objdump: -dr
#skip: aarch64_be-*-*
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d2800009 mov x9, #0x0.*
- 0: R_AARCH64_TLSLD_MOVW_DTPREL_G0 x
+ 0: R_AARCH64_(P32_|)TLSLD_MOVW_DTPREL_G0 x
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: f2800010 movk x16, #0x0
- 0: R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC x
+ 0: R_AARCH64_(P32_|)TLSLD_MOVW_DTPREL_G0_NC x
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d2a00009 movz x9, #0x0, lsl #16
- 0: R_AARCH64_TLSLD_MOVW_DTPREL_G1 x
+ 0: R_AARCH64_(P32_|)TLSLD_MOVW_DTPREL_G1 x
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 91000341 add x1, x26, #0x0
- 0: R_AARCH64_TLSLD_ADD_DTPREL_HI12 x
+ 0: R_AARCH64_(P32_|)TLSLD_ADD_DTPREL_HI12 x
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 91000347 add x7, x26, #0x0
- 0: R_AARCH64_TLSLD_ADD_DTPREL_LO12 x
+ 0: R_AARCH64_(P32_|)TLSLD_ADD_DTPREL_LO12 x
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 91000347 add x7, x26, #0x0
- 0: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC x
+ 0: R_AARCH64_(P32_|)TLSLD_ADD_DTPREL_LO12_NC x
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 8b030041 add x1, x2, x3
4: 10000000 adr x0, 0 <dummy>
- 4: R_AARCH64_TLSLD_ADR_PREL21 dummy
+ 4: R_AARCH64_(P32_|)TLSLD_ADR_PREL21 dummy
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 8b030041 add x1, x2, x3
4: 90000000 adrp x0, 0 <dummy>
- 4: R_AARCH64_TLSLD_ADR_PAGE21 dummy
+ 4: R_AARCH64_(P32_|)TLSLD_ADR_PAGE21 dummy
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 91000000 add x0, x0, #0x0
- 0: R_AARCH64_TLSLD_ADD_LO12_NC x
+ 0: R_AARCH64_(P32_|)TLSLD_ADD_LO12_NC x
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: aa030041 orr x1, x2, x3
4: aa030441 orr x1, x2, x3, lsl #1
8: aa030c41 orr x1, x2, x3, lsl #3
Disassembly of section .*:
-0000000000000000 <.*>:
+0+ <.*>:
.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
.*: 25b9c001 fmov z1\.s, #2\.0+e\+00
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: b9400401 ldr w1, \[x0, #4\]
4: b9400401 ldr w1, \[x0, #4\]
8: b9401001 ldr w1, \[x0, #16\]
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d5380587 mrs x7, id_aa64afr0_el1
4: d53805a7 mrs x7, id_aa64afr1_el1
8: d5380347 mrs x7, mvfr2_el1
Disassembly of section .text:
-0000000000000000 <.*>:
+0+ <.*>:
[0-9a-f]+: d5380725 mrs x5, id_aa64mmfr1_el1
[0-9a-f]+: d5380747 mrs x7, id_aa64mmfr2_el1
[0-9a-f]+: d5385305 mrs x5, erridr_el1
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d5182100 msr apiakeylo_el1, x0
4: d5382100 mrs x0, apiakeylo_el1
8: d5182121 msr apiakeyhi_el1, x1
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d51b9c67 msr pmovsclr_el0, x7
4: d53b9c60 mrs x0, pmovsclr_el0
8: d51b9e67 msr pmovsset_el0, x7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d503221f esb
4: d503221f esb
8: d503223f psb csync
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d50320ff xpaclri
4: d50320ff xpaclri
8: d503211f pacia1716
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d6bf03e0 drps
4: d503201f nop
8: d503203f yield
2dc: d5033fdf isb
2e0: d5033fdf isb
2e4: d8000000 prfm pldl1keep, 0 <LABEL1>
- 2e4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 2e4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
2e8: f8af6be0 prfm pldl1keep, \[sp, x15\]
2ec: f8be58e0 prfm pldl1keep, \[x7, w30, uxtw #3\]
2f0: f9800c60 prfm pldl1keep, \[x3, #24\]
2f4: d8000001 prfm pldl1strm, 0 <LABEL1>
- 2f4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 2f4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
2f8: f8af6be1 prfm pldl1strm, \[sp, x15\]
2fc: f8be58e1 prfm pldl1strm, \[x7, w30, uxtw #3\]
300: f9800c61 prfm pldl1strm, \[x3, #24\]
304: d8000002 prfm pldl2keep, 0 <LABEL1>
- 304: R_AARCH64_LD_PREL_LO19 LABEL1
+ 304: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
308: f8af6be2 prfm pldl2keep, \[sp, x15\]
30c: f8be58e2 prfm pldl2keep, \[x7, w30, uxtw #3\]
310: f9800c62 prfm pldl2keep, \[x3, #24\]
314: d8000003 prfm pldl2strm, 0 <LABEL1>
- 314: R_AARCH64_LD_PREL_LO19 LABEL1
+ 314: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
318: f8af6be3 prfm pldl2strm, \[sp, x15\]
31c: f8be58e3 prfm pldl2strm, \[x7, w30, uxtw #3\]
320: f9800c63 prfm pldl2strm, \[x3, #24\]
324: d8000004 prfm pldl3keep, 0 <LABEL1>
- 324: R_AARCH64_LD_PREL_LO19 LABEL1
+ 324: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
328: f8af6be4 prfm pldl3keep, \[sp, x15\]
32c: f8be58e4 prfm pldl3keep, \[x7, w30, uxtw #3\]
330: f9800c64 prfm pldl3keep, \[x3, #24\]
334: d8000005 prfm pldl3strm, 0 <LABEL1>
- 334: R_AARCH64_LD_PREL_LO19 LABEL1
+ 334: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
338: f8af6be5 prfm pldl3strm, \[sp, x15\]
33c: f8be58e5 prfm pldl3strm, \[x7, w30, uxtw #3\]
340: f9800c65 prfm pldl3strm, \[x3, #24\]
344: d8000006 prfm #0x06, 0 <LABEL1>
- 344: R_AARCH64_LD_PREL_LO19 LABEL1
+ 344: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
348: f8af6be6 prfm #0x06, \[sp, x15\]
34c: f8be58e6 prfm #0x06, \[x7, w30, uxtw #3\]
350: f9800c66 prfm #0x06, \[x3, #24\]
354: d8000007 prfm #0x07, 0 <LABEL1>
- 354: R_AARCH64_LD_PREL_LO19 LABEL1
+ 354: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
358: f8af6be7 prfm #0x07, \[sp, x15\]
35c: f8be58e7 prfm #0x07, \[x7, w30, uxtw #3\]
360: f9800c67 prfm #0x07, \[x3, #24\]
364: d8000008 prfm plil1keep, 0 <LABEL1>
- 364: R_AARCH64_LD_PREL_LO19 LABEL1
+ 364: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
368: f8af6be8 prfm plil1keep, \[sp, x15\]
36c: f8be58e8 prfm plil1keep, \[x7, w30, uxtw #3\]
370: f9800c68 prfm plil1keep, \[x3, #24\]
374: d8000009 prfm plil1strm, 0 <LABEL1>
- 374: R_AARCH64_LD_PREL_LO19 LABEL1
+ 374: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
378: f8af6be9 prfm plil1strm, \[sp, x15\]
37c: f8be58e9 prfm plil1strm, \[x7, w30, uxtw #3\]
380: f9800c69 prfm plil1strm, \[x3, #24\]
384: d800000a prfm plil2keep, 0 <LABEL1>
- 384: R_AARCH64_LD_PREL_LO19 LABEL1
+ 384: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
388: f8af6bea prfm plil2keep, \[sp, x15\]
38c: f8be58ea prfm plil2keep, \[x7, w30, uxtw #3\]
390: f9800c6a prfm plil2keep, \[x3, #24\]
394: d800000b prfm plil2strm, 0 <LABEL1>
- 394: R_AARCH64_LD_PREL_LO19 LABEL1
+ 394: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
398: f8af6beb prfm plil2strm, \[sp, x15\]
39c: f8be58eb prfm plil2strm, \[x7, w30, uxtw #3\]
3a0: f9800c6b prfm plil2strm, \[x3, #24\]
3a4: d800000c prfm plil3keep, 0 <LABEL1>
- 3a4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3a4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
3a8: f8af6bec prfm plil3keep, \[sp, x15\]
3ac: f8be58ec prfm plil3keep, \[x7, w30, uxtw #3\]
3b0: f9800c6c prfm plil3keep, \[x3, #24\]
3b4: d800000d prfm plil3strm, 0 <LABEL1>
- 3b4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3b4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
3b8: f8af6bed prfm plil3strm, \[sp, x15\]
3bc: f8be58ed prfm plil3strm, \[x7, w30, uxtw #3\]
3c0: f9800c6d prfm plil3strm, \[x3, #24\]
3c4: d800000e prfm #0x0e, 0 <LABEL1>
- 3c4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3c4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
3c8: f8af6bee prfm #0x0e, \[sp, x15\]
3cc: f8be58ee prfm #0x0e, \[x7, w30, uxtw #3\]
3d0: f9800c6e prfm #0x0e, \[x3, #24\]
3d4: d800000f prfm #0x0f, 0 <LABEL1>
- 3d4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3d4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
3d8: f8af6bef prfm #0x0f, \[sp, x15\]
3dc: f8be58ef prfm #0x0f, \[x7, w30, uxtw #3\]
3e0: f9800c6f prfm #0x0f, \[x3, #24\]
3e4: d8000010 prfm pstl1keep, 0 <LABEL1>
- 3e4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3e4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
3e8: f8af6bf0 prfm pstl1keep, \[sp, x15\]
3ec: f8be58f0 prfm pstl1keep, \[x7, w30, uxtw #3\]
3f0: f9800c70 prfm pstl1keep, \[x3, #24\]
3f4: d8000011 prfm pstl1strm, 0 <LABEL1>
- 3f4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 3f4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
3f8: f8af6bf1 prfm pstl1strm, \[sp, x15\]
3fc: f8be58f1 prfm pstl1strm, \[x7, w30, uxtw #3\]
400: f9800c71 prfm pstl1strm, \[x3, #24\]
404: d8000012 prfm pstl2keep, 0 <LABEL1>
- 404: R_AARCH64_LD_PREL_LO19 LABEL1
+ 404: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
408: f8af6bf2 prfm pstl2keep, \[sp, x15\]
40c: f8be58f2 prfm pstl2keep, \[x7, w30, uxtw #3\]
410: f9800c72 prfm pstl2keep, \[x3, #24\]
414: d8000013 prfm pstl2strm, 0 <LABEL1>
- 414: R_AARCH64_LD_PREL_LO19 LABEL1
+ 414: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
418: f8af6bf3 prfm pstl2strm, \[sp, x15\]
41c: f8be58f3 prfm pstl2strm, \[x7, w30, uxtw #3\]
420: f9800c73 prfm pstl2strm, \[x3, #24\]
424: d8000014 prfm pstl3keep, 0 <LABEL1>
- 424: R_AARCH64_LD_PREL_LO19 LABEL1
+ 424: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
428: f8af6bf4 prfm pstl3keep, \[sp, x15\]
42c: f8be58f4 prfm pstl3keep, \[x7, w30, uxtw #3\]
430: f9800c74 prfm pstl3keep, \[x3, #24\]
434: d8000015 prfm pstl3strm, 0 <LABEL1>
- 434: R_AARCH64_LD_PREL_LO19 LABEL1
+ 434: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
438: f8af6bf5 prfm pstl3strm, \[sp, x15\]
43c: f8be58f5 prfm pstl3strm, \[x7, w30, uxtw #3\]
440: f9800c75 prfm pstl3strm, \[x3, #24\]
444: d8000016 prfm #0x16, 0 <LABEL1>
- 444: R_AARCH64_LD_PREL_LO19 LABEL1
+ 444: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
448: f8af6bf6 prfm #0x16, \[sp, x15\]
44c: f8be58f6 prfm #0x16, \[x7, w30, uxtw #3\]
450: f9800c76 prfm #0x16, \[x3, #24\]
454: d8000017 prfm #0x17, 0 <LABEL1>
- 454: R_AARCH64_LD_PREL_LO19 LABEL1
+ 454: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
458: f8af6bf7 prfm #0x17, \[sp, x15\]
45c: f8be58f7 prfm #0x17, \[x7, w30, uxtw #3\]
460: f9800c77 prfm #0x17, \[x3, #24\]
464: d8000018 prfm #0x18, 0 <LABEL1>
- 464: R_AARCH64_LD_PREL_LO19 LABEL1
+ 464: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
468: f8af6bf8 prfm #0x18, \[sp, x15\]
46c: f8be58f8 prfm #0x18, \[x7, w30, uxtw #3\]
470: f9800c78 prfm #0x18, \[x3, #24\]
474: d8000019 prfm #0x19, 0 <LABEL1>
- 474: R_AARCH64_LD_PREL_LO19 LABEL1
+ 474: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
478: f8af6bf9 prfm #0x19, \[sp, x15\]
47c: f8be58f9 prfm #0x19, \[x7, w30, uxtw #3\]
480: f9800c79 prfm #0x19, \[x3, #24\]
484: d800001a prfm #0x1a, 0 <LABEL1>
- 484: R_AARCH64_LD_PREL_LO19 LABEL1
+ 484: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
488: f8af6bfa prfm #0x1a, \[sp, x15\]
48c: f8be58fa prfm #0x1a, \[x7, w30, uxtw #3\]
490: f9800c7a prfm #0x1a, \[x3, #24\]
494: d800001b prfm #0x1b, 0 <LABEL1>
- 494: R_AARCH64_LD_PREL_LO19 LABEL1
+ 494: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
498: f8af6bfb prfm #0x1b, \[sp, x15\]
49c: f8be58fb prfm #0x1b, \[x7, w30, uxtw #3\]
4a0: f9800c7b prfm #0x1b, \[x3, #24\]
4a4: d800001c prfm #0x1c, 0 <LABEL1>
- 4a4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 4a4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
4a8: f8af6bfc prfm #0x1c, \[sp, x15\]
4ac: f8be58fc prfm #0x1c, \[x7, w30, uxtw #3\]
4b0: f9800c7c prfm #0x1c, \[x3, #24\]
4b4: d800001d prfm #0x1d, 0 <LABEL1>
- 4b4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 4b4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
4b8: f8af6bfd prfm #0x1d, \[sp, x15\]
4bc: f8be58fd prfm #0x1d, \[x7, w30, uxtw #3\]
4c0: f9800c7d prfm #0x1d, \[x3, #24\]
4c4: d800001e prfm #0x1e, 0 <LABEL1>
- 4c4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 4c4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
4c8: f8af6bfe prfm #0x1e, \[sp, x15\]
4cc: f8be58fe prfm #0x1e, \[x7, w30, uxtw #3\]
4d0: f9800c7e prfm #0x1e, \[x3, #24\]
4d4: d800001f prfm #0x1f, 0 <LABEL1>
- 4d4: R_AARCH64_LD_PREL_LO19 LABEL1
+ 4d4: R_AARCH64_(P32_|)LD_PREL_LO19 LABEL1
4d8: f8af6bff prfm #0x1f, \[sp, x15\]
4dc: f8be58ff prfm #0x1f, \[x7, w30, uxtw #3\]
4e0: f9800c7f prfm #0x1f, \[x3, #24\]
+#as: -mabi=lp64
#readelf: -S
#name: AArch64 section tail padding
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 36080000 tbz w0, #1, 0 <bar>
- 0: R_AARCH64_TSTBR14 bar\+0x8000
+ 0: R_AARCH64_(P32_|)TSTBR14 bar\+0x8000
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: d50c8027 tlbi ipas2e1is, x7
4: d50c80a7 tlbi ipas2le1is, x7
8: d508831f tlbi vmalle1is
+#as: -mabi=lp64
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
0: 90000000 adrp x0, 0 <var>
- 0: R_AARCH64_TLSDESC_ADR_PAGE21 var
+ 0: R_AARCH64_(P32_|)TLSDESC_ADR_PAGE21 var
4: f9400001 ldr x1, \[x0\]
- 4: R_AARCH64_TLSDESC_LD64_LO12_NC var
+ 4: R_AARCH64_(P32_|)TLSDESC_LD(64|32)_LO12_NC var
8: 91000000 add x0, x0, #0x0
- 8: R_AARCH64_TLSDESC_ADD_LO12_NC var
+ 8: R_AARCH64_(P32_|)TLSDESC_ADD_LO12_NC var
c: d63f0020 blr x1
- c: R_AARCH64_TLSDESC_CALL var
+ c: R_AARCH64_(P32_|)TLSDESC_CALL var
10: 90000000 adrp x0, 0 <var>
- 10: R_AARCH64_TLSGD_ADR_PAGE21 var
+ 10: R_AARCH64_(P32_|)TLSGD_ADR_PAGE21 var
14: 91000000 add x0, x0, #0x0
- 14: R_AARCH64_TLSGD_ADD_LO12_NC var
+ 14: R_AARCH64_(P32_|)TLSGD_ADD_LO12_NC var
18: 94000000 bl 0 <__tls_get_addr>
- 18: R_AARCH64_CALL26 __tls_get_addr
+ 18: R_AARCH64_(P32_|)CALL26 __tls_get_addr
1c: 90000000 adrp x0, 0 <var>
- 1c: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 var
+ 1c: R_AARCH64_(P32_|)TLSIE_ADR_GOTTPREL_PAGE21 var
20: f9400000 ldr x0, \[x0\]
- 20: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC var
+ 20: R_AARCH64_(P32_|)TLSIE_LD(64|32)_GOTTPREL_LO12_NC var
24: 91000020 add x0, x1, #0x0
- 24: R_AARCH64_TLSLE_ADD_TPREL_LO12 var
+ 24: R_AARCH64_(P32_|)TLSLE_ADD_TPREL_LO12 var
28: 91400020 add x0, x1, #0x0, lsl #12
- 28: R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+ 28: R_AARCH64_(P32_|)TLSLE_ADD_TPREL_HI12 var
2c: 91400020 add x0, x1, #0x0, lsl #12
- 2c: R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+ 2c: R_AARCH64_(P32_|)TLSLE_ADD_TPREL_HI12 var
30: 91000020 add x0, x1, #0x0
- 30: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC var
+ 30: R_AARCH64_(P32_|)TLSLE_ADD_TPREL_LO12_NC var
34: d2a00000 movz x0, #0x0, lsl #16
- 34: R_AARCH64_TLSLE_MOVW_TPREL_G1 var
+ 34: R_AARCH64_(P32_|)TLSLE_MOVW_TPREL_G1 var
38: f2800000 movk x0, #0x0
- 38: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC var
+ 38: R_AARCH64_(P32_|)TLSLE_MOVW_TPREL_G0_NC var
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
[0-9a-f]:+ d500417f msr uao, #0x1
[0-9a-f]:+ d500407f msr uao, #0x0
[0-9a-f]:+ d5184280 msr uao, x0
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
[0-9a-f]:+ d500417f msr uao, #0x1
[0-9a-f]:+ d500407f msr uao, #0x0
[0-9a-f]:+ d5184280 msr uao, x0
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
[0-9a-f]+: d51d4007 msr spsr_el12, x7
[0-9a-f]+: d53d4007 mrs x7, spsr_el12
[0-9a-f]+: d51d4027 msr elr_el12, x7
Disassembly of section \.text:
-0000000000000000 <.*>:
+0+ <.*>:
[0-9a-f]+: d51d4007 msr spsr_el12, x7
[0-9a-f]+: d53d4007 mrs x7, spsr_el12
[0-9a-f]+: d51d4027 msr elr_el12, x7
projects / deliverable / binutils-gdb.git / commitdiff
