drm/i915: Unlock PCH_PP_CONTROL always

Avoid any question about locked registers by just writing the unlock
pattern with every write to the register.

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b7fbb74b1829dc2fcb6e0e9861d896909552e86c..5596e8e0ead7312eb64089c9b121ddeba0d78d89 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3311,6 +3311,7 @@
 #define PCH_PP_STATUS          0xc7200
 #define PCH_PP_CONTROL         0xc7204
 #define  PANEL_UNLOCK_REGS     (0xabcd << 16)
+#define  PANEL_UNLOCK_MASK     (0xffff << 16)
 #define  EDP_FORCE_VDD         (1 << 3)
 #define  EDP_BLC_ENABLE                (1 << 2)
 #define  PANEL_POWER_RESET     (1 << 1)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1bf3258824c20d0615c6387c3e1f048cf32f5cf0..9c2158c9c1377bf8d3e0db58265fd96c5f444e55 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -840,6 +840,8 @@ static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
                msleep(dev_priv->panel_t3);
 
        pp = I915_READ(PCH_PP_CONTROL);
+       pp &= ~PANEL_UNLOCK_MASK;
+       pp |= PANEL_UNLOCK_REGS;
        pp |= EDP_FORCE_VDD;
        I915_WRITE(PCH_PP_CONTROL, pp);
        POSTING_READ(PCH_PP_CONTROL);
@@ -852,6 +854,8 @@ static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
        u32 pp;
 
        pp = I915_READ(PCH_PP_CONTROL);
+       pp &= ~PANEL_UNLOCK_MASK;
+       pp |= PANEL_UNLOCK_REGS;
        pp &= ~EDP_FORCE_VDD;
        I915_WRITE(PCH_PP_CONTROL, pp);
        POSTING_READ(PCH_PP_CONTROL);
@@ -871,13 +875,15 @@ static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
                return true;
 
        pp = I915_READ(PCH_PP_CONTROL);
+       pp &= ~PANEL_UNLOCK_MASK;
+       pp |= PANEL_UNLOCK_REGS;
 
        /* ILK workaround: disable reset around power sequence */
        pp &= ~PANEL_POWER_RESET;
        I915_WRITE(PCH_PP_CONTROL, pp);
        POSTING_READ(PCH_PP_CONTROL);
 
-       pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
+       pp |= POWER_TARGET_ON;
        I915_WRITE(PCH_PP_CONTROL, pp);
        POSTING_READ(PCH_PP_CONTROL);
 
@@ -900,6 +906,8 @@ static void ironlake_edp_panel_off (struct drm_device *dev)
                PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
 
        pp = I915_READ(PCH_PP_CONTROL);
+       pp &= ~PANEL_UNLOCK_MASK;
+       pp |= PANEL_UNLOCK_REGS;
 
        /* ILK workaround: disable reset around power sequence */
        pp &= ~PANEL_POWER_RESET;
@@ -933,6 +941,8 @@ static void ironlake_edp_backlight_on (struct drm_device *dev)
         */
        msleep(300);
        pp = I915_READ(PCH_PP_CONTROL);
+       pp &= ~PANEL_UNLOCK_MASK;
+       pp |= PANEL_UNLOCK_REGS;
        pp |= EDP_BLC_ENABLE;
        I915_WRITE(PCH_PP_CONTROL, pp);
 }
@@ -944,6 +954,8 @@ static void ironlake_edp_backlight_off (struct drm_device *dev)
 
        DRM_DEBUG_KMS("\n");
        pp = I915_READ(PCH_PP_CONTROL);
+       pp &= ~PANEL_UNLOCK_MASK;
+       pp |= PANEL_UNLOCK_REGS;
        pp &= ~EDP_BLC_ENABLE;
        I915_WRITE(PCH_PP_CONTROL, pp);
 }