x86: restrict %tr<N> visibility

First of all, these registers have never been available on any 64-bit
CPU, and hence should not be recognized in 64-bit mode. But even before
that they had already disappeared - also don't recognize them when 586
or 686 architectures were explicitly set.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index abc0869d10ab5788b36ae974808302f8ab9612da..d40008148d21a52ed31619291e1ef5ef90532d5f 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2020-06-08  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (check_register): Split RegTR handling, to
+       fail recognition also in 64-bit mode as well as with i586 or
+       i686 explicitly enabled.
+       * testsuite/gas/i386/x86_64.s: Add insns referencing tr<N>.
+       * testsuite/gas/i386/x86_64-intel.d,
+       testsuite/gas/i386/x86_64.d: Adjust expectations.
+
 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 
        * testsuite/gas/cfi/cfi-i386-2.d: Adjust expectations.

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 6b9479872c239349ff59ad4ee493d5f8ac72a365..cfb3b992cd81a4e451e207214998c1af40709526 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -12358,11 +12358,17 @@ static bfd_boolean check_register (const reg_entry *r)
   if ((r->reg_type.bitfield.dword
        || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
        || r->reg_type.bitfield.class == RegCR
-       || r->reg_type.bitfield.class == RegDR
-       || r->reg_type.bitfield.class == RegTR)
+       || r->reg_type.bitfield.class == RegDR)
       && !cpu_arch_flags.bitfield.cpui386)
     return FALSE;
 
+  if (r->reg_type.bitfield.class == RegTR
+      && (flag_code == CODE_64BIT
+         || !cpu_arch_flags.bitfield.cpui386
+         || cpu_arch_isa_flags.bitfield.cpui586
+         || cpu_arch_isa_flags.bitfield.cpui686))
+    return FALSE;
+
   if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
     return FALSE;
 

diff --git a/gas/testsuite/gas/i386/x86_64-intel.d b/gas/testsuite/gas/i386/x86_64-intel.d
index 2e39348827bc5d3b5665ee284b53ad0db7f60ee7..293a6d897d511097d1a3d62b81b910b5dffcbc64 100644 (file)
--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -256,4 +256,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    48 0f b7 00             movzx  rax,WORD PTR \[rax\]
 [      ]*[a-f0-9]+:    0f c3 00                movnti DWORD PTR \[rax\],eax
 [      ]*[a-f0-9]+:    48 0f c3 00             movnti QWORD PTR \[rax\],rax
+[      ]*[a-f0-9]+:    8b 04 25 00 00 00 00    mov    eax,DWORD PTR (ds:)?0x0
+[      ]*[a-f0-9]+:    48 89 0c 25 00 00 00 00         mov    QWORD PTR (ds:)?0x0,rcx
 #pass

diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d
index 4a73ddc57f9b1fe8ecbf51731b03511e77220cfc..0c867f844fdec56c683ed9d53cadab1fc8e28acc 100644 (file)
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -256,4 +256,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    48 0f b7 00             movzwq \(%rax\),%rax
 [      ]*[a-f0-9]+:    0f c3 00                movnti %eax,\(%rax\)
 [      ]*[a-f0-9]+:    48 0f c3 00             movnti %rax,\(%rax\)
+[      ]*[a-f0-9]+:    8b 04 25 00 00 00 00    mov    0x0,%eax
+[      ]*[a-f0-9]+:    48 89 0c 25 00 00 00 00         mov    %rcx,0x0
 #pass

diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s
index da820439a9270cb1144daf282baab44cbf6ff4d3..e050b14be3647bd29ab65c1b0f21369618ae3941 100644 (file)
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -307,3 +307,6 @@ movzx rax, WORD PTR [rax]
 
 movnti dword ptr [rax], eax
 movnti qword ptr [rax], rax
+
+mov eax, tr1
+mov tr0, rcx