* config/tc-mips.c (hilo_interlocks, gpr_interlocks,

cop_interlocks): Remove superfluous CPU entries.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2b7977a760cee643fd6d7f50f8c844903cfd3124..672bc686c1b898c27724a89088d8abd09912ea92 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2004-04-22  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+       * config/tc-mips.c (hilo_interlocks, gpr_interlocks,
+       cop_interlocks): Remove superfluous CPU entries.
+
 2004-04-22  Paul Brook  <paul@codesourcery.com>
 
        * config/tc-arm.c (mav_parse_offset): Value must be multiple of 4.

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 7b6cee85df417d8997f4b921c490da93de92440e..80fb607789fd5a3ad92ccd1e4cdf1c26f0e677df 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -346,7 +346,6 @@ static int mips_32bitmode = 0;
    || mips_opts.arch == CPU_R10000                    \
    || mips_opts.arch == CPU_R12000                    \
    || mips_opts.arch == CPU_RM7000                    \
-   || mips_opts.arch == CPU_SB1                       \
    || mips_opts.arch == CPU_VR5500                    \
    )
 
@@ -357,8 +356,6 @@ static int mips_32bitmode = 0;
    level I.  */
 #define gpr_interlocks \
   (mips_opts.isa != ISA_MIPS1  \
-   || mips_opts.arch == CPU_VR5400  \
-   || mips_opts.arch == CPU_VR5500  \
    || mips_opts.arch == CPU_R3900)
 
 /* Whether the processor uses hardware interlocks to avoid delays
@@ -374,9 +371,6 @@ static int mips_32bitmode = 0;
     && mips_opts.isa != ISA_MIPS2                     \
     && mips_opts.isa != ISA_MIPS3)                    \
    || mips_opts.arch == CPU_R4300                     \
-   || mips_opts.arch == CPU_VR5400                    \
-   || mips_opts.arch == CPU_VR5500                    \
-   || mips_opts.arch == CPU_SB1                       \
    )
 
 /* Whether the processor uses hardware interlocks to protect reads