m32c padding with nops

m32c_md_end attempted to pad out a code section with nops, but this
was just plain wrong in many ways:
- The padding didn't happen at all if the last section emitted wasn't
  a code section.
- The padding went to the wrong place if subsections were used, and
  the last subseg used wasn't the highest numbered subseg.
- Padding wasn't added to all code sections.
- If the last section was empty, it was padded to 4 bytes.
- The padding didn't go to a 4-byte alignment boundary, instead it
  effectively made the last instruction 4 bytes in size.
- The padding didn't take into account that code sections may have
  contents other than machine instructions.

So, rip it out and handle nop padding properly, also fixing .align
.balign/.p2align in the middle of code.

gas/
	* config/tc-m32c.c (insn_size): Delete static var.
	(md_begin): Don't set it.
	(m32c_md_end): Delete.
	(md_assemble): Add insn_size auto var.
	* config/tc-m32c.h (md_end): Don't define.
	(m32c_md_end): Delete.
	(NOP_OPCODE, HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Define.
	* testsuite/gas/all/align.d: Remove m32c from notarget list.
	* testsuite/gas/all/incbin.d: Likewise.
	* testsuite/gas/elf/dwarf2-11.d: Likewise.
	* testsuite/gas/macros/semi.d: Likewise.
	* testsuite/gas/all/gas.exp (do_comment): Similarly.
ld/
	* testsuite/ld-scripts/fill.d: Don't xfail m32c
	* testsuite/ld-scripts/fill16.d: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8a82fdecbe66ed885fc2767b0d1eab29bfa42319..8ba1cde35e805d1502125469b65280dd742b020e 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,18 @@
+2019-05-04  Alan Modra  <amodra@gmail.com>
+
+       * config/tc-m32c.c (insn_size): Delete static var.
+       (md_begin): Don't set it.
+       (m32c_md_end): Delete.
+       (md_assemble): Add insn_size auto var.
+       * config/tc-m32c.h (md_end): Don't define.
+       (m32c_md_end): Delete.
+       (NOP_OPCODE, HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Define.
+       * testsuite/gas/all/align.d: Remove m32c from notarget list.
+       * testsuite/gas/all/incbin.d: Likewise.
+       * testsuite/gas/elf/dwarf2-11.d: Likewise.
+       * testsuite/gas/macros/semi.d: Likewise.
+       * testsuite/gas/all/gas.exp (do_comment): Similarly.
+
 2019-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/24485

diff --git a/gas/config/tc-m32c.c b/gas/config/tc-m32c.c
index d6531869668dd96581641389e837637379a5857f..07501df27a556494f0d5c10ed581e4ea3d487cbc 100644 (file)
--- a/gas/config/tc-m32c.c
+++ b/gas/config/tc-m32c.c
@@ -86,7 +86,6 @@ size_t md_longopts_size = sizeof (md_longopts);
 
 static unsigned long m32c_mach = bfd_mach_m16c;
 static int cpu_mach = (1 << MACH_M16C);
-static int insn_size;
 static int m32c_relax = 0;
 
 /* Flags to set in the elf header */
@@ -185,22 +184,6 @@ md_begin (void)
 
   /* Set the machine type */
   bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach);
-
-  insn_size = 0;
-}
-
-void
-m32c_md_end (void)
-{
-  int i, n_nops;
-
-  if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
-    {
-      /* Pad with nops for objdump.  */
-      n_nops = (32 - ((insn_size) % 32)) / 8;
-      for (i = 1; i <= n_nops; i++)
-       md_assemble ((char *) "nop");
-    }
 }
 
 void
@@ -335,6 +318,7 @@ md_assemble (char * str)
   char *    errmsg;
   finished_insnS results;
   int rl_type;
+  int insn_size;
 
   if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str))
     return;

diff --git a/gas/config/tc-m32c.h b/gas/config/tc-m32c.h
index a30b828b78b554a99ad02f0480a576a7466dcd68..b55dd612190e90441ff1fb2be8cc6e24e3c4dcd7 100644 (file)
--- a/gas/config/tc-m32c.h
+++ b/gas/config/tc-m32c.h
@@ -29,9 +29,6 @@
 
 #define TARGET_BYTES_BIG_ENDIAN 0
 
-#define md_end  m32c_md_end
-extern void m32c_md_end (void);
-
 #define md_start_line_hook m32c_start_line_hook
 extern void m32c_start_line_hook (void);
 
@@ -85,3 +82,7 @@ extern long md_pcrel_from_section (struct fix *, segT);
 extern int m32c_is_colon_insn (char *, char *);
 
 #define H_TICK_HEX 1
+
+#define NOP_OPCODE (bfd_get_mach (stdoutput) == bfd_mach_m32c ? 0xde : 0x04)
+#define HANDLE_ALIGN(fragP)
+#define MAX_MEM_FOR_RS_ALIGN_CODE 1

diff --git a/gas/testsuite/gas/all/align.d b/gas/testsuite/gas/all/align.d
index 9fcd6c0466800e03dde6a2b6aeb37246ed096487..c701f25bfcc998373f7b6b9cb579a7d12b72fc3e 100644 (file)
--- a/gas/testsuite/gas/all/align.d
+++ b/gas/testsuite/gas/all/align.d
@@ -4,7 +4,7 @@
 # even if the user requested that they filled with zeros.
 # RISC-V handles alignment via relaxation and therefor won't have object files
 # with the expected alignment.
-#notarget: m32c-* riscv*-* rx-*
+#notarget: riscv*-* rx-*
 
 # Test the alignment pseudo-op.
 

diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index a91f8c29d2a799ccbb6e7d7e69d9b502ebfde965..abae8b15a6ee3fc0d694e51c4a3ff36bcf8a179e 100644 (file)
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -194,13 +194,7 @@ proc do_comment {} {
     if [all_ones $x1 $x2 $x3] then { pass $testname } else { fail $testname }
 }
 
-# m32c pads out sections, even empty ones.
-case $target_triplet in {
-    { m32c-*-* } { }
-    default {
-       do_comment
-    }
-}
+do_comment
 
 # This test checks the output of the -ag switch. It must detect at least
 # the name of the input file, output file, and options passed.

diff --git a/gas/testsuite/gas/all/incbin.d b/gas/testsuite/gas/all/incbin.d
index e0c7c44ae3645c5238dc553a39bd7aba4e70e320..62f6ae78103574c40faec9f399d02790e7d71904 100644 (file)
--- a/gas/testsuite/gas/all/incbin.d
+++ b/gas/testsuite/gas/all/incbin.d
@@ -1,7 +1,6 @@
 #as: -I$srcdir/$subdir
 #objdump: -s -j .text
 #name: incbin
-#notarget: m32c-*
 
 # Test the incbin pseudo-op
 

diff --git a/gas/testsuite/gas/elf/dwarf2-11.d b/gas/testsuite/gas/elf/dwarf2-11.d
index 2a5ec84d4d50ec1679bb144814df207b188e80bf..cdaa4f10b6b99bdd434a8b23e0b1846fd7b5498d 100644 (file)
--- a/gas/testsuite/gas/elf/dwarf2-11.d
+++ b/gas/testsuite/gas/elf/dwarf2-11.d
@@ -4,7 +4,7 @@
 # The am33 avr cr16 crx ft32 mn10 msp430 nds32 pru rl78 and xtensa targets do not evaluate the subtraction of symbols at assembly time.
 # The riscv targets do not support the subtraction of symbols.
 # The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
-#notarget: am3*-* avr-* cr16-* crx-* ft32*-* m32c-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
+#notarget: am3*-* avr-* cr16-* crx-* ft32*-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* tile*-* xtensa-*
 
 Contents of the \.debug_line section:
 

diff --git a/gas/testsuite/gas/macros/semi.d b/gas/testsuite/gas/macros/semi.d
index 66c452adab95408b0911b5db74376f75e11e7bc0..102d732ad6eb65ee5dcb75cef460c4ddce6e9394 100644 (file)
--- a/gas/testsuite/gas/macros/semi.d
+++ b/gas/testsuite/gas/macros/semi.d
@@ -1,6 +1,5 @@
 #objdump: -s -j .text
 #name: semi
-#notarget: m32c-*
 
 .*: .*
 

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 722e65669cc10fc4ce557ee4e45d0bd5dcd5004b..d62a2c4d5f018c8d1387d70120cebd46cf9f33b2 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,8 @@
+2019-05-04  Alan Modra  <amodra@gmail.com>
+
+       * testsuite/ld-scripts/fill.d: Don't xfail m32c
+       * testsuite/ld-scripts/fill16.d: Likewise.
+
 2019-05-04  Alan Modra  <amodra@gmail.com>
 
        PR 24511

diff --git a/ld/testsuite/ld-scripts/fill.d b/ld/testsuite/ld-scripts/fill.d
index 4a263497a8b115e95e0015852e91e8895a840554..54715c58d8e43f903dc9f29c029ffda03679a080 100644 (file)
--- a/ld/testsuite/ld-scripts/fill.d
+++ b/ld/testsuite/ld-scripts/fill.d
@@ -6,7 +6,7 @@
 #skip: ia64-*-* mips*-*-freebsd* mips*-*-gnu* mips*-*-irix* mips*-*-kfreebsd*
 #skip: mips*-*-linux* mips*-*-netbsd* mips*-*-openbsd* mips*-*-sysv4*
 #skip: tilegx*-*-* tilepro-*-* x86_64-*-cygwin x86_64-*-mingw* x86_64-*-pe*
-#xfail: alpha*-*-*ecoff m32c-*-* sh-*-pe sparc*-*-coff
+#xfail: alpha*-*-*ecoff sh-*-pe sparc*-*-coff
 #xfail: tic30-*-coff tic4x-*-* tic54x-*-* z8k-*-*
 #
 # See also fill16.d.  We use `skip' for configurations unsupported
@@ -16,7 +16,6 @@
 #
 # alpha-linuxecoff pads out code to 16 bytes.
 # ia64 aligns code to minimum 16 bytes.
-# m32c pads out code sections with 4 NOPs (see `m32c_md_end').
 # mips aligns to minimum 16 bytes (except for bare-metal ELF and VxWorks).
 # sh-pe pads out code sections to 16 bytes
 # sparc-coff aligns to 8 bytes

diff --git a/ld/testsuite/ld-scripts/fill16.d b/ld/testsuite/ld-scripts/fill16.d
index 693b80c5f1ce9ffed19d63ec1a59454f781f26e0..2f3e0fd26db5ed43ee5f6d6b2617fe39d5c2a63a 100644 (file)
--- a/ld/testsuite/ld-scripts/fill16.d
+++ b/ld/testsuite/ld-scripts/fill16.d
@@ -4,7 +4,7 @@
 #ld: -T fill.t
 #objdump: -s -j .text
 #skip: arm-*-coff i[3-7]86-*-coff
-#xfail: alpha*-*-*ecoff m32c-*-* sh-*-pe sparc*-*-coff
+#xfail: alpha*-*-*ecoff sh-*-pe sparc*-*-coff
 #xfail: tic30-*-coff tic4x-*-* tic54x-*-* z8k-*-*
 #
 # See also fill.d.  We use `skip' for configurations unsupported
@@ -15,7 +15,6 @@
 # alpha-linuxecoff pads out code to 16 bytes.
 # arm-coff always aligns code to 4 bytes.
 # i386-coff always aligns code to 4 bytes.
-# m32c pads out code sections with 4 NOPs (see `m32c_md_end').
 # sh-pe pads out code sections to 16 bytes
 # sparc-coff aligns to 8 bytes
 # tic30-coff aligns to 2 bytes