include/opcode/

	* mips.h (mips_opcode): Add the exclusions field.
	(OPCODE_IS_MEMBER): Remove macro.
	(cpu_is_member): New inline function.
	(opcode_is_member): Likewise.

	opcodes/
	* micromips-opc.c (micromips_opcodes): Update comment.
	* mips-opc.c (mips_builtin_opcodes): Likewise.  Mark coprocessor
	instructions for IOCT as appropriate.
	* mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
	opcode_is_member.
	* configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
	the result of a check for the -Wno-missing-field-initializers
	GCC option.
	* Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
	(mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
	compilation.
	(mips16-opc.lo): Likewise.
	(micromips-opc.lo): Likewise.
	* aclocal.m4: Regenerate.
	* configure: Regenerate.
	* Makefile.in: Regenerate.

	gas/
	* config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
	(is_opcode_valid): Remove coprocessor instruction exclusions.
	Replace OPCODE_IS_MEMBER with opcode_is_member.
	(is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
	opcode_is_member.
	(macro): Remove coprocessor instruction exclusions.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9f07d52448233256a9c50fcbb19d9c11ddb4ca7e..fb6ac642f36dfbe444d8eb98a5ae87cf52f14915 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2012-08-13  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
+       (is_opcode_valid): Remove coprocessor instruction exclusions.
+       Replace OPCODE_IS_MEMBER with opcode_is_member.
+       (is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
+       opcode_is_member.
+       (macro): Remove coprocessor instruction exclusions.
+
 2012-08-13  Maciej W. Rozycki  <macro@codesourcery.com>
 
        * config/tc-mips.c (s_cpload, s_cpsetup): Fail if MIPS16 mode.

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 53e10eac8a7831eeb545bdfd974c60793ea988fb..9e2183cbab708c86b87f7e6e3bbffa56cb94e416 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -505,11 +505,6 @@ static int mips_32bitmode = 0;
 /* True if CPU has seq/sne and seqi/snei instructions.  */
 #define CPU_HAS_SEQ(CPU)       (CPU_IS_OCTEON (CPU))
 
-/* True if CPU does not implement the all the coprocessor insns.  For these
-   CPUs only those COP insns are accepted that are explicitly marked to be
-   available on the CPU.  ISA membership for COP insns is ignored.  */
-#define NO_ISA_COP(CPU)                (CPU_IS_OCTEON (CPU))
-
 /* True if mflo and mfhi can be immediately followed by instructions
    which write to the HI and LO registers.
 
@@ -580,15 +575,6 @@ static int mips_32bitmode = 0;
 #define MF_HILO_INSN(PINFO) \
   ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
 
-/* Returns true for a (non floating-point) coprocessor instruction.  Reading
-   or writing the condition code is only possible on the coprocessors and
-   these insns are not marked with INSN_COP.  Thus for these insns use the
-   condition-code flags.  */
-#define COP_INSN(PINFO)                                                        \
-  (PINFO != INSN_MACRO                                                 \
-   && ((PINFO) & (FP_S | FP_D)) == 0                                   \
-   && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
-
 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
    has been selected.  This implies, in particular, that addresses of text
    labels have their LSB set.  */
@@ -2221,13 +2207,7 @@ is_opcode_valid (const struct mips_opcode *mo)
   if (mips_opts.ase_mcu)
     isa |= INSN_MCU;
 
-  /* Don't accept instructions based on the ISA if the CPU does not implement
-     all the coprocessor insns. */
-  if (NO_ISA_COP (mips_opts.arch)
-      && COP_INSN (mo->pinfo))
-    isa = 0;
-
-  if (!OPCODE_IS_MEMBER (mo, isa, mips_opts.arch))
+  if (!opcode_is_member (mo, isa, mips_opts.arch))
     return FALSE;
 
   /* Check whether the instruction or macro requires single-precision or
@@ -2259,7 +2239,7 @@ is_opcode_valid (const struct mips_opcode *mo)
 static bfd_boolean
 is_opcode_valid_16 (const struct mips_opcode *mo)
 {
-  return OPCODE_IS_MEMBER (mo, mips_opts.isa, mips_opts.arch) ? TRUE : FALSE;
+  return opcode_is_member (mo, mips_opts.isa, mips_opts.arch);
 }
 
 /* Return TRUE if the size of the microMIPS opcode MO matches one
@@ -8265,15 +8245,6 @@ macro (struct mips_cl_insn *ip)
       tempreg = AT;
       used_at = 1;
     ld_noat:
-      if (coproc
-         && NO_ISA_COP (mips_opts.arch)
-         && (ip->insn_mo->pinfo2 & (INSN2_M_FP_S | INSN2_M_FP_D)) == 0)
-       {
-         as_bad (_("Opcode not supported on this processor: %s"),
-                 mips_cpu_info_from_arch (mips_opts.arch)->name);
-         break;
-       }
-
       if (offset_expr.X_op != O_constant
          && offset_expr.X_op != O_symbol)
        {
@@ -9199,14 +9170,6 @@ macro (struct mips_cl_insn *ip)
       s = "c3";
     copz:
       gas_assert (!mips_opts.micromips);
-      if (NO_ISA_COP (mips_opts.arch)
-         && (ip->insn_mo->pinfo2 & INSN2_M_FP_S) == 0)
-       {
-         as_bad (_("Opcode not supported on this processor: %s"),
-                 mips_cpu_info_from_arch (mips_opts.arch)->name);
-         break;
-       }
-
       /* For now we just do C (same as Cz).  The parameter will be
          stored in insn_opcode by mips_ip.  */
       macro_build (NULL, s, "C", ip->insn_opcode);

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 1091973b2b1362a9471031dd2367e4ad784280d3..94f9b3074cf6adc0cf1919e9d9debd8269b474ac 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,11 @@
+2012-08-13  Richard Sandiford  <rdsandiford@googlemail.com>
+            Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * mips.h (mips_opcode): Add the exclusions field.
+       (OPCODE_IS_MEMBER): Remove macro.
+       (cpu_is_member): New inline function.
+       (opcode_is_member): Likewise.
+
 2012-07-31  Chao-Ying Fu  <fu@mips.com>
             Catherine Moore  <clm@codesourcery.com>
             Maciej W. Rozycki  <macro@codesourcery.com>

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 857fc7173deb1e782108fac587787c9763786884..5691ac535b28430643532ed238a2f2950c1173fc 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -25,6 +25,8 @@
 #ifndef _MIPS_H_
 #define _MIPS_H_
 
+#include "bfd.h"
+
 /* These are bit masks and shift counts to use to access the various
    fields of an instruction.  To retrieve the X field of an
    instruction, use the expression
@@ -353,6 +355,9 @@ struct mips_opcode
   /* A collection of bits describing the instruction sets of which this
      instruction or macro is a member. */
   unsigned long membership;
+  /* A collection of bits describing the instruction sets of which this
+     instruction or macro is not a member.  */
+  unsigned long exclusions;
 };
 
 /* These are the characters which may appear in the args field of an
@@ -829,46 +834,102 @@ static const unsigned int mips_isa_table[] =
 #define CPU_OCTEON2    6502
 #define CPU_XLR        887682          /* decimal 'XLR'   */
 
+/* Return true if the given CPU is included in INSN_* mask MASK.  */
+
+static inline bfd_boolean
+cpu_is_member (int cpu, unsigned int mask)
+{
+  switch (cpu)
+    {
+    case CPU_R4650:
+    case CPU_RM7000:
+    case CPU_RM9000:
+      return (mask & INSN_4650) != 0;
+
+    case CPU_R4010:
+      return (mask & INSN_4010) != 0;
+
+    case CPU_VR4100:
+      return (mask & INSN_4100) != 0;
+
+    case CPU_R3900:
+      return (mask & INSN_3900) != 0;
+
+    case CPU_R10000:
+    case CPU_R12000:
+    case CPU_R14000:
+    case CPU_R16000:
+      return (mask & INSN_10000) != 0;
+
+    case CPU_SB1:
+      return (mask & INSN_SB1) != 0;
+
+    case CPU_R4111:
+      return (mask & INSN_4111) != 0;
+
+    case CPU_VR4120:
+      return (mask & INSN_4120) != 0;
+
+    case CPU_VR5400:
+      return (mask & INSN_5400) != 0;
+
+    case CPU_VR5500:
+      return (mask & INSN_5500) != 0;
+
+    case CPU_LOONGSON_2E:
+      return (mask & INSN_LOONGSON_2E) != 0;
+
+    case CPU_LOONGSON_2F:
+      return (mask & INSN_LOONGSON_2F) != 0;
+
+    case CPU_LOONGSON_3A:
+      return (mask & INSN_LOONGSON_3A) != 0;
+
+    case CPU_OCTEON:
+      return (mask & INSN_OCTEON) != 0;
+
+    case CPU_OCTEONP:
+      return (mask & INSN_OCTEONP) != 0;
+
+    case CPU_OCTEON2:
+      return (mask & INSN_OCTEON2) != 0;
+
+    case CPU_XLR:
+      return (mask & INSN_XLR) != 0;
+
+    default:
+      return FALSE;
+    }
+}
+
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
-   test, or zero if no CPU specific ISA test is desired.  */
-
-#define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
-    (((isa & INSN_ISA_MASK) != 0                                        \
-      && ((insn)->membership & INSN_ISA_MASK) != 0                      \
-      && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >>                \
-           (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0)       \
-     || ((isa & ~INSN_ISA_MASK)                                         \
-          & ((insn)->membership & ~INSN_ISA_MASK)) != 0                 \
-     || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)    \
-     || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)   \
-     || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)   \
-     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)    \
-     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)   \
-     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)    \
-     || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000  \
-         || cpu == CPU_R16000)                                         \
-        && ((insn)->membership & INSN_10000) != 0)                     \
-     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)       \
-     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)    \
-     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)   \
-     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)   \
-     || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)   \
-     || (cpu == CPU_LOONGSON_2E                                         \
-         && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
-     || (cpu == CPU_LOONGSON_2F                                         \
-         && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
-     || (cpu == CPU_LOONGSON_3A                                         \
-         && ((insn)->membership & INSN_LOONGSON_3A) != 0)               \
-     || (cpu == CPU_OCTEON                                             \
-        && ((insn)->membership & INSN_OCTEON) != 0)                    \
-     || (cpu == CPU_OCTEONP                                            \
-        && ((insn)->membership & INSN_OCTEONP) != 0)                   \
-     || (cpu == CPU_OCTEON2                                            \
-        && ((insn)->membership & INSN_OCTEON2) != 0)                   \
-     || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \
-     || 0)     /* Please keep this term for easier source merging.  */
+   test, or zero if no CPU specific ISA test is desired.  Return true
+   if instruction INSN is available to the given ISA and CPU. */
+
+static inline bfd_boolean
+opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
+{
+  if (!cpu_is_member (cpu, insn->exclusions))
+    {
+      /* Test for ISA level compatibility.  */
+      if ((isa & INSN_ISA_MASK) != 0
+         && (insn->membership & INSN_ISA_MASK) != 0
+         && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
+              >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
+       return TRUE;
+
+      /* Test for ASE compatibility.  */
+      if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
+       return TRUE;
+
+      /* Test for processor-specific extensions.  */
+      if (cpu_is_member (cpu, insn->membership))
+       return TRUE;
+    }
+  return FALSE;
+}
 
 /* This is a list of macro expanded instructions.
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 76e8a6a33fe588c96d8c67aaf96d6c8997989fe8..4379c1c8bb190e1400e991534f2b3f4d1060abb9 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,22 @@
+2012-08-13  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * micromips-opc.c (micromips_opcodes): Update comment.
+       * mips-opc.c (mips_builtin_opcodes): Likewise.  Mark coprocessor
+       instructions for IOCT as appropriate.
+       * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
+       opcode_is_member.
+       * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
+       the result of a check for the -Wno-missing-field-initializers
+       GCC option.
+       * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
+       (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
+       compilation.
+       (mips16-opc.lo): Likewise.
+       (micromips-opc.lo): Likewise.
+       * aclocal.m4: Regenerate.
+       * configure: Regenerate.
+       * Makefile.in: Regenerate.
+
 2012-08-11  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 
        PR gas/14423

diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index a43aa0d1a1f339684aa065108339fe4fb39cbd7c..f76776ccf1dc7de0307a351018cd3c3d0e857985 100644 (file)
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -11,6 +11,7 @@ BFDDIR = $(srcdir)/../bfd
 
 WARN_CFLAGS = @WARN_CFLAGS@
 NO_WERROR = @NO_WERROR@
+NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
 AM_CFLAGS = $(WARN_CFLAGS)
 
 COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(INCLUDES) $(AM_CPPFLAGS) \
@@ -528,6 +529,15 @@ ia64-opc.lo: $(srcdir)/ia64-asmtab.c
 $(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
        ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
 
+micromips-opc.lo: micromips-opc.c
+       $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips-opc.lo: mips-opc.c
+       $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips16-opc.lo: mips16-opc.c
+       $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
 $(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
        ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
 

diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index f5035ea4ce6c871d635d478fa96408a0cad7387f..f51c98d328198efde36da54294d3d4105bf77c3d 100644 (file)
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -54,6 +54,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \
        $(top_srcdir)/../config/override.m4 \
        $(top_srcdir)/../config/po.m4 \
        $(top_srcdir)/../config/progtest.m4 \
+       $(top_srcdir)/../config/warnings.m4 \
        $(top_srcdir)/../libtool.m4 $(top_srcdir)/../ltoptions.m4 \
        $(top_srcdir)/../ltsugar.m4 $(top_srcdir)/../ltversion.m4 \
        $(top_srcdir)/../lt~obsolete.m4 $(top_srcdir)/configure.in
@@ -195,6 +196,7 @@ MSGMERGE = @MSGMERGE@
 NM = @NM@
 NMEDIT = @NMEDIT@
 NO_WERROR = @NO_WERROR@
+NO_WMISSING_FIELD_INITIALIZERS = @NO_WMISSING_FIELD_INITIALIZERS@
 OBJDUMP = @OBJDUMP@
 OBJEXT = @OBJEXT@
 OTOOL = @OTOOL@
@@ -1377,6 +1379,15 @@ ia64-opc.lo: $(srcdir)/ia64-asmtab.c
 $(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
        ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
 
+micromips-opc.lo: micromips-opc.c
+       $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips-opc.lo: mips-opc.c
+       $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
+mips16-opc.lo: mips16-opc.c
+       $(LTCOMPILE) $(NO_WMISSING_FIELD_INITIALIZERS) -c -o $@ $<
+
 $(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
        ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
 

diff --git a/opcodes/aclocal.m4 b/opcodes/aclocal.m4
index df10cc09c4c4e6842aa584982655b046805e7e1e..0f36783e6536b595bddd85b6d45ba4c325419475 100644 (file)
--- a/opcodes/aclocal.m4
+++ b/opcodes/aclocal.m4
@@ -978,6 +978,7 @@ m4_include([../config/nls.m4])
 m4_include([../config/override.m4])
 m4_include([../config/po.m4])
 m4_include([../config/progtest.m4])
+m4_include([../config/warnings.m4])
 m4_include([../libtool.m4])
 m4_include([../ltoptions.m4])
 m4_include([../ltsugar.m4])

diff --git a/opcodes/configure b/opcodes/configure
index 6d069de427bbaa2409fe397f1a69ad4e841caa45..9b6cc7d6a6cd2fcd5ad606e9270e9123c7bd101c 100755 (executable)
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -640,6 +640,7 @@ INSTALL_LIBBFD_TRUE
 MAINT
 MAINTAINER_MODE_FALSE
 MAINTAINER_MODE_TRUE
+NO_WMISSING_FIELD_INITIALIZERS
 NO_WERROR
 WARN_CFLAGS
 OTOOL64
@@ -11134,7 +11135,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 11137 "configure"
+#line 11138 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -11240,7 +11241,7 @@ else
   lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
   lt_status=$lt_dlunknown
   cat > conftest.$ac_ext <<_LT_EOF
-#line 11243 "configure"
+#line 11244 "configure"
 #include "confdefs.h"
 
 #if HAVE_DLFCN_H
@@ -11561,6 +11562,51 @@ fi
 
 
 
+NO_WMISSING_FIELD_INITIALIZERS=
+save_CFLAGS="$CFLAGS"
+for real_option in -Wno-missing-field-initializers; do
+  # Do the check with the no- prefix removed since gcc silently
+  # accepts any -Wno-* option on purpose
+  case $real_option in
+    -Wno-*) option=-W`expr x$real_option : 'x-Wno-\(.*\)'` ;;
+    *) option=$real_option ;;
+  esac
+  as_acx_Woption=`$as_echo "acx_cv_prog_cc_warning_$option" | $as_tr_sh`
+
+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC supports $option" >&5
+$as_echo_n "checking whether $CC supports $option... " >&6; }
+if { as_var=$as_acx_Woption; eval "test \"\${$as_var+set}\" = set"; }; then :
+  $as_echo_n "(cached) " >&6
+else
+  CFLAGS="$option"
+    cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  eval "$as_acx_Woption=yes"
+else
+  eval "$as_acx_Woption=no"
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+
+fi
+eval ac_res=\$$as_acx_Woption
+              { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5
+$as_echo "$ac_res" >&6; }
+  if test `eval 'as_val=${'$as_acx_Woption'};$as_echo "$as_val"'` = yes; then :
+  NO_WMISSING_FIELD_INITIALIZERS="$NO_WMISSING_FIELD_INITIALIZERS${NO_WMISSING_FIELD_INITIALIZERS:+ }$real_option"
+fi
+  done
+CFLAGS="$save_CFLAGS"
+
 
 ac_config_headers="$ac_config_headers config.h:config.in"
 

diff --git a/opcodes/configure.in b/opcodes/configure.in
index d3e2f922f950f809121264c40a37c2cba061dc55..486ffa0581eab005feab4e3e3b6d5143e36239cd 100644 (file)
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -42,6 +42,8 @@ AC_ARG_ENABLE(targets,
 esac])dnl
 
 AM_BINUTILS_WARNINGS
+ACX_PROG_CC_WARNING_OPTS([-Wno-missing-field-initializers],
+                        [NO_WMISSING_FIELD_INITIALIZERS])
 
 AC_CONFIG_HEADERS(config.h:config.in)
 

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index a15982dfd51055378dc839bcd60eeab5ea00ffd9..b4982cc5e0dd3f79ec2fb6183c3d7acc9bf05a17 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -115,7 +115,7 @@ const struct mips_opcode micromips_opcodes[] =
 /* These instructions appear first so that the disassembler will find
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
-/* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership */
+/* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership,     [exclusions] */
 {"pref",    "k,~(b)",  0x60002000, 0xfc00f000, RD_b,                   0,              I1      },
 {"pref",    "k,o(b)",  0,    (int) M_PREF_OB,  INSN_MACRO,             0,              I1      },
 {"pref",    "k,A(b)",  0,    (int) M_PREF_AB,  INSN_MACRO,             0,              I1      },

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 8f8a5d7165538a2d820236872e46a6b86baa72bf..c338960272486aebc88fdc9c2842ed094f8cd75a 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1562,7 +1562,7 @@ print_insn_mips (bfd_vma memaddr,
              const char *d;
 
              /* We always allow to disassemble the jalx instruction.  */
-             if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
+             if (!opcode_is_member (op, mips_isa, mips_processor)
                  && strcmp (op->name, "jalx"))
                continue;
 

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 93238d43a5c6c242d31db6a6c610f471e34609e6..44cfad2bd73d6d5023f0ae7ad280b57f4b478cd0 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -197,7 +197,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* These instructions appear first so that the disassembler will find
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
-/* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership */
+/* name,    args,      match,      mask,       pinfo,                  pinfo2,         membership,     [exclusions] */
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  0,              I4_32|G3        },
 {"pref",    "k,A(b)",  0,    (int) M_PREF_AB,  INSN_MACRO,             0,              I4_32|G3        },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,         0,              I4_33   },
@@ -593,27 +593,27 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3_33   },
 {"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
 {"ceil.w.s", "D,S",    0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
-{"cfc0",    "t,G",     0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
+{"cfc0",    "t,G",     0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1,             IOCT|IOCTP|IOCT2        },
 {"cfc1",    "t,G",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
 {"cfc1",    "t,S",     0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
 /* cfc2 is at the bottom of the table.  */
 /* cfc3 is at the bottom of the table.  */
 {"cftc1",   "d,E",     0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
 {"cftc1",   "d,T",     0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
-{"cftc2",   "d,E",     0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
+{"cftc2",   "d,E",     0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32,           IOCT|IOCTP|IOCT2        },
 {"cins32",  "t,r,+p,+S",0x70000033, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
 {"cins",    "t,r,+P,+S",0x70000033, 0xfc00003f, WR_t|RD_s,             0,              IOCT    }, /* cins32 */
 {"cins",    "t,r,+p,+s",0x70000032, 0xfc00003f, WR_t|RD_s,             0,              IOCT    },
 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,        0,              I32|N55 },
 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,        0,              I32|N55 },
-{"ctc0",    "t,G",     0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
+{"ctc0",    "t,G",     0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
 {"ctc1",    "t,G",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
 {"ctc1",    "t,S",     0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
 /* ctc2 is at the bottom of the table.  */
 /* ctc3 is at the bottom of the table.  */
 {"cttc1",   "t,g",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
 {"cttc1",   "t,S",     0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
-{"cttc2",   "t,g",     0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
+{"cttc2",   "t,g",     0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32,           IOCT|IOCTP|IOCT2        },
 {"cvt.d.l", "D,S",     0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3_33   },
 {"cvt.d.s", "D,S",     0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
 {"cvt.d.w", "D,S",     0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
@@ -658,8 +658,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3      },
 {"ddivu",   "d,v,t",   0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
 {"ddivu",   "d,v,I",   0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
-{"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33|IOCT},
-{"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33|IOCT},
+{"di",      "",                0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
+{"di",      "t",       0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
 {"dins",    "t,r,I,+I",        0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,                    0,              I65     },
 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,                    0,              I65     },
@@ -694,14 +694,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmaccu",  "d,s,t",   0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
 {"dmaccus", "d,s,t",   0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,             N411    },
-{"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3|IOCT },
-{"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64|IOCT},
-{"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I64|IOCT},
+{"dmfc0",   "t,G",     0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
+{"dmfc0",   "t,+D",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
+{"dmfc0",   "t,G,H",   0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
 {"dmt",     "",                0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
 {"dmt",     "t",       0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
-{"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3|IOCT },
-{"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64|IOCT},
-{"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I64|IOCT},
+{"dmtc0",   "t,G",     0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
+{"dmtc0",   "t,+D",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
+{"dmtc0",   "t,G,H",   0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
 {"dmfc1",   "t,S",     0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,             I3      },
 {"dmtc1",   "t,S",     0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
@@ -773,8 +773,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
 {"dvpe",    "",                0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
 {"dvpe",    "t",       0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
-{"ei",      "",                0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33|IOCT},
-{"ei",      "t",       0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33|IOCT},
+{"ei",      "",                0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
+{"ei",      "t",       0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
 {"emt",     "",                0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
 {"emt",     "t",       0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
 {"eret",    "",         0x42000018, 0xffffffff, NODS,                  0,              I3_32   },
@@ -858,10 +858,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"l.d",     "T,o(b)",  0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      }, /* ldc1 */
 {"l.d",     "T,o(b)",  0,    (int) M_L_DOB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
 {"l.d",     "T,A(b)",  0,    (int) M_L_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
-{"ldc2",    "E,o(b)",  0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
-{"ldc2",    "E,A(b)",  0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2      },
-{"ldc3",    "E,o(b)",  0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
-{"ldc3",    "E,A(b)",  0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2      },
+{"ldc2",    "E,o(b)",  0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2,             IOCT|IOCTP|IOCT2        },
+{"ldc2",    "E,A(b)",  0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2,             IOCT|IOCTP|IOCT2        },
+{"ldc3",    "E,o(b)",  0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2,             IOCT|IOCTP|IOCT2        },
+{"ldc3",    "E,A(b)",  0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2,             IOCT|IOCTP|IOCT2        },
 {"ldl",            "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
 {"ldl",            "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
 {"ldr",            "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
@@ -884,18 +884,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"luxc1",   "D,t(b)",  0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5_33|N55},
 {"lw",      "t,o(b)",  0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lw",      "t,A(b)",  0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
-{"lwc0",    "E,o(b)",  0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
-{"lwc0",    "E,A(b)",  0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1      },
+{"lwc0",    "E,o(b)",  0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"lwc0",    "E,A(b)",  0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
 {"lwc1",    "T,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
 {"lwc1",    "E,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
 {"lwc1",    "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"lwc1",    "E,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"l.s",     "T,o(b)",  0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
 {"l.s",     "T,A(b)",  0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
-{"lwc2",    "E,o(b)",  0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
-{"lwc2",    "E,A(b)",  0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1      },
-{"lwc3",    "E,o(b)",  0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
-{"lwc3",    "E,A(b)",  0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1      },
+{"lwc2",    "E,o(b)",  0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"lwc2",    "E,A(b)",  0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
+{"lwc3",    "E,o(b)",  0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"lwc3",    "E,A(b)",  0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
 {"lwl",     "t,o(b)",  0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lwl",     "t,A(b)",  0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1      },
 {"lcache",  "t,o(b)",  0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
@@ -958,20 +958,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mftc0",   "d,E,H",   0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
 {"mftc1",   "d,T",     0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
 {"mftc1",   "d,E",     0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
-{"mftc2",   "d,E",     0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
+{"mftc2",   "d,E",     0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32,           IOCT|IOCTP|IOCT2        },
 {"mftdsp",  "d",       0x41100021, 0xffff07ff, TRAP|WR_d,              0,              MT32    },
 {"mftgpr",  "d,t",     0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
 {"mfthc1",  "d,T",     0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
 {"mfthc1",  "d,E",     0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
-{"mfthc2",  "d,E",     0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
+{"mfthc2",  "d,E",     0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32,           IOCT|IOCTP|IOCT2        },
 {"mfthi",   "d",       0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
 {"mfthi",   "d,*",     0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
 {"mftlo",   "d",       0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
 {"mftlo",   "d,*",     0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,            0,              MT32    },
-{"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1|IOCT },
-{"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32|IOCT},
-{"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,        0,              I32|IOCT},
+{"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
+{"mfc0",    "t,+D",0x40000000, 0xffe007f8,     LCD|WR_t|RD_C0,         0,              I32     },
+{"mfc0",    "t,G,H",   0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
 {"mfc1",    "t,S",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfc1",    "t,G",     0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
 {"mfhc1",   "t,S",     0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
@@ -1050,9 +1050,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msubu",   "7,s,t",   0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
 {"mtpc",    "t,P",     0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
 {"mtps",    "t,P",     0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
-{"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1|IOCT },
-{"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32|IOCT},
-{"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,             I32|IOCT},
+{"mtc0",    "t,G",     0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
+{"mtc0",    "t,+D",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
+{"mtc0",    "t,G,H",   0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
 {"mtc1",    "t,S",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mtc1",    "t,G",     0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
 {"mthc1",   "t,S",     0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
@@ -1078,14 +1078,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mttc0",   "t,G,H",   0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
 {"mttc1",   "t,S",     0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
 {"mttc1",   "t,G",     0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
-{"mttc2",   "t,g",     0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
+{"mttc2",   "t,g",     0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32,           IOCT|IOCTP|IOCT2        },
 {"mttacx",  "t",       0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
 {"mttacx",  "t,&",     0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
 {"mttdsp",  "t",       0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              MT32    },
 {"mttgpr",  "t,d",     0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
 {"mtthc1",  "t,S",     0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
 {"mtthc1",  "t,G",     0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
-{"mtthc2",  "t,g",     0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
+{"mtthc2",  "t,g",     0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32,           IOCT|IOCTP|IOCT2        },
 {"mtthi",   "t",       0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
 {"mtthi",   "t,&",     0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
 {"mttlo",   "t",       0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
@@ -1303,10 +1303,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
 {"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2      },
 {"sdc1",    "E,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2      },
-{"sdc2",    "E,o(b)",  0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2      },
-{"sdc2",    "E,A(b)",  0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2      },
-{"sdc3",    "E,o(b)",  0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2      },
-{"sdc3",    "E,A(b)",  0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2      },
+{"sdc2",    "E,o(b)",  0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2,             IOCT|IOCTP|IOCT2        },
+{"sdc2",    "E,A(b)",  0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2,             IOCT|IOCTP|IOCT2        },
+{"sdc3",    "E,o(b)",  0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2,             IOCT|IOCTP|IOCT2        },
+{"sdc3",    "E,A(b)",  0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2,             IOCT|IOCTP|IOCT2        },
 {"s.d",     "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
 {"s.d",     "T,o(b)",  0,    (int) M_S_DOB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
 {"s.d",     "T,A(b)",  0,    (int) M_S_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1      },
@@ -1428,18 +1428,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"swapw",   "t,b",     0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
 {"swapwu",  "t,b",     0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
 {"swapd",   "t,b",     0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b,      0,              XLR     },
-{"swc0",    "E,o(b)",  0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1      },
-{"swc0",    "E,A(b)",  0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1      },
+{"swc0",    "E,o(b)",  0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1,             IOCT|IOCTP|IOCT2        },
+{"swc0",    "E,A(b)",  0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
 {"swc1",    "T,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
 {"swc1",    "E,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
 {"swc1",    "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"swc1",    "E,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
 {"s.s",     "T,o(b)",  0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
 {"s.s",     "T,A(b)",  0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1      },
-{"swc2",    "E,o(b)",  0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1      },
-{"swc2",    "E,A(b)",  0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1      },
-{"swc3",    "E,o(b)",  0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1      },
-{"swc3",    "E,A(b)",  0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1      },
+{"swc2",    "E,o(b)",  0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1,             IOCT|IOCTP|IOCT2        },
+{"swc2",    "E,A(b)",  0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
+{"swc3",    "E,o(b)",  0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1,             IOCT|IOCTP|IOCT2        },
+{"swc3",    "E,A(b)",  0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
 {"swl",     "t,o(b)",  0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
 {"swl",     "t,A(b)",  0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1      },
 {"scache",  "t,o(b)",  0xa8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
@@ -1618,47 +1618,47 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
-{"bc2f",    "p",       0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
-{"bc2f",    "N,p",     0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32     },
-{"bc2fl",   "p",       0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
-{"bc2fl",   "N,p",     0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32     },
-{"bc2t",    "p",       0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
-{"bc2t",    "N,p",     0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32     },
-{"bc2tl",   "p",       0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
-{"bc2tl",   "N,p",     0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
-{"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
-{"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
+{"bc2f",    "p",       0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
+{"bc2f",    "N,p",     0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32,            IOCT|IOCTP|IOCT2        },
+{"bc2fl",   "p",       0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
+{"bc2fl",   "N,p",     0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32,            IOCT|IOCTP|IOCT2        },
+{"bc2t",    "p",       0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
+{"bc2t",    "N,p",     0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32,            IOCT|IOCTP|IOCT2        },
+{"bc2tl",   "p",       0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
+{"bc2tl",   "N,p",     0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32,            IOCT|IOCTP|IOCT2        },
+{"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
 {"dmfc2",   "t,i",     0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,              IOCT    },
-{"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
-{"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
+{"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3,             IOCT|IOCTP|IOCT2        },
+{"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64,            IOCT|IOCTP|IOCT2        },
 {"dmtc2",   "t,i",     0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              IOCT    },
-{"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
-{"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
-{"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
-{"mfc2",    "t,G,H",   0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
-{"mfhc2",   "t,G",     0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },
-{"mfhc2",   "t,G,H",   0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33     },
-{"mfhc2",   "t,i",     0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33     },
-{"mtc2",    "t,G",     0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1      },
-{"mtc2",    "t,G,H",   0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32     },
-{"mthc2",   "t,G",     0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
-{"mthc2",   "t,G,H",   0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
-{"mthc2",   "t,i",     0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
+{"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3,             IOCT|IOCTP|IOCT2        },
+{"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64,            IOCT|IOCTP|IOCT2        },
+{"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"mfc2",    "t,G,H",   0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32,            IOCT|IOCTP|IOCT2        },
+{"mfhc2",   "t,G",     0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33,            IOCT|IOCTP|IOCT2        },
+{"mfhc2",   "t,G,H",   0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33,            IOCT|IOCTP|IOCT2        },
+{"mfhc2",   "t,i",     0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33,            IOCT|IOCTP|IOCT2        },
+{"mtc2",    "t,G",     0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1,             IOCT|IOCTP|IOCT2        },
+{"mtc2",    "t,G,H",   0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32,            IOCT|IOCTP|IOCT2        },
+{"mthc2",   "t,G",     0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33,            IOCT|IOCTP|IOCT2        },
+{"mthc2",   "t,G,H",   0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33,            IOCT|IOCTP|IOCT2        },
+{"mthc2",   "t,i",     0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33,            IOCT|IOCTP|IOCT2        },
 
 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
    instructions, so they are here for the latters to take precedence.  */
-{"bc3f",    "p",       0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
-{"bc3fl",   "p",       0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
-{"bc3t",    "p",       0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
-{"bc3tl",   "p",       0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
-{"cfc3",    "t,G",     0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
-{"ctc3",    "t,G",     0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
-{"dmfc3",   "t,G",     0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3      },
-{"dmtc3",   "t,G",     0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3      },
-{"mfc3",    "t,G",     0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
-{"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,        0,              I32     },
-{"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
-{"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,             I32     },
+{"bc3f",    "p",       0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
+{"bc3fl",   "p",       0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
+{"bc3t",    "p",       0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
+{"bc3tl",   "p",       0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
+{"cfc3",    "t,G",     0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"ctc3",    "t,G",     0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"dmfc3",   "t,G",     0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3,             IOCT|IOCTP|IOCT2        },
+{"dmtc3",   "t,G",     0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3,             IOCT|IOCTP|IOCT2        },
+{"mfc3",    "t,G",     0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1,             IOCT|IOCTP|IOCT2        },
+{"mfc3",    "t,G,H",   0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32,            IOCT|IOCTP|IOCT2        },
+{"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1,             IOCT|IOCTP|IOCT2        },
+{"mtc3",    "t,G,H",   0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32,            IOCT|IOCTP|IOCT2        },
 
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
@@ -1945,10 +1945,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,    0,              D33     },
 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
-{"bc0f",    "p",       0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
-{"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
-{"bc0t",    "p",       0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
-{"bc0tl",   "p",       0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
+{"bc0f",    "p",       0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
+{"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
+{"bc0t",    "p",       0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1,             IOCT|IOCTP|IOCT2        },
+{"bc0tl",   "p",       0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3,          IOCT|IOCTP|IOCT2        },
 /* ST Microelectronics Loongson-2E and -2F.  */
 {"mult.g",     "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
 {"mult.g",     "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
@@ -2108,14 +2108,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the
    disassembler recognizes more specific versions first.  */
-{"c0",      "C",       0x42000000, 0xfe000000, CP,                     0,              I1      },
+{"c0",      "C",       0x42000000, 0xfe000000, CP,                     0,              I1,             IOCT|IOCTP|IOCT2        },
 {"c1",      "C",       0x46000000, 0xfe000000, FP_S,                   0,              I1      },
-{"c2",      "C",       0x4a000000, 0xfe000000, CP,                     0,              I1      },
-{"c3",      "C",       0x4e000000, 0xfe000000, CP,                     0,              I1      },
-{"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
+{"c2",      "C",       0x4a000000, 0xfe000000, CP,                     0,              I1,             IOCT|IOCTP|IOCT2        },
+{"c3",      "C",       0x4e000000, 0xfe000000, CP,                     0,              I1,             IOCT|IOCTP|IOCT2        },
+{"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
 {"cop1",     "C",      0,    (int) M_COP1,     INSN_MACRO,             INSN2_M_FP_S,   I1      },
-{"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
-{"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             0,              I1      }
+{"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
+{"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             0,              I1,             IOCT|IOCTP|IOCT2        },
 };
 
 #define MIPS_NUM_OPCODES \