* v850-opc.c (v850_operansd): 3-bit immediate for bit insns

        is unsigned.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f72326887e8dc627da4182eb190423f5b84150bc..430bc692d32ece9f3bab3dbb2f3ae0ff80c495a5 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,6 +1,9 @@
 start-sanitize-v850
 Fri Aug 23 00:27:01 1996  Jeffrey A Law  (law@cygnus.com)
 
+       * v850-opc.c (v850_operansd): 3-bit immediate for bit insns
+       is unsigned.
+
        * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and
        short store word (sst.w).
 

diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 78c769fdf8faefeee2a795317d67ee981d229ded..cf6f6cfb23afc486ffac9f4be96c4be93550a6a4 100644 (file)
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -62,7 +62,7 @@ const struct v850_operand v850_operands[] = {
 
 #define B3     (D22+1)
 /* The 3 bit immediate field in format 8 insn.  */
-  { 3, 11, 0, 0, V850_OPERAND_SIGNED },
+  { 3, 11, 0, 0, 0 },
 
 #define CCCC   (B3+1)
 /* The 4 bit condition code in a setf instruction */