x86, amd: Extend AMD northbridge caching code to support "Link Control" devices

"Link Control" devices (NB function 4) will be used by L3 cache
partitioning on family 0x15.

Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
Cc: <andreas.herrmann3@amd.com>
LKML-Reference: <1295881543-572552-4-git-send-email-hans.rosenfeld@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 64dc82ee19f00da98e796c81e767e677c56cf796..3e7070071d73b6548f564859c6d1fcb7087a8ce2 100644 (file)
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -26,6 +26,7 @@ extern void amd_get_nodes(struct bootnode *nodes);
 
 struct amd_northbridge {
        struct pci_dev *misc;
+       struct pci_dev *link;
 };
 
 struct amd_northbridge_info {

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index a4f394c8e0558b77d8f12c47f75839418965abef..4ae9a961c33c046ecb06a33ce3a54424481a88b5 100644 (file)
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -20,6 +20,11 @@ struct pci_device_id amd_nb_misc_ids[] = {
 };
 EXPORT_SYMBOL(amd_nb_misc_ids);
 
+static struct pci_device_id amd_nb_link_ids[] = {
+       { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_LINK) },
+       {}
+};
+
 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
        { 0x00, 0x18, 0x20 },
        { 0xff, 0x00, 0x20 },
@@ -45,7 +50,7 @@ int amd_cache_northbridges(void)
 {
        int i = 0;
        struct amd_northbridge *nb;
-       struct pci_dev *misc;
+       struct pci_dev *misc, *link;
 
        if (amd_nb_num())
                return 0;
@@ -64,10 +69,12 @@ int amd_cache_northbridges(void)
        amd_northbridges.nb = nb;
        amd_northbridges.num = i;
 
-       misc = NULL;
+       link = misc = NULL;
        for (i = 0; i != amd_nb_num(); i++) {
                node_to_amd_nb(i)->misc = misc =
                        next_northbridge(misc, amd_nb_misc_ids);
+               node_to_amd_nb(i)->link = link =
+                       next_northbridge(link, amd_nb_link_ids);
         }
 
        /* some CPU families (e.g. family 0x11) do not support GART */

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 3adb06ebf8418aa0a886e474a9e3460ddb4cbe09..580de67f318b4216900c04bea1f4b5c522a2da43 100644 (file)
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -518,6 +518,7 @@
 #define PCI_DEVICE_ID_AMD_11H_NB_MISC  0x1303
 #define PCI_DEVICE_ID_AMD_11H_NB_LINK  0x1304
 #define PCI_DEVICE_ID_AMD_15H_NB_MISC  0x1603
+#define PCI_DEVICE_ID_AMD_15H_NB_LINK  0x1604
 #define PCI_DEVICE_ID_AMD_CNB17H_F3    0x1703
 #define PCI_DEVICE_ID_AMD_LANCE                0x2000
 #define PCI_DEVICE_ID_AMD_LANCE_HOME   0x2001