* m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and

mulul insns on the coldfire.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9d351e7de807e703f570e0565d574a485bea77c5..5749e1413b368ce3070f47bb6869e05f332f5957 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+Mon Mar 17 08:48:03 1997  J.T. Conklin  <jtc@beauty.cygnus.com>
+
+       * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
+       mulul insns on the coldfire.
+       
 Sat Mar 15 17:13:05 1997  Ian Lance Taylor  <ian@cygnus.com>
 
        * arm-dis.c (print_insn_arm): Don't print instruction bytes.

diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c
index febad084bc9ec27f699c37b357726cffb0af903b..f635c6c230edea35d39db0b57d916260090942fb 100644 (file)
--- a/opcodes/m68k-opc.c
+++ b/opcodes/m68k-opc.c
@@ -1344,11 +1344,21 @@ const struct m68k_opcode m68k_opcodes[] =
 {"move16",     one(0xf618),            one(0xfff8), "_Las", m68040up },
 
 {"mulsw",      one(0140700),           one(0170700), ";wDd", m68000up|mcf5200 },
-{"mulsl",      two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32|mcf5200 },
+{"mulsl",      two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
+{"mulsl",      two(0046000,004000), two(0177700,0107770), "DsD1", mcf5200 },
+{"mulsl",      two(0046000,004000), two(0177700,0107770), "asD1", mcf5200 },
+{"mulsl",      two(0046000,004000), two(0177700,0107770), "+sD1", mcf5200 },
+{"mulsl",      two(0046000,004000), two(0177700,0107770), "-sD1", mcf5200 },
+{"mulsl",      two(0046000,004000), two(0177700,0107770), "dsD1", mcf5200 },
 {"mulsl",      two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
 
 {"muluw",      one(0140300),           one(0170700), ";wDd", m68000up|mcf5200 },
-{"mulul",      two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32|mcf5200 },
+{"mulul",      two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
+{"mulul",      two(0046000,000000), two(0177700,0107770), "DsD1", mcf5200 },
+{"mulul",      two(0046000,000000), two(0177700,0107770), "asD1", mcf5200 },
+{"mulul",      two(0046000,000000), two(0177700,0107770), "+sD1", mcf5200 },
+{"mulul",      two(0046000,000000), two(0177700,0107770), "-sD1", mcf5200 },
+{"mulul",      two(0046000,000000), two(0177700,0107770), "dsD1", mcf5200 },
 {"mulul",      two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
 
 {"nbcd",       one(0044000),   one(0177700), "$s", m68000up },
@@ -1815,11 +1825,11 @@ TBL("tblunb", "tblunw", "tblunl", 0, 0),
 {"trapv",      one(0047166),   one(0177777), "", m68000up },
 
 {"tstb",       one(0045000),   one(0177700), ";b", m68020up | mcf5200 },
-{"tstb",       one(0045000),   one(0177700), "@b", m68000 },
+{"tstb",       one(0045000),   one(0177700), "@b", m68000up },
 {"tstw",       one(0045100),   one(0177700), "*w", m68020up | mcf5200 },
-{"tstw",       one(0045100),   one(0177700), "@w", m68000 },
+{"tstw",       one(0045100),   one(0177700), "@w", m68000up },
 {"tstl",       one(0045200),   one(0177700), "*l", m68020up | mcf5200 },
-{"tstl",       one(0045200),   one(0177700), "@l", m68000 },
+{"tstl",       one(0045200),   one(0177700), "@l", m68000up },
 
 {"unlk",       one(0047130),   one(0177770), "As", m68000up | mcf5200 },