E6500 spr mnemonics

	PR 21248
	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
	those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 096cf3bfb0922792f80e7c3e211052481e9a01d6..aff4e07ae47f00767da8276f772aa14edb67f0ff 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-17  Alan Modra  <amodra@gmail.com>
+
+       PR 21248
+       * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
+       mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
+       those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
+
 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 
        * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 35804539faed6175c328755e95cf77ba5a8d0320..7e9f9f41480ec83e35541751a70cc06562968e9d 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -5407,12 +5407,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfspefscr",  XSPR(31,339,512), XSPR_MASK, PPCSPE,    0,              {RT}},
 {"mfbbear",    XSPR(31,339,513), XSPR_MASK, PPCBRLK,   0,              {RT}},
 {"mfbbtar",    XSPR(31,339,514), XSPR_MASK, PPCBRLK,   0,              {RT}},
-{"mfivor32",   XSPR(31,339,528), XSPR_MASK, PPCSPE,    0,              {RT}},
-{"mfibatu",    XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
-{"mfivor33",   XSPR(31,339,529), XSPR_MASK, PPCSPE,    0,              {RT}},
-{"mfibatl",    XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
+{"mfivor32",   XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, 0,           {RT}},
+{"mfivor33",   XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, 0,           {RT}},
 {"mfivor34",   XSPR(31,339,530), XSPR_MASK, PPCSPE,    0,              {RT}},
 {"mfivor35",   XSPR(31,339,531), XSPR_MASK, PPCPMR,    0,              {RT}},
+{"mfibatu",    XSPR(31,339,528), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
+{"mfibatl",    XSPR(31,339,529), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
 {"mfdbatu",    XSPR(31,339,536), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
 {"mfdbatl",    XSPR(31,339,537), XSPRBAT_MASK, PPC,    TITAN,          {RT, SPRBAT}},
 {"mfic_cst",   XSPR(31,339,560), XSPR_MASK, PPC860,    0,              {RT}},
@@ -5760,12 +5760,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtspefscr",  XSPR(31,467,512), XSPR_MASK, PPCSPE,    0,              {RS}},
 {"mtbbear",    XSPR(31,467,513), XSPR_MASK, PPCBRLK,   0,              {RS}},
 {"mtbbtar",    XSPR(31,467,514), XSPR_MASK, PPCBRLK,   0,              {RS}},
-{"mtivor32",   XSPR(31,467,528), XSPR_MASK, PPCSPE,    0,              {RS}},
-{"mtibatu",    XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
-{"mtivor33",   XSPR(31,467,529), XSPR_MASK, PPCSPE,    0,              {RS}},
-{"mtibatl",    XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
+{"mtivor32",   XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, 0,           {RS}},
+{"mtivor33",   XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, 0,           {RS}},
 {"mtivor34",   XSPR(31,467,530), XSPR_MASK, PPCSPE,    0,              {RS}},
 {"mtivor35",   XSPR(31,467,531), XSPR_MASK, PPCPMR,    0,              {RS}},
+{"mtibatu",    XSPR(31,467,528), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
+{"mtibatl",    XSPR(31,467,529), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
 {"mtdbatu",    XSPR(31,467,536), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
 {"mtdbatl",    XSPR(31,467,537), XSPRBAT_MASK, PPC,    TITAN,          {SPRBAT, RS}},
 {"mtmcsrr0",   XSPR(31,467,570), XSPR_MASK, PPCRFMCI,  0,              {RS}},