i386/x32: Align .eh_frame section to 4 bytes

.eh_frame section covering PLT sections should be aligned to 4 bytes
for i386 and x32.

bfd/

	* elf32-i386.c (elf_i386_check_relocs): Align .eh_frame section
	to 4 bytes.
	* elf64-x86-64.c (elf_x86_64_create_dynamic_sections): Align
	.eh_frame section to 4 bytes for x32.
	(elf_x86_64_check_relocs): Likewise.

ld/

	* testsuite/ld-x86-64/pr20830b.d: Updated.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index d6d340c7eb8d89ed0ee48e07349415471a21dee5..c45022bae38c96cd5063edc440d10c991f171729 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,11 @@
+2017-01-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * elf32-i386.c (elf_i386_check_relocs): Align .eh_frame section
+       to 4 bytes.
+       * elf64-x86-64.c (elf_x86_64_create_dynamic_sections): Align
+       .eh_frame section to 4 bytes for x32.
+       (elf_x86_64_check_relocs): Likewise.
+
 2017-01-10  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/20830

diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c
index 982bae6ce116dab074f27615803caf48b049b487..0860ada37ef205336133c123e566f49004850b2b 100644 (file)
--- a/bfd/elf32-i386.c
+++ b/bfd/elf32-i386.c
@@ -2395,7 +2395,7 @@ do_size:
              if (htab->plt_got_eh_frame == NULL
                  || !bfd_set_section_alignment (htab->elf.dynobj,
                                                 htab->plt_got_eh_frame,
-                                                3))
+                                                2))
                goto error_return;
            }
        }

diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
index b5a949a9cd89b58976d0ea6c52073975b1f59709..1edab046a1166e04010fe83848a9b15d5ad7a64c 100644 (file)
--- a/bfd/elf64-x86-64.c
+++ b/bfd/elf64-x86-64.c
@@ -1172,7 +1172,8 @@ elf_x86_64_create_dynamic_sections (bfd *dynobj,
       htab->plt_eh_frame
        = bfd_make_section_anyway_with_flags (dynobj, ".eh_frame", flags);
       if (htab->plt_eh_frame == NULL
-         || !bfd_set_section_alignment (dynobj, htab->plt_eh_frame, 3))
+         || !bfd_set_section_alignment (dynobj, htab->plt_eh_frame,
+                                        ABI_64_P (dynobj) ? 3 : 2))
        return FALSE;
     }
 
@@ -2796,7 +2797,7 @@ do_size:
              if (htab->plt_got_eh_frame == NULL
                  || !bfd_set_section_alignment (htab->elf.dynobj,
                                                 htab->plt_got_eh_frame,
-                                                3))
+                                                ABI_64_P (htab->elf.dynobj) ? 3 : 2))
                goto error_return;
            }
        }

diff --git a/ld/ChangeLog b/ld/ChangeLog
index d931ea1c177e513364083603a787fa87aad3e73e..96158cdcab464050cf77121063144e75e6a84592 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,7 @@
+2017-01-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * testsuite/ld-x86-64/pr20830b.d: Updated.
+
 2017-01-10  H.J. Lu  <hongjiu.lu@intel.com>
 
        * emulparams/elf32_x86_64.sh (TINY_READONLY_SECTION): New.

diff --git a/ld/testsuite/ld-x86-64/pr20830b.d b/ld/testsuite/ld-x86-64/pr20830b.d
index 5bd5b8ebbaf9f640e83e8d62dc741d80bf3418bf..218a56e2dfd019bb0599c7623e16f97e220c67c0 100644 (file)
--- a/ld/testsuite/ld-x86-64/pr20830b.d
+++ b/ld/testsuite/ld-x86-64/pr20830b.d
@@ -26,20 +26,14 @@ Contents of the .eh_frame section:
   DW_CFA_nop
   DW_CFA_nop
 
-0+2c ZERO terminator
-
-
-0+30 0000000000000020 00000034 FDE cie=00000000 pc=0000000000000170..0000000000000180
+0+2c 0000000000000020 00000030 FDE cie=00000000 pc=0000000000000170..0000000000000180
   DW_CFA_def_cfa_offset: 16
   DW_CFA_advance_loc: 6 to 0000000000000176
   DW_CFA_def_cfa_offset: 24
   DW_CFA_advance_loc: 10 to 0000000000000180
   DW_CFA_def_cfa_expression \(DW_OP_breg7 \(rsp\): 8; DW_OP_breg16 \(rip\): 0; DW_OP_lit15; DW_OP_and; DW_OP_lit11; DW_OP_ge; DW_OP_lit3; DW_OP_shl; DW_OP_plus\)
 
-0+54 ZERO terminator
-
-
-0+58 0000000000000010 0000005c FDE cie=00000000 pc=0000000000000180..0000000000000188
+0+50 0000000000000010 00000054 FDE cie=00000000 pc=0000000000000180..0000000000000188
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop