#define MAX_DOZE_WAITING_TIMES_9x 64
static bool
-SetRFPowerState8190(
- struct net_device* dev,
- RT_RF_POWER_STATE eRFPowerState
- )
+SetRFPowerState8190(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
{
struct r8192_priv *priv = ieee80211_priv(dev);
PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl));
return false;
priv->SetRFPowerStateInProgress = true;
- switch(priv->rf_chip)
+ switch( eRFPowerState )
{
- case RF_8256:
- switch( eRFPowerState )
+ case eRfOn:
+
+ // turn on RF
+ if((priv->ieee80211->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
+ { // The current RF state is OFF and the RF OFF level is halting the NIC, re-initialize the NIC.
+ bool rtstatus = true;
+ u32 InitializeCount = 3;
+ do
+ {
+ InitializeCount--;
+ rtstatus = NicIFEnableNIC(dev);
+ }while( (rtstatus != true) &&(InitializeCount >0) );
+
+ if(rtstatus != true)
+ {
+ RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__FUNCTION__);
+ priv->SetRFPowerStateInProgress = false;
+ return false;
+ }
+
+ RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
+ } else {
+ write_nic_byte(priv, ANAPAR, 0x37);//160MHz
+ mdelay(1);
+ //enable clock 80/88 MHz
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
+ priv->bHwRfOffAction = 0;
+
+ //RF-A, RF-B
+ //enable RF-Chip A/B
+ rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
+ //analog to digital on
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
+ //digital to analog on
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
+ //rx antenna on
+ rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
+ //rx antenna on
+ rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
+ //analog to digital part2 on
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
+
+ }
+
+ break;
+
+ //
+ // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
+ // By Bruce, 2008-01-16.
+ //
+ case eRfSleep:
+
+ // HW setting had been configured with deeper mode.
+ if(priv->ieee80211->eRFPowerState == eRfOff)
+ break;
+
+ for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
{
- case eRfOn:
-
- // turn on RF
- if((priv->ieee80211->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
- { // The current RF state is OFF and the RF OFF level is halting the NIC, re-initialize the NIC.
- bool rtstatus = true;
- u32 InitializeCount = 3;
- do
- {
- InitializeCount--;
- rtstatus = NicIFEnableNIC(dev);
- }while( (rtstatus != true) &&(InitializeCount >0) );
-
- if(rtstatus != true)
- {
- RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__FUNCTION__);
- priv->SetRFPowerStateInProgress = false;
- return false;
- }
-
- RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
- } else {
- write_nic_byte(priv, ANAPAR, 0x37);//160MHz
- mdelay(1);
- //enable clock 80/88 MHz
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
- priv->bHwRfOffAction = 0;
-
- //RF-A, RF-B
- //enable RF-Chip A/B
- rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
- //digital to analog on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
- //rx antenna on
- rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
- //rx antenna on
- rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
- //analog to digital part2 on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
+ ring = &priv->tx_ring[QueueID];
- }
+ if(skb_queue_len(&ring->queue) == 0)
+ {
+ QueueID++;
+ continue;
+ }
+ else
+ {
+ RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
+ udelay(10);
+ i++;
+ }
+ if(i >= MAX_DOZE_WAITING_TIMES_9x)
+ {
+ RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
break;
+ }
+ }
- //
- // In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
- // By Bruce, 2008-01-16.
- //
- case eRfSleep:
-
- // HW setting had been configured with deeper mode.
- if(priv->ieee80211->eRFPowerState == eRfOff)
- break;
-
- for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
- {
- ring = &priv->tx_ring[QueueID];
-
- if(skb_queue_len(&ring->queue) == 0)
- {
- QueueID++;
- continue;
- }
- else
- {
- RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
- udelay(10);
- i++;
- }
-
- if(i >= MAX_DOZE_WAITING_TIMES_9x)
- {
- RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
- break;
- }
- }
-
- PHY_SetRtl8192eRfOff(dev);
+ PHY_SetRtl8192eRfOff(dev);
- break;
+ break;
- case eRfOff:
+ case eRfOff:
- //
- // Disconnect with Any AP or STA.
- //
- for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
- {
- ring = &priv->tx_ring[QueueID];
-
- if(skb_queue_len(&ring->queue) == 0)
- {
- QueueID++;
- continue;
- }
- else
- {
- RT_TRACE(COMP_POWER,
- "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
- udelay(10);
- i++;
- }
-
- if(i >= MAX_DOZE_WAITING_TIMES_9x)
- {
- RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
- break;
- }
- }
+ //
+ // Disconnect with Any AP or STA.
+ //
+ for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
+ {
+ ring = &priv->tx_ring[QueueID];
+ if(skb_queue_len(&ring->queue) == 0)
+ {
+ QueueID++;
+ continue;
+ }
+ else
+ {
+ RT_TRACE(COMP_POWER,
+ "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
+ udelay(10);
+ i++;
+ }
- if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
- { // Disable all components.
- NicIFDisableNIC(dev);
- RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
- }
- else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
- { // Normal case.
- // IPS should go to this.
- PHY_SetRtl8192eRfOff(dev);
- }
+ if(i >= MAX_DOZE_WAITING_TIMES_9x)
+ {
+ RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
break;
-
- default:
- bResult = false;
- RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState);
- break;
+ }
}
+
+ if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
+ {
+ /* Disable all components. */
+ NicIFDisableNIC(dev);
+ RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
+ }
+ else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
+ {
+ /* Normal case - IPS should go to this. */
+ PHY_SetRtl8192eRfOff(dev);
+ }
break;
- default:
- RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
- break;
+ default:
+ bResult = false;
+ RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState);
+ break;
}
if(bResult)
Offset &= 0x3f;
//switch page for 8256 RF IC
- if (priv->rf_chip == RF_8256)
+ //analog to digital off, for protection
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
+ if (Offset >= 31)
{
- //analog to digital off, for protection
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
- if (Offset >= 31)
- {
- priv->RfReg0Value[eRFPath] |= 0x140;
- //Switch to Reg_Mode2 for Reg 31-45
- rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
- //modify offset
- NewOffset = Offset -30;
- }
- else if (Offset >= 16)
- {
- priv->RfReg0Value[eRFPath] |= 0x100;
- priv->RfReg0Value[eRFPath] &= (~0x40);
- //Switch to Reg_Mode 1 for Reg16-30
- rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
+ priv->RfReg0Value[eRFPath] |= 0x140;
+ //Switch to Reg_Mode2 for Reg 31-45
+ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
+ //modify offset
+ NewOffset = Offset -30;
+ }
+ else if (Offset >= 16)
+ {
+ priv->RfReg0Value[eRFPath] |= 0x100;
+ priv->RfReg0Value[eRFPath] &= (~0x40);
+ //Switch to Reg_Mode 1 for Reg16-30
+ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
- NewOffset = Offset - 15;
- }
- else
- NewOffset = Offset;
+ NewOffset = Offset - 15;
}
else
- {
- RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
NewOffset = Offset;
- }
+
//put desired read addr to LSSI control Register
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
//Issue a posedge trigger
// Switch back to Reg_Mode0;
- if(priv->rf_chip == RF_8256)
- {
- priv->RfReg0Value[eRFPath] &= 0xebf;
-
- rtl8192_setBBreg(
- dev,
- pPhyReg->rf3wireOffset,
- bMaskDWord,
- (priv->RfReg0Value[eRFPath] << 16));
+ priv->RfReg0Value[eRFPath] &= 0xebf;
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
- }
+ rtl8192_setBBreg(
+ dev,
+ pPhyReg->rf3wireOffset,
+ bMaskDWord,
+ (priv->RfReg0Value[eRFPath] << 16));
+ //analog to digital on
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
return ret;
-
}
/******************************************************************************
BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
Offset &= 0x3f;
- if (priv->rf_chip == RF_8256)
- {
- //analog to digital off, for protection
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
+ //analog to digital off, for protection
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
- if (Offset >= 31)
- {
- priv->RfReg0Value[eRFPath] |= 0x140;
- rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
- NewOffset = Offset - 30;
- }
- else if (Offset >= 16)
- {
- priv->RfReg0Value[eRFPath] |= 0x100;
- priv->RfReg0Value[eRFPath] &= (~0x40);
- rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
- NewOffset = Offset - 15;
- }
- else
- NewOffset = Offset;
+ if (Offset >= 31)
+ {
+ priv->RfReg0Value[eRFPath] |= 0x140;
+ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
+ NewOffset = Offset - 30;
}
- else
+ else if (Offset >= 16)
{
- RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
- NewOffset = Offset;
+ priv->RfReg0Value[eRFPath] |= 0x100;
+ priv->RfReg0Value[eRFPath] &= (~0x40);
+ rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
+ NewOffset = Offset - 15;
}
+ else
+ NewOffset = Offset;
// Put write addr in [5:0] and write data in [31:16]
DataAndAddr = (Data<<16) | (NewOffset&0x3f);
priv->RfReg0Value[eRFPath] = Data;
// Switch back to Reg_Mode0;
- if(priv->rf_chip == RF_8256)
+ if(Offset != 0)
{
- if(Offset != 0)
- {
- priv->RfReg0Value[eRFPath] &= 0xebf;
- rtl8192_setBBreg(
- dev,
- pPhyReg->rf3wireOffset,
- bMaskDWord,
- (priv->RfReg0Value[eRFPath] << 16));
- }
- //analog to digital on
- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
+ priv->RfReg0Value[eRFPath] &= 0xebf;
+ rtl8192_setBBreg(
+ dev,
+ pPhyReg->rf3wireOffset,
+ bMaskDWord,
+ (priv->RfReg0Value[eRFPath] << 16));
}
+ //analog to digital on
+ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
}
/******************************************************************************
pHalData->CurrentCckTxPwrIdx = powerlevel;
pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
#endif
- switch(priv->rf_chip)
- {
- case RF_8225:
- // PHY_SetRF8225CckTxPower(Adapter, powerlevel);
- // PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
- break;
- case RF_8256:
- PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
- PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
- break;
- case RF_8258:
- break;
- default:
- RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__);
- break;
- }
+ PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
+ PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
}
/******************************************************************************
* ***************************************************************************/
RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
{
- struct r8192_priv *priv = ieee80211_priv(dev);
- RT_STATUS rtStatus = RT_STATUS_SUCCESS;
- switch(priv->rf_chip)
- {
- case RF_8225:
-// rtStatus = PHY_RF8225_Config(Adapter);
- break;
- case RF_8256:
- rtStatus = PHY_RF8256_Config(dev);
- break;
-
- case RF_8258:
- break;
- case RF_PSEUDO_11N:
- //rtStatus = PHY_RF8225_Config(Adapter);
- break;
-
- default:
- RT_TRACE(COMP_ERR, "error chip id\n");
- break;
- }
- return rtStatus;
+ return PHY_RF8256_Config(dev);
}
/******************************************************************************
u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
- switch(priv->rf_chip)
- {
- case RF_8225:
-#ifdef TO_DO_LIST
- PHY_SetRF8225CckTxPower(Adapter, powerlevel);
- PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
-#endif
- break;
-
- case RF_8256:
- PHY_SetRF8256CCKTxPower(dev, powerlevel);
- PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
- break;
-
- case RF_8258:
- break;
- default:
- RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
- break;
- }
+ PHY_SetRF8256CCKTxPower(dev, powerlevel);
+ PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
}
+
/****************************************************************************************
*function: This function set command table variable(struct SwChnlCmd).
* input: SwChnlCmd* CmdTable //table to be set.
// <3> Fill up RF dependent command.
RfDependCmdCnt = 0;
- switch( priv->rf_chip )
- {
- case RF_8225:
- if (!(channel >= 1 && channel <= 14))
- {
- RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
- return false;
- }
- rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
- rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_End, 0, 0, 0);
- break;
-
- case RF_8256:
- // TEST!! This is not the table for 8256!!
- if (!(channel >= 1 && channel <= 14))
- {
- RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
- return false;
- }
- rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
- rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
- CmdID_End, 0, 0, 0);
- break;
-
- case RF_8258:
- break;
- default:
- RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
+ // TEST!! This is not the table for 8256!!
+ if (!(channel >= 1 && channel <= 14))
+ {
+ RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
return false;
- break;
}
-
+ rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
+ rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_End, 0, 0, 0);
do{
switch(*stage)
priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
- if(priv->rf_chip== RF_PSEUDO_11N)
- {
- priv->SetBWModeInProgress= false;
- return;
- }
if(!priv->up)
{
priv->SetBWModeInProgress= false;
//Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
//<3>Set RF related register
- switch( priv->rf_chip )
- {
- case RF_8225:
-#ifdef TO_DO_LIST
- PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
-#endif
- break;
-
- case RF_8256:
- PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
- break;
-
- case RF_8258:
- // PHY_SetRF8258Bandwidth();
- break;
-
- case RF_PSEUDO_11N:
- // Do Nothing
- break;
-
- default:
- RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
- break;
- }
+ PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
atomic_dec(&(priv->ieee80211->atm_swbw));
priv->SetBWModeInProgress= false;
projects / deliverable / linux.git / commitdiff
