drm/i915: Support for RR switching on VLV

Definition of VLV RR switch bit and corresponding toggling in
set_drrs function.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2124119692d5f858df7b87f8f5c5932d3bbd451..55143cb36e74baaedf0e6aad9947d3ec3b371e70 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3916,6 +3916,7 @@ enum skl_disp_power_wells {
 #define   PIPECONF_INTERLACE_MODE_MASK         (7 << 21)
 #define   PIPECONF_EDP_RR_MODE_SWITCH          (1 << 20)
 #define   PIPECONF_CXSR_DOWNCLOCK      (1<<16)
+#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV      (1 << 14)
 #define   PIPECONF_COLOR_RANGE_SELECT  (1 << 13)
 #define   PIPECONF_BPC_MASK    (0x7 << 5)
 #define   PIPECONF_8BPC                (0<<5)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c837ded8e27544df236a6da8148495e6f22db438..4d6e68c52fd9f53a73ba22e625e773beea24a8ac 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4825,9 +4825,15 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
                val = I915_READ(reg);
 
                if (index > DRRS_HIGH_RR) {
-                       val |= PIPECONF_EDP_RR_MODE_SWITCH;
+                       if (IS_VALLEYVIEW(dev))
+                               val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+                       else
+                               val |= PIPECONF_EDP_RR_MODE_SWITCH;
                } else {
-                       val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
+                       if (IS_VALLEYVIEW(dev))
+                               val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
+                       else
+                               val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
                }
                I915_WRITE(reg, val);
        }