* ECC (tx39) and sky changes.

[ChangeLog]
start-sanitize-tx3904
Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* dv-tx3904tmr.c: Deschedule timer event after dispatching.
	Reduce unnecessarily high timer event frequency.
	* dv-tx3904cpu.c: Ditto for interrupt event.
end-sanitize-tx3904
start-sanitize-sky
Tue Jun 16 14:12:09 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* interp.c (decode_coproc): Removed COP2 branches.
	* r5900.igen: Moved COP2 branch instructions here.
	* mips.igen: Restricted COPz == COP2 bit pattern to
	exclude COP2 branches.
end-sanitize-sky

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index dc403c1b32f7e7218abe0dec6c16c9186b3d99bb..17eafa725c9776c7354f4d2a9a7fcc4a5357be27 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,20 @@
+start-sanitize-tx3904
+Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+       * dv-tx3904tmr.c: Deschedule timer event after dispatching.
+       Reduce unnecessarily high timer event frequency.  
+       * dv-tx3904cpu.c: Ditto for interrupt event.
+       
+end-sanitize-tx3904
+start-sanitize-sky
+Tue Jun 16 14:12:09 1998  Frank Ch. Eigler  <fche@cygnus.com>
+
+       * interp.c (decode_coproc): Removed COP2 branches.
+       * r5900.igen: Moved COP2 branch instructions here.
+       * mips.igen: Restricted COPz == COP2 bit pattern to
+       exclude COP2 branches.
+
+end-sanitize-sky
 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 
        * interp.c (decode_coproc): For TX39, add stub COP0 register #7,

diff --git a/sim/mips/dv-tx3904tmr.c b/sim/mips/dv-tx3904tmr.c
index 98037936cda19d7b72ba1d640f7b3c6ecdfc4d84..0d33678dbee662bdd0fcb41b4f3befeb8ee72d3d 100644 (file)
--- a/sim/mips/dv-tx3904tmr.c
+++ b/sim/mips/dv-tx3904tmr.c
@@ -151,6 +151,7 @@ struct tx3904tmr {
   signed_8 last_ticks; /* time at last deliver_*_tick call */
   signed_8 roundoff_ticks; /* sim ticks unprocessed during last tick call */
   int ff; /* pulse generator flip-flop value: 1/0 */
+  struct hw_event* event; /* last scheduled event */
 
   unsigned_4 tcr;
 #define GET_TCR_TCE(c)      (((c)->tcr & 0x80) >> 7)
@@ -265,6 +266,8 @@ tx3904tmr_finish (struct hw *me)
     controller->trr = 0;
   controller->cpra = controller->cprb = 0x00FFFFFF;
   controller->ff = 0;
+  controller->last_ticks = controller->roundoff_ticks = 0;
+  controller->event = NULL;
 }
 
 
@@ -297,6 +300,10 @@ tx3904tmr_port_event (struct hw *me,
          controller->tisr = 
          controller->trr = 0;
        controller->cpra = controller->cprb = 0x00FFFFFF;
+       controller->last_ticks = controller->roundoff_ticks = 0;
+       if(controller->event != NULL)
+         hw_event_queue_deschedule(me, controller->event);
+       controller->event = NULL;
        break;
       }
 
@@ -491,10 +498,22 @@ deliver_tx3904tmr_tick (struct hw *me,
   SIM_DESC sd = hw_system (me);
   signed_8 this_ticks = sim_events_time(sd);
 
-  /* compute simulation ticks between last tick and this tick */
-  signed_8 warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
+  signed_8 warp;
   signed_8 divisor;
-  signed_8 quotient, reminder;
+  signed_8 quotient, remainder;
+
+  /* compute simulation ticks between last tick and this tick */
+  if(controller->last_ticks != 0)
+    warp = this_ticks - controller->last_ticks + controller->roundoff_ticks;
+  else
+    {
+      controller->last_ticks = this_ticks; /* initialize */
+      warp = controller->roundoff_ticks;
+    }
+
+  if(controller->event != NULL)
+    hw_event_queue_deschedule(me, controller->event);
+  controller->event = NULL;
 
   /* Check whether the timer ticking is enabled at this moment.  This
      largely a function of the TCE bit, but is also slightly
@@ -548,16 +567,16 @@ deliver_tx3904tmr_tick (struct hw *me,
 
   /* how many times to increase counter? */
   quotient = warp / divisor;
-  reminder = warp % divisor;
+  remainder = warp % divisor;
 
   /* NOTE: If the event rescheduling code works properly, the quotient
      should never be larger than 1.  That is, we should receive events
      here at least as frequently as the simulated counter is supposed
-     to decrement.  So the reminder (-> roundoff_ticks) will slowly
+     to decrement.  So the remainder (-> roundoff_ticks) will slowly
      accumulate, with the quotient == 0.  Once in a while, quotient
      will equal 1. */
 
-  controller->roundoff_ticks = reminder;
+  controller->roundoff_ticks = remainder;
   controller->last_ticks = this_ticks;
   while(quotient > 0) /* Is it time to increment counter? */
     {
@@ -668,7 +687,7 @@ deliver_tx3904tmr_tick (struct hw *me,
   /* Reschedule a timer event in near future, so we can increment the
      counter again.  Set the event about 75% of divisor time away, so
      we will experience roughly 1.3 events per counter increment. */
-  hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);
+  controller->event = hw_event_queue_schedule(me, divisor*3/4, deliver_tx3904tmr_tick, NULL);
 }
 
 

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index a9479b2f4735e50f310202ebf05c238f4286626f..4efde4a7904ee7cc95759ea5a9807c7f82381aae 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -976,19 +976,6 @@
 
 
 
-0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
-"cop<ZZ> <COP_FUN>"
-*mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  DecodeCoproc (instruction_0);
-}
 
 
 
@@ -3997,6 +3984,9 @@
 
 
 
+
+
+
 // C.EQ.S
 // C.EQ.D
 // ...
@@ -5620,6 +5610,22 @@
 }
 
 
+0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
+"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
+*mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  DecodeCoproc (instruction_0);
+}
+
+
+
 010000,10000,000000000000000,001000:COP0:32::TLBP
 "tlbp"
 *mipsI,mipsII,mipsIII,mipsIV: