e1000e: Increase PHY PLL clock gate timing

Several packet loss issues were reported for which the root cause for
them was an incorrect configuration of internal HW PHY clock gating
mechanism by SW.
This patch provides the correct mechanism.

Signed-off-by: Raanan Avargil <raanan.avargil@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index c731465d19997432e30d765be97eed061c5704a3..786d2148dd673d986513f6b9baae603dadf379d7 100644 (file)
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -1433,6 +1433,18 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
                        emi_addr = I217_RX_CONFIG;
                ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
 
+               if (hw->mac.type == e1000_pch_lpt ||
+                   hw->mac.type == e1000_pch_spt) {
+                       u16 phy_reg;
+
+                       e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
+                       phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
+                       if (speed == SPEED_100 || speed == SPEED_10)
+                               phy_reg |= 0x3E8;
+                       else
+                               phy_reg |= 0xFA;
+                       e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
+               }
                hw->phy.ops.release(hw);
 
                if (ret_val)

diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
index 34c551e322ebd30a6b3dd4bf994f3df957228db6..7d85f002c3d216d5c6036316119679c17b5ca340 100644 (file)
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.h
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
@@ -226,6 +226,9 @@
 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
 #define HV_PM_CTRL_K1_ENABLE           0x4000
 
+#define I217_PLL_CLOCK_GATE_REG        PHY_REG(772, 28)
+#define I217_PLL_CLOCK_GATE_MASK       0x07FF
+
 #define SW_FLAG_TIMEOUT                1000    /* SW Semaphore flag timeout in ms */
 
 /* Inband Control */