[AArch64] Add SVE system registers

This patch adds the SVE-specific system registers.

opcodes/
	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	(aarch64_sys_reg_supported_p): Handle them.

gas/
	* testsuite/gas/aarch64/sve-sysreg.s,
	testsuite/gas/aarch64/sve-sysreg.d,
	testsuite/gas/aarch64/sve-sysreg-invalid.d,
	testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1a2949c2c393b6a9c00cdf293530b1cf265eb288..d494dc7bd6382738e2619b18513aa327b33becf8 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * testsuite/gas/aarch64/sve-sysreg.s,
+       testsuite/gas/aarch64/sve-sysreg.d,
+       testsuite/gas/aarch64/sve-sysreg-invalid.d,
+       testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
+
 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 
        * doc/c-aarch64.texi: Fix sve entry.

diff --git a/gas/testsuite/gas/aarch64/sve-sysreg-invalid.d b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.d
new file mode 100644 (file)
index 0000000..bea0678
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+nosve
+#source: sve-sysreg.s
+#error-output: sve-sysreg-invalid.l

diff --git a/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l
new file mode 100644 (file)
index 0000000..b68c41d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sysreg-invalid.l
@@ -0,0 +1,21 @@
+.*: Assembler messages:
+.*:1: Error: selected processor does not support system register name 'id_aa64zfr0_el1'
+.*:2: Error: selected processor does not support system register name 'id_aa64zfr0_el1'
+.*:4: Error: selected processor does not support system register name 'zcr_el1'
+.*:5: Error: selected processor does not support system register name 'zcr_el1'
+.*:6: Error: selected processor does not support system register name 'zcr_el1'
+.*:7: Error: selected processor does not support system register name 'zcr_el1'
+.*:9: Error: selected processor does not support system register name 'zcr_el12'
+.*:10: Error: selected processor does not support system register name 'zcr_el12'
+.*:11: Error: selected processor does not support system register name 'zcr_el12'
+.*:12: Error: selected processor does not support system register name 'zcr_el12'
+.*:14: Error: selected processor does not support system register name 'zcr_el2'
+.*:15: Error: selected processor does not support system register name 'zcr_el2'
+.*:16: Error: selected processor does not support system register name 'zcr_el2'
+.*:17: Error: selected processor does not support system register name 'zcr_el2'
+.*:19: Error: selected processor does not support system register name 'zcr_el3'
+.*:20: Error: selected processor does not support system register name 'zcr_el3'
+.*:21: Error: selected processor does not support system register name 'zcr_el3'
+.*:22: Error: selected processor does not support system register name 'zcr_el3'
+.*:24: Error: selected processor does not support system register name 'zidr_el1'
+.*:25: Error: selected processor does not support system register name 'zidr_el1'

diff --git a/gas/testsuite/gas/aarch64/sve-sysreg.d b/gas/testsuite/gas/aarch64/sve-sysreg.d
new file mode 100644 (file)
index 0000000..24ab421
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sysreg.d
@@ -0,0 +1,29 @@
+#as: -march=armv8-a+sve
+#objdump: -dr
+
+
+.* file format .*
+
+Disassembly of section .*:
+
+0+ <.*>:
+.*:    d5380480        mrs     x0, id_aa64zfr0_el1
+.*:    d538049b        mrs     x27, id_aa64zfr0_el1
+.*:    d5381200        mrs     x0, zcr_el1
+.*:    d538121b        mrs     x27, zcr_el1
+.*:    d5181200        msr     zcr_el1, x0
+.*:    d518121a        msr     zcr_el1, x26
+.*:    d53d1200        mrs     x0, zcr_el12
+.*:    d53d121b        mrs     x27, zcr_el12
+.*:    d51d1200        msr     zcr_el12, x0
+.*:    d51d121a        msr     zcr_el12, x26
+.*:    d53c1200        mrs     x0, zcr_el2
+.*:    d53c121b        mrs     x27, zcr_el2
+.*:    d51c1200        msr     zcr_el2, x0
+.*:    d51c121a        msr     zcr_el2, x26
+.*:    d53e1200        mrs     x0, zcr_el3
+.*:    d53e121b        mrs     x27, zcr_el3
+.*:    d51e1200        msr     zcr_el3, x0
+.*:    d51e121a        msr     zcr_el3, x26
+.*:    d53800e0        mrs     x0, zidr_el1
+.*:    d53800fb        mrs     x27, zidr_el1

diff --git a/gas/testsuite/gas/aarch64/sve-sysreg.s b/gas/testsuite/gas/aarch64/sve-sysreg.s
new file mode 100644 (file)
index 0000000..a38ad7f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-sysreg.s
@@ -0,0 +1,25 @@
+       mrs     x0, ID_AA64ZFR0_EL1
+       mrs     X27, id_aa64zfr0_el1
+
+       mrs     x0, ZCR_EL1
+       mrs     X27, zcr_el1
+       msr     ZCR_EL1, X0
+       msr     zcr_el1, x26
+
+       mrs     x0, ZCR_EL12
+       mrs     X27, zcr_el12
+       msr     ZCR_EL12, X0
+       msr     zcr_el12, x26
+
+       mrs     x0, ZCR_EL2
+       mrs     X27, zcr_el2
+       msr     ZCR_EL2, X0
+       msr     zcr_el2, x26
+
+       mrs     x0, ZCR_EL3
+       mrs     X27, zcr_el3
+       msr     ZCR_EL3, X0
+       msr     zcr_el3, x26
+
+       mrs     x0, ZIDR_EL1
+       mrs     X27, zidr_el1

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1bb7b4293729796c996a50c0f074d191ba12b7e0..4e58d6c9c1702bd0622103fe9f4327b6ee7c91ee 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
+       (aarch64_sys_reg_supported_p): Handle them.
+
 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * arc-opc.c (UIMM6_20R): Define.

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 314bcb419386d432042a4f52077bbe418b2963c1..dac61593f91b8f475a3e0adfd371e98ec7f9083a 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3670,6 +3670,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT }, /* RO */
   { "id_aa64afr0_el1",  CPENC(3,0,C0,C5,4),    0 }, /* RO */
   { "id_aa64afr1_el1",  CPENC(3,0,C0,C5,5),    0 }, /* RO */
+  { "id_aa64zfr0_el1",  CPENC (3, 0, C0, C4, 4), F_ARCHEXT }, /* RO */
   { "clidr_el1",        CPENC(3,1,C0,C0,1),    0 }, /* RO */
   { "csselr_el1",       CPENC(3,2,C0,C0,0),    0 }, /* RO */
   { "vpidr_el2",        CPENC(3,4,C0,C0,0),    0 },
@@ -3691,6 +3692,11 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "mdcr_el3",         CPENC(3,6,C1,C3,1),    0 },
   { "hstr_el2",         CPENC(3,4,C1,C1,3),    0 },
   { "hacr_el2",         CPENC(3,4,C1,C1,7),    0 },
+  { "zcr_el1",          CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
+  { "zcr_el12",         CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
+  { "zcr_el2",          CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
+  { "zcr_el3",          CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
+  { "zidr_el1",         CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
   { "ttbr0_el1",        CPENC(3,0,C2,C0,0),    0 },
   { "ttbr1_el1",        CPENC(3,0,C2,C0,1),    0 },
   { "ttbr0_el2",        CPENC(3,4,C2,C0,0),    0 },
@@ -4104,6 +4110,16 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
     return FALSE;
 
+  /* SVE.  */
+  if ((reg->value == CPENC (3, 0, C0, C4, 4)
+       || reg->value == CPENC (3, 0, C1, C2, 0)
+       || reg->value == CPENC (3, 4, C1, C2, 0)
+       || reg->value == CPENC (3, 6, C1, C2, 0)
+       || reg->value == CPENC (3, 5, C1, C2, 0)
+       || reg->value == CPENC (3, 0, C0, C0, 7))
+      && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
+    return FALSE;
+
   return TRUE;
 }