ARM: dts: uniphier: add outer cache controller nodes

Add L2 cache controller nodes for all the UniPhier SoC DTSI.
Also, add an L3 cache controller node for PH1-Pro5 DTSI.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
index a6a185fae8f1dcb0d39ffa61027c1bbcb5756aed..ae13469a387c5c343fc9a083154f953ded62437b 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
@@ -55,6 +55,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -91,6 +92,18 @@
                        #size-cells = <1>;
                };
 
+               l2: l2-cache@500c0000 {
+                       compatible = "socionext,uniphier-system-cache";
+                       reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+                             <0x506c0000 0x400>;
+                       interrupts = <0 174 4>, <0 175 4>;
+                       cache-unified;
+                       cache-size = <(512 * 1024)>;
+                       cache-sets = <256>;
+                       cache-line-size = <128>;
+                       cache-level = <2>;
+               };
+
                serial0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
                        status = "disabled";

diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
index e8bbc454d7887d9f8887065cc4a378fc7bc89a94..85377b23483fdfc5df590a98f48756c01fc50b9a 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
@@ -56,12 +56,14 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -98,6 +100,18 @@
                        #size-cells = <1>;
                };
 
+               l2: l2-cache@500c0000 {
+                       compatible = "socionext,uniphier-system-cache";
+                       reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+                             <0x506c0000 0x400>;
+                       interrupts = <0 174 4>, <0 175 4>;
+                       cache-unified;
+                       cache-size = <(768 * 1024)>;
+                       cache-sets = <256>;
+                       cache-line-size = <128>;
+                       cache-level = <2>;
+               };
+
                serial0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
                        status = "disabled";

diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
index 59c2b127cffabfc87e17e5161ac7473f1d9a4c3c..96da01ed74b64fa7238af92056bb839095d1ad1e 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
@@ -56,12 +56,14 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -98,6 +100,31 @@
                        #size-cells = <1>;
                };
 
+               l2: l2-cache@500c0000 {
+                       compatible = "socionext,uniphier-system-cache";
+                       reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
+                             <0x506c0000 0x400>;
+                       interrupts = <0 190 4>, <0 191 4>;
+                       cache-unified;
+                       cache-size = <(2 * 1024 * 1024)>;
+                       cache-sets = <512>;
+                       cache-line-size = <128>;
+                       cache-level = <2>;
+                       next-level-cache = <&l3>;
+               };
+
+               l3: l3-cache@500c8000 {
+                       compatible = "socionext,uniphier-system-cache";
+                       reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
+                             <0x506c8000 0x400>;
+                       interrupts = <0 174 4>, <0 175 4>;
+                       cache-unified;
+                       cache-size = <(2 * 1024 * 1024)>;
+                       cache-sets = <512>;
+                       cache-line-size = <256>;
+                       cache-level = <3>;
+               };
+
                serial0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
                        status = "disabled";

diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
index 3cc90cd37a263b334635963153c3f9a4c21d1c9b..945b37f45988bbdb77dfb34acc8527d056374cfa 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
@@ -56,12 +56,14 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -120,6 +122,18 @@
                              <0x20000100 0x100>;
                };
 
+               l2: l2-cache@500c0000 {
+                       compatible = "socionext,uniphier-system-cache";
+                       reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+                             <0x506c0000 0x400>;
+                       interrupts = <0 174 4>, <0 175 4>;
+                       cache-unified;
+                       cache-size = <(512 * 1024)>;
+                       cache-sets = <256>;
+                       cache-line-size = <128>;
+                       cache-level = <2>;
+               };
+
                serial0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
                        status = "disabled";

diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
index 58067dfc16e592843ddfeb3a98ccb6b75abfd9ea..c98428caed47948a42cbe2587ca2afef0d10961d 100644 (file)
--- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
@@ -55,6 +55,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -91,6 +92,18 @@
                        #size-cells = <1>;
                };
 
+               l2: l2-cache@500c0000 {
+                       compatible = "socionext,uniphier-system-cache";
+                       reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+                             <0x506c0000 0x400>;
+                       interrupts = <0 174 4>, <0 175 4>;
+                       cache-unified;
+                       cache-size = <(256 * 1024)>;
+                       cache-sets = <256>;
+                       cache-line-size = <128>;
+                       cache-level = <2>;
+               };
+
                serial0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
                        status = "disabled";

diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index 4c7b2461101215dc8075dc2f291450aee268fe8e..ad5fb390e003dfd0a9a836825cee4bae3e93348f 100644 (file)
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -56,24 +56,28 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <2>;
+                       next-level-cache = <&l2>;
                };
 
                cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <3>;
+                       next-level-cache = <&l2>;
                };
        };
 
@@ -110,6 +114,18 @@
                        #size-cells = <1>;
                };
 
+               l2: l2-cache@500c0000 {
+                       compatible = "socionext,uniphier-system-cache";
+                       reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
+                             <0x506c0000 0x400>;
+                       interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+                       cache-unified;
+                       cache-size = <(1280 * 1024)>;
+                       cache-sets = <512>;
+                       cache-line-size = <128>;
+                       cache-level = <2>;
+               };
+
                serial0: serial@54006800 {
                        compatible = "socionext,uniphier-uart";
                        status = "disabled";