+2017-05-03 Maciej W. Rozycki <macro@imgtec.com>
+
+ * config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `pic', `sym32' and
+ `nomacro' flags.
+ (RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO):
+ New macros.
+ (RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
+ (RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
+ (RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
+ (RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
+ (RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
+ (RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED): Shift bits.
+ (RELAX_MIPS16_MACRO, RELAX_MIPS16_MARK_MACRO)
+ (RELAX_MIPS16_CLEAR_MACRO): New macros.
+ (append_insn): Pass `mips_pic', HAVE_32BIT_SYMBOLS and
+ `mips_opts.warn_about_macros' settings to RELAX_MIPS16_ENCODE.
+ (mips16_macro_frag): New function.
+ (md_estimate_size_before_relax): Handle HI16/LO16 relaxation.
+ (mips_relax_frag): Likewise.
+ (md_convert_frag): Likewise.
+
+ * testsuite/gas/mips/mips16@relax-swap3.d: Remove error output,
+ add dump patterns.
+ * testsuite/gas/mips/mips16e@relax-swap3.d: New test
+ subarchitecture.
+ * testsuite/gas/mips/micromips@relax-swap3.d: Remove trailing
+ NOP padding.
+ * testsuite/gas/mips/mips16-pcrel-reloc-2.d: Remove error
+ output, add dump patterns.
+ * testsuite/gas/mips/mips16-pcrel-reloc-3.d: Remove error
+ output, add dump patterns.
+ * testsuite/gas/mips/mips16-pcrel-reloc-6.d: Remove error
+ output, add dump patterns.
+ * testsuite/gas/mips/mips16-pcrel-reloc-7.d: Remove error
+ output, add dump patterns.
+ * testsuite/gas/mips/mips16-pcrel-addend-2.d: Remove error
+ output, add dump patterns.
+ * testsuite/gas/mips/mips16-pcrel-addend-3.d: Remove error
+ output, add dump patterns.
+ * testsuite/gas/mips/mips16-pcrel-absolute.d: Remove error
+ output, add dump patterns.
+ * testsuite/gas/mips/mips16-pcrel-absolute-1.d: Remove error
+ output, add dump patterns.
+ * testsuite/gas/mips/mips16@relax-swap3.l: Remove file.
+ * testsuite/gas/mips/mips16-pcrel-reloc-2.l: Remove file.
+ * testsuite/gas/mips/mips16-pcrel-reloc-3.l: Remove file.
+ * testsuite/gas/mips/mips16-pcrel-reloc-6.l: Remove file.
+ * testsuite/gas/mips/mips16-pcrel-reloc-7.l: Remove file.
+ * testsuite/gas/mips/mips16-pcrel-addend-2.l: Remove file.
+ * testsuite/gas/mips/mips16-pcrel-addend-3.l: Remove file.
+ * testsuite/gas/mips/mips16-pcrel-absolute.l: Remove file.
+ * testsuite/gas/mips/mips16-pcrel-absolute-1.l: Remove file.
+ * testsuite/gas/mips/relax-swap3.s: Adjust trailing padding.
+
+ * testsuite/gas/mips/mips16-pcrel-0.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-1.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-2.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-3.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-4.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-5.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-pic-0.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-pic-1.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-n32-0.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-n32-1.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-n64-sym32-0.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-n64-sym32-1.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-n64-0.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-n64-1.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-delay-0.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-delay-1.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-4.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-5.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-6.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-7.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-8.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-9.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-pic-8.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-pic-9.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-n32-8.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-n32-9.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-8.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-n64-sym32-9.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-n64-8.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-addend-n64-9.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-2.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-3.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-4.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-5.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-6.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-7.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-4.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-6.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n32-4.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n32-6.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-4.d: New
+ test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-n64-sym32-6.d: New
+ test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-4.d: New
+ test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n32-6.d: New
+ test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d: New
+ test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d: New
+ test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-4.d:
+ New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-sym32-6.d:
+ New test.
+ * testsuite/gas/mips/mips16-pcrel-0.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-1.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-2.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-3.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-4.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-5.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-delay-0.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-delay-1.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-addend-8.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-addend-9.l: New stderr output.
+ * testsuite/gas/mips/mips16-pcrel-absolute-4.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16-pcrel-absolute-6.l: New stderr
+ output.
+ * testsuite/gas/mips/mips16-pcrel-0.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-1.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-2.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-3.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-4.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-5.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-delay-0.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-delay-1.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-addend-4.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-addend-5.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-addend-6.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-addend-7.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-addend-8.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-addend-9.s: New test source.
+ * testsuite/gas/mips/mips16-pcrel-absolute-2.s: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-3.s: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-4.s: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-5.s: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-6.s: New test.
+ * testsuite/gas/mips/mips16-pcrel-absolute-7.s: New test.
+ * testsuite/gas/mips/mips.exp: Run the new tests.
+
2017-05-03 Nick Clifton <nickc@redhat.com>
PR gas/20941
store whether this is known to be a branch to a different section,
whether we have tried to relax this frag yet, and whether we have
ever extended a PC relative fragment because of a shift count. */
-#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
+#define RELAX_MIPS16_ENCODE(type, pic, sym32, nomacro, \
+ small, ext, \
+ dslot, jal_dslot) \
(0x80000000 \
| ((type) & 0xff) \
- | ((small) ? 0x100 : 0) \
- | ((ext) ? 0x200 : 0) \
- | ((dslot) ? 0x400 : 0) \
- | ((jal_dslot) ? 0x800 : 0))
+ | ((pic) ? 0x100 : 0) \
+ | ((sym32) ? 0x200 : 0) \
+ | ((nomacro) ? 0x400 : 0) \
+ | ((small) ? 0x800 : 0) \
+ | ((ext) ? 0x1000 : 0) \
+ | ((dslot) ? 0x2000 : 0) \
+ | ((jal_dslot) ? 0x4000 : 0))
+
#define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
-#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
-#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
-#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
-#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
-#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
-#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
-#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
-#define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x2000) != 0)
-#define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x2000)
-#define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x2000)
+#define RELAX_MIPS16_PIC(i) (((i) & 0x100) != 0)
+#define RELAX_MIPS16_SYM32(i) (((i) & 0x200) != 0)
+#define RELAX_MIPS16_NOMACRO(i) (((i) & 0x400) != 0)
+#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x800) != 0)
+#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x1000) != 0)
+#define RELAX_MIPS16_DSLOT(i) (((i) & 0x2000) != 0)
+#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x4000) != 0)
+
+#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x8000) != 0)
+#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x8000)
+#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x8000)
+#define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x10000) != 0)
+#define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x10000)
+#define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x10000)
+#define RELAX_MIPS16_MACRO(i) (((i) & 0x20000) != 0)
+#define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x20000)
+#define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x20000)
/* For microMIPS code, we use relaxation similar to one we use for
MIPS16 code. Some instructions that take immediate values support
symbol_append (symbol, symbol_lastP, &symbol_rootP, &symbol_lastP);
offset = 0;
}
- add_relaxed_insn (ip, 4, 0,
+ add_relaxed_insn (ip, 12, 0,
RELAX_MIPS16_ENCODE
(*reloc_type - BFD_RELOC_UNUSED,
+ mips_pic != NO_PIC,
+ HAVE_32BIT_SYMBOLS,
+ mips_opts.warn_about_macros,
require_unextended, require_extended,
delayed_branch_p (&history[0]),
history[0].mips16_absolute_jump_p),
return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
}
+/* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
+ macro expansion. SEC is the section the frag is in. We only
+ support PC-relative instructions (LA, DLA, LW, LD) here, in
+ non-PIC code using 32-bit addressing. */
+
+static int
+mips16_macro_frag (fragS *fragp, asection *sec, long stretch)
+{
+ const struct mips_pcrel_operand *pcrel_op;
+ const struct mips_int_operand *operand;
+ offsetT val;
+ segT symsec;
+ int type;
+
+ gas_assert (!RELAX_MIPS16_USER_SMALL (fragp->fr_subtype));
+
+ if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))
+ return 0;
+ if (!RELAX_MIPS16_SYM32 (fragp->fr_subtype))
+ return 0;
+
+ type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
+ switch (type)
+ {
+ case 'A':
+ case 'B':
+ case 'E':
+ symsec = S_GET_SEGMENT (fragp->fr_symbol);
+ if (bfd_is_abs_section (symsec))
+ return 1;
+ if (RELAX_MIPS16_PIC (fragp->fr_subtype))
+ return 0;
+ if (S_FORCE_RELOC (fragp->fr_symbol, TRUE) || sec != symsec)
+ return 1;
+
+ operand = mips16_immed_operand (type, TRUE);
+ val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
+ pcrel_op = (const struct mips_pcrel_operand *) operand;
+ val = mips16_pcrel_val (fragp, pcrel_op, val, stretch);
+
+ return !mips16_immed_in_range_p (operand, BFD_RELOC_UNUSED, val);
+
+ default:
+ return 0;
+ }
+}
+
/* Compute the length of a branch sequence, and adjust the
RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
worst-case length is computed, with UPDATE being used to indicate
}
if (RELAX_MIPS16_P (fragp->fr_subtype))
- /* We don't want to modify the EXTENDED bit here; it might get us
- into infinite loops. We change it only in mips_relax_frag(). */
- return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
+ {
+ /* We don't want to modify the EXTENDED bit here; it might get us
+ into infinite loops. We change it only in mips_relax_frag(). */
+ if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
+ return 12;
+ else
+ return RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2;
+ }
if (RELAX_MICROMIPS_P (fragp->fr_subtype))
{
if (! RELAX_MIPS16_P (fragp->fr_subtype))
return 0;
- if (mips16_extended_frag (fragp, sec, stretch))
+ if (!mips16_extended_frag (fragp, sec, stretch))
{
- if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
+ if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
+ {
+ fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
+ return -10;
+ }
+ else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
+ {
+ fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
+ return -2;
+ }
+ else
+ return 0;
+ }
+ else if (!mips16_macro_frag (fragp, sec, stretch))
+ {
+ if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
+ {
+ fragp->fr_subtype = RELAX_MIPS16_CLEAR_MACRO (fragp->fr_subtype);
+ fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
+ return -8;
+ }
+ else if (!RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
+ {
+ fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
+ return 2;
+ }
+ else
return 0;
- fragp->fr_subtype = RELAX_MIPS16_MARK_EXTENDED (fragp->fr_subtype);
- return 2;
}
else
{
- if (! RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
+ if (RELAX_MIPS16_MACRO (fragp->fr_subtype))
return 0;
- fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
- return -2;
+ else if (RELAX_MIPS16_EXTENDED (fragp->fr_subtype))
+ {
+ fragp->fr_subtype = RELAX_MIPS16_CLEAR_EXTENDED (fragp->fr_subtype);
+ fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
+ return 8;
+ }
+ else
+ {
+ fragp->fr_subtype = RELAX_MIPS16_MARK_MACRO (fragp->fr_subtype);
+ return 10;
+ }
}
return 0;
const struct mips_int_operand *operand;
offsetT val;
char *buf;
- unsigned int user_length, length;
+ unsigned int user_length;
bfd_boolean need_reloc;
unsigned long insn;
+ bfd_boolean mac;
bfd_boolean ext;
segT symsec;
type = RELAX_MIPS16_TYPE (fragp->fr_subtype);
operand = mips16_immed_operand (type, FALSE);
+ mac = RELAX_MIPS16_MACRO (fragp->fr_subtype);
ext = RELAX_MIPS16_EXTENDED (fragp->fr_subtype);
val = resolve_symbol_value (fragp->fr_symbol) + fragp->fr_offset;
symsec = S_GET_SEGMENT (fragp->fr_symbol);
need_reloc = (S_FORCE_RELOC (fragp->fr_symbol, TRUE)
- || (operand->root.type == OP_PCREL
+ || (operand->root.type == OP_PCREL && !mac
? asec != symsec
: !bfd_is_abs_section (symsec)));
- if (operand->root.type == OP_PCREL)
+ if (operand->root.type == OP_PCREL && !mac)
{
const struct mips_pcrel_operand *pcrel_op;
record_alignment (asec, operand->shift);
}
- if (ext
- && (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
- || RELAX_MIPS16_DSLOT (fragp->fr_subtype)))
+ if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype)
+ || RELAX_MIPS16_DSLOT (fragp->fr_subtype))
+ {
+ if (mac)
+ as_warn_where (fragp->fr_file, fragp->fr_line,
+ _("macro instruction expanded into multiple "
+ "instructions in a branch delay slot"));
+ else if (ext)
+ as_warn_where (fragp->fr_file, fragp->fr_line,
+ _("extended instruction in a branch delay slot"));
+ }
+ else if (RELAX_MIPS16_NOMACRO (fragp->fr_subtype) && mac)
as_warn_where (fragp->fr_file, fragp->fr_line,
- _("extended instruction in delay slot"));
+ _("macro instruction expanded into multiple "
+ "instructions"));
buf = fragp->fr_literal + fragp->fr_fix;
else
user_length = 0;
- if (need_reloc)
+ if (mac)
{
- bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
- expressionS exp;
- fixS *fixp;
+ unsigned long reg;
+ unsigned long new;
+ unsigned long op;
+
+ gas_assert (type == 'A' || type == 'B' || type == 'E');
+ gas_assert (RELAX_MIPS16_SYM32 (fragp->fr_subtype));
- switch (type)
+ if (need_reloc)
{
- case 'p':
- case 'q':
- reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
+ fixS *fixp;
+
+ gas_assert (!RELAX_MIPS16_PIC (fragp->fr_subtype));
+
+ fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
+ fragp->fr_symbol, fragp->fr_offset,
+ FALSE, BFD_RELOC_MIPS16_HI16_S);
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+
+ fixp = fix_new (fragp, buf - fragp->fr_literal + 8, 4,
+ fragp->fr_symbol, fragp->fr_offset,
+ FALSE, BFD_RELOC_MIPS16_LO16);
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+
+ val = 0;
+ }
+
+ switch (insn & 0xf800)
+ {
+ case 0x0800: /* ADDIU */
+ reg = (insn >> 8) & 0x7;
+ op = 0xf0004800 | (reg << 8);
break;
- default:
- as_bad_where (fragp->fr_file, fragp->fr_line,
- _("unsupported relocation"));
+ case 0xb000: /* LW */
+ reg = (insn >> 8) & 0x7;
+ op = 0xf0009800 | (reg << 8) | (reg << 5);
break;
+ case 0xf800: /* I64 */
+ reg = (insn >> 5) & 0x7;
+ switch (insn & 0x0700)
+ {
+ case 0x0400: /* LD */
+ op = 0xf0003800 | (reg << 8) | (reg << 5);
+ break;
+ case 0x0600: /* DADDIU */
+ op = 0xf000fd00 | (reg << 5);
+ break;
+ default:
+ abort ();
+ }
+ break;
+ default:
+ abort ();
}
- if (reloc == BFD_RELOC_NONE)
- ;
- else if (ext)
+
+ new = 0xf0006800 | (reg << 8); /* LI */
+ new |= mips16_immed_extend ((val + 0x8000) >> 16, 16);
+ buf = write_compressed_insn (buf, new, 4);
+ new = 0xf4003000 | (reg << 8) | (reg << 5); /* SLL */
+ buf = write_compressed_insn (buf, new, 4);
+ op |= mips16_immed_extend (val, 16);
+ buf = write_compressed_insn (buf, op, 4);
+
+ fragp->fr_fix += 12;
+ }
+ else
+ {
+ unsigned int length = ext ? 4 : 2;
+
+ if (need_reloc)
{
- exp.X_op = O_symbol;
- exp.X_add_symbol = fragp->fr_symbol;
- exp.X_add_number = fragp->fr_offset;
+ bfd_reloc_code_real_type reloc = BFD_RELOC_NONE;
+ expressionS exp;
+ fixS *fixp;
- fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
- TRUE, reloc);
+ switch (type)
+ {
+ case 'p':
+ case 'q':
+ reloc = BFD_RELOC_MIPS16_16_PCREL_S1;
+ break;
+ default:
+ break;
+ }
+ if (mac || reloc == BFD_RELOC_NONE)
+ as_bad_where (fragp->fr_file, fragp->fr_line,
+ _("unsupported relocation"));
+ else if (ext)
+ {
+ exp.X_op = O_symbol;
+ exp.X_add_symbol = fragp->fr_symbol;
+ exp.X_add_number = fragp->fr_offset;
- fixp->fx_file = fragp->fr_file;
- fixp->fx_line = fragp->fr_line;
+ fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp,
+ TRUE, reloc);
+
+ fixp->fx_file = fragp->fr_file;
+ fixp->fx_line = fragp->fr_line;
+ }
+ else
+ as_bad_where (fragp->fr_file, fragp->fr_line,
+ _("invalid unextended operand value"));
}
else
- as_bad_where (fragp->fr_file, fragp->fr_line,
- _("invalid unextended operand value"));
- }
- else
- mips16_immed (fragp->fr_file, fragp->fr_line, type,
- BFD_RELOC_UNUSED, val, user_length, &insn);
+ mips16_immed (fragp->fr_file, fragp->fr_line, type,
+ BFD_RELOC_UNUSED, val, user_length, &insn);
- length = (ext ? 4 : 2);
- gas_assert (mips16_opcode_length (insn) == length);
- write_compressed_insn (buf, insn, length);
- fragp->fr_fix += length;
+ gas_assert (mips16_opcode_length (insn) == length);
+ write_compressed_insn (buf, insn, length);
+ fragp->fr_fix += length;
+ }
}
else
{
[ ]*[0-9a-f]+: R_MICROMIPS_LO16 bar
[0-9a-f]+ <[^>]*> 40e3 fffe beqzc v1,[0-9a-f]+ <[^>]*>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
-[0-9a-f]+ <[^>]*> 0c00 nop
\.\.\.
run_list_test "pcrel-reloc-6" "-32 --defsym offset=4" \
"MIPS local PC-relative relocations 6b"
+ run_dump_test "mips16-pcrel-0"
+ run_dump_test "mips16-pcrel-1"
+ run_dump_test "mips16-pcrel-2"
+ run_dump_test "mips16-pcrel-3"
+ run_dump_test "mips16-pcrel-4"
+ run_dump_test "mips16-pcrel-5"
+ run_dump_test "mips16-pcrel-pic-0"
+ run_dump_test "mips16-pcrel-pic-1"
+ if $has_newabi {
+ run_dump_test "mips16-pcrel-n32-0"
+ run_dump_test "mips16-pcrel-n32-1"
+ run_dump_test "mips16-pcrel-n64-sym32-0"
+ run_dump_test "mips16-pcrel-n64-sym32-1"
+ run_dump_test "mips16-pcrel-n64-0"
+ run_dump_test "mips16-pcrel-n64-1"
+ }
+ run_dump_test "mips16-pcrel-delay-0"
+ run_dump_test "mips16-pcrel-delay-1"
run_dump_test "mips16-pcrel-relax-0"
run_dump_test "mips16-pcrel-relax-1"
run_dump_test "mips16-pcrel-relax-2"
run_dump_test "mips16-pcrel-addend-1"
run_dump_test "mips16-pcrel-addend-2"
run_dump_test "mips16-pcrel-addend-3"
+ run_dump_test "mips16-pcrel-addend-4"
+ run_dump_test "mips16-pcrel-addend-5"
+ run_dump_test "mips16-pcrel-addend-6"
+ run_dump_test "mips16-pcrel-addend-7"
+ run_dump_test "mips16-pcrel-addend-8"
+ run_dump_test "mips16-pcrel-addend-9"
+ run_dump_test "mips16-pcrel-addend-pic-8"
+ run_dump_test "mips16-pcrel-addend-pic-9"
+ if $has_newabi {
+ run_dump_test "mips16-pcrel-addend-n32-8"
+ run_dump_test "mips16-pcrel-addend-n32-9"
+ run_dump_test "mips16-pcrel-addend-n64-sym32-8"
+ run_dump_test "mips16-pcrel-addend-n64-sym32-9"
+ run_dump_test "mips16-pcrel-addend-n64-8"
+ run_dump_test "mips16-pcrel-addend-n64-9"
+ }
run_dump_test "mips16-pcrel-absolute"
run_dump_test "mips16-pcrel-absolute-1"
+ run_dump_test "mips16-pcrel-absolute-2"
+ run_dump_test "mips16-pcrel-absolute-3"
+ run_dump_test "mips16-pcrel-absolute-4"
+ run_dump_test "mips16-pcrel-absolute-5"
+ run_dump_test "mips16-pcrel-absolute-6"
+ run_dump_test "mips16-pcrel-absolute-7"
+ run_dump_test "mips16-pcrel-absolute-pic-4"
+ run_dump_test "mips16-pcrel-absolute-pic-6"
+ if $has_newabi {
+ run_dump_test "mips16-pcrel-absolute-n32-4"
+ run_dump_test "mips16-pcrel-absolute-n32-6"
+ run_dump_test "mips16-pcrel-absolute-n64-4"
+ run_dump_test "mips16-pcrel-absolute-n64-6"
+ run_dump_test "mips16-pcrel-absolute-n64-sym32-4"
+ run_dump_test "mips16-pcrel-absolute-n64-sym32-6"
+ run_dump_test "mips16-pcrel-absolute-pic-n32-4"
+ run_dump_test "mips16-pcrel-absolute-pic-n32-6"
+ run_dump_test "mips16-pcrel-absolute-pic-n64-4"
+ run_dump_test "mips16-pcrel-absolute-pic-n64-6"
+ run_dump_test "mips16-pcrel-absolute-pic-n64-sym32-4"
+ run_dump_test "mips16-pcrel-absolute-pic-n64-sym32-6"
+ }
run_dump_test "mips16-branch-reloc-0"
run_dump_test "mips16-branch-reloc-1"
run_dump_test "mips16-branch-reloc-2"
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operations 0
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> 0a00 la v0,00010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> b200 lw v0,00010004 <foo\+0x4>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> 0aff la v0,00010404 <baz\+0x304>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> b2ff lw v0,00010408 <baz\+0x308>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f400 0a00 la v0,00010410 <baz\+0x310>
+[0-9a-f]+ <[^>]*> f400 b200 lw v0,00010414 <baz\+0x314>
+[0-9a-f]+ <[^>]*> f7ff 0a1c la v0,00010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ff b21c lw v0,00010018 <foo\+0x18>
+[0-9a-f]+ <[^>]*> f7ef 0a1f la v0,0001801f <baz\+0x7f1f>
+[0-9a-f]+ <[^>]*> f7ef b21f lw v0,00018023 <baz\+0x7f23>
+[0-9a-f]+ <[^>]*> f010 0a00 la v0,00008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f010 b200 lw v0,0000802c <bar\+0x802c>
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 4a1f addiu v0,32767
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 9a5f lw v0,32767\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> f7ff 6a1f li v0,65535
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 4a1e addiu v0,32766
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> f7ff 6a1f li v0,65535
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 9a5e lw v0,32766\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:25: Error: operand value out of range for instruction
+.*:26: Error: operand value out of range for instruction
+.*:27: Error: operand value out of range for instruction
+.*:28: Error: operand value out of range for instruction
--- /dev/null
+ .text
+
+bar:
+ .space 0x10000
+
+ .ent foo
+ .set mips16
+foo:
+ la $2, . - 1
+ nop
+ lw $2, . - 1
+ nop
+ la $2, . - 1 + 0x3fc
+ nop
+ lw $2, . - 1 + 0x3fc
+ nop
+ la $2, . - 1 + 0x400
+ lw $2, . - 1 + 0x400
+ la $2, . - 1 - 0x4
+ lw $2, . - 1 - 0x4
+ la $2, . - 1 + 0x7fff
+ lw $2, . - 1 + 0x7fff
+ la $2, . - 1 - 0x8000
+ lw $2, . - 1 - 0x8000
+ la $2, . - 1 + 0x8000
+ lw $2, . - 1 + 0x8000
+ la $2, . - 1 - 0x8001
+ lw $2, . - 1 - 0x8001
+ nop
+ .set nomips16
+ .end foo
+
+baz:
+ .align 8, 0
+ .space 0xfe00
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operations 1
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> fe40 dla v0,00010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fc40 ld v0,00010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fe5f dla v0,00010084 <baz\+0x4>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fc5f ld v0,00010100 <baz\+0x80>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f080 fe40 dla v0,00010090 <baz\+0x10>
+[0-9a-f]+ <[^>]*> f100 fc40 ld v0,00010110 <baz\+0x90>
+[0-9a-f]+ <[^>]*> f7ff fe5c dla v0,00010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ff fc5c ld v0,00010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ef fe5f dla v0,0001801f <baz\+0x7f9f>
+[0-9a-f]+ <[^>]*> f7ef fc5f ld v0,0001801f <baz\+0x7f9f>
+[0-9a-f]+ <[^>]*> f010 fe40 dla v0,00008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f010 fc40 ld v0,00008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef fd5f daddiu v0,32767
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 3a5b ld v0,32763\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> f7ff 6a1f li v0,65535
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef fd5e daddiu v0,32766
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> f7ff 6a1f li v0,65535
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 3a5a ld v0,32762\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:25: Error: operand value out of range for instruction
+.*:26: Error: operand value out of range for instruction
+.*:27: Error: operand value out of range for instruction
+.*:28: Error: operand value out of range for instruction
--- /dev/null
+ .text
+
+bar:
+ .space 0x10000
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, . - 1
+ nop
+ ld $2, . - 5
+ nop
+ dla $2, . - 1 + 0x7c
+ nop
+ ld $2, . - 5 + 0xf8
+ nop
+ dla $2, . - 1 + 0x80
+ ld $2, . - 5 + 0x100
+ dla $2, . - 1 - 0x4
+ ld $2, . - 5 - 0x4
+ dla $2, . - 1 + 0x7fff
+ ld $2, . - 5 + 0x7fff
+ dla $2, . - 1 - 0x8000
+ ld $2, . - 5 - 0x8000
+ dla $2, . - 1 + 0x8000
+ ld $2, . - 5 + 0x8000
+ dla $2, . - 1 - 0x8001
+ ld $2, . - 5 - 0x8001
+ nop
+ .set nomips16
+ .end foo
+
+baz:
+ .align 7, 0
+ .space 0xff00
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operations 2
+#as: -32
+#stderr: mips16-pcrel-2.l
+#dump: mips16-pcrel-0.d
--- /dev/null
+.*: Assembler messages:
+.*:27: Warning: macro instruction expanded into multiple instructions
+.*:28: Warning: macro instruction expanded into multiple instructions
+.*:29: Warning: macro instruction expanded into multiple instructions
+.*:30: Warning: macro instruction expanded into multiple instructions
--- /dev/null
+ .text
+
+bar:
+ .space 0x10000
+
+ .ent foo
+ .set mips16
+ .set noreorder
+ .set nomacro
+foo:
+ la $2, . - 1
+ nop
+ lw $2, . - 1
+ nop
+ la $2, . - 1 + 0x3fc
+ nop
+ lw $2, . - 1 + 0x3fc
+ nop
+ la $2, . - 1 + 0x400
+ lw $2, . - 1 + 0x400
+ la $2, . - 1 - 0x4
+ lw $2, . - 1 - 0x4
+ la $2, . - 1 + 0x7fff
+ lw $2, . - 1 + 0x7fff
+ la $2, . - 1 - 0x8000
+ lw $2, . - 1 - 0x8000
+ la $2, . - 1 + 0x8000
+ lw $2, . - 1 + 0x8000
+ la $2, . - 1 - 0x8001
+ lw $2, . - 1 - 0x8001
+ nop
+ .set macro
+ .set reorder
+ .set nomips16
+ .end foo
+
+baz:
+ .align 8, 0
+ .space 0xfe00
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#name: MIPS16 PC-relative operations 3
+#as: -32
+#error-output: mips16-pcrel-3.l
--- /dev/null
+.*: Assembler messages:
+.*:13: Error: operand value out of range for instruction
+.*:14: Error: operand value out of range for instruction
+.*:15: Error: operand value out of range for instruction
+.*:16: Error: operand value out of range for instruction
+.*:17: Error: unsupported relocation
+.*:18: Error: unsupported relocation
--- /dev/null
+ .text
+
+ .space 0x10000
+
+ .ent foo
+ .set mips16
+ .set noautoextend
+foo:
+ la.e $2, . - 1 + 0x7fff
+ lw.e $2, . - 1 + 0x7fff
+ la.e $2, . - 1 - 0x8000
+ lw.e $2, . - 1 - 0x8000
+ la.e $2, . - 1 + 0x8000
+ lw.e $2, . - 1 + 0x8000
+ la.e $2, . - 1 - 0x8001
+ lw.e $2, . - 1 - 0x8001
+ la.e $2, bar
+ lw.e $2, bar
+ nop
+ .set autoextend
+ .set nomips16
+ .end foo
+
+ .align 8, 0
+ .space 0xfe00
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#name: MIPS16 PC-relative operations 4
+#as: -32
+#error-output: mips16-pcrel-4.l
--- /dev/null
+.*: Assembler messages:
+.*:16: Error: invalid unextended operand value
+.*:18: Error: invalid unextended operand value
+.*:20: Error: invalid unextended operand value
+.*:22: Error: invalid unextended operand value
+.*:24: Error: invalid unextended operand value
+.*:26: Error: invalid unextended operand value
+.*:28: Error: invalid unextended operand value
+.*:30: Error: invalid unextended operand value
+.*:32: Error: invalid unextended operand value
+.*:34: Error: invalid unextended operand value
+.*:36: Error: invalid unextended operand value
+.*:38: Error: invalid unextended operand value
+.*:40: Error: unsupported relocation
+.*:42: Error: unsupported relocation
--- /dev/null
+ .text
+
+ .space 0x10000
+
+ .ent foo
+ .set mips16
+foo:
+ la.t $2, . - 1
+ nop
+ lw.t $2, . - 1
+ nop
+ la.t $2, . - 1 + 0x3fc
+ nop
+ lw.t $2, . - 1 + 0x3fc
+ nop
+ la.t $2, . - 1 + 0x400
+ nop
+ lw.t $2, . - 1 + 0x400
+ nop
+ la.t $2, . - 1 - 0x4
+ nop
+ lw.t $2, . - 1 - 0x4
+ nop
+ la.t $2, . - 1 + 0x7fff
+ nop
+ lw.t $2, . - 1 + 0x7fff
+ nop
+ la.t $2, . - 1 - 0x8000
+ nop
+ lw.t $2, . - 1 - 0x8000
+ nop
+ la.t $2, . - 1 + 0x8000
+ nop
+ lw.t $2, . - 1 + 0x8000
+ nop
+ la.t $2, . - 1 - 0x8001
+ nop
+ lw.t $2, . - 1 - 0x8001
+ nop
+ la.t $2, bar
+ nop
+ lw.t $2, bar
+ nop
+ .set nomips16
+ .end foo
+
+ .align 8, 0
+ .space 0xfe00
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#name: MIPS16 PC-relative operations 5
+#as: -32
+#error-output: mips16-pcrel-5.l
--- /dev/null
+.*: Assembler messages:
+.*:17: Error: invalid unextended operand value
+.*:19: Error: invalid unextended operand value
+.*:21: Error: invalid unextended operand value
+.*:23: Error: invalid unextended operand value
+.*:25: Error: invalid unextended operand value
+.*:27: Error: invalid unextended operand value
+.*:29: Error: invalid unextended operand value
+.*:31: Error: invalid unextended operand value
+.*:33: Error: invalid unextended operand value
+.*:35: Error: invalid unextended operand value
+.*:37: Error: invalid unextended operand value
+.*:39: Error: invalid unextended operand value
+.*:41: Error: unsupported relocation
+.*:43: Error: unsupported relocation
--- /dev/null
+ .text
+
+ .space 0x10000
+
+ .ent foo
+ .set mips16
+ .set noautoextend
+foo:
+ la $2, . - 1
+ nop
+ lw $2, . - 1
+ nop
+ la $2, . - 1 + 0x3fc
+ nop
+ lw $2, . - 1 + 0x3fc
+ nop
+ la $2, . - 1 + 0x400
+ nop
+ lw $2, . - 1 + 0x400
+ nop
+ la $2, . - 1 - 0x4
+ nop
+ lw $2, . - 1 - 0x4
+ nop
+ la $2, . - 1 + 0x7fff
+ nop
+ lw $2, . - 1 + 0x7fff
+ nop
+ la $2, . - 1 - 0x8000
+ nop
+ lw $2, . - 1 - 0x8000
+ nop
+ la $2, . - 1 + 0x8000
+ nop
+ lw $2, . - 1 + 0x8000
+ nop
+ la $2, . - 1 - 0x8001
+ nop
+ lw $2, . - 1 - 0x8001
+ nop
+ la $2, bar
+ nop
+ lw $2, bar
+ nop
+ .set autoextend
+ .set nomips16
+ .end foo
+
+ .align 8, 0
+ .space 0xfe00
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative reference to absolute expression 1
#as: -32
-#error-output: mips16-pcrel-absolute-1.l
+#dump: mips16-pcrel-absolute.d
+++ /dev/null
-.*: Assembler messages:
-.*:10: Error: unsupported relocation
-.*:11: Error: unsupported relocation
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 2
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 fd54 daddiu v0,4660
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 3a54 ld v0,4660\(v0\)
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, bar
+ ld $2, bar
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+
+ .set bar, 0x1234
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 3
+#as: -32 -mips3
+#dump: mips16-pcrel-absolute-2.d
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .set bar, 0x1234
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, bar
+ ld $2, bar
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 4
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 4a18 addiu v0,22136
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 9a58 lw v0,22136\(v0\)
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 4a18 addiu v0,22136
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 9a58 lw v0,22136\(v0\)
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f2ef 4a00 addiu v0,31456
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f2ef 9a40 lw v0,31456\(v0\)
+[0-9a-f]+ <[^>]*> f464 6a09 li v0,9321
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f4f5 4a00 addiu v0,-21280
+[0-9a-f]+ <[^>]*> f464 6a09 li v0,9321
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f4f5 9a40 lw v0,-21280\(v0\)
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:8: Error: unsupported relocation
+.*:9: Error: unsupported relocation
+.*:10: Error: unsupported relocation
+.*:11: Error: unsupported relocation
+.*:12: Error: unsupported relocation
+.*:13: Error: unsupported relocation
+.*:14: Error: unsupported relocation
+.*:15: Error: unsupported relocation
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .ent foo
+ .set mips16
+foo:
+ la $2, 0x12345678
+ lw $2, 0x12345678
+ la $2, bar
+ lw $2, bar
+ la $2, bar + 0x2468
+ lw $2, bar + 0x2468
+ la $2, 0x2468ace0
+ lw $2, 0x2468ace0
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+
+ .set bar, 0x12345678
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 5
+#as: -32
+#dump: mips16-pcrel-absolute-4.d
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .set bar, 0x12345678
+
+ .ent foo
+ .set mips16
+foo:
+ la $2, 0x12345678
+ lw $2, 0x12345678
+ la $2, bar
+ lw $2, bar
+ la $2, bar + 0x2468
+ lw $2, bar + 0x2468
+ la $2, 0x2468ace0
+ lw $2, 0x2468ace0
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 6
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a fd58 daddiu v0,22136
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 3a58 ld v0,22136\(v0\)
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a fd58 daddiu v0,22136
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 3a58 ld v0,22136\(v0\)
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f2ef fd40 daddiu v0,31456
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f2ef 3a40 ld v0,31456\(v0\)
+[0-9a-f]+ <[^>]*> f464 6a09 li v0,9321
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f4f5 fd40 daddiu v0,-21280
+[0-9a-f]+ <[^>]*> f464 6a09 li v0,9321
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f4f5 3a40 ld v0,-21280\(v0\)
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:8: Error: unsupported relocation
+.*:9: Error: unsupported relocation
+.*:10: Error: unsupported relocation
+.*:11: Error: unsupported relocation
+.*:12: Error: unsupported relocation
+.*:13: Error: unsupported relocation
+.*:14: Error: unsupported relocation
+.*:15: Error: unsupported relocation
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, 0x12345678
+ ld $2, 0x12345678
+ dla $2, bar
+ ld $2, bar
+ dla $2, bar + 0x2468
+ ld $2, bar + 0x2468
+ dla $2, 0x2468ace0
+ ld $2, 0x2468ace0
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+
+ .set bar, 0x12345678
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 7
+#as: -32 -mips3
+#dump: mips16-pcrel-absolute-6.d
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .set bar, 0x12345678
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, 0x12345678
+ ld $2, 0x12345678
+ dla $2, bar
+ ld $2, bar
+ dla $2, bar + 0x2468
+ ld $2, bar + 0x2468
+ dla $2, 0x2468ace0
+ ld $2, 0x2468ace0
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 4 (n32)
+#as: -n32 -mips3
+#source: mips16-pcrel-absolute-4.s
+#dump: mips16-pcrel-absolute-4.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 6 (n32)
+#as: -n32 -mips3
+#source: mips16-pcrel-absolute-6.s
+#dump: mips16-pcrel-absolute-6.d
--- /dev/null
+#name: MIPS16 PC-relative reference to absolute expression 4 (n64)
+#as: -64 -mips3
+#source: mips16-pcrel-absolute-4.s
+#error-output: mips16-pcrel-absolute-4.l
--- /dev/null
+#name: MIPS16 PC-relative reference to absolute expression 6 (n64)
+#as: -64 -mips3
+#source: mips16-pcrel-absolute-6.s
+#error-output: mips16-pcrel-absolute-6.l
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 4 (n64, sym32)
+#as: -64 -msym32 -mips3
+#source: mips16-pcrel-absolute-4.s
+#dump: mips16-pcrel-absolute-4.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 6 (n64, sym32)
+#as: -64 -msym32 -mips3
+#source: mips16-pcrel-absolute-6.s
+#dump: mips16-pcrel-absolute-6.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 4 (PIC)
+#as: -32 -call_shared
+#source: mips16-pcrel-absolute-4.s
+#dump: mips16-pcrel-absolute-4.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 6 (PIC)
+#as: -32 -mips3 -call_shared
+#source: mips16-pcrel-absolute-6.s
+#dump: mips16-pcrel-absolute-6.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 4 (PIC, n32)
+#as: -n32 -call_shared -mips3
+#source: mips16-pcrel-absolute-4.s
+#dump: mips16-pcrel-absolute-4.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 6 (PIC, n32)
+#as: -n32 -call_shared -mips3
+#source: mips16-pcrel-absolute-6.s
+#dump: mips16-pcrel-absolute-6.d
--- /dev/null
+#name: MIPS16 PC-relative reference to absolute expression 4 (PIC, n64)
+#as: -64 -call_shared -mips3
+#source: mips16-pcrel-absolute-4.s
+#error-output: mips16-pcrel-absolute-4.l
--- /dev/null
+#name: MIPS16 PC-relative reference to absolute expression 6 (PIC, n64)
+#as: -64 -call_shared -mips3
+#source: mips16-pcrel-absolute-6.s
+#error-output: mips16-pcrel-absolute-6.l
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 4 (PIC, n64, sym32)
+#as: -64 -msym32 -call_shared -mips3
+#source: mips16-pcrel-absolute-4.s
+#dump: mips16-pcrel-absolute-4.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative reference to absolute expression 6 (PIC, n64, sym32)
+#as: -64 -msym32 -call_shared -mips3
+#source: mips16-pcrel-absolute-6.s
+#dump: mips16-pcrel-absolute-6.d
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative reference to absolute expression
#as: -32
-#error-output: mips16-pcrel-absolute.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 4a14 addiu v0,4660
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 9a54 lw v0,4660\(v0\)
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+++ /dev/null
-.*: Assembler messages:
-.*:8: Error: unsupported relocation
-.*:9: Error: unsupported relocation
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative relocation with addend 2
#as: -32
-#error-output: mips16-pcrel-addend-2.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 4a14 addiu v0,4660
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 9a54 lw v0,4660\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
+++ /dev/null
-.*: Assembler messages:
-.*:9: Error: unsupported relocation
-.*:10: Error: unsupported relocation
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative relocation with addend 3
#as: -32
-#error-output: mips16-pcrel-addend-3.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 4a14 addiu v0,4660
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 9a54 lw v0,4660\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+++ /dev/null
-.*: Assembler messages:
-.*:8: Error: unsupported relocation
-.*:9: Error: unsupported relocation
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 4
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f242 fe54 dla v0,00002254 <bar\+0x1234>
+[0-9a-f]+ <[^>]*> f242 fc54 ld v0,00002254 <bar\+0x1234>
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, bar + 0x1234
+ ld $2, bar + 0x1234
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+
+ .type bar, @object
+bar:
+ .long 0
+ .size bar, . - bar
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 5
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> f202 fe54 dla v0,00002234 <foo\+0x1214>
+[0-9a-f]+ <[^>]*> f202 fc54 ld v0,00002234 <foo\+0x1214>
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .type bar, @object
+bar:
+ .long 0
+ .size bar, . - bar
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, bar + 0x1234
+ ld $2, bar + 0x1234
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 6
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 fd54 daddiu v0,4660
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 3a54 ld v0,4660\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+ .text
+ .globl bar
+
+ .space 0x1000
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, bar + 0x1234
+ ld $2, bar + 0x1234
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
+
+ .type bar, @object
+bar:
+ .long 0
+ .size bar, . - bar
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 7
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 fd54 daddiu v0,4660
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f222 3a54 ld v0,4660\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, bar + 0x1234
+ ld $2, bar + 0x1234
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 8
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f464 4a08 addiu v0,9320
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f464 9a48 lw v0,9320\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 4a18 addiu v0,22136
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 9a58 lw v0,22136\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f464 6a09 li v0,9321
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f4f5 4a00 addiu v0,-21280
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f464 6a09 li v0,9321
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f4f5 9a40 lw v0,-21280\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:8: Error: unsupported relocation
+.*:9: Error: unsupported relocation
+.*:10: Error: unsupported relocation
+.*:11: Error: unsupported relocation
+.*:12: Error: unsupported relocation
+.*:13: Error: unsupported relocation
+.*:14: Error: unsupported relocation
+.*:15: Error: unsupported relocation
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .ent foo
+ .set mips16
+foo:
+ la $2, bar
+ lw $2, bar
+ la $2, bar + 0x2468
+ lw $2, bar + 0x2468
+ la $2, bar + 0x12345678
+ lw $2, bar + 0x12345678
+ la $2, bar + 0x2468ace0
+ lw $2, bar + 0x2468ace0
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 9
+#as: -32 -mips3
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f464 fd48 daddiu v0,9320
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f464 3a48 ld v0,9320\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a fd58 daddiu v0,22136
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f222 6a14 li v0,4660
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f66a 3a58 ld v0,22136\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f464 6a09 li v0,9321
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f4f5 fd40 daddiu v0,-21280
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f464 6a09 li v0,9321
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f4f5 3a40 ld v0,-21280\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:8: Error: unsupported relocation
+.*:9: Error: unsupported relocation
+.*:10: Error: unsupported relocation
+.*:11: Error: unsupported relocation
+.*:12: Error: unsupported relocation
+.*:13: Error: unsupported relocation
+.*:14: Error: unsupported relocation
+.*:15: Error: unsupported relocation
--- /dev/null
+ .text
+
+ .space 0x1000
+
+ .ent foo
+ .set mips16
+foo:
+ dla $2, bar
+ ld $2, bar
+ dla $2, bar + 0x2468
+ ld $2, bar + 0x2468
+ dla $2, bar + 0x12345678
+ ld $2, bar + 0x12345678
+ dla $2, bar + 0x2468ace0
+ ld $2, bar + 0x2468ace0
+ nop
+ .set nomips16
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 8 (n32)
+#as: -n32 -mips3
+#source: mips16-pcrel-addend-8.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 9 (n32)
+#as: -n32 -mips3
+#source: mips16-pcrel-addend-9.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+#name: MIPS16 PC-relative relocation with addend 8 (n64)
+#as: -64 -mips3
+#source: mips16-pcrel-addend-8.s
+#error-output: mips16-pcrel-addend-8.l
--- /dev/null
+#name: MIPS16 PC-relative relocation with addend 9 (n64)
+#as: -64 -mips3
+#source: mips16-pcrel-addend-9.s
+#error-output: mips16-pcrel-addend-9.l
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 8 (n64, sym32)
+#as: -64 -msym32 -mips3
+#source: mips16-pcrel-addend-8.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative relocation with addend 9 (n64, sym32)
+#as: -64 -msym32 -mips3
+#source: mips16-pcrel-addend-9.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x12345678
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x2468ace0
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
--- /dev/null
+#name: MIPS16 PC-relative relocation with addend 8 (PIC)
+#as: -32 -call_shared
+#source: mips16-pcrel-addend-8.s
+#error-output: mips16-pcrel-addend-8.l
--- /dev/null
+#name: MIPS16 PC-relative relocation with addend 9 (PIC)
+#as: -32 -mips3 -call_shared
+#source: mips16-pcrel-addend-9.s
+#error-output: mips16-pcrel-addend-9.l
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operation in delay slot 0
+#as: -32
+#stderr: mips16-pcrel-delay-0.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> ec00 jr a0
+[0-9a-f]+ <[^>]*> 0aff la v0,000103fc <baz\+0x2fc>
+[0-9a-f]+ <[^>]*> e820 jr ra
+[0-9a-f]+ <[^>]*> b2ff lw v0,00010400 <baz\+0x300>
+[0-9a-f]+ <[^>]*> ec00 jr a0
+[0-9a-f]+ <[^>]*> f7ef 0a1f la v0,00018007 <baz\+0x7f07>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> e820 jr ra
+[0-9a-f]+ <[^>]*> f7ef b21f lw v0,0001800f <baz\+0x7f0f>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> ec00 jr a0
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 4a1d addiu v0,32765
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> e820 jr ra
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 9a5d lw v0,32765\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:15: Warning: extended instruction in a branch delay slot
+.*:18: Warning: extended instruction in a branch delay slot
+.*:21: Warning: macro instruction expanded into multiple instructions in a branch delay slot
+.*:24: Warning: macro instruction expanded into multiple instructions in a branch delay slot
--- /dev/null
+ .text
+
+bar:
+ .space 0x10000
+
+ .ent foo
+ .set mips16
+ .set noreorder
+foo:
+ jr $4
+ la $2, . - 3 + 0x3fc
+ jr $ra
+ lw $2, . - 3 + 0x3fc
+ jr $4
+ la $2, . - 3 + 0x7fff
+ nop
+ jr $ra
+ lw $2, . - 3 + 0x7fff
+ nop
+ jr $4
+ la $2, . - 3 + 0x8000
+ nop
+ jr $ra
+ lw $2, . - 3 + 0x8000
+ nop
+ .set reorder
+ .set nomips16
+ .end foo
+
+baz:
+ .align 8, 0
+ .space 0xfe00
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operation in delay slot 1
+#as: -32
+#stderr: mips16-pcrel-delay-1.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> 1800 0000 jal 00000000 <bar>
+[ ]*[0-9a-f]+: R_MIPS16_26 bat
+[0-9a-f]+ <[^>]*> 0aff la v0,000103fc <baz\+0x2fc>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> 1c00 0000 jalx 00000000 <bar>
+[ ]*[0-9a-f]+: R_MIPS16_26 bax
+[0-9a-f]+ <[^>]*> b2ff lw v0,00010404 <baz\+0x304>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> 1800 0000 jal 00000000 <bar>
+[ ]*[0-9a-f]+: R_MIPS16_26 bat
+[0-9a-f]+ <[^>]*> f7ef 0a1f la v0,00018013 <baz\+0x7f13>
+[0-9a-f]+ <[^>]*> 1c00 0000 jalx 00000000 <bar>
+[ ]*[0-9a-f]+: R_MIPS16_26 bax
+[0-9a-f]+ <[^>]*> f7ef b21f lw v0,0001801b <baz\+0x7f1b>
+[0-9a-f]+ <[^>]*> 1800 0000 jal 00000000 <bar>
+[ ]*[0-9a-f]+: R_MIPS16_26 bat
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 4a1b addiu v0,32763
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> 1c00 0000 jalx 00000000 <bar>
+[ ]*[0-9a-f]+: R_MIPS16_26 bax
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f7ef 9a5b lw v0,32763\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+.*: Assembler messages:
+.*:17: Warning: extended instruction in a branch delay slot
+.*:19: Warning: extended instruction in a branch delay slot
+.*:21: Warning: macro instruction expanded into multiple instructions in a branch delay slot
+.*:23: Warning: macro instruction expanded into multiple instructions in a branch delay slot
--- /dev/null
+ .text
+
+bar:
+ .space 0x10000
+
+ .ent foo
+ .set mips16
+ .set noreorder
+foo:
+ jal bat
+ la $2, . - 5 + 0x3fc
+ nop
+ jalx bax
+ lw $2, . - 5 + 0x3fc
+ nop
+ jal bat
+ la $2, . - 5 + 0x7fff
+ jalx bax
+ lw $2, . - 5 + 0x7fff
+ jal bat
+ la $2, . - 5 + 0x8000
+ jalx bax
+ lw $2, . - 5 + 0x8000
+ nop
+ .set reorder
+ .set nomips16
+ .end foo
+
+baz:
+ .align 8, 0
+ .space 0xfe00
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operations 0 (n32)
+#as: -n32 -mips3
+#source: mips16-pcrel-0.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> 0a00 la v0,00010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> b200 lw v0,00010004 <foo\+0x4>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> 0aff la v0,00010404 <baz\+0x304>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> b2ff lw v0,00010408 <baz\+0x308>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f400 0a00 la v0,00010410 <baz\+0x310>
+[0-9a-f]+ <[^>]*> f400 b200 lw v0,00010414 <baz\+0x314>
+[0-9a-f]+ <[^>]*> f7ff 0a1c la v0,00010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ff b21c lw v0,00010018 <foo\+0x18>
+[0-9a-f]+ <[^>]*> f7ef 0a1f la v0,0001801f <baz\+0x7f1f>
+[0-9a-f]+ <[^>]*> f7ef b21f lw v0,00018023 <baz\+0x7f23>
+[0-9a-f]+ <[^>]*> f010 0a00 la v0,00008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f010 b200 lw v0,0000802c <bar\+0x802c>
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001\+0x7fff
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001\+0x7fff
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001\+0x7fff
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001\+0x7fff
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001-0x8002
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001-0x8002
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001-0x8002
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001-0x8002
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operations 1 (n32)
+#as: -n32 -mips3
+#source: mips16-pcrel-1.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> fe40 dla v0,00010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fc40 ld v0,00010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fe5f dla v0,00010084 <baz\+0x4>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fc5f ld v0,00010100 <baz\+0x80>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f080 fe40 dla v0,00010090 <baz\+0x10>
+[0-9a-f]+ <[^>]*> f100 fc40 ld v0,00010110 <baz\+0x90>
+[0-9a-f]+ <[^>]*> f7ff fe5c dla v0,00010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ff fc5c ld v0,00010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ef fe5f dla v0,0001801f <baz\+0x7f9f>
+[0-9a-f]+ <[^>]*> f7ef fc5f ld v0,0001801f <baz\+0x7f9f>
+[0-9a-f]+ <[^>]*> f010 fe40 dla v0,00008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f010 fc40 ld v0,00008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001\+0x7fff
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001\+0x7fff
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001\+0x7ffb
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001\+0x7ffb
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001-0x8002
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001-0x8002
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001-0x8006
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001-0x8006
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#name: MIPS16 PC-relative operations 0 (n64)
+#as: -64 -mips3
+#source: mips16-pcrel-0.s
+#error-output: mips16-pcrel-0.l
--- /dev/null
+#name: MIPS16 PC-relative operations 1 (n64)
+#as: -64 -mips3
+#source: mips16-pcrel-1.s
+#error-output: mips16-pcrel-1.l
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operations 0 (n64, sym32)
+#as: -64 -msym32 -mips3
+#source: mips16-pcrel-0.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> 0a00 la v0,0000000000010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> b200 lw v0,0000000000010004 <foo\+0x4>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> 0aff la v0,0000000000010404 <baz\+0x304>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> b2ff lw v0,0000000000010408 <baz\+0x308>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f400 0a00 la v0,0000000000010410 <baz\+0x310>
+[0-9a-f]+ <[^>]*> f400 b200 lw v0,0000000000010414 <baz\+0x314>
+[0-9a-f]+ <[^>]*> f7ff 0a1c la v0,0000000000010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ff b21c lw v0,0000000000010018 <foo\+0x18>
+[0-9a-f]+ <[^>]*> f7ef 0a1f la v0,000000000001801f <baz\+0x7f1f>
+[0-9a-f]+ <[^>]*> f7ef b21f lw v0,0000000000018023 <baz\+0x7f23>
+[0-9a-f]+ <[^>]*> f010 0a00 la v0,0000000000008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f010 b200 lw v0,000000000000802c <bar\+0x802c>
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 PC-relative operations 1 (n64, sym32)
+#as: -64 -msym32 -mips3
+#source: mips16-pcrel-1.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> fe40 dla v0,0000000000010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fc40 ld v0,0000000000010000 <foo>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fe5f dla v0,0000000000010084 <baz\+0x4>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fc5f ld v0,0000000000010100 <baz\+0x80>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f080 fe40 dla v0,0000000000010090 <baz\+0x10>
+[0-9a-f]+ <[^>]*> f100 fc40 ld v0,0000000000010110 <baz\+0x90>
+[0-9a-f]+ <[^>]*> f7ff fe5c dla v0,0000000000010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ff fc5c ld v0,0000000000010014 <foo\+0x14>
+[0-9a-f]+ <[^>]*> f7ef fe5f dla v0,000000000001801f <baz\+0x7f9f>
+[0-9a-f]+ <[^>]*> f7ef fc5f ld v0,000000000001801f <baz\+0x7f9f>
+[0-9a-f]+ <[^>]*> f010 fe40 dla v0,0000000000008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f010 fc40 ld v0,0000000000008028 <bar\+0x8028>
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7fff
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001\+0x7ffb
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7ffb
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7ffb
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001\+0x7ffb
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7ffb
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x7ffb
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8002
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 L0\001-0x8006
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8006
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8006
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 L0\001-0x8006
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8006
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x8006
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#name: MIPS16 PC-relative operations 0 (PIC)
+#as: -32 -call_shared
+#source: mips16-pcrel-0.s
+#error-output: mips16-pcrel-0.l
--- /dev/null
+#name: MIPS16 PC-relative operations 1 (PIC)
+#as: -32 -mips3 -call_shared
+#source: mips16-pcrel-1.s
+#error-output: mips16-pcrel-1.l
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative relocation 2
#as: -32
-#error-output: mips16-pcrel-reloc-2.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
+++ /dev/null
-.*: Assembler messages:
-.*:9: Error: unsupported relocation
-.*:10: Error: unsupported relocation
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative relocation 3
#as: -32
-#error-output: mips16-pcrel-reloc-3.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 9a40 lw v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+++ /dev/null
-.*: Assembler messages:
-.*:8: Error: unsupported relocation
-.*:9: Error: unsupported relocation
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative relocation 6
#as: -32 -mips3
-#error-output: mips16-pcrel-reloc-6.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
+++ /dev/null
-.*: Assembler messages:
-.*:9: Error: unsupported relocation
-.*:10: Error: unsupported relocation
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS16 PC-relative relocation 7
#as: -32 -mips3
-#error-output: mips16-pcrel-reloc-7.l
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 fd40 daddiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 3a40 ld v0,0\(v0\)
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+++ /dev/null
-.*: Assembler messages:
-.*:8: Error: unsupported relocation
-.*:9: Error: unsupported relocation
#name: MIPS relaxed macro with branch swapping
#as: -32
#source: relax-swap3.s
-#error-output: mips16@relax-swap3.l
-# This test used to cover the MIPS16 LA macro, but ceased to work when a
-# regression in MIPS16 relocation processing has been corrected, because
-# we have no external relocation available to represent the expression.
-# It is left in place to trigger if we ever get R_MIPS16_PC16 relocation
-# support.
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> eb00 jr v1
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 2300 beqz v1,[0-9a-f]+ <[^>]*>
+ \.\.\.
+++ /dev/null
-.*: Assembler messages:
-.*:5: Error: unsupported relocation
-.*:8: Error: unsupported relocation
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS relaxed macro with branch swapping
+#as: -32
+#source: relax-swap3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> eb80 jrc v1
+[0-9a-f]+ <[^>]*> f000 6a00 li v0,0
+[ ]*[0-9a-f]+: R_MIPS16_HI16 bar
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f000 4a00 addiu v0,0
+[ ]*[0-9a-f]+: R_MIPS16_LO16 bar
+[0-9a-f]+ <[^>]*> 2300 beqz v1,[0-9a-f]+ <[^>]*>
+ \.\.\.
0:
.insn
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
- .align 2
- .space 8
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 16
+ .align 4, 0
+2017-05-03 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/ld-mips-elf/mips16-pcrel-0.d: New test.
+ * testsuite/ld-mips-elf/mips16-pcrel-1.d: New test.
+ * testsuite/ld-mips-elf/mips16-pcrel-addend-2.d: New test.
+ * testsuite/ld-mips-elf/mips16-pcrel-addend-6.d: New test.
+ * testsuite/ld-mips-elf/mips16-pcrel-n32-0.d: New test.
+ * testsuite/ld-mips-elf/mips16-pcrel-n32-1.d: New test.
+ * testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-0.d: New test.
+ * testsuite/ld-mips-elf/mips16-pcrel-n64-sym32-1.d: New test.
+ * testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
+
2017-05-03 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/ld-elf/pr21384.d: Adjusted to accommodate
[list [list ld $abi_ldflags(n64)]]
}
+run_dump_test "mips16-pcrel-0" [list [list ld $abi_ldflags(o32)]]
+run_dump_test "mips16-pcrel-1" [list [list ld $abi_ldflags(o32)]]
+run_dump_test "mips16-pcrel-addend-2" [list [list ld $abi_ldflags(o32)]]
+run_dump_test "mips16-pcrel-addend-6" [list [list ld $abi_ldflags(o32)]]
+if $has_newabi {
+ run_dump_test "mips16-pcrel-n32-0" [list [list ld $abi_ldflags(n32)]]
+ run_dump_test "mips16-pcrel-n32-1" [list [list ld $abi_ldflags(n32)]]
+ run_dump_test "mips16-pcrel-n64-sym32-0" [list [list ld $abi_ldflags(n64)]]
+ run_dump_test "mips16-pcrel-n64-sym32-1" [list [list ld $abi_ldflags(n64)]]
+}
+
run_dump_test "mips16-branch-2" [list [list ld $abi_ldflags(o32)]]
run_dump_test "mips16-branch-3" [list [list ld $abi_ldflags(o32)]]
run_dump_test "mips16-branch-addend-2" [list [list ld $abi_ldflags(o32)]]
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 link PC-relative operations 0
+#source: ../../../gas/testsuite/gas/mips/mips16-pcrel-0.s
+#as: -EB -32
+#ld: -EB -Ttext 0 -e 0
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> 0a00 la v0,0+010000 <.*>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> b200 lw v0,0+010004 <.*>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> 0aff la v0,0+010404 <.*>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> b2ff lw v0,0+010408 <.*>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f400 0a00 la v0,0+010410 <.*>
+[0-9a-f]+ <[^>]*> f400 b200 lw v0,0+010414 <.*>
+[0-9a-f]+ <[^>]*> f7ff 0a1c la v0,0+010014 <.*>
+[0-9a-f]+ <[^>]*> f7ff b21c lw v0,0+010018 <.*>
+[0-9a-f]+ <[^>]*> f7ef 0a1f la v0,0+01801f <.*>
+[0-9a-f]+ <[^>]*> f7ef b21f lw v0,0+018023 <.*>
+[0-9a-f]+ <[^>]*> f010 0a00 la v0,0+008028 <.*>
+[0-9a-f]+ <[^>]*> f010 b200 lw v0,0+00802c <.*>
+[0-9a-f]+ <[^>]*> f000 6a02 li v0,2
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f030 4a10 addiu v0,-32720
+[0-9a-f]+ <[^>]*> f000 6a02 li v0,2
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f030 9a5c lw v0,-32708\(v0\)
+[0-9a-f]+ <[^>]*> f000 6a01 li v0,1
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f050 4a07 addiu v0,-32697
+[0-9a-f]+ <[^>]*> f000 6a01 li v0,1
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f050 9a53 lw v0,-32685\(v0\)
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 link PC-relative operations 1
+#source: ../../../gas/testsuite/gas/mips/mips16-pcrel-1.s
+#as: -EB -32 -mips3
+#ld: -EB -Ttext 0 -e 0
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> fe40 dla v0,0+010000 <.*>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fc40 ld v0,0+010000 <.*>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fe5f dla v0,0+010084 <.*>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> fc5f ld v0,0+010100 <.*>
+[0-9a-f]+ <[^>]*> 6500 nop
+[0-9a-f]+ <[^>]*> f080 fe40 dla v0,0+010090 <.*>
+[0-9a-f]+ <[^>]*> f100 fc40 ld v0,0+010110 <.*>
+[0-9a-f]+ <[^>]*> f7ff fe5c dla v0,0+010014 <.*>
+[0-9a-f]+ <[^>]*> f7ff fc5c ld v0,0+010014 <.*>
+[0-9a-f]+ <[^>]*> f7ef fe5f dla v0,0+01801f <.*>
+[0-9a-f]+ <[^>]*> f7ef fc5f ld v0,0+01801f <.*>
+[0-9a-f]+ <[^>]*> f010 fe40 dla v0,0+008028 <.*>
+[0-9a-f]+ <[^>]*> f010 fc40 ld v0,0+008028 <.*>
+[0-9a-f]+ <[^>]*> f000 6a02 li v0,2
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f030 fd50 daddiu v0,-32720
+[0-9a-f]+ <[^>]*> f000 6a02 li v0,2
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f030 3a58 ld v0,-32712\(v0\)
+[0-9a-f]+ <[^>]*> f000 6a01 li v0,1
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f050 fd47 daddiu v0,-32697
+[0-9a-f]+ <[^>]*> f000 6a01 li v0,1
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f050 3a4f ld v0,-32689\(v0\)
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 link PC-relative relocation with addend 2
+#source: ../../../gas/testsuite/gas/mips/mips16-pcrel-addend-2.s
+#as: -EB -32
+#ld: -EB -Ttext 0x43210000 -e 0
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f328 6a01 li v0,17185
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f264 4a04 addiu v0,8804
+[0-9a-f]+ <[^>]*> f328 6a01 li v0,17185
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f264 9a44 lw v0,8804\(v0\)
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 link PC-relative relocation with addend 6
+#source: ../../../gas/testsuite/gas/mips/mips16-pcrel-addend-6.s
+#as: -EB -32 -mips3
+#ld: -EB -Ttext 0x43210000 -e 0
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> f328 6a01 li v0,17185
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f264 fd44 daddiu v0,8804
+[0-9a-f]+ <[^>]*> f328 6a01 li v0,17185
+[0-9a-f]+ <[^>]*> f400 3240 sll v0,16
+[0-9a-f]+ <[^>]*> f264 3a44 ld v0,8804\(v0\)
+[0-9a-f]+ <[^>]*> 6500 nop
+ \.\.\.
+ \.\.\.
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 link PC-relative operations 0 (n32)
+#source: ../../../gas/testsuite/gas/mips/mips16-pcrel-0.s
+#as: -EB -n32 -mips3
+#ld: -EB -Ttext 0 -e 0
+#dump: mips16-pcrel-0.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 link PC-relative operations 1 (n32)
+#source: ../../../gas/testsuite/gas/mips/mips16-pcrel-1.s
+#as: -EB -n32 -mips3
+#ld: -EB -Ttext 0 -e 0
+#dump: mips16-pcrel-1.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 link PC-relative operations 0 (n64, sym32)
+#source: ../../../gas/testsuite/gas/mips/mips16-pcrel-0.s
+#as: -EB -64 -msym32 -mips3
+#ld: -EB -Ttext 0 -e 0
+#dump: mips16-pcrel-0.d
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 link PC-relative operations 1 (n64, sym32)
+#source: ../../../gas/testsuite/gas/mips/mips16-pcrel-1.s
+#as: -EB -64 -msym32 -mips3
+#ld: -EB -Ttext 0 -e 0
+#dump: mips16-pcrel-1.d
projects / deliverable / binutils-gdb.git / commitdiff
