RISC-V: Linux signal frame support.

Make riscv_isa_flen available to the linux native code, and clean up duplicate
comments.

	gdb/
	* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
	(riscv_isa_flen): Likewise.  Drop static.
	* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
	(riscv_isa_flen): Likewise.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 4376263bbd216071ac58089b5d75e5eec8dd3d00..4d068ee86ca273cb1c0ac45f4233d5ed2634f2a1 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,10 @@
+2018-10-26  Jim Wilson  <jimw@sifive.com>
+
+       * riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
+       (riscv_isa_flen): Likewise.  Drop static.
+       * riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
+       (riscv_isa_flen): Likewise.  Declare.
+
 2018-10-26  Edjunior Barbosa Machado  <emachado@linux.vnet.ibm.com>
            Pedro Franco de Carvalho  <pedromfc@linux.ibm.com>
 

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index e4b35a01ffccb774f3767a490d9e887336614e15..4b5f38a8779838250b8b353b0d5ac9a36efa9cf8 100644 (file)
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -349,9 +349,7 @@ riscv_has_feature (struct gdbarch *gdbarch, char feature)
   return (misa & (1 << (feature - 'A'))) != 0;
 }
 
-/* Return the width in bytes  of the general purpose registers for GDBARCH.
-   Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
-   RV128.  */
+/* See riscv-tdep.h.  */
 
 int
 riscv_isa_xlen (struct gdbarch *gdbarch)
@@ -370,12 +368,9 @@ riscv_isa_xlen (struct gdbarch *gdbarch)
     }
 }
 
-/* Return the width in bytes of the floating point registers for GDBARCH.
-   If this architecture has no floating point registers, then return 0.
-   Possible values are 4, 8, or 16 for depending on which of single, double
-   or quad floating point support is available.  */
+/* See riscv-tdep.h.  */
 
-static int
+int
 riscv_isa_flen (struct gdbarch *gdbarch)
 {
   if (riscv_has_feature (gdbarch, 'Q'))

diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index e04e728f320974ba09f9c5d8f0befb8978e3ed90..2cb51b16c532037ff73b54dcafa5db1c641d1751 100644 (file)
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -84,9 +84,18 @@ struct gdbarch_tdep
   struct type *riscv_fpreg_q_type;
 };
 
-/* Return the width in bytes of the general purpose registers for GDBARCH.  */
+
+/* Return the width in bytes  of the general purpose registers for GDBARCH.
+   Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
+   RV128.  */
 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
 
+/* Return the width in bytes of the floating point registers for GDBARCH.
+   If this architecture has no floating point registers, then return 0.
+   Possible values are 4, 8, or 16 for depending on which of single, double
+   or quad floating point support is available.  */
+extern int riscv_isa_flen (struct gdbarch *gdbarch);
+
 /* Single step based on where the current instruction will take us.  */
 extern std::vector<CORE_ADDR> riscv_software_single_step
   (struct regcache *regcache);