* gas/config/tc-arm.c (do_t_mov_cmp): In unified syntax encode movs as

	lsls and not adds.
	* gas/testsuite/gas/arm/thumb2_it_auto.d: Update for change in movs encoding.
	gas/arm/thumb2_it.d: Likewise.
	gas/arm/thumb32.d: Likewise.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index bce83da542b31470591c7503e6c59a2936c8ca91..f1600c137abff5f03c9f082fc09bfa5556caa567 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+       * config/tc-arm.c (do_t_mov_cmp): In unified syntax encode movs as
+       lsls and not adds.
+
 2010-05-27  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
        * config/tc-arm.c (encode_thumb2_ldmstm): Make warning about

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 6675935f6c6e271a933a8fd524bfbdacb946572a..6cf37b12e38c34bdf5f5210f4f22a37b6cd1de81 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10369,8 +10369,8 @@ do_t_mov_cmp (void)
 
          case T_MNEM_movs:
            /* We know we have low registers at this point.
-              Generate ADD Rd, Rs, #0.  */
-           inst.instruction = T_OPCODE_ADD_I3;
+              Generate LSLS Rd, Rs, #0.  */
+           inst.instruction = T_OPCODE_LSL_I;
            inst.instruction |= Rn;
            inst.instruction |= Rm << 3;
            break;

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 26df217ec783182fa4fbff02f3a31e7d974cd780..b488019a2001c7103019d162c066b5283e277363 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2010-05-28  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
+
+       * gas/arm/thumb2_it_auto.d: Update for change in movs encoding.
+       gas/arm/thumb2_it.d: Likewise.
+       gas/arm/thumb32.d: Likewise.
+
 2010-05-27  Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
 
        * gas/arm/thumb2_ldmstm.d: Add new testcases.

diff --git a/gas/testsuite/gas/arm/thumb2_it.d b/gas/testsuite/gas/arm/thumb2_it.d
index ab31cdb5839302d6379ee3332817bd1345a9c4cf..b55bc6728ad6d996a22281b859269959f3a58832 100644 (file)
--- a/gas/testsuite/gas/arm/thumb2_it.d
+++ b/gas/testsuite/gas/arm/thumb2_it.d
@@ -45,7 +45,7 @@ Disassembly of section .text:
 0+062 <[^>]+> bf08             it      eq
 0+064 <[^>]+> 4640             moveq   r0, r8
 0+066 <[^>]+> 4608             mov     r0, r1
-0+068 <[^>]+> 1c08             adds    r0, r1, #0
+0+068 <[^>]+> 0008             lsls    r0, r1, #0
 0+06a <[^>]+> ea5f 0008        movs.w  r0, r8
 0+06e <[^>]+> bf01             itttt   eq
 0+070 <[^>]+> 43c8             mvneq   r0, r1

diff --git a/gas/testsuite/gas/arm/thumb2_it_auto.d b/gas/testsuite/gas/arm/thumb2_it_auto.d
index 3cd465d26af773a76c929579b2b1a6bb34a0ee86..91d82ca7f86581b1c988d4139c311083352833a2 100644 (file)
--- a/gas/testsuite/gas/arm/thumb2_it_auto.d
+++ b/gas/testsuite/gas/arm/thumb2_it_auto.d
@@ -45,7 +45,7 @@ Disassembly of section .text:
 0+062 <[^>]+> bf08             it      eq
 0+064 <[^>]+> 4640             moveq   r0, r8
 0+066 <[^>]+> 4608             mov     r0, r1
-0+068 <[^>]+> 1c08             adds    r0, r1, #0
+0+068 <[^>]+> 0008             lsls    r0, r1, #0
 0+06a <[^>]+> ea5f 0008        movs.w  r0, r8
 0+06e <[^>]+> bf01             itttt   eq
 0+070 <[^>]+> 43c8             mvneq   r0, r1

diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 530b86bc23c6e1253f3ca6dd46fd2a3e34e839b1..31278d8d4982a280559c7d1b8ca8093ef669875b 100644 (file)
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -618,9 +618,9 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> eb10 0f09   cmn\.w  r0, r9
 0[0-9a-f]+ <[^>]+> f110 0f81   cmn\.w  r0, #129        ; 0x81
 0[0-9a-f]+ <[^>]+> f115 0f81   cmn\.w  r5, #129        ; 0x81
-0[0-9a-f]+ <[^>]+> 1c00        adds    r0, r0, #0
+0[0-9a-f]+ <[^>]+> 0000        lsls    r0, r0, #0
 0[0-9a-f]+ <[^>]+> 4600        mov     r0, r0
-0[0-9a-f]+ <[^>]+> 1c05        adds    r5, r0, #0
+0[0-9a-f]+ <[^>]+> 0005        lsls    r5, r0, #0
 0[0-9a-f]+ <[^>]+> 4628        mov     r0, r5
 0[0-9a-f]+ <[^>]+> ea4f 4065   mov\.w  r0, r5, asr #17
 0[0-9a-f]+ <[^>]+> ea4f 0000   mov\.w  r0, r0