2009-07-17 H.J. Lu <hongjiu.lu@intel.com>

	* config/tc-i386.c (md_assemble): Check implicit registers
	only for instructions with 3 operands or less.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 576c8589502c3ee94a81a2c624dbce2bec39ca74..dba01f6822ba5e298f5e79940c53392a1caebdf2 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2009-07-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (md_assemble): Check implicit registers
+       only for instructions with 3 operands or less.
+
 2009-07-17  Nick Clifton  <nickc@redhat.com>
 
        * config/tc-avr.c (md_apply_fix): Cast fixup reloc type to avoid

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index f4660b4ec7dfed9649465c4f085ad71813c83f25..0862ab00a73fe1469cd7622d3c7634c49a219bf1 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -2821,12 +2821,15 @@ md_assemble (char *line)
   if (i.types[0].bitfield.imm1)
     i.imm_operands = 0;        /* kludge for shift insns.  */
 
-  for (j = 0; j < i.operands; j++)
-    if (i.types[j].bitfield.inoutportreg
-       || i.types[j].bitfield.shiftcount
-       || i.types[j].bitfield.acc
-       || i.types[j].bitfield.floatacc)
-      i.reg_operands--;
+  /* We only need to check those implicit registers for instructions
+     with 3 operands or less.  */
+  if (i.operands <= 3)
+    for (j = 0; j < i.operands; j++)
+      if (i.types[j].bitfield.inoutportreg
+         || i.types[j].bitfield.shiftcount
+         || i.types[j].bitfield.acc
+         || i.types[j].bitfield.floatacc)
+       i.reg_operands--;
 
   /* ImmExt should be processed after SSE2AVX.  */
   if (!i.tm.opcode_modifier.sse2avx