[AArch64] Add support for Cortex-A35
authorJames Greenhalgh <james.greenhalgh@arm.com>
Thu, 12 Nov 2015 12:04:22 +0000 (12:04 +0000)
committerMarcus Shawcroft <marcus.shawcroft@arm.com>
Thu, 12 Nov 2015 12:04:22 +0000 (12:04 +0000)
This patch adds support to the AArch64 back-end for the Cortex-A35
processor, as recently announced by ARM. The ARM Cortex-A35 provides
full support for the ARMv8-A architecture, including the CRC extension,
with optional Advanced-SIMD and Floating-Point support. We therefore set
feature flags for this CPU to AARCH64_ARCH_V8 and AARCH64_FEATURE_CRC, in
the same fashion as Cortex-A53 and Cortex-A57.

Tested in a cross environment for AArch64 with no issues.

gas/ChangeLog
gas/config/tc-aarch64.c
gas/doc/c-aarch64.texi

index 04f934ce043e7e6ccabda9f014210c62c1ba6970..5bbb713d8df2a0cc761e334833e1ee5ae428e5fd 100644 (file)
@@ -1,3 +1,8 @@
+2015-11-12  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add cortex-a35.
+       * doc/c-aarch64.texi (-mcpu=): Likewise.
+
 2015-11-12  James Greenhalgh  <james.greenhalgh@arm.com>
 
        * config/tc-arm.c (arm_cpus): Likewise.
index b45aac8f4bff58846dbd9f11e05ba99e5ab52a4f..e854b966f0b8a5464fbd0b0ab37830fd3714812f 100644 (file)
@@ -7676,6 +7676,8 @@ struct aarch64_cpu_option_table
    recognized by GCC.  */
 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
   {"all", AARCH64_ANY, NULL},
+  {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
+                                 AARCH64_FEATURE_CRC), "Cortex-A35"},
   {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                  AARCH64_FEATURE_CRC), "Cortex-A53"},
   {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8,
index e3ca09d2c9ba93251798fc8c86b9e37a02c823a4..e7e6ba449bddab2d7f507101dbf96d40fc9abe47 100644 (file)
@@ -55,6 +55,7 @@ file in ELF32 and ELF64 format respectively.  The default is @code{lp64}.
 This option specifies the target processor.  The assembler will issue an error
 message if an attempt is made to assemble an instruction which will not execute
 on the target processor.  The following processor names are recognized:
+@code{cortex-a35},
 @code{cortex-a53},
 @code{cortex-a57},
 @code{cortex-a72},
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