MIPS: asm: r4kcache: Add protected cache operation for EVA

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 789792eeb4f13e0ef08527357bded4dafb635601..cac279c65601d6ee91fb5db9b7413b56591e2ef4 100644 (file)
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -212,6 +212,20 @@ static inline void flush_scache_line(unsigned long addr)
        :                                                       \
        : "i" (op), "r" (addr))
 
+#define protected_cachee_op(op,addr)                           \
+       __asm__ __volatile__(                                   \
+       "       .set    push                    \n"             \
+       "       .set    noreorder               \n"             \
+       "       .set    mips0                   \n"             \
+       "       .set    eva                     \n"             \
+       "1:     cachee  %0, (%1)                \n"             \
+       "2:     .set    pop                     \n"             \
+       "       .section __ex_table,\"a\"       \n"             \
+       "       "STR(PTR)" 1b, 2b               \n"             \
+       "       .previous"                                      \
+       :                                                       \
+       : "i" (op), "r" (addr))
+
 /*
  * The next two are for badland addresses like signal trampolines.
  */
@@ -223,7 +237,11 @@ static inline void protected_flush_icache_line(unsigned long addr)
                break;
 
        default:
+#ifdef CONFIG_EVA
+               protected_cachee_op(Hit_Invalidate_I, addr);
+#else
                protected_cache_op(Hit_Invalidate_I, addr);
+#endif
                break;
        }
 }