ARM: sun6i: dt: Add PLL6 and SPI module clocks

The module clocks in the A31 are still compatible with the A10 one. Add the SPI
module clocks and the PLL6 in the device tree to allow their use by the SPI
controllers.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 092bf97c3005ab8214cc1ed15e0e1dd949617eb9..93d7bb6b1697280660fb9d1a959e9117a8427bbe 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -83,16 +83,12 @@
                        clocks = <&osc24M>;
                };
 
-               /*
-                * This is a dummy clock, to be used as placeholder on
-                * other mux clocks when a specific parent clock is not
-                * yet implemented. It should be dropped when the driver
-                * is complete.
-                */
-               pll6: pll6 {
+               pll6: clk@01c20028 {
                        #clock-cells = <0>;
-                       compatible = "fixed-clock";
-                       clock-frequency = <0>;
+                       compatible = "allwinner,sun6i-a31-pll6-clk";
+                       reg = <0x01c20028 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "pll6";
                };
 
                cpu: cpu@01c20050 {
@@ -192,6 +188,38 @@
                                        "apb2_uart1", "apb2_uart2", "apb2_uart3",
                                        "apb2_uart4", "apb2_uart5";
                };
+
+               spi0_clk: clk@01c200a0 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a0 0x4>;
+                       clocks = <&osc24M>, <&pll6>;
+                       clock-output-names = "spi0";
+               };
+
+               spi1_clk: clk@01c200a4 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a4 0x4>;
+                       clocks = <&osc24M>, <&pll6>;
+                       clock-output-names = "spi1";
+               };
+
+               spi2_clk: clk@01c200a8 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200a8 0x4>;
+                       clocks = <&osc24M>, <&pll6>;
+                       clock-output-names = "spi2";
+               };
+
+               spi3_clk: clk@01c200ac {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-mod0-clk";
+                       reg = <0x01c200ac 0x4>;
+                       clocks = <&osc24M>, <&pll6>;
+                       clock-output-names = "spi3";
+               };
        };
 
        soc@01c00000 {