powerpc/perf: Add BHRB constraint and IFM MMCRA handling for EBB

We want a way for users of EBB (Event Based Branches) to also access the
BHRB (Branch History Rolling Buffer). EBB does not interoperate with our
existing BHRB support, which is wired into the generic Linux branch
stack sampling support.

To support EBB & BHRB we add three new bits to the event code. The first
bit indicates that the event wants access to the BHRB, and the other two
bits indicate the desired IFM (Instruction Filtering Mode).

We allow multiple events to request access to the BHRB, but they must
agree on the IFM value. Events which are not interested in the BHRB can
also interoperate with events which do.

Finally we program the desired IFM value into MMCRA. Although we do this
for every event, we know that the value will be identical for all events
that request BHRB access.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 67aab104b9fefb9f05b439b635f9cd50848c8402..3ad363da05f6637e109637cef260a7cf942ffd9a 100644 (file)
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -64,9 +64,11 @@
  *
  *        60        56        52        48        44        40        36        32
  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- *   |                                 [      thresh_cmp     ]   [  thresh_ctl   ]
- *   |                                                                   |
- *   *- EBB (Linux)                      thresh start/stop OR FAB match -*
+ *   | | [ ]                           [      thresh_cmp     ]   [  thresh_ctl   ]
+ *   | |  |                                                              |
+ *   | |  *- IFM (Linux)                 thresh start/stop OR FAB match -*
+ *   | *- BHRB (Linux)
+ *   *- EBB (Linux)
  *
  *        28        24        20        16        12         8         4         0
  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
@@ -115,11 +117,19 @@
  *     MMCRA[63]    = 1                (SAMPLE_ENABLE)
  *     MMCRA[57:59] = sample[0:2]      (RAND_SAMP_ELIG)
  *    MMCRA[61:62] = sample[3:4]      (RAND_SAMP_MODE)
+ *
+ * if EBB and BHRB:
+ *     MMCRA[32:33] = IFM
  *
  */
 
 #define EVENT_EBB_MASK         1ull
 #define EVENT_EBB_SHIFT                PERF_EVENT_CONFIG_EBB_SHIFT
+#define EVENT_BHRB_MASK                1ull
+#define EVENT_BHRB_SHIFT       62
+#define EVENT_WANTS_BHRB       (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)
+#define EVENT_IFM_MASK         3ull
+#define EVENT_IFM_SHIFT                60
 #define EVENT_THR_CMP_SHIFT    40      /* Threshold CMP value */
 #define EVENT_THR_CMP_MASK     0x3ff
 #define EVENT_THR_CTL_SHIFT    32      /* Threshold control value (start/stop) */
@@ -144,6 +154,12 @@
 #define EVENT_IS_MARKED                (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
 #define EVENT_PSEL_MASK                0xff    /* PMCxSEL value */
 
+/* Bits defined by Linux */
+#define EVENT_LINUX_MASK       \
+       ((EVENT_EBB_MASK  << EVENT_EBB_SHIFT)                   |       \
+        (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)                  |       \
+        (EVENT_IFM_MASK  << EVENT_IFM_SHIFT))
+
 #define EVENT_VALID_MASK       \
        ((EVENT_THRESH_MASK    << EVENT_THRESH_SHIFT)           |       \
         (EVENT_SAMPLE_MASK    << EVENT_SAMPLE_SHIFT)           |       \
@@ -152,7 +168,7 @@
         (EVENT_UNIT_MASK      << EVENT_UNIT_SHIFT)             |       \
         (EVENT_COMBINE_MASK   << EVENT_COMBINE_SHIFT)          |       \
         (EVENT_MARKED_MASK    << EVENT_MARKED_SHIFT)           |       \
-        (EVENT_EBB_MASK       << EVENT_EBB_SHIFT)              |       \
+         EVENT_LINUX_MASK                                      |       \
          EVENT_PSEL_MASK)
 
 /* MMCRA IFM bits - POWER8 */
@@ -176,10 +192,11 @@
  *
  *        28        24        20        16        12         8         4         0
  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- *                   |   [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
- *              EBB -*    |                     |
- *                        |                     |      Count of events for each PMC.
- *      L1 I/D qualifier -*                     |        p1, p2, p3, p4, p5, p6.
+ *               [ ] |   [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
+ *                |  |    |                     |
+ *      BHRB IFM -*  |    |                     |      Count of events for each PMC.
+ *              EBB -*    |                     |        p1, p2, p3, p4, p5, p6.
+ *      L1 I/D qualifier -*                     |
  *                     nc - number of counters -*
  *
  * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
@@ -198,6 +215,9 @@
 #define CNST_EBB_VAL(v)                (((v) & EVENT_EBB_MASK) << 24)
 #define CNST_EBB_MASK          CNST_EBB_VAL(EVENT_EBB_MASK)
 
+#define CNST_IFM_VAL(v)                (((v) & EVENT_IFM_MASK) << 25)
+#define CNST_IFM_MASK          CNST_IFM_VAL(EVENT_IFM_MASK)
+
 #define CNST_L1_QUAL_VAL(v)    (((v) & 3) << 22)
 #define CNST_L1_QUAL_MASK      CNST_L1_QUAL_VAL(3)
 
@@ -244,6 +264,7 @@
 #define MMCRA_THR_SEL_SHIFT            16
 #define MMCRA_THR_CMP_SHIFT            32
 #define MMCRA_SDAR_MODE_TLB            (1ull << 42)
+#define MMCRA_IFM_SHIFT                        30
 
 
 static inline bool event_is_fab_match(u64 event)
@@ -277,7 +298,7 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
                        return -1;
 
                /* Ignore Linux defined bits when checking event below */
-               base_event = event & ~(EVENT_EBB_MASK << EVENT_EBB_SHIFT);
+               base_event = event & ~EVENT_LINUX_MASK;
 
                if (pmc >= 5 && base_event != 0x500fa && base_event != 0x600f4)
                        return -1;
@@ -347,6 +368,15 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
                /* EBB events must specify the PMC */
                return -1;
 
+       if (event & EVENT_WANTS_BHRB) {
+               if (!ebb)
+                       /* Only EBB events can request BHRB */
+                       return -1;
+
+               mask  |= CNST_IFM_MASK;
+               value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
+       }
+
        /*
         * All events must agree on EBB, either all request it or none.
         * EBB events are pinned & exclusive, so this should never actually
@@ -436,6 +466,11 @@ static int power8_compute_mmcr(u64 event[], int n_ev,
                        mmcra |= val << MMCRA_THR_CMP_SHIFT;
                }
 
+               if (event[i] & EVENT_WANTS_BHRB) {
+                       val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
+                       mmcra |= val << MMCRA_IFM_SHIFT;
+               }
+
                hwc[i] = pmc - 1;
        }