+2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
+ bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
+ bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
+ bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
+ * bfd-in2.h: Regenerate.
+ * cpu-arm.c (arch_info_struct): Add entries for above new
+ bfd_mach_arm values.
+ * elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
+ bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
+ architectures. Force assert failure for any new Tag_CPU_arch value.
+
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
* doc/bfdint.texi: Use command-line consistently when used in a
.#define bfd_mach_arm_ep9312 11
.#define bfd_mach_arm_iWMMXt 12
.#define bfd_mach_arm_iWMMXt2 13
+.#define bfd_mach_arm_5TEJ 14
+.#define bfd_mach_arm_6 15
+.#define bfd_mach_arm_6KZ 16
+.#define bfd_mach_arm_6T2 17
+.#define bfd_mach_arm_6K 18
+.#define bfd_mach_arm_7 19
+.#define bfd_mach_arm_6M 20
+.#define bfd_mach_arm_6SM 21
+.#define bfd_mach_arm_7EM 22
+.#define bfd_mach_arm_8 23
+.#define bfd_mach_arm_8R 24
+.#define bfd_mach_arm_8M_BASE 25
+.#define bfd_mach_arm_8M_MAIN 26
. bfd_arch_nds32, {* Andes NDS32. *}
.#define bfd_mach_n1 1
.#define bfd_mach_n1h 2
#define bfd_mach_arm_ep9312 11
#define bfd_mach_arm_iWMMXt 12
#define bfd_mach_arm_iWMMXt2 13
+#define bfd_mach_arm_5TEJ 14
+#define bfd_mach_arm_6 15
+#define bfd_mach_arm_6KZ 16
+#define bfd_mach_arm_6T2 17
+#define bfd_mach_arm_6K 18
+#define bfd_mach_arm_7 19
+#define bfd_mach_arm_6M 20
+#define bfd_mach_arm_6SM 21
+#define bfd_mach_arm_7EM 22
+#define bfd_mach_arm_8 23
+#define bfd_mach_arm_8R 24
+#define bfd_mach_arm_8M_BASE 25
+#define bfd_mach_arm_8M_MAIN 26
bfd_arch_nds32, /* Andes NDS32. */
#define bfd_mach_n1 1
#define bfd_mach_n1h 2
static const bfd_arch_info_type arch_info_struct[] =
{
- N (bfd_mach_arm_2, "armv2", FALSE, & arch_info_struct[1]),
- N (bfd_mach_arm_2a, "armv2a", FALSE, & arch_info_struct[2]),
- N (bfd_mach_arm_3, "armv3", FALSE, & arch_info_struct[3]),
- N (bfd_mach_arm_3M, "armv3m", FALSE, & arch_info_struct[4]),
- N (bfd_mach_arm_4, "armv4", FALSE, & arch_info_struct[5]),
- N (bfd_mach_arm_4T, "armv4t", FALSE, & arch_info_struct[6]),
- N (bfd_mach_arm_5, "armv5", FALSE, & arch_info_struct[7]),
- N (bfd_mach_arm_5T, "armv5t", FALSE, & arch_info_struct[8]),
- N (bfd_mach_arm_5TE, "armv5te", FALSE, & arch_info_struct[9]),
- N (bfd_mach_arm_XScale, "xscale", FALSE, & arch_info_struct[10]),
- N (bfd_mach_arm_ep9312, "ep9312", FALSE, & arch_info_struct[11]),
- N (bfd_mach_arm_iWMMXt, "iwmmxt", FALSE, & arch_info_struct[12]),
- N (bfd_mach_arm_iWMMXt2, "iwmmxt2", FALSE, & arch_info_struct[13]),
- N (bfd_mach_arm_unknown, "arm_any", FALSE, NULL)
+ N (bfd_mach_arm_2, "armv2", FALSE, & arch_info_struct[1]),
+ N (bfd_mach_arm_2a, "armv2a", FALSE, & arch_info_struct[2]),
+ N (bfd_mach_arm_3, "armv3", FALSE, & arch_info_struct[3]),
+ N (bfd_mach_arm_3M, "armv3m", FALSE, & arch_info_struct[4]),
+ N (bfd_mach_arm_4, "armv4", FALSE, & arch_info_struct[5]),
+ N (bfd_mach_arm_4T, "armv4t", FALSE, & arch_info_struct[6]),
+ N (bfd_mach_arm_5, "armv5", FALSE, & arch_info_struct[7]),
+ N (bfd_mach_arm_5T, "armv5t", FALSE, & arch_info_struct[8]),
+ N (bfd_mach_arm_5TE, "armv5te", FALSE, & arch_info_struct[9]),
+ N (bfd_mach_arm_XScale, "xscale", FALSE, & arch_info_struct[10]),
+ N (bfd_mach_arm_ep9312, "ep9312", FALSE, & arch_info_struct[11]),
+ N (bfd_mach_arm_iWMMXt, "iwmmxt", FALSE, & arch_info_struct[12]),
+ N (bfd_mach_arm_iWMMXt2, "iwmmxt2", FALSE, & arch_info_struct[13]),
+ N (bfd_mach_arm_5TEJ, "armv5tej", FALSE, & arch_info_struct[14]),
+ N (bfd_mach_arm_6, "armv6", FALSE, & arch_info_struct[15]),
+ N (bfd_mach_arm_6KZ, "armv6kz", FALSE, & arch_info_struct[16]),
+ N (bfd_mach_arm_6T2, "armv6t2", FALSE, & arch_info_struct[17]),
+ N (bfd_mach_arm_6K, "armv6k", FALSE, & arch_info_struct[18]),
+ N (bfd_mach_arm_7, "armv7", FALSE, & arch_info_struct[19]),
+ N (bfd_mach_arm_6M, "armv6-m", FALSE, & arch_info_struct[20]),
+ N (bfd_mach_arm_6SM, "armv6s-m", FALSE, & arch_info_struct[21]),
+ N (bfd_mach_arm_7EM, "armv7e-m", FALSE, & arch_info_struct[22]),
+ N (bfd_mach_arm_8, "armv8-a", FALSE, & arch_info_struct[23]),
+ N (bfd_mach_arm_8R, "armv8-r", FALSE, & arch_info_struct[24]),
+ N (bfd_mach_arm_8M_BASE, "armv8-m.base", FALSE, & arch_info_struct[25]),
+ N (bfd_mach_arm_8M_MAIN, "armv8-m.main", FALSE, & arch_info_struct[26]),
+ N (bfd_mach_arm_unknown, "arm_any", FALSE, NULL)
};
const bfd_arch_info_type bfd_arm_arch =
switch (arch)
{
+ case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
return bfd_mach_arm_5TE;
}
+ case TAG_CPU_ARCH_V5TEJ:
+ return bfd_mach_arm_5TEJ;
+ case TAG_CPU_ARCH_V6:
+ return bfd_mach_arm_6;
+ case TAG_CPU_ARCH_V6KZ:
+ return bfd_mach_arm_6KZ;
+ case TAG_CPU_ARCH_V6T2:
+ return bfd_mach_arm_6T2;
+ case TAG_CPU_ARCH_V6K:
+ return bfd_mach_arm_6K;
+ case TAG_CPU_ARCH_V7:
+ return bfd_mach_arm_7;
+ case TAG_CPU_ARCH_V6_M:
+ return bfd_mach_arm_6M;
+ case TAG_CPU_ARCH_V6S_M:
+ return bfd_mach_arm_6SM;
+ case TAG_CPU_ARCH_V7E_M:
+ return bfd_mach_arm_7EM;
+ case TAG_CPU_ARCH_V8:
+ return bfd_mach_arm_8;
+ case TAG_CPU_ARCH_V8R:
+ return bfd_mach_arm_8R;
+ case TAG_CPU_ARCH_V8M_BASE:
+ return bfd_mach_arm_8M_BASE;
+ case TAG_CPU_ARCH_V8M_MAIN:
+ return bfd_mach_arm_8M_MAIN;
+
default:
+ /* Force entry to be added for any new known Tag_CPU_arch value. */
+ BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
+
+ /* Unknown Tag_CPU_arch value. */
return bfd_mach_arm_unknown;
}
}
+2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
+ rather than hardcode their values.
+
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
* NEWS: Use command-line consistently when used in a compount word.
stable when new architectures are added. */
static const cpu_arch_ver_table cpu_arch_ver[] =
{
- {0, ARM_ARCH_V1},
- {0, ARM_ARCH_V2},
- {0, ARM_ARCH_V2S},
- {0, ARM_ARCH_V3},
- {0, ARM_ARCH_V3M},
- {1, ARM_ARCH_V4xM},
- {1, ARM_ARCH_V4},
- {2, ARM_ARCH_V4TxM},
- {2, ARM_ARCH_V4T},
- {3, ARM_ARCH_V5xM},
- {3, ARM_ARCH_V5},
- {3, ARM_ARCH_V5TxM},
- {3, ARM_ARCH_V5T},
- {4, ARM_ARCH_V5TExP},
- {4, ARM_ARCH_V5TE},
- {5, ARM_ARCH_V5TEJ},
- {6, ARM_ARCH_V6},
- {7, ARM_ARCH_V6Z},
- {7, ARM_ARCH_V6KZ},
- {9, ARM_ARCH_V6K},
- {8, ARM_ARCH_V6T2},
- {8, ARM_ARCH_V6KT2},
- {8, ARM_ARCH_V6ZT2},
- {8, ARM_ARCH_V6KZT2},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
+ {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
+ {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
+ {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
+ {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
+ {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
+ {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
+ {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
+ {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
+ {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
+ {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
+ {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
+ {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
+ {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
+ {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
/* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
always selected build attributes to match those of ARMv6-M
would be selected when fully respecting chronology of architectures.
It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
move them before ARMv7 architectures. */
- {11, ARM_ARCH_V6M},
- {12, ARM_ARCH_V6SM},
-
- {10, ARM_ARCH_V7},
- {10, ARM_ARCH_V7A},
- {10, ARM_ARCH_V7R},
- {10, ARM_ARCH_V7M},
- {10, ARM_ARCH_V7VE},
- {13, ARM_ARCH_V7EM},
- {14, ARM_ARCH_V8A},
- {14, ARM_ARCH_V8_1A},
- {14, ARM_ARCH_V8_2A},
- {14, ARM_ARCH_V8_3A},
- {16, ARM_ARCH_V8M_BASE},
- {17, ARM_ARCH_V8M_MAIN},
- {15, ARM_ARCH_V8R},
- {14, ARM_ARCH_V8_4A},
- {-1, ARM_ARCH_NONE}
+ {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
+ {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
+
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
+ {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
+ {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
+ {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
+ {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
+ {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
+ {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
+ {-1, ARM_ARCH_NONE}
};
/* Set an attribute if it has not already been set by the user. */
+2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
+ all FPU features and add mapping from new bfd_mach_arm values to
+ allowed CPU feature bits.
+
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
* NEWS: Use command-line consistently when used in a compount word.
.*: file format elf32-.*
-architecture: arm, flags 0x[0-9a-f]+:
+architecture: armv7, flags 0x[0-9a-f]+:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x[0-9a-f]+
.*: file format elf32-.*
-architecture: arm, flags 0x[0-9a-f]+:
+architecture: armv7, flags 0x[0-9a-f]+:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x[0-9a-f]+
.*: file format elf32-.*arm
-architecture: arm, flags 0x00000150:
+architecture: armv6t2, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
.*: file format elf32-.*arm
-architecture: arm, flags 0x00000112:
+architecture: armv6t2, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x.*
+2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
+ expected result.
+ * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
+ * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
+ * testsuite/ld-arm/tls-longplt.d: Likewise.
+
2018-06-29 Tamar Christina <tamar.christina@arm.com>
PR binutils/23192
/* Given a bfd_mach_arm_XXX value, this function fills in the fields
of the supplied arm_feature_set structure with bitmasks indicating
- the support base architectures and coprocessor extensions.
+ the supported base architectures and coprocessor extensions.
FIXME: This could more efficiently implemented as a constant array,
although it would also be less robust. */
select_arm_features (unsigned long mach,
arm_feature_set * features)
{
+ arm_feature_set arch_fset;
+ const arm_feature_set fpu_any = FPU_ANY;
+
#undef ARM_SET_FEATURES
#define ARM_SET_FEATURES(FSET) \
{ \
const arm_feature_set fset = FSET; \
- arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
- ARM_MERGE_FEATURE_SETS (*features, tmp, fset); \
+ arch_fset = fset; \
}
+ /* When several architecture versions share the same bfd_mach_arm_XXX value
+ the most featureful is chosen. */
switch (mach)
{
- case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
- case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
- case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
- case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
- case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
- case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
- case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
- case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
- case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
- case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
+ case bfd_mach_arm_2: ARM_SET_FEATURES (ARM_ARCH_V2); break;
+ case bfd_mach_arm_2a: ARM_SET_FEATURES (ARM_ARCH_V2S); break;
+ case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
+ case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
+ case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
+ case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
+ case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
+ case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
+ case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
+ case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
case bfd_mach_arm_ep9312:
- ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
- ARM_CEXT_MAVERICK | FPU_MAVERICK));
+ ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
+ ARM_CEXT_MAVERICK | FPU_MAVERICK));
break;
- case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
- case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
- /* If the machine type is unknown allow all
- architecture types and all extensions. */
- case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
+ case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
+ case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
+ case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;
+ case bfd_mach_arm_6: ARM_SET_FEATURES (ARM_ARCH_V6); break;
+ case bfd_mach_arm_6KZ: ARM_SET_FEATURES (ARM_ARCH_V6KZ); break;
+ case bfd_mach_arm_6T2: ARM_SET_FEATURES (ARM_ARCH_V6KZT2); break;
+ case bfd_mach_arm_6K: ARM_SET_FEATURES (ARM_ARCH_V6K); break;
+ case bfd_mach_arm_7: ARM_SET_FEATURES (ARM_ARCH_V7VE); break;
+ case bfd_mach_arm_6M: ARM_SET_FEATURES (ARM_ARCH_V6M); break;
+ case bfd_mach_arm_6SM: ARM_SET_FEATURES (ARM_ARCH_V6SM); break;
+ case bfd_mach_arm_7EM: ARM_SET_FEATURES (ARM_ARCH_V7EM); break;
+ case bfd_mach_arm_8:
+ {
+ /* Add bits for extensions that Armv8.4-A recognizes. */
+ arm_feature_set armv8_4_ext_fset
+ = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML);
+ ARM_SET_FEATURES (ARM_ARCH_V8_4A);
+ ARM_MERGE_FEATURE_SETS (arch_fset, arch_fset, armv8_4_ext_fset);
+ break;
+ }
+ case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
+ case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
+ case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
+ /* If the machine type is unknown allow all architecture types and all
+ extensions. */
+ case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
default:
abort ();
}
-
#undef ARM_SET_FEATURES
+
+ /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
+ and thus on bfd_mach_arm_XXX value. Therefore for a given
+ bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
+ ARM_MERGE_FEATURE_SETS (*features, arch_fset, fpu_any);
}
projects / deliverable / binutils-gdb.git / commitdiff
