Add MIPS SB1 machine

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index f14ff61eb6d3e51118c8d5224950afeeee2d1b69..1a95e81706de787095c8293f402ca5059b0fbca6 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -36,6 +36,17 @@
         (_bfd_mips_elf_final_write_processing): Add cases for
         bfd_mach_mips5 and bfd_mach_mips64.
 
+        * bfd/aoutx.h (NAME(aout,machine_type)): Add a
+        bfd_mach_mips_sb1 case.
+        * bfd/archures.c (bfd_mach_mips_sb1): New constant.
+        * bfd/bfd-in2.h (bfd_mach_mips_sb1): New constant.
+        * bfd/cpu-mips.c (I_sb1): New constant.
+        (arch_info_struct): Add entry for bfd_mach_mips_sb1.
+        * bfd/elf32-mips.c (elf_mips_mach): Add case for
+        E_MIPS_MACH_SB1.
+        (_bfd_mips_elf_final_write_processing): Add case for
+        bfd_mach_mips_sb1.
+
 2000-12-01      Joel Sherrill <joel@OARcorp.com>
 
        * config.bfd (arm-*-rtems*, a29k-*rtems*): New targets.

diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index 246742f8a3f11e24bb4b669c44ee3b20b3cbf295..f8612a87062e3188b6b24954958f0ee4d0daaefe 100644 (file)
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -780,6 +780,7 @@ NAME(aout,machine_type) (arch, machine, unknown)
     case bfd_mach_mips32_4k:
     case bfd_mach_mips5:
     case bfd_mach_mips64:
+    case bfd_mach_mips_sb1:
       /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc.  */
       arch_flags = M_MIPS2;
       break;

diff --git a/bfd/archures.c b/bfd/archures.c
index 1361be95509b7923c6aeb573c97a606233813603..5bc744a6f6d371641bc7e22d979493133e3224ae 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -135,6 +135,7 @@ DESCRIPTION
 .#define bfd_mach_mips32_4k             3204113 {* 32, 04, octal 'K' *}
 .#define bfd_mach_mips5                 5
 .#define bfd_mach_mips64                64
+.#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
 .  bfd_arch_i386,      {* Intel 386 *}
 .#define bfd_mach_i386_i386 0
 .#define bfd_mach_i386_i8086 1

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 021e7629cfe78eaed885102ef9c8c3d5a5364969..03794fae6762a8024b7d5042e9fa779138bbb55d 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1403,6 +1403,7 @@ enum bfd_architecture
 #define bfd_mach_mips32_4k             3204113 /* 32, 04, octal 'K' */
 #define bfd_mach_mips5                 5
 #define bfd_mach_mips64                64
+#define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
   bfd_arch_i386,      /* Intel 386 */
 #define bfd_mach_i386_i386 0
 #define bfd_mach_i386_i8086 1

diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index e2417a13f8d7afc00e735d3c6ecce08a57c1734a..397e5a9a84083b0b1497bcc29881db5b20dc312c 100644 (file)
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -59,6 +59,7 @@ enum
   I_mips32_4k,
   I_mips5,
   I_mips64,
+  I_sb1,
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
@@ -83,7 +84,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (32, 32, bfd_mach_mips32,   "mips:mips32",    false, NN(I_mips32)),
   N (32, 32, bfd_mach_mips32_4k,"mips:mips32-4k", false, NN(I_mips32_4k)),
   N (64, 64, bfd_mach_mips5,    "mips:mips5",     false, NN(I_mips5)),
-  N (64, 64, bfd_mach_mips64,   "mips:mips64",    false, 0),
+  N (64, 64, bfd_mach_mips64,   "mips:mips64",    false, NN(I_mips64)),
+  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       false, 0),
 };
 
 /* The default architecture is mips:3000, but with a machine number of

diff --git a/bfd/elf32-mips.c b/bfd/elf32-mips.c
index 4b0b641de31e6abafe05e38f298cf2e4df9e7e3f..edb708a56ac3cf1a8b53dd7d3af28e2e0c647c9c 100644 (file)
--- a/bfd/elf32-mips.c
+++ b/bfd/elf32-mips.c
@@ -1846,6 +1846,9 @@ elf_mips_mach (flags)
     case E_MIPS_MACH_MIPS32_4K:
       return bfd_mach_mips32_4k;
 
+    case E_MIPS_MACH_SB1:
+      return bfd_mach_mips_sb1;
+
     default:
       switch (flags & EF_MIPS_ARCH)
        {
@@ -2369,6 +2372,10 @@ _bfd_mips_elf_final_write_processing (abfd, linker)
     case bfd_mach_mips64:
       val = E_MIPS_ARCH_64;
       break;
+
+    case bfd_mach_mips_sb1:
+      val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
+      break;
     }
 
   elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH);

diff --git a/bfd/po/bfd.pot b/bfd/po/bfd.pot
index 0ea2b88365d0a3757b764840c5e1aa516af7fa67..a9392f19fd74437e9971e9720c40aa3a6f548c64 100644 (file)
--- a/bfd/po/bfd.pot
+++ b/bfd/po/bfd.pot
@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-12-01 16:44-0800\n"
+"POT-Creation-Date: 2000-12-01 17:03-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -34,22 +34,22 @@ msgstr ""
 msgid "%s: Bad relocation record imported: %d"
 msgstr ""
 
-#: aoutx.h:1258 aoutx.h:1672
+#: aoutx.h:1259 aoutx.h:1673
 #, c-format
 msgid "%s: can not represent section `%s' in a.out object file format"
 msgstr ""
 
-#: aoutx.h:1642
+#: aoutx.h:1643
 #, c-format
 msgid ""
 "%s: can not represent section for symbol `%s' in a.out object file format"
 msgstr ""
 
-#: aoutx.h:1644
+#: aoutx.h:1645
 msgid "*unknown*"
 msgstr ""
 
-#: aoutx.h:3683
+#: aoutx.h:3684
 #, c-format
 msgid "%s: relocateable link from %s to %s not supported"
 msgstr ""
@@ -660,7 +660,7 @@ msgstr ""
 
 #. Ignore init flag - it may not be set, despite the flags field
 #. containing valid data.
-#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2652
+#: elf32-arm.h:2195 elf32-cris.c:615 elf32-m68k.c:430 elf32-mips.c:2659
 #, c-format
 msgid "private flags = %lx:"
 msgstr ""
@@ -854,132 +854,132 @@ msgstr ""
 msgid "Linking mips16 objects into %s format is not supported"
 msgstr ""
 
-#: elf32-mips.c:2539
+#: elf32-mips.c:2546
 #, c-format
 msgid "%s: linking PIC files with non-PIC files"
 msgstr ""
 
-#: elf32-mips.c:2549
+#: elf32-mips.c:2556
 #, c-format
 msgid "%s: linking abicalls files with non-abicalls files"
 msgstr ""
 
-#: elf32-mips.c:2578
+#: elf32-mips.c:2585
 #, c-format
 msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)"
 msgstr ""
 
-#: elf32-mips.c:2587
+#: elf32-mips.c:2594
 #, c-format
 msgid "%s: ISA mismatch (%d) with previous modules (%d)"
 msgstr ""
 
-#: elf32-mips.c:2610
+#: elf32-mips.c:2617
 #, c-format
 msgid "%s: ABI mismatch: linking %s module with previous %s modules"
 msgstr ""
 
-#: elf32-mips.c:2624 elf32-ppc.c:1481 elf64-sparc.c:2974
+#: elf32-mips.c:2631 elf32-ppc.c:1481 elf64-sparc.c:2974
 #, c-format
 msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
 msgstr ""
 
-#: elf32-mips.c:2655
+#: elf32-mips.c:2662
 msgid " [abi=O32]"
 msgstr ""
 
-#: elf32-mips.c:2657
+#: elf32-mips.c:2664
 msgid " [abi=O64]"
 msgstr ""
 
-#: elf32-mips.c:2659
+#: elf32-mips.c:2666
 msgid " [abi=EABI32]"
 msgstr ""
 
-#: elf32-mips.c:2661
+#: elf32-mips.c:2668
 msgid " [abi=EABI64]"
 msgstr ""
 
-#: elf32-mips.c:2663
+#: elf32-mips.c:2670
 msgid " [abi unknown]"
 msgstr ""
 
-#: elf32-mips.c:2665
+#: elf32-mips.c:2672
 msgid " [abi=N32]"
 msgstr ""
 
-#: elf32-mips.c:2667
+#: elf32-mips.c:2674
 msgid " [abi=64]"
 msgstr ""
 
-#: elf32-mips.c:2669
+#: elf32-mips.c:2676
 msgid " [no abi set]"
 msgstr ""
 
-#: elf32-mips.c:2672
+#: elf32-mips.c:2679
 msgid " [mips1]"
 msgstr ""
 
-#: elf32-mips.c:2674
+#: elf32-mips.c:2681
 msgid " [mips2]"
 msgstr ""
 
-#: elf32-mips.c:2676
+#: elf32-mips.c:2683
 msgid " [mips3]"
 msgstr ""
 
-#: elf32-mips.c:2678
+#: elf32-mips.c:2685
 msgid " [mips4]"
 msgstr ""
 
-#: elf32-mips.c:2680
+#: elf32-mips.c:2687
 msgid " [mips5]"
 msgstr ""
 
-#: elf32-mips.c:2682
+#: elf32-mips.c:2689
 msgid " [mips32]"
 msgstr ""
 
-#: elf32-mips.c:2684
+#: elf32-mips.c:2691
 msgid " [mips64]"
 msgstr ""
 
-#: elf32-mips.c:2686
+#: elf32-mips.c:2693
 msgid " [unknown ISA]"
 msgstr ""
 
-#: elf32-mips.c:2689
+#: elf32-mips.c:2696
 msgid " [32bitmode]"
 msgstr ""
 
-#: elf32-mips.c:2691
+#: elf32-mips.c:2698
 msgid " [not 32bitmode]"
 msgstr ""
 
-#: elf32-mips.c:4340
+#: elf32-mips.c:4347
 msgid "static procedure (no name)"
 msgstr ""
 
-#: elf32-mips.c:4955 elf64-alpha.c:4378
+#: elf32-mips.c:4962 elf64-alpha.c:4378
 #, c-format
 msgid "%s: illegal section name `%s'"
 msgstr ""
 
-#: elf32-mips.c:5519
+#: elf32-mips.c:5526
 msgid "not enough GOT space for local GOT entries"
 msgstr ""
 
-#: elf32-mips.c:6636
+#: elf32-mips.c:6643
 #, c-format
 msgid "%s: %s+0x%lx: jump to stub routine which is not jal"
 msgstr ""
 
-#: elf32-mips.c:7623
+#: elf32-mips.c:7630
 #, c-format
 msgid "Malformed reloc detected for section %s"
 msgstr ""
 
-#: elf32-mips.c:7700
+#: elf32-mips.c:7707
 #, c-format
 msgid "%s: CALL16 reloc at 0x%lx not against global symbol"
 msgstr ""

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index d104f4f17b1f9cc0f4fd16a477eaf36f34910ea0..8b21dbc60273921ddcd47c73efddd16348b44f71 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -7,6 +7,9 @@
         * readelf.c (get_machine_flags): Add cases for E_MIPS_ARCH_5,
         and E_MIPS_ARCH_64.
 
+        * readelf.c (get_machine_flags): Add case for
+        E_MIPS_MACH_SB1.
+
 2000-11-30  Richard Earnshaw  <rearnsha@arm.com>
 
        * readelf.c (frame_display_row): Output 's' for DW_CFA_same_value.

diff --git a/binutils/readelf.c b/binutils/readelf.c
index 03dce77f983691dad0ba39f86cc7204b34e8f919..110fb848b44cb89f327e5a5138a40f175bf2669f 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -1488,6 +1488,7 @@ get_machine_flags (e_flags, e_machine)
            case E_MIPS_MACH_4650: strcat (buf, ", 4650"); break;
            case E_MIPS_MACH_4111: strcat (buf, ", 4111"); break;
            case E_MIPS_MACH_MIPS32_4K: strcat (buf, ", mips32-4k"); break;
+           case E_MIPS_MACH_SB1:  strcat (buf, ", sb1");  break;
            default: strcat (buf, " UNKNOWN"); break;
            }
          break;

diff --git a/gas/ChangeLog b/gas/ChangeLog
index bd23387b3323a767b0d29187a717b98c8c42d861..c2b717909b03a32b6bfbf660d4e4fac94a8f29d3 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -67,6 +67,15 @@
         * doc/c-mips.texi: Likewise.  Also update introduction
         and ".set" usage information.
 
+        * config/tc-mips.c (md_show_usage): Add "sb1" to the
+        CPU list.
+        (mips_cpu_info_table): Add SB-1 entries.
+        * doc/c-mips.texi: Add "sb1" to the list of CPUs
+        known to the -mcpu option.
+        
+        * doc/as.texinfo: Correct description of MIPS -mcpu
+        option, by copying some of the text from doc/c-mips.texi.
+
 2000-12-01      Joel Sherrill <joel@OARcorp.com>
 
        * configure.in (arm-*-rtems*, a29k-*rtems*, h8300-*-rtems*):

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index f4f11305b94a1b71817cf9945cc1c6bb35c4a115..9f171b49ab4130f48adbaa32441ec61e735762fd 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -9243,6 +9243,7 @@ MIPS options:\n\
   show (stream, "8000", &column, &first);
   show (stream, "10000", &column, &first);
   show (stream, "mips32-4k", &column, &first);
+  show (stream, "sb-1", &column, &first);
   fputc ('\n', stream);
 
   fprintf (stream, _("\
@@ -12048,6 +12049,12 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "mips32-4km",     0,      ISA_MIPS32,     CPU_MIPS32_4K, },
   { "mips32-4kp",     0,      ISA_MIPS32,     CPU_MIPS32_4K, },
 
+  /* SiByte SB-1 CPU */
+  { "SB-1",           0,      ISA_MIPS64,     CPU_SB1, },
+  { "sb-1250",                0,      ISA_MIPS64,     CPU_SB1, },
+  { "sb1",            0,      ISA_MIPS64,     CPU_SB1, },
+  { "sb1250",         0,      ISA_MIPS64,     CPU_SB1, },
+
   /* End marker. */
   { NULL, 0, 0, 0, },
 };

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 3988d00944cd8a4e9ecb7d2ba95e8f87ff25cf3d..2ff210320a09ecb7314a5487b2a2b1ee28d939c2 100644 (file)
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -689,8 +689,9 @@ instructions around accesses to the @samp{HI} and @samp{LO} registers.
 @samp{-no-m4650} turns off this option.
 
 @item -mcpu=@var{CPU}
-Generate code for a particular MIPS cpu.  This has little effect on the
-assembler, but it is passed by @code{@value{GCC}}.
+Generate code for a particular MIPS cpu.  It is exactly equivalent to
+@samp{-m@var{cpu}}, except that there are more value of @var{cpu}
+understood.
 
 @cindex emulation
 @item --emulation=@var{name}

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index b9902ffd3c47df5ad8cdc426f331f5232c3ac17a..cb9579fbb5d1970f9dfda47a27a66e709cc2cb9f 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -149,7 +149,8 @@ rm5721,
 rm7000,
 8000,
 10000,
-mips32-4k
+mips32-4k,
+sb1
 @end quotation
 
 

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 7c6b94e07847833a3388531c8fc1dd9efd24fed3..2251ba03a6643386836a8b0405f7349a22c69bec 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -6,6 +6,8 @@
 
         * mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions.
 
+        * mips.h (E_MIPS_MACH_SB1): New constant.
+
 2000-11-30  Jan Hubicka  <jh@suse.cz>
        
         * common.h (EM_X86_64): New macro.

diff --git a/include/elf/mips.h b/include/elf/mips.h
index ec333bfcbef4acc46cc864c1f448756eadf30744..bfa03f12d89d7e8f4501c0f3de2818b31b84ea09 100644 (file)
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -163,6 +163,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_4650       0x00850000
 #define E_MIPS_MACH_4111       0x00880000
 #define E_MIPS_MACH_MIPS32_4K  0x00890000
+#define E_MIPS_MACH_SB1         0x008a0000
 \f
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 798d3039f49d5333a418ade1e46955c37c3977e8..e1a3b2966bc77c64069fe5399cbab2ec9e611816 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -28,6 +28,8 @@
         * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
         definitions. 
 
+        * mips.h (CPU_SB1): New constant.
+
 2000-10-20  Jakub Jelinek  <jakub@redhat.com>
 
        * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index bd8f0234ce80f42bd750ab7b7af219f3c9f59cf7..af6c66c19aa351fe2075fb2dc76d3564a9e3f47a 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -359,9 +359,10 @@ struct mips_opcode
 #define CPU_R10000     10000
 #define CPU_MIPS16     16
 #define CPU_MIPS32     32
-#define CPU_MIPS32_4K  3204113         /* 32, 04, octal 'K' */
+#define CPU_MIPS32_4K  3204113         /* 32, 04, octal 'K'.  */
 #define CPU_MIPS5       5
 #define CPU_MIPS64      64
+#define CPU_SB1         12310201        /* octal 'SB', 01.  */
 
 /* Test for membership in an ISA including chip specific ISAs.
    INSN is pointer to an element of the opcode table; ISA is the
@@ -369,7 +370,7 @@ struct mips_opcode
    to test, or zero if no CPU specific ISA test is desired.  
    The gp32 arg is set when you need to force 32-bit register usage on
    a machine with 64-bit registers; see the documentation under -mgp32
-   in the MIPS gas docs. */
+   in the MIPS gas docs.  */
 
 #define OPCODE_IS_MEMBER(insn, isa, cpu, gp32)                         \
     ((((insn)->membership & isa) != 0                                  \

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5754a5affb84d6916722bf295f180085f4b201d7..4eb4fe33a3c49c60c6afa428a4e392bd06dac97e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -29,6 +29,9 @@
         bfd_mach_mips5 and bfd_mach_mips64.
         * mips-opc.c (I64): New definitions.
 
+        * mips-dis.c (set_mips_isa_type): Add case for
+        bfd_mach_mips_sb1.
+
 2000-11-28  Hans-Peter Nilsson  <hp@bitrange.com>
 
        * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned.

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 61f67880e1536a0b382d9efdf09dd7754b3f8b33..a75dc89d9f8097a28f4c0a9d0f6fa72c85acd684 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -371,6 +371,10 @@ set_mips_isa_type (mach, isa, cputype)
       target_processor = CPU_MIPS64;
       mips_isa = ISA_MIPS64;
       break;
+    case bfd_mach_mips_sb1:
+      target_processor = CPU_SB1;
+      mips_isa = ISA_MIPS64;
+      break;
     default:
       target_processor = CPU_R3000;
       mips_isa = ISA_MIPS3;