Code cleanup.
Signed-off-by: Roland Vossen <rvossen@broadcom.com>
Reviewed-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
#include <linux/netdevice.h>
#include <linux/pci_ids.h>
#include <linux/sched.h>
-#include <bcmdefs.h>
-#include <bcmdevs.h>
+#include <defs.h>
+#include <brcm_hw_ids.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
-#include <bcmsoc.h>
+#include <soc.h>
-#include <bcmsdh.h> /* BRCM API for SDIO
+#include <sdio_host.h> /* BRCM API for SDIO
clients (such as wl, dhd) */
#include <bcmsdbus.h> /* common SDIO/controller interface */
#include <sbsdio.h> /* BRCM sdio device core */
#include <linux/completion.h>
#include <linux/sched.h>
-#include <bcmdefs.h>
-#include <bcmdevs.h>
+#include <defs.h>
+#include <brcm_hw_ids.h>
#include <brcmu_utils.h>
-#include <bcmsdh.h>
+#include <sdio_host.h>
#include <brcmu_wifi.h>
#if defined(OOB_INTR_ONLY)
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/mmc/sdio.h>
-#include <bcmdefs.h>
-#include <bcmdevs.h>
+#include <defs.h>
+#include <brcm_hw_ids.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
-#include <bcmsdh.h>
+#include <sdio_host.h>
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* ioctl/iovars */
#include <linux/sched.h> /* request_irq() */
#include <linux/netdevice.h>
#include <net/cfg80211.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
-#include <bcmsdh.h>
+#include <sdio_host.h>
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* to get msglevel bit values */
#include <linux/types.h>
#include <linux/netdevice.h>
#include <linux/sched.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/sched.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <brcmu_wifi.h>
#include <linux/netdevice.h>
#include <asm/unaligned.h>
#include <linux/netdevice.h>
#include <linux/sched.h>
#include <brcmu_utils.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <brcmu_wifi.h>
#include <dngl_stats.h>
#include <linux/fs.h>
#include <linux/uaccess.h>
#include <net/cfg80211.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#include <linux/sched.h>
#include <linux/mmc/sdio.h>
#include <asm/unaligned.h>
-#include <bcmdefs.h>
-#include <bcmsdh.h>
+#include <defs.h>
+#include <sdio_host.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <brcmu_wifi.h>
#include <brcmu_utils.h>
-#include <bcmdevs.h>
+#include <brcm_hw_ids.h>
-#include <bcmsoc.h>
+#include <soc.h>
/* register access macros */
#ifndef __BIG_ENDIAN
#include <linux/sched.h>
#include <brcmu_utils.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <brcmu_wifi.h>
#include <asm/uaccess.h>
#include <linux/kthread.h>
#include <linux/semaphore.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/wireless.h>
-Idrivers/staging/brcm80211/include
BRCMSMAC_OFILES := \
- brcms_mac80211.o \
+ mac80211_if.o \
ucode_loader.o \
- wlc_alloc.o \
- wlc_ampdu.o \
- wlc_antsel.o \
- wlc_bmac.o \
- wlc_channel.o \
- wlc_main.o \
- wlc_phy_shim.o \
- wlc_pmu.o \
- wlc_rate.o \
- wlc_stf.o \
+ alloc.o \
+ ampdu.o \
+ antsel.o \
+ bottom_mac.o \
+ channel.o \
+ main.o \
+ phy_shim.o \
+ pmu.o \
+ rate.o \
+ stf.o \
aiutils.o \
- phy/wlc_phy_cmn.o \
- phy/wlc_phy_lcn.o \
- phy/wlc_phy_n.o \
- phy/wlc_phytbl_lcn.o \
- phy/wlc_phytbl_n.o \
- phy/wlc_phy_qmath.o \
- bcmotp.o \
- bcmsrom.o \
+ phy/phy_cmn.o \
+ phy/phy_lcn.o \
+ phy/phy_n.o \
+ phy/phytbl_lcn.o \
+ phy/phytbl_n.o \
+ phy/phy_qmath.o \
+ otp.o \
+ srom.o \
dma.o \
nicpci.o
#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/string.h>
-#include <bcmdefs.h>
-#include "wlc_types.h"
+#include <defs.h>
+#include "types.h"
#include <linux/module.h>
#include <linux/pci.h>
#include <brcmu_utils.h>
#include <aiutils.h>
-#include <bcmsoc.h>
+#include <soc.h>
#include <chipcommon.h>
-#include <bcmdevs.h>
+#include <brcm_hw_ids.h>
/* ********** from siutils.c *********** */
#include <nicpci.h>
-#include <bcmsrom.h>
-#include <wlc_pmu.h>
-#include <wlc_scb.h>
-#include <wlc_pub.h>
+#include <srom.h>
+#include <pmu.h>
+#include <scb.h>
+#include <pub.h>
/* slow_clk_ctl */
#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include <defs.h>
+#include <brcmu_utils.h>
+#include <aiutils.h>
+#include "dma.h"
+
+#include "d11.h"
+#include "types.h"
+#include "cfg.h"
+#include "scb.h"
+#include "pub.h"
+#include "key.h"
+#include "alloc.h"
+#include "rate.h"
+#include "bsscfg.h"
+#include "phy/phy_hal.h"
+#include "channel.h"
+#include "main.h"
+
+static struct wlc_bsscfg *wlc_bsscfg_malloc(uint unit);
+static void wlc_bsscfg_mfree(struct wlc_bsscfg *cfg);
+static struct wlc_pub *wlc_pub_malloc(uint unit,
+ uint *err, uint devid);
+static void wlc_pub_mfree(struct wlc_pub *pub);
+static void wlc_tunables_init(wlc_tunables_t *tunables, uint devid);
+
+static void wlc_tunables_init(wlc_tunables_t *tunables, uint devid)
+{
+ tunables->ntxd = NTXD;
+ tunables->nrxd = NRXD;
+ tunables->rxbufsz = RXBUFSZ;
+ tunables->nrxbufpost = NRXBUFPOST;
+ tunables->maxscb = MAXSCB;
+ tunables->ampdunummpdu = AMPDU_NUM_MPDU;
+ tunables->maxpktcb = MAXPKTCB;
+ tunables->maxucodebss = WLC_MAX_UCODE_BSS;
+ tunables->maxucodebss4 = WLC_MAX_UCODE_BSS4;
+ tunables->maxbss = MAXBSS;
+ tunables->datahiwat = WLC_DATAHIWAT;
+ tunables->ampdudatahiwat = WLC_AMPDUDATAHIWAT;
+ tunables->rxbnd = RXBND;
+ tunables->txsbnd = TXSBND;
+}
+
+static struct wlc_pub *wlc_pub_malloc(uint unit, uint *err, uint devid)
+{
+ struct wlc_pub *pub;
+
+ pub = kzalloc(sizeof(struct wlc_pub), GFP_ATOMIC);
+ if (pub == NULL) {
+ *err = 1001;
+ goto fail;
+ }
+
+ pub->tunables = kzalloc(sizeof(wlc_tunables_t), GFP_ATOMIC);
+ if (pub->tunables == NULL) {
+ *err = 1028;
+ goto fail;
+ }
+
+ /* need to init the tunables now */
+ wlc_tunables_init(pub->tunables, devid);
+
+ pub->multicast = kzalloc(ETH_ALEN * MAXMULTILIST, GFP_ATOMIC);
+ if (pub->multicast == NULL) {
+ *err = 1003;
+ goto fail;
+ }
+
+ return pub;
+
+ fail:
+ wlc_pub_mfree(pub);
+ return NULL;
+}
+
+static void wlc_pub_mfree(struct wlc_pub *pub)
+{
+ if (pub == NULL)
+ return;
+
+ kfree(pub->multicast);
+ kfree(pub->tunables);
+ kfree(pub);
+}
+
+static struct wlc_bsscfg *wlc_bsscfg_malloc(uint unit)
+{
+ struct wlc_bsscfg *cfg;
+
+ cfg = kzalloc(sizeof(struct wlc_bsscfg), GFP_ATOMIC);
+ if (cfg == NULL)
+ goto fail;
+
+ cfg->current_bss = kzalloc(sizeof(wlc_bss_info_t), GFP_ATOMIC);
+ if (cfg->current_bss == NULL)
+ goto fail;
+
+ return cfg;
+
+ fail:
+ wlc_bsscfg_mfree(cfg);
+ return NULL;
+}
+
+static void wlc_bsscfg_mfree(struct wlc_bsscfg *cfg)
+{
+ if (cfg == NULL)
+ return;
+
+ kfree(cfg->maclist);
+ kfree(cfg->current_bss);
+ kfree(cfg);
+}
+
+static void wlc_bsscfg_ID_assign(struct wlc_info *wlc,
+ struct wlc_bsscfg *bsscfg)
+{
+ bsscfg->ID = wlc->next_bsscfg_ID;
+ wlc->next_bsscfg_ID++;
+}
+
+/*
+ * The common driver entry routine. Error codes should be unique
+ */
+struct wlc_info *wlc_attach_malloc(uint unit, uint *err, uint devid)
+{
+ struct wlc_info *wlc;
+
+ wlc = kzalloc(sizeof(struct wlc_info), GFP_ATOMIC);
+ if (wlc == NULL) {
+ *err = 1002;
+ goto fail;
+ }
+
+ /* allocate struct wlc_pub state structure */
+ wlc->pub = wlc_pub_malloc(unit, err, devid);
+ if (wlc->pub == NULL) {
+ *err = 1003;
+ goto fail;
+ }
+ wlc->pub->wlc = wlc;
+
+ /* allocate struct wlc_hw_info state structure */
+
+ wlc->hw = kzalloc(sizeof(struct wlc_hw_info), GFP_ATOMIC);
+ if (wlc->hw == NULL) {
+ *err = 1005;
+ goto fail;
+ }
+ wlc->hw->wlc = wlc;
+
+ wlc->hw->bandstate[0] =
+ kzalloc(sizeof(struct wlc_hwband) * MAXBANDS, GFP_ATOMIC);
+ if (wlc->hw->bandstate[0] == NULL) {
+ *err = 1006;
+ goto fail;
+ } else {
+ int i;
+
+ for (i = 1; i < MAXBANDS; i++) {
+ wlc->hw->bandstate[i] = (struct wlc_hwband *)
+ ((unsigned long)wlc->hw->bandstate[0] +
+ (sizeof(struct wlc_hwband) * i));
+ }
+ }
+
+ wlc->modulecb =
+ kzalloc(sizeof(struct modulecb) * WLC_MAXMODULES, GFP_ATOMIC);
+ if (wlc->modulecb == NULL) {
+ *err = 1009;
+ goto fail;
+ }
+
+ wlc->default_bss = kzalloc(sizeof(wlc_bss_info_t), GFP_ATOMIC);
+ if (wlc->default_bss == NULL) {
+ *err = 1010;
+ goto fail;
+ }
+
+ wlc->cfg = wlc_bsscfg_malloc(unit);
+ if (wlc->cfg == NULL) {
+ *err = 1011;
+ goto fail;
+ }
+ wlc_bsscfg_ID_assign(wlc, wlc->cfg);
+
+ wlc->wsec_def_keys[0] =
+ kzalloc(sizeof(wsec_key_t) * WLC_DEFAULT_KEYS, GFP_ATOMIC);
+ if (wlc->wsec_def_keys[0] == NULL) {
+ *err = 1015;
+ goto fail;
+ } else {
+ int i;
+ for (i = 1; i < WLC_DEFAULT_KEYS; i++) {
+ wlc->wsec_def_keys[i] = (wsec_key_t *)
+ ((unsigned long)wlc->wsec_def_keys[0] +
+ (sizeof(wsec_key_t) * i));
+ }
+ }
+
+ wlc->protection = kzalloc(sizeof(struct wlc_protection), GFP_ATOMIC);
+ if (wlc->protection == NULL) {
+ *err = 1016;
+ goto fail;
+ }
+
+ wlc->stf = kzalloc(sizeof(struct wlc_stf), GFP_ATOMIC);
+ if (wlc->stf == NULL) {
+ *err = 1017;
+ goto fail;
+ }
+
+ wlc->bandstate[0] =
+ kzalloc(sizeof(struct wlcband)*MAXBANDS, GFP_ATOMIC);
+ if (wlc->bandstate[0] == NULL) {
+ *err = 1025;
+ goto fail;
+ } else {
+ int i;
+
+ for (i = 1; i < MAXBANDS; i++) {
+ wlc->bandstate[i] =
+ (struct wlcband *) ((unsigned long)wlc->bandstate[0]
+ + (sizeof(struct wlcband)*i));
+ }
+ }
+
+ wlc->corestate = kzalloc(sizeof(struct wlccore), GFP_ATOMIC);
+ if (wlc->corestate == NULL) {
+ *err = 1026;
+ goto fail;
+ }
+
+ wlc->corestate->macstat_snapshot =
+ kzalloc(sizeof(macstat_t), GFP_ATOMIC);
+ if (wlc->corestate->macstat_snapshot == NULL) {
+ *err = 1027;
+ goto fail;
+ }
+
+ return wlc;
+
+ fail:
+ wlc_detach_mfree(wlc);
+ return NULL;
+}
+
+void wlc_detach_mfree(struct wlc_info *wlc)
+{
+ if (wlc == NULL)
+ return;
+
+ wlc_bsscfg_mfree(wlc->cfg);
+ wlc_pub_mfree(wlc->pub);
+ kfree(wlc->modulecb);
+ kfree(wlc->default_bss);
+ kfree(wlc->wsec_def_keys[0]);
+ kfree(wlc->protection);
+ kfree(wlc->stf);
+ kfree(wlc->bandstate[0]);
+ kfree(wlc->corestate->macstat_snapshot);
+ kfree(wlc->corestate);
+ kfree(wlc->hw->bandstate[0]);
+ kfree(wlc->hw);
+
+ /* free the wlc */
+ kfree(wlc);
+ wlc = NULL;
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+extern struct wlc_info *wlc_attach_malloc(uint unit, uint *err, uint devid);
+extern void wlc_detach_mfree(struct wlc_info *wlc);
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <net/mac80211.h>
+
+#include <defs.h>
+#include <brcmu_utils.h>
+#include <aiutils.h>
+#include "dma.h"
+#include <d11.h>
+
+#include "types.h"
+#include "cfg.h"
+#include "rate.h"
+#include "scb.h"
+#include "pub.h"
+#include "key.h"
+#include "phy/phy_hal.h"
+#include "antsel.h"
+#include "channel.h"
+#include "main.h"
+#include "ampdu.h"
+
+#define AMPDU_MAX_MPDU 32 /* max number of mpdus in an ampdu */
+#define AMPDU_NUM_MPDU_LEGACY 16 /* max number of mpdus in an ampdu to a legacy */
+#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
+#define AMPDU_TX_BA_DEF_WSIZE 64 /* default Tx ba window size (in pdu) */
+#define AMPDU_RX_BA_DEF_WSIZE 64 /* max Rx ba window size (in pdu) */
+#define AMPDU_RX_BA_MAX_WSIZE 64 /* default Rx ba window size (in pdu) */
+#define AMPDU_MAX_DUR 5 /* max dur of tx ampdu (in msec) */
+#define AMPDU_DEF_RETRY_LIMIT 5 /* default tx retry limit */
+#define AMPDU_DEF_RR_RETRY_LIMIT 2 /* default tx retry limit at reg rate */
+#define AMPDU_DEF_TXPKT_WEIGHT 2 /* default weight of ampdu in txfifo */
+#define AMPDU_DEF_FFPLD_RSVD 2048 /* default ffpld reserved bytes */
+#define AMPDU_INI_FREE 10 /* # of inis to be freed on detach */
+#define AMPDU_SCB_MAX_RELEASE 20 /* max # of mpdus released at a time */
+
+#define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
+#define FFPLD_TX_MAX_UNFL 200 /* default value of the average number of ampdu
+ * without underflows
+ */
+#define FFPLD_MPDU_SIZE 1800 /* estimate of maximum mpdu size */
+#define FFPLD_MAX_MCS 23 /* we don't deal with mcs 32 */
+#define FFPLD_PLD_INCR 1000 /* increments in bytes */
+#define FFPLD_MAX_AMPDU_CNT 5000 /* maximum number of ampdu we
+ * accumulate between resets.
+ */
+
+#define TX_SEQ_TO_INDEX(seq) ((seq) % AMPDU_TX_BA_MAX_WSIZE)
+
+/* max possible overhead per mpdu in the ampdu; 3 is for roundup if needed */
+#define AMPDU_MAX_MPDU_OVERHEAD (FCS_LEN + DOT11_ICV_AES_LEN +\
+ AMPDU_DELIMITER_LEN + 3\
+ + DOT11_A4_HDR_LEN + DOT11_QOS_LEN + DOT11_IV_MAX_LEN)
+
+/* structure to hold tx fifo information and pre-loading state
+ * counters specific to tx underflows of ampdus
+ * some counters might be redundant with the ones in wlc or ampdu structures.
+ * This allows to maintain a specific state independently of
+ * how often and/or when the wlc counters are updated.
+ */
+typedef struct wlc_fifo_info {
+ u16 ampdu_pld_size; /* number of bytes to be pre-loaded */
+ u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1]; /* per-mcs max # of mpdus in an ampdu */
+ u16 prev_txfunfl; /* num of underflows last read from the HW macstats counter */
+ u32 accum_txfunfl; /* num of underflows since we modified pld params */
+ u32 accum_txampdu; /* num of tx ampdu since we modified pld params */
+ u32 prev_txampdu; /* previous reading of tx ampdu */
+ u32 dmaxferrate; /* estimated dma avg xfer rate in kbits/sec */
+} wlc_fifo_info_t;
+
+/* AMPDU module specific state */
+struct ampdu_info {
+ struct wlc_info *wlc; /* pointer to main wlc structure */
+ int scb_handle; /* scb cubby handle to retrieve data from scb */
+ u8 ini_enable[AMPDU_MAX_SCB_TID]; /* per-tid initiator enable/disable of ampdu */
+ u8 ba_tx_wsize; /* Tx ba window size (in pdu) */
+ u8 ba_rx_wsize; /* Rx ba window size (in pdu) */
+ u8 retry_limit; /* mpdu transmit retry limit */
+ u8 rr_retry_limit; /* mpdu transmit retry limit at regular rate */
+ u8 retry_limit_tid[AMPDU_MAX_SCB_TID]; /* per-tid mpdu transmit retry limit */
+ /* per-tid mpdu transmit retry limit at regular rate */
+ u8 rr_retry_limit_tid[AMPDU_MAX_SCB_TID];
+ u8 mpdu_density; /* min mpdu spacing (0-7) ==> 2^(x-1)/8 usec */
+ s8 max_pdu; /* max pdus allowed in ampdu */
+ u8 dur; /* max duration of an ampdu (in msec) */
+ u8 txpkt_weight; /* weight of ampdu in txfifo; reduces rate lag */
+ u8 rx_factor; /* maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes */
+ u32 ffpld_rsvd; /* number of bytes to reserve for preload */
+ u32 max_txlen[MCS_TABLE_SIZE][2][2]; /* max size of ampdu per mcs, bw and sgi */
+ void *ini_free[AMPDU_INI_FREE]; /* array of ini's to be freed on detach */
+ bool mfbr; /* enable multiple fallback rate */
+ u32 tx_max_funl; /* underflows should be kept such that
+ * (tx_max_funfl*underflows) < tx frames
+ */
+ wlc_fifo_info_t fifo_tb[NUM_FFPLD_FIFO]; /* table of fifo infos */
+
+};
+
+/* used for flushing ampdu packets */
+struct cb_del_ampdu_pars {
+ struct ieee80211_sta *sta;
+ u16 tid;
+};
+
+#define AMPDU_CLEANUPFLAG_RX (0x1)
+#define AMPDU_CLEANUPFLAG_TX (0x2)
+
+#define SCB_AMPDU_CUBBY(ampdu, scb) (&(scb->scb_ampdu))
+#define SCB_AMPDU_INI(scb_ampdu, tid) (&(scb_ampdu->ini[tid]))
+
+static void wlc_ffpld_init(struct ampdu_info *ampdu);
+static int wlc_ffpld_check_txfunfl(struct wlc_info *wlc, int f);
+static void wlc_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu, int f);
+
+static scb_ampdu_tid_ini_t *wlc_ampdu_init_tid_ini(struct ampdu_info *ampdu,
+ scb_ampdu_t *scb_ampdu,
+ u8 tid, bool override);
+static void ampdu_update_max_txlen(struct ampdu_info *ampdu, u8 dur);
+static void scb_ampdu_update_config(struct ampdu_info *ampdu, struct scb *scb);
+static void scb_ampdu_update_config_all(struct ampdu_info *ampdu);
+
+#define wlc_ampdu_txflowcontrol(a, b, c) do {} while (0)
+
+static void wlc_ampdu_dotxstatus_complete(struct ampdu_info *ampdu,
+ struct scb *scb,
+ struct sk_buff *p, tx_status_t *txs,
+ u32 frmtxstatus, u32 frmtxstatus2);
+static bool wlc_ampdu_cap(struct ampdu_info *ampdu);
+static int wlc_ampdu_set(struct ampdu_info *ampdu, bool on);
+
+struct ampdu_info *wlc_ampdu_attach(struct wlc_info *wlc)
+{
+ struct ampdu_info *ampdu;
+ int i;
+
+ ampdu = kzalloc(sizeof(struct ampdu_info), GFP_ATOMIC);
+ if (!ampdu) {
+ wiphy_err(wlc->wiphy, "wl%d: wlc_ampdu_attach: out of mem\n",
+ wlc->pub->unit);
+ return NULL;
+ }
+ ampdu->wlc = wlc;
+
+ for (i = 0; i < AMPDU_MAX_SCB_TID; i++)
+ ampdu->ini_enable[i] = true;
+ /* Disable ampdu for VO by default */
+ ampdu->ini_enable[PRIO_8021D_VO] = false;
+ ampdu->ini_enable[PRIO_8021D_NC] = false;
+
+ /* Disable ampdu for BK by default since not enough fifo space */
+ ampdu->ini_enable[PRIO_8021D_NONE] = false;
+ ampdu->ini_enable[PRIO_8021D_BK] = false;
+
+ ampdu->ba_tx_wsize = AMPDU_TX_BA_DEF_WSIZE;
+ ampdu->ba_rx_wsize = AMPDU_RX_BA_DEF_WSIZE;
+ ampdu->mpdu_density = AMPDU_DEF_MPDU_DENSITY;
+ ampdu->max_pdu = AUTO;
+ ampdu->dur = AMPDU_MAX_DUR;
+ ampdu->txpkt_weight = AMPDU_DEF_TXPKT_WEIGHT;
+
+ ampdu->ffpld_rsvd = AMPDU_DEF_FFPLD_RSVD;
+ /* bump max ampdu rcv size to 64k for all 11n devices except 4321A0 and 4321A1 */
+ if (WLCISNPHY(wlc->band) && NREV_LT(wlc->band->phyrev, 2))
+ ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_32K;
+ else
+ ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_64K;
+ ampdu->retry_limit = AMPDU_DEF_RETRY_LIMIT;
+ ampdu->rr_retry_limit = AMPDU_DEF_RR_RETRY_LIMIT;
+
+ for (i = 0; i < AMPDU_MAX_SCB_TID; i++) {
+ ampdu->retry_limit_tid[i] = ampdu->retry_limit;
+ ampdu->rr_retry_limit_tid[i] = ampdu->rr_retry_limit;
+ }
+
+ ampdu_update_max_txlen(ampdu, ampdu->dur);
+ ampdu->mfbr = false;
+ /* try to set ampdu to the default value */
+ wlc_ampdu_set(ampdu, wlc->pub->_ampdu);
+
+ ampdu->tx_max_funl = FFPLD_TX_MAX_UNFL;
+ wlc_ffpld_init(ampdu);
+
+ return ampdu;
+}
+
+void wlc_ampdu_detach(struct ampdu_info *ampdu)
+{
+ int i;
+
+ if (!ampdu)
+ return;
+
+ /* free all ini's which were to be freed on callbacks which were never called */
+ for (i = 0; i < AMPDU_INI_FREE; i++) {
+ kfree(ampdu->ini_free[i]);
+ }
+
+ wlc_module_unregister(ampdu->wlc->pub, "ampdu", ampdu);
+ kfree(ampdu);
+}
+
+static void scb_ampdu_update_config(struct ampdu_info *ampdu, struct scb *scb)
+{
+ scb_ampdu_t *scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
+ int i;
+
+ scb_ampdu->max_pdu = (u8) ampdu->wlc->pub->tunables->ampdunummpdu;
+
+ /* go back to legacy size if some preloading is occurring */
+ for (i = 0; i < NUM_FFPLD_FIFO; i++) {
+ if (ampdu->fifo_tb[i].ampdu_pld_size > FFPLD_PLD_INCR)
+ scb_ampdu->max_pdu = AMPDU_NUM_MPDU_LEGACY;
+ }
+
+ /* apply user override */
+ if (ampdu->max_pdu != AUTO)
+ scb_ampdu->max_pdu = (u8) ampdu->max_pdu;
+
+ scb_ampdu->release = min_t(u8, scb_ampdu->max_pdu, AMPDU_SCB_MAX_RELEASE);
+
+ if (scb_ampdu->max_rxlen)
+ scb_ampdu->release =
+ min_t(u8, scb_ampdu->release, scb_ampdu->max_rxlen / 1600);
+
+ scb_ampdu->release = min(scb_ampdu->release,
+ ampdu->fifo_tb[TX_AC_BE_FIFO].
+ mcs2ampdu_table[FFPLD_MAX_MCS]);
+}
+
+static void scb_ampdu_update_config_all(struct ampdu_info *ampdu)
+{
+ scb_ampdu_update_config(ampdu, ampdu->wlc->pub->global_scb);
+}
+
+static void wlc_ffpld_init(struct ampdu_info *ampdu)
+{
+ int i, j;
+ wlc_fifo_info_t *fifo;
+
+ for (j = 0; j < NUM_FFPLD_FIFO; j++) {
+ fifo = (ampdu->fifo_tb + j);
+ fifo->ampdu_pld_size = 0;
+ for (i = 0; i <= FFPLD_MAX_MCS; i++)
+ fifo->mcs2ampdu_table[i] = 255;
+ fifo->dmaxferrate = 0;
+ fifo->accum_txampdu = 0;
+ fifo->prev_txfunfl = 0;
+ fifo->accum_txfunfl = 0;
+
+ }
+}
+
+/* evaluate the dma transfer rate using the tx underflows as feedback.
+ * If necessary, increase tx fifo preloading. If not enough,
+ * decrease maximum ampdu size for each mcs till underflows stop
+ * Return 1 if pre-loading not active, -1 if not an underflow event,
+ * 0 if pre-loading module took care of the event.
+ */
+static int wlc_ffpld_check_txfunfl(struct wlc_info *wlc, int fid)
+{
+ struct ampdu_info *ampdu = wlc->ampdu;
+ u32 phy_rate = MCS_RATE(FFPLD_MAX_MCS, true, false);
+ u32 txunfl_ratio;
+ u8 max_mpdu;
+ u32 current_ampdu_cnt = 0;
+ u16 max_pld_size;
+ u32 new_txunfl;
+ wlc_fifo_info_t *fifo = (ampdu->fifo_tb + fid);
+ uint xmtfifo_sz;
+ u16 cur_txunfl;
+
+ /* return if we got here for a different reason than underflows */
+ cur_txunfl =
+ wlc_read_shm(wlc,
+ M_UCODE_MACSTAT + offsetof(macstat_t, txfunfl[fid]));
+ new_txunfl = (u16) (cur_txunfl - fifo->prev_txfunfl);
+ if (new_txunfl == 0) {
+ BCMMSG(wlc->wiphy, "TX status FRAG set but no tx underflows\n");
+ return -1;
+ }
+ fifo->prev_txfunfl = cur_txunfl;
+
+ if (!ampdu->tx_max_funl)
+ return 1;
+
+ /* check if fifo is big enough */
+ if (wlc_xmtfifo_sz_get(wlc, fid, &xmtfifo_sz)) {
+ return -1;
+ }
+
+ if ((TXFIFO_SIZE_UNIT * (u32) xmtfifo_sz) <= ampdu->ffpld_rsvd)
+ return 1;
+
+ max_pld_size = TXFIFO_SIZE_UNIT * xmtfifo_sz - ampdu->ffpld_rsvd;
+ fifo->accum_txfunfl += new_txunfl;
+
+ /* we need to wait for at least 10 underflows */
+ if (fifo->accum_txfunfl < 10)
+ return 0;
+
+ BCMMSG(wlc->wiphy, "ampdu_count %d tx_underflows %d\n",
+ current_ampdu_cnt, fifo->accum_txfunfl);
+
+ /*
+ compute the current ratio of tx unfl per ampdu.
+ When the current ampdu count becomes too
+ big while the ratio remains small, we reset
+ the current count in order to not
+ introduce too big of a latency in detecting a
+ large amount of tx underflows later.
+ */
+
+ txunfl_ratio = current_ampdu_cnt / fifo->accum_txfunfl;
+
+ if (txunfl_ratio > ampdu->tx_max_funl) {
+ if (current_ampdu_cnt >= FFPLD_MAX_AMPDU_CNT) {
+ fifo->accum_txfunfl = 0;
+ }
+ return 0;
+ }
+ max_mpdu =
+ min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS], AMPDU_NUM_MPDU_LEGACY);
+
+ /* In case max value max_pdu is already lower than
+ the fifo depth, there is nothing more we can do.
+ */
+
+ if (fifo->ampdu_pld_size >= max_mpdu * FFPLD_MPDU_SIZE) {
+ fifo->accum_txfunfl = 0;
+ return 0;
+ }
+
+ if (fifo->ampdu_pld_size < max_pld_size) {
+
+ /* increment by TX_FIFO_PLD_INC bytes */
+ fifo->ampdu_pld_size += FFPLD_PLD_INCR;
+ if (fifo->ampdu_pld_size > max_pld_size)
+ fifo->ampdu_pld_size = max_pld_size;
+
+ /* update scb release size */
+ scb_ampdu_update_config_all(ampdu);
+
+ /*
+ compute a new dma xfer rate for max_mpdu @ max mcs.
+ This is the minimum dma rate that
+ can achieve no underflow condition for the current mpdu size.
+ */
+ /* note : we divide/multiply by 100 to avoid integer overflows */
+ fifo->dmaxferrate =
+ (((phy_rate / 100) *
+ (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
+ / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
+
+ BCMMSG(wlc->wiphy, "DMA estimated transfer rate %d; "
+ "pre-load size %d\n",
+ fifo->dmaxferrate, fifo->ampdu_pld_size);
+ } else {
+
+ /* decrease ampdu size */
+ if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] > 1) {
+ if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] == 255)
+ fifo->mcs2ampdu_table[FFPLD_MAX_MCS] =
+ AMPDU_NUM_MPDU_LEGACY - 1;
+ else
+ fifo->mcs2ampdu_table[FFPLD_MAX_MCS] -= 1;
+
+ /* recompute the table */
+ wlc_ffpld_calc_mcs2ampdu_table(ampdu, fid);
+
+ /* update scb release size */
+ scb_ampdu_update_config_all(ampdu);
+ }
+ }
+ fifo->accum_txfunfl = 0;
+ return 0;
+}
+
+static void wlc_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu, int f)
+{
+ int i;
+ u32 phy_rate, dma_rate, tmp;
+ u8 max_mpdu;
+ wlc_fifo_info_t *fifo = (ampdu->fifo_tb + f);
+
+ /* recompute the dma rate */
+ /* note : we divide/multiply by 100 to avoid integer overflows */
+ max_mpdu =
+ min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS], AMPDU_NUM_MPDU_LEGACY);
+ phy_rate = MCS_RATE(FFPLD_MAX_MCS, true, false);
+ dma_rate =
+ (((phy_rate / 100) *
+ (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
+ / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
+ fifo->dmaxferrate = dma_rate;
+
+ /* fill up the mcs2ampdu table; do not recalc the last mcs */
+ dma_rate = dma_rate >> 7;
+ for (i = 0; i < FFPLD_MAX_MCS; i++) {
+ /* shifting to keep it within integer range */
+ phy_rate = MCS_RATE(i, true, false) >> 7;
+ if (phy_rate > dma_rate) {
+ tmp = ((fifo->ampdu_pld_size * phy_rate) /
+ ((phy_rate - dma_rate) * FFPLD_MPDU_SIZE)) + 1;
+ tmp = min_t(u32, tmp, 255);
+ fifo->mcs2ampdu_table[i] = (u8) tmp;
+ }
+ }
+}
+
+static void
+wlc_ampdu_agg(struct ampdu_info *ampdu, struct scb *scb, struct sk_buff *p,
+ uint prec)
+{
+ scb_ampdu_t *scb_ampdu;
+ scb_ampdu_tid_ini_t *ini;
+ u8 tid = (u8) (p->priority);
+
+ scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
+
+ /* initialize initiator on first packet; sends addba req */
+ ini = SCB_AMPDU_INI(scb_ampdu, tid);
+ if (ini->magic != INI_MAGIC) {
+ ini = wlc_ampdu_init_tid_ini(ampdu, scb_ampdu, tid, false);
+ }
+ return;
+}
+
+int
+wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
+ struct sk_buff **pdu, int prec)
+{
+ struct wlc_info *wlc;
+ struct sk_buff *p, *pkt[AMPDU_MAX_MPDU];
+ u8 tid, ndelim;
+ int err = 0;
+ u8 preamble_type = WLC_GF_PREAMBLE;
+ u8 fbr_preamble_type = WLC_GF_PREAMBLE;
+ u8 rts_preamble_type = WLC_LONG_PREAMBLE;
+ u8 rts_fbr_preamble_type = WLC_LONG_PREAMBLE;
+
+ bool rr = true, fbr = false;
+ uint i, count = 0, fifo, seg_cnt = 0;
+ u16 plen, len, seq = 0, mcl, mch, index, frameid, dma_len = 0;
+ u32 ampdu_len, maxlen = 0;
+ d11txh_t *txh = NULL;
+ u8 *plcp;
+ struct ieee80211_hdr *h;
+ struct scb *scb;
+ scb_ampdu_t *scb_ampdu;
+ scb_ampdu_tid_ini_t *ini;
+ u8 mcs = 0;
+ bool use_rts = false, use_cts = false;
+ ratespec_t rspec = 0, rspec_fallback = 0;
+ ratespec_t rts_rspec = 0, rts_rspec_fallback = 0;
+ u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
+ struct ieee80211_rts *rts;
+ u8 rr_retry_limit;
+ wlc_fifo_info_t *f;
+ bool fbr_iscck;
+ struct ieee80211_tx_info *tx_info;
+ u16 qlen;
+ struct wiphy *wiphy;
+
+ wlc = ampdu->wlc;
+ wiphy = wlc->wiphy;
+ p = *pdu;
+
+ tid = (u8) (p->priority);
+
+ f = ampdu->fifo_tb + prio2fifo[tid];
+
+ scb = wlc->pub->global_scb;
+ scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
+ ini = &scb_ampdu->ini[tid];
+
+ /* Let pressure continue to build ... */
+ qlen = pktq_plen(&qi->q, prec);
+ if (ini->tx_in_transit > 0 && qlen < scb_ampdu->max_pdu) {
+ return -EBUSY;
+ }
+
+ wlc_ampdu_agg(ampdu, scb, p, tid);
+
+ rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
+ ampdu_len = 0;
+ dma_len = 0;
+ while (p) {
+ struct ieee80211_tx_rate *txrate;
+
+ tx_info = IEEE80211_SKB_CB(p);
+ txrate = tx_info->status.rates;
+
+ if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+ err = wlc_prep_pdu(wlc, p, &fifo);
+ } else {
+ wiphy_err(wiphy, "%s: AMPDU flag is off!\n", __func__);
+ *pdu = NULL;
+ err = 0;
+ break;
+ }
+
+ if (err) {
+ if (err == -EBUSY) {
+ wiphy_err(wiphy, "wl%d: wlc_sendampdu: "
+ "prep_xdu retry; seq 0x%x\n",
+ wlc->pub->unit, seq);
+ *pdu = p;
+ break;
+ }
+
+ /* error in the packet; reject it */
+ wiphy_err(wiphy, "wl%d: wlc_sendampdu: prep_xdu "
+ "rejected; seq 0x%x\n", wlc->pub->unit, seq);
+ *pdu = NULL;
+ break;
+ }
+
+ /* pkt is good to be aggregated */
+ txh = (d11txh_t *) p->data;
+ plcp = (u8 *) (txh + 1);
+ h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
+ seq = le16_to_cpu(h->seq_ctrl) >> SEQNUM_SHIFT;
+ index = TX_SEQ_TO_INDEX(seq);
+
+ /* check mcl fields and test whether it can be agg'd */
+ mcl = le16_to_cpu(txh->MacTxControlLow);
+ mcl &= ~TXC_AMPDU_MASK;
+ fbr_iscck = !(le16_to_cpu(txh->XtraFrameTypes) & 0x3);
+ txh->PreloadSize = 0; /* always default to 0 */
+
+ /* Handle retry limits */
+ if (txrate[0].count <= rr_retry_limit) {
+ txrate[0].count++;
+ rr = true;
+ fbr = false;
+ } else {
+ fbr = true;
+ rr = false;
+ txrate[1].count++;
+ }
+
+ /* extract the length info */
+ len = fbr_iscck ? WLC_GET_CCK_PLCP_LEN(txh->FragPLCPFallback)
+ : WLC_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
+
+ /* retrieve null delimiter count */
+ ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
+ seg_cnt += 1;
+
+ BCMMSG(wlc->wiphy, "wl%d: mpdu %d plcp_len %d\n",
+ wlc->pub->unit, count, len);
+
+ /*
+ * aggregateable mpdu. For ucode/hw agg,
+ * test whether need to break or change the epoch
+ */
+ if (count == 0) {
+ mcl |= (TXC_AMPDU_FIRST << TXC_AMPDU_SHIFT);
+ /* refill the bits since might be a retx mpdu */
+ mcl |= TXC_STARTMSDU;
+ rts = (struct ieee80211_rts *)&txh->rts_frame;
+
+ if (ieee80211_is_rts(rts->frame_control)) {
+ mcl |= TXC_SENDRTS;
+ use_rts = true;
+ }
+ if (ieee80211_is_cts(rts->frame_control)) {
+ mcl |= TXC_SENDCTS;
+ use_cts = true;
+ }
+ } else {
+ mcl |= (TXC_AMPDU_MIDDLE << TXC_AMPDU_SHIFT);
+ mcl &= ~(TXC_STARTMSDU | TXC_SENDRTS | TXC_SENDCTS);
+ }
+
+ len = roundup(len, 4);
+ ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN);
+
+ dma_len += (u16) brcmu_pkttotlen(p);
+
+ BCMMSG(wlc->wiphy, "wl%d: ampdu_len %d"
+ " seg_cnt %d null delim %d\n",
+ wlc->pub->unit, ampdu_len, seg_cnt, ndelim);
+
+ txh->MacTxControlLow = cpu_to_le16(mcl);
+
+ /* this packet is added */
+ pkt[count++] = p;
+
+ /* patch the first MPDU */
+ if (count == 1) {
+ u8 plcp0, plcp3, is40, sgi;
+ struct ieee80211_sta *sta;
+
+ sta = tx_info->control.sta;
+
+ if (rr) {
+ plcp0 = plcp[0];
+ plcp3 = plcp[3];
+ } else {
+ plcp0 = txh->FragPLCPFallback[0];
+ plcp3 = txh->FragPLCPFallback[3];
+
+ }
+ is40 = (plcp0 & MIMO_PLCP_40MHZ) ? 1 : 0;
+ sgi = PLCP3_ISSGI(plcp3) ? 1 : 0;
+ mcs = plcp0 & ~MIMO_PLCP_40MHZ;
+ maxlen =
+ min(scb_ampdu->max_rxlen,
+ ampdu->max_txlen[mcs][is40][sgi]);
+
+ /* XXX Fix me to honor real max_rxlen */
+ /* can fix this as soon as ampdu_action() in mac80211.h
+ * gets extra u8buf_size par */
+ maxlen = 64 * 1024;
+
+ if (is40)
+ mimo_ctlchbw =
+ CHSPEC_SB_UPPER(WLC_BAND_PI_RADIO_CHANSPEC)
+ ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
+
+ /* rebuild the rspec and rspec_fallback */
+ rspec = RSPEC_MIMORATE;
+ rspec |= plcp[0] & ~MIMO_PLCP_40MHZ;
+ if (plcp[0] & MIMO_PLCP_40MHZ)
+ rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
+
+ if (fbr_iscck) /* CCK */
+ rspec_fallback =
+ CCK_RSPEC(CCK_PHY2MAC_RATE
+ (txh->FragPLCPFallback[0]));
+ else { /* MIMO */
+ rspec_fallback = RSPEC_MIMORATE;
+ rspec_fallback |=
+ txh->FragPLCPFallback[0] & ~MIMO_PLCP_40MHZ;
+ if (txh->FragPLCPFallback[0] & MIMO_PLCP_40MHZ)
+ rspec_fallback |=
+ (PHY_TXC1_BW_40MHZ <<
+ RSPEC_BW_SHIFT);
+ }
+
+ if (use_rts || use_cts) {
+ rts_rspec =
+ wlc_rspec_to_rts_rspec(wlc, rspec, false,
+ mimo_ctlchbw);
+ rts_rspec_fallback =
+ wlc_rspec_to_rts_rspec(wlc, rspec_fallback,
+ false, mimo_ctlchbw);
+ }
+ }
+
+ /* if (first mpdu for host agg) */
+ /* test whether to add more */
+ if ((MCS_RATE(mcs, true, false) >= f->dmaxferrate) &&
+ (count == f->mcs2ampdu_table[mcs])) {
+ BCMMSG(wlc->wiphy, "wl%d: PR 37644: stopping"
+ " ampdu at %d for mcs %d\n",
+ wlc->pub->unit, count, mcs);
+ break;
+ }
+
+ if (count == scb_ampdu->max_pdu) {
+ break;
+ }
+
+ /* check to see if the next pkt is a candidate for aggregation */
+ p = pktq_ppeek(&qi->q, prec);
+ tx_info = IEEE80211_SKB_CB(p); /* tx_info must be checked with current p */
+
+ if (p) {
+ if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
+ ((u8) (p->priority) == tid)) {
+
+ plen = brcmu_pkttotlen(p) +
+ AMPDU_MAX_MPDU_OVERHEAD;
+ plen = max(scb_ampdu->min_len, plen);
+
+ if ((plen + ampdu_len) > maxlen) {
+ p = NULL;
+ wiphy_err(wiphy, "%s: Bogus plen #1\n",
+ __func__);
+ continue;
+ }
+
+ /* check if there are enough descriptors available */
+ if (TXAVAIL(wlc, fifo) <= (seg_cnt + 1)) {
+ wiphy_err(wiphy, "%s: No fifo space "
+ "!!\n", __func__);
+ p = NULL;
+ continue;
+ }
+ p = brcmu_pktq_pdeq(&qi->q, prec);
+ } else {
+ p = NULL;
+ }
+ }
+ } /* end while(p) */
+
+ ini->tx_in_transit += count;
+
+ if (count) {
+ /* patch up the last txh */
+ txh = (d11txh_t *) pkt[count - 1]->data;
+ mcl = le16_to_cpu(txh->MacTxControlLow);
+ mcl &= ~TXC_AMPDU_MASK;
+ mcl |= (TXC_AMPDU_LAST << TXC_AMPDU_SHIFT);
+ txh->MacTxControlLow = cpu_to_le16(mcl);
+
+ /* remove the null delimiter after last mpdu */
+ ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
+ txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 0;
+ ampdu_len -= ndelim * AMPDU_DELIMITER_LEN;
+
+ /* remove the pad len from last mpdu */
+ fbr_iscck = ((le16_to_cpu(txh->XtraFrameTypes) & 0x3) == 0);
+ len = fbr_iscck ? WLC_GET_CCK_PLCP_LEN(txh->FragPLCPFallback)
+ : WLC_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
+ ampdu_len -= roundup(len, 4) - len;
+
+ /* patch up the first txh & plcp */
+ txh = (d11txh_t *) pkt[0]->data;
+ plcp = (u8 *) (txh + 1);
+
+ WLC_SET_MIMO_PLCP_LEN(plcp, ampdu_len);
+ /* mark plcp to indicate ampdu */
+ WLC_SET_MIMO_PLCP_AMPDU(plcp);
+
+ /* reset the mixed mode header durations */
+ if (txh->MModeLen) {
+ u16 mmodelen =
+ wlc_calc_lsig_len(wlc, rspec, ampdu_len);
+ txh->MModeLen = cpu_to_le16(mmodelen);
+ preamble_type = WLC_MM_PREAMBLE;
+ }
+ if (txh->MModeFbrLen) {
+ u16 mmfbrlen =
+ wlc_calc_lsig_len(wlc, rspec_fallback, ampdu_len);
+ txh->MModeFbrLen = cpu_to_le16(mmfbrlen);
+ fbr_preamble_type = WLC_MM_PREAMBLE;
+ }
+
+ /* set the preload length */
+ if (MCS_RATE(mcs, true, false) >= f->dmaxferrate) {
+ dma_len = min(dma_len, f->ampdu_pld_size);
+ txh->PreloadSize = cpu_to_le16(dma_len);
+ } else
+ txh->PreloadSize = 0;
+
+ mch = le16_to_cpu(txh->MacTxControlHigh);
+
+ /* update RTS dur fields */
+ if (use_rts || use_cts) {
+ u16 durid;
+ rts = (struct ieee80211_rts *)&txh->rts_frame;
+ if ((mch & TXC_PREAMBLE_RTS_MAIN_SHORT) ==
+ TXC_PREAMBLE_RTS_MAIN_SHORT)
+ rts_preamble_type = WLC_SHORT_PREAMBLE;
+
+ if ((mch & TXC_PREAMBLE_RTS_FB_SHORT) ==
+ TXC_PREAMBLE_RTS_FB_SHORT)
+ rts_fbr_preamble_type = WLC_SHORT_PREAMBLE;
+
+ durid =
+ wlc_compute_rtscts_dur(wlc, use_cts, rts_rspec,
+ rspec, rts_preamble_type,
+ preamble_type, ampdu_len,
+ true);
+ rts->duration = cpu_to_le16(durid);
+ durid = wlc_compute_rtscts_dur(wlc, use_cts,
+ rts_rspec_fallback,
+ rspec_fallback,
+ rts_fbr_preamble_type,
+ fbr_preamble_type,
+ ampdu_len, true);
+ txh->RTSDurFallback = cpu_to_le16(durid);
+ /* set TxFesTimeNormal */
+ txh->TxFesTimeNormal = rts->duration;
+ /* set fallback rate version of TxFesTimeNormal */
+ txh->TxFesTimeFallback = txh->RTSDurFallback;
+ }
+
+ /* set flag and plcp for fallback rate */
+ if (fbr) {
+ mch |= TXC_AMPDU_FBR;
+ txh->MacTxControlHigh = cpu_to_le16(mch);
+ WLC_SET_MIMO_PLCP_AMPDU(plcp);
+ WLC_SET_MIMO_PLCP_AMPDU(txh->FragPLCPFallback);
+ }
+
+ BCMMSG(wlc->wiphy, "wl%d: count %d ampdu_len %d\n",
+ wlc->pub->unit, count, ampdu_len);
+
+ /* inform rate_sel if it this is a rate probe pkt */
+ frameid = le16_to_cpu(txh->TxFrameID);
+ if (frameid & TXFID_RATE_PROBE_MASK) {
+ wiphy_err(wiphy, "%s: XXX what to do with "
+ "TXFID_RATE_PROBE_MASK!?\n", __func__);
+ }
+ for (i = 0; i < count; i++)
+ wlc_txfifo(wlc, fifo, pkt[i], i == (count - 1),
+ ampdu->txpkt_weight);
+
+ }
+ /* endif (count) */
+ return err;
+}
+
+void
+wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
+ struct sk_buff *p, tx_status_t *txs)
+{
+ scb_ampdu_t *scb_ampdu;
+ struct wlc_info *wlc = ampdu->wlc;
+ scb_ampdu_tid_ini_t *ini;
+ u32 s1 = 0, s2 = 0;
+ struct ieee80211_tx_info *tx_info;
+
+ tx_info = IEEE80211_SKB_CB(p);
+
+ /* BMAC_NOTE: For the split driver, second level txstatus comes later
+ * So if the ACK was received then wait for the second level else just
+ * call the first one
+ */
+ if (txs->status & TX_STATUS_ACK_RCV) {
+ u8 status_delay = 0;
+
+ /* wait till the next 8 bytes of txstatus is available */
+ while (((s1 = R_REG(&wlc->regs->frmtxstatus)) & TXS_V) == 0) {
+ udelay(1);
+ status_delay++;
+ if (status_delay > 10) {
+ return; /* error condition */
+ }
+ }
+
+ s2 = R_REG(&wlc->regs->frmtxstatus2);
+ }
+
+ if (likely(scb)) {
+ scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
+ ini = SCB_AMPDU_INI(scb_ampdu, p->priority);
+ wlc_ampdu_dotxstatus_complete(ampdu, scb, p, txs, s1, s2);
+ } else {
+ /* loop through all pkts and free */
+ u8 queue = txs->frameid & TXFID_QUEUE_MASK;
+ d11txh_t *txh;
+ u16 mcl;
+ while (p) {
+ tx_info = IEEE80211_SKB_CB(p);
+ txh = (d11txh_t *) p->data;
+ mcl = le16_to_cpu(txh->MacTxControlLow);
+ brcmu_pkt_buf_free_skb(p);
+ /* break out if last packet of ampdu */
+ if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
+ TXC_AMPDU_LAST)
+ break;
+ p = GETNEXTTXP(wlc, queue);
+ }
+ wlc_txfifo_complete(wlc, queue, ampdu->txpkt_weight);
+ }
+ wlc_ampdu_txflowcontrol(wlc, scb_ampdu, ini);
+}
+
+static void
+rate_status(struct wlc_info *wlc, struct ieee80211_tx_info *tx_info,
+ tx_status_t *txs, u8 mcs)
+{
+ struct ieee80211_tx_rate *txrate = tx_info->status.rates;
+ int i;
+
+ /* clear the rest of the rates */
+ for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
+ txrate[i].idx = -1;
+ txrate[i].count = 0;
+ }
+}
+
+#define SHORTNAME "AMPDU status"
+
+static void
+wlc_ampdu_dotxstatus_complete(struct ampdu_info *ampdu, struct scb *scb,
+ struct sk_buff *p, tx_status_t *txs,
+ u32 s1, u32 s2)
+{
+ scb_ampdu_t *scb_ampdu;
+ struct wlc_info *wlc = ampdu->wlc;
+ scb_ampdu_tid_ini_t *ini;
+ u8 bitmap[8], queue, tid;
+ d11txh_t *txh;
+ u8 *plcp;
+ struct ieee80211_hdr *h;
+ u16 seq, start_seq = 0, bindex, index, mcl;
+ u8 mcs = 0;
+ bool ba_recd = false, ack_recd = false;
+ u8 suc_mpdu = 0, tot_mpdu = 0;
+ uint supr_status;
+ bool update_rate = true, retry = true, tx_error = false;
+ u16 mimoantsel = 0;
+ u8 antselid = 0;
+ u8 retry_limit, rr_retry_limit;
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
+ struct wiphy *wiphy = wlc->wiphy;
+
+#ifdef BCMDBG
+ u8 hole[AMPDU_MAX_MPDU];
+ memset(hole, 0, sizeof(hole));
+#endif
+
+ scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
+ tid = (u8) (p->priority);
+
+ ini = SCB_AMPDU_INI(scb_ampdu, tid);
+ retry_limit = ampdu->retry_limit_tid[tid];
+ rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
+ memset(bitmap, 0, sizeof(bitmap));
+ queue = txs->frameid & TXFID_QUEUE_MASK;
+ supr_status = txs->status & TX_STATUS_SUPR_MASK;
+
+ if (txs->status & TX_STATUS_ACK_RCV) {
+ if (TX_STATUS_SUPR_UF == supr_status) {
+ update_rate = false;
+ }
+
+ WARN_ON(!(txs->status & TX_STATUS_INTERMEDIATE));
+ start_seq = txs->sequence >> SEQNUM_SHIFT;
+ bitmap[0] = (txs->status & TX_STATUS_BA_BMAP03_MASK) >>
+ TX_STATUS_BA_BMAP03_SHIFT;
+
+ WARN_ON(s1 & TX_STATUS_INTERMEDIATE);
+ WARN_ON(!(s1 & TX_STATUS_AMPDU));
+
+ bitmap[0] |=
+ (s1 & TX_STATUS_BA_BMAP47_MASK) <<
+ TX_STATUS_BA_BMAP47_SHIFT;
+ bitmap[1] = (s1 >> 8) & 0xff;
+ bitmap[2] = (s1 >> 16) & 0xff;
+ bitmap[3] = (s1 >> 24) & 0xff;
+
+ bitmap[4] = s2 & 0xff;
+ bitmap[5] = (s2 >> 8) & 0xff;
+ bitmap[6] = (s2 >> 16) & 0xff;
+ bitmap[7] = (s2 >> 24) & 0xff;
+
+ ba_recd = true;
+ } else {
+ if (supr_status) {
+ update_rate = false;
+ if (supr_status == TX_STATUS_SUPR_BADCH) {
+ wiphy_err(wiphy, "%s: Pkt tx suppressed, "
+ "illegal channel possibly %d\n",
+ __func__, CHSPEC_CHANNEL(
+ wlc->default_bss->chanspec));
+ } else {
+ if (supr_status != TX_STATUS_SUPR_FRAG)
+ wiphy_err(wiphy, "%s: wlc_ampdu_dotx"
+ "status:supr_status 0x%x\n",
+ __func__, supr_status);
+ }
+ /* no need to retry for badch; will fail again */
+ if (supr_status == TX_STATUS_SUPR_BADCH ||
+ supr_status == TX_STATUS_SUPR_EXPTIME) {
+ retry = false;
+ } else if (supr_status == TX_STATUS_SUPR_EXPTIME) {
+ /* TX underflow : try tuning pre-loading or ampdu size */
+ } else if (supr_status == TX_STATUS_SUPR_FRAG) {
+ /* if there were underflows, but pre-loading is not active,
+ notify rate adaptation.
+ */
+ if (wlc_ffpld_check_txfunfl(wlc, prio2fifo[tid])
+ > 0) {
+ tx_error = true;
+ }
+ }
+ } else if (txs->phyerr) {
+ update_rate = false;
+ wiphy_err(wiphy, "wl%d: wlc_ampdu_dotxstatus: tx phy "
+ "error (0x%x)\n", wlc->pub->unit,
+ txs->phyerr);
+
+ if (WL_ERROR_ON()) {
+ brcmu_prpkt("txpkt (AMPDU)", p);
+ wlc_print_txdesc((d11txh_t *) p->data);
+ }
+ wlc_print_txstatus(txs);
+ }
+ }
+
+ /* loop through all pkts and retry if not acked */
+ while (p) {
+ tx_info = IEEE80211_SKB_CB(p);
+ txh = (d11txh_t *) p->data;
+ mcl = le16_to_cpu(txh->MacTxControlLow);
+ plcp = (u8 *) (txh + 1);
+ h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
+ seq = le16_to_cpu(h->seq_ctrl) >> SEQNUM_SHIFT;
+
+ if (tot_mpdu == 0) {
+ mcs = plcp[0] & MIMO_PLCP_MCS_MASK;
+ mimoantsel = le16_to_cpu(txh->ABI_MimoAntSel);
+ }
+
+ index = TX_SEQ_TO_INDEX(seq);
+ ack_recd = false;
+ if (ba_recd) {
+ bindex = MODSUB_POW2(seq, start_seq, SEQNUM_MAX);
+ BCMMSG(wlc->wiphy, "tid %d seq %d,"
+ " start_seq %d, bindex %d set %d, index %d\n",
+ tid, seq, start_seq, bindex,
+ isset(bitmap, bindex), index);
+ /* if acked then clear bit and free packet */
+ if ((bindex < AMPDU_TX_BA_MAX_WSIZE)
+ && isset(bitmap, bindex)) {
+ ini->tx_in_transit--;
+ ini->txretry[index] = 0;
+
+ /* ampdu_ack_len: number of acked aggregated frames */
+ /* ampdu_len: number of aggregated frames */
+ rate_status(wlc, tx_info, txs, mcs);
+ tx_info->flags |= IEEE80211_TX_STAT_ACK;
+ tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
+ tx_info->status.ampdu_ack_len =
+ tx_info->status.ampdu_len = 1;
+
+ skb_pull(p, D11_PHY_HDR_LEN);
+ skb_pull(p, D11_TXH_LEN);
+
+ ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
+ p);
+ ack_recd = true;
+ suc_mpdu++;
+ }
+ }
+ /* either retransmit or send bar if ack not recd */
+ if (!ack_recd) {
+ struct ieee80211_tx_rate *txrate =
+ tx_info->status.rates;
+ if (retry && (txrate[0].count < (int)retry_limit)) {
+ ini->txretry[index]++;
+ ini->tx_in_transit--;
+ /* Use high prededence for retransmit to give some punch */
+ /* wlc_txq_enq(wlc, scb, p, WLC_PRIO_TO_PREC(tid)); */
+ wlc_txq_enq(wlc, scb, p,
+ WLC_PRIO_TO_HI_PREC(tid));
+ } else {
+ /* Retry timeout */
+ ini->tx_in_transit--;
+ ieee80211_tx_info_clear_status(tx_info);
+ tx_info->status.ampdu_ack_len = 0;
+ tx_info->status.ampdu_len = 1;
+ tx_info->flags |=
+ IEEE80211_TX_STAT_AMPDU_NO_BACK;
+ skb_pull(p, D11_PHY_HDR_LEN);
+ skb_pull(p, D11_TXH_LEN);
+ wiphy_err(wiphy, "%s: BA Timeout, seq %d, in_"
+ "transit %d\n", SHORTNAME, seq,
+ ini->tx_in_transit);
+ ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
+ p);
+ }
+ }
+ tot_mpdu++;
+
+ /* break out if last packet of ampdu */
+ if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
+ TXC_AMPDU_LAST)
+ break;
+
+ p = GETNEXTTXP(wlc, queue);
+ }
+ wlc_send_q(wlc);
+
+ /* update rate state */
+ antselid = wlc_antsel_antsel2id(wlc->asi, mimoantsel);
+
+ wlc_txfifo_complete(wlc, queue, ampdu->txpkt_weight);
+}
+
+/* initialize the initiator code for tid */
+static scb_ampdu_tid_ini_t *wlc_ampdu_init_tid_ini(struct ampdu_info *ampdu,
+ scb_ampdu_t *scb_ampdu,
+ u8 tid, bool override)
+{
+ scb_ampdu_tid_ini_t *ini;
+
+ /* check for per-tid control of ampdu */
+ if (!ampdu->ini_enable[tid]) {
+ wiphy_err(ampdu->wlc->wiphy, "%s: Rejecting tid %d\n",
+ __func__, tid);
+ return NULL;
+ }
+
+ ini = SCB_AMPDU_INI(scb_ampdu, tid);
+ ini->tid = tid;
+ ini->scb = scb_ampdu->scb;
+ ini->magic = INI_MAGIC;
+ return ini;
+}
+
+static int wlc_ampdu_set(struct ampdu_info *ampdu, bool on)
+{
+ struct wlc_info *wlc = ampdu->wlc;
+
+ wlc->pub->_ampdu = false;
+
+ if (on) {
+ if (!N_ENAB(wlc->pub)) {
+ wiphy_err(ampdu->wlc->wiphy, "wl%d: driver not "
+ "nmode enabled\n", wlc->pub->unit);
+ return -ENOTSUPP;
+ }
+ if (!wlc_ampdu_cap(ampdu)) {
+ wiphy_err(ampdu->wlc->wiphy, "wl%d: device not "
+ "ampdu capable\n", wlc->pub->unit);
+ return -ENOTSUPP;
+ }
+ wlc->pub->_ampdu = on;
+ }
+
+ return 0;
+}
+
+static bool wlc_ampdu_cap(struct ampdu_info *ampdu)
+{
+ if (WLC_PHY_11N_CAP(ampdu->wlc->band))
+ return true;
+ else
+ return false;
+}
+
+static void ampdu_update_max_txlen(struct ampdu_info *ampdu, u8 dur)
+{
+ u32 rate, mcs;
+
+ for (mcs = 0; mcs < MCS_TABLE_SIZE; mcs++) {
+ /* rate is in Kbps; dur is in msec ==> len = (rate * dur) / 8 */
+ /* 20MHz, No SGI */
+ rate = MCS_RATE(mcs, false, false);
+ ampdu->max_txlen[mcs][0][0] = (rate * dur) >> 3;
+ /* 40 MHz, No SGI */
+ rate = MCS_RATE(mcs, true, false);
+ ampdu->max_txlen[mcs][1][0] = (rate * dur) >> 3;
+ /* 20MHz, SGI */
+ rate = MCS_RATE(mcs, false, true);
+ ampdu->max_txlen[mcs][0][1] = (rate * dur) >> 3;
+ /* 40 MHz, SGI */
+ rate = MCS_RATE(mcs, true, true);
+ ampdu->max_txlen[mcs][1][1] = (rate * dur) >> 3;
+ }
+}
+
+void wlc_ampdu_macaddr_upd(struct wlc_info *wlc)
+{
+ char template[T_RAM_ACCESS_SZ * 2];
+
+ /* driver needs to write the ta in the template; ta is at offset 16 */
+ memset(template, 0, sizeof(template));
+ memcpy(template, wlc->pub->cur_etheraddr, ETH_ALEN);
+ wlc_write_template_ram(wlc, (T_BA_TPL_BASE + 16), (T_RAM_ACCESS_SZ * 2),
+ template);
+}
+
+bool wlc_aggregatable(struct wlc_info *wlc, u8 tid)
+{
+ return wlc->ampdu->ini_enable[tid];
+}
+
+void wlc_ampdu_shm_upd(struct ampdu_info *ampdu)
+{
+ struct wlc_info *wlc = ampdu->wlc;
+
+ /* Extend ucode internal watchdog timer to match larger received frames */
+ if ((ampdu->rx_factor & IEEE80211_HT_AMPDU_PARM_FACTOR) ==
+ IEEE80211_HT_MAX_AMPDU_64K) {
+ wlc_write_shm(wlc, M_MIMO_MAXSYM, MIMO_MAXSYM_MAX);
+ wlc_write_shm(wlc, M_WATCHDOG_8TU, WATCHDOG_8TU_MAX);
+ } else {
+ wlc_write_shm(wlc, M_MIMO_MAXSYM, MIMO_MAXSYM_DEF);
+ wlc_write_shm(wlc, M_WATCHDOG_8TU, WATCHDOG_8TU_DEF);
+ }
+}
+
+/*
+ * callback function that helps flushing ampdu packets from a priority queue
+ */
+static bool cb_del_ampdu_pkt(struct sk_buff *mpdu, void *arg_a)
+{
+ struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(mpdu);
+ struct cb_del_ampdu_pars *ampdu_pars =
+ (struct cb_del_ampdu_pars *)arg_a;
+ bool rc;
+
+ rc = tx_info->flags & IEEE80211_TX_CTL_AMPDU ? true : false;
+ rc = rc && (tx_info->control.sta == NULL || ampdu_pars->sta == NULL ||
+ tx_info->control.sta == ampdu_pars->sta);
+ rc = rc && ((u8)(mpdu->priority) == ampdu_pars->tid);
+ return rc;
+}
+
+/*
+ * callback function that helps invalidating ampdu packets in a DMA queue
+ */
+static void dma_cb_fn_ampdu(void *txi, void *arg_a)
+{
+ struct ieee80211_sta *sta = arg_a;
+ struct ieee80211_tx_info *tx_info = (struct ieee80211_tx_info *)txi;
+
+ if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
+ (tx_info->control.sta == sta || sta == NULL))
+ tx_info->control.sta = NULL;
+}
+
+/*
+ * When a remote party is no longer available for ampdu communication, any
+ * pending tx ampdu packets in the driver have to be flushed.
+ */
+void wlc_ampdu_flush(struct wlc_info *wlc,
+ struct ieee80211_sta *sta, u16 tid)
+{
+ struct wlc_txq_info *qi = wlc->pkt_queue;
+ struct pktq *pq = &qi->q;
+ int prec;
+ struct cb_del_ampdu_pars ampdu_pars;
+
+ ampdu_pars.sta = sta;
+ ampdu_pars.tid = tid;
+ for (prec = 0; prec < pq->num_prec; prec++) {
+ brcmu_pktq_pflush(pq, prec, true, cb_del_ampdu_pkt,
+ (void *)&du_pars);
+ }
+ wlc_inval_dma_pkts(wlc->hw, sta, dma_cb_fn_ampdu);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_AMPDU_H_
+#define _BRCM_AMPDU_H_
+
+extern struct ampdu_info *wlc_ampdu_attach(struct wlc_info *wlc);
+extern void wlc_ampdu_detach(struct ampdu_info *ampdu);
+extern int wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
+ struct sk_buff **aggp, int prec);
+extern void wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
+ struct sk_buff *p, tx_status_t *txs);
+extern void wlc_ampdu_macaddr_upd(struct wlc_info *wlc);
+extern void wlc_ampdu_shm_upd(struct ampdu_info *ampdu);
+
+#endif /* _BRCM_AMPDU_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <cfg.h>
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include <defs.h>
+#include <brcmu_utils.h>
+#include <aiutils.h>
+#include <brcm_hw_ids.h>
+#include "dma.h"
+
+#include "d11.h"
+#include "rate.h"
+#include "key.h"
+#include "scb.h"
+#include "pub.h"
+#include "phy/phy_hal.h"
+#include "bottom_mac.h"
+#include "channel.h"
+#include "main.h"
+#include "antsel.h"
+
+#define ANT_SELCFG_AUTO 0x80 /* bit indicates antenna sel AUTO */
+#define ANT_SELCFG_MASK 0x33 /* antenna configuration mask */
+#define ANT_SELCFG_TX_UNICAST 0 /* unicast tx antenna configuration */
+#define ANT_SELCFG_RX_UNICAST 1 /* unicast rx antenna configuration */
+#define ANT_SELCFG_TX_DEF 2 /* default tx antenna configuration */
+#define ANT_SELCFG_RX_DEF 3 /* default rx antenna configuration */
+
+/* useful macros */
+#define WLC_ANTSEL_11N_0(ant) ((((ant) & ANT_SELCFG_MASK) >> 4) & 0xf)
+#define WLC_ANTSEL_11N_1(ant) (((ant) & ANT_SELCFG_MASK) & 0xf)
+#define WLC_ANTIDX_11N(ant) (((WLC_ANTSEL_11N_0(ant)) << 2) + (WLC_ANTSEL_11N_1(ant)))
+#define WLC_ANT_ISAUTO_11N(ant) (((ant) & ANT_SELCFG_AUTO) == ANT_SELCFG_AUTO)
+#define WLC_ANTSEL_11N(ant) ((ant) & ANT_SELCFG_MASK)
+
+/* antenna switch */
+/* defines for no boardlevel antenna diversity */
+#define ANT_SELCFG_DEF_2x2 0x01 /* default antenna configuration */
+
+/* 2x3 antdiv defines and tables for GPIO communication */
+#define ANT_SELCFG_NUM_2x3 3
+#define ANT_SELCFG_DEF_2x3 0x01 /* default antenna configuration */
+
+/* 2x4 antdiv rev4 defines and tables for GPIO communication */
+#define ANT_SELCFG_NUM_2x4 4
+#define ANT_SELCFG_DEF_2x4 0x02 /* default antenna configuration */
+
+/* static functions */
+static int wlc_antsel_cfgupd(struct antsel_info *asi, wlc_antselcfg_t *antsel);
+static u8 wlc_antsel_id2antcfg(struct antsel_info *asi, u8 id);
+static u16 wlc_antsel_antcfg2antsel(struct antsel_info *asi, u8 ant_cfg);
+static void wlc_antsel_init_cfg(struct antsel_info *asi,
+ wlc_antselcfg_t *antsel,
+ bool auto_sel);
+
+const u16 mimo_2x4_div_antselpat_tbl[] = {
+ 0, 0, 0x9, 0xa, /* ant0: 0 ant1: 2,3 */
+ 0, 0, 0x5, 0x6, /* ant0: 1 ant1: 2,3 */
+ 0, 0, 0, 0, /* n.a. */
+ 0, 0, 0, 0 /* n.a. */
+};
+
+const u8 mimo_2x4_div_antselid_tbl[16] = {
+ 0, 0, 0, 0, 0, 2, 3, 0,
+ 0, 0, 1, 0, 0, 0, 0, 0 /* pat to antselid */
+};
+
+const u16 mimo_2x3_div_antselpat_tbl[] = {
+ 16, 0, 1, 16, /* ant0: 0 ant1: 1,2 */
+ 16, 16, 16, 16, /* n.a. */
+ 16, 2, 16, 16, /* ant0: 2 ant1: 1 */
+ 16, 16, 16, 16 /* n.a. */
+};
+
+const u8 mimo_2x3_div_antselid_tbl[16] = {
+ 0, 1, 2, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 /* pat to antselid */
+};
+
+struct antsel_info *wlc_antsel_attach(struct wlc_info *wlc)
+{
+ struct antsel_info *asi;
+
+ asi = kzalloc(sizeof(struct antsel_info), GFP_ATOMIC);
+ if (!asi) {
+ wiphy_err(wlc->wiphy, "wl%d: wlc_antsel_attach: out of mem\n",
+ wlc->pub->unit);
+ return NULL;
+ }
+
+ asi->wlc = wlc;
+ asi->pub = wlc->pub;
+ asi->antsel_type = ANTSEL_NA;
+ asi->antsel_avail = false;
+ asi->antsel_antswitch = (u8) getintvar(asi->pub->vars, "antswitch");
+
+ if ((asi->pub->sromrev >= 4) && (asi->antsel_antswitch != 0)) {
+ switch (asi->antsel_antswitch) {
+ case ANTSWITCH_TYPE_1:
+ case ANTSWITCH_TYPE_2:
+ case ANTSWITCH_TYPE_3:
+ /* 4321/2 board with 2x3 switch logic */
+ asi->antsel_type = ANTSEL_2x3;
+ /* Antenna selection availability */
+ if (((u16) getintvar(asi->pub->vars, "aa2g") == 7) ||
+ ((u16) getintvar(asi->pub->vars, "aa5g") == 7)) {
+ asi->antsel_avail = true;
+ } else
+ if (((u16) getintvar(asi->pub->vars, "aa2g") ==
+ 3)
+ || ((u16) getintvar(asi->pub->vars, "aa5g")
+ == 3)) {
+ asi->antsel_avail = false;
+ } else {
+ asi->antsel_avail = false;
+ wiphy_err(wlc->wiphy, "wlc_antsel_attach: 2o3 "
+ "board cfg invalid\n");
+ }
+ break;
+ default:
+ break;
+ }
+ } else if ((asi->pub->sromrev == 4) &&
+ ((u16) getintvar(asi->pub->vars, "aa2g") == 7) &&
+ ((u16) getintvar(asi->pub->vars, "aa5g") == 0)) {
+ /* hack to match old 4321CB2 cards with 2of3 antenna switch */
+ asi->antsel_type = ANTSEL_2x3;
+ asi->antsel_avail = true;
+ } else if (asi->pub->boardflags2 & BFL2_2X4_DIV) {
+ asi->antsel_type = ANTSEL_2x4;
+ asi->antsel_avail = true;
+ }
+
+ /* Set the antenna selection type for the low driver */
+ wlc_bmac_antsel_type_set(wlc->hw, asi->antsel_type);
+
+ /* Init (auto/manual) antenna selection */
+ wlc_antsel_init_cfg(asi, &asi->antcfg_11n, true);
+ wlc_antsel_init_cfg(asi, &asi->antcfg_cur, true);
+
+ return asi;
+}
+
+void wlc_antsel_detach(struct antsel_info *asi)
+{
+ kfree(asi);
+}
+
+void wlc_antsel_init(struct antsel_info *asi)
+{
+ if ((asi->antsel_type == ANTSEL_2x3) ||
+ (asi->antsel_type == ANTSEL_2x4))
+ wlc_antsel_cfgupd(asi, &asi->antcfg_11n);
+}
+
+/* boardlevel antenna selection: init antenna selection structure */
+static void
+wlc_antsel_init_cfg(struct antsel_info *asi, wlc_antselcfg_t *antsel,
+ bool auto_sel)
+{
+ if (asi->antsel_type == ANTSEL_2x3) {
+ u8 antcfg_def = ANT_SELCFG_DEF_2x3 |
+ ((asi->antsel_avail && auto_sel) ? ANT_SELCFG_AUTO : 0);
+ antsel->ant_config[ANT_SELCFG_TX_DEF] = antcfg_def;
+ antsel->ant_config[ANT_SELCFG_TX_UNICAST] = antcfg_def;
+ antsel->ant_config[ANT_SELCFG_RX_DEF] = antcfg_def;
+ antsel->ant_config[ANT_SELCFG_RX_UNICAST] = antcfg_def;
+ antsel->num_antcfg = ANT_SELCFG_NUM_2x3;
+
+ } else if (asi->antsel_type == ANTSEL_2x4) {
+
+ antsel->ant_config[ANT_SELCFG_TX_DEF] = ANT_SELCFG_DEF_2x4;
+ antsel->ant_config[ANT_SELCFG_TX_UNICAST] = ANT_SELCFG_DEF_2x4;
+ antsel->ant_config[ANT_SELCFG_RX_DEF] = ANT_SELCFG_DEF_2x4;
+ antsel->ant_config[ANT_SELCFG_RX_UNICAST] = ANT_SELCFG_DEF_2x4;
+ antsel->num_antcfg = ANT_SELCFG_NUM_2x4;
+
+ } else { /* no antenna selection available */
+
+ antsel->ant_config[ANT_SELCFG_TX_DEF] = ANT_SELCFG_DEF_2x2;
+ antsel->ant_config[ANT_SELCFG_TX_UNICAST] = ANT_SELCFG_DEF_2x2;
+ antsel->ant_config[ANT_SELCFG_RX_DEF] = ANT_SELCFG_DEF_2x2;
+ antsel->ant_config[ANT_SELCFG_RX_UNICAST] = ANT_SELCFG_DEF_2x2;
+ antsel->num_antcfg = 0;
+ }
+}
+
+void
+wlc_antsel_antcfg_get(struct antsel_info *asi, bool usedef, bool sel,
+ u8 antselid, u8 fbantselid, u8 *antcfg,
+ u8 *fbantcfg)
+{
+ u8 ant;
+
+ /* if use default, assign it and return */
+ if (usedef) {
+ *antcfg = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_DEF];
+ *fbantcfg = *antcfg;
+ return;
+ }
+
+ if (!sel) {
+ *antcfg = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
+ *fbantcfg = *antcfg;
+
+ } else {
+ ant = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
+ if ((ant & ANT_SELCFG_AUTO) == ANT_SELCFG_AUTO) {
+ *antcfg = wlc_antsel_id2antcfg(asi, antselid);
+ *fbantcfg = wlc_antsel_id2antcfg(asi, fbantselid);
+ } else {
+ *antcfg =
+ asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
+ *fbantcfg = *antcfg;
+ }
+ }
+ return;
+}
+
+/* boardlevel antenna selection: convert mimo_antsel (ucode interface) to id */
+u8 wlc_antsel_antsel2id(struct antsel_info *asi, u16 antsel)
+{
+ u8 antselid = 0;
+
+ if (asi->antsel_type == ANTSEL_2x4) {
+ /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
+ antselid = mimo_2x4_div_antselid_tbl[(antsel & 0xf)];
+ return antselid;
+
+ } else if (asi->antsel_type == ANTSEL_2x3) {
+ /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
+ antselid = mimo_2x3_div_antselid_tbl[(antsel & 0xf)];
+ return antselid;
+ }
+
+ return antselid;
+}
+
+/* boardlevel antenna selection: convert id to ant_cfg */
+static u8 wlc_antsel_id2antcfg(struct antsel_info *asi, u8 id)
+{
+ u8 antcfg = ANT_SELCFG_DEF_2x2;
+
+ if (asi->antsel_type == ANTSEL_2x4) {
+ /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
+ antcfg = (((id & 0x2) << 3) | ((id & 0x1) + 2));
+ return antcfg;
+
+ } else if (asi->antsel_type == ANTSEL_2x3) {
+ /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
+ antcfg = (((id & 0x02) << 4) | ((id & 0x1) + 1));
+ return antcfg;
+ }
+
+ return antcfg;
+}
+
+/* boardlevel antenna selection: convert ant_cfg to mimo_antsel (ucode interface) */
+static u16 wlc_antsel_antcfg2antsel(struct antsel_info *asi, u8 ant_cfg)
+{
+ u8 idx = WLC_ANTIDX_11N(WLC_ANTSEL_11N(ant_cfg));
+ u16 mimo_antsel = 0;
+
+ if (asi->antsel_type == ANTSEL_2x4) {
+ /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
+ mimo_antsel = (mimo_2x4_div_antselpat_tbl[idx] & 0xf);
+ return mimo_antsel;
+
+ } else if (asi->antsel_type == ANTSEL_2x3) {
+ /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
+ mimo_antsel = (mimo_2x3_div_antselpat_tbl[idx] & 0xf);
+ return mimo_antsel;
+ }
+
+ return mimo_antsel;
+}
+
+/* boardlevel antenna selection: ucode interface control */
+static int wlc_antsel_cfgupd(struct antsel_info *asi, wlc_antselcfg_t *antsel)
+{
+ struct wlc_info *wlc = asi->wlc;
+ u8 ant_cfg;
+ u16 mimo_antsel;
+
+ /* 1) Update TX antconfig for all frames that are not unicast data
+ * (aka default TX)
+ */
+ ant_cfg = antsel->ant_config[ANT_SELCFG_TX_DEF];
+ mimo_antsel = wlc_antsel_antcfg2antsel(asi, ant_cfg);
+ wlc_write_shm(wlc, M_MIMO_ANTSEL_TXDFLT, mimo_antsel);
+ /* Update driver stats for currently selected default tx/rx antenna config */
+ asi->antcfg_cur.ant_config[ANT_SELCFG_TX_DEF] = ant_cfg;
+
+ /* 2) Update RX antconfig for all frames that are not unicast data
+ * (aka default RX)
+ */
+ ant_cfg = antsel->ant_config[ANT_SELCFG_RX_DEF];
+ mimo_antsel = wlc_antsel_antcfg2antsel(asi, ant_cfg);
+ wlc_write_shm(wlc, M_MIMO_ANTSEL_RXDFLT, mimo_antsel);
+ /* Update driver stats for currently selected default tx/rx antenna config */
+ asi->antcfg_cur.ant_config[ANT_SELCFG_RX_DEF] = ant_cfg;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_ANTSEL_H_
+#define _BRCM_ANTSEL_H_
+
+extern struct antsel_info *wlc_antsel_attach(struct wlc_info *wlc);
+extern void wlc_antsel_detach(struct antsel_info *asi);
+extern void wlc_antsel_init(struct antsel_info *asi);
+extern void wlc_antsel_antcfg_get(struct antsel_info *asi, bool usedef,
+ bool sel,
+ u8 id, u8 fbid, u8 *antcfg,
+ u8 *fbantcfg);
+extern u8 wlc_antsel_antsel2id(struct antsel_info *asi, u16 antsel);
+
+#endif /* _BRCM_ANTSEL_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_DMA_H_
-#define _BRCM_DMA_H_
-
-#include "wlc_types.h" /* forward structure declarations */
-
-#ifndef _dma_pub_
-#define _dma_pub_
-struct dma_pub;
-#endif /* _dma_pub_ */
-
-/* DMA structure:
- * support two DMA engines: 32 bits address or 64 bit addressing
- * basic DMA register set is per channel(transmit or receive)
- * a pair of channels is defined for convenience
- */
-
-/* 32 bits addressing */
-
-typedef volatile struct { /* diag access */
- u32 fifoaddr; /* diag address */
- u32 fifodatalow; /* low 32bits of data */
- u32 fifodatahigh; /* high 32bits of data */
- u32 pad; /* reserved */
-} dma32diag_t;
-
-/* 64 bits addressing */
-
-/* dma registers per channel(xmt or rcv) */
-typedef volatile struct {
- u32 control; /* enable, et al */
- u32 ptr; /* last descriptor posted to chip */
- u32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
- u32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
- u32 status0; /* current descriptor, xmt state */
- u32 status1; /* active descriptor, xmt error */
-} dma64regs_t;
-
-/* map/unmap direction */
-#define DMA_TX 1 /* TX direction for DMA */
-#define DMA_RX 2 /* RX direction for DMA */
-#define BUS_SWAP32(v) (v)
-
-/* range param for dma_getnexttxp() and dma_txreclaim */
-typedef enum txd_range {
- DMA_RANGE_ALL = 1,
- DMA_RANGE_TRANSMITTED,
- DMA_RANGE_TRANSFERED
-} txd_range_t;
-
-/* dma function type */
-typedef void (*di_detach_t) (struct dma_pub *dmah);
-typedef bool(*di_txreset_t) (struct dma_pub *dmah);
-typedef bool(*di_rxreset_t) (struct dma_pub *dmah);
-typedef bool(*di_rxidle_t) (struct dma_pub *dmah);
-typedef void (*di_txinit_t) (struct dma_pub *dmah);
-typedef bool(*di_txenabled_t) (struct dma_pub *dmah);
-typedef void (*di_rxinit_t) (struct dma_pub *dmah);
-typedef void (*di_txsuspend_t) (struct dma_pub *dmah);
-typedef void (*di_txresume_t) (struct dma_pub *dmah);
-typedef bool(*di_txsuspended_t) (struct dma_pub *dmah);
-typedef bool(*di_txsuspendedidle_t) (struct dma_pub *dmah);
-typedef int (*di_txfast_t) (struct dma_pub *dmah, struct sk_buff *p,
- bool commit);
-typedef int (*di_txunframed_t) (struct dma_pub *dmah, void *p, uint len,
- bool commit);
-typedef void *(*di_getpos_t) (struct dma_pub *di, bool direction);
-typedef void (*di_fifoloopbackenable_t) (struct dma_pub *dmah);
-typedef bool(*di_txstopped_t) (struct dma_pub *dmah);
-typedef bool(*di_rxstopped_t) (struct dma_pub *dmah);
-typedef bool(*di_rxenable_t) (struct dma_pub *dmah);
-typedef bool(*di_rxenabled_t) (struct dma_pub *dmah);
-typedef void *(*di_rx_t) (struct dma_pub *dmah);
-typedef bool(*di_rxfill_t) (struct dma_pub *dmah);
-typedef void (*di_txreclaim_t) (struct dma_pub *dmah, txd_range_t range);
-typedef void (*di_rxreclaim_t) (struct dma_pub *dmah);
-typedef unsigned long (*di_getvar_t) (struct dma_pub *dmah,
- const char *name);
-typedef void *(*di_getnexttxp_t) (struct dma_pub *dmah, txd_range_t range);
-typedef void *(*di_getnextrxp_t) (struct dma_pub *dmah, bool forceall);
-typedef void *(*di_peeknexttxp_t) (struct dma_pub *dmah);
-typedef void *(*di_peeknextrxp_t) (struct dma_pub *dmah);
-typedef void (*di_rxparam_get_t) (struct dma_pub *dmah, u16 *rxoffset,
- u16 *rxbufsize);
-typedef void (*di_txblock_t) (struct dma_pub *dmah);
-typedef void (*di_txunblock_t) (struct dma_pub *dmah);
-typedef uint(*di_txactive_t) (struct dma_pub *dmah);
-typedef void (*di_txrotate_t) (struct dma_pub *dmah);
-typedef void (*di_counterreset_t) (struct dma_pub *dmah);
-typedef uint(*di_ctrlflags_t) (struct dma_pub *dmah, uint mask, uint flags);
-typedef char *(*di_dump_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
- bool dumpring);
-typedef char *(*di_dumptx_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
- bool dumpring);
-typedef char *(*di_dumprx_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
- bool dumpring);
-typedef uint(*di_rxactive_t) (struct dma_pub *dmah);
-typedef uint(*di_txpending_t) (struct dma_pub *dmah);
-typedef uint(*di_txcommitted_t) (struct dma_pub *dmah);
-
-/* dma opsvec */
-typedef struct di_fcn_s {
- di_detach_t detach;
- di_txinit_t txinit;
- di_txreset_t txreset;
- di_txenabled_t txenabled;
- di_txsuspend_t txsuspend;
- di_txresume_t txresume;
- di_txsuspended_t txsuspended;
- di_txsuspendedidle_t txsuspendedidle;
- di_txfast_t txfast;
- di_txunframed_t txunframed;
- di_getpos_t getpos;
- di_txstopped_t txstopped;
- di_txreclaim_t txreclaim;
- di_getnexttxp_t getnexttxp;
- di_peeknexttxp_t peeknexttxp;
- di_txblock_t txblock;
- di_txunblock_t txunblock;
- di_txactive_t txactive;
- di_txrotate_t txrotate;
-
- di_rxinit_t rxinit;
- di_rxreset_t rxreset;
- di_rxidle_t rxidle;
- di_rxstopped_t rxstopped;
- di_rxenable_t rxenable;
- di_rxenabled_t rxenabled;
- di_rx_t rx;
- di_rxfill_t rxfill;
- di_rxreclaim_t rxreclaim;
- di_getnextrxp_t getnextrxp;
- di_peeknextrxp_t peeknextrxp;
- di_rxparam_get_t rxparam_get;
-
- di_fifoloopbackenable_t fifoloopbackenable;
- di_getvar_t d_getvar;
- di_counterreset_t counterreset;
- di_ctrlflags_t ctrlflags;
- di_dump_t dump;
- di_dumptx_t dumptx;
- di_dumprx_t dumprx;
- di_rxactive_t rxactive;
- di_txpending_t txpending;
- di_txcommitted_t txcommitted;
- uint endnum;
-} di_fcn_t;
-
-/*
- * Exported data structure (read-only)
- */
-/* export structure */
-struct dma_pub {
- const di_fcn_t *di_fn; /* DMA function pointers */
- uint txavail; /* # free tx descriptors */
- uint dmactrlflags; /* dma control flags */
-
- /* rx error counters */
- uint rxgiants; /* rx giant frames */
- uint rxnobuf; /* rx out of dma descriptors */
- /* tx error counters */
- uint txnobuf; /* tx out of dma descriptors */
-};
-
-extern struct dma_pub *dma_attach(char *name, struct si_pub *sih,
- void *dmaregstx, void *dmaregsrx, uint ntxd,
- uint nrxd, uint rxbufsize, int rxextheadroom,
- uint nrxpost, uint rxoffset, uint *msg_level);
-
-extern const di_fcn_t dma64proc;
-
-#define dma_detach(di) (dma64proc.detach(di))
-#define dma_txreset(di) (dma64proc.txreset(di))
-#define dma_rxreset(di) (dma64proc.rxreset(di))
-#define dma_rxidle(di) (dma64proc.rxidle(di))
-#define dma_txinit(di) (dma64proc.txinit(di))
-#define dma_txenabled(di) (dma64proc.txenabled(di))
-#define dma_rxinit(di) (dma64proc.rxinit(di))
-#define dma_txsuspend(di) (dma64proc.txsuspend(di))
-#define dma_txresume(di) (dma64proc.txresume(di))
-#define dma_txsuspended(di) (dma64proc.txsuspended(di))
-#define dma_txsuspendedidle(di) (dma64proc.txsuspendedidle(di))
-#define dma_txfast(di, p, commit) (dma64proc.txfast(di, p, commit))
-#define dma_txunframed(di, p, l, commit)(dma64proc.txunframed(di, p, l, commit))
-#define dma_getpos(di, dir) (dma64proc.getpos(di, dir))
-#define dma_fifoloopbackenable(di) (dma64proc.fifoloopbackenable(di))
-#define dma_txstopped(di) (dma64proc.txstopped(di))
-#define dma_rxstopped(di) (dma64proc.rxstopped(di))
-#define dma_rxenable(di) (dma64proc.rxenable(di))
-#define dma_rxenabled(di) (dma64proc.rxenabled(di))
-#define dma_rx(di) (dma64proc.rx(di))
-#define dma_rxfill(di) (dma64proc.rxfill(di))
-#define dma_txreclaim(di, range) (dma64proc.txreclaim(di, range))
-#define dma_rxreclaim(di) (dma64proc.rxreclaim(di))
-#define dma_getvar(di, name) (dma64proc.d_getvar(di, name))
-#define dma_getnexttxp(di, range) (dma64proc.getnexttxp(di, range))
-#define dma_getnextrxp(di, forceall) (dma64proc.getnextrxp(di, forceall))
-#define dma_peeknexttxp(di) (dma64proc.peeknexttxp(di))
-#define dma_peeknextrxp(di) (dma64proc.peeknextrxp(di))
-#define dma_rxparam_get(di, off, bufs) (dma64proc.rxparam_get(di, off, bufs))
-
-#define dma_txblock(di) (dma64proc.txblock(di))
-#define dma_txunblock(di) (dma64proc.txunblock(di))
-#define dma_txactive(di) (dma64proc.txactive(di))
-#define dma_rxactive(di) (dma64proc.rxactive(di))
-#define dma_txrotate(di) (dma64proc.txrotate(di))
-#define dma_counterreset(di) (dma64proc.counterreset(di))
-#define dma_ctrlflags(di, mask, flags) (dma64proc.ctrlflags((di), (mask), (flags)))
-#define dma_txpending(di) (dma64proc.txpending(di))
-#define dma_txcommitted(di) (dma64proc.txcommitted(di))
-
-
-/* return addresswidth allowed
- * This needs to be done after SB attach but before dma attach.
- * SB attach provides ability to probe backplane and dma core capabilities
- * This info is needed by DMA_ALLOC_CONSISTENT in dma attach
- */
-extern uint dma_addrwidth(struct si_pub *sih, void *dmaregs);
-void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
- (void *pkt, void *arg_a), void *arg_a);
-
-/*
- * DMA(Bug) on some chips seems to declare that the packet is ready, but the
- * packet length is not updated yet (by DMA) on the expected time.
- * Workaround is to hold processor till DMA updates the length, and stay off
- * the bus to allow DMA update the length in buffer
- */
-static inline void dma_spin_for_len(uint len, struct sk_buff *head)
-{
-#if defined(__mips__)
- if (!len) {
- while (!(len = *(u16 *) KSEG1ADDR(head->data)))
- udelay(1);
-
- *(u16 *) (head->data) = cpu_to_le16((u16) len);
- }
-#endif /* defined(__mips__) */
-}
-
-#endif /* _BRCM_DMA_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/crc-ccitt.h>
-
-#include <bcmdefs.h>
-#include <bcmdevs.h>
-#include "wlc_types.h"
-#include <brcmu_utils.h>
-#include <aiutils.h>
-#include <bcmsoc.h>
-#include <chipcommon.h>
-#include <bcmotp.h>
-
-#define OTPS_GUP_MASK 0x00000f00
-#define OTPS_GUP_SHIFT 8
-#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
-#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
-#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
-#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
-
-/* Fields in otpprog in rev >= 21 */
-#define OTPP_COL_MASK 0x000000ff
-#define OTPP_COL_SHIFT 0
-#define OTPP_ROW_MASK 0x0000ff00
-#define OTPP_ROW_SHIFT 8
-#define OTPP_OC_MASK 0x0f000000
-#define OTPP_OC_SHIFT 24
-#define OTPP_READERR 0x10000000
-#define OTPP_VALUE_MASK 0x20000000
-#define OTPP_VALUE_SHIFT 29
-#define OTPP_START_BUSY 0x80000000
-#define OTPP_READ 0x40000000
-
-/* Opcodes for OTPP_OC field */
-#define OTPPOC_READ 0
-#define OTPPOC_BIT_PROG 1
-#define OTPPOC_VERIFY 3
-#define OTPPOC_INIT 4
-#define OTPPOC_SET 5
-#define OTPPOC_RESET 6
-#define OTPPOC_OCST 7
-#define OTPPOC_ROW_LOCK 8
-#define OTPPOC_PRESCN_TEST 9
-
-#define OTPTYPE_IPX(ccrev) ((ccrev) == 21 || (ccrev) >= 23)
-
-#define OTPP_TRIES 10000000 /* # of tries for OTPP */
-
-#define MAXNUMRDES 9 /* Maximum OTP redundancy entries */
-
-/* OTP common function type */
-typedef int (*otp_status_t) (void *oh);
-typedef int (*otp_size_t) (void *oh);
-typedef void *(*otp_init_t) (struct si_pub *sih);
-typedef u16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off);
-typedef int (*otp_read_region_t) (struct si_pub *sih, int region, u16 *data,
- uint *wlen);
-typedef int (*otp_nvread_t) (void *oh, char *data, uint *len);
-
-/* OTP function struct */
-typedef struct otp_fn_s {
- otp_size_t size;
- otp_read_bit_t read_bit;
- otp_init_t init;
- otp_read_region_t read_region;
- otp_nvread_t nvread;
- otp_status_t status;
-} otp_fn_t;
-
-typedef struct {
- uint ccrev; /* chipc revision */
- otp_fn_t *fn; /* OTP functions */
- struct si_pub *sih; /* Saved sb handle */
-
- /* IPX OTP section */
- u16 wsize; /* Size of otp in words */
- u16 rows; /* Geometry */
- u16 cols; /* Geometry */
- u32 status; /* Flag bits (lock/prog/rv).
- * (Reflected only when OTP is power cycled)
- */
- u16 hwbase; /* hardware subregion offset */
- u16 hwlim; /* hardware subregion boundary */
- u16 swbase; /* software subregion offset */
- u16 swlim; /* software subregion boundary */
- u16 fbase; /* fuse subregion offset */
- u16 flim; /* fuse subregion boundary */
- int otpgu_base; /* offset to General Use Region */
-} otpinfo_t;
-
-static otpinfo_t otpinfo;
-
-/*
- * IPX OTP Code
- *
- * Exported functions:
- * ipxotp_status()
- * ipxotp_size()
- * ipxotp_init()
- * ipxotp_read_bit()
- * ipxotp_read_region()
- * ipxotp_nvread()
- *
- */
-
-#define HWSW_RGN(rgn) (((rgn) == OTP_HW_RGN) ? "h/w" : "s/w")
-
-/* OTP layout */
-/* CC revs 21, 24 and 27 OTP General Use Region word offset */
-#define REVA4_OTPGU_BASE 12
-
-/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */
-#define REVB8_OTPGU_BASE 20
-
-/* CC rev 36 OTP General Use Region word offset */
-#define REV36_OTPGU_BASE 12
-
-/* Subregion word offsets in General Use region */
-#define OTPGU_HSB_OFF 0
-#define OTPGU_SFB_OFF 1
-#define OTPGU_CI_OFF 2
-#define OTPGU_P_OFF 3
-#define OTPGU_SROM_OFF 4
-
-/* Flag bit offsets in General Use region */
-#define OTPGU_HWP_OFF 60
-#define OTPGU_SWP_OFF 61
-#define OTPGU_CIP_OFF 62
-#define OTPGU_FUSEP_OFF 63
-#define OTPGU_CIP_MSK 0x4000
-#define OTPGU_P_MSK 0xf000
-#define OTPGU_P_SHIFT (OTPGU_HWP_OFF % 16)
-
-/* OTP Size */
-#define OTP_SZ_FU_324 ((roundup(324, 8))/8) /* 324 bits */
-#define OTP_SZ_FU_288 (288/8) /* 288 bits */
-#define OTP_SZ_FU_216 (216/8) /* 216 bits */
-#define OTP_SZ_FU_72 (72/8) /* 72 bits */
-#define OTP_SZ_CHECKSUM (16/8) /* 16 bits */
-#define OTP4315_SWREG_SZ 178 /* 178 bytes */
-#define OTP_SZ_FU_144 (144/8) /* 144 bits */
-
-static int ipxotp_status(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- return (int)(oi->status);
-}
-
-/* Return size in bytes */
-static int ipxotp_size(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- return (int)oi->wsize * 2;
-}
-
-static u16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn)
-{
- otpinfo_t *oi;
-
- oi = (otpinfo_t *) oh;
-
- return R_REG(&cc->sromotp[wn]);
-}
-
-static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- uint k, row, col;
- u32 otpp, st;
-
- row = off / oi->cols;
- col = off % oi->cols;
-
- otpp = OTPP_START_BUSY |
- ((OTPPOC_READ << OTPP_OC_SHIFT) & OTPP_OC_MASK) |
- ((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) |
- ((col << OTPP_COL_SHIFT) & OTPP_COL_MASK);
- W_REG(&cc->otpprog, otpp);
-
- for (k = 0;
- ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
- && (k < OTPP_TRIES); k++)
- ;
- if (k >= OTPP_TRIES) {
- return 0xffff;
- }
- if (st & OTPP_READERR) {
- return 0xffff;
- }
- st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT;
-
- return (int)st;
-}
-
-/* Calculate max HW/SW region byte size by subtracting fuse region and checksum size,
- * osizew is oi->wsize (OTP size - GU size) in words
- */
-static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
-{
- int ret = 0;
-
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
- break;
- case BCM4313_CHIP_ID:
- ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
- break;
- default:
- break; /* Don't know about this chip */
- }
-
- return ret;
-}
-
-static void _ipxotp_init(otpinfo_t *oi, chipcregs_t *cc)
-{
- uint k;
- u32 otpp, st;
-
- /* record word offset of General Use Region for various chipcommon revs */
- if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24
- || oi->sih->ccrev == 27) {
- oi->otpgu_base = REVA4_OTPGU_BASE;
- } else if (oi->sih->ccrev == 36) {
- /* OTP size greater than equal to 2KB (128 words), otpgu_base is similar to rev23 */
- if (oi->wsize >= 128)
- oi->otpgu_base = REVB8_OTPGU_BASE;
- else
- oi->otpgu_base = REV36_OTPGU_BASE;
- } else if (oi->sih->ccrev == 23 || oi->sih->ccrev >= 25) {
- oi->otpgu_base = REVB8_OTPGU_BASE;
- }
-
- /* First issue an init command so the status is up to date */
- otpp =
- OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
-
- W_REG(&cc->otpprog, otpp);
- for (k = 0;
- ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
- && (k < OTPP_TRIES); k++)
- ;
- if (k >= OTPP_TRIES) {
- return;
- }
-
- /* Read OTP lock bits and subregion programmed indication bits */
- oi->status = R_REG(&cc->otpstatus);
-
- if ((oi->sih->chip == BCM43224_CHIP_ID)
- || (oi->sih->chip == BCM43225_CHIP_ID)) {
- u32 p_bits;
- p_bits =
- (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
- OTPGU_P_MSK)
- >> OTPGU_P_SHIFT;
- oi->status |= (p_bits << OTPS_GUP_SHIFT);
- }
-
- /*
- * h/w region base and fuse region limit are fixed to the top and
- * the bottom of the general use region. Everything else can be flexible.
- */
- oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF;
- oi->hwlim = oi->wsize;
- if (oi->status & OTPS_GUP_HW) {
- oi->hwlim =
- ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_HSB_OFF) / 16;
- oi->swbase = oi->hwlim;
- } else
- oi->swbase = oi->hwbase;
-
- /* subtract fuse and checksum from beginning */
- oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2;
-
- if (oi->status & OTPS_GUP_SW) {
- oi->swlim =
- ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_SFB_OFF) / 16;
- oi->fbase = oi->swlim;
- } else
- oi->fbase = oi->swbase;
-
- oi->flim = oi->wsize;
-}
-
-static void *ipxotp_init(struct si_pub *sih)
-{
- uint idx;
- chipcregs_t *cc;
- otpinfo_t *oi;
-
- /* Make sure we're running IPX OTP */
- if (!OTPTYPE_IPX(sih->ccrev))
- return NULL;
-
- /* Make sure OTP is not disabled */
- if (ai_is_otp_disabled(sih))
- return NULL;
-
- /* Make sure OTP is powered up */
- if (!ai_is_otp_powered(sih))
- return NULL;
-
- oi = &otpinfo;
-
- /* Check for otp size */
- switch ((sih->cccaps & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
- case 0:
- /* Nothing there */
- return NULL;
- case 1: /* 32x64 */
- oi->rows = 32;
- oi->cols = 64;
- oi->wsize = 128;
- break;
- case 2: /* 64x64 */
- oi->rows = 64;
- oi->cols = 64;
- oi->wsize = 256;
- break;
- case 5: /* 96x64 */
- oi->rows = 96;
- oi->cols = 64;
- oi->wsize = 384;
- break;
- case 7: /* 16x64 *//* 1024 bits */
- oi->rows = 16;
- oi->cols = 64;
- oi->wsize = 64;
- break;
- default:
- /* Don't know the geometry */
- return NULL;
- }
-
- /* Retrieve OTP region info */
- idx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- _ipxotp_init(oi, cc);
-
- ai_setcoreidx(sih, idx);
-
- return (void *)oi;
-}
-
-static int ipxotp_read_region(void *oh, int region, u16 *data, uint *wlen)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- uint idx;
- chipcregs_t *cc;
- uint base, i, sz;
-
- /* Validate region selection */
- switch (region) {
- case OTP_HW_RGN:
- sz = (uint) oi->hwlim - oi->hwbase;
- if (!(oi->status & OTPS_GUP_HW)) {
- *wlen = sz;
- return -ENODATA;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return -EOVERFLOW;
- }
- base = oi->hwbase;
- break;
- case OTP_SW_RGN:
- sz = ((uint) oi->swlim - oi->swbase);
- if (!(oi->status & OTPS_GUP_SW)) {
- *wlen = sz;
- return -ENODATA;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return -EOVERFLOW;
- }
- base = oi->swbase;
- break;
- case OTP_CI_RGN:
- sz = OTPGU_CI_SZ;
- if (!(oi->status & OTPS_GUP_CI)) {
- *wlen = sz;
- return -ENODATA;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return -EOVERFLOW;
- }
- base = oi->otpgu_base + OTPGU_CI_OFF;
- break;
- case OTP_FUSE_RGN:
- sz = (uint) oi->flim - oi->fbase;
- if (!(oi->status & OTPS_GUP_FUSE)) {
- *wlen = sz;
- return -ENODATA;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return -EOVERFLOW;
- }
- base = oi->fbase;
- break;
- case OTP_ALL_RGN:
- sz = ((uint) oi->flim - oi->hwbase);
- if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) {
- *wlen = sz;
- return -ENODATA;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return -EOVERFLOW;
- }
- base = oi->hwbase;
- break;
- default:
- return -EINVAL;
- }
-
- idx = ai_coreidx(oi->sih);
- cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
-
- /* Read the data */
- for (i = 0; i < sz; i++)
- data[i] = ipxotp_otpr(oh, cc, base + i);
-
- ai_setcoreidx(oi->sih, idx);
- *wlen = sz;
- return 0;
-}
-
-static int ipxotp_nvread(void *oh, char *data, uint *len)
-{
- return -ENOTSUPP;
-}
-
-static otp_fn_t ipxotp_fn = {
- (otp_size_t) ipxotp_size,
- (otp_read_bit_t) ipxotp_read_bit,
-
- (otp_init_t) ipxotp_init,
- (otp_read_region_t) ipxotp_read_region,
- (otp_nvread_t) ipxotp_nvread,
-
- (otp_status_t) ipxotp_status
-};
-
-/*
- * otp_status()
- * otp_size()
- * otp_read_bit()
- * otp_init()
- * otp_read_region()
- * otp_nvread()
- */
-
-int otp_status(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
-
- return oi->fn->status(oh);
-}
-
-int otp_size(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
-
- return oi->fn->size(oh);
-}
-
-u16 otp_read_bit(void *oh, uint offset)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- uint idx = ai_coreidx(oi->sih);
- chipcregs_t *cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
- u16 readBit = (u16) oi->fn->read_bit(oh, cc, offset);
- ai_setcoreidx(oi->sih, idx);
- return readBit;
-}
-
-void *otp_init(struct si_pub *sih)
-{
- otpinfo_t *oi;
- void *ret = NULL;
-
- oi = &otpinfo;
- memset(oi, 0, sizeof(otpinfo_t));
-
- oi->ccrev = sih->ccrev;
-
- if (OTPTYPE_IPX(oi->ccrev))
- oi->fn = &ipxotp_fn;
-
- if (oi->fn == NULL) {
- return NULL;
- }
-
- oi->sih = sih;
-
- ret = (oi->fn->init) (sih);
-
- return ret;
-}
-
-int
-otp_read_region(struct si_pub *sih, int region, u16 *data,
- uint *wlen) {
- bool wasup = false;
- void *oh;
- int err = 0;
-
- wasup = ai_is_otp_powered(sih);
- if (!wasup)
- ai_otp_power(sih, true);
-
- if (!ai_is_otp_powered(sih) || ai_is_otp_disabled(sih)) {
- err = -EPERM;
- goto out;
- }
-
- oh = otp_init(sih);
- if (oh == NULL) {
- err = -EBADE;
- goto out;
- }
-
- err = (((otpinfo_t *) oh)->fn->read_region) (oh, region, data, wlen);
-
- out:
- if (!wasup)
- ai_otp_power(sih, false);
-
- return err;
-}
-
-int otp_nvread(void *oh, char *data, uint *len)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
-
- return oi->fn->nvread(oh, data, len);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_OTP_H_
-#define _BRCM_OTP_H_
-
-/* OTP regions */
-#define OTP_HW_RGN 1
-#define OTP_SW_RGN 2
-#define OTP_CI_RGN 4
-#define OTP_FUSE_RGN 8
-#define OTP_ALL_RGN 0xf /* From h/w region to end of OTP including checksum */
-
-/* OTP Size */
-#define OTP_SZ_MAX (6144/8) /* maximum bytes in one CIS */
-
-/* Fixed size subregions sizes in words */
-#define OTPGU_CI_SZ 2
-
-/* OTP usage */
-#define OTP4325_FM_DISABLED_OFFSET 188
-
-/* Exported functions */
-extern int otp_status(void *oh);
-extern int otp_size(void *oh);
-extern u16 otp_read_bit(void *oh, uint offset);
-extern void *otp_init(struct si_pub *sih);
-extern int otp_read_region(struct si_pub *sih, int region, u16 *data,
- uint *wlen);
-extern int otp_nvread(void *oh, char *data, uint *len);
-
-#endif /* _BRCM_OTP_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/etherdevice.h>
-#include <bcmdefs.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <stdarg.h>
-#include "wlc_types.h"
-#include <brcmu_utils.h>
-#include <bcmsoc.h>
-#include <chipcommon.h>
-#include <bcmdevs.h>
-#include <nicpci.h>
-#include <aiutils.h>
-#include <bcmsrom.h>
-#include <bcmotp.h>
-
-#define SROM_OFFSET(sih) ((sih->ccrev > 31) ? \
- (((sih->cccaps & CC_CAP_SROM) == 0) ? NULL : \
- ((u8 *)curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP)) : \
- ((u8 *)curmap + PCI_BAR0_SPROM_OFFSET))
-
-#if defined(BCMDBG)
-#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
-#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
-#endif
-
-/* Maximum srom: 6 Kilobits == 768 bytes */
-#define SROM_MAX 768
-
-/* PCI fields */
-#define PCI_F0DEVID 48
-
-#define SROM_WORDS 64
-
-#define SROM_SSID 2
-
-#define SROM_WL1LHMAXP 29
-
-#define SROM_WL1LPAB0 30
-#define SROM_WL1LPAB1 31
-#define SROM_WL1LPAB2 32
-
-#define SROM_WL1HPAB0 33
-#define SROM_WL1HPAB1 34
-#define SROM_WL1HPAB2 35
-
-#define SROM_MACHI_IL0 36
-#define SROM_MACMID_IL0 37
-#define SROM_MACLO_IL0 38
-#define SROM_MACHI_ET1 42
-#define SROM_MACMID_ET1 43
-#define SROM_MACLO_ET1 44
-#define SROM3_MACHI 37
-#define SROM3_MACMID 38
-#define SROM3_MACLO 39
-
-#define SROM_BXARSSI2G 40
-#define SROM_BXARSSI5G 41
-
-#define SROM_TRI52G 42
-#define SROM_TRI5GHL 43
-
-#define SROM_RXPO52G 45
-
-#define SROM_AABREV 46
-/* Fields in AABREV */
-#define SROM_BR_MASK 0x00ff
-#define SROM_CC_MASK 0x0f00
-#define SROM_CC_SHIFT 8
-#define SROM_AA0_MASK 0x3000
-#define SROM_AA0_SHIFT 12
-#define SROM_AA1_MASK 0xc000
-#define SROM_AA1_SHIFT 14
-
-#define SROM_WL0PAB0 47
-#define SROM_WL0PAB1 48
-#define SROM_WL0PAB2 49
-
-#define SROM_LEDBH10 50
-#define SROM_LEDBH32 51
-
-#define SROM_WL10MAXP 52
-
-#define SROM_WL1PAB0 53
-#define SROM_WL1PAB1 54
-#define SROM_WL1PAB2 55
-
-#define SROM_ITT 56
-
-#define SROM_BFL 57
-#define SROM_BFL2 28
-#define SROM3_BFL2 61
-
-#define SROM_AG10 58
-
-#define SROM_CCODE 59
-
-#define SROM_OPO 60
-
-#define SROM3_LEDDC 62
-
-#define SROM_CRCREV 63
-
-/* SROM Rev 4: Reallocate the software part of the srom to accommodate
- * MIMO features. It assumes up to two PCIE functions and 440 bytes
- * of usable srom i.e. the usable storage in chips with OTP that
- * implements hardware redundancy.
- */
-
-#define SROM4_WORDS 220
-
-#define SROM4_SIGN 32
-#define SROM4_SIGNATURE 0x5372
-
-#define SROM4_BREV 33
-
-#define SROM4_BFL0 34
-#define SROM4_BFL1 35
-#define SROM4_BFL2 36
-#define SROM4_BFL3 37
-#define SROM5_BFL0 37
-#define SROM5_BFL1 38
-#define SROM5_BFL2 39
-#define SROM5_BFL3 40
-
-#define SROM4_MACHI 38
-#define SROM4_MACMID 39
-#define SROM4_MACLO 40
-#define SROM5_MACHI 41
-#define SROM5_MACMID 42
-#define SROM5_MACLO 43
-
-#define SROM4_CCODE 41
-#define SROM4_REGREV 42
-#define SROM5_CCODE 34
-#define SROM5_REGREV 35
-
-#define SROM4_LEDBH10 43
-#define SROM4_LEDBH32 44
-#define SROM5_LEDBH10 59
-#define SROM5_LEDBH32 60
-
-#define SROM4_LEDDC 45
-#define SROM5_LEDDC 45
-
-#define SROM4_AA 46
-
-#define SROM4_AG10 47
-#define SROM4_AG32 48
-
-#define SROM4_TXPID2G 49
-#define SROM4_TXPID5G 51
-#define SROM4_TXPID5GL 53
-#define SROM4_TXPID5GH 55
-
-#define SROM4_TXRXC 61
-#define SROM4_TXCHAIN_MASK 0x000f
-#define SROM4_TXCHAIN_SHIFT 0
-#define SROM4_RXCHAIN_MASK 0x00f0
-#define SROM4_RXCHAIN_SHIFT 4
-#define SROM4_SWITCH_MASK 0xff00
-#define SROM4_SWITCH_SHIFT 8
-
-/* Per-path fields */
-#define MAX_PATH_SROM 4
-#define SROM4_PATH0 64
-#define SROM4_PATH1 87
-#define SROM4_PATH2 110
-#define SROM4_PATH3 133
-
-#define SROM4_2G_ITT_MAXP 0
-#define SROM4_2G_PA 1
-#define SROM4_5G_ITT_MAXP 5
-#define SROM4_5GLH_MAXP 6
-#define SROM4_5G_PA 7
-#define SROM4_5GL_PA 11
-#define SROM4_5GH_PA 15
-
-/* All the miriad power offsets */
-#define SROM4_2G_CCKPO 156
-#define SROM4_2G_OFDMPO 157
-#define SROM4_5G_OFDMPO 159
-#define SROM4_5GL_OFDMPO 161
-#define SROM4_5GH_OFDMPO 163
-#define SROM4_2G_MCSPO 165
-#define SROM4_5G_MCSPO 173
-#define SROM4_5GL_MCSPO 181
-#define SROM4_5GH_MCSPO 189
-#define SROM4_CDDPO 197
-#define SROM4_STBCPO 198
-#define SROM4_BW40PO 199
-#define SROM4_BWDUPPO 200
-
-#define SROM4_CRCREV 219
-
-/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
- * This is acombined srom for both MIMO and SISO boards, usable in
- * the .130 4Kilobit OTP with hardware redundancy.
- */
-#define SROM8_BREV 65
-
-#define SROM8_BFL0 66
-#define SROM8_BFL1 67
-#define SROM8_BFL2 68
-#define SROM8_BFL3 69
-
-#define SROM8_MACHI 70
-#define SROM8_MACMID 71
-#define SROM8_MACLO 72
-
-#define SROM8_CCODE 73
-#define SROM8_REGREV 74
-
-#define SROM8_LEDBH10 75
-#define SROM8_LEDBH32 76
-
-#define SROM8_LEDDC 77
-
-#define SROM8_AA 78
-
-#define SROM8_AG10 79
-#define SROM8_AG32 80
-
-#define SROM8_TXRXC 81
-
-#define SROM8_BXARSSI2G 82
-#define SROM8_BXARSSI5G 83
-#define SROM8_TRI52G 84
-#define SROM8_TRI5GHL 85
-#define SROM8_RXPO52G 86
-
-#define SROM8_FEM2G 87
-#define SROM8_FEM5G 88
-#define SROM8_FEM_ANTSWLUT_MASK 0xf800
-#define SROM8_FEM_ANTSWLUT_SHIFT 11
-#define SROM8_FEM_TR_ISO_MASK 0x0700
-#define SROM8_FEM_TR_ISO_SHIFT 8
-#define SROM8_FEM_PDET_RANGE_MASK 0x00f8
-#define SROM8_FEM_PDET_RANGE_SHIFT 3
-#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
-#define SROM8_FEM_EXTPA_GAIN_SHIFT 1
-#define SROM8_FEM_TSSIPOS_MASK 0x0001
-#define SROM8_FEM_TSSIPOS_SHIFT 0
-
-#define SROM8_THERMAL 89
-
-/* Temp sense related entries */
-#define SROM8_MPWR_RAWTS 90
-#define SROM8_TS_SLP_OPT_CORRX 91
-/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
-#define SROM8_FOC_HWIQ_IQSWP 92
-
-/* Temperature delta for PHY calibration */
-#define SROM8_PHYCAL_TEMPDELTA 93
-
-/* Per-path offsets & fields */
-#define SROM8_PATH0 96
-#define SROM8_PATH1 112
-#define SROM8_PATH2 128
-#define SROM8_PATH3 144
-
-#define SROM8_2G_ITT_MAXP 0
-#define SROM8_2G_PA 1
-#define SROM8_5G_ITT_MAXP 4
-#define SROM8_5GLH_MAXP 5
-#define SROM8_5G_PA 6
-#define SROM8_5GL_PA 9
-#define SROM8_5GH_PA 12
-
-/* All the miriad power offsets */
-#define SROM8_2G_CCKPO 160
-
-#define SROM8_2G_OFDMPO 161
-#define SROM8_5G_OFDMPO 163
-#define SROM8_5GL_OFDMPO 165
-#define SROM8_5GH_OFDMPO 167
-
-#define SROM8_2G_MCSPO 169
-#define SROM8_5G_MCSPO 177
-#define SROM8_5GL_MCSPO 185
-#define SROM8_5GH_MCSPO 193
-
-#define SROM8_CDDPO 201
-#define SROM8_STBCPO 202
-#define SROM8_BW40PO 203
-#define SROM8_BWDUPPO 204
-
-/* SISO PA parameters are in the path0 spaces */
-#define SROM8_SISO 96
-
-/* Legacy names for SISO PA paramters */
-#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
-#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
-#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
-#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
-#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
-#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
-#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
-#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
-#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
-#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
-#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
-#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
-#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
-#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
-#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
-
-/* SROM REV 9 */
-#define SROM9_2GPO_CCKBW20 160
-#define SROM9_2GPO_CCKBW20UL 161
-#define SROM9_2GPO_LOFDMBW20 162
-#define SROM9_2GPO_LOFDMBW20UL 164
-
-#define SROM9_5GLPO_LOFDMBW20 166
-#define SROM9_5GLPO_LOFDMBW20UL 168
-#define SROM9_5GMPO_LOFDMBW20 170
-#define SROM9_5GMPO_LOFDMBW20UL 172
-#define SROM9_5GHPO_LOFDMBW20 174
-#define SROM9_5GHPO_LOFDMBW20UL 176
-
-#define SROM9_2GPO_MCSBW20 178
-#define SROM9_2GPO_MCSBW20UL 180
-#define SROM9_2GPO_MCSBW40 182
-
-#define SROM9_5GLPO_MCSBW20 184
-#define SROM9_5GLPO_MCSBW20UL 186
-#define SROM9_5GLPO_MCSBW40 188
-#define SROM9_5GMPO_MCSBW20 190
-#define SROM9_5GMPO_MCSBW20UL 192
-#define SROM9_5GMPO_MCSBW40 194
-#define SROM9_5GHPO_MCSBW20 196
-#define SROM9_5GHPO_MCSBW20UL 198
-#define SROM9_5GHPO_MCSBW40 200
-
-#define SROM9_PO_MCS32 202
-#define SROM9_PO_LOFDM40DUP 203
-
-/* SROM flags (see sromvar_t) */
-#define SRFL_MORE 1 /* value continues as described by the next entry */
-#define SRFL_NOFFS 2 /* value bits can't be all one's */
-#define SRFL_PRHEX 4 /* value is in hexdecimal format */
-#define SRFL_PRSIGN 8 /* value is in signed decimal format */
-#define SRFL_CCODE 0x10 /* value is in country code format */
-#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
-#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
-#define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
-
-/* Max. nvram variable table size */
-#define MAXSZ_NVRAM_VARS 4096
-
-typedef struct {
- const char *name;
- u32 revmask;
- u32 flags;
- u16 off;
- u16 mask;
-} sromvar_t;
-
-typedef struct varbuf {
- char *base; /* pointer to buffer base */
- char *buf; /* pointer to current position */
- unsigned int size; /* current (residual) size in bytes */
-} varbuf_t;
-
-/* Assumptions:
- * - Ethernet address spans across 3 consective words
- *
- * Table rules:
- * - Add multiple entries next to each other if a value spans across multiple words
- * (even multiple fields in the same word) with each entry except the last having
- * it's SRFL_MORE bit set.
- * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
- * bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
- * - The last entry's name field must be NULL to indicate the end of the table. Other
- * entries must have non-NULL name.
- */
-static const sromvar_t pci_sromvars[] = {
- {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
- {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
- {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
- {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
- {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
- {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
- {"", 0, 0, SROM_BFL2, 0xffff},
- {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
- {"", 0, 0, SROM3_BFL2, 0xffff},
- {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
- {"", 0, 0, SROM4_BFL1, 0xffff},
- {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
- {"", 0, 0, SROM5_BFL1, 0xffff},
- {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
- {"", 0, 0, SROM8_BFL1, 0xffff},
- {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
- {"", 0, 0, SROM4_BFL3, 0xffff},
- {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
- {"", 0, 0, SROM5_BFL3, 0xffff},
- {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
- {"", 0, 0, SROM8_BFL3, 0xffff},
- {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
- {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
- {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
- {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
- {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
- {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
- {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
- {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
- {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
- {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
- {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
- {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
- {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
- {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
- {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
- {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
- {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
- {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
- {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
- {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
- {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
- {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
- {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
- {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
- {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
- {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
- {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
- {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
- {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
- {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
- {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
- {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
- {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
- {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
- {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
- {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
- {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
- {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
- {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
- {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
- {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
- {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
- {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
- {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
- {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
- {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
- {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
- {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
- {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
- {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
- {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
- {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
- {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
- {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
- {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
- {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
- {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
- {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
- {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
- {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
- {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
- {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
- {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
- {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
- {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
- {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
- {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
- {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
- {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
- {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
- {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
- {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
- {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
- {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
- {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
- {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
- {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
- {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
- {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
- {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
- {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
- {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
- {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
- {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
- {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
- {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
- {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
- {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
- {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
- {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
- {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
- {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
- {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
- {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
- {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
- {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
- {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
- {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
- {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
- {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
- {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
- {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
- {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
- {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
- {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
- {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
- {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
- {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
- {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
- {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
- {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
- {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
- {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
- {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
- {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
- {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
- {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
- {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
- {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
- {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
- {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
- {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
- {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
- {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
- {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
- {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
- {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
- {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
- {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
- {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
- {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
- {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
- {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
- {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
- {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
- {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
- {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
- {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
- {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
- {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
- {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
- {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
- {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
-
- {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
- {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
- {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
- {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
- {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
- {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
- {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
- {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
- {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
- {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
- {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
- {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
- {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
- {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
- {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
- {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
- {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
- 0x00ff},
- {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
- {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
- 0x0300},
- {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
- 0x000f},
- {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
- {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
- {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
-
- {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
- {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
- {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
- {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
- {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
- {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
- {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
- {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
- {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
- {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
- {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
- {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
- {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
- {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
- {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
- {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
- {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
- {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
- {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
- {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
- {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
- {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
- {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
- {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
- {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
- {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
- {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
- {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
- {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
- {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
- {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
- {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
- {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
- {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
- {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
- {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
- {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
- {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
- {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
- {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
- {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
- {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
- {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
- {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
- {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
- {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
- {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
- {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
- {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
- {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
- {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
- {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
- {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
- {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
- {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
- {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
- {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
- {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
- {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
- {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
- {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
- {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
- {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
- {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
- {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
- {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
- {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
- {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
- {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
- {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
- {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
- {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
- {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
- {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
- {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
- {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
- {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
- {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
- {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
- {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
- {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
- {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
- {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
- {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
- {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
- {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
- {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
- {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
- {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
- {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
-
- /* power per rate from sromrev 9 */
- {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
- {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
- {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
- 0xffff},
- {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
- {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
- {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
- 0xffff},
- {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
- {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
- {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
- 0xffff},
- {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
- {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
- {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
- 0xffff},
- {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
- {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
- {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
- {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
- {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
- {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
- {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
- {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
- {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
- {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
- {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
- {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
- {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
- {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
- {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
- {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
- {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
- {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
- {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
- {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
- {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
- {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
- {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
- {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
- {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
-
- {NULL, 0, 0, 0, 0}
-};
-
-static const sromvar_t perpath_pci_sromvars[] = {
- {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
- {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
- {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
- {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
- {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
- {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
- {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
- {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
- {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
- {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
- {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
- {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
- {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
- {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
- {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
- {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
- {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
- {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
- {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
- {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
- {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
- {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
- {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
- {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
- {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
- {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
- {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
- {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
- {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
- {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
- {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
- {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
- {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
- {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
- {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
- {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
- {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
- {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
- {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
- {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
- {NULL, 0, 0, 0, 0}
-};
-
-static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b);
-static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
- uint *count);
-static int sprom_read_pci(struct si_pub *sih, u16 *sprom,
- uint wordoff, u16 *buf, uint nwords, bool check_crc);
-#if defined(BCMNVRAMR)
-static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz);
-#endif
-static u16 srom_cc_cmd(struct si_pub *sih, void *ccregs, u32 cmd,
- uint wordoff, u16 data);
-
-static int initvars_table(char *start, char *end,
- char **vars, uint *count);
-
-/* Initialization of varbuf structure */
-static void varbuf_init(varbuf_t *b, char *buf, uint size)
-{
- b->size = size;
- b->base = b->buf = buf;
-}
-
-/* append a null terminated var=value string */
-static int varbuf_append(varbuf_t *b, const char *fmt, ...)
-{
- va_list ap;
- int r;
- size_t len;
- char *s;
-
- if (b->size < 2)
- return 0;
-
- va_start(ap, fmt);
- r = vsnprintf(b->buf, b->size, fmt, ap);
- va_end(ap);
-
- /* C99 snprintf behavior returns r >= size on overflow,
- * others return -1 on overflow.
- * All return -1 on format error.
- * We need to leave room for 2 null terminations, one for the current var
- * string, and one for final null of the var table. So check that the
- * strlen written, r, leaves room for 2 chars.
- */
- if ((r == -1) || (r > (int)(b->size - 2))) {
- b->size = 0;
- return 0;
- }
-
- /* Remove any earlier occurrence of the same variable */
- s = strchr(b->buf, '=');
- if (s != NULL) {
- len = (size_t) (s - b->buf);
- for (s = b->base; s < b->buf;) {
- if ((memcmp(s, b->buf, len) == 0) && s[len] == '=') {
- len = strlen(s) + 1;
- memmove(s, (s + len),
- ((b->buf + r + 1) - (s + len)));
- b->buf -= len;
- b->size += (unsigned int)len;
- break;
- }
-
- while (*s++)
- ;
- }
- }
-
- /* skip over this string's null termination */
- r++;
- b->size -= r;
- b->buf += r;
-
- return r;
-}
-
-/*
- * Initialize local vars from the right source for this platform.
- * Return 0 on success, nonzero on error.
- */
-int srom_var_init(struct si_pub *sih, uint bustype, void *curmap,
- char **vars, uint *count)
-{
- uint len;
-
- len = 0;
-
- if (vars == NULL || count == NULL)
- return 0;
-
- *vars = NULL;
- *count = 0;
-
- if (curmap != NULL && bustype == PCI_BUS)
- return initvars_srom_pci(sih, curmap, vars, count);
-
- return -1;
-}
-
-/* In chips with chipcommon rev 32 and later, the srom is in chipcommon,
- * not in the bus cores.
- */
-static u16
-srom_cc_cmd(struct si_pub *sih, void *ccregs, u32 cmd,
- uint wordoff, u16 data)
-{
- chipcregs_t *cc = (chipcregs_t *) ccregs;
- uint wait_cnt = 1000;
-
- if ((cmd == SRC_OP_READ) || (cmd == SRC_OP_WRITE)) {
- W_REG(&cc->sromaddress, wordoff * 2);
- if (cmd == SRC_OP_WRITE)
- W_REG(&cc->sromdata, data);
- }
-
- W_REG(&cc->sromcontrol, SRC_START | cmd);
-
- while (wait_cnt--) {
- if ((R_REG(&cc->sromcontrol) & SRC_BUSY) == 0)
- break;
- }
-
- if (!wait_cnt) {
- return 0xffff;
- }
- if (cmd == SRC_OP_READ)
- return (u16) R_REG(&cc->sromdata);
- else
- return 0xffff;
-}
-
-static inline void ltoh16_buf(u16 *buf, unsigned int size)
-{
- for (size /= 2; size; size--)
- *(buf + size) = le16_to_cpu(*(buf + size));
-}
-
-static inline void htol16_buf(u16 *buf, unsigned int size)
-{
- for (size /= 2; size; size--)
- *(buf + size) = cpu_to_le16(*(buf + size));
-}
-
-/*
- * Read in and validate sprom.
- * Return 0 on success, nonzero on error.
- */
-static int
-sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
- u16 *buf, uint nwords, bool check_crc)
-{
- int err = 0;
- uint i;
- void *ccregs = NULL;
-
- /* read the sprom */
- for (i = 0; i < nwords; i++) {
-
- if (sih->ccrev > 31 && ISSIM_ENAB(sih)) {
- /* use indirect since direct is too slow on QT */
- if ((sih->cccaps & CC_CAP_SROM) == 0)
- return 1;
-
- ccregs = (void *)((u8 *) sprom - CC_SROM_OTP);
- buf[i] =
- srom_cc_cmd(sih, ccregs, SRC_OP_READ,
- wordoff + i, 0);
-
- } else {
- if (ISSIM_ENAB(sih))
- buf[i] = R_REG(&sprom[wordoff + i]);
-
- buf[i] = R_REG(&sprom[wordoff + i]);
- }
-
- }
-
- /* bypass crc checking for simulation to allow srom hack */
- if (ISSIM_ENAB(sih))
- return err;
-
- if (check_crc) {
-
- if (buf[0] == 0xffff) {
- /* The hardware thinks that an srom that starts with 0xffff
- * is blank, regardless of the rest of the content, so declare
- * it bad.
- */
- return 1;
- }
-
- /* fixup the endianness so crc8 will pass */
- htol16_buf(buf, nwords * 2);
- if (brcmu_crc8((u8 *) buf, nwords * 2, CRC8_INIT_VALUE) !=
- CRC8_GOOD_VALUE) {
- /* DBG only pci always read srom4 first, then srom8/9 */
- err = 1;
- }
- /* now correct the endianness of the byte array */
- ltoh16_buf(buf, nwords * 2);
- }
- return err;
-}
-
-#if defined(BCMNVRAMR)
-static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
-{
- u8 *otp;
- uint sz = OTP_SZ_MAX / 2; /* size in words */
- int err = 0;
-
- otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
- if (otp == NULL) {
- return -EBADE;
- }
-
- err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
-
- memcpy(buf, otp, bufsz);
-
- kfree(otp);
-
- /* Check CRC */
- if (buf[0] == 0xffff) {
- /* The hardware thinks that an srom that starts with 0xffff
- * is blank, regardless of the rest of the content, so declare
- * it bad.
- */
- return 1;
- }
-
- /* fixup the endianness so crc8 will pass */
- htol16_buf(buf, bufsz);
- if (brcmu_crc8((u8 *) buf, SROM4_WORDS * 2, CRC8_INIT_VALUE) !=
- CRC8_GOOD_VALUE) {
- err = 1;
- }
- /* now correct the endianness of the byte array */
- ltoh16_buf(buf, bufsz);
-
- return err;
-}
-#endif /* defined(BCMNVRAMR) */
-/*
-* Create variable table from memory.
-* Return 0 on success, nonzero on error.
-*/
-static int initvars_table(char *start, char *end,
- char **vars, uint *count)
-{
- int c = (int)(end - start);
-
- /* do it only when there is more than just the null string */
- if (c > 1) {
- char *vp = kmalloc(c, GFP_ATOMIC);
- if (!vp)
- return -ENOMEM;
- memcpy(vp, start, c);
- *vars = vp;
- *count = c;
- } else {
- *vars = NULL;
- *count = 0;
- }
-
- return 0;
-}
-
-/* Parse SROM and create name=value pairs. 'srom' points to
- * the SROM word array. 'off' specifies the offset of the
- * first word 'srom' points to, which should be either 0 or
- * SROM3_SWRG_OFF (full SROM or software region).
- */
-
-static uint mask_shift(u16 mask)
-{
- uint i;
- for (i = 0; i < (sizeof(mask) << 3); i++) {
- if (mask & (1 << i))
- return i;
- }
- return 0;
-}
-
-static uint mask_width(u16 mask)
-{
- int i;
- for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
- if (mask & (1 << i))
- return (uint) (i - mask_shift(mask) + 1);
- }
- return 0;
-}
-
-static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b)
-{
- u16 w;
- u32 val;
- const sromvar_t *srv;
- uint width;
- uint flags;
- u32 sr = (1 << sromrev);
-
- varbuf_append(b, "sromrev=%d", sromrev);
-
- for (srv = pci_sromvars; srv->name != NULL; srv++) {
- const char *name;
-
- if ((srv->revmask & sr) == 0)
- continue;
-
- if (srv->off < off)
- continue;
-
- flags = srv->flags;
- name = srv->name;
-
- /* This entry is for mfgc only. Don't generate param for it, */
- if (flags & SRFL_NOVAR)
- continue;
-
- if (flags & SRFL_ETHADDR) {
- u8 ea[ETH_ALEN];
-
- ea[0] = (srom[srv->off - off] >> 8) & 0xff;
- ea[1] = srom[srv->off - off] & 0xff;
- ea[2] = (srom[srv->off + 1 - off] >> 8) & 0xff;
- ea[3] = srom[srv->off + 1 - off] & 0xff;
- ea[4] = (srom[srv->off + 2 - off] >> 8) & 0xff;
- ea[5] = srom[srv->off + 2 - off] & 0xff;
-
- varbuf_append(b, "%s=%pM", name, ea);
- } else {
- w = srom[srv->off - off];
- val = (w & srv->mask) >> mask_shift(srv->mask);
- width = mask_width(srv->mask);
-
- while (srv->flags & SRFL_MORE) {
- srv++;
- if (srv->off == 0 || srv->off < off)
- continue;
-
- w = srom[srv->off - off];
- val +=
- ((w & srv->mask) >> mask_shift(srv->
- mask)) <<
- width;
- width += mask_width(srv->mask);
- }
-
- if ((flags & SRFL_NOFFS)
- && ((int)val == (1 << width) - 1))
- continue;
-
- if (flags & SRFL_CCODE) {
- if (val == 0)
- varbuf_append(b, "ccode=");
- else
- varbuf_append(b, "ccode=%c%c",
- (val >> 8), (val & 0xff));
- }
- /* LED Powersave duty cycle has to be scaled:
- *(oncount >> 24) (offcount >> 8)
- */
- else if (flags & SRFL_LEDDC) {
- u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
- (((val & 0xff)) << 8); /* offcount */
- varbuf_append(b, "leddc=%d", w32);
- } else if (flags & SRFL_PRHEX)
- varbuf_append(b, "%s=0x%x", name, val);
- else if ((flags & SRFL_PRSIGN)
- && (val & (1 << (width - 1))))
- varbuf_append(b, "%s=%d", name,
- (int)(val | (~0 << width)));
- else
- varbuf_append(b, "%s=%u", name, val);
- }
- }
-
- if (sromrev >= 4) {
- /* Do per-path variables */
- uint p, pb, psz;
-
- if (sromrev >= 8) {
- pb = SROM8_PATH0;
- psz = SROM8_PATH1 - SROM8_PATH0;
- } else {
- pb = SROM4_PATH0;
- psz = SROM4_PATH1 - SROM4_PATH0;
- }
-
- for (p = 0; p < MAX_PATH_SROM; p++) {
- for (srv = perpath_pci_sromvars; srv->name != NULL;
- srv++) {
- if ((srv->revmask & sr) == 0)
- continue;
-
- if (pb + srv->off < off)
- continue;
-
- /* This entry is for mfgc only. Don't generate param for it, */
- if (srv->flags & SRFL_NOVAR)
- continue;
-
- w = srom[pb + srv->off - off];
- val = (w & srv->mask) >> mask_shift(srv->mask);
- width = mask_width(srv->mask);
-
- /* Cheating: no per-path var is more than 1 word */
-
- if ((srv->flags & SRFL_NOFFS)
- && ((int)val == (1 << width) - 1))
- continue;
-
- if (srv->flags & SRFL_PRHEX)
- varbuf_append(b, "%s%d=0x%x", srv->name,
- p, val);
- else
- varbuf_append(b, "%s%d=%d", srv->name,
- p, val);
- }
- pb += psz;
- }
- }
-}
-
-/*
- * Initialize nonvolatile variable table from sprom.
- * Return 0 on success, nonzero on error.
- */
-static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
- uint *count)
-{
- u16 *srom, *sromwindow;
- u8 sromrev = 0;
- u32 sr;
- varbuf_t b;
- char *vp, *base = NULL;
- bool flash = false;
- int err = 0;
-
- /*
- * Apply CRC over SROM content regardless SROM is present or not,
- * and use variable <devpath>sromrev's existence in flash to decide
- * if we should return an error when CRC fails or read SROM variables
- * from flash.
- */
- srom = kmalloc(SROM_MAX, GFP_ATOMIC);
- if (!srom)
- return -2;
-
- sromwindow = (u16 *) SROM_OFFSET(sih);
- if (ai_is_sprom_available(sih)) {
- err =
- sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
- true);
-
- if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
- (((sih->buscoretype == PCIE_CORE_ID)
- && (sih->buscorerev >= 6))
- || ((sih->buscoretype == PCI_CORE_ID)
- && (sih->buscorerev >= 0xe)))) {
- /* sromrev >= 4, read more */
- err =
- sprom_read_pci(sih, sromwindow, 0, srom,
- SROM4_WORDS, true);
- sromrev = srom[SROM4_CRCREV] & 0xff;
- } else if (err == 0) {
- /* srom is good and is rev < 4 */
- /* top word of sprom contains version and crc8 */
- sromrev = srom[SROM_CRCREV] & 0xff;
- /* bcm4401 sroms misprogrammed */
- if (sromrev == 0x10)
- sromrev = 1;
- }
- }
-#if defined(BCMNVRAMR)
- /* Use OTP if SPROM not available */
- else {
- err = otp_read_pci(sih, srom, SROM_MAX);
- if (err == 0)
- /* OTP only contain SROM rev8/rev9 for now */
- sromrev = srom[SROM4_CRCREV] & 0xff;
- else
- err = 1;
- }
-#else
- else
- err = 1;
-#endif
-
- /*
- * We want internal/wltest driver to come up with default
- * sromvars so we can program a blank SPROM/OTP.
- */
- if (err) {
- char *value;
- u32 val;
- val = 0;
-
- value = ai_getdevpathvar(sih, "sromrev");
- if (value) {
- sromrev = (u8) simple_strtoul(value, NULL, 0);
- flash = true;
- goto varscont;
- }
-
- value = ai_getnvramflvar(sih, "sromrev");
- if (value) {
- err = 0;
- goto errout;
- }
-
- {
- err = -1;
- goto errout;
- }
- }
-
- varscont:
- /* Bitmask for the sromrev */
- sr = 1 << sromrev;
-
- /* srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 9 */
- if ((sr & 0x33e) == 0) {
- err = -2;
- goto errout;
- }
-
- base = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
- if (!base) {
- err = -2;
- goto errout;
- }
-
- varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
-
- /* parse SROM into name=value pairs. */
- _initvars_srom_pci(sromrev, srom, 0, &b);
-
- /* final nullbyte terminator */
- vp = b.buf;
- *vp++ = '\0';
-
- err = initvars_table(base, vp, vars, count);
-
- errout:
- if (base)
- kfree(base);
-
- kfree(srom);
- return err;
-}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+
+#include <defs.h>
+#include <brcm_hw_ids.h>
+#include <brcmu_wifi.h>
+#include <aiutils.h>
+#include <srom.h>
+#include "otp.h"
+#include <brcmu_utils.h>
+#include <chipcommon.h>
+#include <nicpci.h>
+#include "dma.h"
+
+#include "types.h"
+#include "pmu.h"
+#include "d11.h"
+#include "cfg.h"
+#include "rate.h"
+#include "scb.h"
+#include "pub.h"
+#include "key.h"
+#include "phy/phy_hal.h"
+#include "channel.h"
+#include "main.h"
+#include "ucode_loader.h"
+#include "antsel.h"
+#include "alloc.h"
+#include "bottom_mac.h"
+#include "mac80211_if.h"
+
+#define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
+
+#define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
+#define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
+#define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
+#define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
+
+#define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
+
+#ifndef BMAC_DUP_TO_REMOVE
+#define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
+
+#define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
+
+#endif /* BMAC_DUP_TO_REMOVE */
+
+#define DMAREG(wlc_hw, direction, fifonum) \
+ ((direction == DMA_TX) ? \
+ (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
+ (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
+
+#define APHY_SLOT_TIME 9
+#define BPHY_SLOT_TIME 20
+
+/*
+ * The following table lists the buffer memory allocated to xmt fifos in HW.
+ * the size is in units of 256bytes(one block), total size is HW dependent
+ * ucode has default fifo partition, sw can overwrite if necessary
+ *
+ * This is documented in twiki under the topic UcodeTxFifo. Please ensure
+ * the twiki is updated before making changes.
+ */
+
+#define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
+
+static u16 xmtfifo_sz[][NFIFO] = {
+ {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
+ {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
+ {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
+ {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
+ {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
+};
+
+static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
+static void wlc_coreinit(struct wlc_info *wlc);
+
+/* used by wlc_wakeucode_init() */
+static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
+ const struct d11init *inits);
+static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
+ const uint nbytes);
+static void wlc_ucode_download(struct wlc_hw_info *wlc);
+static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
+
+/* used by wlc_dpc() */
+static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
+ u32 s2);
+static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
+static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
+
+/* used by wlc_down() */
+static void wlc_flushqueues(struct wlc_info *wlc);
+
+static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
+static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
+static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
+static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
+ uint tx_fifo);
+static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
+static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
+
+/* Low Level Prototypes */
+static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
+static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
+static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
+static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
+ u32 sel);
+static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
+ u16 v, u32 sel);
+static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
+static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
+static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
+static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
+static bool wlc_validboardtype(struct wlc_hw_info *wlc);
+static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
+static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
+static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
+static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
+static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
+static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
+static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
+static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
+static u32 wlc_wlintrsoff(struct wlc_info *wlc);
+static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
+static void wlc_gpio_init(struct wlc_info *wlc);
+static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
+ int len);
+static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
+ int len);
+static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
+static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
+static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
+ chanspec_t chanspec);
+static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
+ bool shortslot);
+static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
+static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
+ u8 rate);
+
+/* === Low Level functions === */
+
+void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
+{
+ wlc_hw->shortslot = shortslot;
+
+ if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
+ wlc_suspend_mac_and_wait(wlc_hw->wlc);
+ wlc_bmac_update_slot_timing(wlc_hw, shortslot);
+ wlc_enable_mac(wlc_hw->wlc);
+ }
+}
+
+/*
+ * Update the slot timing for standard 11b/g (20us slots)
+ * or shortslot 11g (9us slots)
+ * The PSM needs to be suspended for this call.
+ */
+static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
+ bool shortslot)
+{
+ d11regs_t *regs;
+
+ regs = wlc_hw->regs;
+
+ if (shortslot) {
+ /* 11g short slot: 11a timing */
+ W_REG(®s->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
+ wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
+ } else {
+ /* 11g long slot: 11b timing */
+ W_REG(®s->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
+ wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
+ }
+}
+
+static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
+{
+ struct wiphy *wiphy = wlc_hw->wlc->wiphy;
+
+ /* init microcode host flags */
+ wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
+
+ /* do band-specific ucode IHR, SHM, and SCR inits */
+ if (D11REV_IS(wlc_hw->corerev, 23)) {
+ if (WLCISNPHY(wlc_hw->band)) {
+ wlc_write_inits(wlc_hw, d11n0bsinitvals16);
+ } else {
+ wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
+ " %d\n", __func__, wlc_hw->unit,
+ wlc_hw->corerev);
+ }
+ } else {
+ if (D11REV_IS(wlc_hw->corerev, 24)) {
+ if (WLCISLCNPHY(wlc_hw->band)) {
+ wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
+ } else
+ wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
+ " core rev %d\n", __func__,
+ wlc_hw->unit, wlc_hw->corerev);
+ } else {
+ wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
+ __func__, wlc_hw->unit, wlc_hw->corerev);
+ }
+ }
+}
+
+/* switch to new band but leave it inactive */
+static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ u32 macintmask;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
+
+ /* disable interrupts */
+ macintmask = brcms_intrsoff(wlc->wl);
+
+ /* radio off */
+ wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
+
+ wlc_bmac_core_phy_clk(wlc_hw, OFF);
+
+ wlc_setxband(wlc_hw, bandunit);
+
+ return macintmask;
+}
+
+/* Process received frames */
+/*
+ * Return true if more frames need to be processed. false otherwise.
+ * Param 'bound' indicates max. # frames to process before break out.
+ */
+static bool
+wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
+{
+ struct sk_buff *p;
+ struct sk_buff *head = NULL;
+ struct sk_buff *tail = NULL;
+ uint n = 0;
+ uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
+ wlc_d11rxhdr_t *wlc_rxhdr = NULL;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+ /* gather received frames */
+ while ((p = dma_rx(wlc_hw->di[fifo]))) {
+
+ if (!tail)
+ head = tail = p;
+ else {
+ tail->prev = p;
+ tail = p;
+ }
+
+ /* !give others some time to run! */
+ if (++n >= bound_limit)
+ break;
+ }
+
+ /* post more rbufs */
+ dma_rxfill(wlc_hw->di[fifo]);
+
+ /* process each frame */
+ while ((p = head) != NULL) {
+ head = head->prev;
+ p->prev = NULL;
+
+ wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
+
+ /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
+ wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
+
+ wlc_recv(wlc_hw->wlc, p);
+ }
+
+ return n >= bound_limit;
+}
+
+/* second-level interrupt processing
+ * Return true if another dpc needs to be re-scheduled. false otherwise.
+ * Param 'bounded' indicates if applicable loops should be bounded.
+ */
+bool wlc_dpc(struct wlc_info *wlc, bool bounded)
+{
+ u32 macintstatus;
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ d11regs_t *regs = wlc_hw->regs;
+ bool fatal = false;
+ struct wiphy *wiphy = wlc->wiphy;
+
+ if (DEVICEREMOVED(wlc)) {
+ wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
+ __func__);
+ brcms_down(wlc->wl);
+ return false;
+ }
+
+ /* grab and clear the saved software intstatus bits */
+ macintstatus = wlc->macintstatus;
+ wlc->macintstatus = 0;
+
+ BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
+ wlc_hw->unit, macintstatus);
+
+ WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
+
+ /* BCN template is available */
+ /* ZZZ: Use AP_ACTIVE ? */
+ if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
+ && (macintstatus & MI_BCNTPL)) {
+ wlc_update_beacon(wlc);
+ }
+
+ /* PMQ entry addition */
+ if (macintstatus & MI_PMQ) {
+ }
+
+ /* tx status */
+ if (macintstatus & MI_TFS) {
+ if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
+ wlc->macintstatus |= MI_TFS;
+ if (fatal) {
+ wiphy_err(wiphy, "MI_TFS: fatal\n");
+ goto fatal;
+ }
+ }
+
+ if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
+ wlc_tbtt(wlc, regs);
+
+ /* ATIM window end */
+ if (macintstatus & MI_ATIMWINEND) {
+ BCMMSG(wlc->wiphy, "end of ATIM window\n");
+ OR_REG(®s->maccommand, wlc->qvalid);
+ wlc->qvalid = 0;
+ }
+
+ /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
+ if (macintstatus & MI_DMAINT) {
+ if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
+ wlc->macintstatus |= MI_DMAINT;
+ }
+ }
+
+ /* TX FIFO suspend/flush completion */
+ if (macintstatus & MI_TXSTOP) {
+ if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
+ /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
+ }
+ }
+
+ /* noise sample collected */
+ if (macintstatus & MI_BG_NOISE) {
+ wlc_phy_noise_sample_intr(wlc_hw->band->pi);
+ }
+
+ if (macintstatus & MI_GP0) {
+ wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
+ "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
+
+ printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
+ __func__, wlc_hw->sih->chip,
+ wlc_hw->sih->chiprev);
+ /* big hammer */
+ brcms_init(wlc->wl);
+ }
+
+ /* gptimer timeout */
+ if (macintstatus & MI_TO) {
+ W_REG(®s->gptimer, 0);
+ }
+
+ if (macintstatus & MI_RFDISABLE) {
+ BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
+ " RF Disable Input\n", wlc_hw->unit);
+ brcms_rfkill_set_hw_state(wlc->wl);
+ }
+
+ /* send any enq'd tx packets. Just makes sure to jump start tx */
+ if (!pktq_empty(&wlc->pkt_queue->q))
+ wlc_send_q(wlc);
+
+ /* it isn't done and needs to be resched if macintstatus is non-zero */
+ return wlc->macintstatus != 0;
+
+ fatal:
+ brcms_init(wlc->wl);
+ return wlc->macintstatus != 0;
+}
+
+/* common low-level watchdog code */
+void wlc_bmac_watchdog(void *arg)
+{
+ struct wlc_info *wlc = (struct wlc_info *) arg;
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ if (!wlc_hw->up)
+ return;
+
+ /* increment second count */
+ wlc_hw->now++;
+
+ /* Check for FIFO error interrupts */
+ wlc_bmac_fifoerrors(wlc_hw);
+
+ /* make sure RX dma has buffers */
+ dma_rxfill(wlc->hw->di[RX_FIFO]);
+
+ wlc_phy_watchdog(wlc_hw->band->pi);
+}
+
+void
+wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
+ bool mute, struct txpwr_limits *txpwr)
+{
+ uint bandunit;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
+
+ wlc_hw->chanspec = chanspec;
+
+ /* Switch bands if necessary */
+ if (NBANDS_HW(wlc_hw) > 1) {
+ bandunit = CHSPEC_WLCBANDUNIT(chanspec);
+ if (wlc_hw->band->bandunit != bandunit) {
+ /* wlc_bmac_setband disables other bandunit,
+ * use light band switch if not up yet
+ */
+ if (wlc_hw->up) {
+ wlc_phy_chanspec_radio_set(wlc_hw->
+ bandstate[bandunit]->
+ pi, chanspec);
+ wlc_bmac_setband(wlc_hw, bandunit, chanspec);
+ } else {
+ wlc_setxband(wlc_hw, bandunit);
+ }
+ }
+ }
+
+ wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
+
+ if (!wlc_hw->up) {
+ if (wlc_hw->clk)
+ wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
+ chanspec);
+ wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
+ } else {
+ wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
+ wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
+
+ /* Update muting of the channel */
+ wlc_bmac_mute(wlc_hw, mute, 0);
+ }
+}
+
+int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
+{
+ state->machwcap = wlc_hw->machwcap;
+
+ return 0;
+}
+
+static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
+{
+ uint i;
+ char name[8];
+ /* ucode host flag 2 needed for pio mode, independent of band and fifo */
+ u16 pio_mhf2 = 0;
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ uint unit = wlc_hw->unit;
+ wlc_tunables_t *tune = wlc->pub->tunables;
+ struct wiphy *wiphy = wlc->wiphy;
+
+ /* name and offsets for dma_attach */
+ snprintf(name, sizeof(name), "wl%d", unit);
+
+ if (wlc_hw->di[0] == 0) { /* Init FIFOs */
+ uint addrwidth;
+ int dma_attach_err = 0;
+ /* Find out the DMA addressing capability and let OS know
+ * All the channels within one DMA core have 'common-minimum' same
+ * capability
+ */
+ addrwidth =
+ dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
+
+ if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
+ wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
+ "resources failed\n", unit);
+ return false;
+ }
+
+ /*
+ * FIFO 0
+ * TX: TX_AC_BK_FIFO (TX AC Background data packets)
+ * RX: RX_FIFO (RX data packets)
+ */
+ wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
+ (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
+ NULL), DMAREG(wlc_hw, DMA_RX, 0),
+ (wme ? tune->ntxd : 0), tune->nrxd,
+ tune->rxbufsz, -1, tune->nrxbufpost,
+ WL_HWRXOFF, &brcm_msg_level);
+ dma_attach_err |= (NULL == wlc_hw->di[0]);
+
+ /*
+ * FIFO 1
+ * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
+ * (legacy) TX_DATA_FIFO (TX data packets)
+ * RX: UNUSED
+ */
+ wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
+ DMAREG(wlc_hw, DMA_TX, 1), NULL,
+ tune->ntxd, 0, 0, -1, 0, 0,
+ &brcm_msg_level);
+ dma_attach_err |= (NULL == wlc_hw->di[1]);
+
+ /*
+ * FIFO 2
+ * TX: TX_AC_VI_FIFO (TX AC Video data packets)
+ * RX: UNUSED
+ */
+ wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
+ DMAREG(wlc_hw, DMA_TX, 2), NULL,
+ tune->ntxd, 0, 0, -1, 0, 0,
+ &brcm_msg_level);
+ dma_attach_err |= (NULL == wlc_hw->di[2]);
+ /*
+ * FIFO 3
+ * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
+ * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
+ */
+ wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
+ DMAREG(wlc_hw, DMA_TX, 3),
+ NULL, tune->ntxd, 0, 0, -1,
+ 0, 0, &brcm_msg_level);
+ dma_attach_err |= (NULL == wlc_hw->di[3]);
+/* Cleaner to leave this as if with AP defined */
+
+ if (dma_attach_err) {
+ wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
+ "\n", unit);
+ return false;
+ }
+
+ /* get pointer to dma engine tx flow control variable */
+ for (i = 0; i < NFIFO; i++)
+ if (wlc_hw->di[i])
+ wlc_hw->txavail[i] =
+ (uint *) dma_getvar(wlc_hw->di[i],
+ "&txavail");
+ }
+
+ /* initial ucode host flags */
+ wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
+
+ return true;
+}
+
+static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
+{
+ uint j;
+
+ for (j = 0; j < NFIFO; j++) {
+ if (wlc_hw->di[j]) {
+ dma_detach(wlc_hw->di[j]);
+ wlc_hw->di[j] = NULL;
+ }
+ }
+}
+
+/* low level attach
+ * run backplane attach, init nvram
+ * run phy attach
+ * initialize software state for each core and band
+ * put the whole chip in reset(driver down state), no clock
+ */
+int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
+ bool piomode, void *regsva, uint bustype, void *btparam)
+{
+ struct wlc_hw_info *wlc_hw;
+ d11regs_t *regs;
+ char *macaddr = NULL;
+ char *vars;
+ uint err = 0;
+ uint j;
+ bool wme = false;
+ shared_phy_params_t sha_params;
+ struct wiphy *wiphy = wlc->wiphy;
+
+ BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
+ device);
+
+ wme = true;
+
+ wlc_hw = wlc->hw;
+ wlc_hw->wlc = wlc;
+ wlc_hw->unit = unit;
+ wlc_hw->band = wlc_hw->bandstate[0];
+ wlc_hw->_piomode = piomode;
+
+ /* populate struct wlc_hw_info with default values */
+ wlc_bmac_info_init(wlc_hw);
+
+ /*
+ * Do the hardware portion of the attach.
+ * Also initialize software state that depends on the particular hardware
+ * we are running.
+ */
+ wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
+ &wlc_hw->vars, &wlc_hw->vars_size);
+ if (wlc_hw->sih == NULL) {
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
+ unit);
+ err = 11;
+ goto fail;
+ }
+ vars = wlc_hw->vars;
+
+ /*
+ * Get vendid/devid nvram overwrites, which could be different
+ * than those the BIOS recognizes for devices on PCMCIA_BUS,
+ * SDIO_BUS, and SROMless devices on PCI_BUS.
+ */
+#ifdef BCMBUSTYPE
+ bustype = BCMBUSTYPE;
+#endif
+ if (bustype != SI_BUS) {
+ char *var;
+
+ var = getvar(vars, "vendid");
+ if (var) {
+ vendor = (u16) simple_strtoul(var, NULL, 0);
+ wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
+ vendor);
+ }
+ var = getvar(vars, "devid");
+ if (var) {
+ u16 devid = (u16) simple_strtoul(var, NULL, 0);
+ if (devid != 0xffff) {
+ device = devid;
+ wiphy_err(wiphy, "Overriding device id = 0x%x"
+ "\n", device);
+ }
+ }
+
+ /* verify again the device is supported */
+ if (!wlc_chipmatch(vendor, device)) {
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
+ "vendor/device (0x%x/0x%x)\n",
+ unit, vendor, device);
+ err = 12;
+ goto fail;
+ }
+ }
+
+ wlc_hw->vendorid = vendor;
+ wlc_hw->deviceid = device;
+
+ /* set bar0 window to point at D11 core */
+ wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
+ wlc_hw->corerev = ai_corerev(wlc_hw->sih);
+
+ regs = wlc_hw->regs;
+
+ wlc->regs = wlc_hw->regs;
+
+ /* validate chip, chiprev and corerev */
+ if (!wlc_isgoodchip(wlc_hw)) {
+ err = 13;
+ goto fail;
+ }
+
+ /* initialize power control registers */
+ ai_clkctl_init(wlc_hw->sih);
+
+ /* request fastclock and force fastclock for the rest of attach
+ * bring the d11 core out of reset.
+ * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
+ * But it will be called again inside wlc_corereset, after d11 is out of reset.
+ */
+ wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
+
+ if (!wlc_bmac_validate_chip_access(wlc_hw)) {
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
+ "failed\n", unit);
+ err = 14;
+ goto fail;
+ }
+
+ /* get the board rev, used just below */
+ j = getintvar(vars, "boardrev");
+ /* promote srom boardrev of 0xFF to 1 */
+ if (j == BOARDREV_PROMOTABLE)
+ j = BOARDREV_PROMOTED;
+ wlc_hw->boardrev = (u16) j;
+ if (!wlc_validboardtype(wlc_hw)) {
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
+ "board type (0x%x)" " or revision level (0x%x)\n",
+ unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
+ err = 15;
+ goto fail;
+ }
+ wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
+ wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
+ wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
+
+ if (wlc_hw->boardflags & BFL_NOPLLDOWN)
+ wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
+
+ if ((wlc_hw->sih->bustype == PCI_BUS)
+ && (ai_pci_war16165(wlc_hw->sih)))
+ wlc->war16165 = true;
+
+ /* check device id(srom, nvram etc.) to set bands */
+ if (wlc_hw->deviceid == BCM43224_D11N_ID ||
+ wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
+ /* Dualband boards */
+ wlc_hw->_nbands = 2;
+ } else
+ wlc_hw->_nbands = 1;
+
+ if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
+ wlc_hw->_nbands = 1;
+
+ /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
+ * init of these values
+ */
+ wlc->vendorid = wlc_hw->vendorid;
+ wlc->deviceid = wlc_hw->deviceid;
+ wlc->pub->sih = wlc_hw->sih;
+ wlc->pub->corerev = wlc_hw->corerev;
+ wlc->pub->sromrev = wlc_hw->sromrev;
+ wlc->pub->boardrev = wlc_hw->boardrev;
+ wlc->pub->boardflags = wlc_hw->boardflags;
+ wlc->pub->boardflags2 = wlc_hw->boardflags2;
+ wlc->pub->_nbands = wlc_hw->_nbands;
+
+ wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
+
+ if (wlc_hw->physhim == NULL) {
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
+ "failed\n", unit);
+ err = 25;
+ goto fail;
+ }
+
+ /* pass all the parameters to wlc_phy_shared_attach in one struct */
+ sha_params.sih = wlc_hw->sih;
+ sha_params.physhim = wlc_hw->physhim;
+ sha_params.unit = unit;
+ sha_params.corerev = wlc_hw->corerev;
+ sha_params.vars = vars;
+ sha_params.vid = wlc_hw->vendorid;
+ sha_params.did = wlc_hw->deviceid;
+ sha_params.chip = wlc_hw->sih->chip;
+ sha_params.chiprev = wlc_hw->sih->chiprev;
+ sha_params.chippkg = wlc_hw->sih->chippkg;
+ sha_params.sromrev = wlc_hw->sromrev;
+ sha_params.boardtype = wlc_hw->sih->boardtype;
+ sha_params.boardrev = wlc_hw->boardrev;
+ sha_params.boardvendor = wlc_hw->sih->boardvendor;
+ sha_params.boardflags = wlc_hw->boardflags;
+ sha_params.boardflags2 = wlc_hw->boardflags2;
+ sha_params.bustype = wlc_hw->sih->bustype;
+ sha_params.buscorerev = wlc_hw->sih->buscorerev;
+
+ /* alloc and save pointer to shared phy state area */
+ wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
+ if (!wlc_hw->phy_sh) {
+ err = 16;
+ goto fail;
+ }
+
+ /* initialize software state for each core and band */
+ for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
+ /*
+ * band0 is always 2.4Ghz
+ * band1, if present, is 5Ghz
+ */
+
+ /* So if this is a single band 11a card, use band 1 */
+ if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
+ j = BAND_5G_INDEX;
+
+ wlc_setxband(wlc_hw, j);
+
+ wlc_hw->band->bandunit = j;
+ wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
+ wlc->band->bandunit = j;
+ wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
+ wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
+
+ wlc_hw->machwcap = R_REG(®s->machwcap);
+ wlc_hw->machwcap_backup = wlc_hw->machwcap;
+
+ /* init tx fifo size */
+ wlc_hw->xmtfifo_sz =
+ xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
+
+ /* Get a phy for this band */
+ wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
+ (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
+ wlc->wiphy);
+ if (wlc_hw->band->pi == NULL) {
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
+ "attach failed\n", unit);
+ err = 17;
+ goto fail;
+ }
+
+ wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
+
+ wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
+ &wlc_hw->band->phyrev,
+ &wlc_hw->band->radioid,
+ &wlc_hw->band->radiorev);
+ wlc_hw->band->abgphy_encore =
+ wlc_phy_get_encore(wlc_hw->band->pi);
+ wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
+ wlc_hw->band->core_flags =
+ wlc_phy_get_coreflags(wlc_hw->band->pi);
+
+ /* verify good phy_type & supported phy revision */
+ if (WLCISNPHY(wlc_hw->band)) {
+ if (NCONF_HAS(wlc_hw->band->phyrev))
+ goto good_phy;
+ else
+ goto bad_phy;
+ } else if (WLCISLCNPHY(wlc_hw->band)) {
+ if (LCNCONF_HAS(wlc_hw->band->phyrev))
+ goto good_phy;
+ else
+ goto bad_phy;
+ } else {
+ bad_phy:
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
+ "phy type/rev (%d/%d)\n", unit,
+ wlc_hw->band->phytype, wlc_hw->band->phyrev);
+ err = 18;
+ goto fail;
+ }
+
+ good_phy:
+ /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
+ * high level attach. However we can not make that change until all low level access
+ * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
+ * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
+ * low only init when all fns updated.
+ */
+ wlc->band->pi = wlc_hw->band->pi;
+ wlc->band->phytype = wlc_hw->band->phytype;
+ wlc->band->phyrev = wlc_hw->band->phyrev;
+ wlc->band->radioid = wlc_hw->band->radioid;
+ wlc->band->radiorev = wlc_hw->band->radiorev;
+
+ /* default contention windows size limits */
+ wlc_hw->band->CWmin = APHY_CWMIN;
+ wlc_hw->band->CWmax = PHY_CWMAX;
+
+ if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
+ err = 19;
+ goto fail;
+ }
+ }
+
+ /* disable core to match driver "down" state */
+ wlc_coredisable(wlc_hw);
+
+ /* Match driver "down" state */
+ if (wlc_hw->sih->bustype == PCI_BUS)
+ ai_pci_down(wlc_hw->sih);
+
+ /* register sb interrupt callback functions */
+ ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
+ (void *)wlc_wlintrsrestore, NULL, wlc);
+
+ /* turn off pll and xtal to match driver "down" state */
+ wlc_bmac_xtal(wlc_hw, OFF);
+
+ /* *********************************************************************
+ * The hardware is in the DOWN state at this point. D11 core
+ * or cores are in reset with clocks off, and the board PLLs
+ * are off if possible.
+ *
+ * Beyond this point, wlc->sbclk == false and chip registers
+ * should not be touched.
+ *********************************************************************
+ */
+
+ /* init etheraddr state variables */
+ macaddr = wlc_get_macaddr(wlc_hw);
+ if (macaddr == NULL) {
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
+ unit);
+ err = 21;
+ goto fail;
+ }
+ brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
+ if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
+ is_zero_ether_addr(wlc_hw->etheraddr)) {
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
+ unit, macaddr);
+ err = 22;
+ goto fail;
+ }
+
+ BCMMSG(wlc->wiphy,
+ "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
+ wlc_hw->deviceid, wlc_hw->_nbands,
+ wlc_hw->sih->boardtype, macaddr);
+
+ return err;
+
+ fail:
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
+ err);
+ return err;
+}
+
+/*
+ * Initialize wlc_info default values ...
+ * may get overrides later in this function
+ * BMAC_NOTES, move low out and resolve the dangling ones
+ */
+static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
+{
+ struct wlc_info *wlc = wlc_hw->wlc;
+
+ /* set default sw macintmask value */
+ wlc->defmacintmask = DEF_MACINTMASK;
+
+ /* various 802.11g modes */
+ wlc_hw->shortslot = false;
+
+ wlc_hw->SFBL = RETRY_SHORT_FB;
+ wlc_hw->LFBL = RETRY_LONG_FB;
+
+ /* default mac retry limits */
+ wlc_hw->SRL = RETRY_SHORT_DEF;
+ wlc_hw->LRL = RETRY_LONG_DEF;
+ wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
+}
+
+/*
+ * low level detach
+ */
+int wlc_bmac_detach(struct wlc_info *wlc)
+{
+ uint i;
+ struct wlc_hwband *band;
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ int callbacks;
+
+ callbacks = 0;
+
+ if (wlc_hw->sih) {
+ /* detach interrupt sync mechanism since interrupt is disabled and per-port
+ * interrupt object may has been freed. this must be done before sb core switch
+ */
+ ai_deregister_intr_callback(wlc_hw->sih);
+
+ if (wlc_hw->sih->bustype == PCI_BUS)
+ ai_pci_sleep(wlc_hw->sih);
+ }
+
+ wlc_bmac_detach_dmapio(wlc_hw);
+
+ band = wlc_hw->band;
+ for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
+ if (band->pi) {
+ /* Detach this band's phy */
+ wlc_phy_detach(band->pi);
+ band->pi = NULL;
+ }
+ band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
+ }
+
+ /* Free shared phy state */
+ wlc_phy_shared_detach(wlc_hw->phy_sh);
+
+ wlc_phy_shim_detach(wlc_hw->physhim);
+
+ /* free vars */
+ kfree(wlc_hw->vars);
+ wlc_hw->vars = NULL;
+
+ if (wlc_hw->sih) {
+ ai_detach(wlc_hw->sih);
+ wlc_hw->sih = NULL;
+ }
+
+ return callbacks;
+
+}
+
+void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
+{
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ /* reset the core */
+ if (!DEVICEREMOVED(wlc_hw->wlc))
+ wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
+
+ /* purge the dma rings */
+ wlc_flushqueues(wlc_hw->wlc);
+
+ wlc_reset_bmac_done(wlc_hw->wlc);
+}
+
+void
+wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
+ bool mute) {
+ u32 macintmask;
+ bool fastclk;
+ struct wlc_info *wlc = wlc_hw->wlc;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ /* request FAST clock if not on */
+ fastclk = wlc_hw->forcefastclk;
+ if (!fastclk)
+ wlc_clkctl_clk(wlc_hw, CLK_FAST);
+
+ /* disable interrupts */
+ macintmask = brcms_intrsoff(wlc->wl);
+
+ /* set up the specified band and chanspec */
+ wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
+ wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
+
+ /* do one-time phy inits and calibration */
+ wlc_phy_cal_init(wlc_hw->band->pi);
+
+ /* core-specific initialization */
+ wlc_coreinit(wlc);
+
+ /* suspend the tx fifos and mute the phy for preism cac time */
+ if (mute)
+ wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
+
+ /* band-specific inits */
+ wlc_bmac_bsinit(wlc, chanspec);
+
+ /* restore macintmask */
+ brcms_intrsrestore(wlc->wl, macintmask);
+
+ /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
+ * and wlc_enable_mac() will clear this override bit.
+ */
+ mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
+
+ /*
+ * initialize mac_suspend_depth to 1 to match ucode initial suspended state
+ */
+ wlc_hw->mac_suspend_depth = 1;
+
+ /* restore the clk */
+ if (!fastclk)
+ wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
+}
+
+int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
+{
+ uint coremask;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ /*
+ * Enable pll and xtal, initialize the power control registers,
+ * and force fastclock for the remainder of wlc_up().
+ */
+ wlc_bmac_xtal(wlc_hw, ON);
+ ai_clkctl_init(wlc_hw->sih);
+ wlc_clkctl_clk(wlc_hw, CLK_FAST);
+
+ /*
+ * Configure pci/pcmcia here instead of in wlc_attach()
+ * to allow mfg hotswap: down, hotswap (chip power cycle), up.
+ */
+ coremask = (1 << wlc_hw->wlc->core->coreidx);
+
+ if (wlc_hw->sih->bustype == PCI_BUS)
+ ai_pci_setup(wlc_hw->sih, coremask);
+
+ /*
+ * Need to read the hwradio status here to cover the case where the system
+ * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
+ */
+ if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
+ /* put SB PCI in down state again */
+ if (wlc_hw->sih->bustype == PCI_BUS)
+ ai_pci_down(wlc_hw->sih);
+ wlc_bmac_xtal(wlc_hw, OFF);
+ return -ENOMEDIUM;
+ }
+
+ if (wlc_hw->sih->bustype == PCI_BUS)
+ ai_pci_up(wlc_hw->sih);
+
+ /* reset the d11 core */
+ wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
+
+ return 0;
+}
+
+int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
+{
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ wlc_hw->up = true;
+ wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
+
+ /* FULLY enable dynamic power control and d11 core interrupt */
+ wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
+ brcms_intrson(wlc_hw->wlc->wl);
+ return 0;
+}
+
+int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
+{
+ bool dev_gone;
+ uint callbacks = 0;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ if (!wlc_hw->up)
+ return callbacks;
+
+ dev_gone = DEVICEREMOVED(wlc_hw->wlc);
+
+ /* disable interrupts */
+ if (dev_gone)
+ wlc_hw->wlc->macintmask = 0;
+ else {
+ /* now disable interrupts */
+ brcms_intrsoff(wlc_hw->wlc->wl);
+
+ /* ensure we're running on the pll clock again */
+ wlc_clkctl_clk(wlc_hw, CLK_FAST);
+ }
+ /* down phy at the last of this stage */
+ callbacks += wlc_phy_down(wlc_hw->band->pi);
+
+ return callbacks;
+}
+
+int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
+{
+ uint callbacks = 0;
+ bool dev_gone;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ if (!wlc_hw->up)
+ return callbacks;
+
+ wlc_hw->up = false;
+ wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
+
+ dev_gone = DEVICEREMOVED(wlc_hw->wlc);
+
+ if (dev_gone) {
+ wlc_hw->sbclk = false;
+ wlc_hw->clk = false;
+ wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
+
+ /* reclaim any posted packets */
+ wlc_flushqueues(wlc_hw->wlc);
+ } else {
+
+ /* Reset and disable the core */
+ if (ai_iscoreup(wlc_hw->sih)) {
+ if (R_REG(&wlc_hw->regs->maccontrol) &
+ MCTL_EN_MAC)
+ wlc_suspend_mac_and_wait(wlc_hw->wlc);
+ callbacks += brcms_reset(wlc_hw->wlc->wl);
+ wlc_coredisable(wlc_hw);
+ }
+
+ /* turn off primary xtal and pll */
+ if (!wlc_hw->noreset) {
+ if (wlc_hw->sih->bustype == PCI_BUS)
+ ai_pci_down(wlc_hw->sih);
+ wlc_bmac_xtal(wlc_hw, OFF);
+ }
+ }
+
+ return callbacks;
+}
+
+void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
+{
+ /* delay before first read of ucode state */
+ udelay(40);
+
+ /* wait until ucode is no longer asleep */
+ SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
+ DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
+}
+
+void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
+{
+ memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
+}
+
+static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
+{
+ return wlc_hw->band->bandtype;
+}
+
+/* control chip clock to save power, enable dynamic clock or force fast clock */
+static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
+{
+ if (PMUCTL_ENAB(wlc_hw->sih)) {
+ /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
+ * but mac core will still run on ALP(not HT) when it enters powersave mode,
+ * which means the FCA bit may not be set.
+ * should wakeup mac if driver wants it to run on HT.
+ */
+
+ if (wlc_hw->clk) {
+ if (mode == CLK_FAST) {
+ OR_REG(&wlc_hw->regs->clk_ctl_st,
+ CCS_FORCEHT);
+
+ udelay(64);
+
+ SPINWAIT(((R_REG
+ (&wlc_hw->regs->
+ clk_ctl_st) & CCS_HTAVAIL) == 0),
+ PMU_MAX_TRANSITION_DLY);
+ WARN_ON(!(R_REG
+ (&wlc_hw->regs->
+ clk_ctl_st) & CCS_HTAVAIL));
+ } else {
+ if ((wlc_hw->sih->pmurev == 0) &&
+ (R_REG
+ (&wlc_hw->regs->
+ clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
+ SPINWAIT(((R_REG
+ (&wlc_hw->regs->
+ clk_ctl_st) & CCS_HTAVAIL)
+ == 0),
+ PMU_MAX_TRANSITION_DLY);
+ AND_REG(&wlc_hw->regs->clk_ctl_st,
+ ~CCS_FORCEHT);
+ }
+ }
+ wlc_hw->forcefastclk = (mode == CLK_FAST);
+ } else {
+
+ /* old chips w/o PMU, force HT through cc,
+ * then use FCA to verify mac is running fast clock
+ */
+
+ wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
+
+ /* check fast clock is available (if core is not in reset) */
+ if (wlc_hw->forcefastclk && wlc_hw->clk)
+ WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
+ SISF_FCLKA));
+
+ /* keep the ucode wake bit on if forcefastclk is on
+ * since we do not want ucode to put us back to slow clock
+ * when it dozes for PM mode.
+ * Code below matches the wake override bit with current forcefastclk state
+ * Only setting bit in wake_override instead of waking ucode immediately
+ * since old code (wlc.c 1.4499) had this behavior. Older code set
+ * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
+ * (protected by an up check) was executed just below.
+ */
+ if (wlc_hw->forcefastclk)
+ mboolset(wlc_hw->wake_override,
+ WLC_WAKE_OVERRIDE_FORCEFAST);
+ else
+ mboolclr(wlc_hw->wake_override,
+ WLC_WAKE_OVERRIDE_FORCEFAST);
+ }
+}
+
+/* set initial host flags value */
+static void
+wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+
+ memset(mhfs, 0, MHFMAX * sizeof(u16));
+
+ mhfs[MHF2] |= mhf2_init;
+
+ /* prohibit use of slowclock on multifunction boards */
+ if (wlc_hw->boardflags & BFL_NOPLLDOWN)
+ mhfs[MHF1] |= MHF1_FORCEFASTCLK;
+
+ if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
+ mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
+ mhfs[MHF1] |= MHF1_IQSWAP_WAR;
+ }
+}
+
+/* set or clear ucode host flag bits
+ * it has an optimization for no-change write
+ * it only writes through shared memory when the core has clock;
+ * pre-CLK changes should use wlc_write_mhf to get around the optimization
+ *
+ *
+ * bands values are: WLC_BAND_AUTO <--- Current band only
+ * WLC_BAND_5G <--- 5G band only
+ * WLC_BAND_2G <--- 2G band only
+ * WLC_BAND_ALL <--- All bands
+ */
+void
+wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
+ int bands)
+{
+ u16 save;
+ u16 addr[MHFMAX] = {
+ M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
+ M_HOST_FLAGS5
+ };
+ struct wlc_hwband *band;
+
+ if ((val & ~mask) || idx >= MHFMAX)
+ return; /* error condition */
+
+ switch (bands) {
+ /* Current band only or all bands,
+ * then set the band to current band
+ */
+ case WLC_BAND_AUTO:
+ case WLC_BAND_ALL:
+ band = wlc_hw->band;
+ break;
+ case WLC_BAND_5G:
+ band = wlc_hw->bandstate[BAND_5G_INDEX];
+ break;
+ case WLC_BAND_2G:
+ band = wlc_hw->bandstate[BAND_2G_INDEX];
+ break;
+ default:
+ band = NULL; /* error condition */
+ }
+
+ if (band) {
+ save = band->mhfs[idx];
+ band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
+
+ /* optimization: only write through if changed, and
+ * changed band is the current band
+ */
+ if (wlc_hw->clk && (band->mhfs[idx] != save)
+ && (band == wlc_hw->band))
+ wlc_bmac_write_shm(wlc_hw, addr[idx],
+ (u16) band->mhfs[idx]);
+ }
+
+ if (bands == WLC_BAND_ALL) {
+ wlc_hw->bandstate[0]->mhfs[idx] =
+ (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
+ wlc_hw->bandstate[1]->mhfs[idx] =
+ (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
+ }
+}
+
+u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
+{
+ struct wlc_hwband *band;
+
+ if (idx >= MHFMAX)
+ return 0; /* error condition */
+ switch (bands) {
+ case WLC_BAND_AUTO:
+ band = wlc_hw->band;
+ break;
+ case WLC_BAND_5G:
+ band = wlc_hw->bandstate[BAND_5G_INDEX];
+ break;
+ case WLC_BAND_2G:
+ band = wlc_hw->bandstate[BAND_2G_INDEX];
+ break;
+ default:
+ band = NULL; /* error condition */
+ }
+
+ if (!band)
+ return 0;
+
+ return band->mhfs[idx];
+}
+
+static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
+{
+ u8 idx;
+ u16 addr[] = {
+ M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
+ M_HOST_FLAGS5
+ };
+
+ for (idx = 0; idx < MHFMAX; idx++) {
+ wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
+ }
+}
+
+/* set the maccontrol register to desired reset state and
+ * initialize the sw cache of the register
+ */
+static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
+{
+ /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
+ wlc_hw->maccontrol = 0;
+ wlc_hw->suspended_fifos = 0;
+ wlc_hw->wake_override = 0;
+ wlc_hw->mute_override = 0;
+ wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
+}
+
+/* set or clear maccontrol bits */
+void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
+{
+ u32 maccontrol;
+ u32 new_maccontrol;
+
+ if (val & ~mask)
+ return; /* error condition */
+ maccontrol = wlc_hw->maccontrol;
+ new_maccontrol = (maccontrol & ~mask) | val;
+
+ /* if the new maccontrol value is the same as the old, nothing to do */
+ if (new_maccontrol == maccontrol)
+ return;
+
+ /* something changed, cache the new value */
+ wlc_hw->maccontrol = new_maccontrol;
+
+ /* write the new values with overrides applied */
+ wlc_mctrl_write(wlc_hw);
+}
+
+/* write the software state of maccontrol and overrides to the maccontrol register */
+static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
+{
+ u32 maccontrol = wlc_hw->maccontrol;
+
+ /* OR in the wake bit if overridden */
+ if (wlc_hw->wake_override)
+ maccontrol |= MCTL_WAKE;
+
+ /* set AP and INFRA bits for mute if needed */
+ if (wlc_hw->mute_override) {
+ maccontrol &= ~(MCTL_AP);
+ maccontrol |= MCTL_INFRA;
+ }
+
+ W_REG(&wlc_hw->regs->maccontrol, maccontrol);
+}
+
+void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
+{
+ if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
+ mboolset(wlc_hw->wake_override, override_bit);
+ return;
+ }
+
+ mboolset(wlc_hw->wake_override, override_bit);
+
+ wlc_mctrl_write(wlc_hw);
+ wlc_bmac_wait_for_wake(wlc_hw);
+
+ return;
+}
+
+void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
+{
+ mboolclr(wlc_hw->wake_override, override_bit);
+
+ if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
+ return;
+
+ wlc_mctrl_write(wlc_hw);
+
+ return;
+}
+
+/* When driver needs ucode to stop beaconing, it has to make sure that
+ * MCTL_AP is clear and MCTL_INFRA is set
+ * Mode MCTL_AP MCTL_INFRA
+ * AP 1 1
+ * STA 0 1 <--- This will ensure no beacons
+ * IBSS 0 0
+ */
+static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
+{
+ wlc_hw->mute_override = 1;
+
+ /* if maccontrol already has AP == 0 and INFRA == 1 without this
+ * override, then there is no change to write
+ */
+ if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
+ return;
+
+ wlc_mctrl_write(wlc_hw);
+
+ return;
+}
+
+/* Clear the override on AP and INFRA bits */
+static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
+{
+ if (wlc_hw->mute_override == 0)
+ return;
+
+ wlc_hw->mute_override = 0;
+
+ /* if maccontrol already has AP == 0 and INFRA == 1 without this
+ * override, then there is no change to write
+ */
+ if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
+ return;
+
+ wlc_mctrl_write(wlc_hw);
+}
+
+/*
+ * Write a MAC address to the given match reg offset in the RXE match engine.
+ */
+void
+wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
+ const u8 *addr)
+{
+ d11regs_t *regs;
+ u16 mac_l;
+ u16 mac_m;
+ u16 mac_h;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
+ wlc_hw->unit);
+
+ regs = wlc_hw->regs;
+ mac_l = addr[0] | (addr[1] << 8);
+ mac_m = addr[2] | (addr[3] << 8);
+ mac_h = addr[4] | (addr[5] << 8);
+
+ /* enter the MAC addr into the RXE match registers */
+ W_REG(®s->rcm_ctl, RCM_INC_DATA | match_reg_offset);
+ W_REG(®s->rcm_mat_data, mac_l);
+ W_REG(®s->rcm_mat_data, mac_m);
+ W_REG(®s->rcm_mat_data, mac_h);
+
+}
+
+void
+wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
+ void *buf)
+{
+ d11regs_t *regs;
+ u32 word;
+ bool be_bit;
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ regs = wlc_hw->regs;
+ W_REG(®s->tplatewrptr, offset);
+
+ /* if MCTL_BIGEND bit set in mac control register,
+ * the chip swaps data in fifo, as well as data in
+ * template ram
+ */
+ be_bit = (R_REG(®s->maccontrol) & MCTL_BIGEND) != 0;
+
+ while (len > 0) {
+ memcpy(&word, buf, sizeof(u32));
+
+ if (be_bit)
+ word = cpu_to_be32(word);
+ else
+ word = cpu_to_le32(word);
+
+ W_REG(®s->tplatewrdata, word);
+
+ buf = (u8 *) buf + sizeof(u32);
+ len -= sizeof(u32);
+ }
+}
+
+void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
+{
+ wlc_hw->band->CWmin = newmin;
+
+ W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
+ (void)R_REG(&wlc_hw->regs->objaddr);
+ W_REG(&wlc_hw->regs->objdata, newmin);
+}
+
+void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
+{
+ wlc_hw->band->CWmax = newmax;
+
+ W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
+ (void)R_REG(&wlc_hw->regs->objaddr);
+ W_REG(&wlc_hw->regs->objdata, newmax);
+}
+
+void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
+{
+ bool fastclk;
+
+ /* request FAST clock if not on */
+ fastclk = wlc_hw->forcefastclk;
+ if (!fastclk)
+ wlc_clkctl_clk(wlc_hw, CLK_FAST);
+
+ wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
+
+ wlc_bmac_phy_reset(wlc_hw);
+ wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
+
+ /* restore the clk */
+ if (!fastclk)
+ wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
+}
+
+static void
+wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
+{
+ d11regs_t *regs = wlc_hw->regs;
+
+ wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
+ bcn);
+ /* write beacon length to SCR */
+ wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
+ /* mark beacon0 valid */
+ OR_REG(®s->maccommand, MCMD_BCN0VLD);
+}
+
+static void
+wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
+{
+ d11regs_t *regs = wlc_hw->regs;
+
+ wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
+ bcn);
+ /* write beacon length to SCR */
+ wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
+ /* mark beacon1 valid */
+ OR_REG(®s->maccommand, MCMD_BCN1VLD);
+}
+
+/* mac is assumed to be suspended at this point */
+void
+wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
+ bool both)
+{
+ d11regs_t *regs = wlc_hw->regs;
+
+ if (both) {
+ wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
+ wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
+ } else {
+ /* bcn 0 */
+ if (!(R_REG(®s->maccommand) & MCMD_BCN0VLD))
+ wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
+ /* bcn 1 */
+ else if (!
+ (R_REG(®s->maccommand) & MCMD_BCN1VLD))
+ wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
+ }
+}
+
+static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
+{
+ u16 v;
+ struct wlc_info *wlc = wlc_hw->wlc;
+ /* update SYNTHPU_DLY */
+
+ if (WLCISLCNPHY(wlc->band)) {
+ v = SYNTHPU_DLY_LPPHY_US;
+ } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
+ v = SYNTHPU_DLY_NPHY_US;
+ } else {
+ v = SYNTHPU_DLY_BPHY_US;
+ }
+
+ wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
+}
+
+/* band-specific init */
+static void
+WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+
+ BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
+ wlc_hw->band->bandunit);
+
+ wlc_ucode_bsinit(wlc_hw);
+
+ wlc_phy_init(wlc_hw->band->pi, chanspec);
+
+ wlc_ucode_txant_set(wlc_hw);
+
+ /* cwmin is band-specific, update hardware with value for current band */
+ wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
+ wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
+
+ wlc_bmac_update_slot_timing(wlc_hw,
+ BAND_5G(wlc_hw->band->
+ bandtype) ? true : wlc_hw->
+ shortslot);
+
+ /* write phytype and phyvers */
+ wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
+ wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
+
+ /* initialize the txphyctl1 rate table since shmem is shared between bands */
+ wlc_upd_ofdm_pctl1_table(wlc_hw);
+
+ wlc_bmac_upd_synthpu(wlc_hw);
+}
+
+static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
+{
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
+
+ wlc_hw->phyclk = clk;
+
+ if (OFF == clk) { /* clear gmode bit, put phy into reset */
+
+ ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
+ (SICF_PRST | SICF_FGC));
+ udelay(1);
+ ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
+ udelay(1);
+
+ } else { /* take phy out of reset */
+
+ ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
+ udelay(1);
+ ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
+ udelay(1);
+
+ }
+}
+
+/* Perform a soft reset of the PHY PLL */
+void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
+{
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ ai_corereg(wlc_hw->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
+ udelay(1);
+ ai_corereg(wlc_hw->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
+ udelay(1);
+ ai_corereg(wlc_hw->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
+ udelay(1);
+ ai_corereg(wlc_hw->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
+ udelay(1);
+}
+
+/* light way to turn on phy clock without reset for NPHY only
+ * refer to wlc_bmac_core_phy_clk for full version
+ */
+void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
+{
+ /* support(necessary for NPHY and HYPHY) only */
+ if (!WLCISNPHY(wlc_hw->band))
+ return;
+
+ if (ON == clk)
+ ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
+ else
+ ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
+
+}
+
+void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
+{
+ if (ON == clk)
+ ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
+ else
+ ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
+}
+
+void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
+{
+ wlc_phy_t *pih = wlc_hw->band->pi;
+ u32 phy_bw_clkbits;
+ bool phy_in_reset = false;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ if (pih == NULL)
+ return;
+
+ phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
+
+ /* Specific reset sequence required for NPHY rev 3 and 4 */
+ if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
+ NREV_LE(wlc_hw->band->phyrev, 4)) {
+ /* Set the PHY bandwidth */
+ ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
+
+ udelay(1);
+
+ /* Perform a soft reset of the PHY PLL */
+ wlc_bmac_core_phypll_reset(wlc_hw);
+
+ /* reset the PHY */
+ ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
+ (SICF_PRST | SICF_PCLKE));
+ phy_in_reset = true;
+ } else {
+
+ ai_core_cflags(wlc_hw->sih,
+ (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
+ (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
+ }
+
+ udelay(2);
+ wlc_bmac_core_phy_clk(wlc_hw, ON);
+
+ if (pih)
+ wlc_phy_anacore(pih, ON);
+}
+
+/* switch to and initialize new band */
+static void
+WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
+ chanspec_t chanspec) {
+ struct wlc_info *wlc = wlc_hw->wlc;
+ u32 macintmask;
+
+ /* Enable the d11 core before accessing it */
+ if (!ai_iscoreup(wlc_hw->sih)) {
+ ai_core_reset(wlc_hw->sih, 0, 0);
+ wlc_mctrl_reset(wlc_hw);
+ }
+
+ macintmask = wlc_setband_inact(wlc, bandunit);
+
+ if (!wlc_hw->up)
+ return;
+
+ wlc_bmac_core_phy_clk(wlc_hw, ON);
+
+ /* band-specific initializations */
+ wlc_bmac_bsinit(wlc, chanspec);
+
+ /*
+ * If there are any pending software interrupt bits,
+ * then replace these with a harmless nonzero value
+ * so wlc_dpc() will re-enable interrupts when done.
+ */
+ if (wlc->macintstatus)
+ wlc->macintstatus = MI_DMAINT;
+
+ /* restore macintmask */
+ brcms_intrsrestore(wlc->wl, macintmask);
+
+ /* ucode should still be suspended.. */
+ WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
+}
+
+/* low-level band switch utility routine */
+void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
+{
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
+ bandunit);
+
+ wlc_hw->band = wlc_hw->bandstate[bandunit];
+
+ /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
+ wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
+
+ /* set gmode core flag */
+ if (wlc_hw->sbclk && !wlc_hw->noreset) {
+ ai_core_cflags(wlc_hw->sih, SICF_GMODE,
+ ((bandunit == 0) ? SICF_GMODE : 0));
+ }
+}
+
+static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
+{
+
+ /* reject unsupported corerev */
+ if (!VALID_COREREV(wlc_hw->corerev)) {
+ wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
+ wlc_hw->corerev);
+ return false;
+ }
+
+ return true;
+}
+
+static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
+{
+ bool goodboard = true;
+ uint boardrev = wlc_hw->boardrev;
+
+ if (boardrev == 0)
+ goodboard = false;
+ else if (boardrev > 0xff) {
+ uint brt = (boardrev & 0xf000) >> 12;
+ uint b0 = (boardrev & 0xf00) >> 8;
+ uint b1 = (boardrev & 0xf0) >> 4;
+ uint b2 = boardrev & 0xf;
+
+ if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
+ || (b2 > 9))
+ goodboard = false;
+ }
+
+ if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
+ return goodboard;
+
+ return goodboard;
+}
+
+static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
+{
+ const char *varname = "macaddr";
+ char *macaddr;
+
+ /* If macaddr exists, use it (Sromrev4, CIS, ...). */
+ macaddr = getvar(wlc_hw->vars, varname);
+ if (macaddr != NULL)
+ return macaddr;
+
+ if (NBANDS_HW(wlc_hw) > 1)
+ varname = "et1macaddr";
+ else
+ varname = "il0macaddr";
+
+ macaddr = getvar(wlc_hw->vars, varname);
+ if (macaddr == NULL) {
+ wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
+ "getvar(%s) not found\n", wlc_hw->unit, varname);
+ }
+
+ return macaddr;
+}
+
+/*
+ * Return true if radio is disabled, otherwise false.
+ * hw radio disable signal is an external pin, users activate it asynchronously
+ * this function could be called when driver is down and w/o clock
+ * it operates on different registers depending on corerev and boardflag.
+ */
+bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
+{
+ bool v, clk, xtal;
+ u32 resetbits = 0, flags = 0;
+
+ xtal = wlc_hw->sbclk;
+ if (!xtal)
+ wlc_bmac_xtal(wlc_hw, ON);
+
+ /* may need to take core out of reset first */
+ clk = wlc_hw->clk;
+ if (!clk) {
+ /*
+ * mac no longer enables phyclk automatically when driver
+ * accesses phyreg throughput mac. This can be skipped since
+ * only mac reg is accessed below
+ */
+ flags |= SICF_PCLKE;
+
+ /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
+ if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
+ (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
+ (wlc_hw->sih->chip == BCM43421_CHIP_ID))
+ wlc_hw->regs =
+ (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
+ 0);
+ ai_core_reset(wlc_hw->sih, flags, resetbits);
+ wlc_mctrl_reset(wlc_hw);
+ }
+
+ v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
+
+ /* put core back into reset */
+ if (!clk)
+ ai_core_disable(wlc_hw->sih, 0);
+
+ if (!xtal)
+ wlc_bmac_xtal(wlc_hw, OFF);
+
+ return v;
+}
+
+/* Initialize just the hardware when coming out of POR or S3/S5 system states */
+void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
+{
+ if (wlc_hw->wlc->pub->hw_up)
+ return;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ /*
+ * Enable pll and xtal, initialize the power control registers,
+ * and force fastclock for the remainder of wlc_up().
+ */
+ wlc_bmac_xtal(wlc_hw, ON);
+ ai_clkctl_init(wlc_hw->sih);
+ wlc_clkctl_clk(wlc_hw, CLK_FAST);
+
+ if (wlc_hw->sih->bustype == PCI_BUS) {
+ ai_pci_fixcfg(wlc_hw->sih);
+
+ /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
+ if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
+ (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
+ (wlc_hw->sih->chip == BCM43421_CHIP_ID))
+ wlc_hw->regs =
+ (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
+ 0);
+ }
+
+ /* Inform phy that a POR reset has occurred so it does a complete phy init */
+ wlc_phy_por_inform(wlc_hw->band->pi);
+
+ wlc_hw->ucode_loaded = false;
+ wlc_hw->wlc->pub->hw_up = true;
+
+ if ((wlc_hw->boardflags & BFL_FEM)
+ && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
+ if (!
+ (wlc_hw->boardrev >= 0x1250
+ && (wlc_hw->boardflags & BFL_FEM_BT)))
+ ai_epa_4313war(wlc_hw->sih);
+ }
+}
+
+static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
+{
+ struct dma_pub *di = wlc_hw->di[fifo];
+ return dma_rxreset(di);
+}
+
+/* d11 core reset
+ * ensure fask clock during reset
+ * reset dma
+ * reset d11(out of reset)
+ * reset phy(out of reset)
+ * clear software macintstatus for fresh new start
+ * one testing hack wlc_hw->noreset will bypass the d11/phy reset
+ */
+void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
+{
+ d11regs_t *regs;
+ uint i;
+ bool fastclk;
+ u32 resetbits = 0;
+
+ if (flags == WLC_USE_COREFLAGS)
+ flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ regs = wlc_hw->regs;
+
+ /* request FAST clock if not on */
+ fastclk = wlc_hw->forcefastclk;
+ if (!fastclk)
+ wlc_clkctl_clk(wlc_hw, CLK_FAST);
+
+ /* reset the dma engines except first time thru */
+ if (ai_iscoreup(wlc_hw->sih)) {
+ for (i = 0; i < NFIFO; i++)
+ if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
+ wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
+ "dma_txreset[%d]: cannot stop dma\n",
+ wlc_hw->unit, __func__, i);
+ }
+
+ if ((wlc_hw->di[RX_FIFO])
+ && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
+ wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
+ "[%d]: cannot stop dma\n",
+ wlc_hw->unit, __func__, RX_FIFO);
+ }
+ }
+ /* if noreset, just stop the psm and return */
+ if (wlc_hw->noreset) {
+ wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
+ wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
+ return;
+ }
+
+ /*
+ * mac no longer enables phyclk automatically when driver accesses
+ * phyreg throughput mac, AND phy_reset is skipped at early stage when
+ * band->pi is invalid. need to enable PHY CLK
+ */
+ flags |= SICF_PCLKE;
+
+ /* reset the core
+ * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
+ * is cleared by the core_reset. have to re-request it.
+ * This adds some delay and we can optimize it by also requesting fastclk through
+ * chipcommon during this period if necessary. But that has to work coordinate
+ * with other driver like mips/arm since they may touch chipcommon as well.
+ */
+ wlc_hw->clk = false;
+ ai_core_reset(wlc_hw->sih, flags, resetbits);
+ wlc_hw->clk = true;
+ if (wlc_hw->band && wlc_hw->band->pi)
+ wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
+
+ wlc_mctrl_reset(wlc_hw);
+
+ if (PMUCTL_ENAB(wlc_hw->sih))
+ wlc_clkctl_clk(wlc_hw, CLK_FAST);
+
+ wlc_bmac_phy_reset(wlc_hw);
+
+ /* turn on PHY_PLL */
+ wlc_bmac_core_phypll_ctl(wlc_hw, true);
+
+ /* clear sw intstatus */
+ wlc_hw->wlc->macintstatus = 0;
+
+ /* restore the clk setting */
+ if (!fastclk)
+ wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
+}
+
+/* txfifo sizes needs to be modified(increased) since the newer cores
+ * have more memory.
+ */
+static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
+{
+ d11regs_t *regs = wlc_hw->regs;
+ u16 fifo_nu;
+ u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
+ u16 txfifo_def, txfifo_def1;
+ u16 txfifo_cmd;
+
+ /* tx fifos start at TXFIFO_START_BLK from the Base address */
+ txfifo_startblk = TXFIFO_START_BLK;
+
+ /* sequence of operations: reset fifo, set fifo size, reset fifo */
+ for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
+
+ txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
+ txfifo_def = (txfifo_startblk & 0xff) |
+ (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
+ txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
+ ((((txfifo_endblk -
+ 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
+ txfifo_cmd =
+ TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
+
+ W_REG(®s->xmtfifocmd, txfifo_cmd);
+ W_REG(®s->xmtfifodef, txfifo_def);
+ W_REG(®s->xmtfifodef1, txfifo_def1);
+
+ W_REG(®s->xmtfifocmd, txfifo_cmd);
+
+ txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
+ }
+ /*
+ * need to propagate to shm location to be in sync since ucode/hw won't
+ * do this
+ */
+ wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
+ wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
+ wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
+ wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
+ wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
+ ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
+ xmtfifo_sz[TX_AC_BK_FIFO]));
+ wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
+ ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
+ xmtfifo_sz[TX_BCMC_FIFO]));
+}
+
+/* d11 core init
+ * reset PSM
+ * download ucode/PCM
+ * let ucode run to suspended
+ * download ucode inits
+ * config other core registers
+ * init dma
+ */
+static void wlc_coreinit(struct wlc_info *wlc)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ d11regs_t *regs;
+ u32 sflags;
+ uint bcnint_us;
+ uint i = 0;
+ bool fifosz_fixup = false;
+ int err = 0;
+ u16 buf[NFIFO];
+ struct wiphy *wiphy = wlc->wiphy;
+
+ regs = wlc_hw->regs;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ /* reset PSM */
+ wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
+
+ wlc_ucode_download(wlc_hw);
+ /*
+ * FIFOSZ fixup. driver wants to controls the fifo allocation.
+ */
+ fifosz_fixup = true;
+
+ /* let the PSM run to the suspended state, set mode to BSS STA */
+ W_REG(®s->macintstatus, -1);
+ wlc_bmac_mctrl(wlc_hw, ~0,
+ (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
+
+ /* wait for ucode to self-suspend after auto-init */
+ SPINWAIT(((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0),
+ 1000 * 1000);
+ if ((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0)
+ wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
+ "suspend!\n", wlc_hw->unit);
+
+ wlc_gpio_init(wlc);
+
+ sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
+
+ if (D11REV_IS(wlc_hw->corerev, 23)) {
+ if (WLCISNPHY(wlc_hw->band))
+ wlc_write_inits(wlc_hw, d11n0initvals16);
+ else
+ wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
+ " %d\n", __func__, wlc_hw->unit,
+ wlc_hw->corerev);
+ } else if (D11REV_IS(wlc_hw->corerev, 24)) {
+ if (WLCISLCNPHY(wlc_hw->band)) {
+ wlc_write_inits(wlc_hw, d11lcn0initvals24);
+ } else {
+ wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
+ " %d\n", __func__, wlc_hw->unit,
+ wlc_hw->corerev);
+ }
+ } else {
+ wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
+ __func__, wlc_hw->unit, wlc_hw->corerev);
+ }
+
+ /* For old ucode, txfifo sizes needs to be modified(increased) */
+ if (fifosz_fixup == true) {
+ wlc_corerev_fifofixup(wlc_hw);
+ }
+
+ /* check txfifo allocations match between ucode and driver */
+ buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
+ if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
+ i = TX_AC_BE_FIFO;
+ err = -1;
+ }
+ buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
+ if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
+ i = TX_AC_VI_FIFO;
+ err = -1;
+ }
+ buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
+ buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
+ buf[TX_AC_BK_FIFO] &= 0xff;
+ if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
+ i = TX_AC_BK_FIFO;
+ err = -1;
+ }
+ if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
+ i = TX_AC_VO_FIFO;
+ err = -1;
+ }
+ buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
+ buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
+ buf[TX_BCMC_FIFO] &= 0xff;
+ if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
+ i = TX_BCMC_FIFO;
+ err = -1;
+ }
+ if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
+ i = TX_ATIM_FIFO;
+ err = -1;
+ }
+ if (err != 0) {
+ wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
+ " driver size %d index %d\n", buf[i],
+ wlc_hw->xmtfifo_sz[i], i);
+ }
+
+ /* make sure we can still talk to the mac */
+ WARN_ON(R_REG(®s->maccontrol) == 0xffffffff);
+
+ /* band-specific inits done by wlc_bsinit() */
+
+ /* Set up frame burst size and antenna swap threshold init values */
+ wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
+ wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
+
+ /* enable one rx interrupt per received frame */
+ W_REG(®s->intrcvlazy[0], (1 << IRL_FC_SHIFT));
+
+ /* set the station mode (BSS STA) */
+ wlc_bmac_mctrl(wlc_hw,
+ (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
+ (MCTL_INFRA | MCTL_DISCARD_PMQ));
+
+ /* set up Beacon interval */
+ bcnint_us = 0x8000 << 10;
+ W_REG(®s->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
+ W_REG(®s->tsf_cfpstart, bcnint_us);
+ W_REG(®s->macintstatus, MI_GP1);
+
+ /* write interrupt mask */
+ W_REG(®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
+
+ /* allow the MAC to control the PHY clock (dynamic on/off) */
+ wlc_bmac_macphyclk_set(wlc_hw, ON);
+
+ /* program dynamic clock control fast powerup delay register */
+ wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
+ W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
+
+ /* tell the ucode the corerev */
+ wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
+
+ /* tell the ucode MAC capabilities */
+ wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
+ (u16) (wlc_hw->machwcap & 0xffff));
+ wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
+ (u16) ((wlc_hw->
+ machwcap >> 16) & 0xffff));
+
+ /* write retry limits to SCR, this done after PSM init */
+ W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
+ (void)R_REG(®s->objaddr);
+ W_REG(®s->objdata, wlc_hw->SRL);
+ W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
+ (void)R_REG(®s->objaddr);
+ W_REG(®s->objdata, wlc_hw->LRL);
+
+ /* write rate fallback retry limits */
+ wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
+ wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
+
+ AND_REG(®s->ifs_ctl, 0x0FFF);
+ W_REG(®s->ifs_aifsn, EDCF_AIFSN_MIN);
+
+ /* dma initializations */
+ wlc->txpend16165war = 0;
+
+ /* init the tx dma engines */
+ for (i = 0; i < NFIFO; i++) {
+ if (wlc_hw->di[i])
+ dma_txinit(wlc_hw->di[i]);
+ }
+
+ /* init the rx dma engine(s) and post receive buffers */
+ dma_rxinit(wlc_hw->di[RX_FIFO]);
+ dma_rxfill(wlc_hw->di[RX_FIFO]);
+}
+
+/* This function is used for changing the tsf frac register
+ * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
+ * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
+ * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
+ * HTPHY Formula is 2^26/freq(MHz) e.g.
+ * For spuron2 - 126MHz -> 2^26/126 = 532610.0
+ * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
+ * For spuron: 123MHz -> 2^26/123 = 545600.5
+ * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
+ * For spur off: 120MHz -> 2^26/120 = 559240.5
+ * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
+ */
+
+void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
+{
+ d11regs_t *regs;
+ regs = wlc_hw->regs;
+
+ if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
+ (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
+ if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
+ W_REG(®s->tsf_clk_frac_l, 0x2082);
+ W_REG(®s->tsf_clk_frac_h, 0x8);
+ } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
+ W_REG(®s->tsf_clk_frac_l, 0x5341);
+ W_REG(®s->tsf_clk_frac_h, 0x8);
+ } else { /* 120Mhz */
+ W_REG(®s->tsf_clk_frac_l, 0x8889);
+ W_REG(®s->tsf_clk_frac_h, 0x8);
+ }
+ } else if (WLCISLCNPHY(wlc_hw->band)) {
+ if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
+ W_REG(®s->tsf_clk_frac_l, 0x7CE0);
+ W_REG(®s->tsf_clk_frac_h, 0xC);
+ } else { /* 80Mhz */
+ W_REG(®s->tsf_clk_frac_l, 0xCCCD);
+ W_REG(®s->tsf_clk_frac_h, 0xC);
+ }
+ }
+}
+
+/* Initialize GPIOs that are controlled by D11 core */
+static void wlc_gpio_init(struct wlc_info *wlc)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ d11regs_t *regs;
+ u32 gc, gm;
+
+ regs = wlc_hw->regs;
+
+ /* use GPIO select 0 to get all gpio signals from the gpio out reg */
+ wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
+
+ /*
+ * Common GPIO setup:
+ * G0 = LED 0 = WLAN Activity
+ * G1 = LED 1 = WLAN 2.4 GHz Radio State
+ * G2 = LED 2 = WLAN 5 GHz Radio State
+ * G4 = radio disable input (HI enabled, LO disabled)
+ */
+
+ gc = gm = 0;
+
+ /* Allocate GPIOs for mimo antenna diversity feature */
+ if (wlc_hw->antsel_type == ANTSEL_2x3) {
+ /* Enable antenna diversity, use 2x3 mode */
+ wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
+ MHF3_ANTSEL_EN, WLC_BAND_ALL);
+ wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
+ MHF3_ANTSEL_MODE, WLC_BAND_ALL);
+
+ /* init superswitch control */
+ wlc_phy_antsel_init(wlc_hw->band->pi, false);
+
+ } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
+ gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
+ /*
+ * The board itself is powered by these GPIOs
+ * (when not sending pattern) so set them high
+ */
+ OR_REG(®s->psm_gpio_oe,
+ (BOARD_GPIO_12 | BOARD_GPIO_13));
+ OR_REG(®s->psm_gpio_out,
+ (BOARD_GPIO_12 | BOARD_GPIO_13));
+
+ /* Enable antenna diversity, use 2x4 mode */
+ wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
+ MHF3_ANTSEL_EN, WLC_BAND_ALL);
+ wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
+ WLC_BAND_ALL);
+
+ /* Configure the desired clock to be 4Mhz */
+ wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
+ ANTSEL_CLKDIV_4MHZ);
+ }
+
+ /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
+ if (wlc_hw->boardflags & BFL_PACTRL)
+ gm |= gc |= BOARD_GPIO_PACTRL;
+
+ /* apply to gpiocontrol register */
+ ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
+}
+
+static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
+{
+ struct wlc_info *wlc;
+ wlc = wlc_hw->wlc;
+
+ if (wlc_hw->ucode_loaded)
+ return;
+
+ if (D11REV_IS(wlc_hw->corerev, 23)) {
+ if (WLCISNPHY(wlc_hw->band)) {
+ wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
+ bcm43xx_16_mimosz);
+ wlc_hw->ucode_loaded = true;
+ } else
+ wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
+ "corerev %d\n",
+ __func__, wlc_hw->unit, wlc_hw->corerev);
+ } else if (D11REV_IS(wlc_hw->corerev, 24)) {
+ if (WLCISLCNPHY(wlc_hw->band)) {
+ wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
+ bcm43xx_24_lcnsz);
+ wlc_hw->ucode_loaded = true;
+ } else {
+ wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
+ "corerev %d\n",
+ __func__, wlc_hw->unit, wlc_hw->corerev);
+ }
+ }
+}
+
+static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
+ const uint nbytes) {
+ d11regs_t *regs = wlc_hw->regs;
+ uint i;
+ uint count;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ count = (nbytes / sizeof(u32));
+
+ W_REG(®s->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
+ (void)R_REG(®s->objaddr);
+ for (i = 0; i < count; i++)
+ W_REG(®s->objdata, ucode[i]);
+}
+
+static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
+ const struct d11init *inits)
+{
+ int i;
+ volatile u8 *base;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ base = (volatile u8 *)wlc_hw->regs;
+
+ for (i = 0; inits[i].addr != 0xffff; i++) {
+ if (inits[i].size == 2)
+ W_REG((u16 *)(base + inits[i].addr),
+ inits[i].value);
+ else if (inits[i].size == 4)
+ W_REG((u32 *)(base + inits[i].addr),
+ inits[i].value);
+ }
+}
+
+static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
+{
+ u16 phyctl;
+ u16 phytxant = wlc_hw->bmac_phytxant;
+ u16 mask = PHY_TXC_ANT_MASK;
+
+ /* set the Probe Response frame phy control word */
+ phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
+ phyctl = (phyctl & ~mask) | phytxant;
+ wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
+
+ /* set the Response (ACK/CTS) frame phy control word */
+ phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
+ phyctl = (phyctl & ~mask) | phytxant;
+ wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
+}
+
+void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
+{
+ /* update sw state */
+ wlc_hw->bmac_phytxant = phytxant;
+
+ /* push to ucode if up */
+ if (!wlc_hw->up)
+ return;
+ wlc_ucode_txant_set(wlc_hw);
+
+}
+
+u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
+{
+ return (u16) wlc_hw->wlc->stf->txant;
+}
+
+void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
+{
+ wlc_hw->antsel_type = antsel_type;
+
+ /* Update the antsel type for phy module to use */
+ wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
+}
+
+void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
+{
+ bool fatal = false;
+ uint unit;
+ uint intstatus, idx;
+ d11regs_t *regs = wlc_hw->regs;
+ struct wiphy *wiphy = wlc_hw->wlc->wiphy;
+
+ unit = wlc_hw->unit;
+
+ for (idx = 0; idx < NFIFO; idx++) {
+ /* read intstatus register and ignore any non-error bits */
+ intstatus =
+ R_REG(®s->intctrlregs[idx].intstatus) & I_ERRORS;
+ if (!intstatus)
+ continue;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
+ unit, idx, intstatus);
+
+ if (intstatus & I_RO) {
+ wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
+ "overflow\n", unit, idx);
+ fatal = true;
+ }
+
+ if (intstatus & I_PC) {
+ wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
+ unit, idx);
+ fatal = true;
+ }
+
+ if (intstatus & I_PD) {
+ wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
+ idx);
+ fatal = true;
+ }
+
+ if (intstatus & I_DE) {
+ wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
+ "error\n", unit, idx);
+ fatal = true;
+ }
+
+ if (intstatus & I_RU) {
+ wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
+ "underflow\n", idx, unit);
+ }
+
+ if (intstatus & I_XU) {
+ wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
+ "underflow\n", idx, unit);
+ fatal = true;
+ }
+
+ if (fatal) {
+ wlc_fatal_error(wlc_hw->wlc); /* big hammer */
+ break;
+ } else
+ W_REG(®s->intctrlregs[idx].intstatus,
+ intstatus);
+ }
+}
+
+void wlc_intrson(struct wlc_info *wlc)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ wlc->macintmask = wlc->defmacintmask;
+ W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
+}
+
+/* callback for siutils.c, which has only wlc handler, no wl
+ * they both check up, not only because there is no need to off/restore d11 interrupt
+ * but also because per-port code may require sync with valid interrupt.
+ */
+
+static u32 wlc_wlintrsoff(struct wlc_info *wlc)
+{
+ if (!wlc->hw->up)
+ return 0;
+
+ return brcms_intrsoff(wlc->wl);
+}
+
+static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
+{
+ if (!wlc->hw->up)
+ return;
+
+ brcms_intrsrestore(wlc->wl, macintmask);
+}
+
+u32 wlc_intrsoff(struct wlc_info *wlc)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ u32 macintmask;
+
+ if (!wlc_hw->clk)
+ return 0;
+
+ macintmask = wlc->macintmask; /* isr can still happen */
+
+ W_REG(&wlc_hw->regs->macintmask, 0);
+ (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
+ udelay(1); /* ensure int line is no longer driven */
+ wlc->macintmask = 0;
+
+ /* return previous macintmask; resolve race between us and our isr */
+ return wlc->macintstatus ? 0 : macintmask;
+}
+
+void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ if (!wlc_hw->clk)
+ return;
+
+ wlc->macintmask = macintmask;
+ W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
+}
+
+static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
+{
+ u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
+
+ if (on) {
+ /* suspend tx fifos */
+ wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
+ wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
+ wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
+ wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
+
+ /* zero the address match register so we do not send ACKs */
+ wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
+ null_ether_addr);
+ } else {
+ /* resume tx fifos */
+ if (!wlc_hw->wlc->tx_suspended) {
+ wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
+ }
+ wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
+ wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
+ wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
+
+ /* Restore address */
+ wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
+ wlc_hw->etheraddr);
+ }
+
+ wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
+
+ if (on)
+ wlc_ucode_mute_override_set(wlc_hw);
+ else
+ wlc_ucode_mute_override_clear(wlc_hw);
+}
+
+int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
+{
+ if (fifo >= NFIFO)
+ return -EINVAL;
+
+ *blocks = wlc_hw->xmtfifo_sz[fifo];
+
+ return 0;
+}
+
+/* wlc_bmac_tx_fifo_suspended:
+ * Check the MAC's tx suspend status for a tx fifo.
+ *
+ * When the MAC acknowledges a tx suspend, it indicates that no more
+ * packets will be transmitted out the radio. This is independent of
+ * DMA channel suspension---the DMA may have finished suspending, or may still
+ * be pulling data into a tx fifo, by the time the MAC acks the suspend
+ * request.
+ */
+static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
+{
+ /* check that a suspend has been requested and is no longer pending */
+
+ /*
+ * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
+ * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
+ * chnstatus register.
+ * The tx fifo suspend completion is independent of the DMA suspend completion and
+ * may be acked before or after the DMA is suspended.
+ */
+ if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
+ (R_REG(&wlc_hw->regs->chnstatus) &
+ (1 << tx_fifo)) == 0)
+ return true;
+
+ return false;
+}
+
+static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
+{
+ u8 fifo = 1 << tx_fifo;
+
+ /* Two clients of this code, 11h Quiet period and scanning. */
+
+ /* only suspend if not already suspended */
+ if ((wlc_hw->suspended_fifos & fifo) == fifo)
+ return;
+
+ /* force the core awake only if not already */
+ if (wlc_hw->suspended_fifos == 0)
+ wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
+
+ wlc_hw->suspended_fifos |= fifo;
+
+ if (wlc_hw->di[tx_fifo]) {
+ /* Suspending AMPDU transmissions in the middle can cause underflow
+ * which may result in mismatch between ucode and driver
+ * so suspend the mac before suspending the FIFO
+ */
+ if (WLC_PHY_11N_CAP(wlc_hw->band))
+ wlc_suspend_mac_and_wait(wlc_hw->wlc);
+
+ dma_txsuspend(wlc_hw->di[tx_fifo]);
+
+ if (WLC_PHY_11N_CAP(wlc_hw->band))
+ wlc_enable_mac(wlc_hw->wlc);
+ }
+}
+
+static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
+{
+ /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
+ * here for PIO otherwise the watchdog will catch the inconsistency and fire
+ */
+ /* Two clients of this code, 11h Quiet period and scanning. */
+ if (wlc_hw->di[tx_fifo])
+ dma_txresume(wlc_hw->di[tx_fifo]);
+
+ /* allow core to sleep again */
+ if (wlc_hw->suspended_fifos == 0)
+ return;
+ else {
+ wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
+ if (wlc_hw->suspended_fifos == 0)
+ wlc_ucode_wake_override_clear(wlc_hw,
+ WLC_WAKE_OVERRIDE_TXFIFO);
+ }
+}
+
+/*
+ * Read and clear macintmask and macintstatus and intstatus registers.
+ * This routine should be called with interrupts off
+ * Return:
+ * -1 if DEVICEREMOVED(wlc) evaluates to true;
+ * 0 if the interrupt is not for us, or we are in some special cases;
+ * device interrupt status bits otherwise.
+ */
+static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ d11regs_t *regs = wlc_hw->regs;
+ u32 macintstatus;
+
+ /* macintstatus includes a DMA interrupt summary bit */
+ macintstatus = R_REG(®s->macintstatus);
+
+ BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
+ macintstatus);
+
+ /* detect cardbus removed, in power down(suspend) and in reset */
+ if (DEVICEREMOVED(wlc))
+ return -1;
+
+ /* DEVICEREMOVED succeeds even when the core is still resetting,
+ * handle that case here.
+ */
+ if (macintstatus == 0xffffffff)
+ return 0;
+
+ /* defer unsolicited interrupts */
+ macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
+
+ /* if not for us */
+ if (macintstatus == 0)
+ return 0;
+
+ /* interrupts are already turned off for CFE build
+ * Caution: For CFE Turning off the interrupts again has some undesired
+ * consequences
+ */
+ /* turn off the interrupts */
+ W_REG(®s->macintmask, 0);
+ (void)R_REG(®s->macintmask); /* sync readback */
+ wlc->macintmask = 0;
+
+ /* clear device interrupts */
+ W_REG(®s->macintstatus, macintstatus);
+
+ /* MI_DMAINT is indication of non-zero intstatus */
+ if (macintstatus & MI_DMAINT) {
+ /*
+ * only fifo interrupt enabled is I_RI in
+ * RX_FIFO. If MI_DMAINT is set, assume it
+ * is set and clear the interrupt.
+ */
+ W_REG(®s->intctrlregs[RX_FIFO].intstatus,
+ DEF_RXINTMASK);
+ }
+
+ return macintstatus;
+}
+
+/* Update wlc->macintstatus and wlc->intstatus[]. */
+/* Return true if they are updated successfully. false otherwise */
+bool wlc_intrsupd(struct wlc_info *wlc)
+{
+ u32 macintstatus;
+
+ /* read and clear macintstatus and intstatus registers */
+ macintstatus = wlc_intstatus(wlc, false);
+
+ /* device is removed */
+ if (macintstatus == 0xffffffff)
+ return false;
+
+ /* update interrupt status in software */
+ wlc->macintstatus |= macintstatus;
+
+ return true;
+}
+
+/*
+ * First-level interrupt processing.
+ * Return true if this was our interrupt, false otherwise.
+ * *wantdpc will be set to true if further wlc_dpc() processing is required,
+ * false otherwise.
+ */
+bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ u32 macintstatus;
+
+ *wantdpc = false;
+
+ if (!wlc_hw->up || !wlc->macintmask)
+ return false;
+
+ /* read and clear macintstatus and intstatus registers */
+ macintstatus = wlc_intstatus(wlc, true);
+
+ if (macintstatus == 0xffffffff)
+ wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
+ " path\n");
+
+ /* it is not for us */
+ if (macintstatus == 0)
+ return false;
+
+ *wantdpc = true;
+
+ /* save interrupt status bits */
+ wlc->macintstatus = macintstatus;
+
+ return true;
+
+}
+
+static bool
+wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
+{
+ /* discard intermediate indications for ucode with one legitimate case:
+ * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
+ * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
+ * transmission count)
+ */
+ if (!(txs->status & TX_STATUS_AMPDU)
+ && (txs->status & TX_STATUS_INTERMEDIATE)) {
+ return false;
+ }
+
+ return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
+}
+
+/* process tx completion events in BMAC
+ * Return true if more tx status need to be processed. false otherwise.
+ */
+static bool
+wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
+{
+ bool morepending = false;
+ struct wlc_info *wlc = wlc_hw->wlc;
+ d11regs_t *regs;
+ tx_status_t txstatus, *txs;
+ u32 s1, s2;
+ uint n = 0;
+ /*
+ * Param 'max_tx_num' indicates max. # tx status to process before
+ * break out.
+ */
+ uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ txs = &txstatus;
+ regs = wlc_hw->regs;
+ while (!(*fatal)
+ && (s1 = R_REG(®s->frmtxstatus)) & TXS_V) {
+
+ if (s1 == 0xffffffff) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
+ wlc_hw->unit, __func__);
+ return morepending;
+ }
+
+ s2 = R_REG(®s->frmtxstatus2);
+
+ txs->status = s1 & TXS_STATUS_MASK;
+ txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
+ txs->sequence = s2 & TXS_SEQ_MASK;
+ txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
+ txs->lasttxtime = 0;
+
+ *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
+
+ /* !give others some time to run! */
+ if (++n >= max_tx_num)
+ break;
+ }
+
+ if (*fatal)
+ return 0;
+
+ if (n >= max_tx_num)
+ morepending = true;
+
+ if (!pktq_empty(&wlc->pkt_queue->q))
+ wlc_send_q(wlc);
+
+ return morepending;
+}
+
+void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ d11regs_t *regs = wlc_hw->regs;
+ u32 mc, mi;
+ struct wiphy *wiphy = wlc->wiphy;
+
+ BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
+ wlc_hw->band->bandunit);
+
+ /*
+ * Track overlapping suspend requests
+ */
+ wlc_hw->mac_suspend_depth++;
+ if (wlc_hw->mac_suspend_depth > 1)
+ return;
+
+ /* force the core awake */
+ wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
+
+ mc = R_REG(®s->maccontrol);
+
+ if (mc == 0xffffffff) {
+ wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
+ __func__);
+ brcms_down(wlc->wl);
+ return;
+ }
+ WARN_ON(mc & MCTL_PSM_JMP_0);
+ WARN_ON(!(mc & MCTL_PSM_RUN));
+ WARN_ON(!(mc & MCTL_EN_MAC));
+
+ mi = R_REG(®s->macintstatus);
+ if (mi == 0xffffffff) {
+ wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
+ __func__);
+ brcms_down(wlc->wl);
+ return;
+ }
+ WARN_ON(mi & MI_MACSSPNDD);
+
+ wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
+
+ SPINWAIT(!(R_REG(®s->macintstatus) & MI_MACSSPNDD),
+ WLC_MAX_MAC_SUSPEND);
+
+ if (!(R_REG(®s->macintstatus) & MI_MACSSPNDD)) {
+ wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
+ " and MI_MACSSPNDD is still not on.\n",
+ wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
+ wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
+ "psm_brc 0x%04x\n", wlc_hw->unit,
+ R_REG(®s->psmdebug),
+ R_REG(®s->phydebug),
+ R_REG(®s->psm_brc));
+ }
+
+ mc = R_REG(®s->maccontrol);
+ if (mc == 0xffffffff) {
+ wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
+ __func__);
+ brcms_down(wlc->wl);
+ return;
+ }
+ WARN_ON(mc & MCTL_PSM_JMP_0);
+ WARN_ON(!(mc & MCTL_PSM_RUN));
+ WARN_ON(mc & MCTL_EN_MAC);
+}
+
+void wlc_enable_mac(struct wlc_info *wlc)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ d11regs_t *regs = wlc_hw->regs;
+ u32 mc, mi;
+
+ BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
+ wlc->band->bandunit);
+
+ /*
+ * Track overlapping suspend requests
+ */
+ wlc_hw->mac_suspend_depth--;
+ if (wlc_hw->mac_suspend_depth > 0)
+ return;
+
+ mc = R_REG(®s->maccontrol);
+ WARN_ON(mc & MCTL_PSM_JMP_0);
+ WARN_ON(mc & MCTL_EN_MAC);
+ WARN_ON(!(mc & MCTL_PSM_RUN));
+
+ wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
+ W_REG(®s->macintstatus, MI_MACSSPNDD);
+
+ mc = R_REG(®s->maccontrol);
+ WARN_ON(mc & MCTL_PSM_JMP_0);
+ WARN_ON(!(mc & MCTL_EN_MAC));
+ WARN_ON(!(mc & MCTL_PSM_RUN));
+
+ mi = R_REG(®s->macintstatus);
+ WARN_ON(mi & MI_MACSSPNDD);
+
+ wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
+}
+
+static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
+{
+ u8 rate;
+ u8 rates[8] = {
+ WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
+ WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
+ };
+ u16 entry_ptr;
+ u16 pctl1;
+ uint i;
+
+ if (!WLC_PHY_11N_CAP(wlc_hw->band))
+ return;
+
+ /* walk the phy rate table and update the entries */
+ for (i = 0; i < ARRAY_SIZE(rates); i++) {
+ rate = rates[i];
+
+ entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
+
+ /* read the SHM Rate Table entry OFDM PCTL1 values */
+ pctl1 =
+ wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
+
+ /* modify the value */
+ pctl1 &= ~PHY_TXC1_MODE_MASK;
+ pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
+
+ /* Update the SHM Rate Table entry OFDM PCTL1 values */
+ wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
+ pctl1);
+ }
+}
+
+static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
+{
+ uint i;
+ u8 plcp_rate = 0;
+ struct plcp_signal_rate_lookup {
+ u8 rate;
+ u8 signal_rate;
+ };
+ /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
+ const struct plcp_signal_rate_lookup rate_lookup[] = {
+ {WLC_RATE_6M, 0xB},
+ {WLC_RATE_9M, 0xF},
+ {WLC_RATE_12M, 0xA},
+ {WLC_RATE_18M, 0xE},
+ {WLC_RATE_24M, 0x9},
+ {WLC_RATE_36M, 0xD},
+ {WLC_RATE_48M, 0x8},
+ {WLC_RATE_54M, 0xC}
+ };
+
+ for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
+ if (rate == rate_lookup[i].rate) {
+ plcp_rate = rate_lookup[i].signal_rate;
+ break;
+ }
+ }
+
+ /* Find the SHM pointer to the rate table entry by looking in the
+ * Direct-map Table
+ */
+ return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
+}
+
+void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
+{
+ wlc_hw->hw_stf_ss_opmode = stf_mode;
+
+ if (wlc_hw->clk)
+ wlc_upd_ofdm_pctl1_table(wlc_hw);
+}
+
+void
+wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
+ u32 *tsf_h_ptr)
+{
+ d11regs_t *regs = wlc_hw->regs;
+
+ /* read the tsf timer low, then high to get an atomic read */
+ *tsf_l_ptr = R_REG(®s->tsf_timerlow);
+ *tsf_h_ptr = R_REG(®s->tsf_timerhigh);
+
+ return;
+}
+
+static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
+{
+ d11regs_t *regs;
+ u32 w, val;
+ struct wiphy *wiphy = wlc_hw->wlc->wiphy;
+
+ BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
+
+ regs = wlc_hw->regs;
+
+ /* Validate dchip register access */
+
+ W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
+ (void)R_REG(®s->objaddr);
+ w = R_REG(®s->objdata);
+
+ /* Can we write and read back a 32bit register? */
+ W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
+ (void)R_REG(®s->objaddr);
+ W_REG(®s->objdata, (u32) 0xaa5555aa);
+
+ W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
+ (void)R_REG(®s->objaddr);
+ val = R_REG(®s->objdata);
+ if (val != (u32) 0xaa5555aa) {
+ wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
+ "expected 0xaa5555aa\n", wlc_hw->unit, val);
+ return false;
+ }
+
+ W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
+ (void)R_REG(®s->objaddr);
+ W_REG(®s->objdata, (u32) 0x55aaaa55);
+
+ W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
+ (void)R_REG(®s->objaddr);
+ val = R_REG(®s->objdata);
+ if (val != (u32) 0x55aaaa55) {
+ wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
+ "expected 0x55aaaa55\n", wlc_hw->unit, val);
+ return false;
+ }
+
+ W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
+ (void)R_REG(®s->objaddr);
+ W_REG(®s->objdata, w);
+
+ /* clear CFPStart */
+ W_REG(®s->tsf_cfpstart, 0);
+
+ w = R_REG(®s->maccontrol);
+ if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
+ (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
+ wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
+ "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
+ (MCTL_IHR_EN | MCTL_WAKE),
+ (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
+ return false;
+ }
+
+ return true;
+}
+
+#define PHYPLL_WAIT_US 100000
+
+void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
+{
+ d11regs_t *regs;
+ u32 tmp;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ tmp = 0;
+ regs = wlc_hw->regs;
+
+ if (on) {
+ if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
+ OR_REG(®s->clk_ctl_st,
+ (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
+ CCS_ERSRC_REQ_PHYPLL));
+ SPINWAIT((R_REG(®s->clk_ctl_st) &
+ (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
+ PHYPLL_WAIT_US);
+
+ tmp = R_REG(®s->clk_ctl_st);
+ if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
+ (CCS_ERSRC_AVAIL_HT)) {
+ wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
+ " PLL failed\n", __func__);
+ }
+ } else {
+ OR_REG(®s->clk_ctl_st,
+ (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
+ SPINWAIT((R_REG(®s->clk_ctl_st) &
+ (CCS_ERSRC_AVAIL_D11PLL |
+ CCS_ERSRC_AVAIL_PHYPLL)) !=
+ (CCS_ERSRC_AVAIL_D11PLL |
+ CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
+
+ tmp = R_REG(®s->clk_ctl_st);
+ if ((tmp &
+ (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
+ !=
+ (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
+ wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
+ "PHY PLL failed\n", __func__);
+ }
+ }
+ } else {
+ /* Since the PLL may be shared, other cores can still be requesting it;
+ * so we'll deassert the request but not wait for status to comply.
+ */
+ AND_REG(®s->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
+ tmp = R_REG(®s->clk_ctl_st);
+ }
+}
+
+void wlc_coredisable(struct wlc_hw_info *wlc_hw)
+{
+ bool dev_gone;
+
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
+
+ dev_gone = DEVICEREMOVED(wlc_hw->wlc);
+
+ if (dev_gone)
+ return;
+
+ if (wlc_hw->noreset)
+ return;
+
+ /* radio off */
+ wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
+
+ /* turn off analog core */
+ wlc_phy_anacore(wlc_hw->band->pi, OFF);
+
+ /* turn off PHYPLL to save power */
+ wlc_bmac_core_phypll_ctl(wlc_hw, false);
+
+ /* No need to set wlc->pub->radio_active = OFF
+ * because this function needs down capability and
+ * radio_active is designed for BCMNODOWN.
+ */
+
+ /* remove gpio controls */
+ if (wlc_hw->ucode_dbgsel)
+ ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
+
+ wlc_hw->clk = false;
+ ai_core_disable(wlc_hw->sih, 0);
+ wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
+}
+
+/* power both the pll and external oscillator on/off */
+static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
+{
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
+
+ /* dont power down if plldown is false or we must poll hw radio disable */
+ if (!want && wlc_hw->pllreq)
+ return;
+
+ if (wlc_hw->sih)
+ ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
+
+ wlc_hw->sbclk = want;
+ if (!wlc_hw->sbclk) {
+ wlc_hw->clk = false;
+ if (wlc_hw->band && wlc_hw->band->pi)
+ wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
+ }
+}
+
+static void wlc_flushqueues(struct wlc_info *wlc)
+{
+ struct wlc_hw_info *wlc_hw = wlc->hw;
+ uint i;
+
+ wlc->txpend16165war = 0;
+
+ /* free any posted tx packets */
+ for (i = 0; i < NFIFO; i++)
+ if (wlc_hw->di[i]) {
+ dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
+ TXPKTPENDCLR(wlc, i);
+ BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
+ }
+
+ /* free any posted rx packets */
+ dma_rxreclaim(wlc_hw->di[RX_FIFO]);
+}
+
+u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
+{
+ return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
+}
+
+void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
+{
+ wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
+}
+
+static u16
+wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
+{
+ d11regs_t *regs = wlc_hw->regs;
+ volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
+ volatile u16 *objdata_hi = objdata_lo + 1;
+ u16 v;
+
+ W_REG(®s->objaddr, sel | (offset >> 2));
+ (void)R_REG(®s->objaddr);
+ if (offset & 2) {
+ v = R_REG(objdata_hi);
+ } else {
+ v = R_REG(objdata_lo);
+ }
+
+ return v;
+}
+
+static void
+wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
+{
+ d11regs_t *regs = wlc_hw->regs;
+ volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
+ volatile u16 *objdata_hi = objdata_lo + 1;
+
+ W_REG(®s->objaddr, sel | (offset >> 2));
+ (void)R_REG(®s->objaddr);
+ if (offset & 2) {
+ W_REG(objdata_hi, v);
+ } else {
+ W_REG(objdata_lo, v);
+ }
+}
+
+/* Copy a buffer to shared memory of specified type .
+ * SHM 'offset' needs to be an even address and
+ * Buffer length 'len' must be an even number of bytes
+ * 'sel' selects the type of memory
+ */
+void
+wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
+ int len, u32 sel)
+{
+ u16 v;
+ const u8 *p = (const u8 *)buf;
+ int i;
+
+ if (len <= 0 || (offset & 1) || (len & 1))
+ return;
+
+ for (i = 0; i < len; i += 2) {
+ v = p[i] | (p[i + 1] << 8);
+ wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
+ }
+}
+
+/* Copy a piece of shared memory of specified type to a buffer .
+ * SHM 'offset' needs to be an even address and
+ * Buffer length 'len' must be an even number of bytes
+ * 'sel' selects the type of memory
+ */
+void
+wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
+ int len, u32 sel)
+{
+ u16 v;
+ u8 *p = (u8 *) buf;
+ int i;
+
+ if (len <= 0 || (offset & 1) || (len & 1))
+ return;
+
+ for (i = 0; i < len; i += 2) {
+ v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
+ p[i] = v & 0xFF;
+ p[i + 1] = (v >> 8) & 0xFF;
+ }
+}
+
+void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
+{
+ BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
+ wlc_hw->vars_size);
+
+ *buf = wlc_hw->vars;
+ *len = wlc_hw->vars_size;
+}
+
+void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
+{
+ wlc_hw->SRL = SRL;
+ wlc_hw->LRL = LRL;
+
+ /* write retry limit to SCR, shouldn't need to suspend */
+ if (wlc_hw->up) {
+ W_REG(&wlc_hw->regs->objaddr,
+ OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
+ (void)R_REG(&wlc_hw->regs->objaddr);
+ W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
+ W_REG(&wlc_hw->regs->objaddr,
+ OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
+ (void)R_REG(&wlc_hw->regs->objaddr);
+ W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
+ }
+}
+
+void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
+{
+ if (set) {
+ if (mboolisset(wlc_hw->pllreq, req_bit))
+ return;
+
+ mboolset(wlc_hw->pllreq, req_bit);
+
+ if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
+ if (!wlc_hw->sbclk) {
+ wlc_bmac_xtal(wlc_hw, ON);
+ }
+ }
+ } else {
+ if (!mboolisset(wlc_hw->pllreq, req_bit))
+ return;
+
+ mboolclr(wlc_hw->pllreq, req_bit);
+
+ if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
+ if (wlc_hw->sbclk) {
+ wlc_bmac_xtal(wlc_hw, OFF);
+ }
+ }
+ }
+
+ return;
+}
+
+u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
+{
+ u16 table_ptr;
+ u8 phy_rate, index;
+
+ /* get the phy specific rate encoding for the PLCP SIGNAL field */
+ /* XXX4321 fixup needed ? */
+ if (IS_OFDM(rate))
+ table_ptr = M_RT_DIRMAP_A;
+ else
+ table_ptr = M_RT_DIRMAP_B;
+
+ /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
+ * the index into the rate table.
+ */
+ phy_rate = rate_info[rate] & WLC_RATE_MASK;
+ index = phy_rate & 0xf;
+
+ /* Find the SHM pointer to the rate table entry by looking in the
+ * Direct-map Table
+ */
+ return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
+}
+
+void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
+{
+ wlc_hw->antsel_avail = antsel_avail;
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef _BRCM_BOTTOM_MAC_H_
+#define _BRCM_BOTTOM_MAC_H_
+
+/* dup state between BMAC(struct wlc_hw_info) and HIGH(struct wlc_info)
+ driver */
+typedef struct wlc_bmac_state {
+ u32 machwcap; /* mac hw capibility */
+ u32 preamble_ovr; /* preamble override */
+} wlc_bmac_state_t;
+
+enum {
+ IOV_BMAC_DIAG,
+ IOV_BMAC_SBGPIOTIMERVAL,
+ IOV_BMAC_SBGPIOOUT,
+ IOV_BMAC_CCGPIOCTRL, /* CC GPIOCTRL REG */
+ IOV_BMAC_CCGPIOOUT, /* CC GPIOOUT REG */
+ IOV_BMAC_CCGPIOOUTEN, /* CC GPIOOUTEN REG */
+ IOV_BMAC_CCGPIOIN, /* CC GPIOIN REG */
+ IOV_BMAC_WPSGPIO, /* WPS push button GPIO pin */
+ IOV_BMAC_OTPDUMP,
+ IOV_BMAC_OTPSTAT,
+ IOV_BMAC_PCIEASPM, /* obfuscation clkreq/aspm control */
+ IOV_BMAC_PCIEADVCORRMASK, /* advanced correctable error mask */
+ IOV_BMAC_PCIECLKREQ, /* PCIE 1.1 clockreq enab support */
+ IOV_BMAC_PCIELCREG, /* PCIE LCREG */
+ IOV_BMAC_SBGPIOTIMERMASK,
+ IOV_BMAC_RFDISABLEDLY,
+ IOV_BMAC_PCIEREG, /* PCIE REG */
+ IOV_BMAC_PCICFGREG, /* PCI Config register */
+ IOV_BMAC_PCIESERDESREG, /* PCIE SERDES REG (dev, 0}offset) */
+ IOV_BMAC_PCIEGPIOOUT, /* PCIEOUT REG */
+ IOV_BMAC_PCIEGPIOOUTEN, /* PCIEOUTEN REG */
+ IOV_BMAC_PCIECLKREQENCTRL, /* clkreqenctrl REG (PCIE REV > 6.0 */
+ IOV_BMAC_DMALPBK,
+ IOV_BMAC_CCREG,
+ IOV_BMAC_COREREG,
+ IOV_BMAC_SDCIS,
+ IOV_BMAC_SDIO_DRIVE,
+ IOV_BMAC_OTPW,
+ IOV_BMAC_NVOTPW,
+ IOV_BMAC_SROM,
+ IOV_BMAC_SRCRC,
+ IOV_BMAC_CIS_SOURCE,
+ IOV_BMAC_CISVAR,
+ IOV_BMAC_OTPLOCK,
+ IOV_BMAC_OTP_CHIPID,
+ IOV_BMAC_CUSTOMVAR1,
+ IOV_BMAC_BOARDFLAGS,
+ IOV_BMAC_BOARDFLAGS2,
+ IOV_BMAC_WPSLED,
+ IOV_BMAC_NVRAM_SOURCE,
+ IOV_BMAC_OTP_RAW_READ,
+ IOV_BMAC_LAST
+};
+
+extern int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device,
+ uint unit, bool piomode, void *regsva, uint bustype,
+ void *btparam);
+extern int wlc_bmac_detach(struct wlc_info *wlc);
+extern void wlc_bmac_watchdog(void *arg);
+
+/* up/down, reset, clk */
+extern void wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw,
+ uint offset, const void *buf, int len,
+ u32 sel);
+extern void wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset,
+ void *buf, int len, u32 sel);
+#define wlc_bmac_copyfrom_shm(wlc_hw, offset, buf, len) \
+ wlc_bmac_copyfrom_objmem(wlc_hw, offset, buf, len, OBJADDR_SHM_SEL)
+#define wlc_bmac_copyto_shm(wlc_hw, offset, buf, len) \
+ wlc_bmac_copyto_objmem(wlc_hw, offset, buf, len, OBJADDR_SHM_SEL)
+
+extern void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw);
+extern void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on);
+extern void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk);
+extern void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk);
+extern void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw);
+extern void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags);
+extern void wlc_bmac_reset(struct wlc_hw_info *wlc_hw);
+extern void wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
+ bool mute);
+extern int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw);
+extern int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw);
+extern int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw);
+extern int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw);
+extern void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode);
+
+/* chanspec, ucode interface */
+extern void wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw,
+ chanspec_t chanspec,
+ bool mute, struct txpwr_limits *txpwr);
+
+extern int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo,
+ uint *blocks);
+extern void wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask,
+ u16 val, int bands);
+extern void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val);
+extern u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands);
+extern void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant);
+extern u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw);
+extern void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw,
+ u8 antsel_type);
+extern int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw,
+ wlc_bmac_state_t *state);
+extern void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v);
+extern u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset);
+extern void wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset,
+ int len, void *buf);
+extern void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf,
+ uint *len);
+
+extern void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw,
+ u8 *ea);
+
+extern bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw);
+extern void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot);
+extern void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode);
+
+extern void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw);
+
+extern void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw,
+ u32 override_bit);
+extern void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw,
+ u32 override_bit);
+
+extern void wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw,
+ int match_reg_offset,
+ const u8 *addr);
+extern void wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw,
+ void *bcn, int len, bool both);
+
+extern void wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
+ u32 *tsf_h_ptr);
+extern void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin);
+extern void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax);
+
+extern void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL,
+ u16 LRL);
+
+extern void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw);
+
+
+/* API for BMAC driver (e.g. wlc_phy.c etc) */
+
+extern void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw);
+extern void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set,
+ mbool req_bit);
+extern void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw);
+extern u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate);
+extern void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail);
+
+#endif /* _BRCM_BOTTOM_MAC_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#define __UNDEF_NO_VERSION__
-
-#include <linux/kernel.h>
-#include <linux/etherdevice.h>
-#include <linux/types.h>
-#include <linux/pci_ids.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/sched.h>
-#include <linux/firmware.h>
-#include <net/mac80211.h>
-#include <bcmdefs.h>
-#include <brcmu_wifi.h>
-#include <brcmu_utils.h>
-#include <nicpci.h>
-#include "bcmdma.h"
-
-#include "phy/wlc_phy_int.h"
-#include "d11.h"
-#include "wlc_types.h"
-#include "wlc_cfg.h"
-#include "wlc_key.h"
-#include "wlc_channel.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "ucode_loader.h"
-#include "brcms_mac80211.h"
-
-#define N_TX_QUEUES 4 /* #tx queues on mac80211<->driver interface */
-
-#define LOCK(wl) spin_lock_bh(&(wl)->lock)
-#define UNLOCK(wl) spin_unlock_bh(&(wl)->lock)
-
-/* locking from inside brcms_isr */
-#define ISR_LOCK(wl, flags)\
- do {\
- spin_lock(&(wl)->isr_lock);\
- (void)(flags); } \
- while (0)
-
-#define ISR_UNLOCK(wl, flags)\
- do {\
- spin_unlock(&(wl)->isr_lock);\
- (void)(flags); } \
- while (0)
-
-/* locking under LOCK() to synchronize with brcms_isr */
-#define INT_LOCK(wl, flags) spin_lock_irqsave(&(wl)->isr_lock, flags)
-#define INT_UNLOCK(wl, flags) spin_unlock_irqrestore(&(wl)->isr_lock, flags)
-
-static void brcms_timer(unsigned long data);
-static void _brcms_timer(struct brcms_timer *t);
-
-
-static int ieee_hw_init(struct ieee80211_hw *hw);
-static int ieee_hw_rate_init(struct ieee80211_hw *hw);
-
-static int wl_linux_watchdog(void *ctx);
-
-/* Flags we support */
-#define MAC_FILTERS (FIF_PROMISC_IN_BSS | \
- FIF_ALLMULTI | \
- FIF_FCSFAIL | \
- FIF_PLCPFAIL | \
- FIF_CONTROL | \
- FIF_OTHER_BSS | \
- FIF_BCN_PRBRESP_PROMISC)
-
-static int n_adapters_found;
-
-static int brcms_request_fw(struct brcms_info *wl, struct pci_dev *pdev);
-static void brcms_release_fw(struct brcms_info *wl);
-
-/* local prototypes */
-static void brcms_dpc(unsigned long data);
-static irqreturn_t brcms_isr(int irq, void *dev_id);
-
-static int __devinit brcms_pci_probe(struct pci_dev *pdev,
- const struct pci_device_id *ent);
-static void brcms_remove(struct pci_dev *pdev);
-static void brcms_free(struct brcms_info *wl);
-static void brcms_set_basic_rate(struct wl_rateset *rs, u16 rate, bool is_br);
-
-MODULE_AUTHOR("Broadcom Corporation");
-MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver.");
-MODULE_SUPPORTED_DEVICE("Broadcom 802.11n WLAN cards");
-MODULE_LICENSE("Dual BSD/GPL");
-
-/* recognized PCI IDs */
-static DEFINE_PCI_DEVICE_TABLE(brcms_pci_id_table) = {
- {PCI_VENDOR_ID_BROADCOM, 0x4357, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, /* 43225 2G */
- {PCI_VENDOR_ID_BROADCOM, 0x4353, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, /* 43224 DUAL */
- {PCI_VENDOR_ID_BROADCOM, 0x4727, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, /* 4313 DUAL */
- /* 43224 Ven */
- {PCI_VENDOR_ID_BROADCOM, 0x0576, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
- {0}
-};
-
-MODULE_DEVICE_TABLE(pci, brcms_pci_id_table);
-
-#ifdef BCMDBG
-static int msglevel = 0xdeadbeef;
-module_param(msglevel, int, 0);
-static int phymsglevel = 0xdeadbeef;
-module_param(phymsglevel, int, 0);
-#endif /* BCMDBG */
-
-#define HW_TO_WL(hw) (hw->priv)
-#define WL_TO_HW(wl) (wl->pub->ieee_hw)
-
-/* MAC80211 callback functions */
-static int brcms_ops_start(struct ieee80211_hw *hw);
-static void brcms_ops_stop(struct ieee80211_hw *hw);
-static int brcms_ops_add_interface(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif);
-static void brcms_ops_remove_interface(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif);
-static int brcms_ops_config(struct ieee80211_hw *hw, u32 changed);
-static void brcms_ops_bss_info_changed(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_bss_conf *info,
- u32 changed);
-static void brcms_ops_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *total_flags, u64 multicast);
-static int brcms_ops_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
- bool set);
-static void brcms_ops_sw_scan_start(struct ieee80211_hw *hw);
-static void brcms_ops_sw_scan_complete(struct ieee80211_hw *hw);
-static void brcms_ops_set_tsf(struct ieee80211_hw *hw, u64 tsf);
-static int brcms_ops_get_stats(struct ieee80211_hw *hw,
- struct ieee80211_low_level_stats *stats);
-static void brcms_ops_sta_notify(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- enum sta_notify_cmd cmd,
- struct ieee80211_sta *sta);
-static int brcms_ops_conf_tx(struct ieee80211_hw *hw, u16 queue,
- const struct ieee80211_tx_queue_params *params);
-static u64 brcms_ops_get_tsf(struct ieee80211_hw *hw);
-static int brcms_ops_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
- struct ieee80211_sta *sta);
-static int brcms_ops_sta_remove(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_sta *sta);
-static int brcms_ops_ampdu_action(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- enum ieee80211_ampdu_mlme_action action,
- struct ieee80211_sta *sta, u16 tid, u16 *ssn,
- u8 buf_size);
-static void brcms_ops_rfkill_poll(struct ieee80211_hw *hw);
-static void brcms_ops_flush(struct ieee80211_hw *hw, bool drop);
-
-static void brcms_ops_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
- struct brcms_info *wl = hw->priv;
-
- LOCK(wl);
- if (!wl->pub->up) {
- wiphy_err(wl->wiphy, "ops->tx called while down\n");
- kfree_skb(skb);
- goto done;
- }
- wlc_sendpkt_mac80211(wl->wlc, skb, hw);
- done:
- UNLOCK(wl);
-}
-
-static int brcms_ops_start(struct ieee80211_hw *hw)
-{
- struct brcms_info *wl = hw->priv;
- bool blocked;
- /*
- struct ieee80211_channel *curchan = hw->conf.channel;
- */
-
- ieee80211_wake_queues(hw);
- LOCK(wl);
- blocked = brcms_rfkill_set_hw_state(wl);
- UNLOCK(wl);
- if (!blocked)
- wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy);
-
- return 0;
-}
-
-static void brcms_ops_stop(struct ieee80211_hw *hw)
-{
- ieee80211_stop_queues(hw);
-}
-
-static int
-brcms_ops_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
-{
- struct brcms_info *wl;
- int err;
-
- /* Just STA for now */
- if (vif->type != NL80211_IFTYPE_AP &&
- vif->type != NL80211_IFTYPE_MESH_POINT &&
- vif->type != NL80211_IFTYPE_STATION &&
- vif->type != NL80211_IFTYPE_WDS &&
- vif->type != NL80211_IFTYPE_ADHOC) {
- wiphy_err(hw->wiphy, "%s: Attempt to add type %d, only"
- " STA for now\n", __func__, vif->type);
- return -EOPNOTSUPP;
- }
-
- wl = HW_TO_WL(hw);
- LOCK(wl);
- err = brcms_up(wl);
- UNLOCK(wl);
-
- if (err != 0) {
- wiphy_err(hw->wiphy, "%s: brcms_up() returned %d\n", __func__,
- err);
- }
- return err;
-}
-
-static void
-brcms_ops_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
-{
- struct brcms_info *wl;
-
- wl = HW_TO_WL(hw);
-
- /* put driver in down state */
- LOCK(wl);
- brcms_down(wl);
- UNLOCK(wl);
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-static int
-ieee_set_channel(struct ieee80211_hw *hw, struct ieee80211_channel *chan,
- enum nl80211_channel_type type)
-{
- struct brcms_info *wl = HW_TO_WL(hw);
- int err = 0;
-
- switch (type) {
- case NL80211_CHAN_HT20:
- case NL80211_CHAN_NO_HT:
- err = wlc_set(wl->wlc, WLC_SET_CHANNEL, chan->hw_value);
- break;
- case NL80211_CHAN_HT40MINUS:
- case NL80211_CHAN_HT40PLUS:
- wiphy_err(hw->wiphy,
- "%s: Need to implement 40 Mhz Channels!\n", __func__);
- err = 1;
- break;
- }
-
- if (err)
- return -EIO;
- return err;
-}
-
-static int brcms_ops_config(struct ieee80211_hw *hw, u32 changed)
-{
- struct ieee80211_conf *conf = &hw->conf;
- struct brcms_info *wl = HW_TO_WL(hw);
- int err = 0;
- int new_int;
- struct wiphy *wiphy = hw->wiphy;
-
- LOCK(wl);
- if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) {
- if (wlc_set_par(wl->wlc, IOV_BCN_LI_BCN, conf->listen_interval)
- < 0) {
- wiphy_err(wiphy, "%s: Error setting listen_interval\n",
- __func__);
- err = -EIO;
- goto config_out;
- }
- wlc_get_par(wl->wlc, IOV_BCN_LI_BCN, &new_int);
- }
- if (changed & IEEE80211_CONF_CHANGE_MONITOR)
- wiphy_err(wiphy, "%s: change monitor mode: %s (implement)\n",
- __func__, conf->flags & IEEE80211_CONF_MONITOR ?
- "true" : "false");
- if (changed & IEEE80211_CONF_CHANGE_PS)
- wiphy_err(wiphy, "%s: change power-save mode: %s (implement)\n",
- __func__, conf->flags & IEEE80211_CONF_PS ?
- "true" : "false");
-
- if (changed & IEEE80211_CONF_CHANGE_POWER) {
- if (wlc_set_par(wl->wlc, IOV_QTXPOWER, conf->power_level * 4)
- < 0) {
- wiphy_err(wiphy, "%s: Error setting power_level\n",
- __func__);
- err = -EIO;
- goto config_out;
- }
- wlc_get_par(wl->wlc, IOV_QTXPOWER, &new_int);
- if (new_int != (conf->power_level * 4))
- wiphy_err(wiphy, "%s: Power level req != actual, %d %d"
- "\n", __func__, conf->power_level * 4,
- new_int);
- }
- if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
- err = ieee_set_channel(hw, conf->channel, conf->channel_type);
- }
- if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
- if (wlc_set
- (wl->wlc, WLC_SET_SRL,
- conf->short_frame_max_tx_count) < 0) {
- wiphy_err(wiphy, "%s: Error setting srl\n", __func__);
- err = -EIO;
- goto config_out;
- }
- if (wlc_set(wl->wlc, WLC_SET_LRL, conf->long_frame_max_tx_count)
- < 0) {
- wiphy_err(wiphy, "%s: Error setting lrl\n", __func__);
- err = -EIO;
- goto config_out;
- }
- }
-
- config_out:
- UNLOCK(wl);
- return err;
-}
-
-static void
-brcms_ops_bss_info_changed(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- struct ieee80211_bss_conf *info, u32 changed)
-{
- struct brcms_info *wl = HW_TO_WL(hw);
- struct wiphy *wiphy = hw->wiphy;
- int val;
-
- if (changed & BSS_CHANGED_ASSOC) {
- /* association status changed (associated/disassociated)
- * also implies a change in the AID.
- */
- wiphy_err(wiphy, "%s: %s: %sassociated\n", KBUILD_MODNAME,
- __func__, info->assoc ? "" : "dis");
- LOCK(wl);
- wlc_associate_upd(wl->wlc, info->assoc);
- UNLOCK(wl);
- }
- if (changed & BSS_CHANGED_ERP_SLOT) {
- /* slot timing changed */
- if (info->use_short_slot)
- val = 1;
- else
- val = 0;
- LOCK(wl);
- wlc_set(wl->wlc, WLC_SET_SHORTSLOT_OVERRIDE, val);
- UNLOCK(wl);
- }
-
- if (changed & BSS_CHANGED_HT) {
- /* 802.11n parameters changed */
- u16 mode = info->ht_operation_mode;
-
- LOCK(wl);
- wlc_protection_upd(wl->wlc, WLC_PROT_N_CFG,
- mode & IEEE80211_HT_OP_MODE_PROTECTION);
- wlc_protection_upd(wl->wlc, WLC_PROT_N_NONGF,
- mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
- wlc_protection_upd(wl->wlc, WLC_PROT_N_OBSS,
- mode & IEEE80211_HT_OP_MODE_NON_HT_STA_PRSNT);
- UNLOCK(wl);
- }
- if (changed & BSS_CHANGED_BASIC_RATES) {
- struct ieee80211_supported_band *bi;
- u32 br_mask, i;
- u16 rate;
- struct wl_rateset rs;
- int error;
-
- /* retrieve the current rates */
- LOCK(wl);
- error = wlc_ioctl(wl->wlc, WLC_GET_CURR_RATESET,
- &rs, sizeof(rs), NULL);
- UNLOCK(wl);
- if (error) {
- wiphy_err(wiphy, "%s: retrieve rateset failed: %d\n",
- __func__, error);
- return;
- }
- br_mask = info->basic_rates;
- bi = hw->wiphy->bands[wlc_get_curband(wl->wlc)];
- for (i = 0; i < bi->n_bitrates; i++) {
- /* convert to internal rate value */
- rate = (bi->bitrates[i].bitrate << 1) / 10;
-
- /* set/clear basic rate flag */
- brcms_set_basic_rate(&rs, rate, br_mask & 1);
- br_mask >>= 1;
- }
-
- /* update the rate set */
- LOCK(wl);
- wlc_ioctl(wl->wlc, WLC_SET_RATESET, &rs, sizeof(rs), NULL);
- UNLOCK(wl);
- }
- if (changed & BSS_CHANGED_BEACON_INT) {
- /* Beacon interval changed */
- LOCK(wl);
- wlc_set(wl->wlc, WLC_SET_BCNPRD, info->beacon_int);
- UNLOCK(wl);
- }
- if (changed & BSS_CHANGED_BSSID) {
- /* BSSID changed, for whatever reason (IBSS and managed mode) */
- LOCK(wl);
- wlc_set_addrmatch(wl->wlc, RCM_BSSID_OFFSET,
- info->bssid);
- UNLOCK(wl);
- }
- if (changed & BSS_CHANGED_BEACON) {
- /* Beacon data changed, retrieve new beacon (beaconing modes) */
- wiphy_err(wiphy, "%s: beacon changed\n", __func__);
- }
- if (changed & BSS_CHANGED_BEACON_ENABLED) {
- /* Beaconing should be enabled/disabled (beaconing modes) */
- wiphy_err(wiphy, "%s: Beacon enabled: %s\n", __func__,
- info->enable_beacon ? "true" : "false");
- }
- if (changed & BSS_CHANGED_CQM) {
- /* Connection quality monitor config changed */
- wiphy_err(wiphy, "%s: cqm change: threshold %d, hys %d "
- " (implement)\n", __func__, info->cqm_rssi_thold,
- info->cqm_rssi_hyst);
- }
- if (changed & BSS_CHANGED_IBSS) {
- /* IBSS join status changed */
- wiphy_err(wiphy, "%s: IBSS joined: %s (implement)\n", __func__,
- info->ibss_joined ? "true" : "false");
- }
- if (changed & BSS_CHANGED_ARP_FILTER) {
- /* Hardware ARP filter address list or state changed */
- wiphy_err(wiphy, "%s: arp filtering: enabled %s, count %d"
- " (implement)\n", __func__, info->arp_filter_enabled ?
- "true" : "false", info->arp_addr_cnt);
- }
- if (changed & BSS_CHANGED_QOS) {
- /*
- * QoS for this association was enabled/disabled.
- * Note that it is only ever disabled for station mode.
- */
- wiphy_err(wiphy, "%s: qos enabled: %s (implement)\n", __func__,
- info->qos ? "true" : "false");
- }
- if (changed & BSS_CHANGED_IDLE) {
- /* Idle changed for this BSS/interface */
- wiphy_err(wiphy, "%s: BSS idle: %s (implement)\n", __func__,
- info->idle ? "true" : "false");
- }
- return;
-}
-
-static void
-brcms_ops_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *total_flags, u64 multicast)
-{
- struct brcms_info *wl = hw->priv;
- struct wiphy *wiphy = hw->wiphy;
-
- changed_flags &= MAC_FILTERS;
- *total_flags &= MAC_FILTERS;
- if (changed_flags & FIF_PROMISC_IN_BSS)
- wiphy_err(wiphy, "FIF_PROMISC_IN_BSS\n");
- if (changed_flags & FIF_ALLMULTI)
- wiphy_err(wiphy, "FIF_ALLMULTI\n");
- if (changed_flags & FIF_FCSFAIL)
- wiphy_err(wiphy, "FIF_FCSFAIL\n");
- if (changed_flags & FIF_PLCPFAIL)
- wiphy_err(wiphy, "FIF_PLCPFAIL\n");
- if (changed_flags & FIF_CONTROL)
- wiphy_err(wiphy, "FIF_CONTROL\n");
- if (changed_flags & FIF_OTHER_BSS)
- wiphy_err(wiphy, "FIF_OTHER_BSS\n");
- if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
- LOCK(wl);
- if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
- wl->pub->mac80211_state |= MAC80211_PROMISC_BCNS;
- wlc_mac_bcn_promisc_change(wl->wlc, 1);
- } else {
- wlc_mac_bcn_promisc_change(wl->wlc, 0);
- wl->pub->mac80211_state &= ~MAC80211_PROMISC_BCNS;
- }
- UNLOCK(wl);
- }
- return;
-}
-
-static int
-brcms_ops_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set)
-{
- return 0;
-}
-
-static void brcms_ops_sw_scan_start(struct ieee80211_hw *hw)
-{
- struct brcms_info *wl = hw->priv;
- LOCK(wl);
- wlc_scan_start(wl->wlc);
- UNLOCK(wl);
- return;
-}
-
-static void brcms_ops_sw_scan_complete(struct ieee80211_hw *hw)
-{
- struct brcms_info *wl = hw->priv;
- LOCK(wl);
- wlc_scan_stop(wl->wlc);
- UNLOCK(wl);
- return;
-}
-
-static void brcms_ops_set_tsf(struct ieee80211_hw *hw, u64 tsf)
-{
- wiphy_err(hw->wiphy, "%s: Enter\n", __func__);
- return;
-}
-
-static int
-brcms_ops_get_stats(struct ieee80211_hw *hw,
- struct ieee80211_low_level_stats *stats)
-{
- struct brcms_info *wl = hw->priv;
- struct wl_cnt *cnt;
-
- LOCK(wl);
- cnt = wl->pub->_cnt;
- stats->dot11ACKFailureCount = 0;
- stats->dot11RTSFailureCount = 0;
- stats->dot11FCSErrorCount = 0;
- stats->dot11RTSSuccessCount = 0;
- UNLOCK(wl);
- return 0;
-}
-
-static void
-brcms_ops_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
- enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
-{
- switch (cmd) {
- default:
- wiphy_err(hw->wiphy, "%s: Unknown cmd = %d\n", __func__,
- cmd);
- break;
- }
- return;
-}
-
-static int
-brcms_ops_conf_tx(struct ieee80211_hw *hw, u16 queue,
- const struct ieee80211_tx_queue_params *params)
-{
- struct brcms_info *wl = hw->priv;
-
- LOCK(wl);
- wlc_wme_setparams(wl->wlc, queue, params, true);
- UNLOCK(wl);
-
- return 0;
-}
-
-static u64 brcms_ops_get_tsf(struct ieee80211_hw *hw)
-{
- wiphy_err(hw->wiphy, "%s: Enter\n", __func__);
- return 0;
-}
-
-static int
-brcms_ops_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
- struct ieee80211_sta *sta)
-{
- struct scb *scb;
-
- int i;
- struct brcms_info *wl = hw->priv;
-
- /* Init the scb */
- scb = (struct scb *)sta->drv_priv;
- memset(scb, 0, sizeof(struct scb));
- for (i = 0; i < NUMPRIO; i++)
- scb->seqctl[i] = 0xFFFF;
- scb->seqctl_nonqos = 0xFFFF;
- scb->magic = SCB_MAGIC;
-
- wl->pub->global_scb = scb;
- wl->pub->global_ampdu = &(scb->scb_ampdu);
- wl->pub->global_ampdu->scb = scb;
- wl->pub->global_ampdu->max_pdu = 16;
- brcmu_pktq_init(&scb->scb_ampdu.txq, AMPDU_MAX_SCB_TID,
- AMPDU_MAX_SCB_TID * PKTQ_LEN_DEFAULT);
-
- sta->ht_cap.ht_supported = true;
- sta->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
- sta->ht_cap.ampdu_density = AMPDU_DEF_MPDU_DENSITY;
- sta->ht_cap.cap = IEEE80211_HT_CAP_GRN_FLD |
- IEEE80211_HT_CAP_SGI_20 |
- IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT;
-
- /* minstrel_ht initiates addBA on our behalf by calling ieee80211_start_tx_ba_session() */
- return 0;
-}
-
-static int
-brcms_ops_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
- struct ieee80211_sta *sta)
-{
- return 0;
-}
-
-static int
-brcms_ops_ampdu_action(struct ieee80211_hw *hw,
- struct ieee80211_vif *vif,
- enum ieee80211_ampdu_mlme_action action,
- struct ieee80211_sta *sta, u16 tid, u16 *ssn,
- u8 buf_size)
-{
- struct scb *scb = (struct scb *)sta->drv_priv;
- struct brcms_info *wl = hw->priv;
- int status;
-
- if (WARN_ON(scb->magic != SCB_MAGIC))
- return -EIDRM;
- switch (action) {
- case IEEE80211_AMPDU_RX_START:
- break;
- case IEEE80211_AMPDU_RX_STOP:
- break;
- case IEEE80211_AMPDU_TX_START:
- LOCK(wl);
- status = wlc_aggregatable(wl->wlc, tid);
- UNLOCK(wl);
- if (!status) {
- wiphy_err(wl->wiphy, "START: tid %d is not agg\'able\n",
- tid);
- return -EINVAL;
- }
- /* XXX: Use the starting sequence number provided ... */
- *ssn = 0;
- ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
- break;
-
- case IEEE80211_AMPDU_TX_STOP:
- LOCK(wl);
- wlc_ampdu_flush(wl->wlc, sta, tid);
- UNLOCK(wl);
- ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
- break;
- case IEEE80211_AMPDU_TX_OPERATIONAL:
- /* Not sure what to do here */
- /* Power save wakeup */
- break;
- default:
- wiphy_err(wl->wiphy, "%s: Invalid command, ignoring\n",
- __func__);
- }
-
- return 0;
-}
-
-static void brcms_ops_rfkill_poll(struct ieee80211_hw *hw)
-{
- struct brcms_info *wl = HW_TO_WL(hw);
- bool blocked;
-
- LOCK(wl);
- blocked = wlc_check_radio_disabled(wl->wlc);
- UNLOCK(wl);
-
- wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, blocked);
-}
-
-static void brcms_ops_flush(struct ieee80211_hw *hw, bool drop)
-{
- struct brcms_info *wl = HW_TO_WL(hw);
-
- no_printk("%s: drop = %s\n", __func__, drop ? "true" : "false");
-
- /* wait for packet queue and dma fifos to run empty */
- LOCK(wl);
- wlc_wait_for_tx_completion(wl->wlc, drop);
- UNLOCK(wl);
-}
-
-static const struct ieee80211_ops brcms_ops = {
- .tx = brcms_ops_tx,
- .start = brcms_ops_start,
- .stop = brcms_ops_stop,
- .add_interface = brcms_ops_add_interface,
- .remove_interface = brcms_ops_remove_interface,
- .config = brcms_ops_config,
- .bss_info_changed = brcms_ops_bss_info_changed,
- .configure_filter = brcms_ops_configure_filter,
- .set_tim = brcms_ops_set_tim,
- .sw_scan_start = brcms_ops_sw_scan_start,
- .sw_scan_complete = brcms_ops_sw_scan_complete,
- .set_tsf = brcms_ops_set_tsf,
- .get_stats = brcms_ops_get_stats,
- .sta_notify = brcms_ops_sta_notify,
- .conf_tx = brcms_ops_conf_tx,
- .get_tsf = brcms_ops_get_tsf,
- .sta_add = brcms_ops_sta_add,
- .sta_remove = brcms_ops_sta_remove,
- .ampdu_action = brcms_ops_ampdu_action,
- .rfkill_poll = brcms_ops_rfkill_poll,
- .flush = brcms_ops_flush,
-};
-
-/*
- * is called in brcms_pci_probe() context, therefore no locking required.
- */
-static int brcms_set_hint(struct brcms_info *wl, char *abbrev)
-{
- return regulatory_hint(wl->pub->ieee_hw->wiphy, abbrev);
-}
-
-/**
- * attach to the WL device.
- *
- * Attach to the WL device identified by vendor and device parameters.
- * regs is a host accessible memory address pointing to WL device registers.
- *
- * brcms_attach is not defined as static because in the case where no bus
- * is defined, wl_attach will never be called, and thus, gcc will issue
- * a warning that this function is defined but not used if we declare
- * it as static.
- *
- *
- * is called in brcms_pci_probe() context, therefore no locking required.
- */
-static struct brcms_info *brcms_attach(u16 vendor, u16 device,
- unsigned long regs,
- uint bustype, void *btparam, uint irq)
-{
- struct brcms_info *wl = NULL;
- int unit, err;
- unsigned long base_addr;
- struct ieee80211_hw *hw;
- u8 perm[ETH_ALEN];
-
- unit = n_adapters_found;
- err = 0;
-
- if (unit < 0) {
- return NULL;
- }
-
- /* allocate private info */
- hw = pci_get_drvdata(btparam); /* btparam == pdev */
- if (hw != NULL)
- wl = hw->priv;
- if (WARN_ON(hw == NULL) || WARN_ON(wl == NULL))
- return NULL;
- wl->wiphy = hw->wiphy;
-
- atomic_set(&wl->callbacks, 0);
-
- /* setup the bottom half handler */
- tasklet_init(&wl->tasklet, brcms_dpc, (unsigned long) wl);
-
-
-
- base_addr = regs;
-
- if (bustype == PCI_BUS || bustype == RPC_BUS) {
- /* Do nothing */
- } else {
- bustype = PCI_BUS;
- BCMMSG(wl->wiphy, "force to PCI\n");
- }
- wl->bcm_bustype = bustype;
-
- wl->regsva = ioremap_nocache(base_addr, PCI_BAR0_WINSZ);
- if (wl->regsva == NULL) {
- wiphy_err(wl->wiphy, "wl%d: ioremap() failed\n", unit);
- goto fail;
- }
- spin_lock_init(&wl->lock);
- spin_lock_init(&wl->isr_lock);
-
- /* prepare ucode */
- if (brcms_request_fw(wl, (struct pci_dev *)btparam) < 0) {
- wiphy_err(wl->wiphy, "%s: Failed to find firmware usually in "
- "%s\n", KBUILD_MODNAME, "/lib/firmware/brcm");
- brcms_release_fw(wl);
- brcms_remove((struct pci_dev *)btparam);
- return NULL;
- }
-
- /* common load-time initialization */
- wl->wlc = wlc_attach((void *)wl, vendor, device, unit, false,
- wl->regsva, wl->bcm_bustype, btparam, &err);
- brcms_release_fw(wl);
- if (!wl->wlc) {
- wiphy_err(wl->wiphy, "%s: wlc_attach() failed with code %d\n",
- KBUILD_MODNAME, err);
- goto fail;
- }
- wl->pub = wlc_pub(wl->wlc);
-
- wl->pub->ieee_hw = hw;
-
- if (wlc_set_par(wl->wlc, IOV_MPC, 0) < 0) {
- wiphy_err(wl->wiphy, "wl%d: Error setting MPC variable to 0\n",
- unit);
- }
-
- /* register our interrupt handler */
- if (request_irq(irq, brcms_isr, IRQF_SHARED, KBUILD_MODNAME, wl)) {
- wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit);
- goto fail;
- }
- wl->irq = irq;
-
- /* register module */
- wlc_module_register(wl->pub, "linux", wl, wl_linux_watchdog, NULL);
-
- if (ieee_hw_init(hw)) {
- wiphy_err(wl->wiphy, "wl%d: %s: ieee_hw_init failed!\n", unit,
- __func__);
- goto fail;
- }
-
- memcpy(perm, &wl->pub->cur_etheraddr, ETH_ALEN);
- if (WARN_ON(!is_valid_ether_addr(perm)))
- goto fail;
- SET_IEEE80211_PERM_ADDR(hw, perm);
-
- err = ieee80211_register_hw(hw);
- if (err) {
- wiphy_err(wl->wiphy, "%s: ieee80211_register_hw failed, status"
- "%d\n", __func__, err);
- }
-
- if (wl->pub->srom_ccode[0])
- err = brcms_set_hint(wl, wl->pub->srom_ccode);
- else
- err = brcms_set_hint(wl, "US");
- if (err) {
- wiphy_err(wl->wiphy, "%s: regulatory_hint failed, status %d\n",
- __func__, err);
- }
-
- n_adapters_found++;
- return wl;
-
-fail:
- brcms_free(wl);
- return NULL;
-}
-
-
-
-#define CHAN2GHZ(channel, freqency, chflags) { \
- .band = IEEE80211_BAND_2GHZ, \
- .center_freq = (freqency), \
- .hw_value = (channel), \
- .flags = chflags, \
- .max_antenna_gain = 0, \
- .max_power = 19, \
-}
-
-static struct ieee80211_channel brcms_2ghz_chantable[] = {
- CHAN2GHZ(1, 2412, IEEE80211_CHAN_NO_HT40MINUS),
- CHAN2GHZ(2, 2417, IEEE80211_CHAN_NO_HT40MINUS),
- CHAN2GHZ(3, 2422, IEEE80211_CHAN_NO_HT40MINUS),
- CHAN2GHZ(4, 2427, IEEE80211_CHAN_NO_HT40MINUS),
- CHAN2GHZ(5, 2432, 0),
- CHAN2GHZ(6, 2437, 0),
- CHAN2GHZ(7, 2442, 0),
- CHAN2GHZ(8, 2447, IEEE80211_CHAN_NO_HT40PLUS),
- CHAN2GHZ(9, 2452, IEEE80211_CHAN_NO_HT40PLUS),
- CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
- CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
- CHAN2GHZ(12, 2467,
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_NO_HT40PLUS),
- CHAN2GHZ(13, 2472,
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_NO_HT40PLUS),
- CHAN2GHZ(14, 2484,
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS)
-};
-
-#define CHAN5GHZ(channel, chflags) { \
- .band = IEEE80211_BAND_5GHZ, \
- .center_freq = 5000 + 5*(channel), \
- .hw_value = (channel), \
- .flags = chflags, \
- .max_antenna_gain = 0, \
- .max_power = 21, \
-}
-
-static struct ieee80211_channel brcms_5ghz_nphy_chantable[] = {
- /* UNII-1 */
- CHAN5GHZ(36, IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(40, IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(44, IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
- /* UNII-2 */
- CHAN5GHZ(52,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(56,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(60,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(64,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
- /* MID */
- CHAN5GHZ(100,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(104,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(108,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(112,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(116,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(120,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(124,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(128,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(132,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(136,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(140,
- IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
- IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
- IEEE80211_CHAN_NO_HT40MINUS),
- /* UNII-3 */
- CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(153, IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(157, IEEE80211_CHAN_NO_HT40MINUS),
- CHAN5GHZ(161, IEEE80211_CHAN_NO_HT40PLUS),
- CHAN5GHZ(165, IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS)
-};
-
-#define RATE(rate100m, _flags) { \
- .bitrate = (rate100m), \
- .flags = (_flags), \
- .hw_value = (rate100m / 5), \
-}
-
-static struct ieee80211_rate legacy_ratetable[] = {
- RATE(10, 0),
- RATE(20, IEEE80211_RATE_SHORT_PREAMBLE),
- RATE(55, IEEE80211_RATE_SHORT_PREAMBLE),
- RATE(110, IEEE80211_RATE_SHORT_PREAMBLE),
- RATE(60, 0),
- RATE(90, 0),
- RATE(120, 0),
- RATE(180, 0),
- RATE(240, 0),
- RATE(360, 0),
- RATE(480, 0),
- RATE(540, 0),
-};
-
-static struct ieee80211_supported_band brcms_band_2GHz_nphy = {
- .band = IEEE80211_BAND_2GHZ,
- .channels = brcms_2ghz_chantable,
- .n_channels = ARRAY_SIZE(brcms_2ghz_chantable),
- .bitrates = legacy_ratetable,
- .n_bitrates = ARRAY_SIZE(legacy_ratetable),
- .ht_cap = {
- /* from include/linux/ieee80211.h */
- .cap = IEEE80211_HT_CAP_GRN_FLD |
- IEEE80211_HT_CAP_SGI_20 |
- IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT,
- .ht_supported = true,
- .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
- .ampdu_density = AMPDU_DEF_MPDU_DENSITY,
- .mcs = {
- /* placeholders for now */
- .rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
- .rx_highest = 500,
- .tx_params = IEEE80211_HT_MCS_TX_DEFINED}
- }
-};
-
-static struct ieee80211_supported_band brcms_band_5GHz_nphy = {
- .band = IEEE80211_BAND_5GHZ,
- .channels = brcms_5ghz_nphy_chantable,
- .n_channels = ARRAY_SIZE(brcms_5ghz_nphy_chantable),
- .bitrates = legacy_ratetable + 4,
- .n_bitrates = ARRAY_SIZE(legacy_ratetable) - 4,
- .ht_cap = {
- /* use IEEE80211_HT_CAP_* from include/linux/ieee80211.h */
- .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT, /* No 40 mhz yet */
- .ht_supported = true,
- .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
- .ampdu_density = AMPDU_DEF_MPDU_DENSITY,
- .mcs = {
- /* placeholders for now */
- .rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
- .rx_highest = 500,
- .tx_params = IEEE80211_HT_MCS_TX_DEFINED}
- }
-};
-
-/*
- * is called in brcms_pci_probe() context, therefore no locking required.
- */
-static int ieee_hw_rate_init(struct ieee80211_hw *hw)
-{
- struct brcms_info *wl = HW_TO_WL(hw);
- int has_5g;
- char phy_list[4];
-
- has_5g = 0;
-
- hw->wiphy->bands[IEEE80211_BAND_2GHZ] = NULL;
- hw->wiphy->bands[IEEE80211_BAND_5GHZ] = NULL;
-
- if (wlc_get(wl->wlc, WLC_GET_PHYLIST, (int *)&phy_list) < 0) {
- wiphy_err(hw->wiphy, "Phy list failed\n");
- }
-
- if (phy_list[0] == 'n' || phy_list[0] == 'c') {
- if (phy_list[0] == 'c') {
- /* Single stream */
- brcms_band_2GHz_nphy.ht_cap.mcs.rx_mask[1] = 0;
- brcms_band_2GHz_nphy.ht_cap.mcs.rx_highest = 72;
- }
- hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &brcms_band_2GHz_nphy;
- } else {
- return -EPERM;
- }
-
- /* Assume all bands use the same phy. True for 11n devices. */
- if (NBANDS_PUB(wl->pub) > 1) {
- has_5g++;
- if (phy_list[0] == 'n' || phy_list[0] == 'c') {
- hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
- &brcms_band_5GHz_nphy;
- } else {
- return -EPERM;
- }
- }
- return 0;
-}
-
-/*
- * is called in brcms_pci_probe() context, therefore no locking required.
- */
-static int ieee_hw_init(struct ieee80211_hw *hw)
-{
- hw->flags = IEEE80211_HW_SIGNAL_DBM
- /* | IEEE80211_HW_CONNECTION_MONITOR What is this? */
- | IEEE80211_HW_REPORTS_TX_ACK_STATUS
- | IEEE80211_HW_AMPDU_AGGREGATION;
-
- hw->extra_tx_headroom = wlc_get_header_len();
- hw->queues = N_TX_QUEUES;
- /* FIXME: this doesn't seem to be used properly in minstrel_ht.
- * mac80211/status.c:ieee80211_tx_status() checks this value,
- * but mac80211/rc80211_minstrel_ht.c:minstrel_ht_get_rate()
- * appears to always set 3 rates
- */
- hw->max_rates = 2; /* Primary rate and 1 fallback rate */
-
- hw->channel_change_time = 7 * 1000; /* channel change time is dependent on chip and band */
- hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
-
- hw->rate_control_algorithm = "minstrel_ht";
-
- hw->sta_data_size = sizeof(struct scb);
- return ieee_hw_rate_init(hw);
-}
-
-/**
- * determines if a device is a WL device, and if so, attaches it.
- *
- * This function determines if a device pointed to by pdev is a WL device,
- * and if so, performs a brcms_attach() on it.
- *
- * Perimeter lock is initialized in the course of this function.
- */
-static int __devinit
-brcms_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
-{
- int rc;
- struct brcms_info *wl;
- struct ieee80211_hw *hw;
- u32 val;
-
- dev_info(&pdev->dev, "bus %d slot %d func %d irq %d\n",
- pdev->bus->number, PCI_SLOT(pdev->devfn),
- PCI_FUNC(pdev->devfn), pdev->irq);
-
- if ((pdev->vendor != PCI_VENDOR_ID_BROADCOM) ||
- ((pdev->device != 0x0576) &&
- ((pdev->device & 0xff00) != 0x4300) &&
- ((pdev->device & 0xff00) != 0x4700) &&
- ((pdev->device < 43000) || (pdev->device > 43999))))
- return -ENODEV;
-
- rc = pci_enable_device(pdev);
- if (rc) {
- pr_err("%s: Cannot enable device %d-%d_%d\n",
- __func__, pdev->bus->number, PCI_SLOT(pdev->devfn),
- PCI_FUNC(pdev->devfn));
- return -ENODEV;
- }
- pci_set_master(pdev);
-
- pci_read_config_dword(pdev, 0x40, &val);
- if ((val & 0x0000ff00) != 0)
- pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
-
- hw = ieee80211_alloc_hw(sizeof(struct brcms_info), &brcms_ops);
- if (!hw) {
- pr_err("%s: ieee80211_alloc_hw failed\n", __func__);
- return -ENOMEM;
- }
-
- SET_IEEE80211_DEV(hw, &pdev->dev);
-
- pci_set_drvdata(pdev, hw);
-
- memset(hw->priv, 0, sizeof(*wl));
-
- wl = brcms_attach(pdev->vendor, pdev->device,
- pci_resource_start(pdev, 0), PCI_BUS, pdev,
- pdev->irq);
-
- if (!wl) {
- pr_err("%s: %s: brcms_attach failed!\n", KBUILD_MODNAME,
- __func__);
- return -ENODEV;
- }
- return 0;
-}
-
-static int brcms_suspend(struct pci_dev *pdev, pm_message_t state)
-{
- struct brcms_info *wl;
- struct ieee80211_hw *hw;
-
- hw = pci_get_drvdata(pdev);
- wl = HW_TO_WL(hw);
- if (!wl) {
- wiphy_err(wl->wiphy,
- "brcms_suspend: pci_get_drvdata failed\n");
- return -ENODEV;
- }
-
- /* only need to flag hw is down for proper resume */
- LOCK(wl);
- wl->pub->hw_up = false;
- UNLOCK(wl);
-
- pci_save_state(pdev);
- pci_disable_device(pdev);
- return pci_set_power_state(pdev, PCI_D3hot);
-}
-
-static int brcms_resume(struct pci_dev *pdev)
-{
- struct brcms_info *wl;
- struct ieee80211_hw *hw;
- int err = 0;
- u32 val;
-
- hw = pci_get_drvdata(pdev);
- wl = HW_TO_WL(hw);
- if (!wl) {
- wiphy_err(wl->wiphy,
- "wl: brcms_resume: pci_get_drvdata failed\n");
- return -ENODEV;
- }
-
- err = pci_set_power_state(pdev, PCI_D0);
- if (err)
- return err;
-
- pci_restore_state(pdev);
-
- err = pci_enable_device(pdev);
- if (err)
- return err;
-
- pci_set_master(pdev);
-
- pci_read_config_dword(pdev, 0x40, &val);
- if ((val & 0x0000ff00) != 0)
- pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
-
- /*
- * done. driver will be put in up state
- * in brcms_ops_add_interface() call.
- */
- return err;
-}
-
-/*
-* called from both kernel as from this kernel module.
-* precondition: perimeter lock is not acquired.
-*/
-static void brcms_remove(struct pci_dev *pdev)
-{
- struct brcms_info *wl;
- struct ieee80211_hw *hw;
- int status;
-
- hw = pci_get_drvdata(pdev);
- wl = HW_TO_WL(hw);
- if (!wl) {
- pr_err("wl: brcms_remove: pci_get_drvdata failed\n");
- return;
- }
-
- LOCK(wl);
- status = wlc_chipmatch(pdev->vendor, pdev->device);
- UNLOCK(wl);
- if (!status) {
- wiphy_err(wl->wiphy, "wl: brcms_remove: wlc_chipmatch "
- "failed\n");
- return;
- }
- if (wl->wlc) {
- wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, false);
- wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy);
- ieee80211_unregister_hw(hw);
- LOCK(wl);
- brcms_down(wl);
- UNLOCK(wl);
- }
- pci_disable_device(pdev);
-
- brcms_free(wl);
-
- pci_set_drvdata(pdev, NULL);
- ieee80211_free_hw(hw);
-}
-
-static struct pci_driver brcms_pci_driver = {
- .name = KBUILD_MODNAME,
- .probe = brcms_pci_probe,
- .suspend = brcms_suspend,
- .resume = brcms_resume,
- .remove = __devexit_p(brcms_remove),
- .id_table = brcms_pci_id_table,
-};
-
-/**
- * This is the main entry point for the WL driver.
- *
- * This function determines if a device pointed to by pdev is a WL device,
- * and if so, performs a brcms_attach() on it.
- *
- */
-static int __init brcms_module_init(void)
-{
- int error = -ENODEV;
-
-#ifdef BCMDBG
- if (msglevel != 0xdeadbeef)
- brcm_msg_level = msglevel;
- if (phymsglevel != 0xdeadbeef)
- phyhal_msg_level = phymsglevel;
-#endif /* BCMDBG */
-
- error = pci_register_driver(&brcms_pci_driver);
- if (!error)
- return 0;
-
-
-
- return error;
-}
-
-/**
- * This function unloads the WL driver from the system.
- *
- * This function unconditionally unloads the WL driver module from the
- * system.
- *
- */
-static void __exit brcms_module_exit(void)
-{
- pci_unregister_driver(&brcms_pci_driver);
-
-}
-
-module_init(brcms_module_init);
-module_exit(brcms_module_exit);
-
-/**
- * This function frees the WL per-device resources.
- *
- * This function frees resources owned by the WL device pointed to
- * by the wl parameter.
- *
- * precondition: can both be called locked and unlocked
- *
- */
-static void brcms_free(struct brcms_info *wl)
-{
- struct brcms_timer *t, *next;
-
- /* free ucode data */
- if (wl->fw.fw_cnt)
- brcms_ucode_data_free();
- if (wl->irq)
- free_irq(wl->irq, wl);
-
- /* kill dpc */
- tasklet_kill(&wl->tasklet);
-
- if (wl->pub) {
- wlc_module_unregister(wl->pub, "linux", wl);
- }
-
- /* free common resources */
- if (wl->wlc) {
- wlc_detach(wl->wlc);
- wl->wlc = NULL;
- wl->pub = NULL;
- }
-
- /* virtual interface deletion is deferred so we cannot spinwait */
-
- /* wait for all pending callbacks to complete */
- while (atomic_read(&wl->callbacks) > 0)
- schedule();
-
- /* free timers */
- for (t = wl->timers; t; t = next) {
- next = t->next;
-#ifdef BCMDBG
- kfree(t->name);
-#endif
- kfree(t);
- }
-
- /*
- * unregister_netdev() calls get_stats() which may read chip registers
- * so we cannot unmap the chip registers until after calling unregister_netdev() .
- */
- if (wl->regsva && wl->bcm_bustype != SDIO_BUS &&
- wl->bcm_bustype != JTAG_BUS) {
- iounmap((void *)wl->regsva);
- }
- wl->regsva = NULL;
-}
-
-/* flags the given rate in rateset as requested */
-static void brcms_set_basic_rate(struct wl_rateset *rs, u16 rate, bool is_br)
-{
- u32 i;
-
- for (i = 0; i < rs->count; i++) {
- if (rate != (rs->rates[i] & 0x7f))
- continue;
-
- if (is_br)
- rs->rates[i] |= WLC_RATE_FLAG;
- else
- rs->rates[i] &= WLC_RATE_MASK;
- return;
- }
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
- bool state, int prio)
-{
- wiphy_err(wl->wiphy, "Shouldn't be here %s\n", __func__);
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-void brcms_init(struct brcms_info *wl)
-{
- BCMMSG(WL_TO_HW(wl)->wiphy, "wl%d\n", wl->pub->unit);
- brcms_reset(wl);
-
- wlc_init(wl->wlc);
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-uint brcms_reset(struct brcms_info *wl)
-{
- BCMMSG(WL_TO_HW(wl)->wiphy, "wl%d\n", wl->pub->unit);
- wlc_reset(wl->wlc);
-
- /* dpc will not be rescheduled */
- wl->resched = 0;
-
- return 0;
-}
-
-/*
- * These are interrupt on/off entry points. Disable interrupts
- * during interrupt state transition.
- */
-void brcms_intrson(struct brcms_info *wl)
-{
- unsigned long flags;
-
- INT_LOCK(wl, flags);
- wlc_intrson(wl->wlc);
- INT_UNLOCK(wl, flags);
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-bool wl_alloc_dma_resources(struct brcms_info *wl, uint addrwidth)
-{
- return true;
-}
-
-u32 brcms_intrsoff(struct brcms_info *wl)
-{
- unsigned long flags;
- u32 status;
-
- INT_LOCK(wl, flags);
- status = wlc_intrsoff(wl->wlc);
- INT_UNLOCK(wl, flags);
- return status;
-}
-
-void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask)
-{
- unsigned long flags;
-
- INT_LOCK(wl, flags);
- wlc_intrsrestore(wl->wlc, macintmask);
- INT_UNLOCK(wl, flags);
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-int brcms_up(struct brcms_info *wl)
-{
- int error = 0;
-
- if (wl->pub->up)
- return 0;
-
- error = wlc_up(wl->wlc);
-
- return error;
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-void brcms_down(struct brcms_info *wl)
-{
- uint callbacks, ret_val = 0;
-
- /* call common down function */
- ret_val = wlc_down(wl->wlc);
- callbacks = atomic_read(&wl->callbacks) - ret_val;
-
- /* wait for down callbacks to complete */
- UNLOCK(wl);
-
- /* For HIGH_only driver, it's important to actually schedule other work,
- * not just spin wait since everything runs at schedule level
- */
- SPINWAIT((atomic_read(&wl->callbacks) > callbacks), 100 * 1000);
-
- LOCK(wl);
-}
-
-static irqreturn_t brcms_isr(int irq, void *dev_id)
-{
- struct brcms_info *wl;
- bool ours, wantdpc;
- unsigned long flags;
-
- wl = (struct brcms_info *) dev_id;
-
- ISR_LOCK(wl, flags);
-
- /* call common first level interrupt handler */
- ours = wlc_isr(wl->wlc, &wantdpc);
- if (ours) {
- /* if more to do... */
- if (wantdpc) {
-
- /* ...and call the second level interrupt handler */
- /* schedule dpc */
- tasklet_schedule(&wl->tasklet);
- }
- }
-
- ISR_UNLOCK(wl, flags);
-
- return IRQ_RETVAL(ours);
-}
-
-static void brcms_dpc(unsigned long data)
-{
- struct brcms_info *wl;
-
- wl = (struct brcms_info *) data;
-
- LOCK(wl);
-
- /* call the common second level interrupt handler */
- if (wl->pub->up) {
- if (wl->resched) {
- unsigned long flags;
-
- INT_LOCK(wl, flags);
- wlc_intrsupd(wl->wlc);
- INT_UNLOCK(wl, flags);
- }
-
- wl->resched = wlc_dpc(wl->wlc, true);
- }
-
- /* wlc_dpc() may bring the driver down */
- if (!wl->pub->up)
- goto done;
-
- /* re-schedule dpc */
- if (wl->resched)
- tasklet_schedule(&wl->tasklet);
- else {
- /* re-enable interrupts */
- brcms_intrson(wl);
- }
-
- done:
- UNLOCK(wl);
-}
-
-/*
- * is called by the kernel from software irq context
- */
-static void brcms_timer(unsigned long data)
-{
- _brcms_timer((struct brcms_timer *) data);
-}
-
-/*
-* precondition: perimeter lock is not acquired
- */
-static void _brcms_timer(struct brcms_timer *t)
-{
- LOCK(t->wl);
-
- if (t->set) {
- if (t->periodic) {
- t->timer.expires = jiffies + t->ms * HZ / 1000;
- atomic_inc(&t->wl->callbacks);
- add_timer(&t->timer);
- t->set = true;
- } else
- t->set = false;
-
- t->fn(t->arg);
- }
-
- atomic_dec(&t->wl->callbacks);
-
- UNLOCK(t->wl);
-}
-
-/*
- * Adds a timer to the list. Caller supplies a timer function.
- * Is called from wlc.
- *
- * precondition: perimeter lock has been acquired
- */
-struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
- void (*fn) (void *arg),
- void *arg, const char *name)
-{
- struct brcms_timer *t;
-
- t = kzalloc(sizeof(struct brcms_timer), GFP_ATOMIC);
- if (!t) {
- wiphy_err(wl->wiphy, "wl%d: brcms_init_timer: out of memory\n",
- wl->pub->unit);
- return 0;
- }
-
- init_timer(&t->timer);
- t->timer.data = (unsigned long) t;
- t->timer.function = brcms_timer;
- t->wl = wl;
- t->fn = fn;
- t->arg = arg;
- t->next = wl->timers;
- wl->timers = t;
-
-#ifdef BCMDBG
- t->name = kmalloc(strlen(name) + 1, GFP_ATOMIC);
- if (t->name)
- strcpy(t->name, name);
-#endif
-
- return t;
-}
-
-/* BMAC_NOTE: Add timer adds only the kernel timer since it's going to be more accurate
- * as well as it's easier to make it periodic
- *
- * precondition: perimeter lock has been acquired
- */
-void brcms_add_timer(struct brcms_info *wl, struct brcms_timer *t, uint ms,
- int periodic)
-{
-#ifdef BCMDBG
- if (t->set) {
- wiphy_err(wl->wiphy, "%s: Already set. Name: %s, per %d\n",
- __func__, t->name, periodic);
- }
-#endif
- t->ms = ms;
- t->periodic = (bool) periodic;
- t->set = true;
- t->timer.expires = jiffies + ms * HZ / 1000;
-
- atomic_inc(&wl->callbacks);
- add_timer(&t->timer);
-}
-
-/*
- * return true if timer successfully deleted, false if still pending
- *
- * precondition: perimeter lock has been acquired
- */
-bool brcms_del_timer(struct brcms_info *wl, struct brcms_timer *t)
-{
- if (t->set) {
- t->set = false;
- if (!del_timer(&t->timer)) {
- return false;
- }
- atomic_dec(&wl->callbacks);
- }
-
- return true;
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-void brcms_free_timer(struct brcms_info *wl, struct brcms_timer *t)
-{
- struct brcms_timer *tmp;
-
- /* delete the timer in case it is active */
- brcms_del_timer(wl, t);
-
- if (wl->timers == t) {
- wl->timers = wl->timers->next;
-#ifdef BCMDBG
- kfree(t->name);
-#endif
- kfree(t);
- return;
-
- }
-
- tmp = wl->timers;
- while (tmp) {
- if (tmp->next == t) {
- tmp->next = t->next;
-#ifdef BCMDBG
- kfree(t->name);
-#endif
- kfree(t);
- return;
- }
- tmp = tmp->next;
- }
-
-}
-
-/*
- * runs in software irq context
- *
- * precondition: perimeter lock is not acquired
- */
-static int wl_linux_watchdog(void *ctx)
-{
- return 0;
-}
-
-struct firmware_hdr {
- u32 offset;
- u32 len;
- u32 idx;
-};
-
-char *brcms_firmwares[MAX_FW_IMAGES] = {
- "brcm/bcm43xx",
- NULL
-};
-
-/*
- * precondition: perimeter lock has been acquired
- */
-int brcms_ucode_init_buf(struct brcms_info *wl, void **pbuf, u32 idx)
-{
- int i, entry;
- const u8 *pdata;
- struct firmware_hdr *hdr;
- for (i = 0; i < wl->fw.fw_cnt; i++) {
- hdr = (struct firmware_hdr *)wl->fw.fw_hdr[i]->data;
- for (entry = 0; entry < wl->fw.hdr_num_entries[i];
- entry++, hdr++) {
- if (hdr->idx == idx) {
- pdata = wl->fw.fw_bin[i]->data + hdr->offset;
- *pbuf = kmalloc(hdr->len, GFP_ATOMIC);
- if (*pbuf == NULL) {
- wiphy_err(wl->wiphy, "fail to alloc %d"
- " bytes\n", hdr->len);
- goto fail;
- }
- memcpy(*pbuf, pdata, hdr->len);
- return 0;
- }
- }
- }
- wiphy_err(wl->wiphy, "ERROR: ucode buf tag:%d can not be found!\n",
- idx);
- *pbuf = NULL;
-fail:
- return -ENODATA;
-}
-
-/*
- * Precondition: Since this function is called in brcms_pci_probe() context,
- * no locking is required.
- */
-int brcms_ucode_init_uint(struct brcms_info *wl, u32 *data, u32 idx)
-{
- int i, entry;
- const u8 *pdata;
- struct firmware_hdr *hdr;
- for (i = 0; i < wl->fw.fw_cnt; i++) {
- hdr = (struct firmware_hdr *)wl->fw.fw_hdr[i]->data;
- for (entry = 0; entry < wl->fw.hdr_num_entries[i];
- entry++, hdr++) {
- if (hdr->idx == idx) {
- pdata = wl->fw.fw_bin[i]->data + hdr->offset;
- if (hdr->len != 4) {
- wiphy_err(wl->wiphy,
- "ERROR: fw hdr len\n");
- return -ENOMSG;
- }
- *data = *((u32 *) pdata);
- return 0;
- }
- }
- }
- wiphy_err(wl->wiphy, "ERROR: ucode tag:%d can not be found!\n", idx);
- return -ENOMSG;
-}
-
-/*
- * Precondition: Since this function is called in brcms_pci_probe() context,
- * no locking is required.
- */
-static int brcms_request_fw(struct brcms_info *wl, struct pci_dev *pdev)
-{
- int status;
- struct device *device = &pdev->dev;
- char fw_name[100];
- int i;
-
- memset((void *)&wl->fw, 0, sizeof(struct brcms_firmware));
- for (i = 0; i < MAX_FW_IMAGES; i++) {
- if (brcms_firmwares[i] == NULL)
- break;
- sprintf(fw_name, "%s-%d.fw", brcms_firmwares[i],
- UCODE_LOADER_API_VER);
- status = request_firmware(&wl->fw.fw_bin[i], fw_name, device);
- if (status) {
- wiphy_err(wl->wiphy, "%s: fail to load firmware %s\n",
- KBUILD_MODNAME, fw_name);
- return status;
- }
- sprintf(fw_name, "%s_hdr-%d.fw", brcms_firmwares[i],
- UCODE_LOADER_API_VER);
- status = request_firmware(&wl->fw.fw_hdr[i], fw_name, device);
- if (status) {
- wiphy_err(wl->wiphy, "%s: fail to load firmware %s\n",
- KBUILD_MODNAME, fw_name);
- return status;
- }
- wl->fw.hdr_num_entries[i] =
- wl->fw.fw_hdr[i]->size / (sizeof(struct firmware_hdr));
- }
- wl->fw.fw_cnt = i;
- return brcms_ucode_data_init(wl);
-}
-
-/*
- * precondition: can both be called locked and unlocked
- */
-void brcms_ucode_free_buf(void *p)
-{
- kfree(p);
-}
-
-/*
- * Precondition: Since this function is called in brcms_pci_probe() context,
- * no locking is required.
- */
-static void brcms_release_fw(struct brcms_info *wl)
-{
- int i;
- for (i = 0; i < MAX_FW_IMAGES; i++) {
- release_firmware(wl->fw.fw_bin[i]);
- release_firmware(wl->fw.fw_hdr[i]);
- }
-}
-
-
-/*
- * checks validity of all firmware images loaded from user space
- *
- * Precondition: Since this function is called in brcms_pci_probe() context,
- * no locking is required.
- */
-int brcms_check_firmwares(struct brcms_info *wl)
-{
- int i;
- int entry;
- int rc = 0;
- const struct firmware *fw;
- const struct firmware *fw_hdr;
- struct firmware_hdr *ucode_hdr;
- for (i = 0; i < MAX_FW_IMAGES && rc == 0; i++) {
- fw = wl->fw.fw_bin[i];
- fw_hdr = wl->fw.fw_hdr[i];
- if (fw == NULL && fw_hdr == NULL) {
- break;
- } else if (fw == NULL || fw_hdr == NULL) {
- wiphy_err(wl->wiphy, "%s: invalid bin/hdr fw\n",
- __func__);
- rc = -EBADF;
- } else if (fw_hdr->size % sizeof(struct firmware_hdr)) {
- wiphy_err(wl->wiphy, "%s: non integral fw hdr file "
- "size %zu/%zu\n", __func__, fw_hdr->size,
- sizeof(struct firmware_hdr));
- rc = -EBADF;
- } else if (fw->size < MIN_FW_SIZE || fw->size > MAX_FW_SIZE) {
- wiphy_err(wl->wiphy, "%s: out of bounds fw file size "
- "%zu\n", __func__, fw->size);
- rc = -EBADF;
- } else {
- /* check if ucode section overruns firmware image */
- ucode_hdr = (struct firmware_hdr *)fw_hdr->data;
- for (entry = 0; entry < wl->fw.hdr_num_entries[i] &&
- !rc; entry++, ucode_hdr++) {
- if (ucode_hdr->offset + ucode_hdr->len >
- fw->size) {
- wiphy_err(wl->wiphy,
- "%s: conflicting bin/hdr\n",
- __func__);
- rc = -EBADF;
- }
- }
- }
- }
- if (rc == 0 && wl->fw.fw_cnt != i) {
- wiphy_err(wl->wiphy, "%s: invalid fw_cnt=%d\n", __func__,
- wl->fw.fw_cnt);
- rc = -EBADF;
- }
- return rc;
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-bool brcms_rfkill_set_hw_state(struct brcms_info *wl)
-{
- bool blocked = wlc_check_radio_disabled(wl->wlc);
-
- UNLOCK(wl);
- wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, blocked);
- if (blocked)
- wiphy_rfkill_start_polling(wl->pub->ieee_hw->wiphy);
- LOCK(wl);
- return blocked;
-}
-
-/*
- * precondition: perimeter lock has been acquired
- */
-void brcms_msleep(struct brcms_info *wl, uint ms)
-{
- UNLOCK(wl);
- msleep(ms);
- LOCK(wl);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_MAC80211_IF_H_
-#define _BRCM_MAC80211_IF_H_
-
-/* softmac ioctl definitions */
-#define WLC_SET_SHORTSLOT_OVERRIDE 146
-
-
-/* BMAC Note: High-only driver is no longer working in softirq context as it needs to block and
- * sleep so perimeter lock has to be a semaphore instead of spinlock. This requires timers to be
- * submitted to workqueue instead of being on kernel timer
- */
-struct brcms_timer {
- struct timer_list timer;
- struct brcms_info *wl;
- void (*fn) (void *);
- void *arg; /* argument to fn */
- uint ms;
- bool periodic;
- bool set;
- struct brcms_timer *next;
-#ifdef BCMDBG
- char *name; /* Description of the timer */
-#endif
-};
-
-struct brcms_if {
- uint subunit; /* WDS/BSS unit */
- struct pci_dev *pci_dev;
-};
-
-#define MAX_FW_IMAGES 4
-struct brcms_firmware {
- u32 fw_cnt;
- const struct firmware *fw_bin[MAX_FW_IMAGES];
- const struct firmware *fw_hdr[MAX_FW_IMAGES];
- u32 hdr_num_entries[MAX_FW_IMAGES];
-};
-
-struct brcms_info {
- struct wlc_pub *pub; /* pointer to public wlc state */
- void *wlc; /* pointer to private common os-independent data */
- u32 magic;
-
- int irq;
-
- spinlock_t lock; /* per-device perimeter lock */
- spinlock_t isr_lock; /* per-device ISR synchronization lock */
-
- /* bus type and regsva for unmap in brcms_free() */
- uint bcm_bustype; /* bus type */
- void *regsva; /* opaque chip registers virtual address */
-
- /* timer related fields */
- atomic_t callbacks; /* # outstanding callback functions */
- struct brcms_timer *timers; /* timer cleanup queue */
-
- struct tasklet_struct tasklet; /* dpc tasklet */
- bool resched; /* dpc needs to be and is rescheduled */
-#ifdef LINUXSTA_PS
- u32 pci_psstate[16]; /* pci ps-state save/restore */
-#endif
- struct brcms_firmware fw;
- struct wiphy *wiphy;
-};
-
-/* misc callbacks */
-struct brcms_info;
-struct brcms_if;
-struct wlc_if;
-extern void brcms_init(struct brcms_info *wl);
-extern uint brcms_reset(struct brcms_info *wl);
-extern void brcms_intrson(struct brcms_info *wl);
-extern u32 brcms_intrsoff(struct brcms_info *wl);
-extern void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask);
-extern int brcms_up(struct brcms_info *wl);
-extern void brcms_down(struct brcms_info *wl);
-extern void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
- bool state, int prio);
-extern bool wl_alloc_dma_resources(struct brcms_info *wl, uint dmaddrwidth);
-extern bool brcms_rfkill_set_hw_state(struct brcms_info *wl);
-
-/* timer functions */
-struct brcms_timer;
-extern struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
- void (*fn) (void *arg), void *arg,
- const char *name);
-extern void brcms_free_timer(struct brcms_info *wl, struct brcms_timer *timer);
-extern void brcms_add_timer(struct brcms_info *wl, struct brcms_timer *timer,
- uint ms, int periodic);
-extern bool brcms_del_timer(struct brcms_info *wl, struct brcms_timer *timer);
-extern void brcms_msleep(struct brcms_info *wl, uint ms);
-
-#endif /* _BRCM_MAC80211_IF_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_BSSCFG_H_
+#define _BRCM_BSSCFG_H_
+
+/* Check if a particular BSS config is AP or STA */
+#define BSSCFG_AP(cfg) (0)
+#define BSSCFG_STA(cfg) (1)
+
+#define BSSCFG_IBSS(cfg) (!(cfg)->BSS)
+
+#define NTXRATE 64 /* # tx MPDUs rate is reported for */
+#define MAXMACLIST 64 /* max # source MAC matches */
+#define BCN_TEMPLATE_COUNT 2
+
+/* Iterator for "associated" STA bss configs:
+ (struct wlc_info *wlc, int idx, struct wlc_bsscfg *cfg) */
+#define FOREACH_AS_STA(wlc, idx, cfg) \
+ for (idx = 0; (int) idx < WLC_MAXBSSCFG; idx++) \
+ if ((cfg = (wlc)->bsscfg[idx]) && BSSCFG_STA(cfg) && cfg->associated)
+
+/* As above for all non-NULL BSS configs */
+#define FOREACH_BSS(wlc, idx, cfg) \
+ for (idx = 0; (int) idx < WLC_MAXBSSCFG; idx++) \
+ if ((cfg = (wlc)->bsscfg[idx]))
+
+/* BSS configuration state */
+struct wlc_bsscfg {
+ struct wlc_info *wlc; /* wlc to which this bsscfg belongs to. */
+ bool up; /* is this configuration up operational */
+ bool enable; /* is this configuration enabled */
+ bool associated; /* is BSS in ASSOCIATED state */
+ bool BSS; /* infraustructure or adhac */
+ bool dtim_programmed;
+
+ u8 SSID_len; /* the length of SSID */
+ u8 SSID[IEEE80211_MAX_SSID_LEN]; /* SSID string */
+ struct scb *bcmc_scb[MAXBANDS]; /* one bcmc_scb per band */
+ s8 _idx; /* the index of this bsscfg,
+ * assigned at wlc_bsscfg_alloc()
+ */
+ /* MAC filter */
+ uint nmac; /* # of entries on maclist array */
+ int macmode; /* allow/deny stations on maclist array */
+ struct ether_addr *maclist; /* list of source MAC addrs to match */
+
+ /* security */
+ u32 wsec; /* wireless security bitvec */
+ s16 auth; /* 802.11 authentication: Open, Shared Key, WPA */
+ s16 openshared; /* try Open auth first, then Shared Key */
+ bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */
+ bool eap_restrict; /* restrict data until 802.1X auth succeeds */
+ u16 WPA_auth; /* WPA: authenticated key management */
+ bool wpa2_preauth; /* default is true, wpa_cap sets value */
+ bool wsec_portopen; /* indicates keys are plumbed */
+ wsec_iv_t wpa_none_txiv; /* global txiv for WPA_NONE, tkip and aes */
+ int wsec_index; /* 0-3: default tx key, -1: not set */
+ wsec_key_t *bss_def_keys[WLC_DEFAULT_KEYS]; /* default key storage */
+
+ /* TKIP countermeasures */
+ bool tkip_countermeasures; /* flags TKIP no-assoc period */
+ u32 tk_cm_dt; /* detect timer */
+ u32 tk_cm_bt; /* blocking timer */
+ u32 tk_cm_bt_tmstmp; /* Timestamp when TKIP BT is activated */
+ bool tk_cm_activate; /* activate countermeasures after EAPOL-Key sent */
+
+ u8 BSSID[ETH_ALEN]; /* BSSID (associated) */
+ u8 cur_etheraddr[ETH_ALEN]; /* h/w address */
+ u16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */
+ u16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */
+
+ u32 flags; /* WLC_BSSCFG flags; see below */
+
+ u8 *bcn; /* AP beacon */
+ uint bcn_len; /* AP beacon length */
+ bool ar_disassoc; /* disassociated in associated recreation */
+
+ int auth_atmptd; /* auth type (open/shared) attempted */
+
+ pmkid_cand_t pmkid_cand[MAXPMKID]; /* PMKID candidate list */
+ uint npmkid_cand; /* num PMKID candidates */
+ pmkid_t pmkid[MAXPMKID]; /* PMKID cache */
+ uint npmkid; /* num cached PMKIDs */
+
+ wlc_bss_info_t *current_bss; /* BSS parms in ASSOCIATED state */
+
+ /* PM states */
+ bool PMawakebcn; /* bcn recvd during current waking state */
+ bool PMpending; /* waiting for tx status with PM indicated set */
+ bool priorPMstate; /* Detecting PM state transitions */
+ bool PSpoll; /* whether there is an outstanding PS-Poll frame */
+
+ /* BSSID entry in RCMTA, use the wsec key management infrastructure to
+ * manage the RCMTA entries.
+ */
+ wsec_key_t *rcmta;
+
+ /* 'unique' ID of this bsscfg, assigned at bsscfg allocation */
+ u16 ID;
+
+ uint txrspecidx; /* index into tx rate circular buffer */
+ ratespec_t txrspec[NTXRATE][2]; /* circular buffer of prev MPDUs tx rates */
+};
+
+#define WLC_BSSCFG_11N_DISABLE 0x1000 /* Do not advertise .11n IEs for this BSS */
+#define WLC_BSSCFG_HW_BCN 0x20 /* The BSS is generating beacons in HW */
+
+#define HWBCN_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_BCN) != 0)
+#define HWPRB_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_PRB) != 0)
+
+/* Extend N_ENAB to per-BSS */
+#define BSS_N_ENAB(wlc, cfg) \
+ (N_ENAB((wlc)->pub) && !((cfg)->flags & WLC_BSSCFG_11N_DISABLE))
+
+#define MBSS_BCN_ENAB(cfg) 0
+#define MBSS_PRB_ENAB(cfg) 0
+#define SOFTBCN_ENAB(pub) (0)
+#define SOFTPRB_ENAB(pub) (0)
+#define wlc_bsscfg_tx_check(a) do { } while (0);
+
+#endif /* _BRCM_BSSCFG_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_CFG_H_
+#define _BRCM_CFG_H_
+
+#define NBANDS(wlc) ((wlc)->pub->_nbands)
+#define NBANDS_PUB(pub) ((pub)->_nbands)
+#define NBANDS_HW(hw) ((hw)->_nbands)
+
+#define IS_SINGLEBAND_5G(device) 0
+
+/* **** Core type/rev defaults **** */
+#define D11_DEFAULT 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
+ * also need to update wlc.h MAXCOREREV
+ */
+
+#define NPHY_DEFAULT 0x000001ff /* Supported nphy revs:
+ * 0 4321a0
+ * 1 4321a1
+ * 2 4321b0/b1/c0/c1
+ * 3 4322a0
+ * 4 4322a1
+ * 5 4716a0
+ * 6 43222a0, 43224a0
+ * 7 43226a0
+ * 8 5357a0, 43236a0
+ */
+
+#define LCNPHY_DEFAULT 0x00000007 /* Supported lcnphy revs:
+ * 0 4313a0, 4336a0, 4330a0
+ * 1
+ * 2 4330a0
+ */
+
+#define SSLPNPHY_DEFAULT 0x0000000f /* Supported sslpnphy revs:
+ * 0 4329a0/k0
+ * 1 4329b0/4329C0
+ * 2 4319a0
+ * 3 5356a0
+ */
+
+
+/* For undefined values, use defaults */
+#ifndef D11CONF
+#define D11CONF D11_DEFAULT
+#endif
+#ifndef NCONF
+#define NCONF NPHY_DEFAULT
+#endif
+#ifndef LCNCONF
+#define LCNCONF LCNPHY_DEFAULT
+#endif
+
+#ifndef SSLPNCONF
+#define SSLPNCONF SSLPNPHY_DEFAULT
+#endif
+
+/********************************************************************
+ * Phy/Core Configuration. Defines macros to to check core phy/rev *
+ * compile-time configuration. Defines default core support. *
+ * ******************************************************************
+ */
+
+/* Basic macros to check a configuration bitmask */
+
+#define CONF_HAS(config, val) ((config) & (1 << (val)))
+#define CONF_MSK(config, mask) ((config) & (mask))
+#define MSK_RANGE(low, hi) ((1 << ((hi)+1)) - (1 << (low)))
+#define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
+
+#define CONF_IS(config, val) ((config) == (1 << (val)))
+#define CONF_GE(config, val) ((config) & (0-(1 << (val))))
+#define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
+#define CONF_LT(config, val) ((config) & ((1 << (val))-1))
+#define CONF_LE(config, val) ((config) & (2*(1 << (val))-1))
+
+/* Wrappers for some of the above, specific to config constants */
+
+#define NCONF_HAS(val) CONF_HAS(NCONF, val)
+#define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
+#define NCONF_IS(val) CONF_IS(NCONF, val)
+#define NCONF_GE(val) CONF_GE(NCONF, val)
+#define NCONF_GT(val) CONF_GT(NCONF, val)
+#define NCONF_LT(val) CONF_LT(NCONF, val)
+#define NCONF_LE(val) CONF_LE(NCONF, val)
+
+#define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val)
+#define LCNCONF_MSK(mask) CONF_MSK(LCNCONF, mask)
+#define LCNCONF_IS(val) CONF_IS(LCNCONF, val)
+#define LCNCONF_GE(val) CONF_GE(LCNCONF, val)
+#define LCNCONF_GT(val) CONF_GT(LCNCONF, val)
+#define LCNCONF_LT(val) CONF_LT(LCNCONF, val)
+#define LCNCONF_LE(val) CONF_LE(LCNCONF, val)
+
+#define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
+#define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
+#define D11CONF_IS(val) CONF_IS(D11CONF, val)
+#define D11CONF_GE(val) CONF_GE(D11CONF, val)
+#define D11CONF_GT(val) CONF_GT(D11CONF, val)
+#define D11CONF_LT(val) CONF_LT(D11CONF, val)
+#define D11CONF_LE(val) CONF_LE(D11CONF, val)
+
+#define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
+#define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
+
+#define NREV_IS(var, val) (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
+#define NREV_GE(var, val) (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
+#define NREV_GT(var, val) (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
+#define NREV_LT(var, val) (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
+#define NREV_LE(var, val) (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
+
+#define LCNREV_IS(var, val) (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
+#define LCNREV_GE(var, val) (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
+#define LCNREV_GT(var, val) (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
+#define LCNREV_LT(var, val) (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
+#define LCNREV_LE(var, val) (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
+
+#define D11REV_IS(var, val) (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
+#define D11REV_GE(var, val) (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
+#define D11REV_GT(var, val) (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
+#define D11REV_LT(var, val) (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
+#define D11REV_LE(var, val) (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
+
+#define PHYTYPE_IS(var, val) (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
+
+/* Finally, early-exit from switch case if anyone wants it... */
+
+#define CASECHECK(config, val) if (!(CONF_HAS(config, val))) break
+#define CASEMSK(config, mask) if (!(CONF_MSK(config, mask))) break
+
+#if (D11CONF ^ (D11CONF & D11_DEFAULT))
+#error "Unsupported MAC revision configured"
+#endif
+#if (NCONF ^ (NCONF & NPHY_DEFAULT))
+#error "Unsupported NPHY revision configured"
+#endif
+#if (LCNCONF ^ (LCNCONF & LCNPHY_DEFAULT))
+#error "Unsupported LPPHY revision configured"
+#endif
+
+/* *** Consistency checks *** */
+#if !D11CONF
+#error "No MAC revisions configured!"
+#endif
+
+#if !NCONF && !LCNCONF && !SSLPNCONF
+#error "No PHY configured!"
+#endif
+
+/* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
+
+#define _PHYCONF_N (1 << PHY_TYPE_N)
+
+#if LCNCONF
+#define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
+#else
+#define _PHYCONF_LCN 0
+#endif /* LCNCONF */
+
+#if SSLPNCONF
+#define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
+#else
+#define _PHYCONF_SSLPN 0
+#endif /* SSLPNCONF */
+
+#define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
+
+/* Utility macro to identify 802.11n (HT) capable PHYs */
+#define PHYTYPE_11N_CAP(phytype) \
+ (PHYTYPE_IS(phytype, PHY_TYPE_N) || \
+ PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
+ PHYTYPE_IS(phytype, PHY_TYPE_SSN))
+
+/* Last but not least: shorter wlc-specific var checks */
+#define WLCISNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
+#define WLCISLCNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
+#define WLCISSSLPNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
+
+#define WLC_PHY_11N_CAP(band) PHYTYPE_11N_CAP((band)->phytype)
+
+/**********************************************************************
+ * ------------- End of Core phy/rev configuration. ----------------- *
+ * ********************************************************************
+ */
+
+/*************************************************
+ * Defaults for tunables (e.g. sizing constants)
+ *
+ * For each new tunable, add a member to the end
+ * of wlc_tunables_t in wlc_pub.h to enable
+ * runtime checks of tunable values. (Directly
+ * using the macros in code invalidates ROM code)
+ *
+ * ***********************************************
+ */
+#ifndef NTXD
+#define NTXD 256 /* Max # of entries in Tx FIFO based on 4kb page size */
+#endif /* NTXD */
+#ifndef NRXD
+#define NRXD 256 /* Max # of entries in Rx FIFO based on 4kb page size */
+#endif /* NRXD */
+
+#ifndef NRXBUFPOST
+#define NRXBUFPOST 32 /* try to keep this # rbufs posted to the chip */
+#endif /* NRXBUFPOST */
+
+#ifndef MAXSCB /* station control blocks in cache */
+#define MAXSCB 32 /* Maximum SCBs in cache for STA */
+#endif /* MAXSCB */
+
+#ifndef AMPDU_NUM_MPDU
+#define AMPDU_NUM_MPDU 16 /* max allowed number of mpdus in an ampdu (2 streams) */
+#endif /* AMPDU_NUM_MPDU */
+
+#ifndef AMPDU_NUM_MPDU_3STREAMS
+#define AMPDU_NUM_MPDU_3STREAMS 32 /* max allowed number of mpdus in an ampdu for 3+ streams */
+#endif /* AMPDU_NUM_MPDU_3STREAMS */
+
+/* Count of packet callback structures. either of following
+ * 1. Set to the number of SCBs since a STA
+ * can queue up a rate callback for each IBSS STA it knows about, and an AP can
+ * queue up an "are you there?" Null Data callback for each associated STA
+ * 2. controlled by tunable config file
+ */
+#ifndef MAXPKTCB
+#define MAXPKTCB MAXSCB /* Max number of packet callbacks */
+#endif /* MAXPKTCB */
+
+#ifndef CTFPOOLSZ
+#define CTFPOOLSZ 128
+#endif /* CTFPOOLSZ */
+
+/* NetBSD also needs to keep track of this */
+#define WLC_MAX_UCODE_BSS (16) /* Number of BSS handled in ucode bcn/prb */
+#define WLC_MAX_UCODE_BSS4 (4) /* Number of BSS handled in sw bcn/prb */
+#ifndef WLC_MAXBSSCFG
+#define WLC_MAXBSSCFG (1) /* max # BSS configs */
+#endif /* WLC_MAXBSSCFG */
+
+#ifndef MAXBSS
+#define MAXBSS 64 /* max # available networks */
+#endif /* MAXBSS */
+
+#ifndef WLC_DATAHIWAT
+#define WLC_DATAHIWAT 50 /* data msg txq hiwat mark */
+#endif /* WLC_DATAHIWAT */
+
+#ifndef WLC_AMPDUDATAHIWAT
+#define WLC_AMPDUDATAHIWAT 255
+#endif /* WLC_AMPDUDATAHIWAT */
+
+/* bounded rx loops */
+#ifndef RXBND
+#define RXBND 8 /* max # frames to process in wlc_recv() */
+#endif /* RXBND */
+#ifndef TXSBND
+#define TXSBND 8 /* max # tx status to process in wlc_txstatus() */
+#endif /* TXSBND */
+
+#define BAND_5G(bt) ((bt) == WLC_BAND_5G)
+#define BAND_2G(bt) ((bt) == WLC_BAND_2G)
+
+#define WLBANDINITDATA(_data) _data
+#define WLBANDINITFN(_fn) _fn
+
+#endif /* _BRCM_CFG_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include <defs.h>
+#include <brcmu_utils.h>
+#include <aiutils.h>
+#include "dma.h"
+
+#include "types.h"
+#include "d11.h"
+#include "cfg.h"
+#include "scb.h"
+#include "pub.h"
+#include "key.h"
+#include "phy/phy_hal.h"
+#include "bottom_mac.h"
+#include "rate.h"
+#include "channel.h"
+#include "main.h"
+#include "stf.h"
+
+#define VALID_CHANNEL20_DB(wlc, val) wlc_valid_channel20_db((wlc)->cmi, val)
+#define VALID_CHANNEL20_IN_BAND(wlc, bandunit, val) \
+ wlc_valid_channel20_in_band((wlc)->cmi, bandunit, val)
+#define VALID_CHANNEL20(wlc, val) wlc_valid_channel20((wlc)->cmi, val)
+
+typedef struct wlc_cm_band {
+ u8 locale_flags; /* locale_info_t flags */
+ chanvec_t valid_channels; /* List of valid channels in the country */
+ const chanvec_t *restricted_channels; /* List of restricted use channels */
+ const chanvec_t *radar_channels; /* List of radar sensitive channels */
+ u8 PAD[8];
+} wlc_cm_band_t;
+
+struct wlc_cm_info {
+ struct wlc_pub *pub;
+ struct wlc_info *wlc;
+ char srom_ccode[WLC_CNTRY_BUF_SZ]; /* Country Code in SROM */
+ uint srom_regrev; /* Regulatory Rev for the SROM ccode */
+ const country_info_t *country; /* current country def */
+ char ccode[WLC_CNTRY_BUF_SZ]; /* current internal Country Code */
+ uint regrev; /* current Regulatory Revision */
+ char country_abbrev[WLC_CNTRY_BUF_SZ]; /* current advertised ccode */
+ wlc_cm_band_t bandstate[MAXBANDS]; /* per-band state (one per phy/radio) */
+ /* quiet channels currently for radar sensitivity or 11h support */
+ chanvec_t quiet_channels; /* channels on which we cannot transmit */
+};
+
+static int wlc_channels_init(wlc_cm_info_t *wlc_cm,
+ const country_info_t *country);
+static void wlc_set_country_common(wlc_cm_info_t *wlc_cm,
+ const char *country_abbrev,
+ const char *ccode, uint regrev,
+ const country_info_t *country);
+static int wlc_set_countrycode(wlc_cm_info_t *wlc_cm, const char *ccode);
+static int wlc_set_countrycode_rev(wlc_cm_info_t *wlc_cm,
+ const char *country_abbrev,
+ const char *ccode, int regrev);
+static int wlc_country_aggregate_map(wlc_cm_info_t *wlc_cm, const char *ccode,
+ char *mapped_ccode, uint *mapped_regrev);
+static const country_info_t *wlc_country_lookup_direct(const char *ccode,
+ uint regrev);
+static const country_info_t *wlc_countrycode_map(wlc_cm_info_t *wlc_cm,
+ const char *ccode,
+ char *mapped_ccode,
+ uint *mapped_regrev);
+static void wlc_channels_commit(wlc_cm_info_t *wlc_cm);
+static void wlc_quiet_channels_reset(wlc_cm_info_t *wlc_cm);
+static bool wlc_quiet_chanspec(wlc_cm_info_t *wlc_cm, chanspec_t chspec);
+static bool wlc_valid_channel20_db(wlc_cm_info_t *wlc_cm, uint val);
+static bool wlc_valid_channel20_in_band(wlc_cm_info_t *wlc_cm, uint bandunit,
+ uint val);
+static bool wlc_valid_channel20(wlc_cm_info_t *wlc_cm, uint val);
+static const country_info_t *wlc_country_lookup(struct wlc_info *wlc,
+ const char *ccode);
+static void wlc_locale_get_channels(const locale_info_t *locale,
+ chanvec_t *valid_channels);
+static const locale_info_t *wlc_get_locale_2g(u8 locale_idx);
+static const locale_info_t *wlc_get_locale_5g(u8 locale_idx);
+static bool wlc_japan(struct wlc_info *wlc);
+static bool wlc_japan_ccode(const char *ccode);
+static void wlc_channel_min_txpower_limits_with_local_constraint(wlc_cm_info_t *
+ wlc_cm,
+ struct
+ txpwr_limits
+ *txpwr,
+ u8
+ local_constraint_qdbm);
+static void wlc_locale_add_channels(chanvec_t *target,
+ const chanvec_t *channels);
+static const locale_mimo_info_t *wlc_get_mimo_2g(u8 locale_idx);
+static const locale_mimo_info_t *wlc_get_mimo_5g(u8 locale_idx);
+
+/* QDB() macro takes a dB value and converts to a quarter dB value */
+#ifdef QDB
+#undef QDB
+#endif
+#define QDB(n) ((n) * WLC_TXPWR_DB_FACTOR)
+
+/* Regulatory Matrix Spreadsheet (CLM) MIMO v3.7.9 */
+
+/*
+ * Some common channel sets
+ */
+
+/* No channels */
+static const chanvec_t chanvec_none = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+/* All 2.4 GHz HW channels */
+const chanvec_t chanvec_all_2G = {
+ {0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+/* All 5 GHz HW channels */
+const chanvec_t chanvec_all_5G = {
+ {0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x11, 0x11,
+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11,
+ 0x11, 0x11, 0x20, 0x22, 0x22, 0x00, 0x00, 0x11,
+ 0x11, 0x11, 0x11, 0x01}
+};
+
+/*
+ * Radar channel sets
+ */
+
+/* No radar */
+#define radar_set_none chanvec_none
+
+static const chanvec_t radar_set1 = { /* Channels 52 - 64, 100 - 140 */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, /* 52 - 60 */
+ 0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11, /* 64, 100 - 124 */
+ 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 128 - 140 */
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+/*
+ * Restricted channel sets
+ */
+
+#define restricted_set_none chanvec_none
+
+/* Channels 34, 38, 42, 46 */
+static const chanvec_t restricted_set_japan_legacy = {
+ {0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+/* Channels 12, 13 */
+static const chanvec_t restricted_set_2g_short = {
+ {0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+/* Channel 165 */
+static const chanvec_t restricted_chan_165 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+/* Channels 36 - 48 & 149 - 165 */
+static const chanvec_t restricted_low_hi = {
+ {0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x20, 0x22, 0x22, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+/* Channels 12 - 14 */
+static const chanvec_t restricted_set_12_13_14 = {
+ {0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+#define LOCALE_CHAN_01_11 (1<<0)
+#define LOCALE_CHAN_12_13 (1<<1)
+#define LOCALE_CHAN_14 (1<<2)
+#define LOCALE_SET_5G_LOW_JP1 (1<<3) /* 34-48, step 2 */
+#define LOCALE_SET_5G_LOW_JP2 (1<<4) /* 34-46, step 4 */
+#define LOCALE_SET_5G_LOW1 (1<<5) /* 36-48, step 4 */
+#define LOCALE_SET_5G_LOW2 (1<<6) /* 52 */
+#define LOCALE_SET_5G_LOW3 (1<<7) /* 56-64, step 4 */
+#define LOCALE_SET_5G_MID1 (1<<8) /* 100-116, step 4 */
+#define LOCALE_SET_5G_MID2 (1<<9) /* 120-124, step 4 */
+#define LOCALE_SET_5G_MID3 (1<<10) /* 128 */
+#define LOCALE_SET_5G_HIGH1 (1<<11) /* 132-140, step 4 */
+#define LOCALE_SET_5G_HIGH2 (1<<12) /* 149-161, step 4 */
+#define LOCALE_SET_5G_HIGH3 (1<<13) /* 165 */
+#define LOCALE_CHAN_52_140_ALL (1<<14)
+#define LOCALE_SET_5G_HIGH4 (1<<15) /* 184-216 */
+
+#define LOCALE_CHAN_36_64 (LOCALE_SET_5G_LOW1 | LOCALE_SET_5G_LOW2 | LOCALE_SET_5G_LOW3)
+#define LOCALE_CHAN_52_64 (LOCALE_SET_5G_LOW2 | LOCALE_SET_5G_LOW3)
+#define LOCALE_CHAN_100_124 (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2)
+#define LOCALE_CHAN_100_140 \
+ (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2 | LOCALE_SET_5G_MID3 | LOCALE_SET_5G_HIGH1)
+#define LOCALE_CHAN_149_165 (LOCALE_SET_5G_HIGH2 | LOCALE_SET_5G_HIGH3)
+#define LOCALE_CHAN_184_216 LOCALE_SET_5G_HIGH4
+
+#define LOCALE_CHAN_01_14 (LOCALE_CHAN_01_11 | LOCALE_CHAN_12_13 | LOCALE_CHAN_14)
+
+#define LOCALE_RADAR_SET_NONE 0
+#define LOCALE_RADAR_SET_1 1
+
+#define LOCALE_RESTRICTED_NONE 0
+#define LOCALE_RESTRICTED_SET_2G_SHORT 1
+#define LOCALE_RESTRICTED_CHAN_165 2
+#define LOCALE_CHAN_ALL_5G 3
+#define LOCALE_RESTRICTED_JAPAN_LEGACY 4
+#define LOCALE_RESTRICTED_11D_2G 5
+#define LOCALE_RESTRICTED_11D_5G 6
+#define LOCALE_RESTRICTED_LOW_HI 7
+#define LOCALE_RESTRICTED_12_13_14 8
+
+/* global memory to provide working buffer for expanded locale */
+
+static const chanvec_t *g_table_radar_set[] = {
+ &chanvec_none,
+ &radar_set1
+};
+
+static const chanvec_t *g_table_restricted_chan[] = {
+ &chanvec_none, /* restricted_set_none */
+ &restricted_set_2g_short,
+ &restricted_chan_165,
+ &chanvec_all_5G,
+ &restricted_set_japan_legacy,
+ &chanvec_all_2G, /* restricted_set_11d_2G */
+ &chanvec_all_5G, /* restricted_set_11d_5G */
+ &restricted_low_hi,
+ &restricted_set_12_13_14
+};
+
+static const chanvec_t locale_2g_01_11 = {
+ {0xfe, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_2g_12_13 = {
+ {0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_2g_14 = {
+ {0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_LOW_JP1 = {
+ {0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_LOW_JP2 = {
+ {0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_LOW1 = {
+ {0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_LOW2 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_LOW3 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_MID1 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_MID2 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_MID3 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_HIGH1 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_HIGH2 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x20, 0x22, 0x02, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_HIGH3 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_52_140_ALL = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11,
+ 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
+ 0x11, 0x11, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static const chanvec_t locale_5g_HIGH4 = {
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
+ 0x11, 0x11, 0x11, 0x11}
+};
+
+static const chanvec_t *g_table_locale_base[] = {
+ &locale_2g_01_11,
+ &locale_2g_12_13,
+ &locale_2g_14,
+ &locale_5g_LOW_JP1,
+ &locale_5g_LOW_JP2,
+ &locale_5g_LOW1,
+ &locale_5g_LOW2,
+ &locale_5g_LOW3,
+ &locale_5g_MID1,
+ &locale_5g_MID2,
+ &locale_5g_MID3,
+ &locale_5g_HIGH1,
+ &locale_5g_HIGH2,
+ &locale_5g_HIGH3,
+ &locale_5g_52_140_ALL,
+ &locale_5g_HIGH4
+};
+
+static void wlc_locale_add_channels(chanvec_t *target,
+ const chanvec_t *channels)
+{
+ u8 i;
+ for (i = 0; i < sizeof(chanvec_t); i++) {
+ target->vec[i] |= channels->vec[i];
+ }
+}
+
+static void wlc_locale_get_channels(const locale_info_t *locale,
+ chanvec_t *channels)
+{
+ u8 i;
+
+ memset(channels, 0, sizeof(chanvec_t));
+
+ for (i = 0; i < ARRAY_SIZE(g_table_locale_base); i++) {
+ if (locale->valid_channels & (1 << i)) {
+ wlc_locale_add_channels(channels,
+ g_table_locale_base[i]);
+ }
+ }
+}
+
+/*
+ * Locale Definitions - 2.4 GHz
+ */
+static const locale_info_t locale_i = { /* locale i. channel 1 - 13 */
+ LOCALE_CHAN_01_11 | LOCALE_CHAN_12_13,
+ LOCALE_RADAR_SET_NONE,
+ LOCALE_RESTRICTED_SET_2G_SHORT,
+ {QDB(19), QDB(19), QDB(19),
+ QDB(19), QDB(19), QDB(19)},
+ {20, 20, 20, 0},
+ WLC_EIRP
+};
+
+/*
+ * Locale Definitions - 5 GHz
+ */
+static const locale_info_t locale_11 = {
+ /* locale 11. channel 36 - 48, 52 - 64, 100 - 140, 149 - 165 */
+ LOCALE_CHAN_36_64 | LOCALE_CHAN_100_140 | LOCALE_CHAN_149_165,
+ LOCALE_RADAR_SET_1,
+ LOCALE_RESTRICTED_NONE,
+ {QDB(21), QDB(21), QDB(21), QDB(21), QDB(21)},
+ {23, 23, 23, 30, 30},
+ WLC_EIRP | WLC_DFS_EU
+};
+
+#define LOCALE_2G_IDX_i 0
+static const locale_info_t *g_locale_2g_table[] = {
+ &locale_i
+};
+
+#define LOCALE_5G_IDX_11 0
+static const locale_info_t *g_locale_5g_table[] = {
+ &locale_11
+};
+
+/*
+ * MIMO Locale Definitions - 2.4 GHz
+ */
+static const locale_mimo_info_t locale_bn = {
+ {QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
+ QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
+ QDB(13), QDB(13), QDB(13)},
+ {0, 0, QDB(13), QDB(13), QDB(13),
+ QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
+ QDB(13), 0, 0},
+ 0
+};
+
+/* locale mimo 2g indexes */
+#define LOCALE_MIMO_IDX_bn 0
+
+static const locale_mimo_info_t *g_mimo_2g_table[] = {
+ &locale_bn
+};
+
+/*
+ * MIMO Locale Definitions - 5 GHz
+ */
+static const locale_mimo_info_t locale_11n = {
+ { /* 12.5 dBm */ 50, 50, 50, QDB(15), QDB(15)},
+ {QDB(14), QDB(15), QDB(15), QDB(15), QDB(15)},
+ 0
+};
+
+#define LOCALE_MIMO_IDX_11n 0
+static const locale_mimo_info_t *g_mimo_5g_table[] = {
+ &locale_11n
+};
+
+#ifdef LC
+#undef LC
+#endif
+#define LC(id) LOCALE_MIMO_IDX_ ## id
+
+#ifdef LC_2G
+#undef LC_2G
+#endif
+#define LC_2G(id) LOCALE_2G_IDX_ ## id
+
+#ifdef LC_5G
+#undef LC_5G
+#endif
+#define LC_5G(id) LOCALE_5G_IDX_ ## id
+
+#define LOCALES(band2, band5, mimo2, mimo5) {LC_2G(band2), LC_5G(band5), LC(mimo2), LC(mimo5)}
+
+static const struct {
+ char abbrev[WLC_CNTRY_BUF_SZ]; /* country abbreviation */
+ country_info_t country;
+} cntry_locales[] = {
+ {
+ "X2", LOCALES(i, 11, bn, 11n)}, /* Worldwide RoW 2 */
+};
+
+#ifdef SUPPORT_40MHZ
+/* 20MHz channel info for 40MHz pairing support */
+struct chan20_info {
+ u8 sb;
+ u8 adj_sbs;
+};
+
+/* indicates adjacent channels that are allowed for a 40 Mhz channel and
+ * those that permitted by the HT
+ */
+struct chan20_info chan20_info[] = {
+ /* 11b/11g */
+/* 0 */ {1, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 1 */ {2, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 2 */ {3, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 3 */ {4, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 4 */ {5, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
+/* 5 */ {6, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
+/* 6 */ {7, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
+/* 7 */ {8, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
+/* 8 */ {9, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
+/* 9 */ {10, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 10 */ {11, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 11 */ {12, (CH_LOWER_SB)},
+/* 12 */ {13, (CH_LOWER_SB)},
+/* 13 */ {14, (CH_LOWER_SB)},
+
+/* 11a japan high */
+/* 14 */ {34, (CH_UPPER_SB)},
+/* 15 */ {38, (CH_LOWER_SB)},
+/* 16 */ {42, (CH_LOWER_SB)},
+/* 17 */ {46, (CH_LOWER_SB)},
+
+/* 11a usa low */
+/* 18 */ {36, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 19 */ {40, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 20 */ {44, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 21 */ {48, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 22 */ {52, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 23 */ {56, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 24 */ {60, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 25 */ {64, (CH_LOWER_SB | CH_EWA_VALID)},
+
+/* 11a Europe */
+/* 26 */ {100, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 27 */ {104, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 28 */ {108, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 29 */ {112, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 30 */ {116, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 31 */ {120, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 32 */ {124, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 33 */ {128, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 34 */ {132, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 35 */ {136, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 36 */ {140, (CH_LOWER_SB)},
+
+/* 11a usa high, ref5 only */
+/* The 0x80 bit in pdiv means these are REF5, other entries are REF20 */
+/* 37 */ {149, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 38 */ {153, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 39 */ {157, (CH_UPPER_SB | CH_EWA_VALID)},
+/* 40 */ {161, (CH_LOWER_SB | CH_EWA_VALID)},
+/* 41 */ {165, (CH_LOWER_SB)},
+
+/* 11a japan */
+/* 42 */ {184, (CH_UPPER_SB)},
+/* 43 */ {188, (CH_LOWER_SB)},
+/* 44 */ {192, (CH_UPPER_SB)},
+/* 45 */ {196, (CH_LOWER_SB)},
+/* 46 */ {200, (CH_UPPER_SB)},
+/* 47 */ {204, (CH_LOWER_SB)},
+/* 48 */ {208, (CH_UPPER_SB)},
+/* 49 */ {212, (CH_LOWER_SB)},
+/* 50 */ {216, (CH_LOWER_SB)}
+};
+#endif /* SUPPORT_40MHZ */
+
+static const locale_info_t *wlc_get_locale_2g(u8 locale_idx)
+{
+ if (locale_idx >= ARRAY_SIZE(g_locale_2g_table)) {
+ return NULL; /* error condition */
+ }
+ return g_locale_2g_table[locale_idx];
+}
+
+static const locale_info_t *wlc_get_locale_5g(u8 locale_idx)
+{
+ if (locale_idx >= ARRAY_SIZE(g_locale_5g_table)) {
+ return NULL; /* error condition */
+ }
+ return g_locale_5g_table[locale_idx];
+}
+
+static const locale_mimo_info_t *wlc_get_mimo_2g(u8 locale_idx)
+{
+ if (locale_idx >= ARRAY_SIZE(g_mimo_2g_table)) {
+ return NULL;
+ }
+ return g_mimo_2g_table[locale_idx];
+}
+
+static const locale_mimo_info_t *wlc_get_mimo_5g(u8 locale_idx)
+{
+ if (locale_idx >= ARRAY_SIZE(g_mimo_5g_table)) {
+ return NULL;
+ }
+ return g_mimo_5g_table[locale_idx];
+}
+
+wlc_cm_info_t *wlc_channel_mgr_attach(struct wlc_info *wlc)
+{
+ wlc_cm_info_t *wlc_cm;
+ char country_abbrev[WLC_CNTRY_BUF_SZ];
+ const country_info_t *country;
+ struct wlc_pub *pub = wlc->pub;
+ char *ccode;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ wlc_cm = kzalloc(sizeof(wlc_cm_info_t), GFP_ATOMIC);
+ if (wlc_cm == NULL) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: out of memory", pub->unit,
+ __func__);
+ return NULL;
+ }
+ wlc_cm->pub = pub;
+ wlc_cm->wlc = wlc;
+ wlc->cmi = wlc_cm;
+
+ /* store the country code for passing up as a regulatory hint */
+ ccode = getvar(wlc->pub->vars, "ccode");
+ if (ccode) {
+ strncpy(wlc->pub->srom_ccode, ccode, WLC_CNTRY_BUF_SZ - 1);
+ }
+
+ /* internal country information which must match regulatory constraints in firmware */
+ memset(country_abbrev, 0, WLC_CNTRY_BUF_SZ);
+ strncpy(country_abbrev, "X2", sizeof(country_abbrev) - 1);
+ country = wlc_country_lookup(wlc, country_abbrev);
+
+ /* save default country for exiting 11d regulatory mode */
+ strncpy(wlc->country_default, country_abbrev, WLC_CNTRY_BUF_SZ - 1);
+
+ /* initialize autocountry_default to driver default */
+ strncpy(wlc->autocountry_default, "X2", WLC_CNTRY_BUF_SZ - 1);
+
+ wlc_set_countrycode(wlc_cm, country_abbrev);
+
+ return wlc_cm;
+}
+
+void wlc_channel_mgr_detach(wlc_cm_info_t *wlc_cm)
+{
+ kfree(wlc_cm);
+}
+
+u8 wlc_channel_locale_flags_in_band(wlc_cm_info_t *wlc_cm, uint bandunit)
+{
+ return wlc_cm->bandstate[bandunit].locale_flags;
+}
+
+/* set the driver's current country and regulatory information using a country code
+ * as the source. Lookup built in country information found with the country code.
+ */
+static int wlc_set_countrycode(wlc_cm_info_t *wlc_cm, const char *ccode)
+{
+ char country_abbrev[WLC_CNTRY_BUF_SZ];
+ strncpy(country_abbrev, ccode, WLC_CNTRY_BUF_SZ);
+ return wlc_set_countrycode_rev(wlc_cm, country_abbrev, ccode, -1);
+}
+
+static int
+wlc_set_countrycode_rev(wlc_cm_info_t *wlc_cm,
+ const char *country_abbrev,
+ const char *ccode, int regrev)
+{
+ const country_info_t *country;
+ char mapped_ccode[WLC_CNTRY_BUF_SZ];
+ uint mapped_regrev;
+
+ /* if regrev is -1, lookup the mapped country code,
+ * otherwise use the ccode and regrev directly
+ */
+ if (regrev == -1) {
+ /* map the country code to a built-in country code, regrev, and country_info */
+ country =
+ wlc_countrycode_map(wlc_cm, ccode, mapped_ccode,
+ &mapped_regrev);
+ } else {
+ /* find the matching built-in country definition */
+ country = wlc_country_lookup_direct(ccode, regrev);
+ strncpy(mapped_ccode, ccode, WLC_CNTRY_BUF_SZ);
+ mapped_regrev = regrev;
+ }
+
+ if (country == NULL)
+ return -EINVAL;
+
+ /* set the driver state for the country */
+ wlc_set_country_common(wlc_cm, country_abbrev, mapped_ccode,
+ mapped_regrev, country);
+
+ return 0;
+}
+
+/* set the driver's current country and regulatory information using a country code
+ * as the source. Look up built in country information found with the country code.
+ */
+static void
+wlc_set_country_common(wlc_cm_info_t *wlc_cm,
+ const char *country_abbrev,
+ const char *ccode, uint regrev,
+ const country_info_t *country)
+{
+ const locale_mimo_info_t *li_mimo;
+ const locale_info_t *locale;
+ struct wlc_info *wlc = wlc_cm->wlc;
+ char prev_country_abbrev[WLC_CNTRY_BUF_SZ];
+
+ /* save current country state */
+ wlc_cm->country = country;
+
+ memset(&prev_country_abbrev, 0, WLC_CNTRY_BUF_SZ);
+ strncpy(prev_country_abbrev, wlc_cm->country_abbrev,
+ WLC_CNTRY_BUF_SZ - 1);
+
+ strncpy(wlc_cm->country_abbrev, country_abbrev, WLC_CNTRY_BUF_SZ - 1);
+ strncpy(wlc_cm->ccode, ccode, WLC_CNTRY_BUF_SZ - 1);
+ wlc_cm->regrev = regrev;
+
+ /* disable/restore nmode based on country regulations */
+ li_mimo = wlc_get_mimo_2g(country->locale_mimo_2G);
+ if (li_mimo && (li_mimo->flags & WLC_NO_MIMO)) {
+ wlc_set_nmode(wlc, OFF);
+ wlc->stf->no_cddstbc = true;
+ } else {
+ wlc->stf->no_cddstbc = false;
+ if (N_ENAB(wlc->pub) != wlc->protection->nmode_user)
+ wlc_set_nmode(wlc, wlc->protection->nmode_user);
+ }
+
+ wlc_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
+ wlc_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
+ /* set or restore gmode as required by regulatory */
+ locale = wlc_get_locale_2g(country->locale_2G);
+ if (locale && (locale->flags & WLC_NO_OFDM)) {
+ wlc_set_gmode(wlc, GMODE_LEGACY_B, false);
+ } else {
+ wlc_set_gmode(wlc, wlc->protection->gmode_user, false);
+ }
+
+ wlc_channels_init(wlc_cm, country);
+
+ return;
+}
+
+/* Lookup a country info structure from a null terminated country code
+ * The lookup is case sensitive.
+ */
+static const country_info_t *wlc_country_lookup(struct wlc_info *wlc,
+ const char *ccode)
+{
+ const country_info_t *country;
+ char mapped_ccode[WLC_CNTRY_BUF_SZ];
+ uint mapped_regrev;
+
+ /* map the country code to a built-in country code, regrev, and country_info struct */
+ country =
+ wlc_countrycode_map(wlc->cmi, ccode, mapped_ccode, &mapped_regrev);
+
+ return country;
+}
+
+static const country_info_t *wlc_countrycode_map(wlc_cm_info_t *wlc_cm,
+ const char *ccode,
+ char *mapped_ccode,
+ uint *mapped_regrev)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+ const country_info_t *country;
+ uint srom_regrev = wlc_cm->srom_regrev;
+ const char *srom_ccode = wlc_cm->srom_ccode;
+ int mapped;
+
+ /* check for currently supported ccode size */
+ if (strlen(ccode) > (WLC_CNTRY_BUF_SZ - 1)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: ccode \"%s\" too long for "
+ "match\n", wlc->pub->unit, __func__, ccode);
+ return NULL;
+ }
+
+ /* default mapping is the given ccode and regrev 0 */
+ strncpy(mapped_ccode, ccode, WLC_CNTRY_BUF_SZ);
+ *mapped_regrev = 0;
+
+ /* If the desired country code matches the srom country code,
+ * then the mapped country is the srom regulatory rev.
+ * Otherwise look for an aggregate mapping.
+ */
+ if (!strcmp(srom_ccode, ccode)) {
+ *mapped_regrev = srom_regrev;
+ mapped = 0;
+ wiphy_err(wlc->wiphy, "srom_code == ccode %s\n", __func__);
+ } else {
+ mapped =
+ wlc_country_aggregate_map(wlc_cm, ccode, mapped_ccode,
+ mapped_regrev);
+ }
+
+ /* find the matching built-in country definition */
+ country = wlc_country_lookup_direct(mapped_ccode, *mapped_regrev);
+
+ /* if there is not an exact rev match, default to rev zero */
+ if (country == NULL && *mapped_regrev != 0) {
+ *mapped_regrev = 0;
+ country =
+ wlc_country_lookup_direct(mapped_ccode, *mapped_regrev);
+ }
+
+ return country;
+}
+
+static int
+wlc_country_aggregate_map(wlc_cm_info_t *wlc_cm, const char *ccode,
+ char *mapped_ccode, uint *mapped_regrev)
+{
+ return false;
+}
+
+/* Lookup a country info structure from a null terminated country
+ * abbreviation and regrev directly with no translation.
+ */
+static const country_info_t *wlc_country_lookup_direct(const char *ccode,
+ uint regrev)
+{
+ uint size, i;
+
+ /* Should just return 0 for single locale driver. */
+ /* Keep it this way in case we add more locales. (for now anyway) */
+
+ /* all other country def arrays are for regrev == 0, so if regrev is non-zero, fail */
+ if (regrev > 0)
+ return NULL;
+
+ /* find matched table entry from country code */
+ size = ARRAY_SIZE(cntry_locales);
+ for (i = 0; i < size; i++) {
+ if (strcmp(ccode, cntry_locales[i].abbrev) == 0) {
+ return &cntry_locales[i].country;
+ }
+ }
+ return NULL;
+}
+
+static int
+wlc_channels_init(wlc_cm_info_t *wlc_cm, const country_info_t *country)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+ uint i, j;
+ struct wlcband *band;
+ const locale_info_t *li;
+ chanvec_t sup_chan;
+ const locale_mimo_info_t *li_mimo;
+
+ band = wlc->band;
+ for (i = 0; i < NBANDS(wlc);
+ i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
+
+ li = BAND_5G(band->bandtype) ?
+ wlc_get_locale_5g(country->locale_5G) :
+ wlc_get_locale_2g(country->locale_2G);
+ wlc_cm->bandstate[band->bandunit].locale_flags = li->flags;
+ li_mimo = BAND_5G(band->bandtype) ?
+ wlc_get_mimo_5g(country->locale_mimo_5G) :
+ wlc_get_mimo_2g(country->locale_mimo_2G);
+
+ /* merge the mimo non-mimo locale flags */
+ wlc_cm->bandstate[band->bandunit].locale_flags |=
+ li_mimo->flags;
+
+ wlc_cm->bandstate[band->bandunit].restricted_channels =
+ g_table_restricted_chan[li->restricted_channels];
+ wlc_cm->bandstate[band->bandunit].radar_channels =
+ g_table_radar_set[li->radar_channels];
+
+ /* set the channel availability,
+ * masking out the channels that may not be supported on this phy
+ */
+ wlc_phy_chanspec_band_validch(band->pi, band->bandtype,
+ &sup_chan);
+ wlc_locale_get_channels(li,
+ &wlc_cm->bandstate[band->bandunit].
+ valid_channels);
+ for (j = 0; j < sizeof(chanvec_t); j++)
+ wlc_cm->bandstate[band->bandunit].valid_channels.
+ vec[j] &= sup_chan.vec[j];
+ }
+
+ wlc_quiet_channels_reset(wlc_cm);
+ wlc_channels_commit(wlc_cm);
+
+ return 0;
+}
+
+/* Update the radio state (enable/disable) and tx power targets
+ * based on a new set of channel/regulatory information
+ */
+static void wlc_channels_commit(wlc_cm_info_t *wlc_cm)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+ uint chan;
+ struct txpwr_limits txpwr;
+
+ /* search for the existence of any valid channel */
+ for (chan = 0; chan < MAXCHANNEL; chan++) {
+ if (VALID_CHANNEL20_DB(wlc, chan)) {
+ break;
+ }
+ }
+ if (chan == MAXCHANNEL)
+ chan = INVCHANNEL;
+
+ /* based on the channel search above, set or clear WL_RADIO_COUNTRY_DISABLE */
+ if (chan == INVCHANNEL) {
+ /* country/locale with no valid channels, set the radio disable bit */
+ mboolset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
+ wiphy_err(wlc->wiphy, "wl%d: %s: no valid channel for \"%s\" "
+ "nbands %d bandlocked %d\n", wlc->pub->unit,
+ __func__, wlc_cm->country_abbrev, NBANDS(wlc),
+ wlc->bandlocked);
+ } else
+ if (mboolisset(wlc->pub->radio_disabled,
+ WL_RADIO_COUNTRY_DISABLE)) {
+ /* country/locale with valid channel, clear the radio disable bit */
+ mboolclr(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
+ }
+
+ /* Now that the country abbreviation is set, if the radio supports 2G, then
+ * set channel 14 restrictions based on the new locale.
+ */
+ if (NBANDS(wlc) > 1 || BAND_2G(wlc->band->bandtype)) {
+ wlc_phy_chanspec_ch14_widefilter_set(wlc->band->pi,
+ wlc_japan(wlc) ? true :
+ false);
+ }
+
+ if (wlc->pub->up && chan != INVCHANNEL) {
+ wlc_channel_reg_limits(wlc_cm, wlc->chanspec, &txpwr);
+ wlc_channel_min_txpower_limits_with_local_constraint(wlc_cm,
+ &txpwr,
+ WLC_TXPWR_MAX);
+ wlc_phy_txpower_limit_set(wlc->band->pi, &txpwr, wlc->chanspec);
+ }
+}
+
+/* reset the quiet channels vector to the union of the restricted and radar channel sets */
+static void wlc_quiet_channels_reset(wlc_cm_info_t *wlc_cm)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+ uint i, j;
+ struct wlcband *band;
+ const chanvec_t *chanvec;
+
+ memset(&wlc_cm->quiet_channels, 0, sizeof(chanvec_t));
+
+ band = wlc->band;
+ for (i = 0; i < NBANDS(wlc);
+ i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
+
+ /* initialize quiet channels for restricted channels */
+ chanvec = wlc_cm->bandstate[band->bandunit].restricted_channels;
+ for (j = 0; j < sizeof(chanvec_t); j++)
+ wlc_cm->quiet_channels.vec[j] |= chanvec->vec[j];
+
+ }
+}
+
+static bool wlc_quiet_chanspec(wlc_cm_info_t *wlc_cm, chanspec_t chspec)
+{
+ return N_ENAB(wlc_cm->wlc->pub) && CHSPEC_IS40(chspec) ?
+ (isset
+ (wlc_cm->quiet_channels.vec,
+ LOWER_20_SB(CHSPEC_CHANNEL(chspec)))
+ || isset(wlc_cm->quiet_channels.vec,
+ UPPER_20_SB(CHSPEC_CHANNEL(chspec)))) : isset(wlc_cm->
+ quiet_channels.
+ vec,
+ CHSPEC_CHANNEL
+ (chspec));
+}
+
+/* Is the channel valid for the current locale? (but don't consider channels not
+ * available due to bandlocking)
+ */
+static bool wlc_valid_channel20_db(wlc_cm_info_t *wlc_cm, uint val)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+
+ return VALID_CHANNEL20(wlc, val) ||
+ (!wlc->bandlocked
+ && VALID_CHANNEL20_IN_BAND(wlc, OTHERBANDUNIT(wlc), val));
+}
+
+/* Is the channel valid for the current locale and specified band? */
+static bool
+wlc_valid_channel20_in_band(wlc_cm_info_t *wlc_cm, uint bandunit, uint val)
+{
+ return ((val < MAXCHANNEL)
+ && isset(wlc_cm->bandstate[bandunit].valid_channels.vec, val));
+}
+
+/* Is the channel valid for the current locale and current band? */
+static bool wlc_valid_channel20(wlc_cm_info_t *wlc_cm, uint val)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+
+ return ((val < MAXCHANNEL) &&
+ isset(wlc_cm->bandstate[wlc->band->bandunit].valid_channels.vec,
+ val));
+}
+
+static void
+wlc_channel_min_txpower_limits_with_local_constraint(wlc_cm_info_t *wlc_cm,
+ struct txpwr_limits *txpwr,
+ u8
+ local_constraint_qdbm)
+{
+ int j;
+
+ /* CCK Rates */
+ for (j = 0; j < WL_TX_POWER_CCK_NUM; j++) {
+ txpwr->cck[j] = min(txpwr->cck[j], local_constraint_qdbm);
+ }
+
+ /* 20 MHz Legacy OFDM SISO */
+ for (j = 0; j < WL_TX_POWER_OFDM_NUM; j++) {
+ txpwr->ofdm[j] = min(txpwr->ofdm[j], local_constraint_qdbm);
+ }
+
+ /* 20 MHz Legacy OFDM CDD */
+ for (j = 0; j < WLC_NUM_RATES_OFDM; j++) {
+ txpwr->ofdm_cdd[j] =
+ min(txpwr->ofdm_cdd[j], local_constraint_qdbm);
+ }
+
+ /* 40 MHz Legacy OFDM SISO */
+ for (j = 0; j < WLC_NUM_RATES_OFDM; j++) {
+ txpwr->ofdm_40_siso[j] =
+ min(txpwr->ofdm_40_siso[j], local_constraint_qdbm);
+ }
+
+ /* 40 MHz Legacy OFDM CDD */
+ for (j = 0; j < WLC_NUM_RATES_OFDM; j++) {
+ txpwr->ofdm_40_cdd[j] =
+ min(txpwr->ofdm_40_cdd[j], local_constraint_qdbm);
+ }
+
+ /* 20MHz MCS 0-7 SISO */
+ for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
+ txpwr->mcs_20_siso[j] =
+ min(txpwr->mcs_20_siso[j], local_constraint_qdbm);
+ }
+
+ /* 20MHz MCS 0-7 CDD */
+ for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
+ txpwr->mcs_20_cdd[j] =
+ min(txpwr->mcs_20_cdd[j], local_constraint_qdbm);
+ }
+
+ /* 20MHz MCS 0-7 STBC */
+ for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
+ txpwr->mcs_20_stbc[j] =
+ min(txpwr->mcs_20_stbc[j], local_constraint_qdbm);
+ }
+
+ /* 20MHz MCS 8-15 MIMO */
+ for (j = 0; j < WLC_NUM_RATES_MCS_2_STREAM; j++)
+ txpwr->mcs_20_mimo[j] =
+ min(txpwr->mcs_20_mimo[j], local_constraint_qdbm);
+
+ /* 40MHz MCS 0-7 SISO */
+ for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
+ txpwr->mcs_40_siso[j] =
+ min(txpwr->mcs_40_siso[j], local_constraint_qdbm);
+ }
+
+ /* 40MHz MCS 0-7 CDD */
+ for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
+ txpwr->mcs_40_cdd[j] =
+ min(txpwr->mcs_40_cdd[j], local_constraint_qdbm);
+ }
+
+ /* 40MHz MCS 0-7 STBC */
+ for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
+ txpwr->mcs_40_stbc[j] =
+ min(txpwr->mcs_40_stbc[j], local_constraint_qdbm);
+ }
+
+ /* 40MHz MCS 8-15 MIMO */
+ for (j = 0; j < WLC_NUM_RATES_MCS_2_STREAM; j++)
+ txpwr->mcs_40_mimo[j] =
+ min(txpwr->mcs_40_mimo[j], local_constraint_qdbm);
+
+ /* 40MHz MCS 32 */
+ txpwr->mcs32 = min(txpwr->mcs32, local_constraint_qdbm);
+
+}
+
+void
+wlc_channel_set_chanspec(wlc_cm_info_t *wlc_cm, chanspec_t chanspec,
+ u8 local_constraint_qdbm)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+ struct txpwr_limits txpwr;
+
+ wlc_channel_reg_limits(wlc_cm, chanspec, &txpwr);
+
+ wlc_channel_min_txpower_limits_with_local_constraint(wlc_cm, &txpwr,
+ local_constraint_qdbm);
+
+ wlc_bmac_set_chanspec(wlc->hw, chanspec,
+ (wlc_quiet_chanspec(wlc_cm, chanspec) != 0),
+ &txpwr);
+}
+
+#ifdef POWER_DBG
+static void wlc_phy_txpower_limits_dump(txpwr_limits_t *txpwr)
+{
+ int i;
+ char buf[80];
+ char fraction[4][4] = { " ", ".25", ".5 ", ".75" };
+
+ sprintf(buf, "CCK ");
+ for (i = 0; i < WLC_NUM_RATES_CCK; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->cck[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->cck[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "20 MHz OFDM SISO ");
+ for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->ofdm[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->ofdm[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "20 MHz OFDM CDD ");
+ for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->ofdm_cdd[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->ofdm_cdd[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "40 MHz OFDM SISO ");
+ for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->ofdm_40_siso[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->ofdm_40_siso[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "40 MHz OFDM CDD ");
+ for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->ofdm_40_cdd[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->ofdm_40_cdd[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "20 MHz MCS0-7 SISO ");
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->mcs_20_siso[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs_20_siso[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "20 MHz MCS0-7 CDD ");
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->mcs_20_cdd[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs_20_cdd[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "20 MHz MCS0-7 STBC ");
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->mcs_20_stbc[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs_20_stbc[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "20 MHz MCS8-15 SDM ");
+ for (i = 0; i < WLC_NUM_RATES_MCS_2_STREAM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->mcs_20_mimo[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs_20_mimo[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "40 MHz MCS0-7 SISO ");
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->mcs_40_siso[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs_40_siso[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "40 MHz MCS0-7 CDD ");
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->mcs_40_cdd[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs_40_cdd[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "40 MHz MCS0-7 STBC ");
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->mcs_40_stbc[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs_40_stbc[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ sprintf(buf, "40 MHz MCS8-15 SDM ");
+ for (i = 0; i < WLC_NUM_RATES_MCS_2_STREAM; i++) {
+ sprintf(buf[strlen(buf)], " %2d%s",
+ txpwr->mcs_40_mimo[i] / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs_40_mimo[i] % WLC_TXPWR_DB_FACTOR]);
+ }
+ printk(KERN_DEBUG "%s\n", buf);
+
+ printk(KERN_DEBUG "MCS32 %2d%s\n",
+ txpwr->mcs32 / WLC_TXPWR_DB_FACTOR,
+ fraction[txpwr->mcs32 % WLC_TXPWR_DB_FACTOR]);
+}
+#endif /* POWER_DBG */
+
+void
+wlc_channel_reg_limits(wlc_cm_info_t *wlc_cm, chanspec_t chanspec,
+ txpwr_limits_t *txpwr)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+ uint i;
+ uint chan;
+ int maxpwr;
+ int delta;
+ const country_info_t *country;
+ struct wlcband *band;
+ const locale_info_t *li;
+ int conducted_max;
+ int conducted_ofdm_max;
+ const locale_mimo_info_t *li_mimo;
+ int maxpwr20, maxpwr40;
+ int maxpwr_idx;
+ uint j;
+
+ memset(txpwr, 0, sizeof(txpwr_limits_t));
+
+ if (!wlc_valid_chanspec_db(wlc_cm, chanspec)) {
+ country = wlc_country_lookup(wlc, wlc->autocountry_default);
+ if (country == NULL)
+ return;
+ } else {
+ country = wlc_cm->country;
+ }
+
+ chan = CHSPEC_CHANNEL(chanspec);
+ band = wlc->bandstate[CHSPEC_WLCBANDUNIT(chanspec)];
+ li = BAND_5G(band->bandtype) ?
+ wlc_get_locale_5g(country->locale_5G) :
+ wlc_get_locale_2g(country->locale_2G);
+
+ li_mimo = BAND_5G(band->bandtype) ?
+ wlc_get_mimo_5g(country->locale_mimo_5G) :
+ wlc_get_mimo_2g(country->locale_mimo_2G);
+
+ if (li->flags & WLC_EIRP) {
+ delta = band->antgain;
+ } else {
+ delta = 0;
+ if (band->antgain > QDB(6))
+ delta = band->antgain - QDB(6); /* Excess over 6 dB */
+ }
+
+ if (li == &locale_i) {
+ conducted_max = QDB(22);
+ conducted_ofdm_max = QDB(22);
+ }
+
+ /* CCK txpwr limits for 2.4G band */
+ if (BAND_2G(band->bandtype)) {
+ maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_CCK(chan)];
+
+ maxpwr = maxpwr - delta;
+ maxpwr = max(maxpwr, 0);
+ maxpwr = min(maxpwr, conducted_max);
+
+ for (i = 0; i < WLC_NUM_RATES_CCK; i++)
+ txpwr->cck[i] = (u8) maxpwr;
+ }
+
+ /* OFDM txpwr limits for 2.4G or 5G bands */
+ if (BAND_2G(band->bandtype)) {
+ maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_OFDM(chan)];
+
+ } else {
+ maxpwr = li->maxpwr[CHANNEL_POWER_IDX_5G(chan)];
+ }
+
+ maxpwr = maxpwr - delta;
+ maxpwr = max(maxpwr, 0);
+ maxpwr = min(maxpwr, conducted_ofdm_max);
+
+ /* Keep OFDM lmit below CCK limit */
+ if (BAND_2G(band->bandtype))
+ maxpwr = min_t(int, maxpwr, txpwr->cck[0]);
+
+ for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
+ txpwr->ofdm[i] = (u8) maxpwr;
+ }
+
+ for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
+ /* OFDM 40 MHz SISO has the same power as the corresponding MCS0-7 rate unless
+ * overriden by the locale specific code. We set this value to 0 as a
+ * flag (presumably 0 dBm isn't a possibility) and then copy the MCS0-7 value
+ * to the 40 MHz value if it wasn't explicitly set.
+ */
+ txpwr->ofdm_40_siso[i] = 0;
+
+ txpwr->ofdm_cdd[i] = (u8) maxpwr;
+
+ txpwr->ofdm_40_cdd[i] = 0;
+ }
+
+ /* MIMO/HT specific limits */
+ if (li_mimo->flags & WLC_EIRP) {
+ delta = band->antgain;
+ } else {
+ delta = 0;
+ if (band->antgain > QDB(6))
+ delta = band->antgain - QDB(6); /* Excess over 6 dB */
+ }
+
+ if (BAND_2G(band->bandtype))
+ maxpwr_idx = (chan - 1);
+ else
+ maxpwr_idx = CHANNEL_POWER_IDX_5G(chan);
+
+ maxpwr20 = li_mimo->maxpwr20[maxpwr_idx];
+ maxpwr40 = li_mimo->maxpwr40[maxpwr_idx];
+
+ maxpwr20 = maxpwr20 - delta;
+ maxpwr20 = max(maxpwr20, 0);
+ maxpwr40 = maxpwr40 - delta;
+ maxpwr40 = max(maxpwr40, 0);
+
+ /* Fill in the MCS 0-7 (SISO) rates */
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+
+ /* 20 MHz has the same power as the corresponding OFDM rate unless
+ * overriden by the locale specific code.
+ */
+ txpwr->mcs_20_siso[i] = txpwr->ofdm[i];
+ txpwr->mcs_40_siso[i] = 0;
+ }
+
+ /* Fill in the MCS 0-7 CDD rates */
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ txpwr->mcs_20_cdd[i] = (u8) maxpwr20;
+ txpwr->mcs_40_cdd[i] = (u8) maxpwr40;
+ }
+
+ /* These locales have SISO expressed in the table and override CDD later */
+ if (li_mimo == &locale_bn) {
+ if (li_mimo == &locale_bn) {
+ maxpwr20 = QDB(16);
+ maxpwr40 = 0;
+
+ if (chan >= 3 && chan <= 11) {
+ maxpwr40 = QDB(16);
+ }
+ }
+
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ txpwr->mcs_20_siso[i] = (u8) maxpwr20;
+ txpwr->mcs_40_siso[i] = (u8) maxpwr40;
+ }
+ }
+
+ /* Fill in the MCS 0-7 STBC rates */
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ txpwr->mcs_20_stbc[i] = 0;
+ txpwr->mcs_40_stbc[i] = 0;
+ }
+
+ /* Fill in the MCS 8-15 SDM rates */
+ for (i = 0; i < WLC_NUM_RATES_MCS_2_STREAM; i++) {
+ txpwr->mcs_20_mimo[i] = (u8) maxpwr20;
+ txpwr->mcs_40_mimo[i] = (u8) maxpwr40;
+ }
+
+ /* Fill in MCS32 */
+ txpwr->mcs32 = (u8) maxpwr40;
+
+ for (i = 0, j = 0; i < WLC_NUM_RATES_OFDM; i++, j++) {
+ if (txpwr->ofdm_40_cdd[i] == 0)
+ txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j];
+ if (i == 0) {
+ i = i + 1;
+ if (txpwr->ofdm_40_cdd[i] == 0)
+ txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j];
+ }
+ }
+
+ /* Copy the 40 MHZ MCS 0-7 CDD value to the 40 MHZ MCS 0-7 SISO value if it wasn't
+ * provided explicitly.
+ */
+
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ if (txpwr->mcs_40_siso[i] == 0)
+ txpwr->mcs_40_siso[i] = txpwr->mcs_40_cdd[i];
+ }
+
+ for (i = 0, j = 0; i < WLC_NUM_RATES_OFDM; i++, j++) {
+ if (txpwr->ofdm_40_siso[i] == 0)
+ txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j];
+ if (i == 0) {
+ i = i + 1;
+ if (txpwr->ofdm_40_siso[i] == 0)
+ txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j];
+ }
+ }
+
+ /* Copy the 20 and 40 MHz MCS0-7 CDD values to the corresponding STBC values if they weren't
+ * provided explicitly.
+ */
+ for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
+ if (txpwr->mcs_20_stbc[i] == 0)
+ txpwr->mcs_20_stbc[i] = txpwr->mcs_20_cdd[i];
+
+ if (txpwr->mcs_40_stbc[i] == 0)
+ txpwr->mcs_40_stbc[i] = txpwr->mcs_40_cdd[i];
+ }
+
+#ifdef POWER_DBG
+ wlc_phy_txpower_limits_dump(txpwr);
+#endif
+ return;
+}
+
+/* Returns true if currently set country is Japan or variant */
+static bool wlc_japan(struct wlc_info *wlc)
+{
+ return wlc_japan_ccode(wlc->cmi->country_abbrev);
+}
+
+/* JP, J1 - J10 are Japan ccodes */
+static bool wlc_japan_ccode(const char *ccode)
+{
+ return (ccode[0] == 'J' &&
+ (ccode[1] == 'P' || (ccode[1] >= '1' && ccode[1] <= '9')));
+}
+
+/*
+ * Validate the chanspec for this locale, for 40MHZ we need to also check that the sidebands
+ * are valid 20MZH channels in this locale and they are also a legal HT combination
+ */
+static bool
+wlc_valid_chanspec_ext(wlc_cm_info_t *wlc_cm, chanspec_t chspec, bool dualband)
+{
+ struct wlc_info *wlc = wlc_cm->wlc;
+ u8 channel = CHSPEC_CHANNEL(chspec);
+
+ /* check the chanspec */
+ if (brcmu_chspec_malformed(chspec)) {
+ wiphy_err(wlc->wiphy, "wl%d: malformed chanspec 0x%x\n",
+ wlc->pub->unit, chspec);
+ return false;
+ }
+
+ if (CHANNEL_BANDUNIT(wlc_cm->wlc, channel) !=
+ CHSPEC_WLCBANDUNIT(chspec))
+ return false;
+
+ /* Check a 20Mhz channel */
+ if (CHSPEC_IS20(chspec)) {
+ if (dualband)
+ return VALID_CHANNEL20_DB(wlc_cm->wlc, channel);
+ else
+ return VALID_CHANNEL20(wlc_cm->wlc, channel);
+ }
+#ifdef SUPPORT_40MHZ
+ /* We know we are now checking a 40MHZ channel, so we should only be here
+ * for NPHYS
+ */
+ if (WLCISNPHY(wlc->band) || WLCISSSLPNPHY(wlc->band)) {
+ u8 upper_sideband = 0, idx;
+ u8 num_ch20_entries =
+ sizeof(chan20_info) / sizeof(struct chan20_info);
+
+ if (!VALID_40CHANSPEC_IN_BAND(wlc, CHSPEC_WLCBANDUNIT(chspec)))
+ return false;
+
+ if (dualband) {
+ if (!VALID_CHANNEL20_DB(wlc, LOWER_20_SB(channel)) ||
+ !VALID_CHANNEL20_DB(wlc, UPPER_20_SB(channel)))
+ return false;
+ } else {
+ if (!VALID_CHANNEL20(wlc, LOWER_20_SB(channel)) ||
+ !VALID_CHANNEL20(wlc, UPPER_20_SB(channel)))
+ return false;
+ }
+
+ /* find the lower sideband info in the sideband array */
+ for (idx = 0; idx < num_ch20_entries; idx++) {
+ if (chan20_info[idx].sb == LOWER_20_SB(channel))
+ upper_sideband = chan20_info[idx].adj_sbs;
+ }
+ /* check that the lower sideband allows an upper sideband */
+ if ((upper_sideband & (CH_UPPER_SB | CH_EWA_VALID)) ==
+ (CH_UPPER_SB | CH_EWA_VALID))
+ return true;
+ return false;
+ }
+#endif /* 40 MHZ */
+
+ return false;
+}
+
+bool wlc_valid_chanspec_db(wlc_cm_info_t *wlc_cm, chanspec_t chspec)
+{
+ return wlc_valid_chanspec_ext(wlc_cm, chspec, true);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_CHANNEL_H_
+#define _BRCM_CHANNEL_H_
+
+#define WLC_TXPWR_DB_FACTOR 4 /* conversion for phy txpwr cacluations that use .25 dB units */
+
+struct wlc_info;
+
+/* maxpwr mapping to 5GHz band channels:
+ * maxpwr[0] - channels [34-48]
+ * maxpwr[1] - channels [52-60]
+ * maxpwr[2] - channels [62-64]
+ * maxpwr[3] - channels [100-140]
+ * maxpwr[4] - channels [149-165]
+ */
+#define BAND_5G_PWR_LVLS 5 /* 5 power levels for 5G */
+
+/* power level in group of 2.4GHz band channels:
+ * maxpwr[0] - CCK channels [1]
+ * maxpwr[1] - CCK channels [2-10]
+ * maxpwr[2] - CCK channels [11-14]
+ * maxpwr[3] - OFDM channels [1]
+ * maxpwr[4] - OFDM channels [2-10]
+ * maxpwr[5] - OFDM channels [11-14]
+ */
+
+/* macro to get 2.4 GHz channel group index for tx power */
+#define CHANNEL_POWER_IDX_2G_CCK(c) (((c) < 2) ? 0 : (((c) < 11) ? 1 : 2)) /* cck index */
+#define CHANNEL_POWER_IDX_2G_OFDM(c) (((c) < 2) ? 3 : (((c) < 11) ? 4 : 5)) /* ofdm index */
+
+/* macro to get 5 GHz channel group index for tx power */
+#define CHANNEL_POWER_IDX_5G(c) \
+ (((c) < 52) ? 0 : (((c) < 62) ? 1 : (((c) < 100) ? 2 : (((c) < 149) ? 3 : 4))))
+
+#define WLC_MAXPWR_TBL_SIZE 6 /* max of BAND_5G_PWR_LVLS and 6 for 2.4 GHz */
+#define WLC_MAXPWR_MIMO_TBL_SIZE 14 /* max of BAND_5G_PWR_LVLS and 14 for 2.4 GHz */
+
+/* locale channel and power info. */
+typedef struct {
+ u32 valid_channels;
+ u8 radar_channels; /* List of radar sensitive channels */
+ u8 restricted_channels; /* List of channels used only if APs are detected */
+ s8 maxpwr[WLC_MAXPWR_TBL_SIZE]; /* Max tx pwr in qdBm for each sub-band */
+ s8 pub_maxpwr[BAND_5G_PWR_LVLS]; /* Country IE advertised max tx pwr in dBm
+ * per sub-band
+ */
+ u8 flags;
+} locale_info_t;
+
+/* bits for locale_info flags */
+#define WLC_PEAK_CONDUCTED 0x00 /* Peak for locals */
+#define WLC_EIRP 0x01 /* Flag for EIRP */
+#define WLC_DFS_TPC 0x02 /* Flag for DFS TPC */
+#define WLC_NO_OFDM 0x04 /* Flag for No OFDM */
+#define WLC_NO_40MHZ 0x08 /* Flag for No MIMO 40MHz */
+#define WLC_NO_MIMO 0x10 /* Flag for No MIMO, 20 or 40 MHz */
+#define WLC_RADAR_TYPE_EU 0x20 /* Flag for EU */
+#define WLC_DFS_FCC WLC_DFS_TPC /* Flag for DFS FCC */
+#define WLC_DFS_EU (WLC_DFS_TPC | WLC_RADAR_TYPE_EU) /* Flag for DFS EU */
+
+#define ISDFS_EU(fl) (((fl) & WLC_DFS_EU) == WLC_DFS_EU)
+
+/* locale per-channel tx power limits for MIMO frames
+ * maxpwr arrays are index by channel for 2.4 GHz limits, and
+ * by sub-band for 5 GHz limits using CHANNEL_POWER_IDX_5G(channel)
+ */
+typedef struct {
+ s8 maxpwr20[WLC_MAXPWR_MIMO_TBL_SIZE]; /* tx 20 MHz power limits, qdBm units */
+ s8 maxpwr40[WLC_MAXPWR_MIMO_TBL_SIZE]; /* tx 40 MHz power limits, qdBm units */
+ u8 flags;
+} locale_mimo_info_t;
+
+extern const chanvec_t chanvec_all_2G;
+extern const chanvec_t chanvec_all_5G;
+
+/*
+ * Country names and abbreviations with locale defined from ISO 3166
+ */
+struct country_info {
+ const u8 locale_2G; /* 2.4G band locale */
+ const u8 locale_5G; /* 5G band locale */
+ const u8 locale_mimo_2G; /* 2.4G mimo info */
+ const u8 locale_mimo_5G; /* 5G mimo info */
+};
+
+typedef struct country_info country_info_t;
+
+typedef struct wlc_cm_info wlc_cm_info_t;
+
+extern wlc_cm_info_t *wlc_channel_mgr_attach(struct wlc_info *wlc);
+extern void wlc_channel_mgr_detach(wlc_cm_info_t *wlc_cm);
+
+extern u8 wlc_channel_locale_flags_in_band(wlc_cm_info_t *wlc_cm,
+ uint bandunit);
+
+extern bool wlc_valid_chanspec_db(wlc_cm_info_t *wlc_cm, chanspec_t chspec);
+
+extern void wlc_channel_reg_limits(wlc_cm_info_t *wlc_cm,
+ chanspec_t chanspec,
+ struct txpwr_limits *txpwr);
+extern void wlc_channel_set_chanspec(wlc_cm_info_t *wlc_cm,
+ chanspec_t chanspec,
+ u8 local_constraint_qdbm);
+
+#endif /* _WLC_CHANNEL_H */
#include <linux/string.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
-#include <bcmdefs.h>
-#include <bcmdevs.h>
-#include <bcmsoc.h>
+#include <defs.h>
+#include <brcm_hw_ids.h>
+#include <soc.h>
#include <brcmu_utils.h>
#include <aiutils.h>
-#include "wlc_types.h"
-#include "bcmdma.h"
-#include <bcmdma.h>
+#include "types.h"
+#include "dma.h"
#if defined(__mips__)
#include <asm/addrspace.h>
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_DMA_H_
+#define _BRCM_DMA_H_
+
+#include "types.h" /* forward structure declarations */
+
+#ifndef _dma_pub_
+#define _dma_pub_
+struct dma_pub;
+#endif /* _dma_pub_ */
+
+/* DMA structure:
+ * support two DMA engines: 32 bits address or 64 bit addressing
+ * basic DMA register set is per channel(transmit or receive)
+ * a pair of channels is defined for convenience
+ */
+
+/* 32 bits addressing */
+
+typedef volatile struct { /* diag access */
+ u32 fifoaddr; /* diag address */
+ u32 fifodatalow; /* low 32bits of data */
+ u32 fifodatahigh; /* high 32bits of data */
+ u32 pad; /* reserved */
+} dma32diag_t;
+
+/* 64 bits addressing */
+
+/* dma registers per channel(xmt or rcv) */
+typedef volatile struct {
+ u32 control; /* enable, et al */
+ u32 ptr; /* last descriptor posted to chip */
+ u32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
+ u32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
+ u32 status0; /* current descriptor, xmt state */
+ u32 status1; /* active descriptor, xmt error */
+} dma64regs_t;
+
+/* map/unmap direction */
+#define DMA_TX 1 /* TX direction for DMA */
+#define DMA_RX 2 /* RX direction for DMA */
+#define BUS_SWAP32(v) (v)
+
+/* range param for dma_getnexttxp() and dma_txreclaim */
+typedef enum txd_range {
+ DMA_RANGE_ALL = 1,
+ DMA_RANGE_TRANSMITTED,
+ DMA_RANGE_TRANSFERED
+} txd_range_t;
+
+/* dma function type */
+typedef void (*di_detach_t) (struct dma_pub *dmah);
+typedef bool(*di_txreset_t) (struct dma_pub *dmah);
+typedef bool(*di_rxreset_t) (struct dma_pub *dmah);
+typedef bool(*di_rxidle_t) (struct dma_pub *dmah);
+typedef void (*di_txinit_t) (struct dma_pub *dmah);
+typedef bool(*di_txenabled_t) (struct dma_pub *dmah);
+typedef void (*di_rxinit_t) (struct dma_pub *dmah);
+typedef void (*di_txsuspend_t) (struct dma_pub *dmah);
+typedef void (*di_txresume_t) (struct dma_pub *dmah);
+typedef bool(*di_txsuspended_t) (struct dma_pub *dmah);
+typedef bool(*di_txsuspendedidle_t) (struct dma_pub *dmah);
+typedef int (*di_txfast_t) (struct dma_pub *dmah, struct sk_buff *p,
+ bool commit);
+typedef int (*di_txunframed_t) (struct dma_pub *dmah, void *p, uint len,
+ bool commit);
+typedef void *(*di_getpos_t) (struct dma_pub *di, bool direction);
+typedef void (*di_fifoloopbackenable_t) (struct dma_pub *dmah);
+typedef bool(*di_txstopped_t) (struct dma_pub *dmah);
+typedef bool(*di_rxstopped_t) (struct dma_pub *dmah);
+typedef bool(*di_rxenable_t) (struct dma_pub *dmah);
+typedef bool(*di_rxenabled_t) (struct dma_pub *dmah);
+typedef void *(*di_rx_t) (struct dma_pub *dmah);
+typedef bool(*di_rxfill_t) (struct dma_pub *dmah);
+typedef void (*di_txreclaim_t) (struct dma_pub *dmah, txd_range_t range);
+typedef void (*di_rxreclaim_t) (struct dma_pub *dmah);
+typedef unsigned long (*di_getvar_t) (struct dma_pub *dmah,
+ const char *name);
+typedef void *(*di_getnexttxp_t) (struct dma_pub *dmah, txd_range_t range);
+typedef void *(*di_getnextrxp_t) (struct dma_pub *dmah, bool forceall);
+typedef void *(*di_peeknexttxp_t) (struct dma_pub *dmah);
+typedef void *(*di_peeknextrxp_t) (struct dma_pub *dmah);
+typedef void (*di_rxparam_get_t) (struct dma_pub *dmah, u16 *rxoffset,
+ u16 *rxbufsize);
+typedef void (*di_txblock_t) (struct dma_pub *dmah);
+typedef void (*di_txunblock_t) (struct dma_pub *dmah);
+typedef uint(*di_txactive_t) (struct dma_pub *dmah);
+typedef void (*di_txrotate_t) (struct dma_pub *dmah);
+typedef void (*di_counterreset_t) (struct dma_pub *dmah);
+typedef uint(*di_ctrlflags_t) (struct dma_pub *dmah, uint mask, uint flags);
+typedef char *(*di_dump_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
+ bool dumpring);
+typedef char *(*di_dumptx_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
+ bool dumpring);
+typedef char *(*di_dumprx_t) (struct dma_pub *dmah, struct brcmu_strbuf *b,
+ bool dumpring);
+typedef uint(*di_rxactive_t) (struct dma_pub *dmah);
+typedef uint(*di_txpending_t) (struct dma_pub *dmah);
+typedef uint(*di_txcommitted_t) (struct dma_pub *dmah);
+
+/* dma opsvec */
+typedef struct di_fcn_s {
+ di_detach_t detach;
+ di_txinit_t txinit;
+ di_txreset_t txreset;
+ di_txenabled_t txenabled;
+ di_txsuspend_t txsuspend;
+ di_txresume_t txresume;
+ di_txsuspended_t txsuspended;
+ di_txsuspendedidle_t txsuspendedidle;
+ di_txfast_t txfast;
+ di_txunframed_t txunframed;
+ di_getpos_t getpos;
+ di_txstopped_t txstopped;
+ di_txreclaim_t txreclaim;
+ di_getnexttxp_t getnexttxp;
+ di_peeknexttxp_t peeknexttxp;
+ di_txblock_t txblock;
+ di_txunblock_t txunblock;
+ di_txactive_t txactive;
+ di_txrotate_t txrotate;
+
+ di_rxinit_t rxinit;
+ di_rxreset_t rxreset;
+ di_rxidle_t rxidle;
+ di_rxstopped_t rxstopped;
+ di_rxenable_t rxenable;
+ di_rxenabled_t rxenabled;
+ di_rx_t rx;
+ di_rxfill_t rxfill;
+ di_rxreclaim_t rxreclaim;
+ di_getnextrxp_t getnextrxp;
+ di_peeknextrxp_t peeknextrxp;
+ di_rxparam_get_t rxparam_get;
+
+ di_fifoloopbackenable_t fifoloopbackenable;
+ di_getvar_t d_getvar;
+ di_counterreset_t counterreset;
+ di_ctrlflags_t ctrlflags;
+ di_dump_t dump;
+ di_dumptx_t dumptx;
+ di_dumprx_t dumprx;
+ di_rxactive_t rxactive;
+ di_txpending_t txpending;
+ di_txcommitted_t txcommitted;
+ uint endnum;
+} di_fcn_t;
+
+/*
+ * Exported data structure (read-only)
+ */
+/* export structure */
+struct dma_pub {
+ const di_fcn_t *di_fn; /* DMA function pointers */
+ uint txavail; /* # free tx descriptors */
+ uint dmactrlflags; /* dma control flags */
+
+ /* rx error counters */
+ uint rxgiants; /* rx giant frames */
+ uint rxnobuf; /* rx out of dma descriptors */
+ /* tx error counters */
+ uint txnobuf; /* tx out of dma descriptors */
+};
+
+extern struct dma_pub *dma_attach(char *name, struct si_pub *sih,
+ void *dmaregstx, void *dmaregsrx, uint ntxd,
+ uint nrxd, uint rxbufsize, int rxextheadroom,
+ uint nrxpost, uint rxoffset, uint *msg_level);
+
+extern const di_fcn_t dma64proc;
+
+#define dma_detach(di) (dma64proc.detach(di))
+#define dma_txreset(di) (dma64proc.txreset(di))
+#define dma_rxreset(di) (dma64proc.rxreset(di))
+#define dma_rxidle(di) (dma64proc.rxidle(di))
+#define dma_txinit(di) (dma64proc.txinit(di))
+#define dma_txenabled(di) (dma64proc.txenabled(di))
+#define dma_rxinit(di) (dma64proc.rxinit(di))
+#define dma_txsuspend(di) (dma64proc.txsuspend(di))
+#define dma_txresume(di) (dma64proc.txresume(di))
+#define dma_txsuspended(di) (dma64proc.txsuspended(di))
+#define dma_txsuspendedidle(di) (dma64proc.txsuspendedidle(di))
+#define dma_txfast(di, p, commit) (dma64proc.txfast(di, p, commit))
+#define dma_txunframed(di, p, l, commit)(dma64proc.txunframed(di, p, l, commit))
+#define dma_getpos(di, dir) (dma64proc.getpos(di, dir))
+#define dma_fifoloopbackenable(di) (dma64proc.fifoloopbackenable(di))
+#define dma_txstopped(di) (dma64proc.txstopped(di))
+#define dma_rxstopped(di) (dma64proc.rxstopped(di))
+#define dma_rxenable(di) (dma64proc.rxenable(di))
+#define dma_rxenabled(di) (dma64proc.rxenabled(di))
+#define dma_rx(di) (dma64proc.rx(di))
+#define dma_rxfill(di) (dma64proc.rxfill(di))
+#define dma_txreclaim(di, range) (dma64proc.txreclaim(di, range))
+#define dma_rxreclaim(di) (dma64proc.rxreclaim(di))
+#define dma_getvar(di, name) (dma64proc.d_getvar(di, name))
+#define dma_getnexttxp(di, range) (dma64proc.getnexttxp(di, range))
+#define dma_getnextrxp(di, forceall) (dma64proc.getnextrxp(di, forceall))
+#define dma_peeknexttxp(di) (dma64proc.peeknexttxp(di))
+#define dma_peeknextrxp(di) (dma64proc.peeknextrxp(di))
+#define dma_rxparam_get(di, off, bufs) (dma64proc.rxparam_get(di, off, bufs))
+
+#define dma_txblock(di) (dma64proc.txblock(di))
+#define dma_txunblock(di) (dma64proc.txunblock(di))
+#define dma_txactive(di) (dma64proc.txactive(di))
+#define dma_rxactive(di) (dma64proc.rxactive(di))
+#define dma_txrotate(di) (dma64proc.txrotate(di))
+#define dma_counterreset(di) (dma64proc.counterreset(di))
+#define dma_ctrlflags(di, mask, flags) (dma64proc.ctrlflags((di), (mask), (flags)))
+#define dma_txpending(di) (dma64proc.txpending(di))
+#define dma_txcommitted(di) (dma64proc.txcommitted(di))
+
+
+/* return addresswidth allowed
+ * This needs to be done after SB attach but before dma attach.
+ * SB attach provides ability to probe backplane and dma core capabilities
+ * This info is needed by DMA_ALLOC_CONSISTENT in dma attach
+ */
+extern uint dma_addrwidth(struct si_pub *sih, void *dmaregs);
+void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
+ (void *pkt, void *arg_a), void *arg_a);
+
+/*
+ * DMA(Bug) on some chips seems to declare that the packet is ready, but the
+ * packet length is not updated yet (by DMA) on the expected time.
+ * Workaround is to hold processor till DMA updates the length, and stay off
+ * the bus to allow DMA update the length in buffer
+ */
+static inline void dma_spin_for_len(uint len, struct sk_buff *head)
+{
+#if defined(__mips__)
+ if (!len) {
+ while (!(len = *(u16 *) KSEG1ADDR(head->data)))
+ udelay(1);
+
+ *(u16 *) (head->data) = cpu_to_le16((u16) len);
+ }
+#endif /* defined(__mips__) */
+}
+
+#endif /* _BRCM_DMA_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_KEY_H_
+#define _BRCM_KEY_H_
+
+#include <linux/if_ether.h> /* for ETH_ALEN */
+
+struct scb;
+struct wlc_info;
+struct wlc_bsscfg;
+/* Maximum # of keys that wl driver supports in S/W.
+ * Keys supported in H/W is less than or equal to WSEC_MAX_KEYS.
+ */
+#define WSEC_MAX_KEYS 54 /* Max # of keys (50 + 4 default keys) */
+#define WLC_DEFAULT_KEYS 4 /* Default # of keys */
+
+#define WSEC_MAX_WOWL_KEYS 5 /* Max keys in WOWL mode (1 + 4 default keys) */
+
+#define WPA2_GTK_MAX 3
+
+/*
+* Max # of keys currently supported:
+*
+* s/w keys if WSEC_SW(wlc->wsec).
+* h/w keys otherwise.
+*/
+#define WLC_MAX_WSEC_KEYS(wlc) WSEC_MAX_KEYS
+
+/* number of 802.11 default (non-paired, group keys) */
+#define WSEC_MAX_DEFAULT_KEYS 4 /* # of default keys */
+
+/* Max # of hardware keys supported */
+#define WLC_MAX_WSEC_HW_KEYS(wlc) WSEC_MAX_RCMTA_KEYS
+
+/* Max # of hardware TKIP MIC keys supported */
+#define WLC_MAX_TKMIC_HW_KEYS(wlc) (WSEC_MAX_TKMIC_ENGINE_KEYS)
+
+#define WSEC_HW_TKMIC_KEY(wlc, key, bsscfg) \
+ ((((wlc)->machwcap & MCAP_TKIPMIC)) && \
+ (key) && ((key)->algo == CRYPTO_ALGO_TKIP) && \
+ !WSEC_SOFTKEY(wlc, key, bsscfg) && \
+ WSEC_KEY_INDEX(wlc, key) >= WLC_DEFAULT_KEYS && \
+ (WSEC_KEY_INDEX(wlc, key) < WSEC_MAX_TKMIC_ENGINE_KEYS))
+
+/* index of key in key table */
+#define WSEC_KEY_INDEX(wlc, key) ((key)->idx)
+
+#define WSEC_SOFTKEY(wlc, key, bsscfg) (WLC_SW_KEYS(wlc, bsscfg) || \
+ WSEC_KEY_INDEX(wlc, key) >= WLC_MAX_WSEC_HW_KEYS(wlc))
+
+/* get a key, non-NULL only if key allocated and not clear */
+#define WSEC_KEY(wlc, i) (((wlc)->wsec_keys[i] && (wlc)->wsec_keys[i]->len) ? \
+ (wlc)->wsec_keys[i] : NULL)
+
+#define WSEC_SCB_KEY_VALID(scb) (((scb)->key && (scb)->key->len) ? true : false)
+
+/* default key */
+#define WSEC_BSS_DEFAULT_KEY(bsscfg) (((bsscfg)->wsec_index == -1) ? \
+ (struct wsec_key *)NULL:(bsscfg)->bss_def_keys[(bsscfg)->wsec_index])
+
+/* Macros for key management in IBSS mode */
+#define WSEC_IBSS_MAX_PEERS 16 /* Max # of IBSS Peers */
+#define WSEC_IBSS_RCMTA_INDEX(idx) \
+ (((idx - WSEC_MAX_DEFAULT_KEYS) % WSEC_IBSS_MAX_PEERS) + WSEC_MAX_DEFAULT_KEYS)
+
+/* contiguous # key slots for infrastructure mode STA */
+#define WSEC_BSS_STA_KEY_GROUP_SIZE 5
+
+typedef struct wsec_iv {
+ u32 hi; /* upper 32 bits of IV */
+ u16 lo; /* lower 16 bits of IV */
+} wsec_iv_t;
+
+#define WLC_NUMRXIVS 16 /* # rx IVs (one per 802.11e TID) */
+
+typedef struct wsec_key {
+ u8 ea[ETH_ALEN]; /* per station */
+ u8 idx; /* key index in wsec_keys array */
+ u8 id; /* key ID [0-3] */
+ u8 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
+ u8 rcmta; /* rcmta entry index, same as idx by default */
+ u16 flags; /* misc flags */
+ u8 algo_hw; /* cache for hw register */
+ u8 aes_mode; /* cache for hw register */
+ s8 iv_len; /* IV length */
+ s8 icv_len; /* ICV length */
+ u32 len; /* key length..don't move this var */
+ /* data is 4byte aligned */
+ u8 data[WLAN_MAX_KEY_LEN]; /* key data */
+ wsec_iv_t rxiv[WLC_NUMRXIVS]; /* Rx IV (one per TID) */
+ wsec_iv_t txiv; /* Tx IV */
+
+} wsec_key_t;
+
+#define broken_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
+
+/* For use with wsec_key_t.flags */
+
+#define WSEC_BS_UPDATE (1 << 0) /* Indicates hw needs key update on BS switch */
+#define WSEC_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
+#define WSEC_TKIP_ERROR (1 << 2) /* Provoke deliberate MIC error */
+#define WSEC_REPLAY_ERROR (1 << 3) /* Provoke deliberate replay */
+#define WSEC_IBSS_PEER_GROUP_KEY (1 << 7) /* Flag: group key for a IBSS PEER */
+#define WSEC_ICV_ERROR (1 << 8) /* Provoke deliberate ICV error */
+
+#define wlc_key_insert(a, b, c, d, e, f, g, h, i, j) (-EBADE)
+#define wlc_key_update(a, b, c) do {} while (0)
+#define wlc_key_remove(a, b, c) do {} while (0)
+#define wlc_key_remove_all(a, b) do {} while (0)
+#define wlc_key_delete(a, b, c) do {} while (0)
+#define wlc_scb_key_delete(a, b) do {} while (0)
+#define wlc_key_lookup(a, b, c, d, e) (NULL)
+#define wlc_key_hw_init_all(a) do {} while (0)
+#define wlc_key_hw_init(a, b, c) do {} while (0)
+#define wlc_key_hw_wowl_init(a, b, c, d) do {} while (0)
+#define wlc_key_sw_wowl_update(a, b, c, d, e) do {} while (0)
+#define wlc_key_sw_wowl_create(a, b, c) (-EBADE)
+#define wlc_key_iv_update(a, b, c, d, e) do {(void)e; } while (0)
+#define wlc_key_iv_init(a, b, c) do {} while (0)
+#define wlc_key_set_error(a, b, c) (-EBADE)
+#define wlc_key_dump_hw(a, b) (-EBADE)
+#define wlc_key_dump_sw(a, b) (-EBADE)
+#define wlc_key_defkeyflag(a) (0)
+#define wlc_rcmta_add_bssid(a, b) do {} while (0)
+#define wlc_rcmta_del_bssid(a, b) do {} while (0)
+#define wlc_key_scb_delete(a, b) do {} while (0)
+
+#endif /* _BRCM_KEY_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define __UNDEF_NO_VERSION__
+
+#include <linux/kernel.h>
+#include <linux/etherdevice.h>
+#include <linux/types.h>
+#include <linux/pci_ids.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/sched.h>
+#include <linux/firmware.h>
+#include <net/mac80211.h>
+#include <defs.h>
+#include <brcmu_wifi.h>
+#include <brcmu_utils.h>
+#include <nicpci.h>
+#include "dma.h"
+
+#include "phy/phy_int.h"
+#include "d11.h"
+#include "types.h"
+#include "cfg.h"
+#include "key.h"
+#include "channel.h"
+#include "scb.h"
+#include "pub.h"
+#include "ucode_loader.h"
+#include "mac80211_if.h"
+
+#define N_TX_QUEUES 4 /* #tx queues on mac80211<->driver interface */
+
+#define LOCK(wl) spin_lock_bh(&(wl)->lock)
+#define UNLOCK(wl) spin_unlock_bh(&(wl)->lock)
+
+/* locking from inside brcms_isr */
+#define ISR_LOCK(wl, flags)\
+ do {\
+ spin_lock(&(wl)->isr_lock);\
+ (void)(flags); } \
+ while (0)
+
+#define ISR_UNLOCK(wl, flags)\
+ do {\
+ spin_unlock(&(wl)->isr_lock);\
+ (void)(flags); } \
+ while (0)
+
+/* locking under LOCK() to synchronize with brcms_isr */
+#define INT_LOCK(wl, flags) spin_lock_irqsave(&(wl)->isr_lock, flags)
+#define INT_UNLOCK(wl, flags) spin_unlock_irqrestore(&(wl)->isr_lock, flags)
+
+static void brcms_timer(unsigned long data);
+static void _brcms_timer(struct brcms_timer *t);
+
+
+static int ieee_hw_init(struct ieee80211_hw *hw);
+static int ieee_hw_rate_init(struct ieee80211_hw *hw);
+
+static int wl_linux_watchdog(void *ctx);
+
+/* Flags we support */
+#define MAC_FILTERS (FIF_PROMISC_IN_BSS | \
+ FIF_ALLMULTI | \
+ FIF_FCSFAIL | \
+ FIF_PLCPFAIL | \
+ FIF_CONTROL | \
+ FIF_OTHER_BSS | \
+ FIF_BCN_PRBRESP_PROMISC)
+
+static int n_adapters_found;
+
+static int brcms_request_fw(struct brcms_info *wl, struct pci_dev *pdev);
+static void brcms_release_fw(struct brcms_info *wl);
+
+/* local prototypes */
+static void brcms_dpc(unsigned long data);
+static irqreturn_t brcms_isr(int irq, void *dev_id);
+
+static int __devinit brcms_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *ent);
+static void brcms_remove(struct pci_dev *pdev);
+static void brcms_free(struct brcms_info *wl);
+static void brcms_set_basic_rate(struct wl_rateset *rs, u16 rate, bool is_br);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver.");
+MODULE_SUPPORTED_DEVICE("Broadcom 802.11n WLAN cards");
+MODULE_LICENSE("Dual BSD/GPL");
+
+/* recognized PCI IDs */
+static DEFINE_PCI_DEVICE_TABLE(brcms_pci_id_table) = {
+ {PCI_VENDOR_ID_BROADCOM, 0x4357, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, /* 43225 2G */
+ {PCI_VENDOR_ID_BROADCOM, 0x4353, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, /* 43224 DUAL */
+ {PCI_VENDOR_ID_BROADCOM, 0x4727, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, /* 4313 DUAL */
+ /* 43224 Ven */
+ {PCI_VENDOR_ID_BROADCOM, 0x0576, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+ {0}
+};
+
+MODULE_DEVICE_TABLE(pci, brcms_pci_id_table);
+
+#ifdef BCMDBG
+static int msglevel = 0xdeadbeef;
+module_param(msglevel, int, 0);
+static int phymsglevel = 0xdeadbeef;
+module_param(phymsglevel, int, 0);
+#endif /* BCMDBG */
+
+#define HW_TO_WL(hw) (hw->priv)
+#define WL_TO_HW(wl) (wl->pub->ieee_hw)
+
+/* MAC80211 callback functions */
+static int brcms_ops_start(struct ieee80211_hw *hw);
+static void brcms_ops_stop(struct ieee80211_hw *hw);
+static int brcms_ops_add_interface(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif);
+static void brcms_ops_remove_interface(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif);
+static int brcms_ops_config(struct ieee80211_hw *hw, u32 changed);
+static void brcms_ops_bss_info_changed(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *info,
+ u32 changed);
+static void brcms_ops_configure_filter(struct ieee80211_hw *hw,
+ unsigned int changed_flags,
+ unsigned int *total_flags, u64 multicast);
+static int brcms_ops_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
+ bool set);
+static void brcms_ops_sw_scan_start(struct ieee80211_hw *hw);
+static void brcms_ops_sw_scan_complete(struct ieee80211_hw *hw);
+static void brcms_ops_set_tsf(struct ieee80211_hw *hw, u64 tsf);
+static int brcms_ops_get_stats(struct ieee80211_hw *hw,
+ struct ieee80211_low_level_stats *stats);
+static void brcms_ops_sta_notify(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ enum sta_notify_cmd cmd,
+ struct ieee80211_sta *sta);
+static int brcms_ops_conf_tx(struct ieee80211_hw *hw, u16 queue,
+ const struct ieee80211_tx_queue_params *params);
+static u64 brcms_ops_get_tsf(struct ieee80211_hw *hw);
+static int brcms_ops_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta);
+static int brcms_ops_sta_remove(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta);
+static int brcms_ops_ampdu_action(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ enum ieee80211_ampdu_mlme_action action,
+ struct ieee80211_sta *sta, u16 tid, u16 *ssn,
+ u8 buf_size);
+static void brcms_ops_rfkill_poll(struct ieee80211_hw *hw);
+static void brcms_ops_flush(struct ieee80211_hw *hw, bool drop);
+
+static void brcms_ops_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+ struct brcms_info *wl = hw->priv;
+
+ LOCK(wl);
+ if (!wl->pub->up) {
+ wiphy_err(wl->wiphy, "ops->tx called while down\n");
+ kfree_skb(skb);
+ goto done;
+ }
+ wlc_sendpkt_mac80211(wl->wlc, skb, hw);
+ done:
+ UNLOCK(wl);
+}
+
+static int brcms_ops_start(struct ieee80211_hw *hw)
+{
+ struct brcms_info *wl = hw->priv;
+ bool blocked;
+ /*
+ struct ieee80211_channel *curchan = hw->conf.channel;
+ */
+
+ ieee80211_wake_queues(hw);
+ LOCK(wl);
+ blocked = brcms_rfkill_set_hw_state(wl);
+ UNLOCK(wl);
+ if (!blocked)
+ wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy);
+
+ return 0;
+}
+
+static void brcms_ops_stop(struct ieee80211_hw *hw)
+{
+ ieee80211_stop_queues(hw);
+}
+
+static int
+brcms_ops_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+{
+ struct brcms_info *wl;
+ int err;
+
+ /* Just STA for now */
+ if (vif->type != NL80211_IFTYPE_AP &&
+ vif->type != NL80211_IFTYPE_MESH_POINT &&
+ vif->type != NL80211_IFTYPE_STATION &&
+ vif->type != NL80211_IFTYPE_WDS &&
+ vif->type != NL80211_IFTYPE_ADHOC) {
+ wiphy_err(hw->wiphy, "%s: Attempt to add type %d, only"
+ " STA for now\n", __func__, vif->type);
+ return -EOPNOTSUPP;
+ }
+
+ wl = HW_TO_WL(hw);
+ LOCK(wl);
+ err = brcms_up(wl);
+ UNLOCK(wl);
+
+ if (err != 0) {
+ wiphy_err(hw->wiphy, "%s: brcms_up() returned %d\n", __func__,
+ err);
+ }
+ return err;
+}
+
+static void
+brcms_ops_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+{
+ struct brcms_info *wl;
+
+ wl = HW_TO_WL(hw);
+
+ /* put driver in down state */
+ LOCK(wl);
+ brcms_down(wl);
+ UNLOCK(wl);
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+static int
+ieee_set_channel(struct ieee80211_hw *hw, struct ieee80211_channel *chan,
+ enum nl80211_channel_type type)
+{
+ struct brcms_info *wl = HW_TO_WL(hw);
+ int err = 0;
+
+ switch (type) {
+ case NL80211_CHAN_HT20:
+ case NL80211_CHAN_NO_HT:
+ err = wlc_set(wl->wlc, WLC_SET_CHANNEL, chan->hw_value);
+ break;
+ case NL80211_CHAN_HT40MINUS:
+ case NL80211_CHAN_HT40PLUS:
+ wiphy_err(hw->wiphy,
+ "%s: Need to implement 40 Mhz Channels!\n", __func__);
+ err = 1;
+ break;
+ }
+
+ if (err)
+ return -EIO;
+ return err;
+}
+
+static int brcms_ops_config(struct ieee80211_hw *hw, u32 changed)
+{
+ struct ieee80211_conf *conf = &hw->conf;
+ struct brcms_info *wl = HW_TO_WL(hw);
+ int err = 0;
+ int new_int;
+ struct wiphy *wiphy = hw->wiphy;
+
+ LOCK(wl);
+ if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) {
+ if (wlc_set_par(wl->wlc, IOV_BCN_LI_BCN, conf->listen_interval)
+ < 0) {
+ wiphy_err(wiphy, "%s: Error setting listen_interval\n",
+ __func__);
+ err = -EIO;
+ goto config_out;
+ }
+ wlc_get_par(wl->wlc, IOV_BCN_LI_BCN, &new_int);
+ }
+ if (changed & IEEE80211_CONF_CHANGE_MONITOR)
+ wiphy_err(wiphy, "%s: change monitor mode: %s (implement)\n",
+ __func__, conf->flags & IEEE80211_CONF_MONITOR ?
+ "true" : "false");
+ if (changed & IEEE80211_CONF_CHANGE_PS)
+ wiphy_err(wiphy, "%s: change power-save mode: %s (implement)\n",
+ __func__, conf->flags & IEEE80211_CONF_PS ?
+ "true" : "false");
+
+ if (changed & IEEE80211_CONF_CHANGE_POWER) {
+ if (wlc_set_par(wl->wlc, IOV_QTXPOWER, conf->power_level * 4)
+ < 0) {
+ wiphy_err(wiphy, "%s: Error setting power_level\n",
+ __func__);
+ err = -EIO;
+ goto config_out;
+ }
+ wlc_get_par(wl->wlc, IOV_QTXPOWER, &new_int);
+ if (new_int != (conf->power_level * 4))
+ wiphy_err(wiphy, "%s: Power level req != actual, %d %d"
+ "\n", __func__, conf->power_level * 4,
+ new_int);
+ }
+ if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+ err = ieee_set_channel(hw, conf->channel, conf->channel_type);
+ }
+ if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
+ if (wlc_set
+ (wl->wlc, WLC_SET_SRL,
+ conf->short_frame_max_tx_count) < 0) {
+ wiphy_err(wiphy, "%s: Error setting srl\n", __func__);
+ err = -EIO;
+ goto config_out;
+ }
+ if (wlc_set(wl->wlc, WLC_SET_LRL, conf->long_frame_max_tx_count)
+ < 0) {
+ wiphy_err(wiphy, "%s: Error setting lrl\n", __func__);
+ err = -EIO;
+ goto config_out;
+ }
+ }
+
+ config_out:
+ UNLOCK(wl);
+ return err;
+}
+
+static void
+brcms_ops_bss_info_changed(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_bss_conf *info, u32 changed)
+{
+ struct brcms_info *wl = HW_TO_WL(hw);
+ struct wiphy *wiphy = hw->wiphy;
+ int val;
+
+ if (changed & BSS_CHANGED_ASSOC) {
+ /* association status changed (associated/disassociated)
+ * also implies a change in the AID.
+ */
+ wiphy_err(wiphy, "%s: %s: %sassociated\n", KBUILD_MODNAME,
+ __func__, info->assoc ? "" : "dis");
+ LOCK(wl);
+ wlc_associate_upd(wl->wlc, info->assoc);
+ UNLOCK(wl);
+ }
+ if (changed & BSS_CHANGED_ERP_SLOT) {
+ /* slot timing changed */
+ if (info->use_short_slot)
+ val = 1;
+ else
+ val = 0;
+ LOCK(wl);
+ wlc_set(wl->wlc, WLC_SET_SHORTSLOT_OVERRIDE, val);
+ UNLOCK(wl);
+ }
+
+ if (changed & BSS_CHANGED_HT) {
+ /* 802.11n parameters changed */
+ u16 mode = info->ht_operation_mode;
+
+ LOCK(wl);
+ wlc_protection_upd(wl->wlc, WLC_PROT_N_CFG,
+ mode & IEEE80211_HT_OP_MODE_PROTECTION);
+ wlc_protection_upd(wl->wlc, WLC_PROT_N_NONGF,
+ mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
+ wlc_protection_upd(wl->wlc, WLC_PROT_N_OBSS,
+ mode & IEEE80211_HT_OP_MODE_NON_HT_STA_PRSNT);
+ UNLOCK(wl);
+ }
+ if (changed & BSS_CHANGED_BASIC_RATES) {
+ struct ieee80211_supported_band *bi;
+ u32 br_mask, i;
+ u16 rate;
+ struct wl_rateset rs;
+ int error;
+
+ /* retrieve the current rates */
+ LOCK(wl);
+ error = wlc_ioctl(wl->wlc, WLC_GET_CURR_RATESET,
+ &rs, sizeof(rs), NULL);
+ UNLOCK(wl);
+ if (error) {
+ wiphy_err(wiphy, "%s: retrieve rateset failed: %d\n",
+ __func__, error);
+ return;
+ }
+ br_mask = info->basic_rates;
+ bi = hw->wiphy->bands[wlc_get_curband(wl->wlc)];
+ for (i = 0; i < bi->n_bitrates; i++) {
+ /* convert to internal rate value */
+ rate = (bi->bitrates[i].bitrate << 1) / 10;
+
+ /* set/clear basic rate flag */
+ brcms_set_basic_rate(&rs, rate, br_mask & 1);
+ br_mask >>= 1;
+ }
+
+ /* update the rate set */
+ LOCK(wl);
+ wlc_ioctl(wl->wlc, WLC_SET_RATESET, &rs, sizeof(rs), NULL);
+ UNLOCK(wl);
+ }
+ if (changed & BSS_CHANGED_BEACON_INT) {
+ /* Beacon interval changed */
+ LOCK(wl);
+ wlc_set(wl->wlc, WLC_SET_BCNPRD, info->beacon_int);
+ UNLOCK(wl);
+ }
+ if (changed & BSS_CHANGED_BSSID) {
+ /* BSSID changed, for whatever reason (IBSS and managed mode) */
+ LOCK(wl);
+ wlc_set_addrmatch(wl->wlc, RCM_BSSID_OFFSET,
+ info->bssid);
+ UNLOCK(wl);
+ }
+ if (changed & BSS_CHANGED_BEACON) {
+ /* Beacon data changed, retrieve new beacon (beaconing modes) */
+ wiphy_err(wiphy, "%s: beacon changed\n", __func__);
+ }
+ if (changed & BSS_CHANGED_BEACON_ENABLED) {
+ /* Beaconing should be enabled/disabled (beaconing modes) */
+ wiphy_err(wiphy, "%s: Beacon enabled: %s\n", __func__,
+ info->enable_beacon ? "true" : "false");
+ }
+ if (changed & BSS_CHANGED_CQM) {
+ /* Connection quality monitor config changed */
+ wiphy_err(wiphy, "%s: cqm change: threshold %d, hys %d "
+ " (implement)\n", __func__, info->cqm_rssi_thold,
+ info->cqm_rssi_hyst);
+ }
+ if (changed & BSS_CHANGED_IBSS) {
+ /* IBSS join status changed */
+ wiphy_err(wiphy, "%s: IBSS joined: %s (implement)\n", __func__,
+ info->ibss_joined ? "true" : "false");
+ }
+ if (changed & BSS_CHANGED_ARP_FILTER) {
+ /* Hardware ARP filter address list or state changed */
+ wiphy_err(wiphy, "%s: arp filtering: enabled %s, count %d"
+ " (implement)\n", __func__, info->arp_filter_enabled ?
+ "true" : "false", info->arp_addr_cnt);
+ }
+ if (changed & BSS_CHANGED_QOS) {
+ /*
+ * QoS for this association was enabled/disabled.
+ * Note that it is only ever disabled for station mode.
+ */
+ wiphy_err(wiphy, "%s: qos enabled: %s (implement)\n", __func__,
+ info->qos ? "true" : "false");
+ }
+ if (changed & BSS_CHANGED_IDLE) {
+ /* Idle changed for this BSS/interface */
+ wiphy_err(wiphy, "%s: BSS idle: %s (implement)\n", __func__,
+ info->idle ? "true" : "false");
+ }
+ return;
+}
+
+static void
+brcms_ops_configure_filter(struct ieee80211_hw *hw,
+ unsigned int changed_flags,
+ unsigned int *total_flags, u64 multicast)
+{
+ struct brcms_info *wl = hw->priv;
+ struct wiphy *wiphy = hw->wiphy;
+
+ changed_flags &= MAC_FILTERS;
+ *total_flags &= MAC_FILTERS;
+ if (changed_flags & FIF_PROMISC_IN_BSS)
+ wiphy_err(wiphy, "FIF_PROMISC_IN_BSS\n");
+ if (changed_flags & FIF_ALLMULTI)
+ wiphy_err(wiphy, "FIF_ALLMULTI\n");
+ if (changed_flags & FIF_FCSFAIL)
+ wiphy_err(wiphy, "FIF_FCSFAIL\n");
+ if (changed_flags & FIF_PLCPFAIL)
+ wiphy_err(wiphy, "FIF_PLCPFAIL\n");
+ if (changed_flags & FIF_CONTROL)
+ wiphy_err(wiphy, "FIF_CONTROL\n");
+ if (changed_flags & FIF_OTHER_BSS)
+ wiphy_err(wiphy, "FIF_OTHER_BSS\n");
+ if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
+ LOCK(wl);
+ if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
+ wl->pub->mac80211_state |= MAC80211_PROMISC_BCNS;
+ wlc_mac_bcn_promisc_change(wl->wlc, 1);
+ } else {
+ wlc_mac_bcn_promisc_change(wl->wlc, 0);
+ wl->pub->mac80211_state &= ~MAC80211_PROMISC_BCNS;
+ }
+ UNLOCK(wl);
+ }
+ return;
+}
+
+static int
+brcms_ops_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set)
+{
+ return 0;
+}
+
+static void brcms_ops_sw_scan_start(struct ieee80211_hw *hw)
+{
+ struct brcms_info *wl = hw->priv;
+ LOCK(wl);
+ wlc_scan_start(wl->wlc);
+ UNLOCK(wl);
+ return;
+}
+
+static void brcms_ops_sw_scan_complete(struct ieee80211_hw *hw)
+{
+ struct brcms_info *wl = hw->priv;
+ LOCK(wl);
+ wlc_scan_stop(wl->wlc);
+ UNLOCK(wl);
+ return;
+}
+
+static void brcms_ops_set_tsf(struct ieee80211_hw *hw, u64 tsf)
+{
+ wiphy_err(hw->wiphy, "%s: Enter\n", __func__);
+ return;
+}
+
+static int
+brcms_ops_get_stats(struct ieee80211_hw *hw,
+ struct ieee80211_low_level_stats *stats)
+{
+ struct brcms_info *wl = hw->priv;
+ struct wl_cnt *cnt;
+
+ LOCK(wl);
+ cnt = wl->pub->_cnt;
+ stats->dot11ACKFailureCount = 0;
+ stats->dot11RTSFailureCount = 0;
+ stats->dot11FCSErrorCount = 0;
+ stats->dot11RTSSuccessCount = 0;
+ UNLOCK(wl);
+ return 0;
+}
+
+static void
+brcms_ops_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
+{
+ switch (cmd) {
+ default:
+ wiphy_err(hw->wiphy, "%s: Unknown cmd = %d\n", __func__,
+ cmd);
+ break;
+ }
+ return;
+}
+
+static int
+brcms_ops_conf_tx(struct ieee80211_hw *hw, u16 queue,
+ const struct ieee80211_tx_queue_params *params)
+{
+ struct brcms_info *wl = hw->priv;
+
+ LOCK(wl);
+ wlc_wme_setparams(wl->wlc, queue, params, true);
+ UNLOCK(wl);
+
+ return 0;
+}
+
+static u64 brcms_ops_get_tsf(struct ieee80211_hw *hw)
+{
+ wiphy_err(hw->wiphy, "%s: Enter\n", __func__);
+ return 0;
+}
+
+static int
+brcms_ops_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta)
+{
+ struct scb *scb;
+
+ int i;
+ struct brcms_info *wl = hw->priv;
+
+ /* Init the scb */
+ scb = (struct scb *)sta->drv_priv;
+ memset(scb, 0, sizeof(struct scb));
+ for (i = 0; i < NUMPRIO; i++)
+ scb->seqctl[i] = 0xFFFF;
+ scb->seqctl_nonqos = 0xFFFF;
+ scb->magic = SCB_MAGIC;
+
+ wl->pub->global_scb = scb;
+ wl->pub->global_ampdu = &(scb->scb_ampdu);
+ wl->pub->global_ampdu->scb = scb;
+ wl->pub->global_ampdu->max_pdu = 16;
+ brcmu_pktq_init(&scb->scb_ampdu.txq, AMPDU_MAX_SCB_TID,
+ AMPDU_MAX_SCB_TID * PKTQ_LEN_DEFAULT);
+
+ sta->ht_cap.ht_supported = true;
+ sta->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
+ sta->ht_cap.ampdu_density = AMPDU_DEF_MPDU_DENSITY;
+ sta->ht_cap.cap = IEEE80211_HT_CAP_GRN_FLD |
+ IEEE80211_HT_CAP_SGI_20 |
+ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT;
+
+ /* minstrel_ht initiates addBA on our behalf by calling ieee80211_start_tx_ba_session() */
+ return 0;
+}
+
+static int
+brcms_ops_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta)
+{
+ return 0;
+}
+
+static int
+brcms_ops_ampdu_action(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ enum ieee80211_ampdu_mlme_action action,
+ struct ieee80211_sta *sta, u16 tid, u16 *ssn,
+ u8 buf_size)
+{
+ struct scb *scb = (struct scb *)sta->drv_priv;
+ struct brcms_info *wl = hw->priv;
+ int status;
+
+ if (WARN_ON(scb->magic != SCB_MAGIC))
+ return -EIDRM;
+ switch (action) {
+ case IEEE80211_AMPDU_RX_START:
+ break;
+ case IEEE80211_AMPDU_RX_STOP:
+ break;
+ case IEEE80211_AMPDU_TX_START:
+ LOCK(wl);
+ status = wlc_aggregatable(wl->wlc, tid);
+ UNLOCK(wl);
+ if (!status) {
+ wiphy_err(wl->wiphy, "START: tid %d is not agg\'able\n",
+ tid);
+ return -EINVAL;
+ }
+ /* XXX: Use the starting sequence number provided ... */
+ *ssn = 0;
+ ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+ break;
+
+ case IEEE80211_AMPDU_TX_STOP:
+ LOCK(wl);
+ wlc_ampdu_flush(wl->wlc, sta, tid);
+ UNLOCK(wl);
+ ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
+ break;
+ case IEEE80211_AMPDU_TX_OPERATIONAL:
+ /* Not sure what to do here */
+ /* Power save wakeup */
+ break;
+ default:
+ wiphy_err(wl->wiphy, "%s: Invalid command, ignoring\n",
+ __func__);
+ }
+
+ return 0;
+}
+
+static void brcms_ops_rfkill_poll(struct ieee80211_hw *hw)
+{
+ struct brcms_info *wl = HW_TO_WL(hw);
+ bool blocked;
+
+ LOCK(wl);
+ blocked = wlc_check_radio_disabled(wl->wlc);
+ UNLOCK(wl);
+
+ wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, blocked);
+}
+
+static void brcms_ops_flush(struct ieee80211_hw *hw, bool drop)
+{
+ struct brcms_info *wl = HW_TO_WL(hw);
+
+ no_printk("%s: drop = %s\n", __func__, drop ? "true" : "false");
+
+ /* wait for packet queue and dma fifos to run empty */
+ LOCK(wl);
+ wlc_wait_for_tx_completion(wl->wlc, drop);
+ UNLOCK(wl);
+}
+
+static const struct ieee80211_ops brcms_ops = {
+ .tx = brcms_ops_tx,
+ .start = brcms_ops_start,
+ .stop = brcms_ops_stop,
+ .add_interface = brcms_ops_add_interface,
+ .remove_interface = brcms_ops_remove_interface,
+ .config = brcms_ops_config,
+ .bss_info_changed = brcms_ops_bss_info_changed,
+ .configure_filter = brcms_ops_configure_filter,
+ .set_tim = brcms_ops_set_tim,
+ .sw_scan_start = brcms_ops_sw_scan_start,
+ .sw_scan_complete = brcms_ops_sw_scan_complete,
+ .set_tsf = brcms_ops_set_tsf,
+ .get_stats = brcms_ops_get_stats,
+ .sta_notify = brcms_ops_sta_notify,
+ .conf_tx = brcms_ops_conf_tx,
+ .get_tsf = brcms_ops_get_tsf,
+ .sta_add = brcms_ops_sta_add,
+ .sta_remove = brcms_ops_sta_remove,
+ .ampdu_action = brcms_ops_ampdu_action,
+ .rfkill_poll = brcms_ops_rfkill_poll,
+ .flush = brcms_ops_flush,
+};
+
+/*
+ * is called in brcms_pci_probe() context, therefore no locking required.
+ */
+static int brcms_set_hint(struct brcms_info *wl, char *abbrev)
+{
+ return regulatory_hint(wl->pub->ieee_hw->wiphy, abbrev);
+}
+
+/**
+ * attach to the WL device.
+ *
+ * Attach to the WL device identified by vendor and device parameters.
+ * regs is a host accessible memory address pointing to WL device registers.
+ *
+ * brcms_attach is not defined as static because in the case where no bus
+ * is defined, wl_attach will never be called, and thus, gcc will issue
+ * a warning that this function is defined but not used if we declare
+ * it as static.
+ *
+ *
+ * is called in brcms_pci_probe() context, therefore no locking required.
+ */
+static struct brcms_info *brcms_attach(u16 vendor, u16 device,
+ unsigned long regs,
+ uint bustype, void *btparam, uint irq)
+{
+ struct brcms_info *wl = NULL;
+ int unit, err;
+ unsigned long base_addr;
+ struct ieee80211_hw *hw;
+ u8 perm[ETH_ALEN];
+
+ unit = n_adapters_found;
+ err = 0;
+
+ if (unit < 0) {
+ return NULL;
+ }
+
+ /* allocate private info */
+ hw = pci_get_drvdata(btparam); /* btparam == pdev */
+ if (hw != NULL)
+ wl = hw->priv;
+ if (WARN_ON(hw == NULL) || WARN_ON(wl == NULL))
+ return NULL;
+ wl->wiphy = hw->wiphy;
+
+ atomic_set(&wl->callbacks, 0);
+
+ /* setup the bottom half handler */
+ tasklet_init(&wl->tasklet, brcms_dpc, (unsigned long) wl);
+
+
+
+ base_addr = regs;
+
+ if (bustype == PCI_BUS || bustype == RPC_BUS) {
+ /* Do nothing */
+ } else {
+ bustype = PCI_BUS;
+ BCMMSG(wl->wiphy, "force to PCI\n");
+ }
+ wl->bcm_bustype = bustype;
+
+ wl->regsva = ioremap_nocache(base_addr, PCI_BAR0_WINSZ);
+ if (wl->regsva == NULL) {
+ wiphy_err(wl->wiphy, "wl%d: ioremap() failed\n", unit);
+ goto fail;
+ }
+ spin_lock_init(&wl->lock);
+ spin_lock_init(&wl->isr_lock);
+
+ /* prepare ucode */
+ if (brcms_request_fw(wl, (struct pci_dev *)btparam) < 0) {
+ wiphy_err(wl->wiphy, "%s: Failed to find firmware usually in "
+ "%s\n", KBUILD_MODNAME, "/lib/firmware/brcm");
+ brcms_release_fw(wl);
+ brcms_remove((struct pci_dev *)btparam);
+ return NULL;
+ }
+
+ /* common load-time initialization */
+ wl->wlc = wlc_attach((void *)wl, vendor, device, unit, false,
+ wl->regsva, wl->bcm_bustype, btparam, &err);
+ brcms_release_fw(wl);
+ if (!wl->wlc) {
+ wiphy_err(wl->wiphy, "%s: wlc_attach() failed with code %d\n",
+ KBUILD_MODNAME, err);
+ goto fail;
+ }
+ wl->pub = wlc_pub(wl->wlc);
+
+ wl->pub->ieee_hw = hw;
+
+ if (wlc_set_par(wl->wlc, IOV_MPC, 0) < 0) {
+ wiphy_err(wl->wiphy, "wl%d: Error setting MPC variable to 0\n",
+ unit);
+ }
+
+ /* register our interrupt handler */
+ if (request_irq(irq, brcms_isr, IRQF_SHARED, KBUILD_MODNAME, wl)) {
+ wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit);
+ goto fail;
+ }
+ wl->irq = irq;
+
+ /* register module */
+ wlc_module_register(wl->pub, "linux", wl, wl_linux_watchdog, NULL);
+
+ if (ieee_hw_init(hw)) {
+ wiphy_err(wl->wiphy, "wl%d: %s: ieee_hw_init failed!\n", unit,
+ __func__);
+ goto fail;
+ }
+
+ memcpy(perm, &wl->pub->cur_etheraddr, ETH_ALEN);
+ if (WARN_ON(!is_valid_ether_addr(perm)))
+ goto fail;
+ SET_IEEE80211_PERM_ADDR(hw, perm);
+
+ err = ieee80211_register_hw(hw);
+ if (err) {
+ wiphy_err(wl->wiphy, "%s: ieee80211_register_hw failed, status"
+ "%d\n", __func__, err);
+ }
+
+ if (wl->pub->srom_ccode[0])
+ err = brcms_set_hint(wl, wl->pub->srom_ccode);
+ else
+ err = brcms_set_hint(wl, "US");
+ if (err) {
+ wiphy_err(wl->wiphy, "%s: regulatory_hint failed, status %d\n",
+ __func__, err);
+ }
+
+ n_adapters_found++;
+ return wl;
+
+fail:
+ brcms_free(wl);
+ return NULL;
+}
+
+
+
+#define CHAN2GHZ(channel, freqency, chflags) { \
+ .band = IEEE80211_BAND_2GHZ, \
+ .center_freq = (freqency), \
+ .hw_value = (channel), \
+ .flags = chflags, \
+ .max_antenna_gain = 0, \
+ .max_power = 19, \
+}
+
+static struct ieee80211_channel brcms_2ghz_chantable[] = {
+ CHAN2GHZ(1, 2412, IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN2GHZ(2, 2417, IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN2GHZ(3, 2422, IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN2GHZ(4, 2427, IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN2GHZ(5, 2432, 0),
+ CHAN2GHZ(6, 2437, 0),
+ CHAN2GHZ(7, 2442, 0),
+ CHAN2GHZ(8, 2447, IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN2GHZ(9, 2452, IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN2GHZ(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN2GHZ(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN2GHZ(12, 2467,
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN2GHZ(13, 2472,
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN2GHZ(14, 2484,
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS)
+};
+
+#define CHAN5GHZ(channel, chflags) { \
+ .band = IEEE80211_BAND_5GHZ, \
+ .center_freq = 5000 + 5*(channel), \
+ .hw_value = (channel), \
+ .flags = chflags, \
+ .max_antenna_gain = 0, \
+ .max_power = 21, \
+}
+
+static struct ieee80211_channel brcms_5ghz_nphy_chantable[] = {
+ /* UNII-1 */
+ CHAN5GHZ(36, IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(40, IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(44, IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(48, IEEE80211_CHAN_NO_HT40PLUS),
+ /* UNII-2 */
+ CHAN5GHZ(52,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(56,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(60,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(64,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
+ /* MID */
+ CHAN5GHZ(100,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(104,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(108,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(112,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(116,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(120,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(124,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(128,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(132,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(136,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(140,
+ IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_IBSS |
+ IEEE80211_CHAN_PASSIVE_SCAN | IEEE80211_CHAN_NO_HT40PLUS |
+ IEEE80211_CHAN_NO_HT40MINUS),
+ /* UNII-3 */
+ CHAN5GHZ(149, IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(153, IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(157, IEEE80211_CHAN_NO_HT40MINUS),
+ CHAN5GHZ(161, IEEE80211_CHAN_NO_HT40PLUS),
+ CHAN5GHZ(165, IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS)
+};
+
+#define RATE(rate100m, _flags) { \
+ .bitrate = (rate100m), \
+ .flags = (_flags), \
+ .hw_value = (rate100m / 5), \
+}
+
+static struct ieee80211_rate legacy_ratetable[] = {
+ RATE(10, 0),
+ RATE(20, IEEE80211_RATE_SHORT_PREAMBLE),
+ RATE(55, IEEE80211_RATE_SHORT_PREAMBLE),
+ RATE(110, IEEE80211_RATE_SHORT_PREAMBLE),
+ RATE(60, 0),
+ RATE(90, 0),
+ RATE(120, 0),
+ RATE(180, 0),
+ RATE(240, 0),
+ RATE(360, 0),
+ RATE(480, 0),
+ RATE(540, 0),
+};
+
+static struct ieee80211_supported_band brcms_band_2GHz_nphy = {
+ .band = IEEE80211_BAND_2GHZ,
+ .channels = brcms_2ghz_chantable,
+ .n_channels = ARRAY_SIZE(brcms_2ghz_chantable),
+ .bitrates = legacy_ratetable,
+ .n_bitrates = ARRAY_SIZE(legacy_ratetable),
+ .ht_cap = {
+ /* from include/linux/ieee80211.h */
+ .cap = IEEE80211_HT_CAP_GRN_FLD |
+ IEEE80211_HT_CAP_SGI_20 |
+ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT,
+ .ht_supported = true,
+ .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
+ .ampdu_density = AMPDU_DEF_MPDU_DENSITY,
+ .mcs = {
+ /* placeholders for now */
+ .rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
+ .rx_highest = 500,
+ .tx_params = IEEE80211_HT_MCS_TX_DEFINED}
+ }
+};
+
+static struct ieee80211_supported_band brcms_band_5GHz_nphy = {
+ .band = IEEE80211_BAND_5GHZ,
+ .channels = brcms_5ghz_nphy_chantable,
+ .n_channels = ARRAY_SIZE(brcms_5ghz_nphy_chantable),
+ .bitrates = legacy_ratetable + 4,
+ .n_bitrates = ARRAY_SIZE(legacy_ratetable) - 4,
+ .ht_cap = {
+ /* use IEEE80211_HT_CAP_* from include/linux/ieee80211.h */
+ .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_40MHZ_INTOLERANT, /* No 40 mhz yet */
+ .ht_supported = true,
+ .ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
+ .ampdu_density = AMPDU_DEF_MPDU_DENSITY,
+ .mcs = {
+ /* placeholders for now */
+ .rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
+ .rx_highest = 500,
+ .tx_params = IEEE80211_HT_MCS_TX_DEFINED}
+ }
+};
+
+/*
+ * is called in brcms_pci_probe() context, therefore no locking required.
+ */
+static int ieee_hw_rate_init(struct ieee80211_hw *hw)
+{
+ struct brcms_info *wl = HW_TO_WL(hw);
+ int has_5g;
+ char phy_list[4];
+
+ has_5g = 0;
+
+ hw->wiphy->bands[IEEE80211_BAND_2GHZ] = NULL;
+ hw->wiphy->bands[IEEE80211_BAND_5GHZ] = NULL;
+
+ if (wlc_get(wl->wlc, WLC_GET_PHYLIST, (int *)&phy_list) < 0) {
+ wiphy_err(hw->wiphy, "Phy list failed\n");
+ }
+
+ if (phy_list[0] == 'n' || phy_list[0] == 'c') {
+ if (phy_list[0] == 'c') {
+ /* Single stream */
+ brcms_band_2GHz_nphy.ht_cap.mcs.rx_mask[1] = 0;
+ brcms_band_2GHz_nphy.ht_cap.mcs.rx_highest = 72;
+ }
+ hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &brcms_band_2GHz_nphy;
+ } else {
+ return -EPERM;
+ }
+
+ /* Assume all bands use the same phy. True for 11n devices. */
+ if (NBANDS_PUB(wl->pub) > 1) {
+ has_5g++;
+ if (phy_list[0] == 'n' || phy_list[0] == 'c') {
+ hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
+ &brcms_band_5GHz_nphy;
+ } else {
+ return -EPERM;
+ }
+ }
+ return 0;
+}
+
+/*
+ * is called in brcms_pci_probe() context, therefore no locking required.
+ */
+static int ieee_hw_init(struct ieee80211_hw *hw)
+{
+ hw->flags = IEEE80211_HW_SIGNAL_DBM
+ /* | IEEE80211_HW_CONNECTION_MONITOR What is this? */
+ | IEEE80211_HW_REPORTS_TX_ACK_STATUS
+ | IEEE80211_HW_AMPDU_AGGREGATION;
+
+ hw->extra_tx_headroom = wlc_get_header_len();
+ hw->queues = N_TX_QUEUES;
+ /* FIXME: this doesn't seem to be used properly in minstrel_ht.
+ * mac80211/status.c:ieee80211_tx_status() checks this value,
+ * but mac80211/rc80211_minstrel_ht.c:minstrel_ht_get_rate()
+ * appears to always set 3 rates
+ */
+ hw->max_rates = 2; /* Primary rate and 1 fallback rate */
+
+ hw->channel_change_time = 7 * 1000; /* channel change time is dependent on chip and band */
+ hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
+
+ hw->rate_control_algorithm = "minstrel_ht";
+
+ hw->sta_data_size = sizeof(struct scb);
+ return ieee_hw_rate_init(hw);
+}
+
+/**
+ * determines if a device is a WL device, and if so, attaches it.
+ *
+ * This function determines if a device pointed to by pdev is a WL device,
+ * and if so, performs a brcms_attach() on it.
+ *
+ * Perimeter lock is initialized in the course of this function.
+ */
+static int __devinit
+brcms_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ int rc;
+ struct brcms_info *wl;
+ struct ieee80211_hw *hw;
+ u32 val;
+
+ dev_info(&pdev->dev, "bus %d slot %d func %d irq %d\n",
+ pdev->bus->number, PCI_SLOT(pdev->devfn),
+ PCI_FUNC(pdev->devfn), pdev->irq);
+
+ if ((pdev->vendor != PCI_VENDOR_ID_BROADCOM) ||
+ ((pdev->device != 0x0576) &&
+ ((pdev->device & 0xff00) != 0x4300) &&
+ ((pdev->device & 0xff00) != 0x4700) &&
+ ((pdev->device < 43000) || (pdev->device > 43999))))
+ return -ENODEV;
+
+ rc = pci_enable_device(pdev);
+ if (rc) {
+ pr_err("%s: Cannot enable device %d-%d_%d\n",
+ __func__, pdev->bus->number, PCI_SLOT(pdev->devfn),
+ PCI_FUNC(pdev->devfn));
+ return -ENODEV;
+ }
+ pci_set_master(pdev);
+
+ pci_read_config_dword(pdev, 0x40, &val);
+ if ((val & 0x0000ff00) != 0)
+ pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
+
+ hw = ieee80211_alloc_hw(sizeof(struct brcms_info), &brcms_ops);
+ if (!hw) {
+ pr_err("%s: ieee80211_alloc_hw failed\n", __func__);
+ return -ENOMEM;
+ }
+
+ SET_IEEE80211_DEV(hw, &pdev->dev);
+
+ pci_set_drvdata(pdev, hw);
+
+ memset(hw->priv, 0, sizeof(*wl));
+
+ wl = brcms_attach(pdev->vendor, pdev->device,
+ pci_resource_start(pdev, 0), PCI_BUS, pdev,
+ pdev->irq);
+
+ if (!wl) {
+ pr_err("%s: %s: brcms_attach failed!\n", KBUILD_MODNAME,
+ __func__);
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static int brcms_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct brcms_info *wl;
+ struct ieee80211_hw *hw;
+
+ hw = pci_get_drvdata(pdev);
+ wl = HW_TO_WL(hw);
+ if (!wl) {
+ wiphy_err(wl->wiphy,
+ "brcms_suspend: pci_get_drvdata failed\n");
+ return -ENODEV;
+ }
+
+ /* only need to flag hw is down for proper resume */
+ LOCK(wl);
+ wl->pub->hw_up = false;
+ UNLOCK(wl);
+
+ pci_save_state(pdev);
+ pci_disable_device(pdev);
+ return pci_set_power_state(pdev, PCI_D3hot);
+}
+
+static int brcms_resume(struct pci_dev *pdev)
+{
+ struct brcms_info *wl;
+ struct ieee80211_hw *hw;
+ int err = 0;
+ u32 val;
+
+ hw = pci_get_drvdata(pdev);
+ wl = HW_TO_WL(hw);
+ if (!wl) {
+ wiphy_err(wl->wiphy,
+ "wl: brcms_resume: pci_get_drvdata failed\n");
+ return -ENODEV;
+ }
+
+ err = pci_set_power_state(pdev, PCI_D0);
+ if (err)
+ return err;
+
+ pci_restore_state(pdev);
+
+ err = pci_enable_device(pdev);
+ if (err)
+ return err;
+
+ pci_set_master(pdev);
+
+ pci_read_config_dword(pdev, 0x40, &val);
+ if ((val & 0x0000ff00) != 0)
+ pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
+
+ /*
+ * done. driver will be put in up state
+ * in brcms_ops_add_interface() call.
+ */
+ return err;
+}
+
+/*
+* called from both kernel as from this kernel module.
+* precondition: perimeter lock is not acquired.
+*/
+static void brcms_remove(struct pci_dev *pdev)
+{
+ struct brcms_info *wl;
+ struct ieee80211_hw *hw;
+ int status;
+
+ hw = pci_get_drvdata(pdev);
+ wl = HW_TO_WL(hw);
+ if (!wl) {
+ pr_err("wl: brcms_remove: pci_get_drvdata failed\n");
+ return;
+ }
+
+ LOCK(wl);
+ status = wlc_chipmatch(pdev->vendor, pdev->device);
+ UNLOCK(wl);
+ if (!status) {
+ wiphy_err(wl->wiphy, "wl: brcms_remove: wlc_chipmatch "
+ "failed\n");
+ return;
+ }
+ if (wl->wlc) {
+ wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, false);
+ wiphy_rfkill_stop_polling(wl->pub->ieee_hw->wiphy);
+ ieee80211_unregister_hw(hw);
+ LOCK(wl);
+ brcms_down(wl);
+ UNLOCK(wl);
+ }
+ pci_disable_device(pdev);
+
+ brcms_free(wl);
+
+ pci_set_drvdata(pdev, NULL);
+ ieee80211_free_hw(hw);
+}
+
+static struct pci_driver brcms_pci_driver = {
+ .name = KBUILD_MODNAME,
+ .probe = brcms_pci_probe,
+ .suspend = brcms_suspend,
+ .resume = brcms_resume,
+ .remove = __devexit_p(brcms_remove),
+ .id_table = brcms_pci_id_table,
+};
+
+/**
+ * This is the main entry point for the WL driver.
+ *
+ * This function determines if a device pointed to by pdev is a WL device,
+ * and if so, performs a brcms_attach() on it.
+ *
+ */
+static int __init brcms_module_init(void)
+{
+ int error = -ENODEV;
+
+#ifdef BCMDBG
+ if (msglevel != 0xdeadbeef)
+ brcm_msg_level = msglevel;
+ if (phymsglevel != 0xdeadbeef)
+ phyhal_msg_level = phymsglevel;
+#endif /* BCMDBG */
+
+ error = pci_register_driver(&brcms_pci_driver);
+ if (!error)
+ return 0;
+
+
+
+ return error;
+}
+
+/**
+ * This function unloads the WL driver from the system.
+ *
+ * This function unconditionally unloads the WL driver module from the
+ * system.
+ *
+ */
+static void __exit brcms_module_exit(void)
+{
+ pci_unregister_driver(&brcms_pci_driver);
+
+}
+
+module_init(brcms_module_init);
+module_exit(brcms_module_exit);
+
+/**
+ * This function frees the WL per-device resources.
+ *
+ * This function frees resources owned by the WL device pointed to
+ * by the wl parameter.
+ *
+ * precondition: can both be called locked and unlocked
+ *
+ */
+static void brcms_free(struct brcms_info *wl)
+{
+ struct brcms_timer *t, *next;
+
+ /* free ucode data */
+ if (wl->fw.fw_cnt)
+ brcms_ucode_data_free();
+ if (wl->irq)
+ free_irq(wl->irq, wl);
+
+ /* kill dpc */
+ tasklet_kill(&wl->tasklet);
+
+ if (wl->pub) {
+ wlc_module_unregister(wl->pub, "linux", wl);
+ }
+
+ /* free common resources */
+ if (wl->wlc) {
+ wlc_detach(wl->wlc);
+ wl->wlc = NULL;
+ wl->pub = NULL;
+ }
+
+ /* virtual interface deletion is deferred so we cannot spinwait */
+
+ /* wait for all pending callbacks to complete */
+ while (atomic_read(&wl->callbacks) > 0)
+ schedule();
+
+ /* free timers */
+ for (t = wl->timers; t; t = next) {
+ next = t->next;
+#ifdef BCMDBG
+ kfree(t->name);
+#endif
+ kfree(t);
+ }
+
+ /*
+ * unregister_netdev() calls get_stats() which may read chip registers
+ * so we cannot unmap the chip registers until after calling unregister_netdev() .
+ */
+ if (wl->regsva && wl->bcm_bustype != SDIO_BUS &&
+ wl->bcm_bustype != JTAG_BUS) {
+ iounmap((void *)wl->regsva);
+ }
+ wl->regsva = NULL;
+}
+
+/* flags the given rate in rateset as requested */
+static void brcms_set_basic_rate(struct wl_rateset *rs, u16 rate, bool is_br)
+{
+ u32 i;
+
+ for (i = 0; i < rs->count; i++) {
+ if (rate != (rs->rates[i] & 0x7f))
+ continue;
+
+ if (is_br)
+ rs->rates[i] |= WLC_RATE_FLAG;
+ else
+ rs->rates[i] &= WLC_RATE_MASK;
+ return;
+ }
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
+ bool state, int prio)
+{
+ wiphy_err(wl->wiphy, "Shouldn't be here %s\n", __func__);
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+void brcms_init(struct brcms_info *wl)
+{
+ BCMMSG(WL_TO_HW(wl)->wiphy, "wl%d\n", wl->pub->unit);
+ brcms_reset(wl);
+
+ wlc_init(wl->wlc);
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+uint brcms_reset(struct brcms_info *wl)
+{
+ BCMMSG(WL_TO_HW(wl)->wiphy, "wl%d\n", wl->pub->unit);
+ wlc_reset(wl->wlc);
+
+ /* dpc will not be rescheduled */
+ wl->resched = 0;
+
+ return 0;
+}
+
+/*
+ * These are interrupt on/off entry points. Disable interrupts
+ * during interrupt state transition.
+ */
+void brcms_intrson(struct brcms_info *wl)
+{
+ unsigned long flags;
+
+ INT_LOCK(wl, flags);
+ wlc_intrson(wl->wlc);
+ INT_UNLOCK(wl, flags);
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+bool wl_alloc_dma_resources(struct brcms_info *wl, uint addrwidth)
+{
+ return true;
+}
+
+u32 brcms_intrsoff(struct brcms_info *wl)
+{
+ unsigned long flags;
+ u32 status;
+
+ INT_LOCK(wl, flags);
+ status = wlc_intrsoff(wl->wlc);
+ INT_UNLOCK(wl, flags);
+ return status;
+}
+
+void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask)
+{
+ unsigned long flags;
+
+ INT_LOCK(wl, flags);
+ wlc_intrsrestore(wl->wlc, macintmask);
+ INT_UNLOCK(wl, flags);
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+int brcms_up(struct brcms_info *wl)
+{
+ int error = 0;
+
+ if (wl->pub->up)
+ return 0;
+
+ error = wlc_up(wl->wlc);
+
+ return error;
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+void brcms_down(struct brcms_info *wl)
+{
+ uint callbacks, ret_val = 0;
+
+ /* call common down function */
+ ret_val = wlc_down(wl->wlc);
+ callbacks = atomic_read(&wl->callbacks) - ret_val;
+
+ /* wait for down callbacks to complete */
+ UNLOCK(wl);
+
+ /* For HIGH_only driver, it's important to actually schedule other work,
+ * not just spin wait since everything runs at schedule level
+ */
+ SPINWAIT((atomic_read(&wl->callbacks) > callbacks), 100 * 1000);
+
+ LOCK(wl);
+}
+
+static irqreturn_t brcms_isr(int irq, void *dev_id)
+{
+ struct brcms_info *wl;
+ bool ours, wantdpc;
+ unsigned long flags;
+
+ wl = (struct brcms_info *) dev_id;
+
+ ISR_LOCK(wl, flags);
+
+ /* call common first level interrupt handler */
+ ours = wlc_isr(wl->wlc, &wantdpc);
+ if (ours) {
+ /* if more to do... */
+ if (wantdpc) {
+
+ /* ...and call the second level interrupt handler */
+ /* schedule dpc */
+ tasklet_schedule(&wl->tasklet);
+ }
+ }
+
+ ISR_UNLOCK(wl, flags);
+
+ return IRQ_RETVAL(ours);
+}
+
+static void brcms_dpc(unsigned long data)
+{
+ struct brcms_info *wl;
+
+ wl = (struct brcms_info *) data;
+
+ LOCK(wl);
+
+ /* call the common second level interrupt handler */
+ if (wl->pub->up) {
+ if (wl->resched) {
+ unsigned long flags;
+
+ INT_LOCK(wl, flags);
+ wlc_intrsupd(wl->wlc);
+ INT_UNLOCK(wl, flags);
+ }
+
+ wl->resched = wlc_dpc(wl->wlc, true);
+ }
+
+ /* wlc_dpc() may bring the driver down */
+ if (!wl->pub->up)
+ goto done;
+
+ /* re-schedule dpc */
+ if (wl->resched)
+ tasklet_schedule(&wl->tasklet);
+ else {
+ /* re-enable interrupts */
+ brcms_intrson(wl);
+ }
+
+ done:
+ UNLOCK(wl);
+}
+
+/*
+ * is called by the kernel from software irq context
+ */
+static void brcms_timer(unsigned long data)
+{
+ _brcms_timer((struct brcms_timer *) data);
+}
+
+/*
+* precondition: perimeter lock is not acquired
+ */
+static void _brcms_timer(struct brcms_timer *t)
+{
+ LOCK(t->wl);
+
+ if (t->set) {
+ if (t->periodic) {
+ t->timer.expires = jiffies + t->ms * HZ / 1000;
+ atomic_inc(&t->wl->callbacks);
+ add_timer(&t->timer);
+ t->set = true;
+ } else
+ t->set = false;
+
+ t->fn(t->arg);
+ }
+
+ atomic_dec(&t->wl->callbacks);
+
+ UNLOCK(t->wl);
+}
+
+/*
+ * Adds a timer to the list. Caller supplies a timer function.
+ * Is called from wlc.
+ *
+ * precondition: perimeter lock has been acquired
+ */
+struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
+ void (*fn) (void *arg),
+ void *arg, const char *name)
+{
+ struct brcms_timer *t;
+
+ t = kzalloc(sizeof(struct brcms_timer), GFP_ATOMIC);
+ if (!t) {
+ wiphy_err(wl->wiphy, "wl%d: brcms_init_timer: out of memory\n",
+ wl->pub->unit);
+ return 0;
+ }
+
+ init_timer(&t->timer);
+ t->timer.data = (unsigned long) t;
+ t->timer.function = brcms_timer;
+ t->wl = wl;
+ t->fn = fn;
+ t->arg = arg;
+ t->next = wl->timers;
+ wl->timers = t;
+
+#ifdef BCMDBG
+ t->name = kmalloc(strlen(name) + 1, GFP_ATOMIC);
+ if (t->name)
+ strcpy(t->name, name);
+#endif
+
+ return t;
+}
+
+/* BMAC_NOTE: Add timer adds only the kernel timer since it's going to be more accurate
+ * as well as it's easier to make it periodic
+ *
+ * precondition: perimeter lock has been acquired
+ */
+void brcms_add_timer(struct brcms_info *wl, struct brcms_timer *t, uint ms,
+ int periodic)
+{
+#ifdef BCMDBG
+ if (t->set) {
+ wiphy_err(wl->wiphy, "%s: Already set. Name: %s, per %d\n",
+ __func__, t->name, periodic);
+ }
+#endif
+ t->ms = ms;
+ t->periodic = (bool) periodic;
+ t->set = true;
+ t->timer.expires = jiffies + ms * HZ / 1000;
+
+ atomic_inc(&wl->callbacks);
+ add_timer(&t->timer);
+}
+
+/*
+ * return true if timer successfully deleted, false if still pending
+ *
+ * precondition: perimeter lock has been acquired
+ */
+bool brcms_del_timer(struct brcms_info *wl, struct brcms_timer *t)
+{
+ if (t->set) {
+ t->set = false;
+ if (!del_timer(&t->timer)) {
+ return false;
+ }
+ atomic_dec(&wl->callbacks);
+ }
+
+ return true;
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+void brcms_free_timer(struct brcms_info *wl, struct brcms_timer *t)
+{
+ struct brcms_timer *tmp;
+
+ /* delete the timer in case it is active */
+ brcms_del_timer(wl, t);
+
+ if (wl->timers == t) {
+ wl->timers = wl->timers->next;
+#ifdef BCMDBG
+ kfree(t->name);
+#endif
+ kfree(t);
+ return;
+
+ }
+
+ tmp = wl->timers;
+ while (tmp) {
+ if (tmp->next == t) {
+ tmp->next = t->next;
+#ifdef BCMDBG
+ kfree(t->name);
+#endif
+ kfree(t);
+ return;
+ }
+ tmp = tmp->next;
+ }
+
+}
+
+/*
+ * runs in software irq context
+ *
+ * precondition: perimeter lock is not acquired
+ */
+static int wl_linux_watchdog(void *ctx)
+{
+ return 0;
+}
+
+struct firmware_hdr {
+ u32 offset;
+ u32 len;
+ u32 idx;
+};
+
+char *brcms_firmwares[MAX_FW_IMAGES] = {
+ "brcm/bcm43xx",
+ NULL
+};
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+int brcms_ucode_init_buf(struct brcms_info *wl, void **pbuf, u32 idx)
+{
+ int i, entry;
+ const u8 *pdata;
+ struct firmware_hdr *hdr;
+ for (i = 0; i < wl->fw.fw_cnt; i++) {
+ hdr = (struct firmware_hdr *)wl->fw.fw_hdr[i]->data;
+ for (entry = 0; entry < wl->fw.hdr_num_entries[i];
+ entry++, hdr++) {
+ if (hdr->idx == idx) {
+ pdata = wl->fw.fw_bin[i]->data + hdr->offset;
+ *pbuf = kmalloc(hdr->len, GFP_ATOMIC);
+ if (*pbuf == NULL) {
+ wiphy_err(wl->wiphy, "fail to alloc %d"
+ " bytes\n", hdr->len);
+ goto fail;
+ }
+ memcpy(*pbuf, pdata, hdr->len);
+ return 0;
+ }
+ }
+ }
+ wiphy_err(wl->wiphy, "ERROR: ucode buf tag:%d can not be found!\n",
+ idx);
+ *pbuf = NULL;
+fail:
+ return -ENODATA;
+}
+
+/*
+ * Precondition: Since this function is called in brcms_pci_probe() context,
+ * no locking is required.
+ */
+int brcms_ucode_init_uint(struct brcms_info *wl, u32 *data, u32 idx)
+{
+ int i, entry;
+ const u8 *pdata;
+ struct firmware_hdr *hdr;
+ for (i = 0; i < wl->fw.fw_cnt; i++) {
+ hdr = (struct firmware_hdr *)wl->fw.fw_hdr[i]->data;
+ for (entry = 0; entry < wl->fw.hdr_num_entries[i];
+ entry++, hdr++) {
+ if (hdr->idx == idx) {
+ pdata = wl->fw.fw_bin[i]->data + hdr->offset;
+ if (hdr->len != 4) {
+ wiphy_err(wl->wiphy,
+ "ERROR: fw hdr len\n");
+ return -ENOMSG;
+ }
+ *data = *((u32 *) pdata);
+ return 0;
+ }
+ }
+ }
+ wiphy_err(wl->wiphy, "ERROR: ucode tag:%d can not be found!\n", idx);
+ return -ENOMSG;
+}
+
+/*
+ * Precondition: Since this function is called in brcms_pci_probe() context,
+ * no locking is required.
+ */
+static int brcms_request_fw(struct brcms_info *wl, struct pci_dev *pdev)
+{
+ int status;
+ struct device *device = &pdev->dev;
+ char fw_name[100];
+ int i;
+
+ memset((void *)&wl->fw, 0, sizeof(struct brcms_firmware));
+ for (i = 0; i < MAX_FW_IMAGES; i++) {
+ if (brcms_firmwares[i] == NULL)
+ break;
+ sprintf(fw_name, "%s-%d.fw", brcms_firmwares[i],
+ UCODE_LOADER_API_VER);
+ status = request_firmware(&wl->fw.fw_bin[i], fw_name, device);
+ if (status) {
+ wiphy_err(wl->wiphy, "%s: fail to load firmware %s\n",
+ KBUILD_MODNAME, fw_name);
+ return status;
+ }
+ sprintf(fw_name, "%s_hdr-%d.fw", brcms_firmwares[i],
+ UCODE_LOADER_API_VER);
+ status = request_firmware(&wl->fw.fw_hdr[i], fw_name, device);
+ if (status) {
+ wiphy_err(wl->wiphy, "%s: fail to load firmware %s\n",
+ KBUILD_MODNAME, fw_name);
+ return status;
+ }
+ wl->fw.hdr_num_entries[i] =
+ wl->fw.fw_hdr[i]->size / (sizeof(struct firmware_hdr));
+ }
+ wl->fw.fw_cnt = i;
+ return brcms_ucode_data_init(wl);
+}
+
+/*
+ * precondition: can both be called locked and unlocked
+ */
+void brcms_ucode_free_buf(void *p)
+{
+ kfree(p);
+}
+
+/*
+ * Precondition: Since this function is called in brcms_pci_probe() context,
+ * no locking is required.
+ */
+static void brcms_release_fw(struct brcms_info *wl)
+{
+ int i;
+ for (i = 0; i < MAX_FW_IMAGES; i++) {
+ release_firmware(wl->fw.fw_bin[i]);
+ release_firmware(wl->fw.fw_hdr[i]);
+ }
+}
+
+
+/*
+ * checks validity of all firmware images loaded from user space
+ *
+ * Precondition: Since this function is called in brcms_pci_probe() context,
+ * no locking is required.
+ */
+int brcms_check_firmwares(struct brcms_info *wl)
+{
+ int i;
+ int entry;
+ int rc = 0;
+ const struct firmware *fw;
+ const struct firmware *fw_hdr;
+ struct firmware_hdr *ucode_hdr;
+ for (i = 0; i < MAX_FW_IMAGES && rc == 0; i++) {
+ fw = wl->fw.fw_bin[i];
+ fw_hdr = wl->fw.fw_hdr[i];
+ if (fw == NULL && fw_hdr == NULL) {
+ break;
+ } else if (fw == NULL || fw_hdr == NULL) {
+ wiphy_err(wl->wiphy, "%s: invalid bin/hdr fw\n",
+ __func__);
+ rc = -EBADF;
+ } else if (fw_hdr->size % sizeof(struct firmware_hdr)) {
+ wiphy_err(wl->wiphy, "%s: non integral fw hdr file "
+ "size %zu/%zu\n", __func__, fw_hdr->size,
+ sizeof(struct firmware_hdr));
+ rc = -EBADF;
+ } else if (fw->size < MIN_FW_SIZE || fw->size > MAX_FW_SIZE) {
+ wiphy_err(wl->wiphy, "%s: out of bounds fw file size "
+ "%zu\n", __func__, fw->size);
+ rc = -EBADF;
+ } else {
+ /* check if ucode section overruns firmware image */
+ ucode_hdr = (struct firmware_hdr *)fw_hdr->data;
+ for (entry = 0; entry < wl->fw.hdr_num_entries[i] &&
+ !rc; entry++, ucode_hdr++) {
+ if (ucode_hdr->offset + ucode_hdr->len >
+ fw->size) {
+ wiphy_err(wl->wiphy,
+ "%s: conflicting bin/hdr\n",
+ __func__);
+ rc = -EBADF;
+ }
+ }
+ }
+ }
+ if (rc == 0 && wl->fw.fw_cnt != i) {
+ wiphy_err(wl->wiphy, "%s: invalid fw_cnt=%d\n", __func__,
+ wl->fw.fw_cnt);
+ rc = -EBADF;
+ }
+ return rc;
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+bool brcms_rfkill_set_hw_state(struct brcms_info *wl)
+{
+ bool blocked = wlc_check_radio_disabled(wl->wlc);
+
+ UNLOCK(wl);
+ wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, blocked);
+ if (blocked)
+ wiphy_rfkill_start_polling(wl->pub->ieee_hw->wiphy);
+ LOCK(wl);
+ return blocked;
+}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+void brcms_msleep(struct brcms_info *wl, uint ms)
+{
+ UNLOCK(wl);
+ msleep(ms);
+ LOCK(wl);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_MAC80211_IF_H_
+#define _BRCM_MAC80211_IF_H_
+
+/* softmac ioctl definitions */
+#define WLC_SET_SHORTSLOT_OVERRIDE 146
+
+
+/* BMAC Note: High-only driver is no longer working in softirq context as it needs to block and
+ * sleep so perimeter lock has to be a semaphore instead of spinlock. This requires timers to be
+ * submitted to workqueue instead of being on kernel timer
+ */
+struct brcms_timer {
+ struct timer_list timer;
+ struct brcms_info *wl;
+ void (*fn) (void *);
+ void *arg; /* argument to fn */
+ uint ms;
+ bool periodic;
+ bool set;
+ struct brcms_timer *next;
+#ifdef BCMDBG
+ char *name; /* Description of the timer */
+#endif
+};
+
+struct brcms_if {
+ uint subunit; /* WDS/BSS unit */
+ struct pci_dev *pci_dev;
+};
+
+#define MAX_FW_IMAGES 4
+struct brcms_firmware {
+ u32 fw_cnt;
+ const struct firmware *fw_bin[MAX_FW_IMAGES];
+ const struct firmware *fw_hdr[MAX_FW_IMAGES];
+ u32 hdr_num_entries[MAX_FW_IMAGES];
+};
+
+struct brcms_info {
+ struct wlc_pub *pub; /* pointer to public wlc state */
+ void *wlc; /* pointer to private common os-independent data */
+ u32 magic;
+
+ int irq;
+
+ spinlock_t lock; /* per-device perimeter lock */
+ spinlock_t isr_lock; /* per-device ISR synchronization lock */
+
+ /* bus type and regsva for unmap in brcms_free() */
+ uint bcm_bustype; /* bus type */
+ void *regsva; /* opaque chip registers virtual address */
+
+ /* timer related fields */
+ atomic_t callbacks; /* # outstanding callback functions */
+ struct brcms_timer *timers; /* timer cleanup queue */
+
+ struct tasklet_struct tasklet; /* dpc tasklet */
+ bool resched; /* dpc needs to be and is rescheduled */
+#ifdef LINUXSTA_PS
+ u32 pci_psstate[16]; /* pci ps-state save/restore */
+#endif
+ struct brcms_firmware fw;
+ struct wiphy *wiphy;
+};
+
+/* misc callbacks */
+struct brcms_info;
+struct brcms_if;
+struct wlc_if;
+extern void brcms_init(struct brcms_info *wl);
+extern uint brcms_reset(struct brcms_info *wl);
+extern void brcms_intrson(struct brcms_info *wl);
+extern u32 brcms_intrsoff(struct brcms_info *wl);
+extern void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask);
+extern int brcms_up(struct brcms_info *wl);
+extern void brcms_down(struct brcms_info *wl);
+extern void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
+ bool state, int prio);
+extern bool wl_alloc_dma_resources(struct brcms_info *wl, uint dmaddrwidth);
+extern bool brcms_rfkill_set_hw_state(struct brcms_info *wl);
+
+/* timer functions */
+struct brcms_timer;
+extern struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
+ void (*fn) (void *arg), void *arg,
+ const char *name);
+extern void brcms_free_timer(struct brcms_info *wl, struct brcms_timer *timer);
+extern void brcms_add_timer(struct brcms_info *wl, struct brcms_timer *timer,
+ uint ms, int periodic);
+extern bool brcms_del_timer(struct brcms_info *wl, struct brcms_timer *timer);
+extern void brcms_msleep(struct brcms_info *wl, uint ms);
+
+#endif /* _BRCM_MAC80211_IF_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <linux/ctype.h>
+#include <linux/etherdevice.h>
+#include <linux/pci_ids.h>
+#include <net/mac80211.h>
+
+#include <defs.h>
+#include <brcm_hw_ids.h>
+#include <brcmu_utils.h>
+#include <brcmu_wifi.h>
+#include <aiutils.h>
+#include <srom.h>
+#include "dma.h"
+
+#include "pmu.h"
+#include "d11.h"
+#include "types.h"
+#include "cfg.h"
+#include "rate.h"
+#include "scb.h"
+#include "pub.h"
+#include "key.h"
+#include "bsscfg.h"
+#include "phy/phy_hal.h"
+#include "channel.h"
+#include "main.h"
+#include "bottom_mac.h"
+#include "phy_hal.h"
+#include "antsel.h"
+#include "stf.h"
+#include "ampdu.h"
+#include "alloc.h"
+#include "mac80211_if.h"
+
+/*
+ * WPA(2) definitions
+ */
+#define RSN_CAP_4_REPLAY_CNTRS 2
+#define RSN_CAP_16_REPLAY_CNTRS 3
+
+#define WPA_CAP_4_REPLAY_CNTRS RSN_CAP_4_REPLAY_CNTRS
+#define WPA_CAP_16_REPLAY_CNTRS RSN_CAP_16_REPLAY_CNTRS
+
+/*
+ * Indication for txflowcontrol that all priority bits in
+ * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
+ */
+#define ALLPRIO -1
+
+/*
+ * 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
+ */
+#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
+
+#define TIMER_INTERVAL_WATCHDOG 1000 /* watchdog timer, in unit of ms */
+#define TIMER_INTERVAL_RADIOCHK 800 /* radio monitor timer, in unit of ms */
+
+#ifndef WLC_MPC_MAX_DELAYCNT
+#define WLC_MPC_MAX_DELAYCNT 10 /* Max MPC timeout, in unit of watchdog */
+#endif
+#define WLC_MPC_MIN_DELAYCNT 1 /* Min MPC timeout, in unit of watchdog */
+#define WLC_MPC_THRESHOLD 3 /* MPC count threshold level */
+
+#define BEACON_INTERVAL_DEFAULT 100 /* beacon interval, in unit of 1024TU */
+#define DTIM_INTERVAL_DEFAULT 3 /* DTIM interval, in unit of beacon interval */
+
+/* Scale down delays to accommodate QT slow speed */
+#define BEACON_INTERVAL_DEF_QT 20 /* beacon interval, in unit of 1024TU */
+#define DTIM_INTERVAL_DEF_QT 1 /* DTIM interval, in unit of beacon interval */
+
+#define TBTT_ALIGN_LEEWAY_US 100 /* min leeway before first TBTT in us */
+
+/* Software feature flag defines used by wlfeatureflag */
+#define WL_SWFL_NOHWRADIO 0x0004
+#define WL_SWFL_FLOWCONTROL 0x0008 /* Enable backpressure to OS stack */
+#define WL_SWFL_WLBSSSORT 0x0010 /* Per-port supports sorting of BSS */
+
+/* n-mode support capability */
+/* 2x2 includes both 1x1 & 2x2 devices
+ * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
+ * control it independently
+ */
+#define WL_11N_2x2 1
+#define WL_11N_3x3 3
+#define WL_11N_4x4 4
+
+/* define 11n feature disable flags */
+#define WLFEATURE_DISABLE_11N 0x00000001
+#define WLFEATURE_DISABLE_11N_STBC_TX 0x00000002
+#define WLFEATURE_DISABLE_11N_STBC_RX 0x00000004
+#define WLFEATURE_DISABLE_11N_SGI_TX 0x00000008
+#define WLFEATURE_DISABLE_11N_SGI_RX 0x00000010
+#define WLFEATURE_DISABLE_11N_AMPDU_TX 0x00000020
+#define WLFEATURE_DISABLE_11N_AMPDU_RX 0x00000040
+#define WLFEATURE_DISABLE_11N_GF 0x00000080
+
+#define EDCF_ACI_MASK 0x60
+#define EDCF_ACI_SHIFT 5
+#define EDCF_ECWMIN_MASK 0x0f
+#define EDCF_ECWMAX_SHIFT 4
+#define EDCF_AIFSN_MASK 0x0f
+#define EDCF_AIFSN_MAX 15
+#define EDCF_ECWMAX_MASK 0xf0
+
+#define EDCF_AC_BE_TXOP_STA 0x0000
+#define EDCF_AC_BK_TXOP_STA 0x0000
+#define EDCF_AC_VO_ACI_STA 0x62
+#define EDCF_AC_VO_ECW_STA 0x32
+#define EDCF_AC_VI_ACI_STA 0x42
+#define EDCF_AC_VI_ECW_STA 0x43
+#define EDCF_AC_BK_ECW_STA 0xA4
+#define EDCF_AC_VI_TXOP_STA 0x005e
+#define EDCF_AC_VO_TXOP_STA 0x002f
+#define EDCF_AC_BE_ACI_STA 0x03
+#define EDCF_AC_BE_ECW_STA 0xA4
+#define EDCF_AC_BK_ACI_STA 0x27
+#define EDCF_AC_VO_TXOP_AP 0x002f
+
+#define EDCF_TXOP2USEC(txop) ((txop) << 5)
+#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
+
+#define APHY_SYMBOL_TIME 4
+#define APHY_PREAMBLE_TIME 16
+#define APHY_SIGNAL_TIME 4
+#define APHY_SIFS_TIME 16
+#define APHY_SERVICE_NBITS 16
+#define APHY_TAIL_NBITS 6
+#define BPHY_SIFS_TIME 10
+#define BPHY_PLCP_SHORT_TIME 96
+
+#define PREN_PREAMBLE 24
+#define PREN_MM_EXT 12
+#define PREN_PREAMBLE_EXT 4
+
+#define DOT11_MAC_HDR_LEN 24
+#define DOT11_ACK_LEN 10
+#define DOT11_BA_LEN 4
+#define DOT11_OFDM_SIGNAL_EXTENSION 6
+#define DOT11_MIN_FRAG_LEN 256
+#define DOT11_RTS_LEN 16
+#define DOT11_CTS_LEN 10
+#define DOT11_BA_BITMAP_LEN 128
+#define DOT11_MIN_BEACON_PERIOD 1
+#define DOT11_MAX_BEACON_PERIOD 0xFFFF
+#define DOT11_MAXNUMFRAGS 16
+#define DOT11_MAX_FRAG_LEN 2346
+
+#define BPHY_PLCP_TIME 192
+#define RIFS_11N_TIME 2
+
+#define WME_VER 1
+#define WME_SUBTYPE_PARAM_IE 1
+#define WME_TYPE 2
+#define WME_OUI "\x00\x50\xf2"
+
+#define AC_BE 0
+#define AC_BK 1
+#define AC_VI 2
+#define AC_VO 3
+
+/*
+ * driver maintains internal 'tick'(wlc->pub->now) which increments in 1s OS timer(soft
+ * watchdog) it is not a wall clock and won't increment when driver is in "down" state
+ * this low resolution driver tick can be used for maintenance tasks such as phy
+ * calibration and scb update
+ */
+
+/* To inform the ucode of the last mcast frame posted so that it can clear moredata bit */
+#define BCMCFID(wlc, fid) wlc_bmac_write_shm((wlc)->hw, M_BCMC_FID, (fid))
+
+#define WLC_WAR16165(wlc) (wlc->pub->sih->bustype == PCI_BUS && \
+ (!AP_ENAB(wlc->pub)) && (wlc->war16165))
+
+/* debug/trace */
+uint brcm_msg_level =
+#if defined(BCMDBG)
+ LOG_ERROR_VAL;
+#else
+ 0;
+#endif /* BCMDBG */
+
+/* Find basic rate for a given rate */
+#define WLC_BASIC_RATE(wlc, rspec) (IS_MCS(rspec) ? \
+ (wlc)->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK].leg_ofdm] : \
+ (wlc)->band->basic_rate[rspec & RSPEC_RATE_MASK])
+
+#define FRAMETYPE(r, mimoframe) (IS_MCS(r) ? mimoframe : (IS_CCK(r) ? FT_CCK : FT_OFDM))
+
+#define RFDISABLE_DEFAULT 10000000 /* rfdisable delay timer 500 ms, runs of ALP clock */
+
+#define WLC_TEMPSENSE_PERIOD 10 /* 10 second timeout */
+
+#define SCAN_IN_PROGRESS(x) 0
+
+#define EPI_VERSION_NUM 0x054b0b00
+
+#ifdef BCMDBG
+/* pointer to most recently allocated wl/wlc */
+static struct wlc_info *wlc_info_dbg = (struct wlc_info *) (NULL);
+#endif
+
+const u8 prio2fifo[NUMPRIO] = {
+ TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */
+ TX_AC_BK_FIFO, /* 1 BK AC_BK Background */
+ TX_AC_BK_FIFO, /* 2 -- AC_BK Background */
+ TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */
+ TX_AC_VI_FIFO, /* 4 CL AC_VI Video */
+ TX_AC_VI_FIFO, /* 5 VI AC_VI Video */
+ TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */
+ TX_AC_VO_FIFO /* 7 NC AC_VO Voice */
+};
+
+/* precedences numbers for wlc queues. These are twice as may levels as
+ * 802.1D priorities.
+ * Odd numbers are used for HI priority traffic at same precedence levels
+ * These constants are used ONLY by wlc_prio2prec_map. Do not use them elsewhere.
+ */
+#define _WLC_PREC_NONE 0 /* None = - */
+#define _WLC_PREC_BK 2 /* BK - Background */
+#define _WLC_PREC_BE 4 /* BE - Best-effort */
+#define _WLC_PREC_EE 6 /* EE - Excellent-effort */
+#define _WLC_PREC_CL 8 /* CL - Controlled Load */
+#define _WLC_PREC_VI 10 /* Vi - Video */
+#define _WLC_PREC_VO 12 /* Vo - Voice */
+#define _WLC_PREC_NC 14 /* NC - Network Control */
+
+/* 802.1D Priority to precedence queue mapping */
+const u8 wlc_prio2prec_map[] = {
+ _WLC_PREC_BE, /* 0 BE - Best-effort */
+ _WLC_PREC_BK, /* 1 BK - Background */
+ _WLC_PREC_NONE, /* 2 None = - */
+ _WLC_PREC_EE, /* 3 EE - Excellent-effort */
+ _WLC_PREC_CL, /* 4 CL - Controlled Load */
+ _WLC_PREC_VI, /* 5 Vi - Video */
+ _WLC_PREC_VO, /* 6 Vo - Voice */
+ _WLC_PREC_NC, /* 7 NC - Network Control */
+};
+
+/* Sanity check for tx_prec_map and fifo synchup
+ * Either there are some packets pending for the fifo, else if fifo is empty then
+ * all the corresponding precmap bits should be set
+ */
+#define WLC_TX_FIFO_CHECK(wlc, fifo) (TXPKTPENDGET((wlc), (fifo)) || \
+ (TXPKTPENDGET((wlc), (fifo)) == 0 && \
+ ((wlc)->tx_prec_map & (wlc)->fifo2prec_map[(fifo)]) == \
+ (wlc)->fifo2prec_map[(fifo)]))
+
+/* TX FIFO number to WME/802.1E Access Category */
+const u8 wme_fifo2ac[] = { AC_BK, AC_BE, AC_VI, AC_VO, AC_BE, AC_BE };
+
+/* WME/802.1E Access Category to TX FIFO number */
+static const u8 wme_ac2fifo[] = { 1, 0, 2, 3 };
+
+static bool in_send_q = false;
+
+/* Shared memory location index for various AC params */
+#define wme_shmemacindex(ac) wme_ac2fifo[ac]
+
+#ifdef BCMDBG
+static const char *fifo_names[] = {
+ "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
+#else
+static const char fifo_names[6][0];
+#endif
+
+static const u8 acbitmap2maxprio[] = {
+ PRIO_8021D_BE, PRIO_8021D_BE, PRIO_8021D_BK, PRIO_8021D_BK,
+ PRIO_8021D_VI, PRIO_8021D_VI, PRIO_8021D_VI, PRIO_8021D_VI,
+ PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO,
+ PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO
+};
+
+/* currently the best mechanism for determining SIFS is the band in use */
+#define SIFS(band) ((band)->bandtype == WLC_BAND_5G ? APHY_SIFS_TIME : BPHY_SIFS_TIME);
+
+/* value for # replay counters currently supported */
+#define WLC_REPLAY_CNTRS_VALUE WPA_CAP_16_REPLAY_CNTRS
+
+/* local prototypes */
+static u16 wlc_d11hdrs_mac80211(struct wlc_info *wlc,
+ struct ieee80211_hw *hw,
+ struct sk_buff *p,
+ struct scb *scb, uint frag,
+ uint nfrags, uint queue,
+ uint next_frag_len,
+ wsec_key_t *key,
+ ratespec_t rspec_override);
+static void wlc_bss_default_init(struct wlc_info *wlc);
+static void wlc_ucode_mac_upd(struct wlc_info *wlc);
+static ratespec_t mac80211_wlc_set_nrate(struct wlc_info *wlc,
+ struct wlcband *cur_band, u32 int_val);
+static void wlc_tx_prec_map_init(struct wlc_info *wlc);
+static void wlc_watchdog(void *arg);
+static void wlc_watchdog_by_timer(void *arg);
+static u16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate);
+static int wlc_set_rateset(struct wlc_info *wlc, wlc_rateset_t *rs_arg);
+static u8 wlc_local_constraint_qdbm(struct wlc_info *wlc);
+
+/* send and receive */
+static struct wlc_txq_info *wlc_txq_alloc(struct wlc_info *wlc);
+static void wlc_txq_free(struct wlc_info *wlc,
+ struct wlc_txq_info *qi);
+static void wlc_txflowcontrol_signal(struct wlc_info *wlc,
+ struct wlc_txq_info *qi,
+ bool on, int prio);
+static void wlc_txflowcontrol_reset(struct wlc_info *wlc);
+static void wlc_compute_cck_plcp(struct wlc_info *wlc, ratespec_t rate,
+ uint length, u8 *plcp);
+static void wlc_compute_ofdm_plcp(ratespec_t rate, uint length, u8 *plcp);
+static void wlc_compute_mimo_plcp(ratespec_t rate, uint length, u8 *plcp);
+static u16 wlc_compute_frame_dur(struct wlc_info *wlc, ratespec_t rate,
+ u8 preamble_type, uint next_frag_len);
+static u64 wlc_recover_tsf64(struct wlc_info *wlc, struct wlc_d11rxhdr *rxh);
+static void wlc_recvctl(struct wlc_info *wlc,
+ d11rxhdr_t *rxh, struct sk_buff *p);
+static uint wlc_calc_frame_len(struct wlc_info *wlc, ratespec_t rate,
+ u8 preamble_type, uint dur);
+static uint wlc_calc_ack_time(struct wlc_info *wlc, ratespec_t rate,
+ u8 preamble_type);
+static uint wlc_calc_cts_time(struct wlc_info *wlc, ratespec_t rate,
+ u8 preamble_type);
+/* interrupt, up/down, band */
+static void wlc_setband(struct wlc_info *wlc, uint bandunit);
+static chanspec_t wlc_init_chanspec(struct wlc_info *wlc);
+static void wlc_bandinit_ordered(struct wlc_info *wlc, chanspec_t chanspec);
+static void wlc_bsinit(struct wlc_info *wlc);
+static int wlc_duty_cycle_set(struct wlc_info *wlc, int duty_cycle, bool isOFDM,
+ bool writeToShm);
+static void wlc_radio_hwdisable_upd(struct wlc_info *wlc);
+static bool wlc_radio_monitor_start(struct wlc_info *wlc);
+static void wlc_radio_timer(void *arg);
+static void wlc_radio_enable(struct wlc_info *wlc);
+static void wlc_radio_upd(struct wlc_info *wlc);
+
+/* scan, association, BSS */
+static uint wlc_calc_ba_time(struct wlc_info *wlc, ratespec_t rate,
+ u8 preamble_type);
+static void wlc_update_mimo_band_bwcap(struct wlc_info *wlc, u8 bwcap);
+static void wlc_ht_update_sgi_rx(struct wlc_info *wlc, int val);
+static void wlc_ht_update_ldpc(struct wlc_info *wlc, s8 val);
+static void wlc_war16165(struct wlc_info *wlc, bool tx);
+
+static void wlc_wme_retries_write(struct wlc_info *wlc);
+static bool wlc_attach_stf_ant_init(struct wlc_info *wlc);
+static uint wlc_attach_module(struct wlc_info *wlc);
+static void wlc_detach_module(struct wlc_info *wlc);
+static void wlc_timers_deinit(struct wlc_info *wlc);
+static void wlc_down_led_upd(struct wlc_info *wlc);
+static uint wlc_down_del_timer(struct wlc_info *wlc);
+static void wlc_ofdm_rateset_war(struct wlc_info *wlc);
+static int _wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
+ struct wlc_if *wlcif);
+
+/* conditions under which the PM bit should be set in outgoing frames and STAY_AWAKE is meaningful
+ */
+bool wlc_ps_allowed(struct wlc_info *wlc)
+{
+ int idx;
+ struct wlc_bsscfg *cfg;
+
+ /* disallow PS when one of the following global conditions meets */
+ if (!wlc->pub->associated)
+ return false;
+
+ /* disallow PS when one of these meets when not scanning */
+ if (AP_ACTIVE(wlc) || wlc->monitor)
+ return false;
+
+ FOREACH_AS_STA(wlc, idx, cfg) {
+ /* disallow PS when one of the following bsscfg specific conditions meets */
+ if (!cfg->BSS || !WLC_PORTOPEN(cfg))
+ return false;
+
+ if (!cfg->dtim_programmed)
+ return false;
+ }
+
+ return true;
+}
+
+void wlc_reset(struct wlc_info *wlc)
+{
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ /* slurp up hw mac counters before core reset */
+ wlc_statsupd(wlc);
+
+ /* reset our snapshot of macstat counters */
+ memset((char *)wlc->core->macstat_snapshot, 0,
+ sizeof(macstat_t));
+
+ wlc_bmac_reset(wlc->hw);
+}
+
+void wlc_fatal_error(struct wlc_info *wlc)
+{
+ wiphy_err(wlc->wiphy, "wl%d: fatal error, reinitializing\n",
+ wlc->pub->unit);
+ brcms_init(wlc->wl);
+}
+
+/* Return the channel the driver should initialize during wlc_init.
+ * the channel may have to be changed from the currently configured channel
+ * if other configurations are in conflict (bandlocked, 11n mode disabled,
+ * invalid channel for current country, etc.)
+ */
+static chanspec_t wlc_init_chanspec(struct wlc_info *wlc)
+{
+ chanspec_t chanspec =
+ 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
+ WL_CHANSPEC_BAND_2G;
+
+ return chanspec;
+}
+
+struct scb global_scb;
+
+static void wlc_init_scb(struct wlc_info *wlc, struct scb *scb)
+{
+ int i;
+ scb->flags = SCB_WMECAP | SCB_HTCAP;
+ for (i = 0; i < NUMPRIO; i++)
+ scb->seqnum[i] = 0;
+}
+
+void wlc_init(struct wlc_info *wlc)
+{
+ d11regs_t *regs;
+ chanspec_t chanspec;
+ int i;
+ struct wlc_bsscfg *bsscfg;
+ bool mute = false;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ regs = wlc->regs;
+
+ /* This will happen if a big-hammer was executed. In that case, we want to go back
+ * to the channel that we were on and not new channel
+ */
+ if (wlc->pub->associated)
+ chanspec = wlc->home_chanspec;
+ else
+ chanspec = wlc_init_chanspec(wlc);
+
+ wlc_bmac_init(wlc->hw, chanspec, mute);
+
+ /* update beacon listen interval */
+ wlc_bcn_li_upd(wlc);
+
+ /* the world is new again, so is our reported rate */
+ wlc_reprate_init(wlc);
+
+ /* write ethernet address to core */
+ FOREACH_BSS(wlc, i, bsscfg) {
+ wlc_set_mac(bsscfg);
+ wlc_set_bssid(bsscfg);
+ }
+
+ /* Update tsf_cfprep if associated and up */
+ if (wlc->pub->associated) {
+ FOREACH_BSS(wlc, i, bsscfg) {
+ if (bsscfg->up) {
+ u32 bi;
+
+ /* get beacon period and convert to uS */
+ bi = bsscfg->current_bss->beacon_period << 10;
+ /*
+ * update since init path would reset
+ * to default value
+ */
+ W_REG(®s->tsf_cfprep,
+ (bi << CFPREP_CBI_SHIFT));
+
+ /* Update maccontrol PM related bits */
+ wlc_set_ps_ctrl(wlc);
+
+ break;
+ }
+ }
+ }
+
+ wlc_key_hw_init_all(wlc);
+
+ wlc_bandinit_ordered(wlc, chanspec);
+
+ wlc_init_scb(wlc, &global_scb);
+
+ /* init probe response timeout */
+ wlc_write_shm(wlc, M_PRS_MAXTIME, wlc->prb_resp_timeout);
+
+ /* init max burst txop (framebursting) */
+ wlc_write_shm(wlc, M_MBURST_TXOP,
+ (wlc->
+ _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
+
+ /* initialize maximum allowed duty cycle */
+ wlc_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
+ wlc_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
+
+ /* Update some shared memory locations related to max AMPDU size allowed to received */
+ wlc_ampdu_shm_upd(wlc->ampdu);
+
+ /* band-specific inits */
+ wlc_bsinit(wlc);
+
+ /* Enable EDCF mode (while the MAC is suspended) */
+ if (EDCF_ENAB(wlc->pub)) {
+ OR_REG(®s->ifs_ctl, IFS_USEEDCF);
+ wlc_edcf_setparams(wlc, false);
+ }
+
+ /* Init precedence maps for empty FIFOs */
+ wlc_tx_prec_map_init(wlc);
+
+ /* read the ucode version if we have not yet done so */
+ if (wlc->ucode_rev == 0) {
+ wlc->ucode_rev =
+ wlc_read_shm(wlc, M_BOM_REV_MAJOR) << NBITS(u16);
+ wlc->ucode_rev |= wlc_read_shm(wlc, M_BOM_REV_MINOR);
+ }
+
+ /* ..now really unleash hell (allow the MAC out of suspend) */
+ wlc_enable_mac(wlc);
+
+ /* clear tx flow control */
+ wlc_txflowcontrol_reset(wlc);
+
+ /* clear tx data fifo suspends */
+ wlc->tx_suspended = false;
+
+ /* enable the RF Disable Delay timer */
+ W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
+
+ /* initialize mpc delay */
+ wlc->mpc_delay_off = wlc->mpc_dlycnt = WLC_MPC_MIN_DELAYCNT;
+
+ /*
+ * Initialize WME parameters; if they haven't been set by some other
+ * mechanism (IOVar, etc) then read them from the hardware.
+ */
+ if (WLC_WME_RETRY_SHORT_GET(wlc, 0) == 0) { /* Uninitialized; read from HW */
+ int ac;
+
+ for (ac = 0; ac < AC_COUNT; ac++) {
+ wlc->wme_retries[ac] =
+ wlc_read_shm(wlc, M_AC_TXLMT_ADDR(ac));
+ }
+ }
+}
+
+void wlc_mac_bcn_promisc_change(struct wlc_info *wlc, bool promisc)
+{
+ wlc->bcnmisc_monitor = promisc;
+ wlc_mac_bcn_promisc(wlc);
+}
+
+void wlc_mac_bcn_promisc(struct wlc_info *wlc)
+{
+ if ((AP_ENAB(wlc->pub) && (N_ENAB(wlc->pub) || wlc->band->gmode)) ||
+ wlc->bcnmisc_ibss || wlc->bcnmisc_scan || wlc->bcnmisc_monitor)
+ wlc_mctrl(wlc, MCTL_BCNS_PROMISC, MCTL_BCNS_PROMISC);
+ else
+ wlc_mctrl(wlc, MCTL_BCNS_PROMISC, 0);
+}
+
+/* set or clear maccontrol bits MCTL_PROMISC and MCTL_KEEPCONTROL */
+void wlc_mac_promisc(struct wlc_info *wlc)
+{
+ u32 promisc_bits = 0;
+
+ /* promiscuous mode just sets MCTL_PROMISC
+ * Note: APs get all BSS traffic without the need to set the MCTL_PROMISC bit
+ * since all BSS data traffic is directed at the AP
+ */
+ if (PROMISC_ENAB(wlc->pub) && !AP_ENAB(wlc->pub))
+ promisc_bits |= MCTL_PROMISC;
+
+ /* monitor mode needs both MCTL_PROMISC and MCTL_KEEPCONTROL
+ * Note: monitor mode also needs MCTL_BCNS_PROMISC, but that is
+ * handled in wlc_mac_bcn_promisc()
+ */
+ if (MONITOR_ENAB(wlc))
+ promisc_bits |= MCTL_PROMISC | MCTL_KEEPCONTROL;
+
+ wlc_mctrl(wlc, MCTL_PROMISC | MCTL_KEEPCONTROL, promisc_bits);
+}
+
+/* push sw hps and wake state through hardware */
+void wlc_set_ps_ctrl(struct wlc_info *wlc)
+{
+ u32 v1, v2;
+ bool hps;
+ bool awake_before;
+
+ hps = PS_ALLOWED(wlc);
+
+ BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
+
+ v1 = R_REG(&wlc->regs->maccontrol);
+ v2 = MCTL_WAKE;
+ if (hps)
+ v2 |= MCTL_HPS;
+
+ wlc_mctrl(wlc, MCTL_WAKE | MCTL_HPS, v2);
+
+ awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
+
+ if (!awake_before)
+ wlc_bmac_wait_for_wake(wlc->hw);
+
+}
+
+/*
+ * Write this BSS config's MAC address to core.
+ * Updates RXE match engine.
+ */
+int wlc_set_mac(struct wlc_bsscfg *cfg)
+{
+ int err = 0;
+ struct wlc_info *wlc = cfg->wlc;
+
+ if (cfg == wlc->cfg) {
+ /* enter the MAC addr into the RXE match registers */
+ wlc_set_addrmatch(wlc, RCM_MAC_OFFSET, cfg->cur_etheraddr);
+ }
+
+ wlc_ampdu_macaddr_upd(wlc);
+
+ return err;
+}
+
+/* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
+ * Updates RXE match engine.
+ */
+void wlc_set_bssid(struct wlc_bsscfg *cfg)
+{
+ struct wlc_info *wlc = cfg->wlc;
+
+ /* if primary config, we need to update BSSID in RXE match registers */
+ if (cfg == wlc->cfg) {
+ wlc_set_addrmatch(wlc, RCM_BSSID_OFFSET, cfg->BSSID);
+ }
+#ifdef SUPPORT_HWKEYS
+ else if (BSSCFG_STA(cfg) && cfg->BSS) {
+ wlc_rcmta_add_bssid(wlc, cfg);
+ }
+#endif
+}
+
+/*
+ * Suspend the the MAC and update the slot timing
+ * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
+ */
+void wlc_switch_shortslot(struct wlc_info *wlc, bool shortslot)
+{
+ int idx;
+ struct wlc_bsscfg *cfg;
+
+ /* use the override if it is set */
+ if (wlc->shortslot_override != WLC_SHORTSLOT_AUTO)
+ shortslot = (wlc->shortslot_override == WLC_SHORTSLOT_ON);
+
+ if (wlc->shortslot == shortslot)
+ return;
+
+ wlc->shortslot = shortslot;
+
+ /* update the capability based on current shortslot mode */
+ FOREACH_BSS(wlc, idx, cfg) {
+ if (!cfg->associated)
+ continue;
+ cfg->current_bss->capability &=
+ ~WLAN_CAPABILITY_SHORT_SLOT_TIME;
+ if (wlc->shortslot)
+ cfg->current_bss->capability |=
+ WLAN_CAPABILITY_SHORT_SLOT_TIME;
+ }
+
+ wlc_bmac_set_shortslot(wlc->hw, shortslot);
+}
+
+static u8 wlc_local_constraint_qdbm(struct wlc_info *wlc)
+{
+ u8 local;
+ s16 local_max;
+
+ local = WLC_TXPWR_MAX;
+ if (wlc->pub->associated &&
+ (brcmu_chspec_ctlchan(wlc->chanspec) ==
+ brcmu_chspec_ctlchan(wlc->home_chanspec))) {
+
+ /* get the local power constraint if we are on the AP's
+ * channel [802.11h, 7.3.2.13]
+ */
+ /* Clamp the value between 0 and WLC_TXPWR_MAX w/o overflowing the target */
+ local_max =
+ (wlc->txpwr_local_max -
+ wlc->txpwr_local_constraint) * WLC_TXPWR_DB_FACTOR;
+ if (local_max > 0 && local_max < WLC_TXPWR_MAX)
+ return (u8) local_max;
+ if (local_max < 0)
+ return 0;
+ }
+
+ return local;
+}
+
+/* propagate home chanspec to all bsscfgs in case bsscfg->current_bss->chanspec is referenced */
+void wlc_set_home_chanspec(struct wlc_info *wlc, chanspec_t chanspec)
+{
+ if (wlc->home_chanspec != chanspec) {
+ int idx;
+ struct wlc_bsscfg *cfg;
+
+ wlc->home_chanspec = chanspec;
+
+ FOREACH_BSS(wlc, idx, cfg) {
+ if (!cfg->associated)
+ continue;
+
+ cfg->current_bss->chanspec = chanspec;
+ }
+
+ }
+}
+
+static void wlc_set_phy_chanspec(struct wlc_info *wlc, chanspec_t chanspec)
+{
+ /* Save our copy of the chanspec */
+ wlc->chanspec = chanspec;
+
+ /* Set the chanspec and power limits for this locale after computing
+ * any 11h local tx power constraints.
+ */
+ wlc_channel_set_chanspec(wlc->cmi, chanspec,
+ wlc_local_constraint_qdbm(wlc));
+
+ if (wlc->stf->ss_algosel_auto)
+ wlc_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
+ chanspec);
+
+ wlc_stf_ss_update(wlc, wlc->band);
+
+}
+
+void wlc_set_chanspec(struct wlc_info *wlc, chanspec_t chanspec)
+{
+ uint bandunit;
+ bool switchband = false;
+ chanspec_t old_chanspec = wlc->chanspec;
+
+ if (!wlc_valid_chanspec_db(wlc->cmi, chanspec)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
+ wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
+ return;
+ }
+
+ /* Switch bands if necessary */
+ if (NBANDS(wlc) > 1) {
+ bandunit = CHSPEC_WLCBANDUNIT(chanspec);
+ if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
+ switchband = true;
+ if (wlc->bandlocked) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
+ "band is locked!\n",
+ wlc->pub->unit, __func__,
+ CHSPEC_CHANNEL(chanspec));
+ return;
+ }
+ /* BMAC_NOTE: should the setband call come after the wlc_bmac_chanspec() ?
+ * if the setband updates (wlc_bsinit) use low level calls to inspect and
+ * set state, the state inspected may be from the wrong band, or the
+ * following wlc_bmac_set_chanspec() may undo the work.
+ */
+ wlc_setband(wlc, bandunit);
+ }
+ }
+
+ /* sync up phy/radio chanspec */
+ wlc_set_phy_chanspec(wlc, chanspec);
+
+ /* init antenna selection */
+ if (CHSPEC_WLC_BW(old_chanspec) != CHSPEC_WLC_BW(chanspec)) {
+ wlc_antsel_init(wlc->asi);
+
+ /* Fix the hardware rateset based on bw.
+ * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
+ */
+ wlc_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
+ wlc->band->
+ mimo_cap_40 ? CHSPEC_WLC_BW(chanspec)
+ : 0);
+ }
+
+ /* update some mac configuration since chanspec changed */
+ wlc_ucode_mac_upd(wlc);
+}
+
+ratespec_t wlc_lowest_basic_rspec(struct wlc_info *wlc, wlc_rateset_t *rs)
+{
+ ratespec_t lowest_basic_rspec;
+ uint i;
+
+ /* Use the lowest basic rate */
+ lowest_basic_rspec = rs->rates[0] & WLC_RATE_MASK;
+ for (i = 0; i < rs->count; i++) {
+ if (rs->rates[i] & WLC_RATE_FLAG) {
+ lowest_basic_rspec = rs->rates[i] & WLC_RATE_MASK;
+ break;
+ }
+ }
+#if NCONF
+ /* pick siso/cdd as default for OFDM (note no basic rate MCSs are supported yet) */
+ if (IS_OFDM(lowest_basic_rspec)) {
+ lowest_basic_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
+ }
+#endif
+
+ return lowest_basic_rspec;
+}
+
+/* This function changes the phytxctl for beacon based on current beacon ratespec AND txant
+ * setting as per this table:
+ * ratespec CCK ant = wlc->stf->txant
+ * OFDM ant = 3
+ */
+void wlc_beacon_phytxctl_txant_upd(struct wlc_info *wlc, ratespec_t bcn_rspec)
+{
+ u16 phyctl;
+ u16 phytxant = wlc->stf->phytxant;
+ u16 mask = PHY_TXC_ANT_MASK;
+
+ /* for non-siso rates or default setting, use the available chains */
+ if (WLC_PHY_11N_CAP(wlc->band)) {
+ phytxant = wlc_stf_phytxchain_sel(wlc, bcn_rspec);
+ }
+
+ phyctl = wlc_read_shm(wlc, M_BCN_PCTLWD);
+ phyctl = (phyctl & ~mask) | phytxant;
+ wlc_write_shm(wlc, M_BCN_PCTLWD, phyctl);
+}
+
+/* centralized protection config change function to simplify debugging, no consistency checking
+ * this should be called only on changes to avoid overhead in periodic function
+*/
+void wlc_protection_upd(struct wlc_info *wlc, uint idx, int val)
+{
+ BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
+
+ switch (idx) {
+ case WLC_PROT_G_SPEC:
+ wlc->protection->_g = (bool) val;
+ break;
+ case WLC_PROT_G_OVR:
+ wlc->protection->g_override = (s8) val;
+ break;
+ case WLC_PROT_G_USER:
+ wlc->protection->gmode_user = (u8) val;
+ break;
+ case WLC_PROT_OVERLAP:
+ wlc->protection->overlap = (s8) val;
+ break;
+ case WLC_PROT_N_USER:
+ wlc->protection->nmode_user = (s8) val;
+ break;
+ case WLC_PROT_N_CFG:
+ wlc->protection->n_cfg = (s8) val;
+ break;
+ case WLC_PROT_N_CFG_OVR:
+ wlc->protection->n_cfg_override = (s8) val;
+ break;
+ case WLC_PROT_N_NONGF:
+ wlc->protection->nongf = (bool) val;
+ break;
+ case WLC_PROT_N_NONGF_OVR:
+ wlc->protection->nongf_override = (s8) val;
+ break;
+ case WLC_PROT_N_PAM_OVR:
+ wlc->protection->n_pam_override = (s8) val;
+ break;
+ case WLC_PROT_N_OBSS:
+ wlc->protection->n_obss = (bool) val;
+ break;
+
+ default:
+ break;
+ }
+
+}
+
+static void wlc_ht_update_sgi_rx(struct wlc_info *wlc, int val)
+{
+ wlc->ht_cap.cap_info &= ~(IEEE80211_HT_CAP_SGI_20 |
+ IEEE80211_HT_CAP_SGI_40);
+ wlc->ht_cap.cap_info |= (val & WLC_N_SGI_20) ?
+ IEEE80211_HT_CAP_SGI_20 : 0;
+ wlc->ht_cap.cap_info |= (val & WLC_N_SGI_40) ?
+ IEEE80211_HT_CAP_SGI_40 : 0;
+
+ if (wlc->pub->up) {
+ wlc_update_beacon(wlc);
+ wlc_update_probe_resp(wlc, true);
+ }
+}
+
+static void wlc_ht_update_ldpc(struct wlc_info *wlc, s8 val)
+{
+ wlc->stf->ldpc = val;
+
+ wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_LDPC_CODING;
+ if (wlc->stf->ldpc != OFF)
+ wlc->ht_cap.cap_info |= IEEE80211_HT_CAP_LDPC_CODING;
+
+ if (wlc->pub->up) {
+ wlc_update_beacon(wlc);
+ wlc_update_probe_resp(wlc, true);
+ wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
+ }
+}
+
+/*
+ * ucode, hwmac update
+ * Channel dependent updates for ucode and hw
+ */
+static void wlc_ucode_mac_upd(struct wlc_info *wlc)
+{
+ /* enable or disable any active IBSSs depending on whether or not
+ * we are on the home channel
+ */
+ if (wlc->home_chanspec == WLC_BAND_PI_RADIO_CHANSPEC) {
+ if (wlc->pub->associated) {
+ /* BMAC_NOTE: This is something that should be fixed in ucode inits.
+ * I think that the ucode inits set up the bcn templates and shm values
+ * with a bogus beacon. This should not be done in the inits. If ucode needs
+ * to set up a beacon for testing, the test routines should write it down,
+ * not expect the inits to populate a bogus beacon.
+ */
+ if (WLC_PHY_11N_CAP(wlc->band)) {
+ wlc_write_shm(wlc, M_BCN_TXTSF_OFFSET,
+ wlc->band->bcntsfoff);
+ }
+ }
+ } else {
+ /* disable an active IBSS if we are not on the home channel */
+ }
+
+ /* update the various promisc bits */
+ wlc_mac_bcn_promisc(wlc);
+ wlc_mac_promisc(wlc);
+}
+
+static void wlc_bandinit_ordered(struct wlc_info *wlc, chanspec_t chanspec)
+{
+ wlc_rateset_t default_rateset;
+ uint parkband;
+ uint i, band_order[2];
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+ /*
+ * We might have been bandlocked during down and the chip power-cycled (hibernate).
+ * figure out the right band to park on
+ */
+ if (wlc->bandlocked || NBANDS(wlc) == 1) {
+ parkband = wlc->band->bandunit; /* updated in wlc_bandlock() */
+ band_order[0] = band_order[1] = parkband;
+ } else {
+ /* park on the band of the specified chanspec */
+ parkband = CHSPEC_WLCBANDUNIT(chanspec);
+
+ /* order so that parkband initialize last */
+ band_order[0] = parkband ^ 1;
+ band_order[1] = parkband;
+ }
+
+ /* make each band operational, software state init */
+ for (i = 0; i < NBANDS(wlc); i++) {
+ uint j = band_order[i];
+
+ wlc->band = wlc->bandstate[j];
+
+ wlc_default_rateset(wlc, &default_rateset);
+
+ /* fill in hw_rate */
+ wlc_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
+ false, WLC_RATES_CCK_OFDM, WLC_RATE_MASK,
+ (bool) N_ENAB(wlc->pub));
+
+ /* init basic rate lookup */
+ wlc_rate_lookup_init(wlc, &default_rateset);
+ }
+
+ /* sync up phy/radio chanspec */
+ wlc_set_phy_chanspec(wlc, chanspec);
+}
+
+/* band-specific init */
+static void WLBANDINITFN(wlc_bsinit) (struct wlc_info *wlc)
+{
+ BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
+ wlc->pub->unit, wlc->band->bandunit);
+
+ /* write ucode ACK/CTS rate table */
+ wlc_set_ratetable(wlc);
+
+ /* update some band specific mac configuration */
+ wlc_ucode_mac_upd(wlc);
+
+ /* init antenna selection */
+ wlc_antsel_init(wlc->asi);
+
+}
+
+/* switch to and initialize new band */
+static void WLBANDINITFN(wlc_setband) (struct wlc_info *wlc, uint bandunit)
+{
+ int idx;
+ struct wlc_bsscfg *cfg;
+
+ wlc->band = wlc->bandstate[bandunit];
+
+ if (!wlc->pub->up)
+ return;
+
+ /* wait for at least one beacon before entering sleeping state */
+ FOREACH_AS_STA(wlc, idx, cfg)
+ cfg->PMawakebcn = true;
+ wlc_set_ps_ctrl(wlc);
+
+ /* band-specific initializations */
+ wlc_bsinit(wlc);
+}
+
+/* Initialize a WME Parameter Info Element with default STA parameters from WMM Spec, Table 12 */
+void wlc_wme_initparams_sta(struct wlc_info *wlc, wme_param_ie_t *pe)
+{
+ static const wme_param_ie_t stadef = {
+ WME_OUI,
+ WME_TYPE,
+ WME_SUBTYPE_PARAM_IE,
+ WME_VER,
+ 0,
+ 0,
+ {
+ {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA,
+ cpu_to_le16(EDCF_AC_BE_TXOP_STA)},
+ {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA,
+ cpu_to_le16(EDCF_AC_BK_TXOP_STA)},
+ {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA,
+ cpu_to_le16(EDCF_AC_VI_TXOP_STA)},
+ {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA,
+ cpu_to_le16(EDCF_AC_VO_TXOP_STA)}
+ }
+ };
+ memcpy(pe, &stadef, sizeof(*pe));
+}
+
+void wlc_wme_setparams(struct wlc_info *wlc, u16 aci,
+ const struct ieee80211_tx_queue_params *params,
+ bool suspend)
+{
+ int i;
+ shm_acparams_t acp_shm;
+ u16 *shm_entry;
+
+ /* Only apply params if the core is out of reset and has clocks */
+ if (!wlc->clk) {
+ wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
+ __func__);
+ return;
+ }
+
+ do {
+ memset((char *)&acp_shm, 0, sizeof(shm_acparams_t));
+ /* fill in shm ac params struct */
+ acp_shm.txop = le16_to_cpu(params->txop);
+ /* convert from units of 32us to us for ucode */
+ wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
+ EDCF_TXOP2USEC(acp_shm.txop);
+ acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
+
+ if (aci == AC_VI && acp_shm.txop == 0
+ && acp_shm.aifs < EDCF_AIFSN_MAX)
+ acp_shm.aifs++;
+
+ if (acp_shm.aifs < EDCF_AIFSN_MIN
+ || acp_shm.aifs > EDCF_AIFSN_MAX) {
+ wiphy_err(wlc->wiphy, "wl%d: wlc_edcf_setparams: bad "
+ "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
+ continue;
+ }
+
+ acp_shm.cwmin = params->cw_min;
+ acp_shm.cwmax = params->cw_max;
+ acp_shm.cwcur = acp_shm.cwmin;
+ acp_shm.bslots =
+ R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur;
+ acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
+ /* Indicate the new params to the ucode */
+ acp_shm.status = wlc_read_shm(wlc, (M_EDCF_QINFO +
+ wme_shmemacindex(aci) *
+ M_EDCF_QLEN +
+ M_EDCF_STATUS_OFF));
+ acp_shm.status |= WME_STATUS_NEWAC;
+
+ /* Fill in shm acparam table */
+ shm_entry = (u16 *) &acp_shm;
+ for (i = 0; i < (int)sizeof(shm_acparams_t); i += 2)
+ wlc_write_shm(wlc,
+ M_EDCF_QINFO +
+ wme_shmemacindex(aci) * M_EDCF_QLEN + i,
+ *shm_entry++);
+
+ } while (0);
+
+ if (suspend)
+ wlc_suspend_mac_and_wait(wlc);
+
+ if (suspend)
+ wlc_enable_mac(wlc);
+
+}
+
+void wlc_edcf_setparams(struct wlc_info *wlc, bool suspend)
+{
+ u16 aci;
+ int i_ac;
+ edcf_acparam_t *edcf_acp;
+
+ struct ieee80211_tx_queue_params txq_pars;
+ struct ieee80211_tx_queue_params *params = &txq_pars;
+
+ /*
+ * AP uses AC params from wme_param_ie_ap.
+ * AP advertises AC params from wme_param_ie.
+ * STA uses AC params from wme_param_ie.
+ */
+
+ edcf_acp = (edcf_acparam_t *) &wlc->wme_param_ie.acparam[0];
+
+ for (i_ac = 0; i_ac < AC_COUNT; i_ac++, edcf_acp++) {
+ /* find out which ac this set of params applies to */
+ aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
+
+ /* fill in shm ac params struct */
+ params->txop = edcf_acp->TXOP;
+ params->aifs = edcf_acp->ACI;
+
+ /* CWmin = 2^(ECWmin) - 1 */
+ params->cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
+ /* CWmax = 2^(ECWmax) - 1 */
+ params->cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
+ >> EDCF_ECWMAX_SHIFT);
+ wlc_wme_setparams(wlc, aci, params, suspend);
+ }
+
+ if (suspend)
+ wlc_suspend_mac_and_wait(wlc);
+
+ if (AP_ENAB(wlc->pub) && WME_ENAB(wlc->pub)) {
+ wlc_update_beacon(wlc);
+ wlc_update_probe_resp(wlc, false);
+ }
+
+ if (suspend)
+ wlc_enable_mac(wlc);
+
+}
+
+bool wlc_timers_init(struct wlc_info *wlc, int unit)
+{
+ wlc->wdtimer = brcms_init_timer(wlc->wl, wlc_watchdog_by_timer,
+ wlc, "watchdog");
+ if (!wlc->wdtimer) {
+ wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
+ "failed\n", unit);
+ goto fail;
+ }
+
+ wlc->radio_timer = brcms_init_timer(wlc->wl, wlc_radio_timer,
+ wlc, "radio");
+ if (!wlc->radio_timer) {
+ wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
+ "failed\n", unit);
+ goto fail;
+ }
+
+ return true;
+
+ fail:
+ return false;
+}
+
+/*
+ * Initialize wlc_info default values ...
+ * may get overrides later in this function
+ */
+void wlc_info_init(struct wlc_info *wlc, int unit)
+{
+ int i;
+ /* Assume the device is there until proven otherwise */
+ wlc->device_present = true;
+
+ /* Save our copy of the chanspec */
+ wlc->chanspec = CH20MHZ_CHSPEC(1);
+
+ /* various 802.11g modes */
+ wlc->shortslot = false;
+ wlc->shortslot_override = WLC_SHORTSLOT_AUTO;
+
+ wlc_protection_upd(wlc, WLC_PROT_G_OVR, WLC_PROTECTION_AUTO);
+ wlc_protection_upd(wlc, WLC_PROT_G_SPEC, false);
+
+ wlc_protection_upd(wlc, WLC_PROT_N_CFG_OVR, WLC_PROTECTION_AUTO);
+ wlc_protection_upd(wlc, WLC_PROT_N_CFG, WLC_N_PROTECTION_OFF);
+ wlc_protection_upd(wlc, WLC_PROT_N_NONGF_OVR, WLC_PROTECTION_AUTO);
+ wlc_protection_upd(wlc, WLC_PROT_N_NONGF, false);
+ wlc_protection_upd(wlc, WLC_PROT_N_PAM_OVR, AUTO);
+
+ wlc_protection_upd(wlc, WLC_PROT_OVERLAP, WLC_PROTECTION_CTL_OVERLAP);
+
+ /* 802.11g draft 4.0 NonERP elt advertisement */
+ wlc->include_legacy_erp = true;
+
+ wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
+ wlc->stf->txant = ANT_TX_DEF;
+
+ wlc->prb_resp_timeout = WLC_PRB_RESP_TIMEOUT;
+
+ wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
+ for (i = 0; i < NFIFO; i++)
+ wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
+ wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
+
+ /* default rate fallback retry limits */
+ wlc->SFBL = RETRY_SHORT_FB;
+ wlc->LFBL = RETRY_LONG_FB;
+
+ /* default mac retry limits */
+ wlc->SRL = RETRY_SHORT_DEF;
+ wlc->LRL = RETRY_LONG_DEF;
+
+ /* Set flag to indicate that hw keys should be used when available. */
+ wlc->wsec_swkeys = false;
+
+ /* init the 4 static WEP default keys */
+ for (i = 0; i < WSEC_MAX_DEFAULT_KEYS; i++) {
+ wlc->wsec_keys[i] = wlc->wsec_def_keys[i];
+ wlc->wsec_keys[i]->idx = (u8) i;
+ }
+
+ /* WME QoS mode is Auto by default */
+ wlc->pub->_wme = AUTO;
+
+#ifdef BCMSDIODEV_ENABLED
+ wlc->pub->_priofc = true; /* enable priority flow control for sdio dongle */
+#endif
+
+ wlc->pub->_ampdu = AMPDU_AGG_HOST;
+ wlc->pub->bcmerror = 0;
+ wlc->pub->_coex = ON;
+
+ /* initialize mpc delay */
+ wlc->mpc_delay_off = wlc->mpc_dlycnt = WLC_MPC_MIN_DELAYCNT;
+}
+
+static bool wlc_state_bmac_sync(struct wlc_info *wlc)
+{
+ wlc_bmac_state_t state_bmac;
+
+ if (wlc_bmac_state_get(wlc->hw, &state_bmac) != 0)
+ return false;
+
+ wlc->machwcap = state_bmac.machwcap;
+ wlc_protection_upd(wlc, WLC_PROT_N_PAM_OVR,
+ (s8) state_bmac.preamble_ovr);
+
+ return true;
+}
+
+static uint wlc_attach_module(struct wlc_info *wlc)
+{
+ uint err = 0;
+ uint unit;
+ unit = wlc->pub->unit;
+
+ wlc->asi = wlc_antsel_attach(wlc);
+ if (wlc->asi == NULL) {
+ wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_antsel_attach "
+ "failed\n", unit);
+ err = 44;
+ goto fail;
+ }
+
+ wlc->ampdu = wlc_ampdu_attach(wlc);
+ if (wlc->ampdu == NULL) {
+ wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_ampdu_attach "
+ "failed\n", unit);
+ err = 50;
+ goto fail;
+ }
+
+ if ((wlc_stf_attach(wlc) != 0)) {
+ wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_stf_attach "
+ "failed\n", unit);
+ err = 68;
+ goto fail;
+ }
+ fail:
+ return err;
+}
+
+struct wlc_pub *wlc_pub(void *wlc)
+{
+ return ((struct wlc_info *) wlc)->pub;
+}
+
+#define CHIP_SUPPORTS_11N(wlc) 1
+
+/*
+ * The common driver entry routine. Error codes should be unique
+ */
+void *wlc_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit,
+ bool piomode, void *regsva, uint bustype, void *btparam,
+ uint *perr)
+{
+ struct wlc_info *wlc;
+ uint err = 0;
+ uint j;
+ struct wlc_pub *pub;
+ uint n_disabled;
+
+ /* allocate struct wlc_info state and its substructures */
+ wlc = (struct wlc_info *) wlc_attach_malloc(unit, &err, device);
+ if (wlc == NULL)
+ goto fail;
+ wlc->wiphy = wl->wiphy;
+ pub = wlc->pub;
+
+#if defined(BCMDBG)
+ wlc_info_dbg = wlc;
+#endif
+
+ wlc->band = wlc->bandstate[0];
+ wlc->core = wlc->corestate;
+ wlc->wl = wl;
+ pub->unit = unit;
+ pub->_piomode = piomode;
+ wlc->bandinit_pending = false;
+
+ /* populate struct wlc_info with default values */
+ wlc_info_init(wlc, unit);
+
+ /* update sta/ap related parameters */
+ wlc_ap_upd(wlc);
+
+ /* 11n_disable nvram */
+ n_disabled = getintvar(pub->vars, "11n_disable");
+
+ /*
+ * low level attach steps(all hw accesses go
+ * inside, no more in rest of the attach)
+ */
+ err = wlc_bmac_attach(wlc, vendor, device, unit, piomode, regsva,
+ bustype, btparam);
+ if (err)
+ goto fail;
+
+ /* for some states, due to different info pointer(e,g, wlc, wlc_hw) or master/slave split,
+ * HIGH driver(both monolithic and HIGH_ONLY) needs to sync states FROM BMAC portion driver
+ */
+ if (!wlc_state_bmac_sync(wlc)) {
+ err = 20;
+ goto fail;
+ }
+
+ pub->phy_11ncapable = WLC_PHY_11N_CAP(wlc->band);
+
+ /* propagate *vars* from BMAC driver to high driver */
+ wlc_bmac_copyfrom_vars(wlc->hw, &pub->vars, &wlc->vars_size);
+
+
+ /* set maximum allowed duty cycle */
+ wlc->tx_duty_cycle_ofdm =
+ (u16) getintvar(pub->vars, "tx_duty_cycle_ofdm");
+ wlc->tx_duty_cycle_cck =
+ (u16) getintvar(pub->vars, "tx_duty_cycle_cck");
+
+ wlc_stf_phy_chain_calc(wlc);
+
+ /* txchain 1: txant 0, txchain 2: txant 1 */
+ if (WLCISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
+ wlc->stf->txant = wlc->stf->hw_txchain - 1;
+
+ /* push to BMAC driver */
+ wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
+ wlc->stf->hw_rxchain);
+
+ /* pull up some info resulting from the low attach */
+ {
+ int i;
+ for (i = 0; i < NFIFO; i++)
+ wlc->core->txavail[i] = wlc->hw->txavail[i];
+ }
+
+ wlc_bmac_hw_etheraddr(wlc->hw, wlc->perm_etheraddr);
+
+ memcpy(&pub->cur_etheraddr, &wlc->perm_etheraddr, ETH_ALEN);
+
+ for (j = 0; j < NBANDS(wlc); j++) {
+ /* Use band 1 for single band 11a */
+ if (IS_SINGLEBAND_5G(wlc->deviceid))
+ j = BAND_5G_INDEX;
+
+ wlc->band = wlc->bandstate[j];
+
+ if (!wlc_attach_stf_ant_init(wlc)) {
+ err = 24;
+ goto fail;
+ }
+
+ /* default contention windows size limits */
+ wlc->band->CWmin = APHY_CWMIN;
+ wlc->band->CWmax = PHY_CWMAX;
+
+ /* init gmode value */
+ if (BAND_2G(wlc->band->bandtype)) {
+ wlc->band->gmode = GMODE_AUTO;
+ wlc_protection_upd(wlc, WLC_PROT_G_USER,
+ wlc->band->gmode);
+ }
+
+ /* init _n_enab supported mode */
+ if (WLC_PHY_11N_CAP(wlc->band) && CHIP_SUPPORTS_11N(wlc)) {
+ if (n_disabled & WLFEATURE_DISABLE_11N) {
+ pub->_n_enab = OFF;
+ wlc_protection_upd(wlc, WLC_PROT_N_USER, OFF);
+ } else {
+ pub->_n_enab = SUPPORT_11N;
+ wlc_protection_upd(wlc, WLC_PROT_N_USER,
+ ((pub->_n_enab ==
+ SUPPORT_11N) ? WL_11N_2x2 :
+ WL_11N_3x3));
+ }
+ }
+
+ /* init per-band default rateset, depend on band->gmode */
+ wlc_default_rateset(wlc, &wlc->band->defrateset);
+
+ /* fill in hw_rateset (used early by WLC_SET_RATESET) */
+ wlc_rateset_filter(&wlc->band->defrateset,
+ &wlc->band->hw_rateset, false,
+ WLC_RATES_CCK_OFDM, WLC_RATE_MASK,
+ (bool) N_ENAB(wlc->pub));
+ }
+
+ /* update antenna config due to wlc->stf->txant/txchain/ant_rx_ovr change */
+ wlc_stf_phy_txant_upd(wlc);
+
+ /* attach each modules */
+ err = wlc_attach_module(wlc);
+ if (err != 0)
+ goto fail;
+
+ if (!wlc_timers_init(wlc, unit)) {
+ wiphy_err(wl->wiphy, "wl%d: %s: wlc_init_timer failed\n", unit,
+ __func__);
+ err = 32;
+ goto fail;
+ }
+
+ /* depend on rateset, gmode */
+ wlc->cmi = wlc_channel_mgr_attach(wlc);
+ if (!wlc->cmi) {
+ wiphy_err(wl->wiphy, "wl%d: %s: wlc_channel_mgr_attach failed"
+ "\n", unit, __func__);
+ err = 33;
+ goto fail;
+ }
+
+ /* init default when all parameters are ready, i.e. ->rateset */
+ wlc_bss_default_init(wlc);
+
+ /*
+ * Complete the wlc default state initializations..
+ */
+
+ /* allocate our initial queue */
+ wlc->pkt_queue = wlc_txq_alloc(wlc);
+ if (wlc->pkt_queue == NULL) {
+ wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
+ unit, __func__);
+ err = 100;
+ goto fail;
+ }
+
+ wlc->bsscfg[0] = wlc->cfg;
+ wlc->cfg->_idx = 0;
+ wlc->cfg->wlc = wlc;
+ pub->txmaxpkts = MAXTXPKTS;
+
+ wlc_wme_initparams_sta(wlc, &wlc->wme_param_ie);
+
+ wlc->mimoft = FT_HT;
+ wlc->ht_cap.cap_info = HT_CAP;
+ if (HT_ENAB(wlc->pub))
+ wlc->stf->ldpc = AUTO;
+
+ wlc->mimo_40txbw = AUTO;
+ wlc->ofdm_40txbw = AUTO;
+ wlc->cck_40txbw = AUTO;
+ wlc_update_mimo_band_bwcap(wlc, WLC_N_BW_20IN2G_40IN5G);
+
+ /* Set default values of SGI */
+ if (WLC_SGI_CAP_PHY(wlc)) {
+ wlc_ht_update_sgi_rx(wlc, (WLC_N_SGI_20 | WLC_N_SGI_40));
+ wlc->sgi_tx = AUTO;
+ } else if (WLCISSSLPNPHY(wlc->band)) {
+ wlc_ht_update_sgi_rx(wlc, (WLC_N_SGI_20 | WLC_N_SGI_40));
+ wlc->sgi_tx = AUTO;
+ } else {
+ wlc_ht_update_sgi_rx(wlc, 0);
+ wlc->sgi_tx = OFF;
+ }
+
+ /* *******nvram 11n config overrides Start ********* */
+
+ /* apply the sgi override from nvram conf */
+ if (n_disabled & WLFEATURE_DISABLE_11N_SGI_TX)
+ wlc->sgi_tx = OFF;
+
+ if (n_disabled & WLFEATURE_DISABLE_11N_SGI_RX)
+ wlc_ht_update_sgi_rx(wlc, 0);
+
+ /* apply the stbc override from nvram conf */
+ if (n_disabled & WLFEATURE_DISABLE_11N_STBC_TX) {
+ wlc->bandstate[BAND_2G_INDEX]->band_stf_stbc_tx = OFF;
+ wlc->bandstate[BAND_5G_INDEX]->band_stf_stbc_tx = OFF;
+ wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_TX_STBC;
+ }
+ if (n_disabled & WLFEATURE_DISABLE_11N_STBC_RX)
+ wlc_stf_stbc_rx_set(wlc, HT_CAP_RX_STBC_NO);
+
+ /* apply the GF override from nvram conf */
+ if (n_disabled & WLFEATURE_DISABLE_11N_GF)
+ wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_GRN_FLD;
+
+ /* initialize radio_mpc_disable according to wlc->mpc */
+ wlc_radio_mpc_upd(wlc);
+
+ if ((wlc->pub->sih->chip) == BCM43235_CHIP_ID) {
+ if ((getintvar(wlc->pub->vars, "aa2g") == 7) ||
+ (getintvar(wlc->pub->vars, "aa5g") == 7)) {
+ wlc_bmac_antsel_set(wlc->hw, 1);
+ }
+ } else {
+ wlc_bmac_antsel_set(wlc->hw, wlc->asi->antsel_avail);
+ }
+
+ if (perr)
+ *perr = 0;
+
+ return (void *)wlc;
+
+ fail:
+ wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
+ unit, __func__, err);
+ if (wlc)
+ wlc_detach(wlc);
+
+ if (perr)
+ *perr = err;
+ return NULL;
+}
+
+static void wlc_attach_antgain_init(struct wlc_info *wlc)
+{
+ uint unit;
+ unit = wlc->pub->unit;
+
+ if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
+ /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
+ wlc->band->antgain = 8;
+ } else if (wlc->band->antgain == -1) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
+ " srom, using 2dB\n", unit, __func__);
+ wlc->band->antgain = 8;
+ } else {
+ s8 gain, fract;
+ /* Older sroms specified gain in whole dbm only. In order
+ * be able to specify qdbm granularity and remain backward compatible
+ * the whole dbms are now encoded in only low 6 bits and remaining qdbms
+ * are encoded in the hi 2 bits. 6 bit signed number ranges from
+ * -32 - 31. Examples: 0x1 = 1 db,
+ * 0xc1 = 1.75 db (1 + 3 quarters),
+ * 0x3f = -1 (-1 + 0 quarters),
+ * 0x7f = -.75 (-1 in low 6 bits + 1 quarters in hi 2 bits) = -3 qdbm.
+ * 0xbf = -.50 (-1 in low 6 bits + 2 quarters in hi 2 bits) = -2 qdbm.
+ */
+ gain = wlc->band->antgain & 0x3f;
+ gain <<= 2; /* Sign extend */
+ gain >>= 2;
+ fract = (wlc->band->antgain & 0xc0) >> 6;
+ wlc->band->antgain = 4 * gain + fract;
+ }
+}
+
+static bool wlc_attach_stf_ant_init(struct wlc_info *wlc)
+{
+ int aa;
+ uint unit;
+ char *vars;
+ int bandtype;
+
+ unit = wlc->pub->unit;
+ vars = wlc->pub->vars;
+ bandtype = wlc->band->bandtype;
+
+ /* get antennas available */
+ aa = (s8) getintvar(vars, (BAND_5G(bandtype) ? "aa5g" : "aa2g"));
+ if (aa == 0)
+ aa = (s8) getintvar(vars,
+ (BAND_5G(bandtype) ? "aa1" : "aa0"));
+ if ((aa < 1) || (aa > 15)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
+ " srom (0x%x), using 3\n", unit, __func__, aa);
+ aa = 3;
+ }
+
+ /* reset the defaults if we have a single antenna */
+ if (aa == 1) {
+ wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
+ wlc->stf->txant = ANT_TX_FORCE_0;
+ } else if (aa == 2) {
+ wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
+ wlc->stf->txant = ANT_TX_FORCE_1;
+ } else {
+ }
+
+ /* Compute Antenna Gain */
+ wlc->band->antgain =
+ (s8) getintvar(vars, (BAND_5G(bandtype) ? "ag1" : "ag0"));
+ wlc_attach_antgain_init(wlc);
+
+ return true;
+}
+
+
+static void wlc_timers_deinit(struct wlc_info *wlc)
+{
+ /* free timer state */
+ if (wlc->wdtimer) {
+ brcms_free_timer(wlc->wl, wlc->wdtimer);
+ wlc->wdtimer = NULL;
+ }
+ if (wlc->radio_timer) {
+ brcms_free_timer(wlc->wl, wlc->radio_timer);
+ wlc->radio_timer = NULL;
+ }
+}
+
+static void wlc_detach_module(struct wlc_info *wlc)
+{
+ if (wlc->asi) {
+ wlc_antsel_detach(wlc->asi);
+ wlc->asi = NULL;
+ }
+
+ if (wlc->ampdu) {
+ wlc_ampdu_detach(wlc->ampdu);
+ wlc->ampdu = NULL;
+ }
+
+ wlc_stf_detach(wlc);
+}
+
+/*
+ * Return a count of the number of driver callbacks still pending.
+ *
+ * General policy is that wlc_detach can only dealloc/free software states. It can NOT
+ * touch hardware registers since the d11core may be in reset and clock may not be available.
+ * One exception is sb register access, which is possible if crystal is turned on
+ * After "down" state, driver should avoid software timer with the exception of radio_monitor.
+ */
+uint wlc_detach(struct wlc_info *wlc)
+{
+ uint callbacks = 0;
+
+ if (wlc == NULL)
+ return 0;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ callbacks += wlc_bmac_detach(wlc);
+
+ /* delete software timers */
+ if (!wlc_radio_monitor_stop(wlc))
+ callbacks++;
+
+ wlc_channel_mgr_detach(wlc->cmi);
+
+ wlc_timers_deinit(wlc);
+
+ wlc_detach_module(wlc);
+
+
+ while (wlc->tx_queues != NULL)
+ wlc_txq_free(wlc, wlc->tx_queues);
+
+ wlc_detach_mfree(wlc);
+ return callbacks;
+}
+
+/* update state that depends on the current value of "ap" */
+void wlc_ap_upd(struct wlc_info *wlc)
+{
+ if (AP_ENAB(wlc->pub))
+ wlc->PLCPHdr_override = WLC_PLCP_AUTO; /* AP: short not allowed, but not enforced */
+ else
+ wlc->PLCPHdr_override = WLC_PLCP_SHORT; /* STA-BSS; short capable */
+
+ /* fixup mpc */
+ wlc->mpc = true;
+}
+
+/* read hwdisable state and propagate to wlc flag */
+static void wlc_radio_hwdisable_upd(struct wlc_info *wlc)
+{
+ if (wlc->pub->wlfeatureflag & WL_SWFL_NOHWRADIO || wlc->pub->hw_off)
+ return;
+
+ if (wlc_bmac_radio_read_hwdisabled(wlc->hw)) {
+ mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
+ } else {
+ mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
+ }
+}
+
+/* return true if Minimum Power Consumption should be entered, false otherwise */
+bool wlc_is_non_delay_mpc(struct wlc_info *wlc)
+{
+ return false;
+}
+
+bool wlc_ismpc(struct wlc_info *wlc)
+{
+ return (wlc->mpc_delay_off == 0) && (wlc_is_non_delay_mpc(wlc));
+}
+
+void wlc_radio_mpc_upd(struct wlc_info *wlc)
+{
+ bool mpc_radio, radio_state;
+
+ /*
+ * Clear the WL_RADIO_MPC_DISABLE bit when mpc feature is disabled
+ * in case the WL_RADIO_MPC_DISABLE bit was set. Stop the radio
+ * monitor also when WL_RADIO_MPC_DISABLE is the only reason that
+ * the radio is going down.
+ */
+ if (!wlc->mpc) {
+ if (!wlc->pub->radio_disabled)
+ return;
+ mboolclr(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE);
+ wlc_radio_upd(wlc);
+ if (!wlc->pub->radio_disabled)
+ wlc_radio_monitor_stop(wlc);
+ return;
+ }
+
+ /*
+ * sync ismpc logic with WL_RADIO_MPC_DISABLE bit in wlc->pub->radio_disabled
+ * to go ON, always call radio_upd synchronously
+ * to go OFF, postpone radio_upd to later when context is safe(e.g. watchdog)
+ */
+ radio_state =
+ (mboolisset(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE) ? OFF :
+ ON);
+ mpc_radio = (wlc_ismpc(wlc) == true) ? OFF : ON;
+
+ if (radio_state == ON && mpc_radio == OFF)
+ wlc->mpc_delay_off = wlc->mpc_dlycnt;
+ else if (radio_state == OFF && mpc_radio == ON) {
+ mboolclr(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE);
+ wlc_radio_upd(wlc);
+ if (wlc->mpc_offcnt < WLC_MPC_THRESHOLD) {
+ wlc->mpc_dlycnt = WLC_MPC_MAX_DELAYCNT;
+ } else
+ wlc->mpc_dlycnt = WLC_MPC_MIN_DELAYCNT;
+ wlc->mpc_dur += OSL_SYSUPTIME() - wlc->mpc_laston_ts;
+ }
+ /* Below logic is meant to capture the transition from mpc off to mpc on for reasons
+ * other than wlc->mpc_delay_off keeping the mpc off. In that case reset
+ * wlc->mpc_delay_off to wlc->mpc_dlycnt, so that we restart the countdown of mpc_delay_off
+ */
+ if ((wlc->prev_non_delay_mpc == false) &&
+ (wlc_is_non_delay_mpc(wlc) == true) && wlc->mpc_delay_off) {
+ wlc->mpc_delay_off = wlc->mpc_dlycnt;
+ }
+ wlc->prev_non_delay_mpc = wlc_is_non_delay_mpc(wlc);
+}
+
+/*
+ * centralized radio disable/enable function,
+ * invoke radio enable/disable after updating hwradio status
+ */
+static void wlc_radio_upd(struct wlc_info *wlc)
+{
+ if (wlc->pub->radio_disabled) {
+ wlc_radio_disable(wlc);
+ } else {
+ wlc_radio_enable(wlc);
+ }
+}
+
+/* maintain LED behavior in down state */
+static void wlc_down_led_upd(struct wlc_info *wlc)
+{
+ /* maintain LEDs while in down state, turn on sbclk if not available yet */
+ /* turn on sbclk if necessary */
+ if (!AP_ENAB(wlc->pub)) {
+ wlc_pllreq(wlc, true, WLC_PLLREQ_FLIP);
+
+ wlc_pllreq(wlc, false, WLC_PLLREQ_FLIP);
+ }
+}
+
+/* update hwradio status and return it */
+bool wlc_check_radio_disabled(struct wlc_info *wlc)
+{
+ wlc_radio_hwdisable_upd(wlc);
+
+ return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ? true : false;
+}
+
+void wlc_radio_disable(struct wlc_info *wlc)
+{
+ if (!wlc->pub->up) {
+ wlc_down_led_upd(wlc);
+ return;
+ }
+
+ wlc_radio_monitor_start(wlc);
+ brcms_down(wlc->wl);
+}
+
+static void wlc_radio_enable(struct wlc_info *wlc)
+{
+ if (wlc->pub->up)
+ return;
+
+ if (DEVICEREMOVED(wlc))
+ return;
+
+ brcms_up(wlc->wl);
+}
+
+/* periodical query hw radio button while driver is "down" */
+static void wlc_radio_timer(void *arg)
+{
+ struct wlc_info *wlc = (struct wlc_info *) arg;
+
+ if (DEVICEREMOVED(wlc)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
+ __func__);
+ brcms_down(wlc->wl);
+ return;
+ }
+
+ /* cap mpc off count */
+ if (wlc->mpc_offcnt < WLC_MPC_MAX_DELAYCNT)
+ wlc->mpc_offcnt++;
+
+ wlc_radio_hwdisable_upd(wlc);
+ wlc_radio_upd(wlc);
+}
+
+static bool wlc_radio_monitor_start(struct wlc_info *wlc)
+{
+ /* Don't start the timer if HWRADIO feature is disabled */
+ if (wlc->radio_monitor || (wlc->pub->wlfeatureflag & WL_SWFL_NOHWRADIO))
+ return true;
+
+ wlc->radio_monitor = true;
+ wlc_pllreq(wlc, true, WLC_PLLREQ_RADIO_MON);
+ brcms_add_timer(wlc->wl, wlc->radio_timer, TIMER_INTERVAL_RADIOCHK,
+ true);
+ return true;
+}
+
+bool wlc_radio_monitor_stop(struct wlc_info *wlc)
+{
+ if (!wlc->radio_monitor)
+ return true;
+
+ wlc->radio_monitor = false;
+ wlc_pllreq(wlc, false, WLC_PLLREQ_RADIO_MON);
+ return brcms_del_timer(wlc->wl, wlc->radio_timer);
+}
+
+static void wlc_watchdog_by_timer(void *arg)
+{
+ wlc_watchdog(arg);
+}
+
+/* common watchdog code */
+static void wlc_watchdog(void *arg)
+{
+ struct wlc_info *wlc = (struct wlc_info *) arg;
+ int i;
+ struct wlc_bsscfg *cfg;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ if (!wlc->pub->up)
+ return;
+
+ if (DEVICEREMOVED(wlc)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
+ __func__);
+ brcms_down(wlc->wl);
+ return;
+ }
+
+ /* increment second count */
+ wlc->pub->now++;
+
+ /* delay radio disable */
+ if (wlc->mpc_delay_off) {
+ if (--wlc->mpc_delay_off == 0) {
+ mboolset(wlc->pub->radio_disabled,
+ WL_RADIO_MPC_DISABLE);
+ if (wlc->mpc && wlc_ismpc(wlc))
+ wlc->mpc_offcnt = 0;
+ wlc->mpc_laston_ts = OSL_SYSUPTIME();
+ }
+ }
+
+ /* mpc sync */
+ wlc_radio_mpc_upd(wlc);
+ /* radio sync: sw/hw/mpc --> radio_disable/radio_enable */
+ wlc_radio_hwdisable_upd(wlc);
+ wlc_radio_upd(wlc);
+ /* if radio is disable, driver may be down, quit here */
+ if (wlc->pub->radio_disabled)
+ return;
+
+ wlc_bmac_watchdog(wlc);
+
+ /* occasionally sample mac stat counters to detect 16-bit counter wrap */
+ if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
+ wlc_statsupd(wlc);
+
+ /* Manage TKIP countermeasures timers */
+ FOREACH_BSS(wlc, i, cfg) {
+ if (cfg->tk_cm_dt) {
+ cfg->tk_cm_dt--;
+ }
+ if (cfg->tk_cm_bt) {
+ cfg->tk_cm_bt--;
+ }
+ }
+
+ /* Call any registered watchdog handlers */
+ for (i = 0; i < WLC_MAXMODULES; i++) {
+ if (wlc->modulecb[i].watchdog_fn)
+ wlc->modulecb[i].watchdog_fn(wlc->modulecb[i].hdl);
+ }
+
+ if (WLCISNPHY(wlc->band) && !wlc->pub->tempsense_disable &&
+ ((wlc->pub->now - wlc->tempsense_lasttime) >=
+ WLC_TEMPSENSE_PERIOD)) {
+ wlc->tempsense_lasttime = wlc->pub->now;
+ wlc_tempsense_upd(wlc);
+ }
+}
+
+/* make interface operational */
+int wlc_up(struct wlc_info *wlc)
+{
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ /* HW is turned off so don't try to access it */
+ if (wlc->pub->hw_off || DEVICEREMOVED(wlc))
+ return -ENOMEDIUM;
+
+ if (!wlc->pub->hw_up) {
+ wlc_bmac_hw_up(wlc->hw);
+ wlc->pub->hw_up = true;
+ }
+
+ if ((wlc->pub->boardflags & BFL_FEM)
+ && (wlc->pub->sih->chip == BCM4313_CHIP_ID)) {
+ if (wlc->pub->boardrev >= 0x1250
+ && (wlc->pub->boardflags & BFL_FEM_BT)) {
+ wlc_mhf(wlc, MHF5, MHF5_4313_GPIOCTRL,
+ MHF5_4313_GPIOCTRL, WLC_BAND_ALL);
+ } else {
+ wlc_mhf(wlc, MHF4, MHF4_EXTPA_ENABLE, MHF4_EXTPA_ENABLE,
+ WLC_BAND_ALL);
+ }
+ }
+
+ /*
+ * Need to read the hwradio status here to cover the case where the system
+ * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
+ * if radio is disabled, abort up, lower power, start radio timer and return 0(for NDIS)
+ * don't call radio_update to avoid looping wlc_up.
+ *
+ * wlc_bmac_up_prep() returns either 0 or -BCME_RADIOOFF only
+ */
+ if (!wlc->pub->radio_disabled) {
+ int status = wlc_bmac_up_prep(wlc->hw);
+ if (status == -ENOMEDIUM) {
+ if (!mboolisset
+ (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
+ int idx;
+ struct wlc_bsscfg *bsscfg;
+ mboolset(wlc->pub->radio_disabled,
+ WL_RADIO_HW_DISABLE);
+
+ FOREACH_BSS(wlc, idx, bsscfg) {
+ if (!BSSCFG_STA(bsscfg)
+ || !bsscfg->enable || !bsscfg->BSS)
+ continue;
+ wiphy_err(wlc->wiphy, "wl%d.%d: wlc_up"
+ ": rfdisable -> "
+ "wlc_bsscfg_disable()\n",
+ wlc->pub->unit, idx);
+ }
+ }
+ }
+ }
+
+ if (wlc->pub->radio_disabled) {
+ wlc_radio_monitor_start(wlc);
+ return 0;
+ }
+
+ /* wlc_bmac_up_prep has done wlc_corereset(). so clk is on, set it */
+ wlc->clk = true;
+
+ wlc_radio_monitor_stop(wlc);
+
+ /* Set EDCF hostflags */
+ if (EDCF_ENAB(wlc->pub)) {
+ wlc_mhf(wlc, MHF1, MHF1_EDCF, MHF1_EDCF, WLC_BAND_ALL);
+ } else {
+ wlc_mhf(wlc, MHF1, MHF1_EDCF, 0, WLC_BAND_ALL);
+ }
+
+ if (WLC_WAR16165(wlc))
+ wlc_mhf(wlc, MHF2, MHF2_PCISLOWCLKWAR, MHF2_PCISLOWCLKWAR,
+ WLC_BAND_ALL);
+
+ brcms_init(wlc->wl);
+ wlc->pub->up = true;
+
+ if (wlc->bandinit_pending) {
+ wlc_suspend_mac_and_wait(wlc);
+ wlc_set_chanspec(wlc, wlc->default_bss->chanspec);
+ wlc->bandinit_pending = false;
+ wlc_enable_mac(wlc);
+ }
+
+ wlc_bmac_up_finish(wlc->hw);
+
+ /* other software states up after ISR is running */
+ /* start APs that were to be brought up but are not up yet */
+ /* if (AP_ENAB(wlc->pub)) wlc_restart_ap(wlc->ap); */
+
+ /* Program the TX wme params with the current settings */
+ wlc_wme_retries_write(wlc);
+
+ /* start one second watchdog timer */
+ brcms_add_timer(wlc->wl, wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
+ wlc->WDarmed = true;
+
+ /* ensure antenna config is up to date */
+ wlc_stf_phy_txant_upd(wlc);
+ /* ensure LDPC config is in sync */
+ wlc_ht_update_ldpc(wlc, wlc->stf->ldpc);
+
+ return 0;
+}
+
+/* Initialize the base precedence map for dequeueing from txq based on WME settings */
+static void wlc_tx_prec_map_init(struct wlc_info *wlc)
+{
+ wlc->tx_prec_map = WLC_PREC_BMP_ALL;
+ memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16));
+
+ /* For non-WME, both fifos have overlapping MAXPRIO. So just disable all precedences
+ * if either is full.
+ */
+ if (!EDCF_ENAB(wlc->pub)) {
+ wlc->fifo2prec_map[TX_DATA_FIFO] = WLC_PREC_BMP_ALL;
+ wlc->fifo2prec_map[TX_CTL_FIFO] = WLC_PREC_BMP_ALL;
+ } else {
+ wlc->fifo2prec_map[TX_AC_BK_FIFO] = WLC_PREC_BMP_AC_BK;
+ wlc->fifo2prec_map[TX_AC_BE_FIFO] = WLC_PREC_BMP_AC_BE;
+ wlc->fifo2prec_map[TX_AC_VI_FIFO] = WLC_PREC_BMP_AC_VI;
+ wlc->fifo2prec_map[TX_AC_VO_FIFO] = WLC_PREC_BMP_AC_VO;
+ }
+}
+
+static uint wlc_down_del_timer(struct wlc_info *wlc)
+{
+ uint callbacks = 0;
+
+ return callbacks;
+}
+
+/*
+ * Mark the interface nonoperational, stop the software mechanisms,
+ * disable the hardware, free any transient buffer state.
+ * Return a count of the number of driver callbacks still pending.
+ */
+uint wlc_down(struct wlc_info *wlc)
+{
+
+ uint callbacks = 0;
+ int i;
+ bool dev_gone = false;
+ struct wlc_txq_info *qi;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ /* check if we are already in the going down path */
+ if (wlc->going_down) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
+ "\n", wlc->pub->unit, __func__);
+ return 0;
+ }
+ if (!wlc->pub->up)
+ return callbacks;
+
+ /* in between, mpc could try to bring down again.. */
+ wlc->going_down = true;
+
+ callbacks += wlc_bmac_down_prep(wlc->hw);
+
+ dev_gone = DEVICEREMOVED(wlc);
+
+ /* Call any registered down handlers */
+ for (i = 0; i < WLC_MAXMODULES; i++) {
+ if (wlc->modulecb[i].down_fn)
+ callbacks +=
+ wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
+ }
+
+ /* cancel the watchdog timer */
+ if (wlc->WDarmed) {
+ if (!brcms_del_timer(wlc->wl, wlc->wdtimer))
+ callbacks++;
+ wlc->WDarmed = false;
+ }
+ /* cancel all other timers */
+ callbacks += wlc_down_del_timer(wlc);
+
+ wlc->pub->up = false;
+
+ wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
+
+ /* clear txq flow control */
+ wlc_txflowcontrol_reset(wlc);
+
+ /* flush tx queues */
+ for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
+ brcmu_pktq_flush(&qi->q, true, NULL, NULL);
+ }
+
+ callbacks += wlc_bmac_down_finish(wlc->hw);
+
+ /* wlc_bmac_down_finish has done wlc_coredisable(). so clk is off */
+ wlc->clk = false;
+
+ wlc->going_down = false;
+ return callbacks;
+}
+
+/* Set the current gmode configuration */
+int wlc_set_gmode(struct wlc_info *wlc, u8 gmode, bool config)
+{
+ int ret = 0;
+ uint i;
+ wlc_rateset_t rs;
+ /* Default to 54g Auto */
+ s8 shortslot = WLC_SHORTSLOT_AUTO; /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
+ bool shortslot_restrict = false; /* Restrict association to stations that support shortslot
+ */
+ bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
+ int preamble = WLC_PLCP_LONG; /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
+ bool preamble_restrict = false; /* Restrict association to stations that support short
+ * preambles
+ */
+ struct wlcband *band;
+
+ /* if N-support is enabled, allow Gmode set as long as requested
+ * Gmode is not GMODE_LEGACY_B
+ */
+ if (N_ENAB(wlc->pub) && gmode == GMODE_LEGACY_B)
+ return -ENOTSUPP;
+
+ /* verify that we are dealing with 2G band and grab the band pointer */
+ if (wlc->band->bandtype == WLC_BAND_2G)
+ band = wlc->band;
+ else if ((NBANDS(wlc) > 1) &&
+ (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == WLC_BAND_2G))
+ band = wlc->bandstate[OTHERBANDUNIT(wlc)];
+ else
+ return -EINVAL;
+
+ /* Legacy or bust when no OFDM is supported by regulatory */
+ if ((wlc_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
+ WLC_NO_OFDM) && (gmode != GMODE_LEGACY_B))
+ return -EINVAL;
+
+ /* update configuration value */
+ if (config == true)
+ wlc_protection_upd(wlc, WLC_PROT_G_USER, gmode);
+
+ /* Clear supported rates filter */
+ memset(&wlc->sup_rates_override, 0, sizeof(wlc_rateset_t));
+
+ /* Clear rateset override */
+ memset(&rs, 0, sizeof(wlc_rateset_t));
+
+ switch (gmode) {
+ case GMODE_LEGACY_B:
+ shortslot = WLC_SHORTSLOT_OFF;
+ wlc_rateset_copy(&gphy_legacy_rates, &rs);
+
+ break;
+
+ case GMODE_LRS:
+ if (AP_ENAB(wlc->pub))
+ wlc_rateset_copy(&cck_rates, &wlc->sup_rates_override);
+ break;
+
+ case GMODE_AUTO:
+ /* Accept defaults */
+ break;
+
+ case GMODE_ONLY:
+ ofdm_basic = true;
+ preamble = WLC_PLCP_SHORT;
+ preamble_restrict = true;
+ break;
+
+ case GMODE_PERFORMANCE:
+ if (AP_ENAB(wlc->pub)) /* Put all rates into the Supported Rates element */
+ wlc_rateset_copy(&cck_ofdm_rates,
+ &wlc->sup_rates_override);
+
+ shortslot = WLC_SHORTSLOT_ON;
+ shortslot_restrict = true;
+ ofdm_basic = true;
+ preamble = WLC_PLCP_SHORT;
+ preamble_restrict = true;
+ break;
+
+ default:
+ /* Error */
+ wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
+ wlc->pub->unit, __func__, gmode);
+ return -ENOTSUPP;
+ }
+
+ /*
+ * If we are switching to gmode == GMODE_LEGACY_B,
+ * clean up rate info that may refer to OFDM rates.
+ */
+ if ((gmode == GMODE_LEGACY_B) && (band->gmode != GMODE_LEGACY_B)) {
+ band->gmode = gmode;
+ if (band->rspec_override && !IS_CCK(band->rspec_override)) {
+ band->rspec_override = 0;
+ wlc_reprate_init(wlc);
+ }
+ if (band->mrspec_override && !IS_CCK(band->mrspec_override)) {
+ band->mrspec_override = 0;
+ }
+ }
+
+ band->gmode = gmode;
+
+ wlc->shortslot_override = shortslot;
+
+ if (AP_ENAB(wlc->pub)) {
+ /* wlc->ap->shortslot_restrict = shortslot_restrict; */
+ wlc->PLCPHdr_override =
+ (preamble !=
+ WLC_PLCP_LONG) ? WLC_PLCP_SHORT : WLC_PLCP_AUTO;
+ }
+
+ if ((AP_ENAB(wlc->pub) && preamble != WLC_PLCP_LONG)
+ || preamble == WLC_PLCP_SHORT)
+ wlc->default_bss->capability |= WLAN_CAPABILITY_SHORT_PREAMBLE;
+ else
+ wlc->default_bss->capability &= ~WLAN_CAPABILITY_SHORT_PREAMBLE;
+
+ /* Update shortslot capability bit for AP and IBSS */
+ if ((AP_ENAB(wlc->pub) && shortslot == WLC_SHORTSLOT_AUTO) ||
+ shortslot == WLC_SHORTSLOT_ON)
+ wlc->default_bss->capability |= WLAN_CAPABILITY_SHORT_SLOT_TIME;
+ else
+ wlc->default_bss->capability &=
+ ~WLAN_CAPABILITY_SHORT_SLOT_TIME;
+
+ /* Use the default 11g rateset */
+ if (!rs.count)
+ wlc_rateset_copy(&cck_ofdm_rates, &rs);
+
+ if (ofdm_basic) {
+ for (i = 0; i < rs.count; i++) {
+ if (rs.rates[i] == WLC_RATE_6M
+ || rs.rates[i] == WLC_RATE_12M
+ || rs.rates[i] == WLC_RATE_24M)
+ rs.rates[i] |= WLC_RATE_FLAG;
+ }
+ }
+
+ /* Set default bss rateset */
+ wlc->default_bss->rateset.count = rs.count;
+ memcpy(wlc->default_bss->rateset.rates, rs.rates,
+ sizeof(wlc->default_bss->rateset.rates));
+
+ return ret;
+}
+
+static int wlc_nmode_validate(struct wlc_info *wlc, s32 nmode)
+{
+ int err = 0;
+
+ switch (nmode) {
+
+ case OFF:
+ break;
+
+ case AUTO:
+ case WL_11N_2x2:
+ case WL_11N_3x3:
+ if (!(WLC_PHY_11N_CAP(wlc->band)))
+ err = -EINVAL;
+ break;
+
+ default:
+ err = -EINVAL;
+ break;
+ }
+
+ return err;
+}
+
+int wlc_set_nmode(struct wlc_info *wlc, s32 nmode)
+{
+ uint i;
+ int err;
+
+ err = wlc_nmode_validate(wlc, nmode);
+ if (err)
+ return err;
+
+ switch (nmode) {
+ case OFF:
+ wlc->pub->_n_enab = OFF;
+ wlc->default_bss->flags &= ~WLC_BSS_HT;
+ /* delete the mcs rates from the default and hw ratesets */
+ wlc_rateset_mcs_clear(&wlc->default_bss->rateset);
+ for (i = 0; i < NBANDS(wlc); i++) {
+ memset(wlc->bandstate[i]->hw_rateset.mcs, 0,
+ MCSSET_LEN);
+ if (IS_MCS(wlc->band->rspec_override)) {
+ wlc->bandstate[i]->rspec_override = 0;
+ wlc_reprate_init(wlc);
+ }
+ if (IS_MCS(wlc->band->mrspec_override))
+ wlc->bandstate[i]->mrspec_override = 0;
+ }
+ break;
+
+ case AUTO:
+ if (wlc->stf->txstreams == WL_11N_3x3)
+ nmode = WL_11N_3x3;
+ else
+ nmode = WL_11N_2x2;
+ case WL_11N_2x2:
+ case WL_11N_3x3:
+ /* force GMODE_AUTO if NMODE is ON */
+ wlc_set_gmode(wlc, GMODE_AUTO, true);
+ if (nmode == WL_11N_3x3)
+ wlc->pub->_n_enab = SUPPORT_HT;
+ else
+ wlc->pub->_n_enab = SUPPORT_11N;
+ wlc->default_bss->flags |= WLC_BSS_HT;
+ /* add the mcs rates to the default and hw ratesets */
+ wlc_rateset_mcs_build(&wlc->default_bss->rateset,
+ wlc->stf->txstreams);
+ for (i = 0; i < NBANDS(wlc); i++)
+ memcpy(wlc->bandstate[i]->hw_rateset.mcs,
+ wlc->default_bss->rateset.mcs, MCSSET_LEN);
+ break;
+
+ default:
+ break;
+ }
+
+ return err;
+}
+
+static int wlc_set_rateset(struct wlc_info *wlc, wlc_rateset_t *rs_arg)
+{
+ wlc_rateset_t rs, new;
+ uint bandunit;
+
+ memcpy(&rs, rs_arg, sizeof(wlc_rateset_t));
+
+ /* check for bad count value */
+ if ((rs.count == 0) || (rs.count > WLC_NUMRATES))
+ return -EINVAL;
+
+ /* try the current band */
+ bandunit = wlc->band->bandunit;
+ memcpy(&new, &rs, sizeof(wlc_rateset_t));
+ if (wlc_rate_hwrs_filter_sort_validate
+ (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
+ wlc->stf->txstreams))
+ goto good;
+
+ /* try the other band */
+ if (IS_MBAND_UNLOCKED(wlc)) {
+ bandunit = OTHERBANDUNIT(wlc);
+ memcpy(&new, &rs, sizeof(wlc_rateset_t));
+ if (wlc_rate_hwrs_filter_sort_validate(&new,
+ &wlc->
+ bandstate[bandunit]->
+ hw_rateset, true,
+ wlc->stf->txstreams))
+ goto good;
+ }
+
+ return -EBADE;
+
+ good:
+ /* apply new rateset */
+ memcpy(&wlc->default_bss->rateset, &new, sizeof(wlc_rateset_t));
+ memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
+ sizeof(wlc_rateset_t));
+ return 0;
+}
+
+/* simplified integer set interface for common ioctl handler */
+int wlc_set(struct wlc_info *wlc, int cmd, int arg)
+{
+ return wlc_ioctl(wlc, cmd, (void *)&arg, sizeof(arg), NULL);
+}
+
+/* simplified integer get interface for common ioctl handler */
+int wlc_get(struct wlc_info *wlc, int cmd, int *arg)
+{
+ return wlc_ioctl(wlc, cmd, arg, sizeof(int), NULL);
+}
+
+static void wlc_ofdm_rateset_war(struct wlc_info *wlc)
+{
+ u8 r;
+ bool war = false;
+
+ if (wlc->cfg->associated)
+ r = wlc->cfg->current_bss->rateset.rates[0];
+ else
+ r = wlc->default_bss->rateset.rates[0];
+
+ wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
+
+ return;
+}
+
+int
+wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
+ struct wlc_if *wlcif)
+{
+ return _wlc_ioctl(wlc, cmd, arg, len, wlcif);
+}
+
+/* common ioctl handler. return: 0=ok, -1=error, positive=particular error */
+static int
+_wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
+ struct wlc_if *wlcif)
+{
+ int val, *pval;
+ bool bool_val;
+ int bcmerror;
+ d11regs_t *regs;
+ struct scb *nextscb;
+ bool ta_ok;
+ uint band;
+ struct wlc_bsscfg *bsscfg;
+ wlc_bss_info_t *current_bss;
+
+ /* update bsscfg pointer */
+ bsscfg = wlc->cfg;
+ current_bss = bsscfg->current_bss;
+
+ /* initialize the following to get rid of compiler warning */
+ nextscb = NULL;
+ ta_ok = false;
+ band = 0;
+
+ /* If the device is turned off, then it's not "removed" */
+ if (!wlc->pub->hw_off && DEVICEREMOVED(wlc)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
+ __func__);
+ brcms_down(wlc->wl);
+ return -EBADE;
+ }
+
+ /* default argument is generic integer */
+ pval = arg ? (int *)arg:NULL;
+
+ /* This will prevent the misaligned access */
+ if (pval && (u32) len >= sizeof(val))
+ memcpy(&val, pval, sizeof(val));
+ else
+ val = 0;
+
+ /* bool conversion to avoid duplication below */
+ bool_val = val != 0;
+ bcmerror = 0;
+ regs = wlc->regs;
+
+ if ((arg == NULL) || (len <= 0)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Command %d needs arguments\n",
+ wlc->pub->unit, __func__, cmd);
+ bcmerror = -EINVAL;
+ goto done;
+ }
+
+ switch (cmd) {
+
+ case WLC_SET_CHANNEL:{
+ chanspec_t chspec = CH20MHZ_CHSPEC(val);
+
+ if (val < 0 || val > MAXCHANNEL) {
+ bcmerror = -EINVAL;
+ break;
+ }
+
+ if (!wlc_valid_chanspec_db(wlc->cmi, chspec)) {
+ bcmerror = -EINVAL;
+ break;
+ }
+
+ if (!wlc->pub->up && IS_MBAND_UNLOCKED(wlc)) {
+ if (wlc->band->bandunit !=
+ CHSPEC_WLCBANDUNIT(chspec))
+ wlc->bandinit_pending = true;
+ else
+ wlc->bandinit_pending = false;
+ }
+
+ wlc->default_bss->chanspec = chspec;
+ /* wlc_BSSinit() will sanitize the rateset before using it.. */
+ if (wlc->pub->up &&
+ (WLC_BAND_PI_RADIO_CHANSPEC != chspec)) {
+ wlc_set_home_chanspec(wlc, chspec);
+ wlc_suspend_mac_and_wait(wlc);
+ wlc_set_chanspec(wlc, chspec);
+ wlc_enable_mac(wlc);
+ }
+ break;
+ }
+
+ case WLC_SET_SRL:
+ if (val >= 1 && val <= RETRY_SHORT_MAX) {
+ int ac;
+ wlc->SRL = (u16) val;
+
+ wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
+
+ for (ac = 0; ac < AC_COUNT; ac++) {
+ WLC_WME_RETRY_SHORT_SET(wlc, ac, wlc->SRL);
+ }
+ wlc_wme_retries_write(wlc);
+ } else
+ bcmerror = -EINVAL;
+ break;
+
+ case WLC_SET_LRL:
+ if (val >= 1 && val <= 255) {
+ int ac;
+ wlc->LRL = (u16) val;
+
+ wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
+
+ for (ac = 0; ac < AC_COUNT; ac++) {
+ WLC_WME_RETRY_LONG_SET(wlc, ac, wlc->LRL);
+ }
+ wlc_wme_retries_write(wlc);
+ } else
+ bcmerror = -EINVAL;
+ break;
+
+ case WLC_GET_CURR_RATESET:{
+ wl_rateset_t *ret_rs = (wl_rateset_t *) arg;
+ wlc_rateset_t *rs;
+
+ if (wlc->pub->associated)
+ rs = ¤t_bss->rateset;
+ else
+ rs = &wlc->default_bss->rateset;
+
+ if (len < (int)(rs->count + sizeof(rs->count))) {
+ bcmerror = -EOVERFLOW;
+ break;
+ }
+
+ /* Copy only legacy rateset section */
+ ret_rs->count = rs->count;
+ memcpy(&ret_rs->rates, &rs->rates, rs->count);
+ break;
+ }
+
+ case WLC_SET_RATESET:{
+ wlc_rateset_t rs;
+ wl_rateset_t *in_rs = (wl_rateset_t *) arg;
+
+ if (len < (int)(in_rs->count + sizeof(in_rs->count))) {
+ bcmerror = -EOVERFLOW;
+ break;
+ }
+
+ if (in_rs->count > WLC_NUMRATES) {
+ bcmerror = -ENOBUFS;
+ break;
+ }
+
+ memset(&rs, 0, sizeof(wlc_rateset_t));
+
+ /* Copy only legacy rateset section */
+ rs.count = in_rs->count;
+ memcpy(&rs.rates, &in_rs->rates, rs.count);
+
+ /* merge rateset coming in with the current mcsset */
+ if (N_ENAB(wlc->pub)) {
+ if (bsscfg->associated)
+ memcpy(rs.mcs,
+ ¤t_bss->rateset.mcs[0],
+ MCSSET_LEN);
+ else
+ memcpy(rs.mcs,
+ &wlc->default_bss->rateset.mcs[0],
+ MCSSET_LEN);
+ }
+
+ bcmerror = wlc_set_rateset(wlc, &rs);
+
+ if (!bcmerror)
+ wlc_ofdm_rateset_war(wlc);
+
+ break;
+ }
+
+ case WLC_SET_BCNPRD:
+ /* range [1, 0xffff] */
+ if (val >= DOT11_MIN_BEACON_PERIOD
+ && val <= DOT11_MAX_BEACON_PERIOD) {
+ wlc->default_bss->beacon_period = (u16) val;
+ } else
+ bcmerror = -EINVAL;
+ break;
+
+ case WLC_GET_PHYLIST:
+ {
+ unsigned char *cp = arg;
+ if (len < 3) {
+ bcmerror = -EOVERFLOW;
+ break;
+ }
+
+ if (WLCISNPHY(wlc->band)) {
+ *cp++ = 'n';
+ } else if (WLCISLCNPHY(wlc->band)) {
+ *cp++ = 'c';
+ } else if (WLCISSSLPNPHY(wlc->band)) {
+ *cp++ = 's';
+ }
+ *cp = '\0';
+ break;
+ }
+
+ case WLC_SET_SHORTSLOT_OVERRIDE:
+ if ((val != WLC_SHORTSLOT_AUTO) &&
+ (val != WLC_SHORTSLOT_OFF) && (val != WLC_SHORTSLOT_ON)) {
+ bcmerror = -EINVAL;
+ break;
+ }
+
+ wlc->shortslot_override = (s8) val;
+
+ /* shortslot is an 11g feature, so no more work if we are
+ * currently on the 5G band
+ */
+ if (BAND_5G(wlc->band->bandtype))
+ break;
+
+ if (wlc->pub->up && wlc->pub->associated) {
+ /* let watchdog or beacon processing update shortslot */
+ } else if (wlc->pub->up) {
+ /* unassociated shortslot is off */
+ wlc_switch_shortslot(wlc, false);
+ } else {
+ /* driver is down, so just update the wlc_info value */
+ if (wlc->shortslot_override == WLC_SHORTSLOT_AUTO) {
+ wlc->shortslot = false;
+ } else {
+ wlc->shortslot =
+ (wlc->shortslot_override ==
+ WLC_SHORTSLOT_ON);
+ }
+ }
+
+ break;
+
+ }
+ done:
+
+ if (bcmerror)
+ wlc->pub->bcmerror = bcmerror;
+
+ return bcmerror;
+}
+
+/*
+ * register watchdog and down handlers.
+ */
+int wlc_module_register(struct wlc_pub *pub,
+ const char *name, void *hdl,
+ watchdog_fn_t w_fn, down_fn_t d_fn)
+{
+ struct wlc_info *wlc = (struct wlc_info *) pub->wlc;
+ int i;
+
+ /* find an empty entry and just add, no duplication check! */
+ for (i = 0; i < WLC_MAXMODULES; i++) {
+ if (wlc->modulecb[i].name[0] == '\0') {
+ strncpy(wlc->modulecb[i].name, name,
+ sizeof(wlc->modulecb[i].name) - 1);
+ wlc->modulecb[i].hdl = hdl;
+ wlc->modulecb[i].watchdog_fn = w_fn;
+ wlc->modulecb[i].down_fn = d_fn;
+ return 0;
+ }
+ }
+
+ return -ENOSR;
+}
+
+/* unregister module callbacks */
+int wlc_module_unregister(struct wlc_pub *pub, const char *name, void *hdl)
+{
+ struct wlc_info *wlc = (struct wlc_info *) pub->wlc;
+ int i;
+
+ if (wlc == NULL)
+ return -ENODATA;
+
+ for (i = 0; i < WLC_MAXMODULES; i++) {
+ if (!strcmp(wlc->modulecb[i].name, name) &&
+ (wlc->modulecb[i].hdl == hdl)) {
+ memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
+ return 0;
+ }
+ }
+
+ /* table not found! */
+ return -ENODATA;
+}
+
+/* Write WME tunable parameters for retransmit/max rate from wlc struct to ucode */
+static void wlc_wme_retries_write(struct wlc_info *wlc)
+{
+ int ac;
+
+ /* Need clock to do this */
+ if (!wlc->clk)
+ return;
+
+ for (ac = 0; ac < AC_COUNT; ac++) {
+ wlc_write_shm(wlc, M_AC_TXLMT_ADDR(ac), wlc->wme_retries[ac]);
+ }
+}
+
+#ifdef BCMDBG
+static const char *supr_reason[] = {
+ "None", "PMQ Entry", "Flush request",
+ "Previous frag failure", "Channel mismatch",
+ "Lifetime Expiry", "Underflow"
+};
+
+static void wlc_print_txs_status(u16 s)
+{
+ printk(KERN_DEBUG "[15:12] %d frame attempts\n",
+ (s & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT);
+ printk(KERN_DEBUG " [11:8] %d rts attempts\n",
+ (s & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT);
+ printk(KERN_DEBUG " [7] %d PM mode indicated\n",
+ ((s & TX_STATUS_PMINDCTD) ? 1 : 0));
+ printk(KERN_DEBUG " [6] %d intermediate status\n",
+ ((s & TX_STATUS_INTERMEDIATE) ? 1 : 0));
+ printk(KERN_DEBUG " [5] %d AMPDU\n",
+ (s & TX_STATUS_AMPDU) ? 1 : 0);
+ printk(KERN_DEBUG " [4:2] %d Frame Suppressed Reason (%s)\n",
+ ((s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT),
+ supr_reason[(s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT]);
+ printk(KERN_DEBUG " [1] %d acked\n",
+ ((s & TX_STATUS_ACK_RCV) ? 1 : 0));
+}
+#endif /* BCMDBG */
+
+void wlc_print_txstatus(tx_status_t *txs)
+{
+#if defined(BCMDBG)
+ u16 s = txs->status;
+ u16 ackphyrxsh = txs->ackphyrxsh;
+
+ printk(KERN_DEBUG "\ntxpkt (MPDU) Complete\n");
+
+ printk(KERN_DEBUG "FrameID: %04x ", txs->frameid);
+ printk(KERN_DEBUG "TxStatus: %04x", s);
+ printk(KERN_DEBUG "\n");
+
+ wlc_print_txs_status(s);
+
+ printk(KERN_DEBUG "LastTxTime: %04x ", txs->lasttxtime);
+ printk(KERN_DEBUG "Seq: %04x ", txs->sequence);
+ printk(KERN_DEBUG "PHYTxStatus: %04x ", txs->phyerr);
+ printk(KERN_DEBUG "RxAckRSSI: %04x ",
+ (ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT);
+ printk(KERN_DEBUG "RxAckSQ: %04x",
+ (ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
+ printk(KERN_DEBUG "\n");
+#endif /* defined(BCMDBG) */
+}
+
+void wlc_statsupd(struct wlc_info *wlc)
+{
+ int i;
+ macstat_t macstats;
+#ifdef BCMDBG
+ u16 delta;
+ u16 rxf0ovfl;
+ u16 txfunfl[NFIFO];
+#endif /* BCMDBG */
+
+ /* if driver down, make no sense to update stats */
+ if (!wlc->pub->up)
+ return;
+
+#ifdef BCMDBG
+ /* save last rx fifo 0 overflow count */
+ rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
+
+ /* save last tx fifo underflow count */
+ for (i = 0; i < NFIFO; i++)
+ txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
+#endif /* BCMDBG */
+
+ /* Read mac stats from contiguous shared memory */
+ wlc_bmac_copyfrom_shm(wlc->hw, M_UCODE_MACSTAT,
+ &macstats, sizeof(macstat_t));
+
+#ifdef BCMDBG
+ /* check for rx fifo 0 overflow */
+ delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
+ if (delta)
+ wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
+ wlc->pub->unit, delta);
+
+ /* check for tx fifo underflows */
+ for (i = 0; i < NFIFO; i++) {
+ delta =
+ (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
+ txfunfl[i]);
+ if (delta)
+ wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
+ "\n", wlc->pub->unit, delta, i);
+ }
+#endif /* BCMDBG */
+
+ /* merge counters from dma module */
+ for (i = 0; i < NFIFO; i++) {
+ if (wlc->hw->di[i]) {
+ dma_counterreset(wlc->hw->di[i]);
+ }
+ }
+}
+
+bool wlc_chipmatch(u16 vendor, u16 device)
+{
+ if (vendor != PCI_VENDOR_ID_BROADCOM) {
+ pr_err("wlc_chipmatch: unknown vendor id %04x\n", vendor);
+ return false;
+ }
+
+ if (device == BCM43224_D11N_ID_VEN1)
+ return true;
+ if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
+ return true;
+ if (device == BCM4313_D11N2G_ID)
+ return true;
+ if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
+ return true;
+
+ pr_err("wlc_chipmatch: unknown device id %04x\n", device);
+ return false;
+}
+
+#if defined(BCMDBG)
+void wlc_print_txdesc(d11txh_t *txh)
+{
+ u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
+ u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
+ u16 mfc = le16_to_cpu(txh->MacFrameControl);
+ u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
+ u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
+ u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
+ u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
+ u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
+ u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
+ u16 mainrates = le16_to_cpu(txh->MainRates);
+ u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
+ u8 *iv = txh->IV;
+ u8 *ra = txh->TxFrameRA;
+ u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
+ u8 *rtspfb = txh->RTSPLCPFallback;
+ u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
+ u8 *fragpfb = txh->FragPLCPFallback;
+ u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
+ u16 mmodelen = le16_to_cpu(txh->MModeLen);
+ u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
+ u16 tfid = le16_to_cpu(txh->TxFrameID);
+ u16 txs = le16_to_cpu(txh->TxStatus);
+ u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
+ u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
+ u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
+ u16 mmbyte = le16_to_cpu(txh->MinMBytes);
+
+ u8 *rtsph = txh->RTSPhyHeader;
+ struct ieee80211_rts rts = txh->rts_frame;
+ char hexbuf[256];
+
+ /* add plcp header along with txh descriptor */
+ printk(KERN_DEBUG "Raw TxDesc + plcp header:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ txh, sizeof(d11txh_t) + 48);
+
+ printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl);
+ printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch);
+ printk(KERN_DEBUG "FC: %04x ", mfc);
+ printk(KERN_DEBUG "FES Time: %04x\n", tfest);
+ printk(KERN_DEBUG "PhyCtl: %04x%s ", ptcw,
+ (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
+ printk(KERN_DEBUG "PhyCtl_1: %04x ", ptcw_1);
+ printk(KERN_DEBUG "PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
+ printk(KERN_DEBUG "PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
+ printk(KERN_DEBUG "PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
+ printk(KERN_DEBUG "MainRates: %04x ", mainrates);
+ printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft);
+ printk(KERN_DEBUG "\n");
+
+ brcmu_format_hex(hexbuf, iv, sizeof(txh->IV));
+ printk(KERN_DEBUG "SecIV: %s\n", hexbuf);
+ brcmu_format_hex(hexbuf, ra, sizeof(txh->TxFrameRA));
+ printk(KERN_DEBUG "RA: %s\n", hexbuf);
+
+ printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb);
+ brcmu_format_hex(hexbuf, rtspfb, sizeof(txh->RTSPLCPFallback));
+ printk(KERN_DEBUG "RTS PLCP: %s ", hexbuf);
+ printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb);
+ brcmu_format_hex(hexbuf, fragpfb, sizeof(txh->FragPLCPFallback));
+ printk(KERN_DEBUG "PLCP: %s ", hexbuf);
+ printk(KERN_DEBUG "DUR: %04x", fragdfb);
+ printk(KERN_DEBUG "\n");
+
+ printk(KERN_DEBUG "MModeLen: %04x ", mmodelen);
+ printk(KERN_DEBUG "MModeFbrLen: %04x\n", mmodefbrlen);
+
+ printk(KERN_DEBUG "FrameID: %04x\n", tfid);
+ printk(KERN_DEBUG "TxStatus: %04x\n", txs);
+
+ printk(KERN_DEBUG "MaxNumMpdu: %04x\n", mnmpdu);
+ printk(KERN_DEBUG "MaxAggbyte: %04x\n", mabyte);
+ printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f);
+ printk(KERN_DEBUG "MinByte: %04x\n", mmbyte);
+
+ brcmu_format_hex(hexbuf, rtsph, sizeof(txh->RTSPhyHeader));
+ printk(KERN_DEBUG "RTS PLCP: %s ", hexbuf);
+ brcmu_format_hex(hexbuf, (u8 *) &rts, sizeof(txh->rts_frame));
+ printk(KERN_DEBUG "RTS Frame: %s", hexbuf);
+ printk(KERN_DEBUG "\n");
+}
+#endif /* defined(BCMDBG) */
+
+#if defined(BCMDBG)
+void wlc_print_rxh(d11rxhdr_t *rxh)
+{
+ u16 len = rxh->RxFrameSize;
+ u16 phystatus_0 = rxh->PhyRxStatus_0;
+ u16 phystatus_1 = rxh->PhyRxStatus_1;
+ u16 phystatus_2 = rxh->PhyRxStatus_2;
+ u16 phystatus_3 = rxh->PhyRxStatus_3;
+ u16 macstatus1 = rxh->RxStatus1;
+ u16 macstatus2 = rxh->RxStatus2;
+ char flagstr[64];
+ char lenbuf[20];
+ static const struct brcmu_bit_desc macstat_flags[] = {
+ {RXS_FCSERR, "FCSErr"},
+ {RXS_RESPFRAMETX, "Reply"},
+ {RXS_PBPRES, "PADDING"},
+ {RXS_DECATMPT, "DeCr"},
+ {RXS_DECERR, "DeCrErr"},
+ {RXS_BCNSENT, "Bcn"},
+ {0, NULL}
+ };
+
+ printk(KERN_DEBUG "Raw RxDesc:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh, sizeof(d11rxhdr_t));
+
+ brcmu_format_flags(macstat_flags, macstatus1, flagstr, 64);
+
+ snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
+
+ printk(KERN_DEBUG "RxFrameSize: %6s (%d)%s\n", lenbuf, len,
+ (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
+ printk(KERN_DEBUG "RxPHYStatus: %04x %04x %04x %04x\n",
+ phystatus_0, phystatus_1, phystatus_2, phystatus_3);
+ printk(KERN_DEBUG "RxMACStatus: %x %s\n", macstatus1, flagstr);
+ printk(KERN_DEBUG "RXMACaggtype: %x\n",
+ (macstatus2 & RXS_AGGTYPE_MASK));
+ printk(KERN_DEBUG "RxTSFTime: %04x\n", rxh->RxTSFTime);
+}
+#endif /* defined(BCMDBG) */
+
+static u16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate)
+{
+ return wlc_bmac_rate_shm_offset(wlc->hw, rate);
+}
+
+/* Callback for device removed */
+
+/*
+ * Attempts to queue a packet onto a multiple-precedence queue,
+ * if necessary evicting a lower precedence packet from the queue.
+ *
+ * 'prec' is the precedence number that has already been mapped
+ * from the packet priority.
+ *
+ * Returns true if packet consumed (queued), false if not.
+ */
+bool
+wlc_prec_enq(struct wlc_info *wlc, struct pktq *q, void *pkt, int prec)
+{
+ return wlc_prec_enq_head(wlc, q, pkt, prec, false);
+}
+
+bool
+wlc_prec_enq_head(struct wlc_info *wlc, struct pktq *q, struct sk_buff *pkt,
+ int prec, bool head)
+{
+ struct sk_buff *p;
+ int eprec = -1; /* precedence to evict from */
+
+ /* Determine precedence from which to evict packet, if any */
+ if (pktq_pfull(q, prec))
+ eprec = prec;
+ else if (pktq_full(q)) {
+ p = brcmu_pktq_peek_tail(q, &eprec);
+ if (eprec > prec) {
+ wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
+ "\n", __func__, eprec, prec);
+ return false;
+ }
+ }
+
+ /* Evict if needed */
+ if (eprec >= 0) {
+ bool discard_oldest;
+
+ discard_oldest = AC_BITMAP_TST(wlc->wme_dp, eprec);
+
+ /* Refuse newer packet unless configured to discard oldest */
+ if (eprec == prec && !discard_oldest) {
+ wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
+ "\n", __func__, prec);
+ return false;
+ }
+
+ /* Evict packet according to discard policy */
+ p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
+ brcmu_pktq_pdeq_tail(q, eprec);
+ brcmu_pkt_buf_free_skb(p);
+ }
+
+ /* Enqueue */
+ if (head)
+ p = brcmu_pktq_penq_head(q, prec, pkt);
+ else
+ p = brcmu_pktq_penq(q, prec, pkt);
+
+ return true;
+}
+
+void wlc_txq_enq(void *ctx, struct scb *scb, struct sk_buff *sdu,
+ uint prec)
+{
+ struct wlc_info *wlc = (struct wlc_info *) ctx;
+ struct wlc_txq_info *qi = wlc->pkt_queue; /* Check me */
+ struct pktq *q = &qi->q;
+ int prio;
+
+ prio = sdu->priority;
+
+ if (!wlc_prec_enq(wlc, q, sdu, prec)) {
+ if (!EDCF_ENAB(wlc->pub)
+ || (wlc->pub->wlfeatureflag & WL_SWFL_FLOWCONTROL))
+ wiphy_err(wlc->wiphy, "wl%d: wlc_txq_enq: txq overflow"
+ "\n", wlc->pub->unit);
+
+ /*
+ * XXX we might hit this condtion in case
+ * packet flooding from mac80211 stack
+ */
+ brcmu_pkt_buf_free_skb(sdu);
+ }
+
+ /* Check if flow control needs to be turned on after enqueuing the packet
+ * Don't turn on flow control if EDCF is enabled. Driver would make the decision on what
+ * to drop instead of relying on stack to make the right decision
+ */
+ if (!EDCF_ENAB(wlc->pub)
+ || (wlc->pub->wlfeatureflag & WL_SWFL_FLOWCONTROL)) {
+ if (pktq_len(q) >= wlc->pub->tunables->datahiwat) {
+ wlc_txflowcontrol(wlc, qi, ON, ALLPRIO);
+ }
+ } else if (wlc->pub->_priofc) {
+ if (pktq_plen(q, wlc_prio2prec_map[prio]) >=
+ wlc->pub->tunables->datahiwat) {
+ wlc_txflowcontrol(wlc, qi, ON, prio);
+ }
+ }
+}
+
+bool
+wlc_sendpkt_mac80211(struct wlc_info *wlc, struct sk_buff *sdu,
+ struct ieee80211_hw *hw)
+{
+ u8 prio;
+ uint fifo;
+ void *pkt;
+ struct scb *scb = &global_scb;
+ struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data);
+
+ /* 802.11 standard requires management traffic to go at highest priority */
+ prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority :
+ MAXPRIO;
+ fifo = prio2fifo[prio];
+ pkt = sdu;
+ if (unlikely
+ (wlc_d11hdrs_mac80211(wlc, hw, pkt, scb, 0, 1, fifo, 0, NULL, 0)))
+ return -EINVAL;
+ wlc_txq_enq(wlc, scb, pkt, WLC_PRIO_TO_PREC(prio));
+ wlc_send_q(wlc);
+ return 0;
+}
+
+void wlc_send_q(struct wlc_info *wlc)
+{
+ struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
+ int prec;
+ u16 prec_map;
+ int err = 0, i, count;
+ uint fifo;
+ struct wlc_txq_info *qi = wlc->pkt_queue;
+ struct pktq *q = &qi->q;
+ struct ieee80211_tx_info *tx_info;
+
+ if (in_send_q)
+ return;
+ else
+ in_send_q = true;
+
+ prec_map = wlc->tx_prec_map;
+
+ /* Send all the enq'd pkts that we can.
+ * Dequeue packets with precedence with empty HW fifo only
+ */
+ while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) {
+ tx_info = IEEE80211_SKB_CB(pkt[0]);
+ if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+ err = wlc_sendampdu(wlc->ampdu, qi, pkt, prec);
+ } else {
+ count = 1;
+ err = wlc_prep_pdu(wlc, pkt[0], &fifo);
+ if (!err) {
+ for (i = 0; i < count; i++) {
+ wlc_txfifo(wlc, fifo, pkt[i], true, 1);
+ }
+ }
+ }
+
+ if (err == -EBUSY) {
+ brcmu_pktq_penq_head(q, prec, pkt[0]);
+ /* If send failed due to any other reason than a change in
+ * HW FIFO condition, quit. Otherwise, read the new prec_map!
+ */
+ if (prec_map == wlc->tx_prec_map)
+ break;
+ prec_map = wlc->tx_prec_map;
+ }
+ }
+
+ /* Check if flow control needs to be turned off after sending the packet */
+ if (!EDCF_ENAB(wlc->pub)
+ || (wlc->pub->wlfeatureflag & WL_SWFL_FLOWCONTROL)) {
+ if (wlc_txflowcontrol_prio_isset(wlc, qi, ALLPRIO)
+ && (pktq_len(q) < wlc->pub->tunables->datahiwat / 2)) {
+ wlc_txflowcontrol(wlc, qi, OFF, ALLPRIO);
+ }
+ } else if (wlc->pub->_priofc) {
+ int prio;
+ for (prio = MAXPRIO; prio >= 0; prio--) {
+ if (wlc_txflowcontrol_prio_isset(wlc, qi, prio) &&
+ (pktq_plen(q, wlc_prio2prec_map[prio]) <
+ wlc->pub->tunables->datahiwat / 2)) {
+ wlc_txflowcontrol(wlc, qi, OFF, prio);
+ }
+ }
+ }
+ in_send_q = false;
+}
+
+/*
+ * bcmc_fid_generate:
+ * Generate frame ID for a BCMC packet. The frag field is not used
+ * for MC frames so is used as part of the sequence number.
+ */
+static inline u16
+bcmc_fid_generate(struct wlc_info *wlc, struct wlc_bsscfg *bsscfg,
+ d11txh_t *txh)
+{
+ u16 frameid;
+
+ frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
+ TXFID_QUEUE_MASK);
+ frameid |=
+ (((wlc->
+ mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
+ TX_BCMC_FIFO;
+
+ return frameid;
+}
+
+void
+wlc_txfifo(struct wlc_info *wlc, uint fifo, struct sk_buff *p, bool commit,
+ s8 txpktpend)
+{
+ u16 frameid = INVALIDFID;
+ d11txh_t *txh;
+
+ txh = (d11txh_t *) (p->data);
+
+ /* When a BC/MC frame is being committed to the BCMC fifo via DMA (NOT PIO), update
+ * ucode or BSS info as appropriate.
+ */
+ if (fifo == TX_BCMC_FIFO) {
+ frameid = le16_to_cpu(txh->TxFrameID);
+
+ }
+
+ if (WLC_WAR16165(wlc))
+ wlc_war16165(wlc, true);
+
+
+ /* Bump up pending count for if not using rpc. If rpc is used, this will be handled
+ * in wlc_bmac_txfifo()
+ */
+ if (commit) {
+ TXPKTPENDINC(wlc, fifo, txpktpend);
+ BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n",
+ txpktpend, TXPKTPENDGET(wlc, fifo));
+ }
+
+ /* Commit BCMC sequence number in the SHM frame ID location */
+ if (frameid != INVALIDFID)
+ BCMCFID(wlc, frameid);
+
+ if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0) {
+ wiphy_err(wlc->wiphy, "wlc_txfifo: fatal, toss frames !!!\n");
+ }
+}
+
+void
+wlc_compute_plcp(struct wlc_info *wlc, ratespec_t rspec, uint length, u8 *plcp)
+{
+ if (IS_MCS(rspec)) {
+ wlc_compute_mimo_plcp(rspec, length, plcp);
+ } else if (IS_OFDM(rspec)) {
+ wlc_compute_ofdm_plcp(rspec, length, plcp);
+ } else {
+ wlc_compute_cck_plcp(wlc, rspec, length, plcp);
+ }
+ return;
+}
+
+/* Rate: 802.11 rate code, length: PSDU length in octets */
+static void wlc_compute_mimo_plcp(ratespec_t rspec, uint length, u8 *plcp)
+{
+ u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
+ plcp[0] = mcs;
+ if (RSPEC_IS40MHZ(rspec) || (mcs == 32))
+ plcp[0] |= MIMO_PLCP_40MHZ;
+ WLC_SET_MIMO_PLCP_LEN(plcp, length);
+ plcp[3] = RSPEC_MIMOPLCP3(rspec); /* rspec already holds this byte */
+ plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
+ plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
+ plcp[5] = 0;
+}
+
+/* Rate: 802.11 rate code, length: PSDU length in octets */
+static void
+wlc_compute_ofdm_plcp(ratespec_t rspec, u32 length, u8 *plcp)
+{
+ u8 rate_signal;
+ u32 tmp = 0;
+ int rate = RSPEC2RATE(rspec);
+
+ /* encode rate per 802.11a-1999 sec 17.3.4.1, with lsb transmitted first */
+ rate_signal = rate_info[rate] & WLC_RATE_MASK;
+ memset(plcp, 0, D11_PHY_HDR_LEN);
+ D11A_PHY_HDR_SRATE((ofdm_phy_hdr_t *) plcp, rate_signal);
+
+ tmp = (length & 0xfff) << 5;
+ plcp[2] |= (tmp >> 16) & 0xff;
+ plcp[1] |= (tmp >> 8) & 0xff;
+ plcp[0] |= tmp & 0xff;
+
+ return;
+}
+
+/*
+ * Compute PLCP, but only requires actual rate and length of pkt.
+ * Rate is given in the driver standard multiple of 500 kbps.
+ * le is set for 11 Mbps rate if necessary.
+ * Broken out for PRQ.
+ */
+
+static void wlc_cck_plcp_set(struct wlc_info *wlc, int rate_500, uint length,
+ u8 *plcp)
+{
+ u16 usec = 0;
+ u8 le = 0;
+
+ switch (rate_500) {
+ case WLC_RATE_1M:
+ usec = length << 3;
+ break;
+ case WLC_RATE_2M:
+ usec = length << 2;
+ break;
+ case WLC_RATE_5M5:
+ usec = (length << 4) / 11;
+ if ((length << 4) - (usec * 11) > 0)
+ usec++;
+ break;
+ case WLC_RATE_11M:
+ usec = (length << 3) / 11;
+ if ((length << 3) - (usec * 11) > 0) {
+ usec++;
+ if ((usec * 11) - (length << 3) >= 8)
+ le = D11B_PLCP_SIGNAL_LE;
+ }
+ break;
+
+ default:
+ wiphy_err(wlc->wiphy, "wlc_cck_plcp_set: unsupported rate %d"
+ "\n", rate_500);
+ rate_500 = WLC_RATE_1M;
+ usec = length << 3;
+ break;
+ }
+ /* PLCP signal byte */
+ plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
+ /* PLCP service byte */
+ plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
+ /* PLCP length u16, little endian */
+ plcp[2] = usec & 0xff;
+ plcp[3] = (usec >> 8) & 0xff;
+ /* PLCP CRC16 */
+ plcp[4] = 0;
+ plcp[5] = 0;
+}
+
+/* Rate: 802.11 rate code, length: PSDU length in octets */
+static void wlc_compute_cck_plcp(struct wlc_info *wlc, ratespec_t rspec,
+ uint length, u8 *plcp)
+{
+ int rate = RSPEC2RATE(rspec);
+
+ wlc_cck_plcp_set(wlc, rate, length, plcp);
+}
+
+/* wlc_compute_frame_dur()
+ *
+ * Calculate the 802.11 MAC header DUR field for MPDU
+ * DUR for a single frame = 1 SIFS + 1 ACK
+ * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
+ *
+ * rate MPDU rate in unit of 500kbps
+ * next_frag_len next MPDU length in bytes
+ * preamble_type use short/GF or long/MM PLCP header
+ */
+static u16
+wlc_compute_frame_dur(struct wlc_info *wlc, ratespec_t rate, u8 preamble_type,
+ uint next_frag_len)
+{
+ u16 dur, sifs;
+
+ sifs = SIFS(wlc->band);
+
+ dur = sifs;
+ dur += (u16) wlc_calc_ack_time(wlc, rate, preamble_type);
+
+ if (next_frag_len) {
+ /* Double the current DUR to get 2 SIFS + 2 ACKs */
+ dur *= 2;
+ /* add another SIFS and the frag time */
+ dur += sifs;
+ dur +=
+ (u16) wlc_calc_frame_time(wlc, rate, preamble_type,
+ next_frag_len);
+ }
+ return dur;
+}
+
+/* wlc_compute_rtscts_dur()
+ *
+ * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
+ * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
+ * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
+ *
+ * cts cts-to-self or rts/cts
+ * rts_rate rts or cts rate in unit of 500kbps
+ * rate next MPDU rate in unit of 500kbps
+ * frame_len next MPDU frame length in bytes
+ */
+u16
+wlc_compute_rtscts_dur(struct wlc_info *wlc, bool cts_only, ratespec_t rts_rate,
+ ratespec_t frame_rate, u8 rts_preamble_type,
+ u8 frame_preamble_type, uint frame_len, bool ba)
+{
+ u16 dur, sifs;
+
+ sifs = SIFS(wlc->band);
+
+ if (!cts_only) { /* RTS/CTS */
+ dur = 3 * sifs;
+ dur +=
+ (u16) wlc_calc_cts_time(wlc, rts_rate,
+ rts_preamble_type);
+ } else { /* CTS-TO-SELF */
+ dur = 2 * sifs;
+ }
+
+ dur +=
+ (u16) wlc_calc_frame_time(wlc, frame_rate, frame_preamble_type,
+ frame_len);
+ if (ba)
+ dur +=
+ (u16) wlc_calc_ba_time(wlc, frame_rate,
+ WLC_SHORT_PREAMBLE);
+ else
+ dur +=
+ (u16) wlc_calc_ack_time(wlc, frame_rate,
+ frame_preamble_type);
+ return dur;
+}
+
+u16 wlc_phytxctl1_calc(struct wlc_info *wlc, ratespec_t rspec)
+{
+ u16 phyctl1 = 0;
+ u16 bw;
+
+ if (WLCISLCNPHY(wlc->band)) {
+ bw = PHY_TXC1_BW_20MHZ;
+ } else {
+ bw = RSPEC_GET_BW(rspec);
+ /* 10Mhz is not supported yet */
+ if (bw < PHY_TXC1_BW_20MHZ) {
+ wiphy_err(wlc->wiphy, "wlc_phytxctl1_calc: bw %d is "
+ "not supported yet, set to 20L\n", bw);
+ bw = PHY_TXC1_BW_20MHZ;
+ }
+ }
+
+ if (IS_MCS(rspec)) {
+ uint mcs = rspec & RSPEC_RATE_MASK;
+
+ /* bw, stf, coding-type is part of RSPEC_PHYTXBYTE2 returns */
+ phyctl1 = RSPEC_PHYTXBYTE2(rspec);
+ /* set the upper byte of phyctl1 */
+ phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
+ } else if (IS_CCK(rspec) && !WLCISLCNPHY(wlc->band)
+ && !WLCISSSLPNPHY(wlc->band)) {
+ /* In CCK mode LPPHY overloads OFDM Modulation bits with CCK Data Rate */
+ /* Eventually MIMOPHY would also be converted to this format */
+ /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
+ phyctl1 = (bw | (RSPEC_STF(rspec) << PHY_TXC1_MODE_SHIFT));
+ } else { /* legacy OFDM/CCK */
+ s16 phycfg;
+ /* get the phyctl byte from rate phycfg table */
+ phycfg = wlc_rate_legacy_phyctl(RSPEC2RATE(rspec));
+ if (phycfg == -1) {
+ wiphy_err(wlc->wiphy, "wlc_phytxctl1_calc: wrong "
+ "legacy OFDM/CCK rate\n");
+ phycfg = 0;
+ }
+ /* set the upper byte of phyctl1 */
+ phyctl1 =
+ (bw | (phycfg << 8) |
+ (RSPEC_STF(rspec) << PHY_TXC1_MODE_SHIFT));
+ }
+ return phyctl1;
+}
+
+ratespec_t
+wlc_rspec_to_rts_rspec(struct wlc_info *wlc, ratespec_t rspec, bool use_rspec,
+ u16 mimo_ctlchbw)
+{
+ ratespec_t rts_rspec = 0;
+
+ if (use_rspec) {
+ /* use frame rate as rts rate */
+ rts_rspec = rspec;
+
+ } else if (wlc->band->gmode && wlc->protection->_g && !IS_CCK(rspec)) {
+ /* Use 11Mbps as the g protection RTS target rate and fallback.
+ * Use the WLC_BASIC_RATE() lookup to find the best basic rate under the
+ * target in case 11 Mbps is not Basic.
+ * 6 and 9 Mbps are not usually selected by rate selection, but even
+ * if the OFDM rate we are protecting is 6 or 9 Mbps, 11 is more robust.
+ */
+ rts_rspec = WLC_BASIC_RATE(wlc, WLC_RATE_11M);
+ } else {
+ /* calculate RTS rate and fallback rate based on the frame rate
+ * RTS must be sent at a basic rate since it is a
+ * control frame, sec 9.6 of 802.11 spec
+ */
+ rts_rspec = WLC_BASIC_RATE(wlc, rspec);
+ }
+
+ if (WLC_PHY_11N_CAP(wlc->band)) {
+ /* set rts txbw to correct side band */
+ rts_rspec &= ~RSPEC_BW_MASK;
+
+ /* if rspec/rspec_fallback is 40MHz, then send RTS on both 20MHz channel
+ * (DUP), otherwise send RTS on control channel
+ */
+ if (RSPEC_IS40MHZ(rspec) && !IS_CCK(rts_rspec))
+ rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
+ else
+ rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
+
+ /* pick siso/cdd as default for ofdm */
+ if (IS_OFDM(rts_rspec)) {
+ rts_rspec &= ~RSPEC_STF_MASK;
+ rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
+ }
+ }
+ return rts_rspec;
+}
+
+/*
+ * Add d11txh_t, cck_phy_hdr_t.
+ *
+ * 'p' data must start with 802.11 MAC header
+ * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
+ *
+ * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
+ *
+ */
+static u16
+wlc_d11hdrs_mac80211(struct wlc_info *wlc, struct ieee80211_hw *hw,
+ struct sk_buff *p, struct scb *scb, uint frag,
+ uint nfrags, uint queue, uint next_frag_len,
+ wsec_key_t *key, ratespec_t rspec_override)
+{
+ struct ieee80211_hdr *h;
+ d11txh_t *txh;
+ u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
+ int len, phylen, rts_phylen;
+ u16 mch, phyctl, xfts, mainrates;
+ u16 seq = 0, mcl = 0, status = 0, frameid = 0;
+ ratespec_t rspec[2] = { WLC_RATE_1M, WLC_RATE_1M }, rts_rspec[2] = {
+ WLC_RATE_1M, WLC_RATE_1M};
+ bool use_rts = false;
+ bool use_cts = false;
+ bool use_rifs = false;
+ bool short_preamble[2] = { false, false };
+ u8 preamble_type[2] = { WLC_LONG_PREAMBLE, WLC_LONG_PREAMBLE };
+ u8 rts_preamble_type[2] = { WLC_LONG_PREAMBLE, WLC_LONG_PREAMBLE };
+ u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
+ struct ieee80211_rts *rts = NULL;
+ bool qos;
+ uint ac;
+ u32 rate_val[2];
+ bool hwtkmic = false;
+ u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
+#define ANTCFG_NONE 0xFF
+ u8 antcfg = ANTCFG_NONE;
+ u8 fbantcfg = ANTCFG_NONE;
+ uint phyctl1_stf = 0;
+ u16 durid = 0;
+ struct ieee80211_tx_rate *txrate[2];
+ int k;
+ struct ieee80211_tx_info *tx_info;
+ bool is_mcs[2];
+ u16 mimo_txbw;
+ u8 mimo_preamble_type;
+
+ /* locate 802.11 MAC header */
+ h = (struct ieee80211_hdr *)(p->data);
+ qos = ieee80211_is_data_qos(h->frame_control);
+
+ /* compute length of frame in bytes for use in PLCP computations */
+ len = brcmu_pkttotlen(p);
+ phylen = len + FCS_LEN;
+
+ /* If WEP enabled, add room in phylen for the additional bytes of
+ * ICV which MAC generates. We do NOT add the additional bytes to
+ * the packet itself, thus phylen = packet length + ICV_LEN + FCS_LEN
+ * in this case
+ */
+ if (key) {
+ phylen += key->icv_len;
+ }
+
+ /* Get tx_info */
+ tx_info = IEEE80211_SKB_CB(p);
+
+ /* add PLCP */
+ plcp = skb_push(p, D11_PHY_HDR_LEN);
+
+ /* add Broadcom tx descriptor header */
+ txh = (d11txh_t *) skb_push(p, D11_TXH_LEN);
+ memset(txh, 0, D11_TXH_LEN);
+
+ /* setup frameid */
+ if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
+ /* non-AP STA should never use BCMC queue */
+ if (queue == TX_BCMC_FIFO) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
+ "TX_BCMC!\n", WLCWLUNIT(wlc), __func__);
+ frameid = bcmc_fid_generate(wlc, NULL, txh);
+ } else {
+ /* Increment the counter for first fragment */
+ if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
+ SCB_SEQNUM(scb, p->priority)++;
+ }
+
+ /* extract fragment number from frame first */
+ seq = le16_to_cpu(seq) & FRAGNUM_MASK;
+ seq |= (SCB_SEQNUM(scb, p->priority) << SEQNUM_SHIFT);
+ h->seq_ctrl = cpu_to_le16(seq);
+
+ frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
+ (queue & TXFID_QUEUE_MASK);
+ }
+ }
+ frameid |= queue & TXFID_QUEUE_MASK;
+
+ /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
+ if (SCB_PS(scb) || ieee80211_is_beacon(h->frame_control))
+ mcl |= TXC_IGNOREPMQ;
+
+ txrate[0] = tx_info->control.rates;
+ txrate[1] = txrate[0] + 1;
+
+ /* if rate control algorithm didn't give us a fallback rate, use the primary rate */
+ if (txrate[1]->idx < 0) {
+ txrate[1] = txrate[0];
+ }
+
+ for (k = 0; k < hw->max_rates; k++) {
+ is_mcs[k] =
+ txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
+ if (!is_mcs[k]) {
+ if ((txrate[k]->idx >= 0)
+ && (txrate[k]->idx <
+ hw->wiphy->bands[tx_info->band]->n_bitrates)) {
+ rate_val[k] =
+ hw->wiphy->bands[tx_info->band]->
+ bitrates[txrate[k]->idx].hw_value;
+ short_preamble[k] =
+ txrate[k]->
+ flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
+ true : false;
+ } else {
+ rate_val[k] = WLC_RATE_1M;
+ }
+ } else {
+ rate_val[k] = txrate[k]->idx;
+ }
+ /* Currently only support same setting for primay and fallback rates.
+ * Unify flags for each rate into a single value for the frame
+ */
+ use_rts |=
+ txrate[k]->
+ flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
+ use_cts |=
+ txrate[k]->
+ flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
+
+ if (is_mcs[k])
+ rate_val[k] |= NRATE_MCS_INUSE;
+
+ rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band, rate_val[k]);
+
+ /* (1) RATE: determine and validate primary rate and fallback rates */
+ if (!RSPEC_ACTIVE(rspec[k])) {
+ rspec[k] = WLC_RATE_1M;
+ } else {
+ if (!is_multicast_ether_addr(h->addr1)) {
+ /* set tx antenna config */
+ wlc_antsel_antcfg_get(wlc->asi, false, false, 0,
+ 0, &antcfg, &fbantcfg);
+ }
+ }
+ }
+
+ phyctl1_stf = wlc->stf->ss_opmode;
+
+ if (N_ENAB(wlc->pub)) {
+ for (k = 0; k < hw->max_rates; k++) {
+ /* apply siso/cdd to single stream mcs's or ofdm if rspec is auto selected */
+ if (((IS_MCS(rspec[k]) &&
+ IS_SINGLE_STREAM(rspec[k] & RSPEC_RATE_MASK)) ||
+ IS_OFDM(rspec[k]))
+ && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
+ || !(rspec[k] & RSPEC_OVERRIDE))) {
+ rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
+
+ /* For SISO MCS use STBC if possible */
+ if (IS_MCS(rspec[k])
+ && WLC_STF_SS_STBC_TX(wlc, scb)) {
+ u8 stc;
+
+ stc = 1; /* Nss for single stream is always 1 */
+ rspec[k] |=
+ (PHY_TXC1_MODE_STBC <<
+ RSPEC_STF_SHIFT) | (stc <<
+ RSPEC_STC_SHIFT);
+ } else
+ rspec[k] |=
+ (phyctl1_stf << RSPEC_STF_SHIFT);
+ }
+
+ /* Is the phy configured to use 40MHZ frames? If so then pick the desired txbw */
+ if (CHSPEC_WLC_BW(wlc->chanspec) == WLC_40_MHZ) {
+ /* default txbw is 20in40 SB */
+ mimo_ctlchbw = mimo_txbw =
+ CHSPEC_SB_UPPER(WLC_BAND_PI_RADIO_CHANSPEC)
+ ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
+
+ if (IS_MCS(rspec[k])) {
+ /* mcs 32 must be 40b/w DUP */
+ if ((rspec[k] & RSPEC_RATE_MASK) == 32) {
+ mimo_txbw =
+ PHY_TXC1_BW_40MHZ_DUP;
+ /* use override */
+ } else if (wlc->mimo_40txbw != AUTO)
+ mimo_txbw = wlc->mimo_40txbw;
+ /* else check if dst is using 40 Mhz */
+ else if (scb->flags & SCB_IS40)
+ mimo_txbw = PHY_TXC1_BW_40MHZ;
+ } else if (IS_OFDM(rspec[k])) {
+ if (wlc->ofdm_40txbw != AUTO)
+ mimo_txbw = wlc->ofdm_40txbw;
+ } else {
+ if (wlc->cck_40txbw != AUTO)
+ mimo_txbw = wlc->cck_40txbw;
+ }
+ } else {
+ /* mcs32 is 40 b/w only.
+ * This is possible for probe packets on a STA during SCAN
+ */
+ if ((rspec[k] & RSPEC_RATE_MASK) == 32) {
+ /* mcs 0 */
+ rspec[k] = RSPEC_MIMORATE;
+ }
+ mimo_txbw = PHY_TXC1_BW_20MHZ;
+ }
+
+ /* Set channel width */
+ rspec[k] &= ~RSPEC_BW_MASK;
+ if ((k == 0) || ((k > 0) && IS_MCS(rspec[k])))
+ rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
+ else
+ rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
+
+ /* Set Short GI */
+#ifdef NOSGIYET
+ if (IS_MCS(rspec[k])
+ && (txrate[k]->flags & IEEE80211_TX_RC_SHORT_GI))
+ rspec[k] |= RSPEC_SHORT_GI;
+ else if (!(txrate[k]->flags & IEEE80211_TX_RC_SHORT_GI))
+ rspec[k] &= ~RSPEC_SHORT_GI;
+#else
+ rspec[k] &= ~RSPEC_SHORT_GI;
+#endif
+
+ mimo_preamble_type = WLC_MM_PREAMBLE;
+ if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
+ mimo_preamble_type = WLC_GF_PREAMBLE;
+
+ if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
+ && (!IS_MCS(rspec[k]))) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
+ "RC_MCS != IS_MCS(rspec)\n",
+ WLCWLUNIT(wlc), __func__);
+ }
+
+ if (IS_MCS(rspec[k])) {
+ preamble_type[k] = mimo_preamble_type;
+
+ /* if SGI is selected, then forced mm for single stream */
+ if ((rspec[k] & RSPEC_SHORT_GI)
+ && IS_SINGLE_STREAM(rspec[k] &
+ RSPEC_RATE_MASK)) {
+ preamble_type[k] = WLC_MM_PREAMBLE;
+ }
+ }
+
+ /* should be better conditionalized */
+ if (!IS_MCS(rspec[0])
+ && (tx_info->control.rates[0].
+ flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
+ preamble_type[k] = WLC_SHORT_PREAMBLE;
+ }
+ } else {
+ for (k = 0; k < hw->max_rates; k++) {
+ /* Set ctrlchbw as 20Mhz */
+ rspec[k] &= ~RSPEC_BW_MASK;
+ rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
+
+ /* for nphy, stf of ofdm frames must follow policies */
+ if (WLCISNPHY(wlc->band) && IS_OFDM(rspec[k])) {
+ rspec[k] &= ~RSPEC_STF_MASK;
+ rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
+ }
+ }
+ }
+
+ /* Reset these for use with AMPDU's */
+ txrate[0]->count = 0;
+ txrate[1]->count = 0;
+
+ /* (2) PROTECTION, may change rspec */
+ if ((ieee80211_is_data(h->frame_control) ||
+ ieee80211_is_mgmt(h->frame_control)) &&
+ (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
+ use_rts = true;
+
+ /* (3) PLCP: determine PLCP header and MAC duration, fill d11txh_t */
+ wlc_compute_plcp(wlc, rspec[0], phylen, plcp);
+ wlc_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
+ memcpy(&txh->FragPLCPFallback,
+ plcp_fallback, sizeof(txh->FragPLCPFallback));
+
+ /* Length field now put in CCK FBR CRC field */
+ if (IS_CCK(rspec[1])) {
+ txh->FragPLCPFallback[4] = phylen & 0xff;
+ txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
+ }
+
+ /* MIMO-RATE: need validation ?? */
+ mainrates =
+ IS_OFDM(rspec[0]) ? D11A_PHY_HDR_GRATE((ofdm_phy_hdr_t *) plcp) :
+ plcp[0];
+
+ /* DUR field for main rate */
+ if (!ieee80211_is_pspoll(h->frame_control) &&
+ !is_multicast_ether_addr(h->addr1) && !use_rifs) {
+ durid =
+ wlc_compute_frame_dur(wlc, rspec[0], preamble_type[0],
+ next_frag_len);
+ h->duration_id = cpu_to_le16(durid);
+ } else if (use_rifs) {
+ /* NAV protect to end of next max packet size */
+ durid =
+ (u16) wlc_calc_frame_time(wlc, rspec[0],
+ preamble_type[0],
+ DOT11_MAX_FRAG_LEN);
+ durid += RIFS_11N_TIME;
+ h->duration_id = cpu_to_le16(durid);
+ }
+
+ /* DUR field for fallback rate */
+ if (ieee80211_is_pspoll(h->frame_control))
+ txh->FragDurFallback = h->duration_id;
+ else if (is_multicast_ether_addr(h->addr1) || use_rifs)
+ txh->FragDurFallback = 0;
+ else {
+ durid = wlc_compute_frame_dur(wlc, rspec[1],
+ preamble_type[1], next_frag_len);
+ txh->FragDurFallback = cpu_to_le16(durid);
+ }
+
+ /* (4) MAC-HDR: MacTxControlLow */
+ if (frag == 0)
+ mcl |= TXC_STARTMSDU;
+
+ if (!is_multicast_ether_addr(h->addr1))
+ mcl |= TXC_IMMEDACK;
+
+ if (BAND_5G(wlc->band->bandtype))
+ mcl |= TXC_FREQBAND_5G;
+
+ if (CHSPEC_IS40(WLC_BAND_PI_RADIO_CHANSPEC))
+ mcl |= TXC_BW_40;
+
+ /* set AMIC bit if using hardware TKIP MIC */
+ if (hwtkmic)
+ mcl |= TXC_AMIC;
+
+ txh->MacTxControlLow = cpu_to_le16(mcl);
+
+ /* MacTxControlHigh */
+ mch = 0;
+
+ /* Set fallback rate preamble type */
+ if ((preamble_type[1] == WLC_SHORT_PREAMBLE) ||
+ (preamble_type[1] == WLC_GF_PREAMBLE)) {
+ if (RSPEC2RATE(rspec[1]) != WLC_RATE_1M)
+ mch |= TXC_PREAMBLE_DATA_FB_SHORT;
+ }
+
+ /* MacFrameControl */
+ memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
+ txh->TxFesTimeNormal = cpu_to_le16(0);
+
+ txh->TxFesTimeFallback = cpu_to_le16(0);
+
+ /* TxFrameRA */
+ memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
+
+ /* TxFrameID */
+ txh->TxFrameID = cpu_to_le16(frameid);
+
+ /* TxStatus, Note the case of recreating the first frag of a suppressed frame
+ * then we may need to reset the retry cnt's via the status reg
+ */
+ txh->TxStatus = cpu_to_le16(status);
+
+ /* extra fields for ucode AMPDU aggregation, the new fields are added to
+ * the END of previous structure so that it's compatible in driver.
+ */
+ txh->MaxNMpdus = cpu_to_le16(0);
+ txh->MaxABytes_MRT = cpu_to_le16(0);
+ txh->MaxABytes_FBR = cpu_to_le16(0);
+ txh->MinMBytes = cpu_to_le16(0);
+
+ /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration, furnish d11txh_t */
+ /* RTS PLCP header and RTS frame */
+ if (use_rts || use_cts) {
+ if (use_rts && use_cts)
+ use_cts = false;
+
+ for (k = 0; k < 2; k++) {
+ rts_rspec[k] = wlc_rspec_to_rts_rspec(wlc, rspec[k],
+ false,
+ mimo_ctlchbw);
+ }
+
+ if (!IS_OFDM(rts_rspec[0]) &&
+ !((RSPEC2RATE(rts_rspec[0]) == WLC_RATE_1M) ||
+ (wlc->PLCPHdr_override == WLC_PLCP_LONG))) {
+ rts_preamble_type[0] = WLC_SHORT_PREAMBLE;
+ mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
+ }
+
+ if (!IS_OFDM(rts_rspec[1]) &&
+ !((RSPEC2RATE(rts_rspec[1]) == WLC_RATE_1M) ||
+ (wlc->PLCPHdr_override == WLC_PLCP_LONG))) {
+ rts_preamble_type[1] = WLC_SHORT_PREAMBLE;
+ mch |= TXC_PREAMBLE_RTS_FB_SHORT;
+ }
+
+ /* RTS/CTS additions to MacTxControlLow */
+ if (use_cts) {
+ txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
+ } else {
+ txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
+ txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
+ }
+
+ /* RTS PLCP header */
+ rts_plcp = txh->RTSPhyHeader;
+ if (use_cts)
+ rts_phylen = DOT11_CTS_LEN + FCS_LEN;
+ else
+ rts_phylen = DOT11_RTS_LEN + FCS_LEN;
+
+ wlc_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
+
+ /* fallback rate version of RTS PLCP header */
+ wlc_compute_plcp(wlc, rts_rspec[1], rts_phylen,
+ rts_plcp_fallback);
+ memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
+ sizeof(txh->RTSPLCPFallback));
+
+ /* RTS frame fields... */
+ rts = (struct ieee80211_rts *)&txh->rts_frame;
+
+ durid = wlc_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
+ rspec[0], rts_preamble_type[0],
+ preamble_type[0], phylen, false);
+ rts->duration = cpu_to_le16(durid);
+ /* fallback rate version of RTS DUR field */
+ durid = wlc_compute_rtscts_dur(wlc, use_cts,
+ rts_rspec[1], rspec[1],
+ rts_preamble_type[1],
+ preamble_type[1], phylen, false);
+ txh->RTSDurFallback = cpu_to_le16(durid);
+
+ if (use_cts) {
+ rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
+ IEEE80211_STYPE_CTS);
+
+ memcpy(&rts->ra, &h->addr2, ETH_ALEN);
+ } else {
+ rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
+ IEEE80211_STYPE_RTS);
+
+ memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
+ }
+
+ /* mainrate
+ * low 8 bits: main frag rate/mcs,
+ * high 8 bits: rts/cts rate/mcs
+ */
+ mainrates |= (IS_OFDM(rts_rspec[0]) ?
+ D11A_PHY_HDR_GRATE((ofdm_phy_hdr_t *) rts_plcp) :
+ rts_plcp[0]) << 8;
+ } else {
+ memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
+ memset((char *)&txh->rts_frame, 0,
+ sizeof(struct ieee80211_rts));
+ memset((char *)txh->RTSPLCPFallback, 0,
+ sizeof(txh->RTSPLCPFallback));
+ txh->RTSDurFallback = 0;
+ }
+
+#ifdef SUPPORT_40MHZ
+ /* add null delimiter count */
+ if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && IS_MCS(rspec)) {
+ txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
+ wlc_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
+ }
+#endif
+
+ /* Now that RTS/RTS FB preamble types are updated, write the final value */
+ txh->MacTxControlHigh = cpu_to_le16(mch);
+
+ /* MainRates (both the rts and frag plcp rates have been calculated now) */
+ txh->MainRates = cpu_to_le16(mainrates);
+
+ /* XtraFrameTypes */
+ xfts = FRAMETYPE(rspec[1], wlc->mimoft);
+ xfts |= (FRAMETYPE(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
+ xfts |= (FRAMETYPE(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
+ xfts |=
+ CHSPEC_CHANNEL(WLC_BAND_PI_RADIO_CHANSPEC) << XFTS_CHANNEL_SHIFT;
+ txh->XtraFrameTypes = cpu_to_le16(xfts);
+
+ /* PhyTxControlWord */
+ phyctl = FRAMETYPE(rspec[0], wlc->mimoft);
+ if ((preamble_type[0] == WLC_SHORT_PREAMBLE) ||
+ (preamble_type[0] == WLC_GF_PREAMBLE)) {
+ if (RSPEC2RATE(rspec[0]) != WLC_RATE_1M)
+ phyctl |= PHY_TXC_SHORT_HDR;
+ }
+
+ /* phytxant is properly bit shifted */
+ phyctl |= wlc_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
+ txh->PhyTxControlWord = cpu_to_le16(phyctl);
+
+ /* PhyTxControlWord_1 */
+ if (WLC_PHY_11N_CAP(wlc->band)) {
+ u16 phyctl1 = 0;
+
+ phyctl1 = wlc_phytxctl1_calc(wlc, rspec[0]);
+ txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
+ phyctl1 = wlc_phytxctl1_calc(wlc, rspec[1]);
+ txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
+
+ if (use_rts || use_cts) {
+ phyctl1 = wlc_phytxctl1_calc(wlc, rts_rspec[0]);
+ txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
+ phyctl1 = wlc_phytxctl1_calc(wlc, rts_rspec[1]);
+ txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
+ }
+
+ /*
+ * For mcs frames, if mixedmode(overloaded with long preamble) is going to be set,
+ * fill in non-zero MModeLen and/or MModeFbrLen
+ * it will be unnecessary if they are separated
+ */
+ if (IS_MCS(rspec[0]) && (preamble_type[0] == WLC_MM_PREAMBLE)) {
+ u16 mmodelen =
+ wlc_calc_lsig_len(wlc, rspec[0], phylen);
+ txh->MModeLen = cpu_to_le16(mmodelen);
+ }
+
+ if (IS_MCS(rspec[1]) && (preamble_type[1] == WLC_MM_PREAMBLE)) {
+ u16 mmodefbrlen =
+ wlc_calc_lsig_len(wlc, rspec[1], phylen);
+ txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
+ }
+ }
+
+ ac = skb_get_queue_mapping(p);
+ if (SCB_WME(scb) && qos && wlc->edcf_txop[ac]) {
+ uint frag_dur, dur, dur_fallback;
+
+ /* WME: Update TXOP threshold */
+ if ((!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) && (frag == 0)) {
+ frag_dur =
+ wlc_calc_frame_time(wlc, rspec[0], preamble_type[0],
+ phylen);
+
+ if (rts) {
+ /* 1 RTS or CTS-to-self frame */
+ dur =
+ wlc_calc_cts_time(wlc, rts_rspec[0],
+ rts_preamble_type[0]);
+ dur_fallback =
+ wlc_calc_cts_time(wlc, rts_rspec[1],
+ rts_preamble_type[1]);
+ /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
+ dur += le16_to_cpu(rts->duration);
+ dur_fallback +=
+ le16_to_cpu(txh->RTSDurFallback);
+ } else if (use_rifs) {
+ dur = frag_dur;
+ dur_fallback = 0;
+ } else {
+ /* frame + SIFS + ACK */
+ dur = frag_dur;
+ dur +=
+ wlc_compute_frame_dur(wlc, rspec[0],
+ preamble_type[0], 0);
+
+ dur_fallback =
+ wlc_calc_frame_time(wlc, rspec[1],
+ preamble_type[1],
+ phylen);
+ dur_fallback +=
+ wlc_compute_frame_dur(wlc, rspec[1],
+ preamble_type[1], 0);
+ }
+ /* NEED to set TxFesTimeNormal (hard) */
+ txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
+ /* NEED to set fallback rate version of TxFesTimeNormal (hard) */
+ txh->TxFesTimeFallback =
+ cpu_to_le16((u16) dur_fallback);
+
+ /* update txop byte threshold (txop minus intraframe overhead) */
+ if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
+ {
+ uint newfragthresh;
+
+ newfragthresh =
+ wlc_calc_frame_len(wlc, rspec[0],
+ preamble_type[0],
+ (wlc->
+ edcf_txop[ac] -
+ (dur -
+ frag_dur)));
+ /* range bound the fragthreshold */
+ if (newfragthresh < DOT11_MIN_FRAG_LEN)
+ newfragthresh =
+ DOT11_MIN_FRAG_LEN;
+ else if (newfragthresh >
+ wlc->usr_fragthresh)
+ newfragthresh =
+ wlc->usr_fragthresh;
+ /* update the fragthresh and do txc update */
+ if (wlc->fragthresh[queue] !=
+ (u16) newfragthresh) {
+ wlc->fragthresh[queue] =
+ (u16) newfragthresh;
+ }
+ }
+ } else
+ wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
+ "for rate %d\n",
+ wlc->pub->unit, fifo_names[queue],
+ RSPEC2RATE(rspec[0]));
+
+ if (dur > wlc->edcf_txop[ac])
+ wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
+ "exceeded phylen %d/%d dur %d/%d\n",
+ wlc->pub->unit, __func__,
+ fifo_names[queue],
+ phylen, wlc->fragthresh[queue],
+ dur, wlc->edcf_txop[ac]);
+ }
+ }
+
+ return 0;
+}
+
+void wlc_tbtt(struct wlc_info *wlc, d11regs_t *regs)
+{
+ struct wlc_bsscfg *cfg = wlc->cfg;
+
+ if (!cfg->BSS) {
+ /* DirFrmQ is now valid...defer setting until end of ATIM window */
+ wlc->qvalid |= MCMD_DIRFRMQVAL;
+ }
+}
+
+static void wlc_war16165(struct wlc_info *wlc, bool tx)
+{
+ if (tx) {
+ /* the post-increment is used in STAY_AWAKE macro */
+ if (wlc->txpend16165war++ == 0)
+ wlc_set_ps_ctrl(wlc);
+ } else {
+ wlc->txpend16165war--;
+ if (wlc->txpend16165war == 0)
+ wlc_set_ps_ctrl(wlc);
+ }
+}
+
+/* process an individual tx_status_t */
+/* WLC_HIGH_API */
+bool
+wlc_dotxstatus(struct wlc_info *wlc, tx_status_t *txs, u32 frm_tx2)
+{
+ struct sk_buff *p;
+ uint queue;
+ d11txh_t *txh;
+ struct scb *scb = NULL;
+ bool free_pdu;
+ int tx_rts, tx_frame_count, tx_rts_count;
+ uint totlen, supr_status;
+ bool lastframe;
+ struct ieee80211_hdr *h;
+ u16 mcl;
+ struct ieee80211_tx_info *tx_info;
+ struct ieee80211_tx_rate *txrate;
+ int i;
+
+ (void)(frm_tx2); /* Compiler reference to avoid unused variable warning */
+
+ /* discard intermediate indications for ucode with one legitimate case:
+ * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
+ * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
+ * transmission count)
+ */
+ if (!(txs->status & TX_STATUS_AMPDU)
+ && (txs->status & TX_STATUS_INTERMEDIATE)) {
+ wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
+ __func__);
+ return false;
+ }
+
+ queue = txs->frameid & TXFID_QUEUE_MASK;
+ if (queue >= NFIFO) {
+ p = NULL;
+ goto fatal;
+ }
+
+ p = GETNEXTTXP(wlc, queue);
+ if (WLC_WAR16165(wlc))
+ wlc_war16165(wlc, false);
+ if (p == NULL)
+ goto fatal;
+
+ txh = (d11txh_t *) (p->data);
+ mcl = le16_to_cpu(txh->MacTxControlLow);
+
+ if (txs->phyerr) {
+ if (WL_ERROR_ON()) {
+ wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
+ txs->phyerr, txh->MainRates);
+ wlc_print_txdesc(txh);
+ }
+ wlc_print_txstatus(txs);
+ }
+
+ if (txs->frameid != cpu_to_le16(txh->TxFrameID))
+ goto fatal;
+ tx_info = IEEE80211_SKB_CB(p);
+ h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
+
+ if (tx_info->control.sta)
+ scb = (struct scb *)tx_info->control.sta->drv_priv;
+
+ if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
+ wlc_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
+ return false;
+ }
+
+ supr_status = txs->status & TX_STATUS_SUPR_MASK;
+ if (supr_status == TX_STATUS_SUPR_BADCH)
+ BCMMSG(wlc->wiphy,
+ "%s: Pkt tx suppressed, possibly channel %d\n",
+ __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
+
+ tx_rts = cpu_to_le16(txh->MacTxControlLow) & TXC_SENDRTS;
+ tx_frame_count =
+ (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
+ tx_rts_count =
+ (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
+
+ lastframe = !ieee80211_has_morefrags(h->frame_control);
+
+ if (!lastframe) {
+ wiphy_err(wlc->wiphy, "Not last frame!\n");
+ } else {
+ u16 sfbl, lfbl;
+ ieee80211_tx_info_clear_status(tx_info);
+ if (queue < AC_COUNT) {
+ sfbl = WLC_WME_RETRY_SFB_GET(wlc, wme_fifo2ac[queue]);
+ lfbl = WLC_WME_RETRY_LFB_GET(wlc, wme_fifo2ac[queue]);
+ } else {
+ sfbl = wlc->SFBL;
+ lfbl = wlc->LFBL;
+ }
+
+ txrate = tx_info->status.rates;
+ /* FIXME: this should use a combination of sfbl, lfbl depending on frame length and RTS setting */
+ if ((tx_frame_count > sfbl) && (txrate[1].idx >= 0)) {
+ /* rate selection requested a fallback rate and we used it */
+ txrate->count = lfbl;
+ txrate[1].count = tx_frame_count - lfbl;
+ } else {
+ /* rate selection did not request fallback rate, or we didn't need it */
+ txrate->count = tx_frame_count;
+ /* rc80211_minstrel.c:minstrel_tx_status() expects unused rates to be marked with idx = -1 */
+ txrate[1].idx = -1;
+ txrate[1].count = 0;
+ }
+
+ /* clear the rest of the rates */
+ for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
+ txrate[i].idx = -1;
+ txrate[i].count = 0;
+ }
+
+ if (txs->status & TX_STATUS_ACK_RCV)
+ tx_info->flags |= IEEE80211_TX_STAT_ACK;
+ }
+
+ totlen = brcmu_pkttotlen(p);
+ free_pdu = true;
+
+ wlc_txfifo_complete(wlc, queue, 1);
+
+ if (lastframe) {
+ p->next = NULL;
+ p->prev = NULL;
+ /* remove PLCP & Broadcom tx descriptor header */
+ skb_pull(p, D11_PHY_HDR_LEN);
+ skb_pull(p, D11_TXH_LEN);
+ ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
+ } else {
+ wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
+ "tx_status\n", __func__);
+ }
+
+ return false;
+
+ fatal:
+ if (p)
+ brcmu_pkt_buf_free_skb(p);
+
+ return true;
+
+}
+
+void
+wlc_txfifo_complete(struct wlc_info *wlc, uint fifo, s8 txpktpend)
+{
+ TXPKTPENDDEC(wlc, fifo, txpktpend);
+ BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend,
+ TXPKTPENDGET(wlc, fifo));
+
+ /* There is more room; mark precedences related to this FIFO sendable */
+ WLC_TX_FIFO_ENAB(wlc, fifo);
+
+ /* Clear MHF2_TXBCMC_NOW flag if BCMC fifo has drained */
+ if (AP_ENAB(wlc->pub) &&
+ !TXPKTPENDGET(wlc, TX_BCMC_FIFO)) {
+ wlc_mhf(wlc, MHF2, MHF2_TXBCMC_NOW, 0, WLC_BAND_AUTO);
+ }
+
+ /* figure out which bsscfg is being worked on... */
+}
+
+/* Update beacon listen interval in shared memory */
+void wlc_bcn_li_upd(struct wlc_info *wlc)
+{
+ if (AP_ENAB(wlc->pub))
+ return;
+
+ /* wake up every DTIM is the default */
+ if (wlc->bcn_li_dtim == 1)
+ wlc_write_shm(wlc, M_BCN_LI, 0);
+ else
+ wlc_write_shm(wlc, M_BCN_LI,
+ (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
+}
+
+/*
+ * recover 64bit TSF value from the 16bit TSF value in the rx header
+ * given the assumption that the TSF passed in header is within 65ms
+ * of the current tsf.
+ *
+ * 6 5 4 4 3 2 1
+ * 3.......6.......8.......0.......2.......4.......6.......8......0
+ * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
+ *
+ * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
+ * tsf_l is filled in by wlc_bmac_recv, which is done earlier in the
+ * receive call sequence after rx interrupt. Only the higher 16 bits
+ * are used. Finally, the tsf_h is read from the tsf register.
+ */
+static u64 wlc_recover_tsf64(struct wlc_info *wlc, struct wlc_d11rxhdr *rxh)
+{
+ u32 tsf_h, tsf_l;
+ u16 rx_tsf_0_15, rx_tsf_16_31;
+
+ wlc_bmac_read_tsf(wlc->hw, &tsf_l, &tsf_h);
+
+ rx_tsf_16_31 = (u16)(tsf_l >> 16);
+ rx_tsf_0_15 = rxh->rxhdr.RxTSFTime;
+
+ /*
+ * a greater tsf time indicates the low 16 bits of
+ * tsf_l wrapped, so decrement the high 16 bits.
+ */
+ if ((u16)tsf_l < rx_tsf_0_15) {
+ rx_tsf_16_31 -= 1;
+ if (rx_tsf_16_31 == 0xffff)
+ tsf_h -= 1;
+ }
+
+ return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
+}
+
+static void
+prep_mac80211_status(struct wlc_info *wlc, d11rxhdr_t *rxh, struct sk_buff *p,
+ struct ieee80211_rx_status *rx_status)
+{
+ wlc_d11rxhdr_t *wlc_rxh = (wlc_d11rxhdr_t *) rxh;
+ int preamble;
+ int channel;
+ ratespec_t rspec;
+ unsigned char *plcp;
+
+ /* fill in TSF and flag its presence */
+ rx_status->mactime = wlc_recover_tsf64(wlc, wlc_rxh);
+ rx_status->flag |= RX_FLAG_MACTIME_MPDU;
+
+ channel = WLC_CHAN_CHANNEL(rxh->RxChan);
+
+ if (channel > 14) {
+ rx_status->band = IEEE80211_BAND_5GHZ;
+ rx_status->freq = ieee80211_ofdm_chan_to_freq(
+ WF_CHAN_FACTOR_5_G/2, channel);
+
+ } else {
+ rx_status->band = IEEE80211_BAND_2GHZ;
+ rx_status->freq = ieee80211_dsss_chan_to_freq(channel);
+ }
+
+ rx_status->signal = wlc_rxh->rssi; /* signal */
+
+ /* noise */
+ /* qual */
+ rx_status->antenna = (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0; /* ant */
+
+ plcp = p->data;
+
+ rspec = wlc_compute_rspec(rxh, plcp);
+ if (IS_MCS(rspec)) {
+ rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
+ rx_status->flag |= RX_FLAG_HT;
+ if (RSPEC_IS40MHZ(rspec))
+ rx_status->flag |= RX_FLAG_40MHZ;
+ } else {
+ switch (RSPEC2RATE(rspec)) {
+ case WLC_RATE_1M:
+ rx_status->rate_idx = 0;
+ break;
+ case WLC_RATE_2M:
+ rx_status->rate_idx = 1;
+ break;
+ case WLC_RATE_5M5:
+ rx_status->rate_idx = 2;
+ break;
+ case WLC_RATE_11M:
+ rx_status->rate_idx = 3;
+ break;
+ case WLC_RATE_6M:
+ rx_status->rate_idx = 4;
+ break;
+ case WLC_RATE_9M:
+ rx_status->rate_idx = 5;
+ break;
+ case WLC_RATE_12M:
+ rx_status->rate_idx = 6;
+ break;
+ case WLC_RATE_18M:
+ rx_status->rate_idx = 7;
+ break;
+ case WLC_RATE_24M:
+ rx_status->rate_idx = 8;
+ break;
+ case WLC_RATE_36M:
+ rx_status->rate_idx = 9;
+ break;
+ case WLC_RATE_48M:
+ rx_status->rate_idx = 10;
+ break;
+ case WLC_RATE_54M:
+ rx_status->rate_idx = 11;
+ break;
+ default:
+ wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
+ }
+
+ /* Determine short preamble and rate_idx */
+ preamble = 0;
+ if (IS_CCK(rspec)) {
+ if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
+ rx_status->flag |= RX_FLAG_SHORTPRE;
+ } else if (IS_OFDM(rspec)) {
+ rx_status->flag |= RX_FLAG_SHORTPRE;
+ } else {
+ wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
+ __func__);
+ }
+ }
+
+ if (PLCP3_ISSGI(plcp[3]))
+ rx_status->flag |= RX_FLAG_SHORT_GI;
+
+ if (rxh->RxStatus1 & RXS_DECERR) {
+ rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
+ wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
+ __func__);
+ }
+ if (rxh->RxStatus1 & RXS_FCSERR) {
+ rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
+ wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
+ __func__);
+ }
+}
+
+static void
+wlc_recvctl(struct wlc_info *wlc, d11rxhdr_t *rxh, struct sk_buff *p)
+{
+ int len_mpdu;
+ struct ieee80211_rx_status rx_status;
+
+ memset(&rx_status, 0, sizeof(rx_status));
+ prep_mac80211_status(wlc, rxh, p, &rx_status);
+
+ /* mac header+body length, exclude CRC and plcp header */
+ len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
+ skb_pull(p, D11_PHY_HDR_LEN);
+ __skb_trim(p, len_mpdu);
+
+ memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
+ ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
+ return;
+}
+
+/* Process received frames */
+/*
+ * Return true if more frames need to be processed. false otherwise.
+ * Param 'bound' indicates max. # frames to process before break out.
+ */
+/* WLC_HIGH_API */
+void wlc_recv(struct wlc_info *wlc, struct sk_buff *p)
+{
+ d11rxhdr_t *rxh;
+ struct ieee80211_hdr *h;
+ uint len;
+ bool is_amsdu;
+
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
+
+ /* frame starts with rxhdr */
+ rxh = (d11rxhdr_t *) (p->data);
+
+ /* strip off rxhdr */
+ skb_pull(p, WL_HWRXOFF);
+
+ /* fixup rx header endianness */
+ rxh->RxFrameSize = le16_to_cpu(rxh->RxFrameSize);
+ rxh->PhyRxStatus_0 = le16_to_cpu(rxh->PhyRxStatus_0);
+ rxh->PhyRxStatus_1 = le16_to_cpu(rxh->PhyRxStatus_1);
+ rxh->PhyRxStatus_2 = le16_to_cpu(rxh->PhyRxStatus_2);
+ rxh->PhyRxStatus_3 = le16_to_cpu(rxh->PhyRxStatus_3);
+ rxh->PhyRxStatus_4 = le16_to_cpu(rxh->PhyRxStatus_4);
+ rxh->PhyRxStatus_5 = le16_to_cpu(rxh->PhyRxStatus_5);
+ rxh->RxStatus1 = le16_to_cpu(rxh->RxStatus1);
+ rxh->RxStatus2 = le16_to_cpu(rxh->RxStatus2);
+ rxh->RxTSFTime = le16_to_cpu(rxh->RxTSFTime);
+ rxh->RxChan = le16_to_cpu(rxh->RxChan);
+
+ /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
+ if (rxh->RxStatus1 & RXS_PBPRES) {
+ if (p->len < 2) {
+ wiphy_err(wlc->wiphy, "wl%d: wlc_recv: rcvd runt of "
+ "len %d\n", wlc->pub->unit, p->len);
+ goto toss;
+ }
+ skb_pull(p, 2);
+ }
+
+ h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
+ len = p->len;
+
+ if (rxh->RxStatus1 & RXS_FCSERR) {
+ if (wlc->pub->mac80211_state & MAC80211_PROMISC_BCNS) {
+ wiphy_err(wlc->wiphy, "FCSERR while scanning******* -"
+ " tossing\n");
+ goto toss;
+ } else {
+ wiphy_err(wlc->wiphy, "RCSERR!!!\n");
+ goto toss;
+ }
+ }
+
+ /* check received pkt has at least frame control field */
+ if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control)) {
+ goto toss;
+ }
+
+ is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
+
+ /* explicitly test bad src address to avoid sending bad deauth */
+ if (!is_amsdu) {
+ /* CTS and ACK CTL frames are w/o a2 */
+
+ if (ieee80211_is_data(h->frame_control) ||
+ ieee80211_is_mgmt(h->frame_control)) {
+ if ((is_zero_ether_addr(h->addr2) ||
+ is_multicast_ether_addr(h->addr2))) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: dropping a "
+ "frame with invalid src mac address,"
+ " a2: %pM\n",
+ wlc->pub->unit, __func__, h->addr2);
+ goto toss;
+ }
+ }
+ }
+
+ /* due to sheer numbers, toss out probe reqs for now */
+ if (ieee80211_is_probe_req(h->frame_control))
+ goto toss;
+
+ if (is_amsdu)
+ goto toss;
+
+ wlc_recvctl(wlc, rxh, p);
+ return;
+
+ toss:
+ brcmu_pkt_buf_free_skb(p);
+}
+
+/* calculate frame duration for Mixed-mode L-SIG spoofing, return
+ * number of bytes goes in the length field
+ *
+ * Formula given by HT PHY Spec v 1.13
+ * len = 3(nsyms + nstream + 3) - 3
+ */
+u16
+wlc_calc_lsig_len(struct wlc_info *wlc, ratespec_t ratespec, uint mac_len)
+{
+ uint nsyms, len = 0, kNdps;
+
+ BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
+ wlc->pub->unit, RSPEC2RATE(ratespec), mac_len);
+
+ if (IS_MCS(ratespec)) {
+ uint mcs = ratespec & RSPEC_RATE_MASK;
+ /* MCS_TXS(mcs) returns num tx streams - 1 */
+ int tot_streams = (MCS_TXS(mcs) + 1) + RSPEC_STC(ratespec);
+
+ /* the payload duration calculation matches that of regular ofdm */
+ /* 1000Ndbps = kbps * 4 */
+ kNdps =
+ MCS_RATE(mcs, RSPEC_IS40MHZ(ratespec),
+ RSPEC_ISSGI(ratespec)) * 4;
+
+ if (RSPEC_STC(ratespec) == 0)
+ /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
+ nsyms =
+ CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
+ APHY_TAIL_NBITS) * 1000, kNdps);
+ else
+ /* STBC needs to have even number of symbols */
+ nsyms =
+ 2 *
+ CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
+ APHY_TAIL_NBITS) * 1000, 2 * kNdps);
+
+ nsyms += (tot_streams + 3); /* (+3) account for HT-SIG(2) and HT-STF(1) */
+ /* 3 bytes/symbol @ legacy 6Mbps rate */
+ len = (3 * nsyms) - 3; /* (-3) excluding service bits and tail bits */
+ }
+
+ return (u16) len;
+}
+
+/* calculate frame duration of a given rate and length, return time in usec unit */
+uint
+wlc_calc_frame_time(struct wlc_info *wlc, ratespec_t ratespec, u8 preamble_type,
+ uint mac_len)
+{
+ uint nsyms, dur = 0, Ndps, kNdps;
+ uint rate = RSPEC2RATE(ratespec);
+
+ if (rate == 0) {
+ wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
+ wlc->pub->unit);
+ rate = WLC_RATE_1M;
+ }
+
+ BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
+ wlc->pub->unit, ratespec, preamble_type, mac_len);
+
+ if (IS_MCS(ratespec)) {
+ uint mcs = ratespec & RSPEC_RATE_MASK;
+ int tot_streams = MCS_TXS(mcs) + RSPEC_STC(ratespec);
+
+ dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
+ if (preamble_type == WLC_MM_PREAMBLE)
+ dur += PREN_MM_EXT;
+ /* 1000Ndbps = kbps * 4 */
+ kNdps =
+ MCS_RATE(mcs, RSPEC_IS40MHZ(ratespec),
+ RSPEC_ISSGI(ratespec)) * 4;
+
+ if (RSPEC_STC(ratespec) == 0)
+ /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
+ nsyms =
+ CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
+ APHY_TAIL_NBITS) * 1000, kNdps);
+ else
+ /* STBC needs to have even number of symbols */
+ nsyms =
+ 2 *
+ CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
+ APHY_TAIL_NBITS) * 1000, 2 * kNdps);
+
+ dur += APHY_SYMBOL_TIME * nsyms;
+ if (BAND_2G(wlc->band->bandtype))
+ dur += DOT11_OFDM_SIGNAL_EXTENSION;
+ } else if (IS_OFDM(rate)) {
+ dur = APHY_PREAMBLE_TIME;
+ dur += APHY_SIGNAL_TIME;
+ /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
+ Ndps = rate * 2;
+ /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
+ nsyms =
+ CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
+ Ndps);
+ dur += APHY_SYMBOL_TIME * nsyms;
+ if (BAND_2G(wlc->band->bandtype))
+ dur += DOT11_OFDM_SIGNAL_EXTENSION;
+ } else {
+ /* calc # bits * 2 so factor of 2 in rate (1/2 mbps) will divide out */
+ mac_len = mac_len * 8 * 2;
+ /* calc ceiling of bits/rate = microseconds of air time */
+ dur = (mac_len + rate - 1) / rate;
+ if (preamble_type & WLC_SHORT_PREAMBLE)
+ dur += BPHY_PLCP_SHORT_TIME;
+ else
+ dur += BPHY_PLCP_TIME;
+ }
+ return dur;
+}
+
+/* The opposite of wlc_calc_frame_time */
+static uint
+wlc_calc_frame_len(struct wlc_info *wlc, ratespec_t ratespec, u8 preamble_type,
+ uint dur)
+{
+ uint nsyms, mac_len, Ndps, kNdps;
+ uint rate = RSPEC2RATE(ratespec);
+
+ BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
+ wlc->pub->unit, ratespec, preamble_type, dur);
+
+ if (IS_MCS(ratespec)) {
+ uint mcs = ratespec & RSPEC_RATE_MASK;
+ int tot_streams = MCS_TXS(mcs) + RSPEC_STC(ratespec);
+ dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
+ /* payload calculation matches that of regular ofdm */
+ if (BAND_2G(wlc->band->bandtype))
+ dur -= DOT11_OFDM_SIGNAL_EXTENSION;
+ /* kNdbps = kbps * 4 */
+ kNdps =
+ MCS_RATE(mcs, RSPEC_IS40MHZ(ratespec),
+ RSPEC_ISSGI(ratespec)) * 4;
+ nsyms = dur / APHY_SYMBOL_TIME;
+ mac_len =
+ ((nsyms * kNdps) -
+ ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
+ } else if (IS_OFDM(ratespec)) {
+ dur -= APHY_PREAMBLE_TIME;
+ dur -= APHY_SIGNAL_TIME;
+ /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
+ Ndps = rate * 2;
+ nsyms = dur / APHY_SYMBOL_TIME;
+ mac_len =
+ ((nsyms * Ndps) -
+ (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
+ } else {
+ if (preamble_type & WLC_SHORT_PREAMBLE)
+ dur -= BPHY_PLCP_SHORT_TIME;
+ else
+ dur -= BPHY_PLCP_TIME;
+ mac_len = dur * rate;
+ /* divide out factor of 2 in rate (1/2 mbps) */
+ mac_len = mac_len / 8 / 2;
+ }
+ return mac_len;
+}
+
+static uint
+wlc_calc_ba_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
+{
+ BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
+ "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
+ /* Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that is less than
+ * or equal to the rate of the immediately previous frame in the FES
+ */
+ rspec = WLC_BASIC_RATE(wlc, rspec);
+ /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
+ return wlc_calc_frame_time(wlc, rspec, preamble_type,
+ (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
+ FCS_LEN));
+}
+
+static uint
+wlc_calc_ack_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
+{
+ uint dur = 0;
+
+ BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
+ wlc->pub->unit, rspec, preamble_type);
+ /* Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that is less than
+ * or equal to the rate of the immediately previous frame in the FES
+ */
+ rspec = WLC_BASIC_RATE(wlc, rspec);
+ /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
+ dur =
+ wlc_calc_frame_time(wlc, rspec, preamble_type,
+ (DOT11_ACK_LEN + FCS_LEN));
+ return dur;
+}
+
+static uint
+wlc_calc_cts_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
+{
+ BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
+ wlc->pub->unit, rspec, preamble_type);
+ return wlc_calc_ack_time(wlc, rspec, preamble_type);
+}
+
+/* derive wlc->band->basic_rate[] table from 'rateset' */
+void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset)
+{
+ u8 rate;
+ u8 mandatory;
+ u8 cck_basic = 0;
+ u8 ofdm_basic = 0;
+ u8 *br = wlc->band->basic_rate;
+ uint i;
+
+ /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
+ memset(br, 0, WLC_MAXRATE + 1);
+
+ /* For each basic rate in the rates list, make an entry in the
+ * best basic lookup.
+ */
+ for (i = 0; i < rateset->count; i++) {
+ /* only make an entry for a basic rate */
+ if (!(rateset->rates[i] & WLC_RATE_FLAG))
+ continue;
+
+ /* mask off basic bit */
+ rate = (rateset->rates[i] & WLC_RATE_MASK);
+
+ if (rate > WLC_MAXRATE) {
+ wiphy_err(wlc->wiphy, "wlc_rate_lookup_init: invalid "
+ "rate 0x%X in rate set\n",
+ rateset->rates[i]);
+ continue;
+ }
+
+ br[rate] = rate;
+ }
+
+ /* The rate lookup table now has non-zero entries for each
+ * basic rate, equal to the basic rate: br[basicN] = basicN
+ *
+ * To look up the best basic rate corresponding to any
+ * particular rate, code can use the basic_rate table
+ * like this
+ *
+ * basic_rate = wlc->band->basic_rate[tx_rate]
+ *
+ * Make sure there is a best basic rate entry for
+ * every rate by walking up the table from low rates
+ * to high, filling in holes in the lookup table
+ */
+
+ for (i = 0; i < wlc->band->hw_rateset.count; i++) {
+ rate = wlc->band->hw_rateset.rates[i];
+
+ if (br[rate] != 0) {
+ /* This rate is a basic rate.
+ * Keep track of the best basic rate so far by
+ * modulation type.
+ */
+ if (IS_OFDM(rate))
+ ofdm_basic = rate;
+ else
+ cck_basic = rate;
+
+ continue;
+ }
+
+ /* This rate is not a basic rate so figure out the
+ * best basic rate less than this rate and fill in
+ * the hole in the table
+ */
+
+ br[rate] = IS_OFDM(rate) ? ofdm_basic : cck_basic;
+
+ if (br[rate] != 0)
+ continue;
+
+ if (IS_OFDM(rate)) {
+ /* In 11g and 11a, the OFDM mandatory rates are 6, 12, and 24 Mbps */
+ if (rate >= WLC_RATE_24M)
+ mandatory = WLC_RATE_24M;
+ else if (rate >= WLC_RATE_12M)
+ mandatory = WLC_RATE_12M;
+ else
+ mandatory = WLC_RATE_6M;
+ } else {
+ /* In 11b, all the CCK rates are mandatory 1 - 11 Mbps */
+ mandatory = rate;
+ }
+
+ br[rate] = mandatory;
+ }
+}
+
+static void wlc_write_rate_shm(struct wlc_info *wlc, u8 rate, u8 basic_rate)
+{
+ u8 phy_rate, index;
+ u8 basic_phy_rate, basic_index;
+ u16 dir_table, basic_table;
+ u16 basic_ptr;
+
+ /* Shared memory address for the table we are reading */
+ dir_table = IS_OFDM(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
+
+ /* Shared memory address for the table we are writing */
+ basic_table = IS_OFDM(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
+
+ /*
+ * for a given rate, the LS-nibble of the PLCP SIGNAL field is
+ * the index into the rate table.
+ */
+ phy_rate = rate_info[rate] & WLC_RATE_MASK;
+ basic_phy_rate = rate_info[basic_rate] & WLC_RATE_MASK;
+ index = phy_rate & 0xf;
+ basic_index = basic_phy_rate & 0xf;
+
+ /* Find the SHM pointer to the ACK rate entry by looking in the
+ * Direct-map Table
+ */
+ basic_ptr = wlc_read_shm(wlc, (dir_table + basic_index * 2));
+
+ /* Update the SHM BSS-basic-rate-set mapping table with the pointer
+ * to the correct basic rate for the given incoming rate
+ */
+ wlc_write_shm(wlc, (basic_table + index * 2), basic_ptr);
+}
+
+static const wlc_rateset_t *wlc_rateset_get_hwrs(struct wlc_info *wlc)
+{
+ const wlc_rateset_t *rs_dflt;
+
+ if (WLC_PHY_11N_CAP(wlc->band)) {
+ if (BAND_5G(wlc->band->bandtype))
+ rs_dflt = &ofdm_mimo_rates;
+ else
+ rs_dflt = &cck_ofdm_mimo_rates;
+ } else if (wlc->band->gmode)
+ rs_dflt = &cck_ofdm_rates;
+ else
+ rs_dflt = &cck_rates;
+
+ return rs_dflt;
+}
+
+void wlc_set_ratetable(struct wlc_info *wlc)
+{
+ const wlc_rateset_t *rs_dflt;
+ wlc_rateset_t rs;
+ u8 rate, basic_rate;
+ uint i;
+
+ rs_dflt = wlc_rateset_get_hwrs(wlc);
+
+ wlc_rateset_copy(rs_dflt, &rs);
+ wlc_rateset_mcs_upd(&rs, wlc->stf->txstreams);
+
+ /* walk the phy rate table and update SHM basic rate lookup table */
+ for (i = 0; i < rs.count; i++) {
+ rate = rs.rates[i] & WLC_RATE_MASK;
+
+ /* for a given rate WLC_BASIC_RATE returns the rate at
+ * which a response ACK/CTS should be sent.
+ */
+ basic_rate = WLC_BASIC_RATE(wlc, rate);
+ if (basic_rate == 0) {
+ /* This should only happen if we are using a
+ * restricted rateset.
+ */
+ basic_rate = rs.rates[0] & WLC_RATE_MASK;
+ }
+
+ wlc_write_rate_shm(wlc, rate, basic_rate);
+ }
+}
+
+/*
+ * Return true if the specified rate is supported by the specified band.
+ * WLC_BAND_AUTO indicates the current band.
+ */
+bool wlc_valid_rate(struct wlc_info *wlc, ratespec_t rspec, int band,
+ bool verbose)
+{
+ wlc_rateset_t *hw_rateset;
+ uint i;
+
+ if ((band == WLC_BAND_AUTO) || (band == wlc->band->bandtype)) {
+ hw_rateset = &wlc->band->hw_rateset;
+ } else if (NBANDS(wlc) > 1) {
+ hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
+ } else {
+ /* other band specified and we are a single band device */
+ return false;
+ }
+
+ /* check if this is a mimo rate */
+ if (IS_MCS(rspec)) {
+ if (!VALID_MCS((rspec & RSPEC_RATE_MASK)))
+ goto error;
+
+ return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
+ }
+
+ for (i = 0; i < hw_rateset->count; i++)
+ if (hw_rateset->rates[i] == RSPEC2RATE(rspec))
+ return true;
+ error:
+ if (verbose) {
+ wiphy_err(wlc->wiphy, "wl%d: wlc_valid_rate: rate spec 0x%x "
+ "not in hw_rateset\n", wlc->pub->unit, rspec);
+ }
+
+ return false;
+}
+
+static void wlc_update_mimo_band_bwcap(struct wlc_info *wlc, u8 bwcap)
+{
+ uint i;
+ struct wlcband *band;
+
+ for (i = 0; i < NBANDS(wlc); i++) {
+ if (IS_SINGLEBAND_5G(wlc->deviceid))
+ i = BAND_5G_INDEX;
+ band = wlc->bandstate[i];
+ if (band->bandtype == WLC_BAND_5G) {
+ if ((bwcap == WLC_N_BW_40ALL)
+ || (bwcap == WLC_N_BW_20IN2G_40IN5G))
+ band->mimo_cap_40 = true;
+ else
+ band->mimo_cap_40 = false;
+ } else {
+ if (bwcap == WLC_N_BW_40ALL)
+ band->mimo_cap_40 = true;
+ else
+ band->mimo_cap_40 = false;
+ }
+ }
+}
+
+void wlc_mod_prb_rsp_rate_table(struct wlc_info *wlc, uint frame_len)
+{
+ const wlc_rateset_t *rs_dflt;
+ wlc_rateset_t rs;
+ u8 rate;
+ u16 entry_ptr;
+ u8 plcp[D11_PHY_HDR_LEN];
+ u16 dur, sifs;
+ uint i;
+
+ sifs = SIFS(wlc->band);
+
+ rs_dflt = wlc_rateset_get_hwrs(wlc);
+
+ wlc_rateset_copy(rs_dflt, &rs);
+ wlc_rateset_mcs_upd(&rs, wlc->stf->txstreams);
+
+ /* walk the phy rate table and update MAC core SHM basic rate table entries */
+ for (i = 0; i < rs.count; i++) {
+ rate = rs.rates[i] & WLC_RATE_MASK;
+
+ entry_ptr = wlc_rate_shm_offset(wlc, rate);
+
+ /* Calculate the Probe Response PLCP for the given rate */
+ wlc_compute_plcp(wlc, rate, frame_len, plcp);
+
+ /* Calculate the duration of the Probe Response frame plus SIFS for the MAC */
+ dur =
+ (u16) wlc_calc_frame_time(wlc, rate, WLC_LONG_PREAMBLE,
+ frame_len);
+ dur += sifs;
+
+ /* Update the SHM Rate Table entry Probe Response values */
+ wlc_write_shm(wlc, entry_ptr + M_RT_PRS_PLCP_POS,
+ (u16) (plcp[0] + (plcp[1] << 8)));
+ wlc_write_shm(wlc, entry_ptr + M_RT_PRS_PLCP_POS + 2,
+ (u16) (plcp[2] + (plcp[3] << 8)));
+ wlc_write_shm(wlc, entry_ptr + M_RT_PRS_DUR_POS, dur);
+ }
+}
+
+/* Max buffering needed for beacon template/prb resp template is 142 bytes.
+ *
+ * PLCP header is 6 bytes.
+ * 802.11 A3 header is 24 bytes.
+ * Max beacon frame body template length is 112 bytes.
+ * Max probe resp frame body template length is 110 bytes.
+ *
+ * *len on input contains the max length of the packet available.
+ *
+ * The *len value is set to the number of bytes in buf used, and starts with the PLCP
+ * and included up to, but not including, the 4 byte FCS.
+ */
+static void
+wlc_bcn_prb_template(struct wlc_info *wlc, u16 type, ratespec_t bcn_rspec,
+ struct wlc_bsscfg *cfg, u16 *buf, int *len)
+{
+ static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
+ cck_phy_hdr_t *plcp;
+ struct ieee80211_mgmt *h;
+ int hdr_len, body_len;
+
+ if (MBSS_BCN_ENAB(cfg) && type == IEEE80211_STYPE_BEACON)
+ hdr_len = DOT11_MAC_HDR_LEN;
+ else
+ hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
+ body_len = *len - hdr_len; /* calc buffer size provided for frame body */
+
+ *len = hdr_len + body_len; /* return actual size */
+
+ /* format PHY and MAC headers */
+ memset((char *)buf, 0, hdr_len);
+
+ plcp = (cck_phy_hdr_t *) buf;
+
+ /* PLCP for Probe Response frames are filled in from core's rate table */
+ if (type == IEEE80211_STYPE_BEACON && !MBSS_BCN_ENAB(cfg)) {
+ /* fill in PLCP */
+ wlc_compute_plcp(wlc, bcn_rspec,
+ (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
+ (u8 *) plcp);
+
+ }
+ /* "Regular" and 16 MBSS but not for 4 MBSS */
+ /* Update the phytxctl for the beacon based on the rspec */
+ if (!SOFTBCN_ENAB(cfg))
+ wlc_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
+
+ if (MBSS_BCN_ENAB(cfg) && type == IEEE80211_STYPE_BEACON)
+ h = (struct ieee80211_mgmt *)&plcp[0];
+ else
+ h = (struct ieee80211_mgmt *)&plcp[1];
+
+ /* fill in 802.11 header */
+ h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
+
+ /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
+ /* A1 filled in by MAC for prb resp, broadcast for bcn */
+ if (type == IEEE80211_STYPE_BEACON)
+ memcpy(&h->da, ðer_bcast, ETH_ALEN);
+ memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
+ memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
+
+ /* SEQ filled in by MAC */
+
+ return;
+}
+
+int wlc_get_header_len()
+{
+ return TXOFF;
+}
+
+/* Update a beacon for a particular BSS
+ * For MBSS, this updates the software template and sets "latest" to the index of the
+ * template updated.
+ * Otherwise, it updates the hardware template.
+ */
+void wlc_bss_update_beacon(struct wlc_info *wlc, struct wlc_bsscfg *cfg)
+{
+ int len = BCN_TMPL_LEN;
+
+ /* Clear the soft intmask */
+ wlc->defmacintmask &= ~MI_BCNTPL;
+
+ if (!cfg->up) { /* Only allow updates on an UP bss */
+ return;
+ }
+
+ /* Optimize: Some of if/else could be combined */
+ if (!MBSS_BCN_ENAB(cfg) && HWBCN_ENAB(cfg)) {
+ /* Hardware beaconing for this config */
+ u16 bcn[BCN_TMPL_LEN / 2];
+ u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD;
+ d11regs_t *regs = wlc->regs;
+
+ /* Check if both templates are in use, if so sched. an interrupt
+ * that will call back into this routine
+ */
+ if ((R_REG(®s->maccommand) & both_valid) == both_valid) {
+ /* clear any previous status */
+ W_REG(®s->macintstatus, MI_BCNTPL);
+ }
+ /* Check that after scheduling the interrupt both of the
+ * templates are still busy. if not clear the int. & remask
+ */
+ if ((R_REG(®s->maccommand) & both_valid) == both_valid) {
+ wlc->defmacintmask |= MI_BCNTPL;
+ return;
+ }
+
+ wlc->bcn_rspec =
+ wlc_lowest_basic_rspec(wlc, &cfg->current_bss->rateset);
+ /* update the template and ucode shm */
+ wlc_bcn_prb_template(wlc, IEEE80211_STYPE_BEACON,
+ wlc->bcn_rspec, cfg, bcn, &len);
+ wlc_write_hw_bcntemplates(wlc, bcn, len, false);
+ }
+}
+
+/*
+ * Update all beacons for the system.
+ */
+void wlc_update_beacon(struct wlc_info *wlc)
+{
+ int idx;
+ struct wlc_bsscfg *bsscfg;
+
+ /* update AP or IBSS beacons */
+ FOREACH_BSS(wlc, idx, bsscfg) {
+ if (bsscfg->up && (BSSCFG_AP(bsscfg) || !bsscfg->BSS))
+ wlc_bss_update_beacon(wlc, bsscfg);
+ }
+}
+
+/* Write ssid into shared memory */
+void wlc_shm_ssid_upd(struct wlc_info *wlc, struct wlc_bsscfg *cfg)
+{
+ u8 *ssidptr = cfg->SSID;
+ u16 base = M_SSID;
+ u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
+
+ /* padding the ssid with zero and copy it into shm */
+ memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
+ memcpy(ssidbuf, ssidptr, cfg->SSID_len);
+
+ wlc_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
+
+ if (!MBSS_BCN_ENAB(cfg))
+ wlc_write_shm(wlc, M_SSIDLEN, (u16) cfg->SSID_len);
+}
+
+void wlc_update_probe_resp(struct wlc_info *wlc, bool suspend)
+{
+ int idx;
+ struct wlc_bsscfg *bsscfg;
+
+ /* update AP or IBSS probe responses */
+ FOREACH_BSS(wlc, idx, bsscfg) {
+ if (bsscfg->up && (BSSCFG_AP(bsscfg) || !bsscfg->BSS))
+ wlc_bss_update_probe_resp(wlc, bsscfg, suspend);
+ }
+}
+
+void
+wlc_bss_update_probe_resp(struct wlc_info *wlc, struct wlc_bsscfg *cfg,
+ bool suspend)
+{
+ u16 prb_resp[BCN_TMPL_LEN / 2];
+ int len = BCN_TMPL_LEN;
+
+ /* write the probe response to hardware, or save in the config structure */
+ if (!MBSS_PRB_ENAB(cfg)) {
+
+ /* create the probe response template */
+ wlc_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0, cfg,
+ prb_resp, &len);
+
+ if (suspend)
+ wlc_suspend_mac_and_wait(wlc);
+
+ /* write the probe response into the template region */
+ wlc_bmac_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
+ (len + 3) & ~3, prb_resp);
+
+ /* write the length of the probe response frame (+PLCP/-FCS) */
+ wlc_write_shm(wlc, M_PRB_RESP_FRM_LEN, (u16) len);
+
+ /* write the SSID and SSID length */
+ wlc_shm_ssid_upd(wlc, cfg);
+
+ /*
+ * Write PLCP headers and durations for probe response frames at all rates.
+ * Use the actual frame length covered by the PLCP header for the call to
+ * wlc_mod_prb_rsp_rate_table() by subtracting the PLCP len and adding the FCS.
+ */
+ len += (-D11_PHY_HDR_LEN + FCS_LEN);
+ wlc_mod_prb_rsp_rate_table(wlc, (u16) len);
+
+ if (suspend)
+ wlc_enable_mac(wlc);
+ } else { /* Generating probe resp in sw; update local template */
+ /* error: No software probe response support without MBSS */
+ }
+}
+
+/* prepares pdu for transmission. returns BCM error codes */
+int wlc_prep_pdu(struct wlc_info *wlc, struct sk_buff *pdu, uint *fifop)
+{
+ uint fifo;
+ d11txh_t *txh;
+ struct ieee80211_hdr *h;
+ struct scb *scb;
+
+ txh = (d11txh_t *) (pdu->data);
+ h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
+
+ /* get the pkt queue info. This was put at wlc_sendctl or wlc_send for PDU */
+ fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
+
+ scb = NULL;
+
+ *fifop = fifo;
+
+ /* return if insufficient dma resources */
+ if (TXAVAIL(wlc, fifo) < MAX_DMA_SEGS) {
+ /* Mark precedences related to this FIFO, unsendable */
+ WLC_TX_FIFO_CLEAR(wlc, fifo);
+ return -EBUSY;
+ }
+ return 0;
+}
+
+/* init tx reported rate mechanism */
+void wlc_reprate_init(struct wlc_info *wlc)
+{
+ int i;
+ struct wlc_bsscfg *bsscfg;
+
+ FOREACH_BSS(wlc, i, bsscfg) {
+ wlc_bsscfg_reprate_init(bsscfg);
+ }
+}
+
+/* per bsscfg init tx reported rate mechanism */
+void wlc_bsscfg_reprate_init(struct wlc_bsscfg *bsscfg)
+{
+ bsscfg->txrspecidx = 0;
+ memset((char *)bsscfg->txrspec, 0, sizeof(bsscfg->txrspec));
+}
+
+void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs)
+{
+ wlc_rateset_default(rs, NULL, wlc->band->phytype, wlc->band->bandtype,
+ false, WLC_RATE_MASK_FULL, (bool) N_ENAB(wlc->pub),
+ CHSPEC_WLC_BW(wlc->default_bss->chanspec),
+ wlc->stf->txstreams);
+}
+
+static void wlc_bss_default_init(struct wlc_info *wlc)
+{
+ chanspec_t chanspec;
+ struct wlcband *band;
+ wlc_bss_info_t *bi = wlc->default_bss;
+
+ /* init default and target BSS with some sane initial values */
+ memset((char *)(bi), 0, sizeof(wlc_bss_info_t));
+ bi->beacon_period = ISSIM_ENAB(wlc->pub->sih) ? BEACON_INTERVAL_DEF_QT :
+ BEACON_INTERVAL_DEFAULT;
+ bi->dtim_period = ISSIM_ENAB(wlc->pub->sih) ? DTIM_INTERVAL_DEF_QT :
+ DTIM_INTERVAL_DEFAULT;
+
+ /* fill the default channel as the first valid channel
+ * starting from the 2G channels
+ */
+ chanspec = CH20MHZ_CHSPEC(1);
+ wlc->home_chanspec = bi->chanspec = chanspec;
+
+ /* find the band of our default channel */
+ band = wlc->band;
+ if (NBANDS(wlc) > 1 && band->bandunit != CHSPEC_WLCBANDUNIT(chanspec))
+ band = wlc->bandstate[OTHERBANDUNIT(wlc)];
+
+ /* init bss rates to the band specific default rate set */
+ wlc_rateset_default(&bi->rateset, NULL, band->phytype, band->bandtype,
+ false, WLC_RATE_MASK_FULL, (bool) N_ENAB(wlc->pub),
+ CHSPEC_WLC_BW(chanspec), wlc->stf->txstreams);
+
+ if (N_ENAB(wlc->pub))
+ bi->flags |= WLC_BSS_HT;
+}
+
+static ratespec_t
+mac80211_wlc_set_nrate(struct wlc_info *wlc, struct wlcband *cur_band,
+ u32 int_val)
+{
+ u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
+ u8 rate = int_val & NRATE_RATE_MASK;
+ ratespec_t rspec;
+ bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
+ bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
+ bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
+ == NRATE_OVERRIDE_MCS_ONLY);
+ int bcmerror = 0;
+
+ if (!ismcs) {
+ return (ratespec_t) rate;
+ }
+
+ /* validate the combination of rate/mcs/stf is allowed */
+ if (N_ENAB(wlc->pub) && ismcs) {
+ /* mcs only allowed when nmode */
+ if (stf > PHY_TXC1_MODE_SDM) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
+ WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
+ goto done;
+ }
+
+ /* mcs 32 is a special case, DUP mode 40 only */
+ if (rate == 32) {
+ if (!CHSPEC_IS40(wlc->home_chanspec) ||
+ ((stf != PHY_TXC1_MODE_SISO)
+ && (stf != PHY_TXC1_MODE_CDD))) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
+ "32\n", WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
+ goto done;
+ }
+ /* mcs > 7 must use stf SDM */
+ } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
+ /* mcs > 7 must use stf SDM */
+ if (stf != PHY_TXC1_MODE_SDM) {
+ BCMMSG(wlc->wiphy, "wl%d: enabling "
+ "SDM mode for mcs %d\n",
+ WLCWLUNIT(wlc), rate);
+ stf = PHY_TXC1_MODE_SDM;
+ }
+ } else {
+ /* MCS 0-7 may use SISO, CDD, and for phy_rev >= 3 STBC */
+ if ((stf > PHY_TXC1_MODE_STBC) ||
+ (!WLC_STBC_CAP_PHY(wlc)
+ && (stf == PHY_TXC1_MODE_STBC))) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
+ "\n", WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
+ goto done;
+ }
+ }
+ } else if (IS_OFDM(rate)) {
+ if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
+ WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
+ goto done;
+ }
+ } else if (IS_CCK(rate)) {
+ if ((cur_band->bandtype != WLC_BAND_2G)
+ || (stf != PHY_TXC1_MODE_SISO)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
+ WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
+ goto done;
+ }
+ } else {
+ wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
+ WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
+ goto done;
+ }
+ /* make sure multiple antennae are available for non-siso rates */
+ if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
+ wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
+ "request\n", WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
+ goto done;
+ }
+
+ rspec = rate;
+ if (ismcs) {
+ rspec |= RSPEC_MIMORATE;
+ /* For STBC populate the STC field of the ratespec */
+ if (stf == PHY_TXC1_MODE_STBC) {
+ u8 stc;
+ stc = 1; /* Nss for single stream is always 1 */
+ rspec |= (stc << RSPEC_STC_SHIFT);
+ }
+ }
+
+ rspec |= (stf << RSPEC_STF_SHIFT);
+
+ if (override_mcs_only)
+ rspec |= RSPEC_OVERRIDE_MCS_ONLY;
+
+ if (issgi)
+ rspec |= RSPEC_SHORT_GI;
+
+ if ((rate != 0)
+ && !wlc_valid_rate(wlc, rspec, cur_band->bandtype, true)) {
+ return rate;
+ }
+
+ return rspec;
+done:
+ return rate;
+}
+
+/* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
+static int
+wlc_duty_cycle_set(struct wlc_info *wlc, int duty_cycle, bool isOFDM,
+ bool writeToShm)
+{
+ int idle_busy_ratio_x_16 = 0;
+ uint offset =
+ isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
+ M_TX_IDLE_BUSY_RATIO_X_16_CCK;
+ if (duty_cycle > 100 || duty_cycle < 0) {
+ wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
+ wlc->pub->unit);
+ return -EINVAL;
+ }
+ if (duty_cycle)
+ idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
+ /* Only write to shared memory when wl is up */
+ if (writeToShm)
+ wlc_write_shm(wlc, offset, (u16) idle_busy_ratio_x_16);
+
+ if (isOFDM)
+ wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
+ else
+ wlc->tx_duty_cycle_cck = (u16) duty_cycle;
+
+ return 0;
+}
+
+/* Read a single u16 from shared memory.
+ * SHM 'offset' needs to be an even address
+ */
+u16 wlc_read_shm(struct wlc_info *wlc, uint offset)
+{
+ return wlc_bmac_read_shm(wlc->hw, offset);
+}
+
+/* Write a single u16 to shared memory.
+ * SHM 'offset' needs to be an even address
+ */
+void wlc_write_shm(struct wlc_info *wlc, uint offset, u16 v)
+{
+ wlc_bmac_write_shm(wlc->hw, offset, v);
+}
+
+/* Copy a buffer to shared memory.
+ * SHM 'offset' needs to be an even address and
+ * Buffer length 'len' must be an even number of bytes
+ */
+void wlc_copyto_shm(struct wlc_info *wlc, uint offset, const void *buf, int len)
+{
+ /* offset and len need to be even */
+ if (len <= 0 || (offset & 1) || (len & 1))
+ return;
+
+ wlc_bmac_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
+
+}
+
+/* wrapper BMAC functions to for HIGH driver access */
+void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val)
+{
+ wlc_bmac_mctrl(wlc->hw, mask, val);
+}
+
+void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val, int bands)
+{
+ wlc_bmac_mhf(wlc->hw, idx, mask, val, bands);
+}
+
+int wlc_xmtfifo_sz_get(struct wlc_info *wlc, uint fifo, uint *blocks)
+{
+ return wlc_bmac_xmtfifo_sz_get(wlc->hw, fifo, blocks);
+}
+
+void wlc_write_template_ram(struct wlc_info *wlc, int offset, int len,
+ void *buf)
+{
+ wlc_bmac_write_template_ram(wlc->hw, offset, len, buf);
+}
+
+void wlc_write_hw_bcntemplates(struct wlc_info *wlc, void *bcn, int len,
+ bool both)
+{
+ wlc_bmac_write_hw_bcntemplates(wlc->hw, bcn, len, both);
+}
+
+void
+wlc_set_addrmatch(struct wlc_info *wlc, int match_reg_offset,
+ const u8 *addr)
+{
+ wlc_bmac_set_addrmatch(wlc->hw, match_reg_offset, addr);
+ if (match_reg_offset == RCM_BSSID_OFFSET)
+ memcpy(wlc->cfg->BSSID, addr, ETH_ALEN);
+}
+
+void wlc_pllreq(struct wlc_info *wlc, bool set, mbool req_bit)
+{
+ wlc_bmac_pllreq(wlc->hw, set, req_bit);
+}
+
+void wlc_reset_bmac_done(struct wlc_info *wlc)
+{
+}
+
+/* check for the particular priority flow control bit being set */
+bool
+wlc_txflowcontrol_prio_isset(struct wlc_info *wlc, struct wlc_txq_info *q,
+ int prio)
+{
+ uint prio_mask;
+
+ if (prio == ALLPRIO) {
+ prio_mask = TXQ_STOP_FOR_PRIOFC_MASK;
+ } else {
+ prio_mask = NBITVAL(prio);
+ }
+
+ return (q->stopped & prio_mask) == prio_mask;
+}
+
+/* propagate the flow control to all interfaces using the given tx queue */
+void wlc_txflowcontrol(struct wlc_info *wlc, struct wlc_txq_info *qi,
+ bool on, int prio)
+{
+ uint prio_bits;
+ uint cur_bits;
+
+ BCMMSG(wlc->wiphy, "flow control kicks in\n");
+
+ if (prio == ALLPRIO) {
+ prio_bits = TXQ_STOP_FOR_PRIOFC_MASK;
+ } else {
+ prio_bits = NBITVAL(prio);
+ }
+
+ cur_bits = qi->stopped & prio_bits;
+
+ /* Check for the case of no change and return early
+ * Otherwise update the bit and continue
+ */
+ if (on) {
+ if (cur_bits == prio_bits) {
+ return;
+ }
+ mboolset(qi->stopped, prio_bits);
+ } else {
+ if (cur_bits == 0) {
+ return;
+ }
+ mboolclr(qi->stopped, prio_bits);
+ }
+
+ /* If there is a flow control override we will not change the external
+ * flow control state.
+ */
+ if (qi->stopped & ~TXQ_STOP_FOR_PRIOFC_MASK) {
+ return;
+ }
+
+ wlc_txflowcontrol_signal(wlc, qi, on, prio);
+}
+
+void
+wlc_txflowcontrol_override(struct wlc_info *wlc, struct wlc_txq_info *qi,
+ bool on, uint override)
+{
+ uint prev_override;
+
+ prev_override = (qi->stopped & ~TXQ_STOP_FOR_PRIOFC_MASK);
+
+ /* Update the flow control bits and do an early return if there is
+ * no change in the external flow control state.
+ */
+ if (on) {
+ mboolset(qi->stopped, override);
+ /* if there was a previous override bit on, then setting this
+ * makes no difference.
+ */
+ if (prev_override) {
+ return;
+ }
+
+ wlc_txflowcontrol_signal(wlc, qi, ON, ALLPRIO);
+ } else {
+ mboolclr(qi->stopped, override);
+ /* clearing an override bit will only make a difference for
+ * flow control if it was the only bit set. For any other
+ * override setting, just return
+ */
+ if (prev_override != override) {
+ return;
+ }
+
+ if (qi->stopped == 0) {
+ wlc_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
+ } else {
+ int prio;
+
+ for (prio = MAXPRIO; prio >= 0; prio--) {
+ if (!mboolisset(qi->stopped, NBITVAL(prio)))
+ wlc_txflowcontrol_signal(wlc, qi, OFF,
+ prio);
+ }
+ }
+ }
+}
+
+static void wlc_txflowcontrol_reset(struct wlc_info *wlc)
+{
+ struct wlc_txq_info *qi;
+
+ for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
+ if (qi->stopped) {
+ wlc_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
+ qi->stopped = 0;
+ }
+ }
+}
+
+static void
+wlc_txflowcontrol_signal(struct wlc_info *wlc, struct wlc_txq_info *qi, bool on,
+ int prio)
+{
+#ifdef NON_FUNCTIONAL
+ /* wlcif_list is never filled so this function is not functional */
+ struct wlc_if *wlcif;
+
+ for (wlcif = wlc->wlcif_list; wlcif != NULL; wlcif = wlcif->next) {
+ if (wlcif->qi == qi && wlcif->flags & WLC_IF_LINKED)
+ brcms_txflowcontrol(wlc->wl, wlcif->wlif, on, prio);
+ }
+#endif
+}
+
+static struct wlc_txq_info *wlc_txq_alloc(struct wlc_info *wlc)
+{
+ struct wlc_txq_info *qi, *p;
+
+ qi = kzalloc(sizeof(struct wlc_txq_info), GFP_ATOMIC);
+ if (qi != NULL) {
+ /*
+ * Have enough room for control packets along with HI watermark
+ * Also, add room to txq for total psq packets if all the SCBs
+ * leave PS mode. The watermark for flowcontrol to OS packets
+ * will remain the same
+ */
+ brcmu_pktq_init(&qi->q, WLC_PREC_COUNT,
+ (2 * wlc->pub->tunables->datahiwat) + PKTQ_LEN_DEFAULT
+ + wlc->pub->psq_pkts_total);
+
+ /* add this queue to the the global list */
+ p = wlc->tx_queues;
+ if (p == NULL) {
+ wlc->tx_queues = qi;
+ } else {
+ while (p->next != NULL)
+ p = p->next;
+ p->next = qi;
+ }
+ }
+ return qi;
+}
+
+static void wlc_txq_free(struct wlc_info *wlc, struct wlc_txq_info *qi)
+{
+ struct wlc_txq_info *p;
+
+ if (qi == NULL)
+ return;
+
+ /* remove the queue from the linked list */
+ p = wlc->tx_queues;
+ if (p == qi)
+ wlc->tx_queues = p->next;
+ else {
+ while (p != NULL && p->next != qi)
+ p = p->next;
+ if (p != NULL)
+ p->next = p->next->next;
+ }
+
+ kfree(qi);
+}
+
+/*
+ * Flag 'scan in progress' to withhold dynamic phy calibration
+ */
+void wlc_scan_start(struct wlc_info *wlc)
+{
+ wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
+}
+
+void wlc_scan_stop(struct wlc_info *wlc)
+{
+ wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
+}
+
+void wlc_associate_upd(struct wlc_info *wlc, bool state)
+{
+ wlc->pub->associated = state;
+ wlc->cfg->associated = state;
+}
+
+/*
+ * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
+ * AMPDU traffic, packets pending in hardware have to be invalidated so that
+ * when later on hardware releases them, they can be handled appropriately.
+ */
+void wlc_inval_dma_pkts(struct wlc_hw_info *hw,
+ struct ieee80211_sta *sta,
+ void (*dma_callback_fn))
+{
+ struct dma_pub *dmah;
+ int i;
+ for (i = 0; i < NFIFO; i++) {
+ dmah = hw->di[i];
+ if (dmah != NULL)
+ dma_walk_packets(dmah, dma_callback_fn, sta);
+ }
+}
+
+int wlc_get_curband(struct wlc_info *wlc)
+{
+ return wlc->band->bandunit;
+}
+
+void wlc_wait_for_tx_completion(struct wlc_info *wlc, bool drop)
+{
+ /* flush packet queue when requested */
+ if (drop)
+ brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
+
+ /* wait for queue and DMA fifos to run dry */
+ while (!pktq_empty(&wlc->pkt_queue->q) ||
+ TXPKTPENDTOT(wlc) > 0) {
+ brcms_msleep(wlc->wl, 1);
+ }
+}
+
+int wlc_set_par(struct wlc_info *wlc, enum wlc_par_id par_id, int int_val)
+{
+ int err = 0;
+
+ switch (par_id) {
+ case IOV_BCN_LI_BCN:
+ wlc->bcn_li_bcn = (u8) int_val;
+ if (wlc->pub->up)
+ wlc_bcn_li_upd(wlc);
+ break;
+ /* As long as override is false, this only sets the *user*
+ targets. User can twiddle this all he wants with no harm.
+ wlc_phy_txpower_set() explicitly sets override to false if
+ not internal or test.
+ */
+ case IOV_QTXPOWER:{
+ u8 qdbm;
+ bool override;
+
+ /* Remove override bit and clip to max qdbm value */
+ qdbm = (u8)min_t(u32, (int_val & ~WL_TXPWR_OVERRIDE), 0xff);
+ /* Extract override setting */
+ override = (int_val & WL_TXPWR_OVERRIDE) ? true : false;
+ err =
+ wlc_phy_txpower_set(wlc->band->pi, qdbm, override);
+ break;
+ }
+ case IOV_MPC:
+ wlc->mpc = (bool)int_val;
+ wlc_radio_mpc_upd(wlc);
+ break;
+ default:
+ err = -ENOTSUPP;
+ }
+ return err;
+}
+
+int wlc_get_par(struct wlc_info *wlc, enum wlc_par_id par_id, int *ret_int_ptr)
+{
+ int err = 0;
+
+ switch (par_id) {
+ case IOV_BCN_LI_BCN:
+ *ret_int_ptr = wlc->bcn_li_bcn;
+ break;
+ case IOV_QTXPOWER: {
+ uint qdbm;
+ bool override;
+
+ err = wlc_phy_txpower_get(wlc->band->pi, &qdbm,
+ &override);
+ if (err != 0)
+ return err;
+
+ /* Return qdbm units */
+ *ret_int_ptr =
+ qdbm | (override ? WL_TXPWR_OVERRIDE : 0);
+ break;
+ }
+ case IOV_MPC:
+ *ret_int_ptr = (s32) wlc->mpc;
+ break;
+ default:
+ err = -ENOTSUPP;
+ }
+ return err;
+}
+
+/*
+ * Search the name=value vars for a specific one and return its value.
+ * Returns NULL if not found.
+ */
+char *getvar(char *vars, const char *name)
+{
+ char *s;
+ int len;
+
+ if (!name)
+ return NULL;
+
+ len = strlen(name);
+ if (len == 0)
+ return NULL;
+
+ /* first look in vars[] */
+ for (s = vars; s && *s;) {
+ if ((memcmp(s, name, len) == 0) && (s[len] == '='))
+ return &s[len + 1];
+
+ while (*s++)
+ ;
+ }
+ /* nothing found */
+ return NULL;
+}
+
+/*
+ * Search the vars for a specific one and return its value as
+ * an integer. Returns 0 if not found.
+ */
+int getintvar(char *vars, const char *name)
+{
+ char *val;
+
+ val = getvar(vars, name);
+ if (val == NULL)
+ return 0;
+
+ return simple_strtoul(val, NULL, 0);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_MAIN_H_
+#define _BRCM_MAIN_H_
+
+#define MA_WINDOW_SZ 8 /* moving average window size */
+#define WL_HWRXOFF 38 /* chip rx buffer offset */
+#define INVCHANNEL 255 /* invalid channel */
+#define MAXCOREREV 28 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
+#define WLC_MAXMODULES 22 /* max # wlc_module_register() calls */
+
+#define SEQNUM_SHIFT 4
+#define AMPDU_DELIMITER_LEN 4
+#define SEQNUM_MAX 0x1000
+
+#define APHY_CWMIN 15
+#define PHY_CWMAX 1023
+
+#define EDCF_AIFSN_MIN 1
+#define FRAGNUM_MASK 0xF
+
+#define WLC_BITSCNT(x) brcmu_bitcount((u8 *)&(x), sizeof(u8))
+
+/* Maximum wait time for a MAC suspend */
+#define WLC_MAX_MAC_SUSPEND 83000 /* uS: 83mS is max packet time (64KB ampdu @ 6Mbps) */
+
+/* Probe Response timeout - responses for probe requests older that this are tossed, zero to disable
+ */
+#define WLC_PRB_RESP_TIMEOUT 0 /* Disable probe response timeout */
+
+/* transmit buffer max headroom for protocol headers */
+#define TXOFF (D11_TXH_LEN + D11_PHY_HDR_LEN)
+
+#define AC_COUNT 4
+
+/* Macros for doing definition and get/set of bitfields
+ * Usage example, e.g. a three-bit field (bits 4-6):
+ * #define <NAME>_M BITFIELD_MASK(3)
+ * #define <NAME>_S 4
+ * ...
+ * regval = R_REG(osh, ®s->regfoo);
+ * field = GFIELD(regval, <NAME>);
+ * regval = SFIELD(regval, <NAME>, 1);
+ * W_REG(osh, ®s->regfoo, regval);
+ */
+#define BITFIELD_MASK(width) \
+ (((unsigned)1 << (width)) - 1)
+#define GFIELD(val, field) \
+ (((val) >> field ## _S) & field ## _M)
+#define SFIELD(val, field, bits) \
+ (((val) & (~(field ## _M << field ## _S))) | \
+ ((unsigned)(bits) << field ## _S))
+
+/* For managing scan result lists */
+struct wlc_bss_list {
+ uint count;
+ bool beacon; /* set for beacon, cleared for probe response */
+ wlc_bss_info_t *ptrs[MAXBSS];
+};
+
+#define SW_TIMER_MAC_STAT_UPD 30 /* periodic MAC stats update */
+
+/* Double check that unsupported cores are not enabled */
+#if CONF_MSK(D11CONF, 0x4f) || CONF_GE(D11CONF, MAXCOREREV)
+#error "Configuration for D11CONF includes unsupported versions."
+#endif /* Bad versions */
+
+#define VALID_COREREV(corerev) CONF_HAS(D11CONF, corerev)
+
+/* values for shortslot_override */
+#define WLC_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
+#define WLC_SHORTSLOT_OFF 0 /* Turn off short slot */
+#define WLC_SHORTSLOT_ON 1 /* Turn on short slot */
+
+/* value for short/long and mixmode/greenfield preamble */
+
+#define WLC_LONG_PREAMBLE (0)
+#define WLC_SHORT_PREAMBLE (1 << 0)
+#define WLC_GF_PREAMBLE (1 << 1)
+#define WLC_MM_PREAMBLE (1 << 2)
+#define WLC_IS_MIMO_PREAMBLE(_pre) (((_pre) == WLC_GF_PREAMBLE) || ((_pre) == WLC_MM_PREAMBLE))
+
+/* values for barker_preamble */
+#define WLC_BARKER_SHORT_ALLOWED 0 /* Short pre-amble allowed */
+
+/* A fifo is full. Clear precedences related to that FIFO */
+#define WLC_TX_FIFO_CLEAR(wlc, fifo) ((wlc)->tx_prec_map &= ~(wlc)->fifo2prec_map[fifo])
+
+/* Fifo is NOT full. Enable precedences for that FIFO */
+#define WLC_TX_FIFO_ENAB(wlc, fifo) ((wlc)->tx_prec_map |= (wlc)->fifo2prec_map[fifo])
+
+/* TxFrameID */
+/* seq and frag bits: SEQNUM_SHIFT, FRAGNUM_MASK (802.11.h) */
+/* rate epoch bits: TXFID_RATE_SHIFT, TXFID_RATE_MASK ((wlc_rate.c) */
+#define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
+#define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
+#define TXFID_SEQ_SHIFT 5 /* Number of bit shifts */
+#define TXFID_RATE_PROBE_MASK 0x8000 /* Bit 15 for rate probe */
+#define TXFID_RATE_MASK 0x0018 /* Mask for bits 3 and 4 */
+#define TXFID_RATE_SHIFT 3 /* Shift 3 bits for rate mask */
+
+/* promote boardrev */
+#define BOARDREV_PROMOTABLE 0xFF /* from */
+#define BOARDREV_PROMOTED 1 /* to */
+
+/* if wpa is in use then portopen is true when the group key is plumbed otherwise it is always true
+ */
+#define WSEC_ENABLED(wsec) ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
+#define WLC_SW_KEYS(wlc, bsscfg) ((((wlc)->wsec_swkeys) || \
+ ((bsscfg)->wsec & WSEC_SWFLAG)))
+
+#define WLC_PORTOPEN(cfg) \
+ (((cfg)->WPA_auth != WPA_AUTH_DISABLED && WSEC_ENABLED((cfg)->wsec)) ? \
+ (cfg)->wsec_portopen : true)
+
+#define PS_ALLOWED(wlc) wlc_ps_allowed(wlc)
+
+#define DATA_BLOCK_TX_SUPR (1 << 4)
+
+/* 802.1D Priority to TX FIFO number for wme */
+extern const u8 prio2fifo[];
+
+/* Ucode MCTL_WAKE override bits */
+#define WLC_WAKE_OVERRIDE_CLKCTL 0x01
+#define WLC_WAKE_OVERRIDE_PHYREG 0x02
+#define WLC_WAKE_OVERRIDE_MACSUSPEND 0x04
+#define WLC_WAKE_OVERRIDE_TXFIFO 0x08
+#define WLC_WAKE_OVERRIDE_FORCEFAST 0x10
+
+/* stuff pulled in from wlc.c */
+
+/* Interrupt bit error summary. Don't include I_RU: we refill DMA at other
+ * times; and if we run out, constant I_RU interrupts may cause lockup. We
+ * will still get error counts from rx0ovfl.
+ */
+#define I_ERRORS (I_PC | I_PD | I_DE | I_RO | I_XU)
+/* default software intmasks */
+#define DEF_RXINTMASK (I_RI) /* enable rx int on rxfifo only */
+#define DEF_MACINTMASK (MI_TXSTOP | MI_TBTT | MI_ATIMWINEND | MI_PMQ | \
+ MI_PHYTXERR | MI_DMAINT | MI_TFS | MI_BG_NOISE | \
+ MI_CCA | MI_TO | MI_GP0 | MI_RFDISABLE | MI_PWRUP)
+
+#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
+#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
+#define RETRY_LONG_DEF 4 /* Default Long retry count */
+#define RETRY_SHORT_FB 3 /* Short retry count for fallback rate */
+#define RETRY_LONG_FB 2 /* Long retry count for fallback rate */
+
+#define MAXTXPKTS 6 /* max # pkts pending */
+
+/* frameburst */
+#define MAXTXFRAMEBURST 8 /* vanilla xpress mode: max frames/burst */
+#define MAXFRAMEBURST_TXOP 10000 /* Frameburst TXOP in usec */
+
+/* Per-AC retry limit register definitions; uses defs.h bitfield macros */
+#define EDCF_SHORT_S 0
+#define EDCF_SFB_S 4
+#define EDCF_LONG_S 8
+#define EDCF_LFB_S 12
+#define EDCF_SHORT_M BITFIELD_MASK(4)
+#define EDCF_SFB_M BITFIELD_MASK(4)
+#define EDCF_LONG_M BITFIELD_MASK(4)
+#define EDCF_LFB_M BITFIELD_MASK(4)
+
+#define NFIFO 6 /* # tx/rx fifopairs */
+
+#define WLC_WME_RETRY_SHORT_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_SHORT)
+#define WLC_WME_RETRY_SFB_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_SFB)
+#define WLC_WME_RETRY_LONG_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_LONG)
+#define WLC_WME_RETRY_LFB_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_LFB)
+
+#define WLC_WME_RETRY_SHORT_SET(wlc, ac, val) \
+ (wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], EDCF_SHORT, val))
+#define WLC_WME_RETRY_SFB_SET(wlc, ac, val) \
+ (wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], EDCF_SFB, val))
+#define WLC_WME_RETRY_LONG_SET(wlc, ac, val) \
+ (wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], EDCF_LONG, val))
+#define WLC_WME_RETRY_LFB_SET(wlc, ac, val) \
+ (wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], EDCF_LFB, val))
+
+/* PLL requests */
+#define WLC_PLLREQ_SHARED 0x1 /* pll is shared on old chips */
+#define WLC_PLLREQ_RADIO_MON 0x2 /* hold pll for radio monitor register checking */
+#define WLC_PLLREQ_FLIP 0x4 /* hold/release pll for some short operation */
+
+/*
+ * Macros to check if AP or STA is active.
+ * AP Active means more than just configured: driver and BSS are "up";
+ * that is, we are beaconing/responding as an AP (aps_associated).
+ * STA Active similarly means the driver is up and a configured STA BSS
+ * is up: either associated (stas_associated) or trying.
+ *
+ * Macro definitions vary as per AP/STA ifdefs, allowing references to
+ * ifdef'd structure fields and constant values (0) for optimization.
+ * Make sure to enclose blocks of code such that any routines they
+ * reference can also be unused and optimized out by the linker.
+ */
+/* NOTE: References structure fields defined in wlc.h */
+#define AP_ACTIVE(wlc) (0)
+
+/*
+ * Detect Card removed.
+ * Even checking an sbconfig register read will not false trigger when the core is in reset.
+ * it breaks CF address mechanism. Accessing gphy phyversion will cause SB error if aphy
+ * is in reset on 4306B0-DB. Need a simple accessible reg with fixed 0/1 pattern
+ * (some platforms return all 0).
+ * If clocks are present, call the sb routine which will figure out if the device is removed.
+ */
+#define DEVICEREMOVED(wlc) \
+ ((wlc->hw->clk) ? \
+ ((R_REG(&wlc->hw->regs->maccontrol) & \
+ (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN) : \
+ (ai_deviceremoved(wlc->hw->sih)))
+
+#define WLCWLUNIT(wlc) ((wlc)->pub->unit)
+
+struct wlc_protection {
+ bool _g; /* use g spec protection, driver internal */
+ s8 g_override; /* override for use of g spec protection */
+ u8 gmode_user; /* user config gmode, operating band->gmode is different */
+ s8 overlap; /* Overlap BSS/IBSS protection for both 11g and 11n */
+ s8 nmode_user; /* user config nmode, operating pub->nmode is different */
+ s8 n_cfg; /* use OFDM protection on MIMO frames */
+ s8 n_cfg_override; /* override for use of N protection */
+ bool nongf; /* non-GF present protection */
+ s8 nongf_override; /* override for use of GF protection */
+ s8 n_pam_override; /* override for preamble: MM or GF */
+ bool n_obss; /* indicated OBSS Non-HT STA present */
+};
+
+/* anything affects the single/dual streams/antenna operation */
+struct wlc_stf {
+ u8 hw_txchain; /* HW txchain bitmap cfg */
+ u8 txchain; /* txchain bitmap being used */
+ u8 txstreams; /* number of txchains being used */
+
+ u8 hw_rxchain; /* HW rxchain bitmap cfg */
+ u8 rxchain; /* rxchain bitmap being used */
+ u8 rxstreams; /* number of rxchains being used */
+
+ u8 ant_rx_ovr; /* rx antenna override */
+ s8 txant; /* userTx antenna setting */
+ u16 phytxant; /* phyTx antenna setting in txheader */
+
+ u8 ss_opmode; /* singlestream Operational mode, 0:siso; 1:cdd */
+ bool ss_algosel_auto; /* if true, use wlc->stf->ss_algo_channel; */
+ /* else use wlc->band->stf->ss_mode_band; */
+ u16 ss_algo_channel; /* ss based on per-channel algo: 0: SISO, 1: CDD 2: STBC */
+ u8 no_cddstbc; /* stf override, 1: no CDD (or STBC) allowed */
+
+ u8 rxchain_restore_delay; /* delay time to restore default rxchain */
+
+ s8 ldpc; /* AUTO/ON/OFF ldpc cap supported */
+ u8 txcore[MAX_STREAMS_SUPPORTED + 1]; /* bitmap of selected core for each Nsts */
+ s8 spatial_policy;
+};
+
+#define WLC_STF_SS_STBC_TX(wlc, scb) \
+ (((wlc)->stf->txstreams > 1) && (((wlc)->band->band_stf_stbc_tx == ON) || \
+ (SCB_STBC_CAP((scb)) && \
+ (wlc)->band->band_stf_stbc_tx == AUTO && \
+ isset(&((wlc)->stf->ss_algo_channel), PHY_TXC1_MODE_STBC))))
+
+#define WLC_STBC_CAP_PHY(wlc) (WLCISNPHY(wlc->band) && NREV_GE(wlc->band->phyrev, 3))
+
+#define WLC_SGI_CAP_PHY(wlc) ((WLCISNPHY(wlc->band) && NREV_GE(wlc->band->phyrev, 3)) || \
+ WLCISLCNPHY(wlc->band))
+
+#define WLC_CHAN_PHYTYPE(x) (((x) & RXS_CHAN_PHYTYPE_MASK) >> RXS_CHAN_PHYTYPE_SHIFT)
+#define WLC_CHAN_CHANNEL(x) (((x) & RXS_CHAN_ID_MASK) >> RXS_CHAN_ID_SHIFT)
+#define WLC_RX_CHANNEL(rxh) (WLC_CHAN_CHANNEL((rxh)->RxChan))
+
+/* wlc_bss_info flag bit values */
+#define WLC_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
+
+/* Flags used in wlc_txq_info.stopped */
+#define TXQ_STOP_FOR_PRIOFC_MASK 0x000000FF /* per prio flow control bits */
+#define TXQ_STOP_FOR_PKT_DRAIN 0x00000100 /* stop txq enqueue for packet drain */
+#define TXQ_STOP_FOR_AMPDU_FLOW_CNTRL 0x00000200 /* stop txq enqueue for ampdu flow control */
+
+#define WLC_HT_WEP_RESTRICT 0x01 /* restrict HT with WEP */
+#define WLC_HT_TKIP_RESTRICT 0x02 /* restrict HT with TKIP */
+
+/*
+ * core state (mac)
+ */
+struct wlccore {
+ uint coreidx; /* # sb enumerated core */
+
+ /* fifo */
+ uint *txavail[NFIFO]; /* # tx descriptors available */
+ s16 txpktpend[NFIFO]; /* tx admission control */
+
+ macstat_t *macstat_snapshot; /* mac hw prev read values */
+};
+
+/*
+ * band state (phy+ana+radio)
+ */
+struct wlcband {
+ int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */
+ uint bandunit; /* bandstate[] index */
+
+ u16 phytype; /* phytype */
+ u16 phyrev;
+ u16 radioid;
+ u16 radiorev;
+ wlc_phy_t *pi; /* pointer to phy specific information */
+ bool abgphy_encore;
+
+ u8 gmode; /* currently active gmode */
+
+ struct scb *hwrs_scb; /* permanent scb for hw rateset */
+
+ wlc_rateset_t defrateset; /* band-specific copy of default_bss.rateset */
+
+ ratespec_t rspec_override; /* 802.11 rate override */
+ ratespec_t mrspec_override; /* multicast rate override */
+ u8 band_stf_ss_mode; /* Configured STF type, 0:siso; 1:cdd */
+ s8 band_stf_stbc_tx; /* STBC TX 0:off; 1:force on; -1:auto */
+ wlc_rateset_t hw_rateset; /* rates supported by chip (phy-specific) */
+ u8 basic_rate[WLC_MAXRATE + 1]; /* basic rates indexed by rate */
+ bool mimo_cap_40; /* 40 MHz cap enabled on this band */
+ s8 antgain; /* antenna gain from srom */
+
+ u16 CWmin; /* The minimum size of contention window, in unit of aSlotTime */
+ u16 CWmax; /* The maximum size of contention window, in unit of aSlotTime */
+ u16 bcntsfoff; /* beacon tsf offset */
+};
+
+/* tx completion callback takes 3 args */
+typedef void (*pkcb_fn_t) (struct wlc_info *wlc, uint txstatus, void *arg);
+
+struct pkt_cb {
+ pkcb_fn_t fn; /* function to call when tx frame completes */
+ void *arg; /* void arg for fn */
+ u8 nextidx; /* index of next call back if threading */
+ bool entered; /* recursion check */
+};
+
+/* module control blocks */
+struct modulecb {
+ char name[32]; /* module name : NULL indicates empty array member */
+ const struct brcmu_iovar *iovars; /* iovar table */
+ void *hdl; /* handle passed when handler 'doiovar' is called */
+ watchdog_fn_t watchdog_fn; /* watchdog handler */
+ iovar_fn_t iovar_fn; /* iovar handler */
+ down_fn_t down_fn; /* down handler. Note: the int returned
+ * by the down function is a count of the
+ * number of timers that could not be
+ * freed.
+ */
+};
+
+/* dump control blocks */
+struct dumpcb_s {
+ const char *name; /* dump name */
+ dump_fn_t dump_fn; /* 'wl dump' handler */
+ void *dump_fn_arg;
+ struct dumpcb_s *next;
+};
+
+struct edcf_acparam {
+ u8 ACI;
+ u8 ECW;
+ u16 TXOP;
+} __attribute__((packed));
+typedef struct edcf_acparam edcf_acparam_t;
+
+struct wme_param_ie {
+ u8 oui[3];
+ u8 type;
+ u8 subtype;
+ u8 version;
+ u8 qosinfo;
+ u8 rsvd;
+ edcf_acparam_t acparam[AC_COUNT];
+} __attribute__((packed));
+typedef struct wme_param_ie wme_param_ie_t;
+
+/* virtual interface */
+struct wlc_if {
+ struct wlc_if *next;
+ u8 type; /* WLC_IFTYPE_BSS or WLC_IFTYPE_WDS */
+ u8 index; /* assigned in wl_add_if(), index of the wlif if any,
+ * not necessarily corresponding to bsscfg._idx or
+ * AID2PVBMAP(scb).
+ */
+ u8 flags; /* flags for the interface */
+ struct brcms_if *wlif; /* pointer to wlif */
+ struct wlc_txq_info *qi; /* pointer to associated tx queue */
+ union {
+ struct scb *scb; /* pointer to scb if WLC_IFTYPE_WDS */
+ struct wlc_bsscfg *bsscfg; /* pointer to bsscfg if WLC_IFTYPE_BSS */
+ } u;
+};
+
+/* flags for the interface, this interface is linked to a brcms_if */
+#define WLC_IF_LINKED 0x02
+
+struct wlc_hwband {
+ int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */
+ uint bandunit; /* bandstate[] index */
+ u16 mhfs[MHFMAX]; /* MHF array shadow */
+ u8 bandhw_stf_ss_mode; /* HW configured STF type, 0:siso; 1:cdd */
+ u16 CWmin;
+ u16 CWmax;
+ u32 core_flags;
+
+ u16 phytype; /* phytype */
+ u16 phyrev;
+ u16 radioid;
+ u16 radiorev;
+ wlc_phy_t *pi; /* pointer to phy specific information */
+ bool abgphy_encore;
+};
+
+struct wlc_hw_info {
+ bool _piomode; /* true if pio mode */
+ struct wlc_info *wlc;
+
+ /* fifo */
+ struct dma_pub *di[NFIFO]; /* dma handles, per fifo */
+
+ uint unit; /* device instance number */
+
+ /* version info */
+ u16 vendorid; /* PCI vendor id */
+ u16 deviceid; /* PCI device id */
+ uint corerev; /* core revision */
+ u8 sromrev; /* version # of the srom */
+ u16 boardrev; /* version # of particular board */
+ u32 boardflags; /* Board specific flags from srom */
+ u32 boardflags2; /* More board flags if sromrev >= 4 */
+ u32 machwcap; /* MAC capabilities */
+ u32 machwcap_backup; /* backup of machwcap */
+ u16 ucode_dbgsel; /* dbgsel for ucode debug(config gpio) */
+
+ struct si_pub *sih; /* SI handle (cookie for siutils calls) */
+ char *vars; /* "environment" name=value */
+ uint vars_size; /* size of vars, free vars on detach */
+ d11regs_t *regs; /* pointer to device registers */
+ void *physhim; /* phy shim layer handler */
+ void *phy_sh; /* pointer to shared phy state */
+ struct wlc_hwband *band;/* pointer to active per-band state */
+ struct wlc_hwband *bandstate[MAXBANDS];/* band state per phy/radio */
+ u16 bmac_phytxant; /* cache of high phytxant state */
+ bool shortslot; /* currently using 11g ShortSlot timing */
+ u16 SRL; /* 802.11 dot11ShortRetryLimit */
+ u16 LRL; /* 802.11 dot11LongRetryLimit */
+ u16 SFBL; /* Short Frame Rate Fallback Limit */
+ u16 LFBL; /* Long Frame Rate Fallback Limit */
+
+ bool up; /* d11 hardware up and running */
+ uint now; /* # elapsed seconds */
+ uint _nbands; /* # bands supported */
+ chanspec_t chanspec; /* bmac chanspec shadow */
+
+ uint *txavail[NFIFO]; /* # tx descriptors available */
+ u16 *xmtfifo_sz; /* fifo size in 256B for each xmt fifo */
+
+ mbool pllreq; /* pll requests to keep PLL on */
+
+ u8 suspended_fifos; /* Which TX fifo to remain awake for */
+ u32 maccontrol; /* Cached value of maccontrol */
+ uint mac_suspend_depth; /* current depth of mac_suspend levels */
+ u32 wake_override; /* Various conditions to force MAC to WAKE mode */
+ u32 mute_override; /* Prevent ucode from sending beacons */
+ u8 etheraddr[ETH_ALEN]; /* currently configured ethernet address */
+ u32 led_gpio_mask; /* LED GPIO Mask */
+ bool noreset; /* true= do not reset hw, used by WLC_OUT */
+ bool forcefastclk; /* true if the h/w is forcing the use of fast clk */
+ bool clk; /* core is out of reset and has clock */
+ bool sbclk; /* sb has clock */
+ struct bmac_pmq *bmac_pmq; /* bmac PM states derived from ucode PMQ */
+ bool phyclk; /* phy is out of reset and has clock */
+ bool dma_lpbk; /* core is in DMA loopback */
+
+ bool ucode_loaded; /* true after ucode downloaded */
+
+
+ u8 hw_stf_ss_opmode; /* STF single stream operation mode */
+ u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic
+ * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
+ */
+ u32 antsel_avail; /*
+ * put struct antsel_info here if more info is
+ * needed
+ */
+};
+
+/* TX Queue information
+ *
+ * Each flow of traffic out of the device has a TX Queue with independent
+ * flow control. Several interfaces may be associated with a single TX Queue
+ * if they belong to the same flow of traffic from the device. For multi-channel
+ * operation there are independent TX Queues for each channel.
+ */
+struct wlc_txq_info {
+ struct wlc_txq_info *next;
+ struct pktq q;
+ uint stopped; /* tx flow control bits */
+};
+
+/*
+ * Principal common (os-independent) software data structure.
+ */
+struct wlc_info {
+ struct wlc_pub *pub; /* pointer to wlc public state */
+ struct brcms_info *wl; /* pointer to os-specific private state */
+ d11regs_t *regs; /* pointer to device registers */
+
+ struct wlc_hw_info *hw; /* HW related state used primarily by BMAC */
+
+ /* clock */
+ int clkreq_override; /* setting for clkreq for PCIE : Auto, 0, 1 */
+ u16 fastpwrup_dly; /* time in us needed to bring up d11 fast clock */
+
+ /* interrupt */
+ u32 macintstatus; /* bit channel between isr and dpc */
+ u32 macintmask; /* sw runtime master macintmask value */
+ u32 defmacintmask; /* default "on" macintmask value */
+
+ /* up and down */
+ bool device_present; /* (removable) device is present */
+
+ bool clk; /* core is out of reset and has clock */
+
+ /* multiband */
+ struct wlccore *core; /* pointer to active io core */
+ struct wlcband *band; /* pointer to active per-band state */
+ struct wlccore *corestate; /* per-core state (one per hw core) */
+ /* per-band state (one per phy/radio): */
+ struct wlcband *bandstate[MAXBANDS];
+
+ bool war16165; /* PCI slow clock 16165 war flag */
+
+ bool tx_suspended; /* data fifos need to remain suspended */
+
+ uint txpend16165war;
+
+ /* packet queue */
+ uint qvalid; /* DirFrmQValid and BcMcFrmQValid */
+
+ /* Regulatory power limits */
+ s8 txpwr_local_max; /* regulatory local txpwr max */
+ u8 txpwr_local_constraint; /* local power contraint in dB */
+
+
+ struct ampdu_info *ampdu; /* ampdu module handler */
+ struct antsel_info *asi; /* antsel module handler */
+ wlc_cm_info_t *cmi; /* channel manager module handler */
+
+ uint vars_size; /* size of vars, free vars on detach */
+
+ u16 vendorid; /* PCI vendor id */
+ u16 deviceid; /* PCI device id */
+ uint ucode_rev; /* microcode revision */
+
+ u32 machwcap; /* MAC capabilities, BMAC shadow */
+
+ u8 perm_etheraddr[ETH_ALEN]; /* original sprom local ethernet address */
+
+ bool bandlocked; /* disable auto multi-band switching */
+ bool bandinit_pending; /* track band init in auto band */
+
+ bool radio_monitor; /* radio timer is running */
+ bool going_down; /* down path intermediate variable */
+
+ bool mpc; /* enable minimum power consumption */
+ u8 mpc_dlycnt; /* # of watchdog cnt before turn disable radio */
+ u8 mpc_offcnt; /* # of watchdog cnt that radio is disabled */
+ u8 mpc_delay_off; /* delay radio disable by # of watchdog cnt */
+ u8 prev_non_delay_mpc; /* prev state wlc_is_non_delay_mpc */
+
+ /* timer for watchdog routine */
+ struct brcms_timer *wdtimer;
+ /* timer for hw radio button monitor routine */
+ struct brcms_timer *radio_timer;
+
+ /* promiscuous */
+ bool monitor; /* monitor (MPDU sniffing) mode */
+ bool bcnmisc_ibss; /* bcns promisc mode override for IBSS */
+ bool bcnmisc_scan; /* bcns promisc mode override for scan */
+ bool bcnmisc_monitor; /* bcns promisc mode override for monitor */
+
+ /* driver feature */
+ bool _rifs; /* enable per-packet rifs */
+ s8 sgi_tx; /* sgi tx */
+
+ /* AP-STA synchronization, power save */
+ u8 bcn_li_bcn; /* beacon listen interval in # beacons */
+ u8 bcn_li_dtim; /* beacon listen interval in # dtims */
+
+ bool WDarmed; /* watchdog timer is armed */
+ u32 WDlast; /* last time wlc_watchdog() was called */
+
+ /* WME */
+ ac_bitmap_t wme_dp; /* Discard (oldest first) policy per AC */
+ u16 edcf_txop[AC_COUNT]; /* current txop for each ac */
+ wme_param_ie_t wme_param_ie; /* WME parameter info element, which on STA
+ * contains parameters in use locally, and on
+ * AP contains parameters advertised to STA
+ * in beacons and assoc responses.
+ */
+ u16 wme_retries[AC_COUNT]; /* per-AC retry limits */
+
+ u16 tx_prec_map; /* Precedence map based on HW FIFO space */
+ u16 fifo2prec_map[NFIFO]; /* pointer to fifo2_prec map based on WME */
+
+ /*
+ * BSS Configurations set of BSS configurations, idx 0 is default and
+ * always valid
+ */
+ struct wlc_bsscfg *bsscfg[WLC_MAXBSSCFG];
+ struct wlc_bsscfg *cfg; /* the primary bsscfg (can be AP or STA) */
+
+ /* tx queue */
+ struct wlc_txq_info *tx_queues; /* common TX Queue list */
+
+ /* security */
+ wsec_key_t *wsec_keys[WSEC_MAX_KEYS]; /* dynamic key storage */
+ wsec_key_t *wsec_def_keys[WLC_DEFAULT_KEYS]; /* default key storage */
+ bool wsec_swkeys; /* indicates that all keys should be
+ * treated as sw keys (used for debugging)
+ */
+ struct modulecb *modulecb;
+
+ u8 mimoft; /* SIGN or 11N */
+ s8 cck_40txbw; /* 11N, cck tx b/w override when in 40MHZ mode */
+ s8 ofdm_40txbw; /* 11N, ofdm tx b/w override when in 40MHZ mode */
+ s8 mimo_40txbw; /* 11N, mimo tx b/w override when in 40MHZ mode */
+ /* HT CAP IE being advertised by this node: */
+ struct ieee80211_ht_cap ht_cap;
+
+ wlc_bss_info_t *default_bss; /* configured BSS parameters */
+
+ u16 mc_fid_counter; /* BC/MC FIFO frame ID counter */
+
+ char country_default[WLC_CNTRY_BUF_SZ]; /* saved country for leaving 802.11d
+ * auto-country mode
+ */
+ char autocountry_default[WLC_CNTRY_BUF_SZ]; /* initial country for 802.11d
+ * auto-country mode
+ */
+ u16 prb_resp_timeout; /* do not send prb resp if request older than this,
+ * 0 = disable
+ */
+
+ wlc_rateset_t sup_rates_override; /* use only these rates in 11g supported rates if
+ * specifed
+ */
+
+ chanspec_t home_chanspec; /* shared home chanspec */
+
+ /* PHY parameters */
+ chanspec_t chanspec; /* target operational channel */
+ u16 usr_fragthresh; /* user configured fragmentation threshold */
+ u16 fragthresh[NFIFO]; /* per-fifo fragmentation thresholds */
+ u16 RTSThresh; /* 802.11 dot11RTSThreshold */
+ u16 SRL; /* 802.11 dot11ShortRetryLimit */
+ u16 LRL; /* 802.11 dot11LongRetryLimit */
+ u16 SFBL; /* Short Frame Rate Fallback Limit */
+ u16 LFBL; /* Long Frame Rate Fallback Limit */
+
+ /* network config */
+ bool shortslot; /* currently using 11g ShortSlot timing */
+ s8 shortslot_override; /* 11g ShortSlot override */
+ bool include_legacy_erp; /* include Legacy ERP info elt ID 47 as well as g ID 42 */
+
+ struct wlc_protection *protection;
+ s8 PLCPHdr_override; /* 802.11b Preamble Type override */
+
+ struct wlc_stf *stf;
+
+ ratespec_t bcn_rspec; /* save bcn ratespec purpose */
+
+ uint tempsense_lasttime;
+
+ u16 tx_duty_cycle_ofdm; /* maximum allowed duty cycle for OFDM */
+ u16 tx_duty_cycle_cck; /* maximum allowed duty cycle for CCK */
+
+ u16 next_bsscfg_ID;
+
+ struct wlc_txq_info *pkt_queue; /* txq for transmit packets */
+ u32 mpc_dur; /* total time (ms) in mpc mode except for the
+ * portion since radio is turned off last time
+ */
+ u32 mpc_laston_ts; /* timestamp (ms) when radio is turned off last
+ * time
+ */
+ struct wiphy *wiphy;
+};
+
+/* antsel module specific state */
+struct antsel_info {
+ struct wlc_info *wlc; /* pointer to main wlc structure */
+ struct wlc_pub *pub; /* pointer to public fn */
+ u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic
+ * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
+ */
+ u8 antsel_antswitch; /* board level antenna switch type */
+ bool antsel_avail; /* Ant selection availability (SROM based) */
+ wlc_antselcfg_t antcfg_11n; /* antenna configuration */
+ wlc_antselcfg_t antcfg_cur; /* current antenna config (auto) */
+};
+
+#define CHANNEL_BANDUNIT(wlc, ch) (((ch) <= CH_MAX_2G_CHANNEL) ? BAND_2G_INDEX : BAND_5G_INDEX)
+#define OTHERBANDUNIT(wlc) ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
+
+#define IS_MBAND_UNLOCKED(wlc) \
+ ((NBANDS(wlc) > 1) && !(wlc)->bandlocked)
+
+#define WLC_BAND_PI_RADIO_CHANSPEC wlc_phy_chanspec_get(wlc->band->pi)
+
+/* sum the individual fifo tx pending packet counts */
+#define TXPKTPENDTOT(wlc) ((wlc)->core->txpktpend[0] + (wlc)->core->txpktpend[1] + \
+ (wlc)->core->txpktpend[2] + (wlc)->core->txpktpend[3])
+#define TXPKTPENDGET(wlc, fifo) ((wlc)->core->txpktpend[(fifo)])
+#define TXPKTPENDINC(wlc, fifo, val) ((wlc)->core->txpktpend[(fifo)] += (val))
+#define TXPKTPENDDEC(wlc, fifo, val) ((wlc)->core->txpktpend[(fifo)] -= (val))
+#define TXPKTPENDCLR(wlc, fifo) ((wlc)->core->txpktpend[(fifo)] = 0)
+#define TXAVAIL(wlc, fifo) (*(wlc)->core->txavail[(fifo)])
+#define GETNEXTTXP(wlc, _queue) \
+ dma_getnexttxp((wlc)->hw->di[(_queue)], DMA_RANGE_TRANSMITTED)
+
+#define WLC_IS_MATCH_SSID(wlc, ssid1, ssid2, len1, len2) \
+ ((len1 == len2) && !memcmp(ssid1, ssid2, len1))
+
+extern void wlc_fatal_error(struct wlc_info *wlc);
+extern void wlc_bmac_rpc_watchdog(struct wlc_info *wlc);
+extern void wlc_recv(struct wlc_info *wlc, struct sk_buff *p);
+extern bool wlc_dotxstatus(struct wlc_info *wlc, tx_status_t *txs, u32 frm_tx2);
+extern void wlc_txfifo(struct wlc_info *wlc, uint fifo, struct sk_buff *p,
+ bool commit, s8 txpktpend);
+extern void wlc_txfifo_complete(struct wlc_info *wlc, uint fifo, s8 txpktpend);
+extern void wlc_txq_enq(void *ctx, struct scb *scb, struct sk_buff *sdu,
+ uint prec);
+extern void wlc_info_init(struct wlc_info *wlc, int unit);
+extern void wlc_print_txstatus(tx_status_t *txs);
+extern int wlc_xmtfifo_sz_get(struct wlc_info *wlc, uint fifo, uint *blocks);
+extern void wlc_write_template_ram(struct wlc_info *wlc, int offset, int len,
+ void *buf);
+extern void wlc_write_hw_bcntemplates(struct wlc_info *wlc, void *bcn, int len,
+ bool both);
+extern void wlc_pllreq(struct wlc_info *wlc, bool set, mbool req_bit);
+extern void wlc_reset_bmac_done(struct wlc_info *wlc);
+
+#if defined(BCMDBG)
+extern void wlc_print_rxh(d11rxhdr_t *rxh);
+extern void wlc_print_hdrs(struct wlc_info *wlc, const char *prefix, u8 *frame,
+ d11txh_t *txh, d11rxhdr_t *rxh, uint len);
+extern void wlc_print_txdesc(d11txh_t *txh);
+#else
+#define wlc_print_txdesc(a)
+#endif
+#if defined(BCMDBG)
+extern void wlc_print_dot11_mac_hdr(u8 *buf, int len);
+#endif
+
+extern void wlc_setxband(struct wlc_hw_info *wlc_hw, uint bandunit);
+extern void wlc_coredisable(struct wlc_hw_info *wlc_hw);
+
+extern bool wlc_valid_rate(struct wlc_info *wlc, ratespec_t rate, int band,
+ bool verbose);
+extern void wlc_ap_upd(struct wlc_info *wlc);
+
+/* helper functions */
+extern void wlc_shm_ssid_upd(struct wlc_info *wlc, struct wlc_bsscfg *cfg);
+extern int wlc_set_gmode(struct wlc_info *wlc, u8 gmode, bool config);
+
+extern void wlc_mac_bcn_promisc_change(struct wlc_info *wlc, bool promisc);
+extern void wlc_mac_bcn_promisc(struct wlc_info *wlc);
+extern void wlc_mac_promisc(struct wlc_info *wlc);
+extern void wlc_txflowcontrol(struct wlc_info *wlc, struct wlc_txq_info *qi,
+ bool on, int prio);
+extern void wlc_txflowcontrol_override(struct wlc_info *wlc,
+ struct wlc_txq_info *qi,
+ bool on, uint override);
+extern bool wlc_txflowcontrol_prio_isset(struct wlc_info *wlc,
+ struct wlc_txq_info *qi, int prio);
+extern void wlc_send_q(struct wlc_info *wlc);
+extern int wlc_prep_pdu(struct wlc_info *wlc, struct sk_buff *pdu, uint *fifo);
+
+extern u16 wlc_calc_lsig_len(struct wlc_info *wlc, ratespec_t ratespec,
+ uint mac_len);
+extern ratespec_t wlc_rspec_to_rts_rspec(struct wlc_info *wlc, ratespec_t rspec,
+ bool use_rspec, u16 mimo_ctlchbw);
+extern u16 wlc_compute_rtscts_dur(struct wlc_info *wlc, bool cts_only,
+ ratespec_t rts_rate, ratespec_t frame_rate,
+ u8 rts_preamble_type,
+ u8 frame_preamble_type, uint frame_len,
+ bool ba);
+
+extern void wlc_tbtt(struct wlc_info *wlc, d11regs_t *regs);
+extern void wlc_inval_dma_pkts(struct wlc_hw_info *hw,
+ struct ieee80211_sta *sta,
+ void (*dma_callback_fn));
+
+#if defined(BCMDBG)
+extern void wlc_dump_ie(struct wlc_info *wlc, struct brcmu_tlv *ie,
+ struct brcmu_strbuf *b);
+#endif
+
+extern void wlc_reprate_init(struct wlc_info *wlc);
+extern void wlc_bsscfg_reprate_init(struct wlc_bsscfg *bsscfg);
+
+/* Shared memory access */
+extern void wlc_write_shm(struct wlc_info *wlc, uint offset, u16 v);
+extern u16 wlc_read_shm(struct wlc_info *wlc, uint offset);
+extern void wlc_copyto_shm(struct wlc_info *wlc, uint offset, const void *buf,
+ int len);
+
+extern void wlc_update_beacon(struct wlc_info *wlc);
+extern void wlc_bss_update_beacon(struct wlc_info *wlc,
+ struct wlc_bsscfg *bsscfg);
+
+extern void wlc_update_probe_resp(struct wlc_info *wlc, bool suspend);
+extern void wlc_bss_update_probe_resp(struct wlc_info *wlc,
+ struct wlc_bsscfg *cfg, bool suspend);
+
+extern bool wlc_ismpc(struct wlc_info *wlc);
+extern bool wlc_is_non_delay_mpc(struct wlc_info *wlc);
+extern void wlc_radio_mpc_upd(struct wlc_info *wlc);
+extern bool wlc_prec_enq(struct wlc_info *wlc, struct pktq *q, void *pkt,
+ int prec);
+extern bool wlc_prec_enq_head(struct wlc_info *wlc, struct pktq *q,
+ struct sk_buff *pkt, int prec, bool head);
+extern u16 wlc_phytxctl1_calc(struct wlc_info *wlc, ratespec_t rspec);
+extern void wlc_compute_plcp(struct wlc_info *wlc, ratespec_t rate, uint length,
+ u8 *plcp);
+extern uint wlc_calc_frame_time(struct wlc_info *wlc, ratespec_t ratespec,
+ u8 preamble_type, uint mac_len);
+
+extern void wlc_set_chanspec(struct wlc_info *wlc, chanspec_t chanspec);
+
+extern bool wlc_timers_init(struct wlc_info *wlc, int unit);
+
+#if defined(BCMDBG)
+extern void wlc_print_ies(struct wlc_info *wlc, u8 *ies, uint ies_len);
+#endif
+
+extern int wlc_set_nmode(struct wlc_info *wlc, s32 nmode);
+extern void wlc_mimops_action_ht_send(struct wlc_info *wlc,
+ struct wlc_bsscfg *bsscfg,
+ u8 mimops_mode);
+
+extern void wlc_switch_shortslot(struct wlc_info *wlc, bool shortslot);
+extern void wlc_set_bssid(struct wlc_bsscfg *cfg);
+extern void wlc_edcf_setparams(struct wlc_info *wlc, bool suspend);
+
+extern void wlc_set_ratetable(struct wlc_info *wlc);
+extern int wlc_set_mac(struct wlc_bsscfg *cfg);
+extern void wlc_beacon_phytxctl_txant_upd(struct wlc_info *wlc,
+ ratespec_t bcn_rate);
+extern void wlc_mod_prb_rsp_rate_table(struct wlc_info *wlc, uint frame_len);
+extern ratespec_t wlc_lowest_basic_rspec(struct wlc_info *wlc,
+ wlc_rateset_t *rs);
+extern void wlc_radio_disable(struct wlc_info *wlc);
+extern void wlc_bcn_li_upd(struct wlc_info *wlc);
+extern void wlc_set_home_chanspec(struct wlc_info *wlc, chanspec_t chanspec);
+extern bool wlc_ps_allowed(struct wlc_info *wlc);
+extern bool wlc_stay_awake(struct wlc_info *wlc);
+extern void wlc_wme_initparams_sta(struct wlc_info *wlc, wme_param_ie_t *pe);
+
+#endif /* _BRCM_MAIN_H_ */
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/pci.h>
-#include <bcmdefs.h>
-#include "wlc_types.h"
+#include <defs.h>
+#include "types.h"
#include <brcmu_utils.h>
#include <aiutils.h>
-#include <bcmsoc.h>
-#include <bcmdevs.h>
+#include <soc.h>
+#include <brcm_hw_ids.h>
#include <chipcommon.h>
-#include <wlc_scb.h>
-#include <wlc_pub.h>
+#include <scb.h>
+#include <pub.h>
#include <nicpci.h>
/* SPROM offsets */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/crc-ccitt.h>
+
+#include <defs.h>
+#include <brcm_hw_ids.h>
+#include "types.h"
+#include <brcmu_utils.h>
+#include <aiutils.h>
+#include <soc.h>
+#include <chipcommon.h>
+#include "otp.h"
+
+#define OTPS_GUP_MASK 0x00000f00
+#define OTPS_GUP_SHIFT 8
+#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
+#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
+#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
+#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
+
+/* Fields in otpprog in rev >= 21 */
+#define OTPP_COL_MASK 0x000000ff
+#define OTPP_COL_SHIFT 0
+#define OTPP_ROW_MASK 0x0000ff00
+#define OTPP_ROW_SHIFT 8
+#define OTPP_OC_MASK 0x0f000000
+#define OTPP_OC_SHIFT 24
+#define OTPP_READERR 0x10000000
+#define OTPP_VALUE_MASK 0x20000000
+#define OTPP_VALUE_SHIFT 29
+#define OTPP_START_BUSY 0x80000000
+#define OTPP_READ 0x40000000
+
+/* Opcodes for OTPP_OC field */
+#define OTPPOC_READ 0
+#define OTPPOC_BIT_PROG 1
+#define OTPPOC_VERIFY 3
+#define OTPPOC_INIT 4
+#define OTPPOC_SET 5
+#define OTPPOC_RESET 6
+#define OTPPOC_OCST 7
+#define OTPPOC_ROW_LOCK 8
+#define OTPPOC_PRESCN_TEST 9
+
+#define OTPTYPE_IPX(ccrev) ((ccrev) == 21 || (ccrev) >= 23)
+
+#define OTPP_TRIES 10000000 /* # of tries for OTPP */
+
+#define MAXNUMRDES 9 /* Maximum OTP redundancy entries */
+
+/* OTP common function type */
+typedef int (*otp_status_t) (void *oh);
+typedef int (*otp_size_t) (void *oh);
+typedef void *(*otp_init_t) (struct si_pub *sih);
+typedef u16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off);
+typedef int (*otp_read_region_t) (struct si_pub *sih, int region, u16 *data,
+ uint *wlen);
+typedef int (*otp_nvread_t) (void *oh, char *data, uint *len);
+
+/* OTP function struct */
+typedef struct otp_fn_s {
+ otp_size_t size;
+ otp_read_bit_t read_bit;
+ otp_init_t init;
+ otp_read_region_t read_region;
+ otp_nvread_t nvread;
+ otp_status_t status;
+} otp_fn_t;
+
+typedef struct {
+ uint ccrev; /* chipc revision */
+ otp_fn_t *fn; /* OTP functions */
+ struct si_pub *sih; /* Saved sb handle */
+
+ /* IPX OTP section */
+ u16 wsize; /* Size of otp in words */
+ u16 rows; /* Geometry */
+ u16 cols; /* Geometry */
+ u32 status; /* Flag bits (lock/prog/rv).
+ * (Reflected only when OTP is power cycled)
+ */
+ u16 hwbase; /* hardware subregion offset */
+ u16 hwlim; /* hardware subregion boundary */
+ u16 swbase; /* software subregion offset */
+ u16 swlim; /* software subregion boundary */
+ u16 fbase; /* fuse subregion offset */
+ u16 flim; /* fuse subregion boundary */
+ int otpgu_base; /* offset to General Use Region */
+} otpinfo_t;
+
+static otpinfo_t otpinfo;
+
+/*
+ * IPX OTP Code
+ *
+ * Exported functions:
+ * ipxotp_status()
+ * ipxotp_size()
+ * ipxotp_init()
+ * ipxotp_read_bit()
+ * ipxotp_read_region()
+ * ipxotp_nvread()
+ *
+ */
+
+#define HWSW_RGN(rgn) (((rgn) == OTP_HW_RGN) ? "h/w" : "s/w")
+
+/* OTP layout */
+/* CC revs 21, 24 and 27 OTP General Use Region word offset */
+#define REVA4_OTPGU_BASE 12
+
+/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */
+#define REVB8_OTPGU_BASE 20
+
+/* CC rev 36 OTP General Use Region word offset */
+#define REV36_OTPGU_BASE 12
+
+/* Subregion word offsets in General Use region */
+#define OTPGU_HSB_OFF 0
+#define OTPGU_SFB_OFF 1
+#define OTPGU_CI_OFF 2
+#define OTPGU_P_OFF 3
+#define OTPGU_SROM_OFF 4
+
+/* Flag bit offsets in General Use region */
+#define OTPGU_HWP_OFF 60
+#define OTPGU_SWP_OFF 61
+#define OTPGU_CIP_OFF 62
+#define OTPGU_FUSEP_OFF 63
+#define OTPGU_CIP_MSK 0x4000
+#define OTPGU_P_MSK 0xf000
+#define OTPGU_P_SHIFT (OTPGU_HWP_OFF % 16)
+
+/* OTP Size */
+#define OTP_SZ_FU_324 ((roundup(324, 8))/8) /* 324 bits */
+#define OTP_SZ_FU_288 (288/8) /* 288 bits */
+#define OTP_SZ_FU_216 (216/8) /* 216 bits */
+#define OTP_SZ_FU_72 (72/8) /* 72 bits */
+#define OTP_SZ_CHECKSUM (16/8) /* 16 bits */
+#define OTP4315_SWREG_SZ 178 /* 178 bytes */
+#define OTP_SZ_FU_144 (144/8) /* 144 bits */
+
+static int ipxotp_status(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ return (int)(oi->status);
+}
+
+/* Return size in bytes */
+static int ipxotp_size(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ return (int)oi->wsize * 2;
+}
+
+static u16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn)
+{
+ otpinfo_t *oi;
+
+ oi = (otpinfo_t *) oh;
+
+ return R_REG(&cc->sromotp[wn]);
+}
+
+static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ uint k, row, col;
+ u32 otpp, st;
+
+ row = off / oi->cols;
+ col = off % oi->cols;
+
+ otpp = OTPP_START_BUSY |
+ ((OTPPOC_READ << OTPP_OC_SHIFT) & OTPP_OC_MASK) |
+ ((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) |
+ ((col << OTPP_COL_SHIFT) & OTPP_COL_MASK);
+ W_REG(&cc->otpprog, otpp);
+
+ for (k = 0;
+ ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
+ && (k < OTPP_TRIES); k++)
+ ;
+ if (k >= OTPP_TRIES) {
+ return 0xffff;
+ }
+ if (st & OTPP_READERR) {
+ return 0xffff;
+ }
+ st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT;
+
+ return (int)st;
+}
+
+/* Calculate max HW/SW region byte size by subtracting fuse region and checksum size,
+ * osizew is oi->wsize (OTP size - GU size) in words
+ */
+static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
+{
+ int ret = 0;
+
+ switch (sih->chip) {
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
+ break;
+ case BCM4313_CHIP_ID:
+ ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
+ break;
+ default:
+ break; /* Don't know about this chip */
+ }
+
+ return ret;
+}
+
+static void _ipxotp_init(otpinfo_t *oi, chipcregs_t *cc)
+{
+ uint k;
+ u32 otpp, st;
+
+ /* record word offset of General Use Region for various chipcommon revs */
+ if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24
+ || oi->sih->ccrev == 27) {
+ oi->otpgu_base = REVA4_OTPGU_BASE;
+ } else if (oi->sih->ccrev == 36) {
+ /* OTP size greater than equal to 2KB (128 words), otpgu_base is similar to rev23 */
+ if (oi->wsize >= 128)
+ oi->otpgu_base = REVB8_OTPGU_BASE;
+ else
+ oi->otpgu_base = REV36_OTPGU_BASE;
+ } else if (oi->sih->ccrev == 23 || oi->sih->ccrev >= 25) {
+ oi->otpgu_base = REVB8_OTPGU_BASE;
+ }
+
+ /* First issue an init command so the status is up to date */
+ otpp =
+ OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
+
+ W_REG(&cc->otpprog, otpp);
+ for (k = 0;
+ ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
+ && (k < OTPP_TRIES); k++)
+ ;
+ if (k >= OTPP_TRIES) {
+ return;
+ }
+
+ /* Read OTP lock bits and subregion programmed indication bits */
+ oi->status = R_REG(&cc->otpstatus);
+
+ if ((oi->sih->chip == BCM43224_CHIP_ID)
+ || (oi->sih->chip == BCM43225_CHIP_ID)) {
+ u32 p_bits;
+ p_bits =
+ (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
+ OTPGU_P_MSK)
+ >> OTPGU_P_SHIFT;
+ oi->status |= (p_bits << OTPS_GUP_SHIFT);
+ }
+
+ /*
+ * h/w region base and fuse region limit are fixed to the top and
+ * the bottom of the general use region. Everything else can be flexible.
+ */
+ oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF;
+ oi->hwlim = oi->wsize;
+ if (oi->status & OTPS_GUP_HW) {
+ oi->hwlim =
+ ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_HSB_OFF) / 16;
+ oi->swbase = oi->hwlim;
+ } else
+ oi->swbase = oi->hwbase;
+
+ /* subtract fuse and checksum from beginning */
+ oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2;
+
+ if (oi->status & OTPS_GUP_SW) {
+ oi->swlim =
+ ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_SFB_OFF) / 16;
+ oi->fbase = oi->swlim;
+ } else
+ oi->fbase = oi->swbase;
+
+ oi->flim = oi->wsize;
+}
+
+static void *ipxotp_init(struct si_pub *sih)
+{
+ uint idx;
+ chipcregs_t *cc;
+ otpinfo_t *oi;
+
+ /* Make sure we're running IPX OTP */
+ if (!OTPTYPE_IPX(sih->ccrev))
+ return NULL;
+
+ /* Make sure OTP is not disabled */
+ if (ai_is_otp_disabled(sih))
+ return NULL;
+
+ /* Make sure OTP is powered up */
+ if (!ai_is_otp_powered(sih))
+ return NULL;
+
+ oi = &otpinfo;
+
+ /* Check for otp size */
+ switch ((sih->cccaps & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
+ case 0:
+ /* Nothing there */
+ return NULL;
+ case 1: /* 32x64 */
+ oi->rows = 32;
+ oi->cols = 64;
+ oi->wsize = 128;
+ break;
+ case 2: /* 64x64 */
+ oi->rows = 64;
+ oi->cols = 64;
+ oi->wsize = 256;
+ break;
+ case 5: /* 96x64 */
+ oi->rows = 96;
+ oi->cols = 64;
+ oi->wsize = 384;
+ break;
+ case 7: /* 16x64 *//* 1024 bits */
+ oi->rows = 16;
+ oi->cols = 64;
+ oi->wsize = 64;
+ break;
+ default:
+ /* Don't know the geometry */
+ return NULL;
+ }
+
+ /* Retrieve OTP region info */
+ idx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ _ipxotp_init(oi, cc);
+
+ ai_setcoreidx(sih, idx);
+
+ return (void *)oi;
+}
+
+static int ipxotp_read_region(void *oh, int region, u16 *data, uint *wlen)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ uint idx;
+ chipcregs_t *cc;
+ uint base, i, sz;
+
+ /* Validate region selection */
+ switch (region) {
+ case OTP_HW_RGN:
+ sz = (uint) oi->hwlim - oi->hwbase;
+ if (!(oi->status & OTPS_GUP_HW)) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->hwbase;
+ break;
+ case OTP_SW_RGN:
+ sz = ((uint) oi->swlim - oi->swbase);
+ if (!(oi->status & OTPS_GUP_SW)) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->swbase;
+ break;
+ case OTP_CI_RGN:
+ sz = OTPGU_CI_SZ;
+ if (!(oi->status & OTPS_GUP_CI)) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->otpgu_base + OTPGU_CI_OFF;
+ break;
+ case OTP_FUSE_RGN:
+ sz = (uint) oi->flim - oi->fbase;
+ if (!(oi->status & OTPS_GUP_FUSE)) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->fbase;
+ break;
+ case OTP_ALL_RGN:
+ sz = ((uint) oi->flim - oi->hwbase);
+ if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->hwbase;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ idx = ai_coreidx(oi->sih);
+ cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
+
+ /* Read the data */
+ for (i = 0; i < sz; i++)
+ data[i] = ipxotp_otpr(oh, cc, base + i);
+
+ ai_setcoreidx(oi->sih, idx);
+ *wlen = sz;
+ return 0;
+}
+
+static int ipxotp_nvread(void *oh, char *data, uint *len)
+{
+ return -ENOTSUPP;
+}
+
+static otp_fn_t ipxotp_fn = {
+ (otp_size_t) ipxotp_size,
+ (otp_read_bit_t) ipxotp_read_bit,
+
+ (otp_init_t) ipxotp_init,
+ (otp_read_region_t) ipxotp_read_region,
+ (otp_nvread_t) ipxotp_nvread,
+
+ (otp_status_t) ipxotp_status
+};
+
+/*
+ * otp_status()
+ * otp_size()
+ * otp_read_bit()
+ * otp_init()
+ * otp_read_region()
+ * otp_nvread()
+ */
+
+int otp_status(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+
+ return oi->fn->status(oh);
+}
+
+int otp_size(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+
+ return oi->fn->size(oh);
+}
+
+u16 otp_read_bit(void *oh, uint offset)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ uint idx = ai_coreidx(oi->sih);
+ chipcregs_t *cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
+ u16 readBit = (u16) oi->fn->read_bit(oh, cc, offset);
+ ai_setcoreidx(oi->sih, idx);
+ return readBit;
+}
+
+void *otp_init(struct si_pub *sih)
+{
+ otpinfo_t *oi;
+ void *ret = NULL;
+
+ oi = &otpinfo;
+ memset(oi, 0, sizeof(otpinfo_t));
+
+ oi->ccrev = sih->ccrev;
+
+ if (OTPTYPE_IPX(oi->ccrev))
+ oi->fn = &ipxotp_fn;
+
+ if (oi->fn == NULL) {
+ return NULL;
+ }
+
+ oi->sih = sih;
+
+ ret = (oi->fn->init) (sih);
+
+ return ret;
+}
+
+int
+otp_read_region(struct si_pub *sih, int region, u16 *data,
+ uint *wlen) {
+ bool wasup = false;
+ void *oh;
+ int err = 0;
+
+ wasup = ai_is_otp_powered(sih);
+ if (!wasup)
+ ai_otp_power(sih, true);
+
+ if (!ai_is_otp_powered(sih) || ai_is_otp_disabled(sih)) {
+ err = -EPERM;
+ goto out;
+ }
+
+ oh = otp_init(sih);
+ if (oh == NULL) {
+ err = -EBADE;
+ goto out;
+ }
+
+ err = (((otpinfo_t *) oh)->fn->read_region) (oh, region, data, wlen);
+
+ out:
+ if (!wasup)
+ ai_otp_power(sih, false);
+
+ return err;
+}
+
+int otp_nvread(void *oh, char *data, uint *len)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+
+ return oi->fn->nvread(oh, data, len);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_OTP_H_
+#define _BRCM_OTP_H_
+
+/* OTP regions */
+#define OTP_HW_RGN 1
+#define OTP_SW_RGN 2
+#define OTP_CI_RGN 4
+#define OTP_FUSE_RGN 8
+#define OTP_ALL_RGN 0xf /* From h/w region to end of OTP including checksum */
+
+/* OTP Size */
+#define OTP_SZ_MAX (6144/8) /* maximum bytes in one CIS */
+
+/* Fixed size subregions sizes in words */
+#define OTPGU_CI_SZ 2
+
+/* OTP usage */
+#define OTP4325_FM_DISABLED_OFFSET 188
+
+/* Exported functions */
+extern int otp_status(void *oh);
+extern int otp_size(void *oh);
+extern u16 otp_read_bit(void *oh, uint offset);
+extern void *otp_init(struct si_pub *sih);
+extern int otp_read_region(struct si_pub *sih, int region, u16 *data,
+ uint *wlen);
+extern int otp_nvread(void *oh, char *data, uint *len);
+
+#endif /* _BRCM_OTP_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <cfg.h>
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include <defs.h>
+#include <chipcommon.h>
+#include <brcm_hw_ids.h>
+#include <dma.h>
+
+#include <types.h>
+#include <phy_int.h>
+#include <phyreg_n.h>
+#include <phy_radio.h>
+#include <phy_lcn.h>
+
+u32 phyhal_msg_level = PHYHAL_ERROR;
+
+typedef struct _chan_info_basic {
+ u16 chan;
+ u16 freq;
+} chan_info_basic_t;
+
+static chan_info_basic_t chan_info_all[] = {
+
+ {1, 2412},
+ {2, 2417},
+ {3, 2422},
+ {4, 2427},
+ {5, 2432},
+ {6, 2437},
+ {7, 2442},
+ {8, 2447},
+ {9, 2452},
+ {10, 2457},
+ {11, 2462},
+ {12, 2467},
+ {13, 2472},
+ {14, 2484},
+
+ {34, 5170},
+ {38, 5190},
+ {42, 5210},
+ {46, 5230},
+
+ {36, 5180},
+ {40, 5200},
+ {44, 5220},
+ {48, 5240},
+ {52, 5260},
+ {56, 5280},
+ {60, 5300},
+ {64, 5320},
+
+ {100, 5500},
+ {104, 5520},
+ {108, 5540},
+ {112, 5560},
+ {116, 5580},
+ {120, 5600},
+ {124, 5620},
+ {128, 5640},
+ {132, 5660},
+ {136, 5680},
+ {140, 5700},
+
+ {149, 5745},
+ {153, 5765},
+ {157, 5785},
+ {161, 5805},
+ {165, 5825},
+
+ {184, 4920},
+ {188, 4940},
+ {192, 4960},
+ {196, 4980},
+ {200, 5000},
+ {204, 5020},
+ {208, 5040},
+ {212, 5060},
+ {216, 50800}
+};
+
+u16 ltrn_list[PHY_LTRN_LIST_LEN] = {
+ 0x18f9, 0x0d01, 0x00e4, 0xdef4, 0x06f1, 0x0ffc,
+ 0xfa27, 0x1dff, 0x10f0, 0x0918, 0xf20a, 0xe010,
+ 0x1417, 0x1104, 0xf114, 0xf2fa, 0xf7db, 0xe2fc,
+ 0xe1fb, 0x13ee, 0xff0d, 0xe91c, 0x171a, 0x0318,
+ 0xda00, 0x03e8, 0x17e6, 0xe9e4, 0xfff3, 0x1312,
+ 0xe105, 0xe204, 0xf725, 0xf206, 0xf1ec, 0x11fc,
+ 0x14e9, 0xe0f0, 0xf2f6, 0x09e8, 0x1010, 0x1d01,
+ 0xfad9, 0x0f04, 0x060f, 0xde0c, 0x001c, 0x0dff,
+ 0x1807, 0xf61a, 0xe40e, 0x0f16, 0x05f9, 0x18ec,
+ 0x0a1b, 0xff1e, 0x2600, 0xffe2, 0x0ae5, 0x1814,
+ 0x0507, 0x0fea, 0xe4f2, 0xf6e6
+};
+
+const u8 ofdm_rate_lookup[] = {
+
+ WLC_RATE_48M,
+ WLC_RATE_24M,
+ WLC_RATE_12M,
+ WLC_RATE_6M,
+ WLC_RATE_54M,
+ WLC_RATE_36M,
+ WLC_RATE_18M,
+ WLC_RATE_9M
+};
+
+#define PHY_WREG_LIMIT 24
+
+static void wlc_set_phy_uninitted(phy_info_t *pi);
+static u32 wlc_phy_get_radio_ver(phy_info_t *pi);
+static void wlc_phy_timercb_phycal(void *arg);
+
+static bool wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr,
+ s8 *pwr_ant);
+
+static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay);
+static void wlc_phy_noise_cb(phy_info_t *pi, u8 channel, s8 noise_dbm);
+static void wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason,
+ u8 ch);
+
+static void wlc_phy_txpower_reg_limit_calc(phy_info_t *pi,
+ struct txpwr_limits *tp, chanspec_t);
+static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi);
+
+static s8 wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan,
+ u32 band, u8 rate);
+static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band);
+static s8 wlc_phy_env_measure_vbat(phy_info_t *pi);
+static s8 wlc_phy_env_measure_temperature(phy_info_t *pi);
+
+char *phy_getvar(phy_info_t *pi, const char *name)
+{
+ char *vars = pi->vars;
+ char *s;
+ int len;
+
+ if (!name)
+ return NULL;
+
+ len = strlen(name);
+ if (len == 0)
+ return NULL;
+
+ for (s = vars; s && *s;) {
+ if ((memcmp(s, name, len) == 0) && (s[len] == '='))
+ return &s[len + 1];
+
+ while (*s++)
+ ;
+ }
+
+ return NULL;
+}
+
+int phy_getintvar(phy_info_t *pi, const char *name)
+{
+ char *val;
+
+ val = PHY_GETVAR(pi, name);
+ if (val == NULL)
+ return 0;
+
+ return simple_strtoul(val, NULL, 0);
+}
+
+void wlc_phyreg_enter(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ wlapi_bmac_ucode_wake_override_phyreg_set(pi->sh->physhim);
+}
+
+void wlc_phyreg_exit(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ wlapi_bmac_ucode_wake_override_phyreg_clear(pi->sh->physhim);
+}
+
+void wlc_radioreg_enter(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO);
+
+ udelay(10);
+}
+
+void wlc_radioreg_exit(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ volatile u16 dummy;
+
+ dummy = R_REG(&pi->regs->phyversion);
+ pi->phy_wreg = 0;
+ wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);
+}
+
+u16 read_radio_reg(phy_info_t *pi, u16 addr)
+{
+ u16 data;
+
+ if ((addr == RADIO_IDCODE))
+ return 0xffff;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return NORADIO_IDCODE & 0xffff;
+
+ switch (pi->pubpi.phy_type) {
+ case PHY_TYPE_N:
+ CASECHECK(PHYTYPE, PHY_TYPE_N);
+ if (NREV_GE(pi->pubpi.phy_rev, 7))
+ addr |= RADIO_2057_READ_OFF;
+ else
+ addr |= RADIO_2055_READ_OFF;
+ break;
+
+ case PHY_TYPE_LCN:
+ CASECHECK(PHYTYPE, PHY_TYPE_LCN);
+ addr |= RADIO_2064_READ_OFF;
+ break;
+
+ default:
+ break;
+ }
+
+ if ((D11REV_GE(pi->sh->corerev, 24)) ||
+ (D11REV_IS(pi->sh->corerev, 22)
+ && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
+ W_REG_FLUSH(&pi->regs->radioregaddr, addr);
+ data = R_REG(&pi->regs->radioregdata);
+ } else {
+ W_REG_FLUSH(&pi->regs->phy4waddr, addr);
+
+#ifdef __ARM_ARCH_4T__
+ __asm__(" .align 4 ");
+ __asm__(" nop ");
+ data = R_REG(&pi->regs->phy4wdatalo);
+#else
+ data = R_REG(&pi->regs->phy4wdatalo);
+#endif
+
+ }
+ pi->phy_wreg = 0;
+
+ return data;
+}
+
+void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
+{
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ if ((D11REV_GE(pi->sh->corerev, 24)) ||
+ (D11REV_IS(pi->sh->corerev, 22)
+ && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
+
+ W_REG_FLUSH(&pi->regs->radioregaddr, addr);
+ W_REG(&pi->regs->radioregdata, val);
+ } else {
+ W_REG_FLUSH(&pi->regs->phy4waddr, addr);
+ W_REG(&pi->regs->phy4wdatalo, val);
+ }
+
+ if (pi->sh->bustype == PCI_BUS) {
+ if (++pi->phy_wreg >= pi->phy_wreg_limit) {
+ (void)R_REG(&pi->regs->maccontrol);
+ pi->phy_wreg = 0;
+ }
+ }
+}
+
+static u32 read_radio_id(phy_info_t *pi)
+{
+ u32 id;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return NORADIO_IDCODE;
+
+ if (D11REV_GE(pi->sh->corerev, 24)) {
+ u32 b0, b1, b2;
+
+ W_REG_FLUSH(&pi->regs->radioregaddr, 0);
+ b0 = (u32) R_REG(&pi->regs->radioregdata);
+ W_REG_FLUSH(&pi->regs->radioregaddr, 1);
+ b1 = (u32) R_REG(&pi->regs->radioregdata);
+ W_REG_FLUSH(&pi->regs->radioregaddr, 2);
+ b2 = (u32) R_REG(&pi->regs->radioregdata);
+
+ id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
+ & 0xf);
+ } else {
+ W_REG_FLUSH(&pi->regs->phy4waddr, RADIO_IDCODE);
+ id = (u32) R_REG(&pi->regs->phy4wdatalo);
+ id |= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
+ }
+ pi->phy_wreg = 0;
+ return id;
+}
+
+void and_radio_reg(phy_info_t *pi, u16 addr, u16 val)
+{
+ u16 rval;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ rval = read_radio_reg(pi, addr);
+ write_radio_reg(pi, addr, (rval & val));
+}
+
+void or_radio_reg(phy_info_t *pi, u16 addr, u16 val)
+{
+ u16 rval;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ rval = read_radio_reg(pi, addr);
+ write_radio_reg(pi, addr, (rval | val));
+}
+
+void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask)
+{
+ u16 rval;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ rval = read_radio_reg(pi, addr);
+ write_radio_reg(pi, addr, (rval ^ mask));
+}
+
+void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
+{
+ u16 rval;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ rval = read_radio_reg(pi, addr);
+ write_radio_reg(pi, addr, (rval & ~mask) | (val & mask));
+}
+
+void write_phy_channel_reg(phy_info_t *pi, uint val)
+{
+ W_REG(&pi->regs->phychannel, val);
+}
+
+u16 read_phy_reg(phy_info_t *pi, u16 addr)
+{
+ d11regs_t *regs;
+
+ regs = pi->regs;
+
+ W_REG_FLUSH(®s->phyregaddr, addr);
+
+ pi->phy_wreg = 0;
+ return R_REG(®s->phyregdata);
+}
+
+void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
+{
+ d11regs_t *regs;
+
+ regs = pi->regs;
+
+#ifdef __mips__
+ W_REG_FLUSH(®s->phyregaddr, addr);
+ W_REG(®s->phyregdata, val);
+ if (addr == 0x72)
+ (void)R_REG(®s->phyregdata);
+#else
+ W_REG((u32 *)(®s->phyregaddr),
+ addr | (val << 16));
+ if (pi->sh->bustype == PCI_BUS) {
+ if (++pi->phy_wreg >= pi->phy_wreg_limit) {
+ pi->phy_wreg = 0;
+ (void)R_REG(®s->phyversion);
+ }
+ }
+#endif
+}
+
+void and_phy_reg(phy_info_t *pi, u16 addr, u16 val)
+{
+ d11regs_t *regs;
+
+ regs = pi->regs;
+
+ W_REG_FLUSH(®s->phyregaddr, addr);
+
+ W_REG(®s->phyregdata, (R_REG(®s->phyregdata) & val));
+ pi->phy_wreg = 0;
+}
+
+void or_phy_reg(phy_info_t *pi, u16 addr, u16 val)
+{
+ d11regs_t *regs;
+
+ regs = pi->regs;
+
+ W_REG_FLUSH(®s->phyregaddr, addr);
+
+ W_REG(®s->phyregdata, (R_REG(®s->phyregdata) | val));
+ pi->phy_wreg = 0;
+}
+
+void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
+{
+ d11regs_t *regs;
+
+ regs = pi->regs;
+
+ W_REG_FLUSH(®s->phyregaddr, addr);
+
+ W_REG(®s->phyregdata,
+ ((R_REG(®s->phyregdata) & ~mask) | (val & mask)));
+ pi->phy_wreg = 0;
+}
+
+static void WLBANDINITFN(wlc_set_phy_uninitted) (phy_info_t *pi)
+{
+ int i, j;
+
+ pi->initialized = false;
+
+ pi->tx_vos = 0xffff;
+ pi->nrssi_table_delta = 0x7fffffff;
+ pi->rc_cal = 0xffff;
+ pi->mintxbias = 0xffff;
+ pi->txpwridx = -1;
+ if (ISNPHY(pi)) {
+ pi->phy_spuravoid = SPURAVOID_DISABLE;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)
+ && NREV_LT(pi->pubpi.phy_rev, 7))
+ pi->phy_spuravoid = SPURAVOID_AUTO;
+
+ pi->nphy_papd_skip = 0;
+ pi->nphy_papd_epsilon_offset[0] = 0xf588;
+ pi->nphy_papd_epsilon_offset[1] = 0xf588;
+ pi->nphy_txpwr_idx[0] = 128;
+ pi->nphy_txpwr_idx[1] = 128;
+ pi->nphy_txpwrindex[0].index_internal = 40;
+ pi->nphy_txpwrindex[1].index_internal = 40;
+ pi->phy_pabias = 0;
+ } else {
+ pi->phy_spuravoid = SPURAVOID_AUTO;
+ }
+ pi->radiopwr = 0xffff;
+ for (i = 0; i < STATIC_NUM_RF; i++) {
+ for (j = 0; j < STATIC_NUM_BB; j++) {
+ pi->stats_11b_txpower[i][j] = -1;
+ }
+ }
+}
+
+shared_phy_t *wlc_phy_shared_attach(shared_phy_params_t *shp)
+{
+ shared_phy_t *sh;
+
+ sh = kzalloc(sizeof(shared_phy_t), GFP_ATOMIC);
+ if (sh == NULL) {
+ return NULL;
+ }
+
+ sh->sih = shp->sih;
+ sh->physhim = shp->physhim;
+ sh->unit = shp->unit;
+ sh->corerev = shp->corerev;
+
+ sh->vid = shp->vid;
+ sh->did = shp->did;
+ sh->chip = shp->chip;
+ sh->chiprev = shp->chiprev;
+ sh->chippkg = shp->chippkg;
+ sh->sromrev = shp->sromrev;
+ sh->boardtype = shp->boardtype;
+ sh->boardrev = shp->boardrev;
+ sh->boardvendor = shp->boardvendor;
+ sh->boardflags = shp->boardflags;
+ sh->boardflags2 = shp->boardflags2;
+ sh->bustype = shp->bustype;
+ sh->buscorerev = shp->buscorerev;
+
+ sh->fast_timer = PHY_SW_TIMER_FAST;
+ sh->slow_timer = PHY_SW_TIMER_SLOW;
+ sh->glacial_timer = PHY_SW_TIMER_GLACIAL;
+
+ sh->rssi_mode = RSSI_ANT_MERGE_MAX;
+
+ return sh;
+}
+
+void wlc_phy_shared_detach(shared_phy_t *phy_sh)
+{
+ if (phy_sh) {
+ kfree(phy_sh);
+ }
+}
+
+wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype,
+ char *vars, struct wiphy *wiphy)
+{
+ phy_info_t *pi;
+ u32 sflags = 0;
+ uint phyversion;
+ int i;
+
+ if (D11REV_IS(sh->corerev, 4))
+ sflags = SISF_2G_PHY | SISF_5G_PHY;
+ else
+ sflags = ai_core_sflags(sh->sih, 0, 0);
+
+ if (BAND_5G(bandtype)) {
+ if ((sflags & (SISF_5G_PHY | SISF_DB_PHY)) == 0) {
+ return NULL;
+ }
+ }
+
+ pi = sh->phy_head;
+ if ((sflags & SISF_DB_PHY) && pi) {
+
+ wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
+ pi->refcnt++;
+ return &pi->pubpi_ro;
+ }
+
+ pi = kzalloc(sizeof(phy_info_t), GFP_ATOMIC);
+ if (pi == NULL) {
+ return NULL;
+ }
+ pi->wiphy = wiphy;
+ pi->regs = (d11regs_t *) regs;
+ pi->sh = sh;
+ pi->phy_init_por = true;
+ pi->phy_wreg_limit = PHY_WREG_LIMIT;
+
+ pi->vars = vars;
+
+ pi->txpwr_percent = 100;
+
+ pi->do_initcal = true;
+
+ pi->phycal_tempdelta = 0;
+
+ if (BAND_2G(bandtype) && (sflags & SISF_2G_PHY)) {
+
+ pi->pubpi.coreflags = SICF_GMODE;
+ }
+
+ wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
+ phyversion = R_REG(&pi->regs->phyversion);
+
+ pi->pubpi.phy_type = PHY_TYPE(phyversion);
+ pi->pubpi.phy_rev = phyversion & PV_PV_MASK;
+
+ if (pi->pubpi.phy_type == PHY_TYPE_LCNXN) {
+ pi->pubpi.phy_type = PHY_TYPE_N;
+ pi->pubpi.phy_rev += LCNXN_BASEREV;
+ }
+ pi->pubpi.phy_corenum = PHY_CORE_NUM_2;
+ pi->pubpi.ana_rev = (phyversion & PV_AV_MASK) >> PV_AV_SHIFT;
+
+ if (!VALID_PHYTYPE(pi->pubpi.phy_type)) {
+ goto err;
+ }
+ if (BAND_5G(bandtype)) {
+ if (!ISNPHY(pi)) {
+ goto err;
+ }
+ } else {
+ if (!ISNPHY(pi) && !ISLCNPHY(pi)) {
+ goto err;
+ }
+ }
+
+ if (ISSIM_ENAB(pi->sh->sih)) {
+ pi->pubpi.radioid = NORADIO_ID;
+ pi->pubpi.radiorev = 5;
+ } else {
+ u32 idcode;
+
+ wlc_phy_anacore((wlc_phy_t *) pi, ON);
+
+ idcode = wlc_phy_get_radio_ver(pi);
+ pi->pubpi.radioid =
+ (idcode & IDCODE_ID_MASK) >> IDCODE_ID_SHIFT;
+ pi->pubpi.radiorev =
+ (idcode & IDCODE_REV_MASK) >> IDCODE_REV_SHIFT;
+ pi->pubpi.radiover =
+ (idcode & IDCODE_VER_MASK) >> IDCODE_VER_SHIFT;
+ if (!VALID_RADIO(pi, pi->pubpi.radioid)) {
+ goto err;
+ }
+
+ wlc_phy_switch_radio((wlc_phy_t *) pi, OFF);
+ }
+
+ wlc_set_phy_uninitted(pi);
+
+ pi->bw = WL_CHANSPEC_BW_20;
+ pi->radio_chanspec =
+ BAND_2G(bandtype) ? CH20MHZ_CHSPEC(1) : CH20MHZ_CHSPEC(36);
+
+ pi->rxiq_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
+ pi->rxiq_antsel = ANT_RX_DIV_DEF;
+
+ pi->watchdog_override = true;
+
+ pi->cal_type_override = PHY_PERICAL_AUTO;
+
+ pi->nphy_saved_noisevars.bufcount = 0;
+
+ if (ISNPHY(pi))
+ pi->min_txpower = PHY_TXPWR_MIN_NPHY;
+ else
+ pi->min_txpower = PHY_TXPWR_MIN;
+
+ pi->sh->phyrxchain = 0x3;
+
+ pi->rx2tx_biasentry = -1;
+
+ pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
+ pi->phy_txcore_enable_temp =
+ PHY_CHAIN_TX_DISABLE_TEMP - PHY_HYSTERESIS_DELTATEMP;
+ pi->phy_tempsense_offset = 0;
+ pi->phy_txcore_heatedup = false;
+
+ pi->nphy_lastcal_temp = -50;
+
+ pi->phynoise_polling = true;
+ if (ISNPHY(pi) || ISLCNPHY(pi))
+ pi->phynoise_polling = false;
+
+ for (i = 0; i < TXP_NUM_RATES; i++) {
+ pi->txpwr_limit[i] = WLC_TXPWR_MAX;
+ pi->txpwr_env_limit[i] = WLC_TXPWR_MAX;
+ pi->tx_user_target[i] = WLC_TXPWR_MAX;
+ }
+
+ pi->radiopwr_override = RADIOPWR_OVERRIDE_DEF;
+
+ pi->user_txpwr_at_rfport = false;
+
+ if (ISNPHY(pi)) {
+
+ pi->phycal_timer = wlapi_init_timer(pi->sh->physhim,
+ wlc_phy_timercb_phycal,
+ pi, "phycal");
+ if (!pi->phycal_timer) {
+ goto err;
+ }
+
+ if (!wlc_phy_attach_nphy(pi))
+ goto err;
+
+ } else if (ISLCNPHY(pi)) {
+ if (!wlc_phy_attach_lcnphy(pi))
+ goto err;
+
+ } else {
+
+ }
+
+ pi->refcnt++;
+ pi->next = pi->sh->phy_head;
+ sh->phy_head = pi;
+
+ pi->vars = (char *)&pi->vars;
+
+ memcpy(&pi->pubpi_ro, &pi->pubpi, sizeof(wlc_phy_t));
+
+ return &pi->pubpi_ro;
+
+ err:
+ kfree(pi);
+ return NULL;
+}
+
+void wlc_phy_detach(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (pih) {
+ if (--pi->refcnt) {
+ return;
+ }
+
+ if (pi->phycal_timer) {
+ wlapi_free_timer(pi->sh->physhim, pi->phycal_timer);
+ pi->phycal_timer = NULL;
+ }
+
+ if (pi->sh->phy_head == pi)
+ pi->sh->phy_head = pi->next;
+ else if (pi->sh->phy_head->next == pi)
+ pi->sh->phy_head->next = NULL;
+
+ if (pi->pi_fptr.detach)
+ (pi->pi_fptr.detach) (pi);
+
+ kfree(pi);
+ }
+}
+
+bool
+wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype, u16 *phyrev,
+ u16 *radioid, u16 *radiover)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ *phytype = (u16) pi->pubpi.phy_type;
+ *phyrev = (u16) pi->pubpi.phy_rev;
+ *radioid = pi->pubpi.radioid;
+ *radiover = pi->pubpi.radiorev;
+
+ return true;
+}
+
+bool wlc_phy_get_encore(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ return pi->pubpi.abgphy_encore;
+}
+
+u32 wlc_phy_get_coreflags(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ return pi->pubpi.coreflags;
+}
+
+static void wlc_phy_timercb_phycal(void *arg)
+{
+ phy_info_t *pi = (phy_info_t *) arg;
+ uint delay = 5;
+
+ if (PHY_PERICAL_MPHASE_PENDING(pi)) {
+ if (!pi->sh->up) {
+ wlc_phy_cal_perical_mphase_reset(pi);
+ return;
+ }
+
+ if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)) {
+
+ delay = 1000;
+ wlc_phy_cal_perical_mphase_restart(pi);
+ } else
+ wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_AUTO);
+ wlapi_add_timer(pi->sh->physhim, pi->phycal_timer, delay, 0);
+ return;
+ }
+
+}
+
+void wlc_phy_anacore(wlc_phy_t *pih, bool on)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (ISNPHY(pi)) {
+ if (on) {
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ write_phy_reg(pi, 0xa6, 0x0d);
+ write_phy_reg(pi, 0x8f, 0x0);
+ write_phy_reg(pi, 0xa7, 0x0d);
+ write_phy_reg(pi, 0xa5, 0x0);
+ } else {
+ write_phy_reg(pi, 0xa5, 0x0);
+ }
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ write_phy_reg(pi, 0x8f, 0x07ff);
+ write_phy_reg(pi, 0xa6, 0x0fd);
+ write_phy_reg(pi, 0xa5, 0x07ff);
+ write_phy_reg(pi, 0xa7, 0x0fd);
+ } else {
+ write_phy_reg(pi, 0xa5, 0x7fff);
+ }
+ }
+ } else if (ISLCNPHY(pi)) {
+ if (on) {
+ and_phy_reg(pi, 0x43b,
+ ~((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
+ } else {
+ or_phy_reg(pi, 0x43c,
+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
+ or_phy_reg(pi, 0x43b,
+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
+ }
+ }
+}
+
+u32 wlc_phy_clk_bwbits(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ u32 phy_bw_clkbits = 0;
+
+ if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
+ switch (pi->bw) {
+ case WL_CHANSPEC_BW_10:
+ phy_bw_clkbits = SICF_BW10;
+ break;
+ case WL_CHANSPEC_BW_20:
+ phy_bw_clkbits = SICF_BW20;
+ break;
+ case WL_CHANSPEC_BW_40:
+ phy_bw_clkbits = SICF_BW40;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return phy_bw_clkbits;
+}
+
+void WLBANDINITFN(wlc_phy_por_inform) (wlc_phy_t *ppi)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ pi->phy_init_por = true;
+}
+
+void wlc_phy_edcrs_lock(wlc_phy_t *pih, bool lock)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ pi->edcrs_threshold_lock = lock;
+
+ write_phy_reg(pi, 0x22c, 0x46b);
+ write_phy_reg(pi, 0x22d, 0x46b);
+ write_phy_reg(pi, 0x22e, 0x3c0);
+ write_phy_reg(pi, 0x22f, 0x3c0);
+}
+
+void wlc_phy_initcal_enable(wlc_phy_t *pih, bool initcal)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ pi->do_initcal = initcal;
+}
+
+void wlc_phy_hw_clk_state_upd(wlc_phy_t *pih, bool newstate)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (!pi || !pi->sh)
+ return;
+
+ pi->sh->clk = newstate;
+}
+
+void wlc_phy_hw_state_upd(wlc_phy_t *pih, bool newstate)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (!pi || !pi->sh)
+ return;
+
+ pi->sh->up = newstate;
+}
+
+void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec)
+{
+ u32 mc;
+ initfn_t phy_init = NULL;
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (pi->init_in_progress)
+ return;
+
+ pi->init_in_progress = true;
+
+ pi->radio_chanspec = chanspec;
+
+ mc = R_REG(&pi->regs->maccontrol);
+ if (WARN(mc & MCTL_EN_MAC, "HW error MAC running on init"))
+ return;
+
+ if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN)) {
+ pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
+ }
+
+ if (WARN(!(ai_core_sflags(pi->sh->sih, 0, 0) & SISF_FCLKA),
+ "HW error SISF_FCLKA\n"))
+ return;
+
+ phy_init = pi->pi_fptr.init;
+
+ if (phy_init == NULL) {
+ return;
+ }
+
+ wlc_phy_anacore(pih, ON);
+
+ if (CHSPEC_BW(pi->radio_chanspec) != pi->bw)
+ wlapi_bmac_bw_set(pi->sh->physhim,
+ CHSPEC_BW(pi->radio_chanspec));
+
+ pi->nphy_gain_boost = true;
+
+ wlc_phy_switch_radio((wlc_phy_t *) pi, ON);
+
+ (*phy_init) (pi);
+
+ pi->phy_init_por = false;
+
+ if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
+ wlc_phy_do_dummy_tx(pi, true, OFF);
+
+ if (!(ISNPHY(pi)))
+ wlc_phy_txpower_update_shm(pi);
+
+ wlc_phy_ant_rxdiv_set((wlc_phy_t *) pi, pi->sh->rx_antdiv);
+
+ pi->init_in_progress = false;
+}
+
+void wlc_phy_cal_init(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ initfn_t cal_init = NULL;
+
+ if (WARN((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) != 0,
+ "HW error: MAC enabled during phy cal\n"))
+ return;
+
+ if (!pi->initialized) {
+ cal_init = pi->pi_fptr.calinit;
+ if (cal_init)
+ (*cal_init) (pi);
+
+ pi->initialized = true;
+ }
+}
+
+int wlc_phy_down(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ int callbacks = 0;
+
+ if (pi->phycal_timer
+ && !wlapi_del_timer(pi->sh->physhim, pi->phycal_timer))
+ callbacks++;
+
+ pi->nphy_iqcal_chanspec_2G = 0;
+ pi->nphy_iqcal_chanspec_5G = 0;
+
+ return callbacks;
+}
+
+static u32 wlc_phy_get_radio_ver(phy_info_t *pi)
+{
+ u32 ver;
+
+ ver = read_radio_id(pi);
+
+ return ver;
+}
+
+void
+wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
+ u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
+{
+ write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
+
+ pi->tbl_data_hi = tblDataHi;
+ pi->tbl_data_lo = tblDataLo;
+
+ if ((pi->sh->chip == BCM43224_CHIP_ID ||
+ pi->sh->chip == BCM43421_CHIP_ID) &&
+ (pi->sh->chiprev == 1)) {
+ pi->tbl_addr = tblAddr;
+ pi->tbl_save_id = tbl_id;
+ pi->tbl_save_offset = tbl_offset;
+ }
+}
+
+void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val)
+{
+ if ((pi->sh->chip == BCM43224_CHIP_ID ||
+ pi->sh->chip == BCM43421_CHIP_ID) &&
+ (pi->sh->chiprev == 1) &&
+ (pi->tbl_save_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
+ read_phy_reg(pi, pi->tbl_data_lo);
+
+ write_phy_reg(pi, pi->tbl_addr,
+ (pi->tbl_save_id << 10) | pi->tbl_save_offset);
+ pi->tbl_save_offset++;
+ }
+
+ if (width == 32) {
+
+ write_phy_reg(pi, pi->tbl_data_hi, (u16) (val >> 16));
+ write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
+ } else {
+
+ write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
+ }
+}
+
+void
+wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
+ u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
+{
+ uint idx;
+ uint tbl_id = ptbl_info->tbl_id;
+ uint tbl_offset = ptbl_info->tbl_offset;
+ uint tbl_width = ptbl_info->tbl_width;
+ const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr;
+ const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
+ const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
+
+ write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
+
+ for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
+
+ if ((pi->sh->chip == BCM43224_CHIP_ID ||
+ pi->sh->chip == BCM43421_CHIP_ID) &&
+ (pi->sh->chiprev == 1) &&
+ (tbl_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
+ read_phy_reg(pi, tblDataLo);
+
+ write_phy_reg(pi, tblAddr,
+ (tbl_id << 10) | (tbl_offset + idx));
+ }
+
+ if (tbl_width == 32) {
+
+ write_phy_reg(pi, tblDataHi,
+ (u16) (ptbl_32b[idx] >> 16));
+ write_phy_reg(pi, tblDataLo, (u16) ptbl_32b[idx]);
+ } else if (tbl_width == 16) {
+
+ write_phy_reg(pi, tblDataLo, ptbl_16b[idx]);
+ } else {
+
+ write_phy_reg(pi, tblDataLo, ptbl_8b[idx]);
+ }
+ }
+}
+
+void
+wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
+ u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
+{
+ uint idx;
+ uint tbl_id = ptbl_info->tbl_id;
+ uint tbl_offset = ptbl_info->tbl_offset;
+ uint tbl_width = ptbl_info->tbl_width;
+ u8 *ptbl_8b = (u8 *)ptbl_info->tbl_ptr;
+ u16 *ptbl_16b = (u16 *)ptbl_info->tbl_ptr;
+ u32 *ptbl_32b = (u32 *)ptbl_info->tbl_ptr;
+
+ write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
+
+ for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
+
+ if ((pi->sh->chip == BCM43224_CHIP_ID ||
+ pi->sh->chip == BCM43421_CHIP_ID) &&
+ (pi->sh->chiprev == 1)) {
+ (void)read_phy_reg(pi, tblDataLo);
+
+ write_phy_reg(pi, tblAddr,
+ (tbl_id << 10) | (tbl_offset + idx));
+ }
+
+ if (tbl_width == 32) {
+
+ ptbl_32b[idx] = read_phy_reg(pi, tblDataLo);
+ ptbl_32b[idx] |= (read_phy_reg(pi, tblDataHi) << 16);
+ } else if (tbl_width == 16) {
+
+ ptbl_16b[idx] = read_phy_reg(pi, tblDataLo);
+ } else {
+
+ ptbl_8b[idx] = (u8) read_phy_reg(pi, tblDataLo);
+ }
+ }
+}
+
+uint
+wlc_phy_init_radio_regs_allbands(phy_info_t *pi, radio_20xx_regs_t *radioregs)
+{
+ uint i = 0;
+
+ do {
+ if (radioregs[i].do_init) {
+ write_radio_reg(pi, radioregs[i].address,
+ (u16) radioregs[i].init);
+ }
+
+ i++;
+ } while (radioregs[i].address != 0xffff);
+
+ return i;
+}
+
+uint
+wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
+ u16 core_offset)
+{
+ uint i = 0;
+ uint count = 0;
+
+ do {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if (radioregs[i].do_init_a) {
+ write_radio_reg(pi,
+ radioregs[i].
+ address | core_offset,
+ (u16) radioregs[i].init_a);
+ if (ISNPHY(pi) && (++count % 4 == 0))
+ WLC_PHY_WAR_PR51571(pi);
+ }
+ } else {
+ if (radioregs[i].do_init_g) {
+ write_radio_reg(pi,
+ radioregs[i].
+ address | core_offset,
+ (u16) radioregs[i].init_g);
+ if (ISNPHY(pi) && (++count % 4 == 0))
+ WLC_PHY_WAR_PR51571(pi);
+ }
+ }
+
+ i++;
+ } while (radioregs[i].address != 0xffff);
+
+ return i;
+}
+
+void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
+{
+#define DUMMY_PKT_LEN 20
+ d11regs_t *regs = pi->regs;
+ int i, count;
+ u8 ofdmpkt[DUMMY_PKT_LEN] = {
+ 0xcc, 0x01, 0x02, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
+ };
+ u8 cckpkt[DUMMY_PKT_LEN] = {
+ 0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
+ };
+ u32 *dummypkt;
+
+ dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
+ wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
+ dummypkt);
+
+ W_REG(®s->xmtsel, 0);
+
+ if (D11REV_GE(pi->sh->corerev, 11))
+ W_REG(®s->wepctl, 0x100);
+ else
+ W_REG(®s->wepctl, 0);
+
+ W_REG(®s->txe_phyctl, (ofdm ? 1 : 0) | PHY_TXC_ANT_0);
+ if (ISNPHY(pi) || ISLCNPHY(pi)) {
+ W_REG(®s->txe_phyctl1, 0x1A02);
+ }
+
+ W_REG(®s->txe_wm_0, 0);
+ W_REG(®s->txe_wm_1, 0);
+
+ W_REG(®s->xmttplatetxptr, 0);
+ W_REG(®s->xmttxcnt, DUMMY_PKT_LEN);
+
+ W_REG(®s->xmtsel, ((8 << 8) | (1 << 5) | (1 << 2) | 2));
+
+ W_REG(®s->txe_ctl, 0);
+
+ if (!pa_on) {
+ if (ISNPHY(pi))
+ wlc_phy_pa_override_nphy(pi, OFF);
+ }
+
+ if (ISNPHY(pi) || ISLCNPHY(pi))
+ W_REG(®s->txe_aux, 0xD0);
+ else
+ W_REG(®s->txe_aux, ((1 << 5) | (1 << 4)));
+
+ (void)R_REG(®s->txe_aux);
+
+ i = 0;
+ count = ofdm ? 30 : 250;
+
+ if (ISSIM_ENAB(pi->sh->sih)) {
+ count *= 100;
+ }
+
+ while ((i++ < count)
+ && (R_REG(®s->txe_status) & (1 << 7))) {
+ udelay(10);
+ }
+
+ i = 0;
+
+ while ((i++ < 10)
+ && ((R_REG(®s->txe_status) & (1 << 10)) == 0)) {
+ udelay(10);
+ }
+
+ i = 0;
+
+ while ((i++ < 10) && ((R_REG(®s->ifsstat) & (1 << 8))))
+ udelay(10);
+
+ if (!pa_on) {
+ if (ISNPHY(pi))
+ wlc_phy_pa_override_nphy(pi, ON);
+ }
+}
+
+void wlc_phy_hold_upd(wlc_phy_t *pih, mbool id, bool set)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (set) {
+ mboolset(pi->measure_hold, id);
+ } else {
+ mboolclr(pi->measure_hold, id);
+ }
+
+ return;
+}
+
+void wlc_phy_mute_upd(wlc_phy_t *pih, bool mute, mbool flags)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (mute) {
+ mboolset(pi->measure_hold, PHY_HOLD_FOR_MUTE);
+ } else {
+ mboolclr(pi->measure_hold, PHY_HOLD_FOR_MUTE);
+ }
+
+ if (!mute && (flags & PHY_MUTE_FOR_PREISM))
+ pi->nphy_perical_last = pi->sh->now - pi->sh->glacial_timer;
+ return;
+}
+
+void wlc_phy_clear_tssi(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (ISNPHY(pi)) {
+ return;
+ } else {
+ wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_0, NULL_TSSI_W);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_1, NULL_TSSI_W);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_0, NULL_TSSI_W);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_1, NULL_TSSI_W);
+ }
+}
+
+static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi)
+{
+ return false;
+}
+
+void wlc_phy_switch_radio(wlc_phy_t *pih, bool on)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ {
+ uint mc;
+
+ mc = R_REG(&pi->regs->maccontrol);
+ }
+
+ if (ISNPHY(pi)) {
+ wlc_phy_switch_radio_nphy(pi, on);
+
+ } else if (ISLCNPHY(pi)) {
+ if (on) {
+ and_phy_reg(pi, 0x44c,
+ ~((0x1 << 8) |
+ (0x1 << 9) |
+ (0x1 << 10) | (0x1 << 11) | (0x1 << 12)));
+ and_phy_reg(pi, 0x4b0, ~((0x1 << 3) | (0x1 << 11)));
+ and_phy_reg(pi, 0x4f9, ~(0x1 << 3));
+ } else {
+ and_phy_reg(pi, 0x44d,
+ ~((0x1 << 10) |
+ (0x1 << 11) |
+ (0x1 << 12) | (0x1 << 13) | (0x1 << 14)));
+ or_phy_reg(pi, 0x44c,
+ (0x1 << 8) |
+ (0x1 << 9) |
+ (0x1 << 10) | (0x1 << 11) | (0x1 << 12));
+
+ and_phy_reg(pi, 0x4b7, ~((0x7f << 8)));
+ and_phy_reg(pi, 0x4b1, ~((0x1 << 13)));
+ or_phy_reg(pi, 0x4b0, (0x1 << 3) | (0x1 << 11));
+ and_phy_reg(pi, 0x4fa, ~((0x1 << 3)));
+ or_phy_reg(pi, 0x4f9, (0x1 << 3));
+ }
+ }
+}
+
+u16 wlc_phy_bw_state_get(wlc_phy_t *ppi)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ return pi->bw;
+}
+
+void wlc_phy_bw_state_set(wlc_phy_t *ppi, u16 bw)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ pi->bw = bw;
+}
+
+void wlc_phy_chanspec_radio_set(wlc_phy_t *ppi, chanspec_t newch)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ pi->radio_chanspec = newch;
+
+}
+
+chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ return pi->radio_chanspec;
+}
+
+void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ u16 m_cur_channel;
+ chansetfn_t chanspec_set = NULL;
+
+ m_cur_channel = CHSPEC_CHANNEL(chanspec);
+ if (CHSPEC_IS5G(chanspec))
+ m_cur_channel |= D11_CURCHANNEL_5G;
+ if (CHSPEC_IS40(chanspec))
+ m_cur_channel |= D11_CURCHANNEL_40;
+ wlapi_bmac_write_shm(pi->sh->physhim, M_CURCHANNEL, m_cur_channel);
+
+ chanspec_set = pi->pi_fptr.chanset;
+ if (chanspec_set)
+ (*chanspec_set) (pi, chanspec);
+
+}
+
+int wlc_phy_chanspec_freq2bandrange_lpssn(uint freq)
+{
+ int range = -1;
+
+ if (freq < 2500)
+ range = WL_CHAN_FREQ_RANGE_2G;
+ else if (freq <= 5320)
+ range = WL_CHAN_FREQ_RANGE_5GL;
+ else if (freq <= 5700)
+ range = WL_CHAN_FREQ_RANGE_5GM;
+ else
+ range = WL_CHAN_FREQ_RANGE_5GH;
+
+ return range;
+}
+
+int wlc_phy_chanspec_bandrange_get(phy_info_t *pi, chanspec_t chanspec)
+{
+ int range = -1;
+ uint channel = CHSPEC_CHANNEL(chanspec);
+ uint freq = wlc_phy_channel2freq(channel);
+
+ if (ISNPHY(pi)) {
+ range = wlc_phy_get_chan_freq_range_nphy(pi, channel);
+ } else if (ISLCNPHY(pi)) {
+ range = wlc_phy_chanspec_freq2bandrange_lpssn(freq);
+ }
+
+ return range;
+}
+
+void wlc_phy_chanspec_ch14_widefilter_set(wlc_phy_t *ppi, bool wide_filter)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ pi->channel_14_wide_filter = wide_filter;
+
+}
+
+int wlc_phy_channel2freq(uint channel)
+{
+ uint i;
+
+ for (i = 0; i < ARRAY_SIZE(chan_info_all); i++)
+ if (chan_info_all[i].chan == channel)
+ return chan_info_all[i].freq;
+ return 0;
+}
+
+void
+wlc_phy_chanspec_band_validch(wlc_phy_t *ppi, uint band, chanvec_t *channels)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ uint i;
+ uint channel;
+
+ memset(channels, 0, sizeof(chanvec_t));
+
+ for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
+ channel = chan_info_all[i].chan;
+
+ if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
+ && (channel <= LAST_REF5_CHANNUM))
+ continue;
+
+ if (((band == WLC_BAND_2G) && (channel <= CH_MAX_2G_CHANNEL)) ||
+ ((band == WLC_BAND_5G) && (channel > CH_MAX_2G_CHANNEL)))
+ setbit(channels->vec, channel);
+ }
+}
+
+chanspec_t wlc_phy_chanspec_band_firstch(wlc_phy_t *ppi, uint band)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ uint i;
+ uint channel;
+ chanspec_t chspec;
+
+ for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
+ channel = chan_info_all[i].chan;
+
+ if (ISNPHY(pi) && IS40MHZ(pi)) {
+ uint j;
+
+ for (j = 0; j < ARRAY_SIZE(chan_info_all); j++) {
+ if (chan_info_all[j].chan ==
+ channel + CH_10MHZ_APART)
+ break;
+ }
+
+ if (j == ARRAY_SIZE(chan_info_all))
+ continue;
+
+ channel = UPPER_20_SB(channel);
+ chspec =
+ channel | WL_CHANSPEC_BW_40 |
+ WL_CHANSPEC_CTL_SB_LOWER;
+ if (band == WLC_BAND_2G)
+ chspec |= WL_CHANSPEC_BAND_2G;
+ else
+ chspec |= WL_CHANSPEC_BAND_5G;
+ } else
+ chspec = CH20MHZ_CHSPEC(channel);
+
+ if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
+ && (channel <= LAST_REF5_CHANNUM))
+ continue;
+
+ if (((band == WLC_BAND_2G) && (channel <= CH_MAX_2G_CHANNEL)) ||
+ ((band == WLC_BAND_5G) && (channel > CH_MAX_2G_CHANNEL)))
+ return chspec;
+ }
+
+ return (chanspec_t) INVCHANSPEC;
+}
+
+int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ *qdbm = pi->tx_user_target[0];
+ if (override != NULL)
+ *override = pi->txpwroverride;
+ return 0;
+}
+
+void wlc_phy_txpower_target_set(wlc_phy_t *ppi, struct txpwr_limits *txpwr)
+{
+ bool mac_enabled = false;
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ memcpy(&pi->tx_user_target[TXP_FIRST_CCK],
+ &txpwr->cck[0], WLC_NUM_RATES_CCK);
+
+ memcpy(&pi->tx_user_target[TXP_FIRST_OFDM],
+ &txpwr->ofdm[0], WLC_NUM_RATES_OFDM);
+ memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_20_CDD],
+ &txpwr->ofdm_cdd[0], WLC_NUM_RATES_OFDM);
+
+ memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_SISO],
+ &txpwr->ofdm_40_siso[0], WLC_NUM_RATES_OFDM);
+ memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_CDD],
+ &txpwr->ofdm_40_cdd[0], WLC_NUM_RATES_OFDM);
+
+ memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SISO],
+ &txpwr->mcs_20_siso[0], WLC_NUM_RATES_MCS_1_STREAM);
+ memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_CDD],
+ &txpwr->mcs_20_cdd[0], WLC_NUM_RATES_MCS_1_STREAM);
+ memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_STBC],
+ &txpwr->mcs_20_stbc[0], WLC_NUM_RATES_MCS_1_STREAM);
+ memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SDM],
+ &txpwr->mcs_20_mimo[0], WLC_NUM_RATES_MCS_2_STREAM);
+
+ memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SISO],
+ &txpwr->mcs_40_siso[0], WLC_NUM_RATES_MCS_1_STREAM);
+ memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_CDD],
+ &txpwr->mcs_40_cdd[0], WLC_NUM_RATES_MCS_1_STREAM);
+ memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_STBC],
+ &txpwr->mcs_40_stbc[0], WLC_NUM_RATES_MCS_1_STREAM);
+ memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],
+ &txpwr->mcs_40_mimo[0], WLC_NUM_RATES_MCS_2_STREAM);
+
+ if (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC)
+ mac_enabled = true;
+
+ if (mac_enabled)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ wlc_phy_txpower_recalc_target(pi);
+ wlc_phy_cal_txpower_recalc_sw(pi);
+
+ if (mac_enabled)
+ wlapi_enable_mac(pi->sh->physhim);
+}
+
+int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ int i;
+
+ if (qdbm > 127)
+ return 5;
+
+ for (i = 0; i < TXP_NUM_RATES; i++)
+ pi->tx_user_target[i] = (u8) qdbm;
+
+ pi->txpwroverride = false;
+
+ if (pi->sh->up) {
+ if (!SCAN_INPROG_PHY(pi)) {
+ bool suspend;
+
+ suspend =
+ (0 ==
+ (R_REG(&pi->regs->maccontrol) &
+ MCTL_EN_MAC));
+
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ wlc_phy_txpower_recalc_target(pi);
+ wlc_phy_cal_txpower_recalc_sw(pi);
+
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+ }
+ }
+ return 0;
+}
+
+void
+wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint channel, u8 *min_pwr,
+ u8 *max_pwr, int txp_rate_idx)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ uint i;
+
+ *min_pwr = pi->min_txpower * WLC_TXPWR_DB_FACTOR;
+
+ if (ISNPHY(pi)) {
+ if (txp_rate_idx < 0)
+ txp_rate_idx = TXP_FIRST_CCK;
+ wlc_phy_txpower_sromlimit_get_nphy(pi, channel, max_pwr,
+ (u8) txp_rate_idx);
+
+ } else if ((channel <= CH_MAX_2G_CHANNEL)) {
+ if (txp_rate_idx < 0)
+ txp_rate_idx = TXP_FIRST_CCK;
+ *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
+ } else {
+
+ *max_pwr = WLC_TXPWR_MAX;
+
+ if (txp_rate_idx < 0)
+ txp_rate_idx = TXP_FIRST_OFDM;
+
+ for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
+ if (channel == chan_info_all[i].chan) {
+ break;
+ }
+ }
+
+ if (pi->hwtxpwr) {
+ *max_pwr = pi->hwtxpwr[i];
+ } else {
+
+ if ((i >= FIRST_MID_5G_CHAN) && (i <= LAST_MID_5G_CHAN))
+ *max_pwr =
+ pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
+ if ((i >= FIRST_HIGH_5G_CHAN)
+ && (i <= LAST_HIGH_5G_CHAN))
+ *max_pwr =
+ pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
+ if ((i >= FIRST_LOW_5G_CHAN) && (i <= LAST_LOW_5G_CHAN))
+ *max_pwr =
+ pi->tx_srom_max_rate_5g_low[txp_rate_idx];
+ }
+ }
+}
+
+void
+wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan, u8 *max_txpwr,
+ u8 *min_txpwr)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ u8 tx_pwr_max = 0;
+ u8 tx_pwr_min = 255;
+ u8 max_num_rate;
+ u8 maxtxpwr, mintxpwr, rate, pactrl;
+
+ pactrl = 0;
+
+ max_num_rate = ISNPHY(pi) ? TXP_NUM_RATES :
+ ISLCNPHY(pi) ? (TXP_LAST_SISO_MCS_20 + 1) : (TXP_LAST_OFDM + 1);
+
+ for (rate = 0; rate < max_num_rate; rate++) {
+
+ wlc_phy_txpower_sromlimit(ppi, chan, &mintxpwr, &maxtxpwr,
+ rate);
+
+ maxtxpwr = (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
+
+ maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
+
+ tx_pwr_max = max(tx_pwr_max, maxtxpwr);
+ tx_pwr_min = min(tx_pwr_min, maxtxpwr);
+ }
+ *max_txpwr = tx_pwr_max;
+ *min_txpwr = tx_pwr_min;
+}
+
+void
+wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint bandunit, s32 *max_pwr,
+ s32 *min_pwr, u32 *step_pwr)
+{
+ return;
+}
+
+u8 wlc_phy_txpower_get_target_min(wlc_phy_t *ppi)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ return pi->tx_power_min;
+}
+
+u8 wlc_phy_txpower_get_target_max(wlc_phy_t *ppi)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ return pi->tx_power_max;
+}
+
+void wlc_phy_txpower_recalc_target(phy_info_t *pi)
+{
+ u8 maxtxpwr, mintxpwr, rate, pactrl;
+ uint target_chan;
+ u8 tx_pwr_target[TXP_NUM_RATES];
+ u8 tx_pwr_max = 0;
+ u8 tx_pwr_min = 255;
+ u8 tx_pwr_max_rate_ind = 0;
+ u8 max_num_rate;
+ u8 start_rate = 0;
+ chanspec_t chspec;
+ u32 band = CHSPEC2WLC_BAND(pi->radio_chanspec);
+ initfn_t txpwr_recalc_fn = NULL;
+
+ chspec = pi->radio_chanspec;
+ if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_NONE)
+ target_chan = CHSPEC_CHANNEL(chspec);
+ else if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER)
+ target_chan = UPPER_20_SB(CHSPEC_CHANNEL(chspec));
+ else
+ target_chan = LOWER_20_SB(CHSPEC_CHANNEL(chspec));
+
+ pactrl = 0;
+ if (ISLCNPHY(pi)) {
+ u32 offset_mcs, i;
+
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ offset_mcs = pi->mcs40_po;
+ for (i = TXP_FIRST_SISO_MCS_20;
+ i <= TXP_LAST_SISO_MCS_20; i++) {
+ pi->tx_srom_max_rate_2g[i - 8] =
+ pi->tx_srom_max_2g -
+ ((offset_mcs & 0xf) * 2);
+ offset_mcs >>= 4;
+ }
+ } else {
+ offset_mcs = pi->mcs20_po;
+ for (i = TXP_FIRST_SISO_MCS_20;
+ i <= TXP_LAST_SISO_MCS_20; i++) {
+ pi->tx_srom_max_rate_2g[i - 8] =
+ pi->tx_srom_max_2g -
+ ((offset_mcs & 0xf) * 2);
+ offset_mcs >>= 4;
+ }
+ }
+ }
+#if WL11N
+ max_num_rate = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
+ ((ISLCNPHY(pi)) ?
+ (TXP_LAST_SISO_MCS_20 + 1) : (TXP_LAST_OFDM + 1)));
+#else
+ max_num_rate = ((ISNPHY(pi)) ? (TXP_NUM_RATES) : (TXP_LAST_OFDM + 1));
+#endif
+
+ wlc_phy_upd_env_txpwr_rate_limits(pi, band);
+
+ for (rate = start_rate; rate < max_num_rate; rate++) {
+
+ tx_pwr_target[rate] = pi->tx_user_target[rate];
+
+ if (pi->user_txpwr_at_rfport) {
+ tx_pwr_target[rate] +=
+ wlc_user_txpwr_antport_to_rfport(pi, target_chan,
+ band, rate);
+ }
+
+ {
+
+ wlc_phy_txpower_sromlimit((wlc_phy_t *) pi, target_chan,
+ &mintxpwr, &maxtxpwr, rate);
+
+ maxtxpwr = min(maxtxpwr, pi->txpwr_limit[rate]);
+
+ maxtxpwr =
+ (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
+
+ maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
+
+ maxtxpwr = min(maxtxpwr, tx_pwr_target[rate]);
+
+ if (pi->txpwr_percent <= 100)
+ maxtxpwr = (maxtxpwr * pi->txpwr_percent) / 100;
+
+ tx_pwr_target[rate] = max(maxtxpwr, mintxpwr);
+ }
+
+ tx_pwr_target[rate] =
+ min(tx_pwr_target[rate], pi->txpwr_env_limit[rate]);
+
+ if (tx_pwr_target[rate] > tx_pwr_max)
+ tx_pwr_max_rate_ind = rate;
+
+ tx_pwr_max = max(tx_pwr_max, tx_pwr_target[rate]);
+ tx_pwr_min = min(tx_pwr_min, tx_pwr_target[rate]);
+ }
+
+ memset(pi->tx_power_offset, 0, sizeof(pi->tx_power_offset));
+ pi->tx_power_max = tx_pwr_max;
+ pi->tx_power_min = tx_pwr_min;
+ pi->tx_power_max_rate_ind = tx_pwr_max_rate_ind;
+ for (rate = 0; rate < max_num_rate; rate++) {
+
+ pi->tx_power_target[rate] = tx_pwr_target[rate];
+
+ if (!pi->hwpwrctrl || ISNPHY(pi)) {
+ pi->tx_power_offset[rate] =
+ pi->tx_power_max - pi->tx_power_target[rate];
+ } else {
+ pi->tx_power_offset[rate] =
+ pi->tx_power_target[rate] - pi->tx_power_min;
+ }
+ }
+
+ txpwr_recalc_fn = pi->pi_fptr.txpwrrecalc;
+ if (txpwr_recalc_fn)
+ (*txpwr_recalc_fn) (pi);
+}
+
+void
+wlc_phy_txpower_reg_limit_calc(phy_info_t *pi, struct txpwr_limits *txpwr,
+ chanspec_t chanspec)
+{
+ u8 tmp_txpwr_limit[2 * WLC_NUM_RATES_OFDM];
+ u8 *txpwr_ptr1 = NULL, *txpwr_ptr2 = NULL;
+ int rate_start_index = 0, rate1, rate2, k;
+
+ for (rate1 = WL_TX_POWER_CCK_FIRST, rate2 = 0;
+ rate2 < WL_TX_POWER_CCK_NUM; rate1++, rate2++)
+ pi->txpwr_limit[rate1] = txpwr->cck[rate2];
+
+ for (rate1 = WL_TX_POWER_OFDM_FIRST, rate2 = 0;
+ rate2 < WL_TX_POWER_OFDM_NUM; rate1++, rate2++)
+ pi->txpwr_limit[rate1] = txpwr->ofdm[rate2];
+
+ if (ISNPHY(pi)) {
+
+ for (k = 0; k < 4; k++) {
+ switch (k) {
+ case 0:
+
+ txpwr_ptr1 = txpwr->mcs_20_siso;
+ txpwr_ptr2 = txpwr->ofdm;
+ rate_start_index = WL_TX_POWER_OFDM_FIRST;
+ break;
+ case 1:
+
+ txpwr_ptr1 = txpwr->mcs_20_cdd;
+ txpwr_ptr2 = txpwr->ofdm_cdd;
+ rate_start_index = WL_TX_POWER_OFDM20_CDD_FIRST;
+ break;
+ case 2:
+
+ txpwr_ptr1 = txpwr->mcs_40_siso;
+ txpwr_ptr2 = txpwr->ofdm_40_siso;
+ rate_start_index =
+ WL_TX_POWER_OFDM40_SISO_FIRST;
+ break;
+ case 3:
+
+ txpwr_ptr1 = txpwr->mcs_40_cdd;
+ txpwr_ptr2 = txpwr->ofdm_40_cdd;
+ rate_start_index = WL_TX_POWER_OFDM40_CDD_FIRST;
+ break;
+ }
+
+ for (rate2 = 0; rate2 < WLC_NUM_RATES_OFDM; rate2++) {
+ tmp_txpwr_limit[rate2] = 0;
+ tmp_txpwr_limit[WLC_NUM_RATES_OFDM + rate2] =
+ txpwr_ptr1[rate2];
+ }
+ wlc_phy_mcs_to_ofdm_powers_nphy(tmp_txpwr_limit, 0,
+ WLC_NUM_RATES_OFDM - 1,
+ WLC_NUM_RATES_OFDM);
+ for (rate1 = rate_start_index, rate2 = 0;
+ rate2 < WLC_NUM_RATES_OFDM; rate1++, rate2++)
+ pi->txpwr_limit[rate1] =
+ min(txpwr_ptr2[rate2],
+ tmp_txpwr_limit[rate2]);
+ }
+
+ for (k = 0; k < 4; k++) {
+ switch (k) {
+ case 0:
+
+ txpwr_ptr1 = txpwr->ofdm;
+ txpwr_ptr2 = txpwr->mcs_20_siso;
+ rate_start_index = WL_TX_POWER_MCS20_SISO_FIRST;
+ break;
+ case 1:
+
+ txpwr_ptr1 = txpwr->ofdm_cdd;
+ txpwr_ptr2 = txpwr->mcs_20_cdd;
+ rate_start_index = WL_TX_POWER_MCS20_CDD_FIRST;
+ break;
+ case 2:
+
+ txpwr_ptr1 = txpwr->ofdm_40_siso;
+ txpwr_ptr2 = txpwr->mcs_40_siso;
+ rate_start_index = WL_TX_POWER_MCS40_SISO_FIRST;
+ break;
+ case 3:
+
+ txpwr_ptr1 = txpwr->ofdm_40_cdd;
+ txpwr_ptr2 = txpwr->mcs_40_cdd;
+ rate_start_index = WL_TX_POWER_MCS40_CDD_FIRST;
+ break;
+ }
+ for (rate2 = 0; rate2 < WLC_NUM_RATES_OFDM; rate2++) {
+ tmp_txpwr_limit[rate2] = 0;
+ tmp_txpwr_limit[WLC_NUM_RATES_OFDM + rate2] =
+ txpwr_ptr1[rate2];
+ }
+ wlc_phy_ofdm_to_mcs_powers_nphy(tmp_txpwr_limit, 0,
+ WLC_NUM_RATES_OFDM - 1,
+ WLC_NUM_RATES_OFDM);
+ for (rate1 = rate_start_index, rate2 = 0;
+ rate2 < WLC_NUM_RATES_MCS_1_STREAM;
+ rate1++, rate2++)
+ pi->txpwr_limit[rate1] =
+ min(txpwr_ptr2[rate2],
+ tmp_txpwr_limit[rate2]);
+ }
+
+ for (k = 0; k < 2; k++) {
+ switch (k) {
+ case 0:
+
+ rate_start_index = WL_TX_POWER_MCS20_STBC_FIRST;
+ txpwr_ptr1 = txpwr->mcs_20_stbc;
+ break;
+ case 1:
+
+ rate_start_index = WL_TX_POWER_MCS40_STBC_FIRST;
+ txpwr_ptr1 = txpwr->mcs_40_stbc;
+ break;
+ }
+ for (rate1 = rate_start_index, rate2 = 0;
+ rate2 < WLC_NUM_RATES_MCS_1_STREAM;
+ rate1++, rate2++)
+ pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
+ }
+
+ for (k = 0; k < 2; k++) {
+ switch (k) {
+ case 0:
+
+ rate_start_index = WL_TX_POWER_MCS20_SDM_FIRST;
+ txpwr_ptr1 = txpwr->mcs_20_mimo;
+ break;
+ case 1:
+
+ rate_start_index = WL_TX_POWER_MCS40_SDM_FIRST;
+ txpwr_ptr1 = txpwr->mcs_40_mimo;
+ break;
+ }
+ for (rate1 = rate_start_index, rate2 = 0;
+ rate2 < WLC_NUM_RATES_MCS_2_STREAM;
+ rate1++, rate2++)
+ pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
+ }
+
+ pi->txpwr_limit[WL_TX_POWER_MCS_32] = txpwr->mcs32;
+
+ pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST] =
+ min(pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST],
+ pi->txpwr_limit[WL_TX_POWER_MCS_32]);
+ pi->txpwr_limit[WL_TX_POWER_MCS_32] =
+ pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST];
+ }
+}
+
+void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ pi->txpwr_percent = txpwr_percent;
+}
+
+void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ pi->sh->machwcap = machwcap;
+}
+
+void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ u16 rxc;
+ rxc = 0;
+
+ if (start_end == ON) {
+ if (!ISNPHY(pi))
+ return;
+
+ if (NREV_IS(pi->pubpi.phy_rev, 3)
+ || NREV_IS(pi->pubpi.phy_rev, 4)) {
+ W_REG(&pi->regs->phyregaddr, 0xa0);
+ (void)R_REG(&pi->regs->phyregaddr);
+ rxc = R_REG(&pi->regs->phyregdata);
+ W_REG(&pi->regs->phyregdata,
+ (0x1 << 15) | rxc);
+ }
+ } else {
+ if (NREV_IS(pi->pubpi.phy_rev, 3)
+ || NREV_IS(pi->pubpi.phy_rev, 4)) {
+ W_REG(&pi->regs->phyregaddr, 0xa0);
+ (void)R_REG(&pi->regs->phyregaddr);
+ W_REG(&pi->regs->phyregdata, rxc);
+ }
+
+ wlc_phy_por_inform(ppi);
+ }
+}
+
+void
+wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *txpwr,
+ chanspec_t chanspec)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ wlc_phy_txpower_reg_limit_calc(pi, txpwr, chanspec);
+
+ if (ISLCNPHY(pi)) {
+ int i, j;
+ for (i = TXP_FIRST_OFDM_20_CDD, j = 0;
+ j < WLC_NUM_RATES_MCS_1_STREAM; i++, j++) {
+ if (txpwr->mcs_20_siso[j])
+ pi->txpwr_limit[i] = txpwr->mcs_20_siso[j];
+ else
+ pi->txpwr_limit[i] = txpwr->ofdm[j];
+ }
+ }
+
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ wlc_phy_txpower_recalc_target(pi);
+ wlc_phy_cal_txpower_recalc_sw(pi);
+ wlapi_enable_mac(pi->sh->physhim);
+}
+
+void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ pi->ofdm_rateset_war = war;
+}
+
+void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ pi->bf_preempt_4306 = bf_preempt;
+}
+
+void wlc_phy_txpower_update_shm(phy_info_t *pi)
+{
+ int j;
+ if (ISNPHY(pi)) {
+ return;
+ }
+
+ if (!pi->sh->clk)
+ return;
+
+ if (pi->hwpwrctrl) {
+ u16 offset;
+
+ wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N,
+ 1 << NUM_TSSI_FRAMES);
+
+ wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_TARGET,
+ pi->tx_power_min << NUM_TSSI_FRAMES);
+
+ wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_CUR,
+ pi->hwpwr_txcur);
+
+ for (j = TXP_FIRST_OFDM; j <= TXP_LAST_OFDM; j++) {
+ const u8 ucode_ofdm_rates[] = {
+ 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c
+ };
+ offset = wlapi_bmac_rate_shm_offset(pi->sh->physhim,
+ ucode_ofdm_rates[j -
+ TXP_FIRST_OFDM]);
+ wlapi_bmac_write_shm(pi->sh->physhim, offset + 6,
+ pi->tx_power_offset[j]);
+ wlapi_bmac_write_shm(pi->sh->physhim, offset + 14,
+ -(pi->tx_power_offset[j] / 2));
+ }
+
+ wlapi_bmac_mhf(pi->sh->physhim, MHF2, MHF2_HWPWRCTL,
+ MHF2_HWPWRCTL, WLC_BAND_ALL);
+ } else {
+ int i;
+
+ for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++)
+ pi->tx_power_offset[i] =
+ (u8) roundup(pi->tx_power_offset[i], 8);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET,
+ (u16) ((pi->
+ tx_power_offset[TXP_FIRST_OFDM]
+ + 7) >> 3));
+ }
+}
+
+bool wlc_phy_txpower_hw_ctrl_get(wlc_phy_t *ppi)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ if (ISNPHY(pi)) {
+ return pi->nphy_txpwrctrl;
+ } else {
+ return pi->hwpwrctrl;
+ }
+}
+
+void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ bool cur_hwpwrctrl = pi->hwpwrctrl;
+ bool suspend;
+
+ if (!pi->hwpwrctrl_capable) {
+ return;
+ }
+
+ pi->hwpwrctrl = hwpwrctrl;
+ pi->nphy_txpwrctrl = hwpwrctrl;
+ pi->txpwrctrl = hwpwrctrl;
+
+ if (ISNPHY(pi)) {
+ suspend =
+ (0 ==
+ (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
+ if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
+ wlc_phy_txpwr_fixpower_nphy(pi);
+ } else {
+
+ mod_phy_reg(pi, 0x1e7, (0x7f << 0),
+ pi->saved_txpwr_idx);
+ }
+
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+ } else if (hwpwrctrl != cur_hwpwrctrl) {
+
+ return;
+ }
+}
+
+void wlc_phy_txpower_ipa_upd(phy_info_t *pi)
+{
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ pi->ipa2g_on = (pi->srom_fem2g.extpagain == 2);
+ pi->ipa5g_on = (pi->srom_fem5g.extpagain == 2);
+ } else {
+ pi->ipa2g_on = false;
+ pi->ipa5g_on = false;
+ }
+}
+
+static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi);
+
+static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
+{
+ s16 tx0_status, tx1_status;
+ u16 estPower1, estPower2;
+ u8 pwr0, pwr1, adj_pwr0, adj_pwr1;
+ u32 est_pwr;
+
+ estPower1 = read_phy_reg(pi, 0x118);
+ estPower2 = read_phy_reg(pi, 0x119);
+
+ if ((estPower1 & (0x1 << 8))
+ == (0x1 << 8)) {
+ pwr0 = (u8) (estPower1 & (0xff << 0))
+ >> 0;
+ } else {
+ pwr0 = 0x80;
+ }
+
+ if ((estPower2 & (0x1 << 8))
+ == (0x1 << 8)) {
+ pwr1 = (u8) (estPower2 & (0xff << 0))
+ >> 0;
+ } else {
+ pwr1 = 0x80;
+ }
+
+ tx0_status = read_phy_reg(pi, 0x1ed);
+ tx1_status = read_phy_reg(pi, 0x1ee);
+
+ if ((tx0_status & (0x1 << 15))
+ == (0x1 << 15)) {
+ adj_pwr0 = (u8) (tx0_status & (0xff << 0))
+ >> 0;
+ } else {
+ adj_pwr0 = 0x80;
+ }
+ if ((tx1_status & (0x1 << 15))
+ == (0x1 << 15)) {
+ adj_pwr1 = (u8) (tx1_status & (0xff << 0))
+ >> 0;
+ } else {
+ adj_pwr1 = 0x80;
+ }
+
+ est_pwr =
+ (u32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) | adj_pwr1);
+ return est_pwr;
+}
+
+void
+wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power, uint channel)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ uint rate, num_rates;
+ u8 min_pwr, max_pwr;
+
+#if WL_TX_POWER_RATES != TXP_NUM_RATES
+#error "tx_power_t struct out of sync with this fn"
+#endif
+
+ if (ISNPHY(pi)) {
+ power->rf_cores = 2;
+ power->flags |= (WL_TX_POWER_F_MIMO);
+ if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
+ power->flags |=
+ (WL_TX_POWER_F_ENABLED | WL_TX_POWER_F_HW);
+ } else if (ISLCNPHY(pi)) {
+ power->rf_cores = 1;
+ power->flags |= (WL_TX_POWER_F_SISO);
+ if (pi->radiopwr_override == RADIOPWR_OVERRIDE_DEF)
+ power->flags |= WL_TX_POWER_F_ENABLED;
+ if (pi->hwpwrctrl)
+ power->flags |= WL_TX_POWER_F_HW;
+ }
+
+ num_rates = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
+ ((ISLCNPHY(pi)) ?
+ (TXP_LAST_OFDM_20_CDD + 1) : (TXP_LAST_OFDM + 1)));
+
+ for (rate = 0; rate < num_rates; rate++) {
+ power->user_limit[rate] = pi->tx_user_target[rate];
+ wlc_phy_txpower_sromlimit(ppi, channel, &min_pwr, &max_pwr,
+ rate);
+ power->board_limit[rate] = (u8) max_pwr;
+ power->target[rate] = pi->tx_power_target[rate];
+ }
+
+ if (ISNPHY(pi)) {
+ u32 est_pout;
+
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ wlc_phyreg_enter((wlc_phy_t *) pi);
+ est_pout = wlc_phy_txpower_est_power_nphy(pi);
+ wlc_phyreg_exit((wlc_phy_t *) pi);
+ wlapi_enable_mac(pi->sh->physhim);
+
+ power->est_Pout[0] = (est_pout >> 8) & 0xff;
+ power->est_Pout[1] = est_pout & 0xff;
+
+ power->est_Pout_act[0] = est_pout >> 24;
+ power->est_Pout_act[1] = (est_pout >> 16) & 0xff;
+
+ if (power->est_Pout[0] == 0x80)
+ power->est_Pout[0] = 0;
+ if (power->est_Pout[1] == 0x80)
+ power->est_Pout[1] = 0;
+
+ if (power->est_Pout_act[0] == 0x80)
+ power->est_Pout_act[0] = 0;
+ if (power->est_Pout_act[1] == 0x80)
+ power->est_Pout_act[1] = 0;
+
+ power->est_Pout_cck = 0;
+
+ power->tx_power_max[0] = pi->tx_power_max;
+ power->tx_power_max[1] = pi->tx_power_max;
+
+ power->tx_power_max_rate_ind[0] = pi->tx_power_max_rate_ind;
+ power->tx_power_max_rate_ind[1] = pi->tx_power_max_rate_ind;
+ } else if (!pi->hwpwrctrl) {
+ } else if (pi->sh->up) {
+
+ wlc_phyreg_enter(ppi);
+ if (ISLCNPHY(pi)) {
+
+ power->tx_power_max[0] = pi->tx_power_max;
+ power->tx_power_max[1] = pi->tx_power_max;
+
+ power->tx_power_max_rate_ind[0] =
+ pi->tx_power_max_rate_ind;
+ power->tx_power_max_rate_ind[1] =
+ pi->tx_power_max_rate_ind;
+
+ if (wlc_phy_tpc_isenabled_lcnphy(pi))
+ power->flags |=
+ (WL_TX_POWER_F_HW | WL_TX_POWER_F_ENABLED);
+ else
+ power->flags &=
+ ~(WL_TX_POWER_F_HW | WL_TX_POWER_F_ENABLED);
+
+ wlc_lcnphy_get_tssi(pi, (s8 *) &power->est_Pout[0],
+ (s8 *) &power->est_Pout_cck);
+ }
+ wlc_phyreg_exit(ppi);
+ }
+}
+
+void wlc_phy_antsel_type_set(wlc_phy_t *ppi, u8 antsel_type)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ pi->antsel_type = antsel_type;
+}
+
+bool wlc_phy_test_ison(wlc_phy_t *ppi)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ return pi->phytest_on;
+}
+
+void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ bool suspend;
+
+ pi->sh->rx_antdiv = val;
+
+ if (!(ISNPHY(pi) && D11REV_IS(pi->sh->corerev, 16))) {
+ if (val > ANT_RX_DIV_FORCE_1)
+ wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV,
+ MHF1_ANTDIV, WLC_BAND_ALL);
+ else
+ wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV, 0,
+ WLC_BAND_ALL);
+ }
+
+ if (ISNPHY(pi)) {
+
+ return;
+ }
+
+ if (!pi->sh->clk)
+ return;
+
+ suspend =
+ (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ if (ISLCNPHY(pi)) {
+ if (val > ANT_RX_DIV_FORCE_1) {
+ mod_phy_reg(pi, 0x410, (0x1 << 1), 0x01 << 1);
+ mod_phy_reg(pi, 0x410,
+ (0x1 << 0),
+ ((ANT_RX_DIV_START_1 == val) ? 1 : 0) << 0);
+ } else {
+ mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1);
+ mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0);
+ }
+ }
+
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+
+ return;
+}
+
+static bool
+wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr, s8 *pwr_ant)
+{
+ s8 cmplx_pwr_dbm[PHY_CORE_MAX];
+ u8 i;
+
+ memset((u8 *) cmplx_pwr_dbm, 0, sizeof(cmplx_pwr_dbm));
+ wlc_phy_compute_dB(cmplx_pwr, cmplx_pwr_dbm, pi->pubpi.phy_corenum);
+
+ for (i = 0; i < pi->pubpi.phy_corenum; i++) {
+ if (NREV_GE(pi->pubpi.phy_rev, 3))
+ cmplx_pwr_dbm[i] += (s8) PHY_NOISE_OFFSETFACT_4322;
+ else
+
+ cmplx_pwr_dbm[i] += (s8) (16 - (15) * 3 - 70);
+ }
+
+ for (i = 0; i < pi->pubpi.phy_corenum; i++) {
+ pi->nphy_noise_win[i][pi->nphy_noise_index] = cmplx_pwr_dbm[i];
+ pwr_ant[i] = cmplx_pwr_dbm[i];
+ }
+ pi->nphy_noise_index =
+ MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
+ return true;
+}
+
+static void
+wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
+ bool sampling_in_progress = (pi->phynoise_state != 0);
+ bool wait_for_intr = true;
+
+ if (NORADIO_ENAB(pi->pubpi)) {
+ return;
+ }
+
+ switch (reason) {
+ case PHY_NOISE_SAMPLE_MON:
+
+ pi->phynoise_chan_watchdog = ch;
+ pi->phynoise_state |= PHY_NOISE_STATE_MON;
+
+ break;
+
+ case PHY_NOISE_SAMPLE_EXTERNAL:
+
+ pi->phynoise_state |= PHY_NOISE_STATE_EXTERNAL;
+ break;
+
+ default:
+ break;
+ }
+
+ if (sampling_in_progress)
+ return;
+
+ pi->phynoise_now = pi->sh->now;
+
+ if (pi->phy_fixed_noise) {
+ if (ISNPHY(pi)) {
+ pi->nphy_noise_win[WL_ANT_IDX_1][pi->nphy_noise_index] =
+ PHY_NOISE_FIXED_VAL_NPHY;
+ pi->nphy_noise_win[WL_ANT_IDX_2][pi->nphy_noise_index] =
+ PHY_NOISE_FIXED_VAL_NPHY;
+ pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
+ PHY_NOISE_WINDOW_SZ);
+
+ noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
+ } else {
+
+ noise_dbm = PHY_NOISE_FIXED_VAL;
+ }
+
+ wait_for_intr = false;
+ goto done;
+ }
+
+ if (ISLCNPHY(pi)) {
+ if (!pi->phynoise_polling
+ || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
+ wlapi_bmac_write_shm(pi->sh->physhim, M_JSSI_0, 0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
+
+ OR_REG(&pi->regs->maccommand,
+ MCMD_BG_NOISE);
+ } else {
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ wlc_lcnphy_deaf_mode(pi, (bool) 0);
+ noise_dbm = (s8) wlc_lcnphy_rx_signal_power(pi, 20);
+ wlc_lcnphy_deaf_mode(pi, (bool) 1);
+ wlapi_enable_mac(pi->sh->physhim);
+ wait_for_intr = false;
+ }
+ } else if (ISNPHY(pi)) {
+ if (!pi->phynoise_polling
+ || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
+
+ wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
+
+ OR_REG(&pi->regs->maccommand,
+ MCMD_BG_NOISE);
+ } else {
+ phy_iq_est_t est[PHY_CORE_MAX];
+ u32 cmplx_pwr[PHY_CORE_MAX];
+ s8 noise_dbm_ant[PHY_CORE_MAX];
+ u16 log_num_samps, num_samps, classif_state = 0;
+ u8 wait_time = 32;
+ u8 wait_crs = 0;
+ u8 i;
+
+ memset((u8 *) est, 0, sizeof(est));
+ memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
+ memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
+
+ log_num_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
+ num_samps = 1 << log_num_samps;
+
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
+ wlc_phy_classifier_nphy(pi, 3, 0);
+ wlc_phy_rx_iq_est_nphy(pi, est, num_samps, wait_time,
+ wait_crs);
+ wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
+ wlapi_enable_mac(pi->sh->physhim);
+
+ for (i = 0; i < pi->pubpi.phy_corenum; i++)
+ cmplx_pwr[i] =
+ (est[i].i_pwr +
+ est[i].q_pwr) >> log_num_samps;
+
+ wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
+
+ for (i = 0; i < pi->pubpi.phy_corenum; i++) {
+ pi->nphy_noise_win[i][pi->nphy_noise_index] =
+ noise_dbm_ant[i];
+
+ if (noise_dbm_ant[i] > noise_dbm)
+ noise_dbm = noise_dbm_ant[i];
+ }
+ pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
+ PHY_NOISE_WINDOW_SZ);
+
+ wait_for_intr = false;
+ }
+ }
+
+ done:
+
+ if (!wait_for_intr)
+ wlc_phy_noise_cb(pi, ch, noise_dbm);
+
+}
+
+void wlc_phy_noise_sample_request_external(wlc_phy_t *pih)
+{
+ u8 channel;
+
+ channel = CHSPEC_CHANNEL(wlc_phy_chanspec_get(pih));
+
+ wlc_phy_noise_sample_request(pih, PHY_NOISE_SAMPLE_EXTERNAL, channel);
+}
+
+static void wlc_phy_noise_cb(phy_info_t *pi, u8 channel, s8 noise_dbm)
+{
+ if (!pi->phynoise_state)
+ return;
+
+ if (pi->phynoise_state & PHY_NOISE_STATE_MON) {
+ if (pi->phynoise_chan_watchdog == channel) {
+ pi->sh->phy_noise_window[pi->sh->phy_noise_index] =
+ noise_dbm;
+ pi->sh->phy_noise_index =
+ MODINC(pi->sh->phy_noise_index, MA_WINDOW_SZ);
+ }
+ pi->phynoise_state &= ~PHY_NOISE_STATE_MON;
+ }
+
+ if (pi->phynoise_state & PHY_NOISE_STATE_EXTERNAL) {
+ pi->phynoise_state &= ~PHY_NOISE_STATE_EXTERNAL;
+ }
+
+}
+
+static s8 wlc_phy_noise_read_shmem(phy_info_t *pi)
+{
+ u32 cmplx_pwr[PHY_CORE_MAX];
+ s8 noise_dbm_ant[PHY_CORE_MAX];
+ u16 lo, hi;
+ u32 cmplx_pwr_tot = 0;
+ s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
+ u8 idx, core;
+
+ memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
+ memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
+
+ for (idx = 0, core = 0; core < pi->pubpi.phy_corenum; idx += 2, core++) {
+ lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP(idx));
+ hi = wlapi_bmac_read_shm(pi->sh->physhim,
+ M_PWRIND_MAP(idx + 1));
+ cmplx_pwr[core] = (hi << 16) + lo;
+ cmplx_pwr_tot += cmplx_pwr[core];
+ if (cmplx_pwr[core] == 0) {
+ noise_dbm_ant[core] = PHY_NOISE_FIXED_VAL_NPHY;
+ } else
+ cmplx_pwr[core] >>= PHY_NOISE_SAMPLE_LOG_NUM_UCODE;
+ }
+
+ if (cmplx_pwr_tot != 0)
+ wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ pi->nphy_noise_win[core][pi->nphy_noise_index] =
+ noise_dbm_ant[core];
+
+ if (noise_dbm_ant[core] > noise_dbm)
+ noise_dbm = noise_dbm_ant[core];
+ }
+ pi->nphy_noise_index =
+ MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
+
+ return noise_dbm;
+
+}
+
+void wlc_phy_noise_sample_intr(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ u16 jssi_aux;
+ u8 channel = 0;
+ s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
+
+ if (ISLCNPHY(pi)) {
+ u32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
+ u16 lo, hi;
+ s32 pwr_offset_dB, gain_dB;
+ u16 status_0, status_1;
+
+ jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
+ channel = jssi_aux & D11_CURCHANNEL_MAX;
+
+ lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP0);
+ hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP1);
+ cmplx_pwr0 = (hi << 16) + lo;
+
+ lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP2);
+ hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP3);
+ cmplx_pwr1 = (hi << 16) + lo;
+ cmplx_pwr = (cmplx_pwr0 + cmplx_pwr1) >> 6;
+
+ status_0 = 0x44;
+ status_1 = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_0);
+ if ((cmplx_pwr > 0 && cmplx_pwr < 500)
+ && ((status_1 & 0xc000) == 0x4000)) {
+
+ wlc_phy_compute_dB(&cmplx_pwr, &noise_dbm,
+ pi->pubpi.phy_corenum);
+ pwr_offset_dB = (read_phy_reg(pi, 0x434) & 0xFF);
+ if (pwr_offset_dB > 127)
+ pwr_offset_dB -= 256;
+
+ noise_dbm += (s8) (pwr_offset_dB - 30);
+
+ gain_dB = (status_0 & 0x1ff);
+ noise_dbm -= (s8) (gain_dB);
+ } else {
+ noise_dbm = PHY_NOISE_FIXED_VAL_LCNPHY;
+ }
+ } else if (ISNPHY(pi)) {
+
+ jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
+ channel = jssi_aux & D11_CURCHANNEL_MAX;
+
+ noise_dbm = wlc_phy_noise_read_shmem(pi);
+ }
+
+ wlc_phy_noise_cb(pi, channel, noise_dbm);
+
+}
+
+s8 lcnphy_gain_index_offset_for_pkt_rssi[] = {
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 8,
+ 9,
+ 10,
+ 8,
+ 8,
+ 7,
+ 7,
+ 1,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 1,
+ 1,
+ 0,
+ 0,
+ 0,
+ 0
+};
+
+void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
+{
+ u8 msb, secondmsb, i;
+ u32 tmp;
+
+ for (i = 0; i < core; i++) {
+ secondmsb = 0;
+ tmp = cmplx_pwr[i];
+ msb = fls(tmp);
+ if (msb)
+ secondmsb = (u8) ((tmp >> (--msb - 1)) & 1);
+ p_cmplx_pwr_dB[i] = (s8) (3 * msb + 2 * secondmsb);
+ }
+}
+
+void wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx)
+{
+ wlc_d11rxhdr_t *wlc_rxhdr = (wlc_d11rxhdr_t *) ctx;
+ d11rxhdr_t *rxh = &wlc_rxhdr->rxhdr;
+ int rssi = le16_to_cpu(rxh->PhyRxStatus_1) & PRXS1_JSSI_MASK;
+ uint radioid = pih->radioid;
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (NORADIO_ENAB(pi->pubpi)) {
+ rssi = WLC_RSSI_INVALID;
+ goto end;
+ }
+
+ if ((pi->sh->corerev >= 11)
+ && !(le16_to_cpu(rxh->RxStatus2) & RXS_PHYRXST_VALID)) {
+ rssi = WLC_RSSI_INVALID;
+ goto end;
+ }
+
+ if (ISLCNPHY(pi)) {
+ u8 gidx = (le16_to_cpu(rxh->PhyRxStatus_2) & 0xFC00) >> 10;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (rssi > 127)
+ rssi -= 256;
+
+ rssi = rssi + lcnphy_gain_index_offset_for_pkt_rssi[gidx];
+ if ((rssi > -46) && (gidx > 18))
+ rssi = rssi + 7;
+
+ rssi = rssi + pi_lcn->lcnphy_pkteng_rssi_slope;
+
+ rssi = rssi + 2;
+
+ }
+
+ if (ISLCNPHY(pi)) {
+
+ if (rssi > 127)
+ rssi -= 256;
+ } else if (radioid == BCM2055_ID || radioid == BCM2056_ID
+ || radioid == BCM2057_ID) {
+ rssi = wlc_phy_rssi_compute_nphy(pi, wlc_rxhdr);
+ }
+
+ end:
+ wlc_rxhdr->rssi = (s8) rssi;
+}
+
+void wlc_phy_freqtrack_start(wlc_phy_t *pih)
+{
+ return;
+}
+
+void wlc_phy_freqtrack_end(wlc_phy_t *pih)
+{
+ return;
+}
+
+void wlc_phy_set_deaf(wlc_phy_t *ppi, bool user_flag)
+{
+ phy_info_t *pi;
+ pi = (phy_info_t *) ppi;
+
+ if (ISLCNPHY(pi))
+ wlc_lcnphy_deaf_mode(pi, true);
+ else if (ISNPHY(pi))
+ wlc_nphy_deaf_mode(pi, true);
+}
+
+void wlc_phy_watchdog(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ bool delay_phy_cal = false;
+ pi->sh->now++;
+
+ if (!pi->watchdog_override)
+ return;
+
+ if (!(SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi))) {
+ wlc_phy_noise_sample_request((wlc_phy_t *) pi,
+ PHY_NOISE_SAMPLE_MON,
+ CHSPEC_CHANNEL(pi->
+ radio_chanspec));
+ }
+
+ if (pi->phynoise_state && (pi->sh->now - pi->phynoise_now) > 5) {
+ pi->phynoise_state = 0;
+ }
+
+ if ((!pi->phycal_txpower) ||
+ ((pi->sh->now - pi->phycal_txpower) >= pi->sh->fast_timer)) {
+
+ if (!SCAN_INPROG_PHY(pi) && wlc_phy_cal_txpower_recalc_sw(pi)) {
+ pi->phycal_txpower = pi->sh->now;
+ }
+ }
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ if ((SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
+ || ASSOC_INPROG_PHY(pi)))
+ return;
+
+ if (ISNPHY(pi) && !pi->disable_percal && !delay_phy_cal) {
+
+ if ((pi->nphy_perical != PHY_PERICAL_DISABLE) &&
+ (pi->nphy_perical != PHY_PERICAL_MANUAL) &&
+ ((pi->sh->now - pi->nphy_perical_last) >=
+ pi->sh->glacial_timer))
+ wlc_phy_cal_perical((wlc_phy_t *) pi,
+ PHY_PERICAL_WATCHDOG);
+
+ wlc_phy_txpwr_papd_cal_nphy(pi);
+ }
+
+ if (ISLCNPHY(pi)) {
+ if (pi->phy_forcecal ||
+ ((pi->sh->now - pi->phy_lastcal) >=
+ pi->sh->glacial_timer)) {
+ if (!(SCAN_RM_IN_PROGRESS(pi) || ASSOC_INPROG_PHY(pi)))
+ wlc_lcnphy_calib_modes(pi,
+ LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
+ if (!
+ (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
+ || ASSOC_INPROG_PHY(pi)
+ || pi->carrier_suppr_disable
+ || pi->disable_percal))
+ wlc_lcnphy_calib_modes(pi,
+ PHY_PERICAL_WATCHDOG);
+ }
+ }
+}
+
+void wlc_phy_BSSinit(wlc_phy_t *pih, bool bonlyap, int rssi)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ uint i;
+ uint k;
+
+ for (i = 0; i < MA_WINDOW_SZ; i++) {
+ pi->sh->phy_noise_window[i] = (s8) (rssi & 0xff);
+ }
+ if (ISLCNPHY(pi)) {
+ for (i = 0; i < MA_WINDOW_SZ; i++)
+ pi->sh->phy_noise_window[i] =
+ PHY_NOISE_FIXED_VAL_LCNPHY;
+ }
+ pi->sh->phy_noise_index = 0;
+
+ for (i = 0; i < PHY_NOISE_WINDOW_SZ; i++) {
+ for (k = WL_ANT_IDX_1; k < WL_ANT_RX_MAX; k++)
+ pi->nphy_noise_win[k][i] = PHY_NOISE_FIXED_VAL_NPHY;
+ }
+ pi->nphy_noise_index = 0;
+}
+
+void
+wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag)
+{
+ *eps_imag = (epsilon >> 13);
+ if (*eps_imag > 0xfff)
+ *eps_imag -= 0x2000;
+
+ *eps_real = (epsilon & 0x1fff);
+ if (*eps_real > 0xfff)
+ *eps_real -= 0x2000;
+}
+
+static const fixed AtanTbl[] = {
+ 2949120,
+ 1740967,
+ 919879,
+ 466945,
+ 234379,
+ 117304,
+ 58666,
+ 29335,
+ 14668,
+ 7334,
+ 3667,
+ 1833,
+ 917,
+ 458,
+ 229,
+ 115,
+ 57,
+ 29
+};
+
+void wlc_phy_cordic(fixed theta, cs32 *val)
+{
+ fixed angle, valtmp;
+ unsigned iter;
+ int signx = 1;
+ int signtheta;
+
+ val[0].i = CORDIC_AG;
+ val[0].q = 0;
+ angle = 0;
+
+ signtheta = (theta < 0) ? -1 : 1;
+ theta =
+ ((theta + FIXED(180) * signtheta) % FIXED(360)) -
+ FIXED(180) * signtheta;
+
+ if (FLOAT(theta) > 90) {
+ theta -= FIXED(180);
+ signx = -1;
+ } else if (FLOAT(theta) < -90) {
+ theta += FIXED(180);
+ signx = -1;
+ }
+
+ for (iter = 0; iter < CORDIC_NI; iter++) {
+ if (theta > angle) {
+ valtmp = val[0].i - (val[0].q >> iter);
+ val[0].q = (val[0].i >> iter) + val[0].q;
+ val[0].i = valtmp;
+ angle += AtanTbl[iter];
+ } else {
+ valtmp = val[0].i + (val[0].q >> iter);
+ val[0].q = -(val[0].i >> iter) + val[0].q;
+ val[0].i = valtmp;
+ angle -= AtanTbl[iter];
+ }
+ }
+
+ val[0].i = val[0].i * signx;
+ val[0].q = val[0].q * signx;
+}
+
+void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi)
+{
+ wlapi_del_timer(pi->sh->physhim, pi->phycal_timer);
+
+ pi->cal_type_override = PHY_PERICAL_AUTO;
+ pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
+ pi->mphase_txcal_cmdidx = 0;
+}
+
+static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay)
+{
+
+ if ((pi->nphy_perical != PHY_PERICAL_MPHASE) &&
+ (pi->nphy_perical != PHY_PERICAL_MANUAL))
+ return;
+
+ wlapi_del_timer(pi->sh->physhim, pi->phycal_timer);
+
+ pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
+ wlapi_add_timer(pi->sh->physhim, pi->phycal_timer, delay, 0);
+}
+
+void wlc_phy_cal_perical(wlc_phy_t *pih, u8 reason)
+{
+ s16 nphy_currtemp = 0;
+ s16 delta_temp = 0;
+ bool do_periodic_cal = true;
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ if (!ISNPHY(pi))
+ return;
+
+ if ((pi->nphy_perical == PHY_PERICAL_DISABLE) ||
+ (pi->nphy_perical == PHY_PERICAL_MANUAL))
+ return;
+
+ switch (reason) {
+ case PHY_PERICAL_DRIVERUP:
+ break;
+
+ case PHY_PERICAL_PHYINIT:
+ if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
+ if (PHY_PERICAL_MPHASE_PENDING(pi)) {
+ wlc_phy_cal_perical_mphase_reset(pi);
+ }
+ wlc_phy_cal_perical_mphase_schedule(pi,
+ PHY_PERICAL_INIT_DELAY);
+ }
+ break;
+
+ case PHY_PERICAL_JOIN_BSS:
+ case PHY_PERICAL_START_IBSS:
+ case PHY_PERICAL_UP_BSS:
+ if ((pi->nphy_perical == PHY_PERICAL_MPHASE) &&
+ PHY_PERICAL_MPHASE_PENDING(pi)) {
+ wlc_phy_cal_perical_mphase_reset(pi);
+ }
+
+ pi->first_cal_after_assoc = true;
+
+ pi->cal_type_override = PHY_PERICAL_FULL;
+
+ if (pi->phycal_tempdelta) {
+ pi->nphy_lastcal_temp = wlc_phy_tempsense_nphy(pi);
+ }
+ wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_FULL);
+ break;
+
+ case PHY_PERICAL_WATCHDOG:
+ if (pi->phycal_tempdelta) {
+ nphy_currtemp = wlc_phy_tempsense_nphy(pi);
+ delta_temp =
+ (nphy_currtemp > pi->nphy_lastcal_temp) ?
+ nphy_currtemp - pi->nphy_lastcal_temp :
+ pi->nphy_lastcal_temp - nphy_currtemp;
+
+ if ((delta_temp < (s16) pi->phycal_tempdelta) &&
+ (pi->nphy_txiqlocal_chanspec ==
+ pi->radio_chanspec)) {
+ do_periodic_cal = false;
+ } else {
+ pi->nphy_lastcal_temp = nphy_currtemp;
+ }
+ }
+
+ if (do_periodic_cal) {
+
+ if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
+
+ if (!PHY_PERICAL_MPHASE_PENDING(pi))
+ wlc_phy_cal_perical_mphase_schedule(pi,
+ PHY_PERICAL_WDOG_DELAY);
+ } else if (pi->nphy_perical == PHY_PERICAL_SPHASE)
+ wlc_phy_cal_perical_nphy_run(pi,
+ PHY_PERICAL_AUTO);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void wlc_phy_cal_perical_mphase_restart(phy_info_t *pi)
+{
+ pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
+ pi->mphase_txcal_cmdidx = 0;
+}
+
+u8 wlc_phy_nbits(s32 value)
+{
+ s32 abs_val;
+ u8 nbits = 0;
+
+ abs_val = ABS(value);
+ while ((abs_val >> nbits) > 0)
+ nbits++;
+
+ return nbits;
+}
+
+void wlc_phy_stf_chain_init(wlc_phy_t *pih, u8 txchain, u8 rxchain)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ pi->sh->hw_phytxchain = txchain;
+ pi->sh->hw_phyrxchain = rxchain;
+ pi->sh->phytxchain = txchain;
+ pi->sh->phyrxchain = rxchain;
+ pi->pubpi.phy_corenum = (u8) PHY_BITSCNT(pi->sh->phyrxchain);
+}
+
+void wlc_phy_stf_chain_set(wlc_phy_t *pih, u8 txchain, u8 rxchain)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ pi->sh->phytxchain = txchain;
+
+ if (ISNPHY(pi)) {
+ wlc_phy_rxcore_setstate_nphy(pih, rxchain);
+ }
+ pi->pubpi.phy_corenum = (u8) PHY_BITSCNT(pi->sh->phyrxchain);
+}
+
+void wlc_phy_stf_chain_get(wlc_phy_t *pih, u8 *txchain, u8 *rxchain)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ *txchain = pi->sh->phytxchain;
+ *rxchain = pi->sh->phyrxchain;
+}
+
+u8 wlc_phy_stf_chain_active_get(wlc_phy_t *pih)
+{
+ s16 nphy_currtemp;
+ u8 active_bitmap;
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ active_bitmap = (pi->phy_txcore_heatedup) ? 0x31 : 0x33;
+
+ if (!pi->watchdog_override)
+ return active_bitmap;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ nphy_currtemp = wlc_phy_tempsense_nphy(pi);
+ wlapi_enable_mac(pi->sh->physhim);
+
+ if (!pi->phy_txcore_heatedup) {
+ if (nphy_currtemp >= pi->phy_txcore_disable_temp) {
+ active_bitmap &= 0xFD;
+ pi->phy_txcore_heatedup = true;
+ }
+ } else {
+ if (nphy_currtemp <= pi->phy_txcore_enable_temp) {
+ active_bitmap |= 0x2;
+ pi->phy_txcore_heatedup = false;
+ }
+ }
+ }
+
+ return active_bitmap;
+}
+
+s8 wlc_phy_stf_ssmode_get(wlc_phy_t *pih, chanspec_t chanspec)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ u8 siso_mcs_id, cdd_mcs_id;
+
+ siso_mcs_id =
+ (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_SISO :
+ TXP_FIRST_MCS_20_SISO;
+ cdd_mcs_id =
+ (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_CDD :
+ TXP_FIRST_MCS_20_CDD;
+
+ if (pi->tx_power_target[siso_mcs_id] >
+ (pi->tx_power_target[cdd_mcs_id] + 12))
+ return PHY_TXC1_MODE_SISO;
+ else
+ return PHY_TXC1_MODE_CDD;
+}
+
+const u8 *wlc_phy_get_ofdm_rate_lookup(void)
+{
+ return ofdm_rate_lookup;
+}
+
+void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode)
+{
+ if ((pi->sh->chip == BCM4313_CHIP_ID) &&
+ (pi->sh->boardflags & BFL_FEM)) {
+ if (mode) {
+ u16 txant = 0;
+ txant = wlapi_bmac_get_txant(pi->sh->physhim);
+ if (txant == 1) {
+ mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
+
+ }
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, gpiocontrol), ~0x0,
+ 0x0);
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, gpioout), 0x40, 0x40);
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, gpioouten), 0x40,
+ 0x40);
+ } else {
+ mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
+
+ mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
+
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, gpioout), 0x40, 0x00);
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, gpioouten), 0x40, 0x0);
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, gpiocontrol), ~0x0,
+ 0x40);
+ }
+ }
+}
+
+static s8
+wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, u32 band,
+ u8 rate)
+{
+ s8 offset = 0;
+
+ if (!pi->user_txpwr_at_rfport)
+ return offset;
+ return offset;
+}
+
+static s8 wlc_phy_env_measure_vbat(phy_info_t *pi)
+{
+ if (ISLCNPHY(pi))
+ return wlc_lcnphy_vbatsense(pi, 0);
+ else
+ return 0;
+}
+
+static s8 wlc_phy_env_measure_temperature(phy_info_t *pi)
+{
+ if (ISLCNPHY(pi))
+ return wlc_lcnphy_tempsense_degree(pi, 0);
+ else
+ return 0;
+}
+
+static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band)
+{
+ u8 i;
+ s8 temp, vbat;
+
+ for (i = 0; i < TXP_NUM_RATES; i++)
+ pi->txpwr_env_limit[i] = WLC_TXPWR_MAX;
+
+ vbat = wlc_phy_env_measure_vbat(pi);
+ temp = wlc_phy_env_measure_temperature(pi);
+
+}
+
+void wlc_phy_ldpc_override_set(wlc_phy_t *ppi, bool ldpc)
+{
+ return;
+}
+
+void
+wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset, s8 *ofdmoffset)
+{
+ *cckoffset = 0;
+ *ofdmoffset = 0;
+}
+
+s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi, chanspec_t chanspec)
+{
+
+ return rssi;
+}
+
+bool wlc_phy_txpower_ipa_ison(wlc_phy_t *ppi)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ if (ISNPHY(pi))
+ return wlc_phy_n_txpower_ipa_ison(pi);
+ else
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * phy_hal.h: functionality exported from the phy to higher layers
+ */
+
+#ifndef _BRCM_PHY_HAL_H_
+#define _BRCM_PHY_HAL_H_
+
+#include <aiutils.h>
+#include <d11.h>
+#include <phy_shim.h>
+#include <net/mac80211.h> /* struct wiphy */
+#include "brcmu_wifi.h" /* chanspec_t */
+
+#define IDCODE_VER_MASK 0x0000000f
+#define IDCODE_VER_SHIFT 0
+#define IDCODE_MFG_MASK 0x00000fff
+#define IDCODE_MFG_SHIFT 0
+#define IDCODE_ID_MASK 0x0ffff000
+#define IDCODE_ID_SHIFT 12
+#define IDCODE_REV_MASK 0xf0000000
+#define IDCODE_REV_SHIFT 28
+
+#define NORADIO_ID 0xe4f5
+#define NORADIO_IDCODE 0x4e4f5246
+
+#define BCM2055_ID 0x2055
+#define BCM2055_IDCODE 0x02055000
+#define BCM2055A0_IDCODE 0x1205517f
+
+#define BCM2056_ID 0x2056
+#define BCM2056_IDCODE 0x02056000
+#define BCM2056A0_IDCODE 0x1205617f
+
+#define BCM2057_ID 0x2057
+#define BCM2057_IDCODE 0x02057000
+#define BCM2057A0_IDCODE 0x1205717f
+
+#define BCM2064_ID 0x2064
+#define BCM2064_IDCODE 0x02064000
+#define BCM2064A0_IDCODE 0x0206417f
+
+#define PHY_TPC_HW_OFF false
+#define PHY_TPC_HW_ON true
+
+#define PHY_PERICAL_DRIVERUP 1
+#define PHY_PERICAL_WATCHDOG 2
+#define PHY_PERICAL_PHYINIT 3
+#define PHY_PERICAL_JOIN_BSS 4
+#define PHY_PERICAL_START_IBSS 5
+#define PHY_PERICAL_UP_BSS 6
+#define PHY_PERICAL_CHAN 7
+#define PHY_FULLCAL 8
+
+#define PHY_PERICAL_DISABLE 0
+#define PHY_PERICAL_SPHASE 1
+#define PHY_PERICAL_MPHASE 2
+#define PHY_PERICAL_MANUAL 3
+
+#define PHY_HOLD_FOR_ASSOC 1
+#define PHY_HOLD_FOR_SCAN 2
+#define PHY_HOLD_FOR_RM 4
+#define PHY_HOLD_FOR_PLT 8
+#define PHY_HOLD_FOR_MUTE 16
+#define PHY_HOLD_FOR_NOT_ASSOC 0x20
+
+#define PHY_MUTE_FOR_PREISM 1
+#define PHY_MUTE_ALL 0xffffffff
+
+#define PHY_NOISE_FIXED_VAL (-95)
+#define PHY_NOISE_FIXED_VAL_NPHY (-92)
+#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)
+
+#define PHY_MODE_CAL 0x0002
+#define PHY_MODE_NOISEM 0x0004
+
+#define WLC_TXPWR_DB_FACTOR 4
+
+/* a large TX Power as an init value to factor out of min() calculations,
+ * keep low enough to fit in an s8, units are .25 dBm
+ */
+#define WLC_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
+
+#define WLC_NUM_RATES_CCK 4
+#define WLC_NUM_RATES_OFDM 8
+#define WLC_NUM_RATES_MCS_1_STREAM 8
+#define WLC_NUM_RATES_MCS_2_STREAM 8
+#define WLC_NUM_RATES_MCS_3_STREAM 8
+#define WLC_NUM_RATES_MCS_4_STREAM 8
+
+#define WLC_RSSI_INVALID 0 /* invalid RSSI value */
+
+typedef struct txpwr_limits {
+ u8 cck[WLC_NUM_RATES_CCK];
+ u8 ofdm[WLC_NUM_RATES_OFDM];
+
+ u8 ofdm_cdd[WLC_NUM_RATES_OFDM];
+
+ u8 ofdm_40_siso[WLC_NUM_RATES_OFDM];
+ u8 ofdm_40_cdd[WLC_NUM_RATES_OFDM];
+
+ u8 mcs_20_siso[WLC_NUM_RATES_MCS_1_STREAM];
+ u8 mcs_20_cdd[WLC_NUM_RATES_MCS_1_STREAM];
+ u8 mcs_20_stbc[WLC_NUM_RATES_MCS_1_STREAM];
+ u8 mcs_20_mimo[WLC_NUM_RATES_MCS_2_STREAM];
+
+ u8 mcs_40_siso[WLC_NUM_RATES_MCS_1_STREAM];
+ u8 mcs_40_cdd[WLC_NUM_RATES_MCS_1_STREAM];
+ u8 mcs_40_stbc[WLC_NUM_RATES_MCS_1_STREAM];
+ u8 mcs_40_mimo[WLC_NUM_RATES_MCS_2_STREAM];
+ u8 mcs32;
+} txpwr_limits_t;
+
+typedef struct {
+ u32 flags;
+ chanspec_t chanspec; /* txpwr report for this channel */
+ chanspec_t local_chanspec; /* channel on which we are associated */
+ u8 local_max; /* local max according to the AP */
+ u8 local_constraint; /* local constraint according to the AP */
+ s8 antgain[2]; /* Ant gain for each band - from SROM */
+ u8 rf_cores; /* count of RF Cores being reported */
+ u8 est_Pout[4]; /* Latest tx power out estimate per RF chain */
+ u8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain
+ * without adjustment
+ */
+ u8 est_Pout_cck; /* Latest CCK tx power out estimate */
+ u8 tx_power_max[4]; /* Maximum target power among all rates */
+ u8 tx_power_max_rate_ind[4]; /* Index of the rate with the max target power */
+ u8 user_limit[WL_TX_POWER_RATES]; /* User limit */
+ u8 reg_limit[WL_TX_POWER_RATES]; /* Regulatory power limit */
+ u8 board_limit[WL_TX_POWER_RATES]; /* Max power board can support (SROM) */
+ u8 target[WL_TX_POWER_RATES]; /* Latest target power */
+} tx_power_t;
+
+typedef struct tx_inst_power {
+ u8 txpwr_est_Pout[2]; /* Latest estimate for 2.4 and 5 Ghz */
+ u8 txpwr_est_Pout_gofdm; /* Pwr estimate for 2.4 OFDM */
+} tx_inst_power_t;
+
+typedef struct {
+ u8 vec[MAXCHANNEL / NBBY];
+} chanvec_t;
+
+struct rpc_info;
+typedef struct shared_phy shared_phy_t;
+
+struct phy_pub;
+
+typedef struct phy_pub wlc_phy_t;
+
+typedef struct shared_phy_params {
+ struct si_pub *sih;
+ void *physhim;
+ uint unit;
+ uint corerev;
+ uint bustype;
+ uint buscorerev;
+ char *vars;
+ u16 vid;
+ u16 did;
+ uint chip;
+ uint chiprev;
+ uint chippkg;
+ uint sromrev;
+ uint boardtype;
+ uint boardrev;
+ uint boardvendor;
+ u32 boardflags;
+ u32 boardflags2;
+} shared_phy_params_t;
+
+
+extern shared_phy_t *wlc_phy_shared_attach(shared_phy_params_t *shp);
+extern void wlc_phy_shared_detach(shared_phy_t *phy_sh);
+extern wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype,
+ char *vars, struct wiphy *wiphy);
+extern void wlc_phy_detach(wlc_phy_t *ppi);
+
+extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype,
+ u16 *phyrev, u16 *radioid,
+ u16 *radiover);
+extern bool wlc_phy_get_encore(wlc_phy_t *pih);
+extern u32 wlc_phy_get_coreflags(wlc_phy_t *pih);
+
+extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate);
+extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate);
+extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec);
+extern void wlc_phy_watchdog(wlc_phy_t *ppi);
+extern int wlc_phy_down(wlc_phy_t *ppi);
+extern u32 wlc_phy_clk_bwbits(wlc_phy_t *pih);
+extern void wlc_phy_cal_init(wlc_phy_t *ppi);
+extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init);
+
+extern void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec);
+extern chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi);
+extern void wlc_phy_chanspec_radio_set(wlc_phy_t *ppi, chanspec_t newch);
+extern u16 wlc_phy_bw_state_get(wlc_phy_t *ppi);
+extern void wlc_phy_bw_state_set(wlc_phy_t *ppi, u16 bw);
+
+extern void wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx);
+extern void wlc_phy_por_inform(wlc_phy_t *ppi);
+extern void wlc_phy_noise_sample_intr(wlc_phy_t *ppi);
+extern bool wlc_phy_bist_check_phy(wlc_phy_t *ppi);
+
+extern void wlc_phy_set_deaf(wlc_phy_t *ppi, bool user_flag);
+
+extern void wlc_phy_switch_radio(wlc_phy_t *ppi, bool on);
+extern void wlc_phy_anacore(wlc_phy_t *ppi, bool on);
+
+
+extern void wlc_phy_BSSinit(wlc_phy_t *ppi, bool bonlyap, int rssi);
+
+extern void wlc_phy_chanspec_ch14_widefilter_set(wlc_phy_t *ppi,
+ bool wide_filter);
+extern void wlc_phy_chanspec_band_validch(wlc_phy_t *ppi, uint band,
+ chanvec_t *channels);
+extern chanspec_t wlc_phy_chanspec_band_firstch(wlc_phy_t *ppi, uint band);
+
+extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan,
+ u8 *_min_, u8 *_max_, int rate);
+extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan,
+ u8 *_max_, u8 *_min_);
+extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, s32 *,
+ s32 *, u32 *);
+extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *,
+ chanspec_t chanspec);
+extern int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override);
+extern int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override);
+extern void wlc_phy_txpower_target_set(wlc_phy_t *ppi, struct txpwr_limits *);
+extern bool wlc_phy_txpower_hw_ctrl_get(wlc_phy_t *ppi);
+extern void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl);
+extern u8 wlc_phy_txpower_get_target_min(wlc_phy_t *ppi);
+extern u8 wlc_phy_txpower_get_target_max(wlc_phy_t *ppi);
+extern bool wlc_phy_txpower_ipa_ison(wlc_phy_t *pih);
+
+extern void wlc_phy_stf_chain_init(wlc_phy_t *pih, u8 txchain,
+ u8 rxchain);
+extern void wlc_phy_stf_chain_set(wlc_phy_t *pih, u8 txchain,
+ u8 rxchain);
+extern void wlc_phy_stf_chain_get(wlc_phy_t *pih, u8 *txchain,
+ u8 *rxchain);
+extern u8 wlc_phy_stf_chain_active_get(wlc_phy_t *pih);
+extern s8 wlc_phy_stf_ssmode_get(wlc_phy_t *pih, chanspec_t chanspec);
+extern void wlc_phy_ldpc_override_set(wlc_phy_t *ppi, bool val);
+
+extern void wlc_phy_cal_perical(wlc_phy_t *ppi, u8 reason);
+extern void wlc_phy_noise_sample_request_external(wlc_phy_t *ppi);
+extern void wlc_phy_edcrs_lock(wlc_phy_t *pih, bool lock);
+extern void wlc_phy_cal_papd_recal(wlc_phy_t *ppi);
+
+extern void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val);
+extern void wlc_phy_clear_tssi(wlc_phy_t *ppi);
+extern void wlc_phy_hold_upd(wlc_phy_t *ppi, mbool id, bool val);
+extern void wlc_phy_mute_upd(wlc_phy_t *ppi, bool val, mbool flags);
+
+extern void wlc_phy_antsel_type_set(wlc_phy_t *ppi, u8 antsel_type);
+
+extern void wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power,
+ uint channel);
+
+extern void wlc_phy_initcal_enable(wlc_phy_t *pih, bool initcal);
+extern bool wlc_phy_test_ison(wlc_phy_t *ppi);
+extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent);
+extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war);
+extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt);
+extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap);
+
+extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end);
+
+extern void wlc_phy_freqtrack_start(wlc_phy_t *ppi);
+extern void wlc_phy_freqtrack_end(wlc_phy_t *ppi);
+
+extern const u8 *wlc_phy_get_ofdm_rate_lookup(void);
+
+extern s8 wlc_phy_get_tx_power_offset_by_mcs(wlc_phy_t *ppi,
+ u8 mcs_offset);
+extern s8 wlc_phy_get_tx_power_offset(wlc_phy_t *ppi, u8 tbl_offset);
+#endif /* _BRCM_PHY_HAL_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_PHY_INT_H_
+#define _BRCM_PHY_INT_H_
+
+#include <linux/kernel.h>
+#include <defs.h>
+#include <brcmu_utils.h>
+
+#include <phy_hal.h>
+
+#define PHY_VERSION { 1, 82, 8, 0 }
+
+#define PHYHAL_ERROR 0x0001
+#define PHYHAL_TRACE 0x0002
+#define PHYHAL_INFORM 0x0004
+
+extern u32 phyhal_msg_level;
+
+#define PHY_INFORM_ON() (phyhal_msg_level & PHYHAL_INFORM)
+#define PHY_THERMAL_ON() (phyhal_msg_level & PHYHAL_THERMAL)
+#define PHY_CAL_ON() (phyhal_msg_level & PHYHAL_CAL)
+
+#ifdef BOARD_TYPE
+#define BOARDTYPE(_type) BOARD_TYPE
+#else
+#define BOARDTYPE(_type) _type
+#endif
+
+#define LCNXN_BASEREV 16
+
+typedef struct {
+ u8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */
+ u8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
+ u8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */
+ u8 triso; /* TR switch isolation */
+ u8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */
+} wlc_phy_srom_fem_t;
+
+struct wlc_hw_info;
+typedef struct phy_info phy_info_t;
+typedef void (*initfn_t) (phy_info_t *);
+typedef void (*chansetfn_t) (phy_info_t *, chanspec_t);
+typedef int (*longtrnfn_t) (phy_info_t *, int);
+typedef void (*txiqccgetfn_t) (phy_info_t *, u16 *, u16 *);
+typedef void (*txiqccsetfn_t) (phy_info_t *, u16, u16);
+typedef u16(*txloccgetfn_t) (phy_info_t *);
+typedef void (*radioloftgetfn_t) (phy_info_t *, u8 *, u8 *, u8 *,
+ u8 *);
+typedef s32(*rxsigpwrfn_t) (phy_info_t *, s32);
+typedef void (*detachfn_t) (phy_info_t *);
+
+#undef ISNPHY
+#undef ISLCNPHY
+#define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
+#define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
+
+#define ISPHY_11N_CAP(pi) (ISNPHY(pi) || ISLCNPHY(pi))
+
+#define IS20MHZ(pi) ((pi)->bw == WL_CHANSPEC_BW_20)
+#define IS40MHZ(pi) ((pi)->bw == WL_CHANSPEC_BW_40)
+
+#define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f)
+#define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4)
+#define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
+#define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
+ ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
+#define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
+#define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0)))
+
+#define CH_5G_GROUP 3
+#define A_LOW_CHANS 0
+#define A_MID_CHANS 1
+#define A_HIGH_CHANS 2
+#define CH_2G_GROUP 1
+#define G_ALL_CHANS 0
+
+#define FIRST_REF5_CHANNUM 149
+#define LAST_REF5_CHANNUM 165
+#define FIRST_5G_CHAN 14
+#define LAST_5G_CHAN 50
+#define FIRST_MID_5G_CHAN 14
+#define LAST_MID_5G_CHAN 35
+#define FIRST_HIGH_5G_CHAN 36
+#define LAST_HIGH_5G_CHAN 41
+#define FIRST_LOW_5G_CHAN 42
+#define LAST_LOW_5G_CHAN 50
+
+#define BASE_LOW_5G_CHAN 4900
+#define BASE_MID_5G_CHAN 5100
+#define BASE_HIGH_5G_CHAN 5500
+
+#define CHAN5G_FREQ(chan) (5000 + chan*5)
+#define CHAN2G_FREQ(chan) (2407 + chan*5)
+
+#define TXP_FIRST_CCK 0
+#define TXP_LAST_CCK 3
+#define TXP_FIRST_OFDM 4
+#define TXP_LAST_OFDM 11
+#define TXP_FIRST_OFDM_20_CDD 12
+#define TXP_LAST_OFDM_20_CDD 19
+#define TXP_FIRST_MCS_20_SISO 20
+#define TXP_LAST_MCS_20_SISO 27
+#define TXP_FIRST_MCS_20_CDD 28
+#define TXP_LAST_MCS_20_CDD 35
+#define TXP_FIRST_MCS_20_STBC 36
+#define TXP_LAST_MCS_20_STBC 43
+#define TXP_FIRST_MCS_20_SDM 44
+#define TXP_LAST_MCS_20_SDM 51
+#define TXP_FIRST_OFDM_40_SISO 52
+#define TXP_LAST_OFDM_40_SISO 59
+#define TXP_FIRST_OFDM_40_CDD 60
+#define TXP_LAST_OFDM_40_CDD 67
+#define TXP_FIRST_MCS_40_SISO 68
+#define TXP_LAST_MCS_40_SISO 75
+#define TXP_FIRST_MCS_40_CDD 76
+#define TXP_LAST_MCS_40_CDD 83
+#define TXP_FIRST_MCS_40_STBC 84
+#define TXP_LAST_MCS_40_STBC 91
+#define TXP_FIRST_MCS_40_SDM 92
+#define TXP_LAST_MCS_40_SDM 99
+#define TXP_MCS_32 100
+#define TXP_NUM_RATES 101
+#define ADJ_PWR_TBL_LEN 84
+
+#define TXP_FIRST_SISO_MCS_20 20
+#define TXP_LAST_SISO_MCS_20 27
+
+#define PHY_CORE_NUM_1 1
+#define PHY_CORE_NUM_2 2
+#define PHY_CORE_NUM_3 3
+#define PHY_CORE_NUM_4 4
+#define PHY_CORE_MAX PHY_CORE_NUM_4
+#define PHY_CORE_0 0
+#define PHY_CORE_1 1
+#define PHY_CORE_2 2
+#define PHY_CORE_3 3
+
+#define MA_WINDOW_SZ 8
+
+#define PHY_NOISE_SAMPLE_MON 1
+#define PHY_NOISE_SAMPLE_EXTERNAL 2
+#define PHY_NOISE_WINDOW_SZ 16
+#define PHY_NOISE_GLITCH_INIT_MA 10
+#define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
+#define PHY_NOISE_STATE_MON 0x1
+#define PHY_NOISE_STATE_EXTERNAL 0x2
+#define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10
+#define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9
+
+#define PHY_NOISE_OFFSETFACT_4322 (-103)
+#define PHY_NOISE_MA_WINDOW_SZ 2
+
+#define PHY_RSSI_TABLE_SIZE 64
+#define RSSI_ANT_MERGE_MAX 0
+#define RSSI_ANT_MERGE_MIN 1
+#define RSSI_ANT_MERGE_AVG 2
+
+#define PHY_TSSI_TABLE_SIZE 64
+#define APHY_TSSI_TABLE_SIZE 256
+#define TX_GAIN_TABLE_LENGTH 64
+#define DEFAULT_11A_TXP_IDX 24
+#define NUM_TSSI_FRAMES 4
+#define NULL_TSSI 0x7f
+#define NULL_TSSI_W 0x7f7f
+
+#define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
+
+#define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
+
+#define PHY_TXPWR_MIN 10
+#define PHY_TXPWR_MIN_NPHY 8
+#define RADIOPWR_OVERRIDE_DEF (-1)
+
+#define PWRTBL_NUM_COEFF 3
+
+#define SPURAVOID_DISABLE 0
+#define SPURAVOID_AUTO 1
+#define SPURAVOID_FORCEON 2
+#define SPURAVOID_FORCEON2 3
+
+#define PHY_SW_TIMER_FAST 15
+#define PHY_SW_TIMER_SLOW 60
+#define PHY_SW_TIMER_GLACIAL 120
+
+#define PHY_PERICAL_AUTO 0
+#define PHY_PERICAL_FULL 1
+#define PHY_PERICAL_PARTIAL 2
+
+#define PHY_PERICAL_NODELAY 0
+#define PHY_PERICAL_INIT_DELAY 5
+#define PHY_PERICAL_ASSOC_DELAY 5
+#define PHY_PERICAL_WDOG_DELAY 5
+
+#define MPHASE_TXCAL_NUMCMDS 2
+#define PHY_PERICAL_MPHASE_PENDING(pi) (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
+
+enum {
+ MPHASE_CAL_STATE_IDLE = 0,
+ MPHASE_CAL_STATE_INIT = 1,
+ MPHASE_CAL_STATE_TXPHASE0,
+ MPHASE_CAL_STATE_TXPHASE1,
+ MPHASE_CAL_STATE_TXPHASE2,
+ MPHASE_CAL_STATE_TXPHASE3,
+ MPHASE_CAL_STATE_TXPHASE4,
+ MPHASE_CAL_STATE_TXPHASE5,
+ MPHASE_CAL_STATE_PAPDCAL,
+ MPHASE_CAL_STATE_RXCAL,
+ MPHASE_CAL_STATE_RSSICAL,
+ MPHASE_CAL_STATE_IDLETSSI
+};
+
+typedef enum {
+ CAL_FULL,
+ CAL_RECAL,
+ CAL_CURRECAL,
+ CAL_DIGCAL,
+ CAL_GCTRL,
+ CAL_SOFT,
+ CAL_DIGLO
+} phy_cal_mode_t;
+
+#define RDR_NTIERS 1
+#define RDR_TIER_SIZE 64
+#define RDR_LIST_SIZE (512/3)
+#define RDR_EPOCH_SIZE 40
+#define RDR_NANTENNAS 2
+#define RDR_NTIER_SIZE RDR_LIST_SIZE
+#define RDR_LP_BUFFER_SIZE 64
+#define LP_LEN_HIS_SIZE 10
+
+#define STATIC_NUM_RF 32
+#define STATIC_NUM_BB 9
+
+#define BB_MULT_MASK 0x0000ffff
+#define BB_MULT_VALID_MASK 0x80000000
+
+#define CORDIC_AG 39797
+#define CORDIC_NI 18
+#define FIXED(X) ((s32)((X) << 16))
+#define FLOAT(X) (((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
+
+#define PHY_CHAIN_TX_DISABLE_TEMP 115
+#define PHY_HYSTERESIS_DELTATEMP 5
+
+#define PHY_BITSCNT(x) brcmu_bitcount((u8 *)&(x), sizeof(u8))
+
+#define MOD_PHY_REG(pi, phy_type, reg_name, field, value) \
+ mod_phy_reg(pi, phy_type##_##reg_name, phy_type##_##reg_name##_##field##_MASK, \
+ (value) << phy_type##_##reg_name##_##field##_##SHIFT);
+#define READ_PHY_REG(pi, phy_type, reg_name, field) \
+ ((read_phy_reg(pi, phy_type##_##reg_name) & phy_type##_##reg_name##_##field##_##MASK)\
+ >> phy_type##_##reg_name##_##field##_##SHIFT)
+
+#define VALID_PHYTYPE(phytype) (((uint)phytype == PHY_TYPE_N) || \
+ ((uint)phytype == PHY_TYPE_LCN))
+
+#define VALID_N_RADIO(radioid) ((radioid == BCM2055_ID) || (radioid == BCM2056_ID) || \
+ (radioid == BCM2057_ID))
+#define VALID_LCN_RADIO(radioid) (radioid == BCM2064_ID)
+
+#define VALID_RADIO(pi, radioid) (\
+ (ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
+ (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
+
+#define SCAN_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
+#define RM_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_RM))
+#define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
+#define ASSOC_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
+#define SCAN_RM_IN_PROGRESS(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
+#define PHY_MUTED(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
+#define PUB_NOT_ASSOC(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
+
+#if defined(EXT_CBALL)
+#define NORADIO_ENAB(pub) ((pub).radioid == NORADIO_ID)
+#else
+#define NORADIO_ENAB(pub) 0
+#endif
+
+#define PHY_LTRN_LIST_LEN 64
+extern u16 ltrn_list[PHY_LTRN_LIST_LEN];
+
+typedef struct _phy_table_info {
+ uint table;
+ int q;
+ uint max;
+} phy_table_info_t;
+
+typedef struct phytbl_info {
+ const void *tbl_ptr;
+ u32 tbl_len;
+ u32 tbl_id;
+ u32 tbl_offset;
+ u32 tbl_width;
+} phytbl_info_t;
+
+typedef struct {
+ u8 curr_home_channel;
+ u16 crsminpwrthld_40_stored;
+ u16 crsminpwrthld_20L_stored;
+ u16 crsminpwrthld_20U_stored;
+ u16 init_gain_code_core1_stored;
+ u16 init_gain_code_core2_stored;
+ u16 init_gain_codeb_core1_stored;
+ u16 init_gain_codeb_core2_stored;
+ u16 init_gain_table_stored[4];
+
+ u16 clip1_hi_gain_code_core1_stored;
+ u16 clip1_hi_gain_code_core2_stored;
+ u16 clip1_hi_gain_codeb_core1_stored;
+ u16 clip1_hi_gain_codeb_core2_stored;
+ u16 nb_clip_thresh_core1_stored;
+ u16 nb_clip_thresh_core2_stored;
+ u16 init_ofdmlna2gainchange_stored[4];
+ u16 init_ccklna2gainchange_stored[4];
+ u16 clip1_lo_gain_code_core1_stored;
+ u16 clip1_lo_gain_code_core2_stored;
+ u16 clip1_lo_gain_codeb_core1_stored;
+ u16 clip1_lo_gain_codeb_core2_stored;
+ u16 w1_clip_thresh_core1_stored;
+ u16 w1_clip_thresh_core2_stored;
+ u16 radio_2056_core1_rssi_gain_stored;
+ u16 radio_2056_core2_rssi_gain_stored;
+ u16 energy_drop_timeout_len_stored;
+
+ u16 ed_crs40_assertthld0_stored;
+ u16 ed_crs40_assertthld1_stored;
+ u16 ed_crs40_deassertthld0_stored;
+ u16 ed_crs40_deassertthld1_stored;
+ u16 ed_crs20L_assertthld0_stored;
+ u16 ed_crs20L_assertthld1_stored;
+ u16 ed_crs20L_deassertthld0_stored;
+ u16 ed_crs20L_deassertthld1_stored;
+ u16 ed_crs20U_assertthld0_stored;
+ u16 ed_crs20U_assertthld1_stored;
+ u16 ed_crs20U_deassertthld0_stored;
+ u16 ed_crs20U_deassertthld1_stored;
+
+ u16 badplcp_ma;
+ u16 badplcp_ma_previous;
+ u16 badplcp_ma_total;
+ u16 badplcp_ma_list[MA_WINDOW_SZ];
+ int badplcp_ma_index;
+ s16 pre_badplcp_cnt;
+ s16 bphy_pre_badplcp_cnt;
+
+ u16 init_gain_core1;
+ u16 init_gain_core2;
+ u16 init_gainb_core1;
+ u16 init_gainb_core2;
+ u16 init_gain_rfseq[4];
+
+ u16 crsminpwr0;
+ u16 crsminpwrl0;
+ u16 crsminpwru0;
+
+ s16 crsminpwr_index;
+
+ u16 radio_2057_core1_rssi_wb1a_gc_stored;
+ u16 radio_2057_core2_rssi_wb1a_gc_stored;
+ u16 radio_2057_core1_rssi_wb1g_gc_stored;
+ u16 radio_2057_core2_rssi_wb1g_gc_stored;
+ u16 radio_2057_core1_rssi_wb2_gc_stored;
+ u16 radio_2057_core2_rssi_wb2_gc_stored;
+ u16 radio_2057_core1_rssi_nb_gc_stored;
+ u16 radio_2057_core2_rssi_nb_gc_stored;
+
+} interference_info_t;
+
+typedef struct {
+ u16 rc_cal_ovr;
+ u16 phycrsth1;
+ u16 phycrsth2;
+ u16 init_n1p1_gain;
+ u16 p1_p2_gain;
+ u16 n1_n2_gain;
+ u16 n1_p1_gain;
+ u16 div_search_gain;
+ u16 div_p1_p2_gain;
+ u16 div_search_gn_change;
+ u16 table_7_2;
+ u16 table_7_3;
+ u16 cckshbits_gnref;
+ u16 clip_thresh;
+ u16 clip2_thresh;
+ u16 clip3_thresh;
+ u16 clip_p2_thresh;
+ u16 clip_pwdn_thresh;
+ u16 clip_n1p1_thresh;
+ u16 clip_n1_pwdn_thresh;
+ u16 bbconfig;
+ u16 cthr_sthr_shdin;
+ u16 energy;
+ u16 clip_p1_p2_thresh;
+ u16 threshold;
+ u16 reg15;
+ u16 reg16;
+ u16 reg17;
+ u16 div_srch_idx;
+ u16 div_srch_p1_p2;
+ u16 div_srch_gn_back;
+ u16 ant_dwell;
+ u16 ant_wr_settle;
+} aci_save_gphy_t;
+
+typedef struct _lo_complex_t {
+ s8 i;
+ s8 q;
+} lo_complex_abgphy_info_t;
+
+typedef struct _nphy_iq_comp {
+ s16 a0;
+ s16 b0;
+ s16 a1;
+ s16 b1;
+} nphy_iq_comp_t;
+
+typedef struct _nphy_txpwrindex {
+ s8 index;
+ s8 index_internal;
+ s8 index_internal_save;
+ u16 AfectrlOverride;
+ u16 AfeCtrlDacGain;
+ u16 rad_gain;
+ u8 bbmult;
+ u16 iqcomp_a;
+ u16 iqcomp_b;
+ u16 locomp;
+} phy_txpwrindex_t;
+
+typedef struct {
+
+ u16 txcal_coeffs_2G[8];
+ u16 txcal_radio_regs_2G[8];
+ nphy_iq_comp_t rxcal_coeffs_2G;
+
+ u16 txcal_coeffs_5G[8];
+ u16 txcal_radio_regs_5G[8];
+ nphy_iq_comp_t rxcal_coeffs_5G;
+} txiqcal_cache_t;
+
+typedef struct _nphy_pwrctrl {
+ s8 max_pwr_2g;
+ s8 idle_targ_2g;
+ s16 pwrdet_2g_a1;
+ s16 pwrdet_2g_b0;
+ s16 pwrdet_2g_b1;
+ s8 max_pwr_5gm;
+ s8 idle_targ_5gm;
+ s8 max_pwr_5gh;
+ s8 max_pwr_5gl;
+ s16 pwrdet_5gm_a1;
+ s16 pwrdet_5gm_b0;
+ s16 pwrdet_5gm_b1;
+ s16 pwrdet_5gl_a1;
+ s16 pwrdet_5gl_b0;
+ s16 pwrdet_5gl_b1;
+ s16 pwrdet_5gh_a1;
+ s16 pwrdet_5gh_b0;
+ s16 pwrdet_5gh_b1;
+ s8 idle_targ_5gl;
+ s8 idle_targ_5gh;
+ s8 idle_tssi_2g;
+ s8 idle_tssi_5g;
+ s8 idle_tssi;
+ s16 a1;
+ s16 b0;
+ s16 b1;
+} phy_pwrctrl_t;
+
+typedef struct _nphy_txgains {
+ u16 txlpf[2];
+ u16 txgm[2];
+ u16 pga[2];
+ u16 pad[2];
+ u16 ipa[2];
+} nphy_txgains_t;
+
+#define PHY_NOISEVAR_BUFSIZE 10
+
+typedef struct _nphy_noisevar_buf {
+ int bufcount;
+ int tone_id[PHY_NOISEVAR_BUFSIZE];
+ u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
+ u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
+} phy_noisevar_buf_t;
+
+typedef struct {
+ u16 rssical_radio_regs_2G[2];
+ u16 rssical_phyregs_2G[12];
+
+ u16 rssical_radio_regs_5G[2];
+ u16 rssical_phyregs_5G[12];
+} rssical_cache_t;
+
+typedef struct {
+
+ u16 txiqlocal_a;
+ u16 txiqlocal_b;
+ u16 txiqlocal_didq;
+ u8 txiqlocal_ei0;
+ u8 txiqlocal_eq0;
+ u8 txiqlocal_fi0;
+ u8 txiqlocal_fq0;
+
+ u16 txiqlocal_bestcoeffs[11];
+ u16 txiqlocal_bestcoeffs_valid;
+
+ u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
+ u16 analog_gain_ref;
+ u16 lut_begin;
+ u16 lut_end;
+ u16 lut_step;
+ u16 rxcompdbm;
+ u16 papdctrl;
+ u16 sslpnCalibClkEnCtrl;
+
+ u16 rxiqcal_coeff_a0;
+ u16 rxiqcal_coeff_b0;
+} lcnphy_cal_results_t;
+
+struct shared_phy {
+ struct phy_info *phy_head;
+ uint unit;
+ struct si_pub *sih;
+ void *physhim;
+ uint corerev;
+ u32 machwcap;
+ bool up;
+ bool clk;
+ uint now;
+ u16 vid;
+ u16 did;
+ uint chip;
+ uint chiprev;
+ uint chippkg;
+ uint sromrev;
+ uint boardtype;
+ uint boardrev;
+ uint boardvendor;
+ u32 boardflags;
+ u32 boardflags2;
+ uint bustype;
+ uint buscorerev;
+ uint fast_timer;
+ uint slow_timer;
+ uint glacial_timer;
+ u8 rx_antdiv;
+ s8 phy_noise_window[MA_WINDOW_SZ];
+ uint phy_noise_index;
+ u8 hw_phytxchain;
+ u8 hw_phyrxchain;
+ u8 phytxchain;
+ u8 phyrxchain;
+ u8 rssi_mode;
+ bool _rifs_phy;
+};
+
+struct phy_pub {
+ uint phy_type;
+ uint phy_rev;
+ u8 phy_corenum;
+ u16 radioid;
+ u8 radiorev;
+ u8 radiover;
+
+ uint coreflags;
+ uint ana_rev;
+ bool abgphy_encore;
+};
+
+struct phy_info_nphy;
+typedef struct phy_info_nphy phy_info_nphy_t;
+
+struct phy_info_lcnphy;
+typedef struct phy_info_lcnphy phy_info_lcnphy_t;
+
+struct phy_func_ptr {
+ initfn_t init;
+ initfn_t calinit;
+ chansetfn_t chanset;
+ initfn_t txpwrrecalc;
+ longtrnfn_t longtrn;
+ txiqccgetfn_t txiqccget;
+ txiqccsetfn_t txiqccset;
+ txloccgetfn_t txloccget;
+ radioloftgetfn_t radioloftget;
+ initfn_t carrsuppr;
+ rxsigpwrfn_t rxsigpwr;
+ detachfn_t detach;
+};
+typedef struct phy_func_ptr phy_func_ptr_t;
+
+struct phy_info {
+ wlc_phy_t pubpi_ro;
+ shared_phy_t *sh;
+ phy_func_ptr_t pi_fptr;
+ void *pi_ptr;
+
+ union {
+ phy_info_lcnphy_t *pi_lcnphy;
+ } u;
+ bool user_txpwr_at_rfport;
+
+ d11regs_t *regs;
+ struct phy_info *next;
+ char *vars;
+ wlc_phy_t pubpi;
+
+ bool do_initcal;
+ bool phytest_on;
+ bool ofdm_rateset_war;
+ bool bf_preempt_4306;
+ chanspec_t radio_chanspec;
+ u8 antsel_type;
+ u16 bw;
+ u8 txpwr_percent;
+ bool phy_init_por;
+
+ bool init_in_progress;
+ bool initialized;
+ bool sbtml_gm;
+ uint refcnt;
+ bool watchdog_override;
+ u8 phynoise_state;
+ uint phynoise_now;
+ int phynoise_chan_watchdog;
+ bool phynoise_polling;
+ bool disable_percal;
+ mbool measure_hold;
+
+ s16 txpa_2g[PWRTBL_NUM_COEFF];
+ s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
+ s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
+ s16 txpa_5g_low[PWRTBL_NUM_COEFF];
+ s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
+ s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
+
+ u8 tx_srom_max_2g;
+ u8 tx_srom_max_5g_low;
+ u8 tx_srom_max_5g_mid;
+ u8 tx_srom_max_5g_hi;
+ u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
+ u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
+ u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
+ u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
+ u8 tx_user_target[TXP_NUM_RATES];
+ s8 tx_power_offset[TXP_NUM_RATES];
+ u8 tx_power_target[TXP_NUM_RATES];
+
+ wlc_phy_srom_fem_t srom_fem2g;
+ wlc_phy_srom_fem_t srom_fem5g;
+
+ u8 tx_power_max;
+ u8 tx_power_max_rate_ind;
+ bool hwpwrctrl;
+ u8 nphy_txpwrctrl;
+ s8 nphy_txrx_chain;
+ bool phy_5g_pwrgain;
+
+ u16 phy_wreg;
+ u16 phy_wreg_limit;
+
+ s8 n_preamble_override;
+ u8 antswitch;
+ u8 aa2g, aa5g;
+
+ s8 idle_tssi[CH_5G_GROUP];
+ s8 target_idle_tssi;
+ s8 txpwr_est_Pout;
+ u8 tx_power_min;
+ u8 txpwr_limit[TXP_NUM_RATES];
+ u8 txpwr_env_limit[TXP_NUM_RATES];
+ u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
+
+ bool channel_14_wide_filter;
+
+ bool txpwroverride;
+ bool txpwridx_override_aphy;
+ s16 radiopwr_override;
+ u16 hwpwr_txcur;
+ u8 saved_txpwr_idx;
+
+ bool edcrs_threshold_lock;
+
+ u32 tr_R_gain_val;
+ u32 tr_T_gain_val;
+
+ s16 ofdm_analog_filt_bw_override;
+ s16 cck_analog_filt_bw_override;
+ s16 ofdm_rccal_override;
+ s16 cck_rccal_override;
+ u16 extlna_type;
+
+ uint interference_mode_crs_time;
+ u16 crsglitch_prev;
+ bool interference_mode_crs;
+
+ u32 phy_tx_tone_freq;
+ uint phy_lastcal;
+ bool phy_forcecal;
+ bool phy_fixed_noise;
+ u32 xtalfreq;
+ u8 pdiv;
+ s8 carrier_suppr_disable;
+
+ bool phy_bphy_evm;
+ bool phy_bphy_rfcs;
+ s8 phy_scraminit;
+ u8 phy_gpiosel;
+
+ s16 phy_txcore_disable_temp;
+ s16 phy_txcore_enable_temp;
+ s8 phy_tempsense_offset;
+ bool phy_txcore_heatedup;
+
+ u16 radiopwr;
+ u16 bb_atten;
+ u16 txctl1;
+
+ u16 mintxbias;
+ u16 mintxmag;
+ lo_complex_abgphy_info_t gphy_locomp_iq[STATIC_NUM_RF][STATIC_NUM_BB];
+ s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
+ u16 gain_table[TX_GAIN_TABLE_LENGTH];
+ bool loopback_gain;
+ s16 max_lpback_gain_hdB;
+ s16 trsw_rx_gain_hdB;
+ u8 power_vec[8];
+
+ u16 rc_cal;
+ int nrssi_table_delta;
+ int nrssi_slope_scale;
+ int nrssi_slope_offset;
+ int min_rssi;
+ int max_rssi;
+
+ s8 txpwridx;
+ u8 min_txpower;
+
+ u8 a_band_high_disable;
+
+ u16 tx_vos;
+ u16 global_tx_bb_dc_bias_loft;
+
+ int rf_max;
+ int bb_max;
+ int rf_list_size;
+ int bb_list_size;
+ u16 *rf_attn_list;
+ u16 *bb_attn_list;
+ u16 padmix_mask;
+ u16 padmix_reg;
+ u16 *txmag_list;
+ uint txmag_len;
+ bool txmag_enable;
+
+ s8 *a_tssi_to_dbm;
+ s8 *m_tssi_to_dbm;
+ s8 *l_tssi_to_dbm;
+ s8 *h_tssi_to_dbm;
+ u8 *hwtxpwr;
+
+ u16 freqtrack_saved_regs[2];
+ int cur_interference_mode;
+ bool hwpwrctrl_capable;
+ bool temppwrctrl_capable;
+
+ uint phycal_nslope;
+ uint phycal_noffset;
+ uint phycal_mlo;
+ uint phycal_txpower;
+
+ u8 phy_aa2g;
+
+ bool nphy_tableloaded;
+ s8 nphy_rssisel;
+ u32 nphy_bb_mult_save;
+ u16 nphy_txiqlocal_bestc[11];
+ bool nphy_txiqlocal_coeffsvalid;
+ phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
+ phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
+ u16 cck2gpo;
+ u32 ofdm2gpo;
+ u32 ofdm5gpo;
+ u32 ofdm5glpo;
+ u32 ofdm5ghpo;
+ u8 bw402gpo;
+ u8 bw405gpo;
+ u8 bw405glpo;
+ u8 bw405ghpo;
+ u8 cdd2gpo;
+ u8 cdd5gpo;
+ u8 cdd5glpo;
+ u8 cdd5ghpo;
+ u8 stbc2gpo;
+ u8 stbc5gpo;
+ u8 stbc5glpo;
+ u8 stbc5ghpo;
+ u8 bwdup2gpo;
+ u8 bwdup5gpo;
+ u8 bwdup5glpo;
+ u8 bwdup5ghpo;
+ u16 mcs2gpo[8];
+ u16 mcs5gpo[8];
+ u16 mcs5glpo[8];
+ u16 mcs5ghpo[8];
+ u32 nphy_rxcalparams;
+
+ u8 phy_spuravoid;
+ bool phy_isspuravoid;
+
+ u8 phy_pabias;
+ u8 nphy_papd_skip;
+ u8 nphy_tssi_slope;
+
+ s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
+ u8 nphy_noise_index;
+
+ u8 nphy_txpid2g[PHY_CORE_NUM_2];
+ u8 nphy_txpid5g[PHY_CORE_NUM_2];
+ u8 nphy_txpid5gl[PHY_CORE_NUM_2];
+ u8 nphy_txpid5gh[PHY_CORE_NUM_2];
+
+ bool nphy_gain_boost;
+ bool nphy_elna_gain_config;
+ u16 old_bphy_test;
+ u16 old_bphy_testcontrol;
+
+ bool phyhang_avoid;
+
+ bool rssical_nphy;
+ u8 nphy_perical;
+ uint nphy_perical_last;
+ u8 cal_type_override;
+ u8 mphase_cal_phase_id;
+ u8 mphase_txcal_cmdidx;
+ u8 mphase_txcal_numcmds;
+ u16 mphase_txcal_bestcoeffs[11];
+ chanspec_t nphy_txiqlocal_chanspec;
+ chanspec_t nphy_iqcal_chanspec_2G;
+ chanspec_t nphy_iqcal_chanspec_5G;
+ chanspec_t nphy_rssical_chanspec_2G;
+ chanspec_t nphy_rssical_chanspec_5G;
+ struct wlapi_timer *phycal_timer;
+ bool use_int_tx_iqlo_cal_nphy;
+ bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
+ s16 nphy_lastcal_temp;
+
+ txiqcal_cache_t calibration_cache;
+ rssical_cache_t rssical_cache;
+
+ u8 nphy_txpwr_idx[2];
+ u8 nphy_papd_cal_type;
+ uint nphy_papd_last_cal;
+ u16 nphy_papd_tx_gain_at_last_cal[2];
+ u8 nphy_papd_cal_gain_index[2];
+ s16 nphy_papd_epsilon_offset[2];
+ bool nphy_papd_recal_enable;
+ u32 nphy_papd_recal_counter;
+ bool nphy_force_papd_cal;
+ bool nphy_papdcomp;
+ bool ipa2g_on;
+ bool ipa5g_on;
+
+ u16 classifier_state;
+ u16 clip_state[2];
+ uint nphy_deaf_count;
+ u8 rxiq_samps;
+ u8 rxiq_antsel;
+
+ u16 rfctrlIntc1_save;
+ u16 rfctrlIntc2_save;
+ bool first_cal_after_assoc;
+ u16 tx_rx_cal_radio_saveregs[22];
+ u16 tx_rx_cal_phy_saveregs[15];
+
+ u8 nphy_cal_orig_pwr_idx[2];
+ u8 nphy_txcal_pwr_idx[2];
+ u8 nphy_rxcal_pwr_idx[2];
+ u16 nphy_cal_orig_tx_gain[2];
+ nphy_txgains_t nphy_cal_target_gain;
+ u16 nphy_txcal_bbmult;
+ u16 nphy_gmval;
+
+ u16 nphy_saved_bbconf;
+
+ bool nphy_gband_spurwar_en;
+ bool nphy_gband_spurwar2_en;
+ bool nphy_aband_spurwar_en;
+ u16 nphy_rccal_value;
+ u16 nphy_crsminpwr[3];
+ phy_noisevar_buf_t nphy_saved_noisevars;
+ bool nphy_anarxlpf_adjusted;
+ bool nphy_crsminpwr_adjusted;
+ bool nphy_noisevars_adjusted;
+
+ bool nphy_rxcal_active;
+ u16 radar_percal_mask;
+ bool dfs_lp_buffer_nphy;
+
+ u16 nphy_fineclockgatecontrol;
+
+ s8 rx2tx_biasentry;
+
+ u16 crsminpwr0;
+ u16 crsminpwrl0;
+ u16 crsminpwru0;
+ s16 noise_crsminpwr_index;
+ u16 init_gain_core1;
+ u16 init_gain_core2;
+ u16 init_gainb_core1;
+ u16 init_gainb_core2;
+ u8 aci_noise_curr_channel;
+ u16 init_gain_rfseq[4];
+
+ bool radio_is_on;
+
+ bool nphy_sample_play_lpf_bw_ctl_ovr;
+
+ u16 tbl_data_hi;
+ u16 tbl_data_lo;
+ u16 tbl_addr;
+
+ uint tbl_save_id;
+ uint tbl_save_offset;
+
+ u8 txpwrctrl;
+ s8 txpwrindex[PHY_CORE_MAX];
+
+ u8 phycal_tempdelta;
+ u32 mcs20_po;
+ u32 mcs40_po;
+ struct wiphy *wiphy;
+};
+
+typedef s32 fixed;
+
+typedef struct _cs32 {
+ fixed q;
+ fixed i;
+} cs32;
+
+typedef struct radio_regs {
+ u16 address;
+ u32 init_a;
+ u32 init_g;
+ u8 do_init_a;
+ u8 do_init_g;
+} radio_regs_t;
+
+typedef struct radio_20xx_regs {
+ u16 address;
+ u8 init;
+ u8 do_init;
+} radio_20xx_regs_t;
+
+typedef struct lcnphy_radio_regs {
+ u16 address;
+ u8 init_a;
+ u8 init_g;
+ u8 do_init_a;
+ u8 do_init_g;
+} lcnphy_radio_regs_t;
+
+extern lcnphy_radio_regs_t lcnphy_radio_regs_2064[];
+extern lcnphy_radio_regs_t lcnphy_radio_regs_2066[];
+extern radio_regs_t regs_2055[], regs_SYN_2056[], regs_TX_2056[],
+ regs_RX_2056[];
+extern radio_regs_t regs_SYN_2056_A1[], regs_TX_2056_A1[], regs_RX_2056_A1[];
+extern radio_regs_t regs_SYN_2056_rev5[], regs_TX_2056_rev5[],
+ regs_RX_2056_rev5[];
+extern radio_regs_t regs_SYN_2056_rev6[], regs_TX_2056_rev6[],
+ regs_RX_2056_rev6[];
+extern radio_regs_t regs_SYN_2056_rev7[], regs_TX_2056_rev7[],
+ regs_RX_2056_rev7[];
+extern radio_regs_t regs_SYN_2056_rev8[], regs_TX_2056_rev8[],
+ regs_RX_2056_rev8[];
+extern radio_20xx_regs_t regs_2057_rev4[], regs_2057_rev5[], regs_2057_rev5v1[];
+extern radio_20xx_regs_t regs_2057_rev7[], regs_2057_rev8[];
+
+extern char *phy_getvar(phy_info_t *pi, const char *name);
+extern int phy_getintvar(phy_info_t *pi, const char *name);
+#define PHY_GETVAR(pi, name) phy_getvar(pi, name)
+#define PHY_GETINTVAR(pi, name) phy_getintvar(pi, name)
+
+extern u16 read_phy_reg(phy_info_t *pi, u16 addr);
+extern void write_phy_reg(phy_info_t *pi, u16 addr, u16 val);
+extern void and_phy_reg(phy_info_t *pi, u16 addr, u16 val);
+extern void or_phy_reg(phy_info_t *pi, u16 addr, u16 val);
+extern void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val);
+
+extern u16 read_radio_reg(phy_info_t *pi, u16 addr);
+extern void or_radio_reg(phy_info_t *pi, u16 addr, u16 val);
+extern void and_radio_reg(phy_info_t *pi, u16 addr, u16 val);
+extern void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask,
+ u16 val);
+extern void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask);
+
+extern void write_radio_reg(phy_info_t *pi, u16 addr, u16 val);
+
+extern void wlc_phyreg_enter(wlc_phy_t *pih);
+extern void wlc_phyreg_exit(wlc_phy_t *pih);
+extern void wlc_radioreg_enter(wlc_phy_t *pih);
+extern void wlc_radioreg_exit(wlc_phy_t *pih);
+
+extern void wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
+ u16 tblAddr, u16 tblDataHi,
+ u16 tblDatalo);
+extern void wlc_phy_write_table(phy_info_t *pi,
+ const phytbl_info_t *ptbl_info, u16 tblAddr,
+ u16 tblDataHi, u16 tblDatalo);
+extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
+ u16 tblAddr, u16 tblDataHi,
+ u16 tblDataLo);
+extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val);
+
+extern void write_phy_channel_reg(phy_info_t *pi, uint val);
+extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
+
+extern void wlc_phy_cordic(fixed theta, cs32 *val);
+extern u8 wlc_phy_nbits(s32 value);
+extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
+
+extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
+ radio_20xx_regs_t *radioregs);
+extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
+ u16 core_offset);
+
+extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
+
+extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
+extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
+ s32 *eps_imag);
+
+extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
+extern void wlc_phy_cal_perical_mphase_restart(phy_info_t *pi);
+
+extern bool wlc_phy_attach_nphy(phy_info_t *pi);
+extern bool wlc_phy_attach_lcnphy(phy_info_t *pi);
+
+extern void wlc_phy_detach_lcnphy(phy_info_t *pi);
+
+extern void wlc_phy_init_nphy(phy_info_t *pi);
+extern void wlc_phy_init_lcnphy(phy_info_t *pi);
+
+extern void wlc_phy_cal_init_nphy(phy_info_t *pi);
+extern void wlc_phy_cal_init_lcnphy(phy_info_t *pi);
+
+extern void wlc_phy_chanspec_set_nphy(phy_info_t *pi, chanspec_t chanspec);
+extern void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec);
+extern void wlc_phy_chanspec_set_fixup_lcnphy(phy_info_t *pi,
+ chanspec_t chanspec);
+extern int wlc_phy_channel2freq(uint channel);
+extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
+extern int wlc_phy_chanspec_bandrange_get(phy_info_t *, chanspec_t);
+
+extern void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode);
+extern s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi);
+
+extern void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi);
+extern void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi);
+extern void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi);
+
+extern void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index);
+extern void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable);
+extern void wlc_lcnphy_stop_tx_tone(phy_info_t *pi);
+extern void wlc_lcnphy_start_tx_tone(phy_info_t *pi, s32 f_kHz,
+ u16 max_val, bool iqcalmode);
+
+extern void wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan,
+ u8 *max_pwr, u8 rate_id);
+extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
+ u8 rate_mcs_end,
+ u8 rate_ofdm_start);
+extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
+ u8 rate_ofdm_start,
+ u8 rate_ofdm_end,
+ u8 rate_mcs_start);
+
+extern u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode);
+extern s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode);
+extern s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode);
+extern s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode);
+extern void wlc_phy_carrier_suppress_lcnphy(phy_info_t *pi);
+extern void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel);
+extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
+extern void wlc_2064_vco_cal(phy_info_t *pi);
+
+extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
+
+#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
+#define LCNPHY_TX_POWER_TABLE_SIZE 128
+#define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1)
+#define LCNPHY_TBL_ID_TXPWRCTL 0x07
+#define LCNPHY_TX_PWR_CTRL_OFF 0
+#define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15)
+#define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \
+ (0x1 << 14) | \
+ (0x1 << 13))
+
+#define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001
+
+extern void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti);
+extern void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti);
+extern void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b);
+extern void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq);
+extern void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b);
+extern u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi);
+extern void wlc_lcnphy_get_radio_loft(phy_info_t *pi, u8 *ei0,
+ u8 *eq0, u8 *fi0, u8 *fq0);
+extern void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode);
+extern void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode);
+extern bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi);
+extern void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi);
+extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
+extern void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr,
+ s8 *cck_pwr);
+extern void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi);
+
+extern s32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, s32 gain_index);
+
+#define NPHY_MAX_HPVGA1_INDEX 10
+#define NPHY_DEF_HPVGA1_INDEXLIMIT 7
+
+typedef struct _phy_iq_est {
+ s32 iq_prod;
+ u32 i_pwr;
+ u32 q_pwr;
+} phy_iq_est_t;
+
+extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
+extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
+
+#define wlc_phy_write_table_nphy(pi, pti) wlc_phy_write_table(pi, pti, 0x72, \
+ 0x74, 0x73)
+#define wlc_phy_read_table_nphy(pi, pti) wlc_phy_read_table(pi, pti, 0x72, \
+ 0x74, 0x73)
+#define wlc_nphy_table_addr(pi, id, off) wlc_phy_table_addr((pi), (id), (off), \
+ 0x72, 0x74, 0x73)
+#define wlc_nphy_table_data_write(pi, w, v) wlc_phy_table_data_write((pi), (w), (v))
+
+extern void wlc_phy_table_read_nphy(phy_info_t *pi, u32, u32 l, u32 o,
+ u32 w, void *d);
+extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,
+ u32, const void *);
+
+#define PHY_IPA(pi) \
+ ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
+ (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
+
+#define WLC_PHY_WAR_PR51571(pi) \
+ if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
+ (void)R_REG(&(pi)->regs->maccontrol)
+
+extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype);
+extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);
+extern void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en);
+
+extern u8 wlc_phy_get_chan_freq_range_nphy(phy_info_t *pi, uint chan);
+extern void wlc_phy_switch_radio_nphy(phy_info_t *pi, bool on);
+
+extern void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi);
+
+extern void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd);
+extern s16 wlc_phy_tempsense_nphy(phy_info_t *pi);
+
+extern u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val);
+
+extern void wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est,
+ u16 num_samps, u8 wait_time,
+ u8 wait_for_crs);
+
+extern void wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write,
+ nphy_iq_comp_t *comp);
+extern void wlc_phy_aci_and_noise_reduction_nphy(phy_info_t *pi);
+
+extern void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask);
+extern u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih);
+
+extern void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type);
+extern void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi);
+extern void wlc_phy_txpwr_apply_nphy(phy_info_t *pi);
+extern void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi);
+extern u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi);
+
+extern nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi);
+extern int wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
+ bool full, bool m);
+extern int wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
+ u8 type, bool d);
+extern void wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask,
+ s8 txpwrindex, bool res);
+extern void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core, u8 rssi_type);
+extern int wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type,
+ s32 *rssi_buf, u8 nsamps);
+extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
+extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
+extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower,
+ bool debug);
+extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
+ u8 mode, u8, bool);
+extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
+extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, s32 *qdBm_pwrbuf,
+ u8 num_samps);
+extern void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi);
+
+extern int wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh);
+
+#define NPHY_TESTPATTERN_BPHY_EVM 0
+#define NPHY_TESTPATTERN_BPHY_RFCS 1
+
+extern void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs);
+
+void wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset,
+ s8 *ofdmoffset);
+extern s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi,
+ chanspec_t chanspec);
+
+extern bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pih);
+#endif /* _BRCM_PHY_INT_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <cfg.h>
+#include <linux/pci.h>
+#include <brcmu_utils.h>
+#include <aiutils.h>
+#include <pmu.h>
+#include <scb.h>
+#include <pub.h>
+
+#include <brcm_hw_ids.h>
+#include <dma.h>
+
+#include "phy_radio.h"
+#include "phy_int.h"
+#include "phy_qmath.h"
+#include "phy_lcn.h"
+#include "phytbl_lcn.h"
+
+#define PLL_2064_NDIV 90
+#define PLL_2064_LOW_END_VCO 3000
+#define PLL_2064_LOW_END_KVCO 27
+#define PLL_2064_HIGH_END_VCO 4200
+#define PLL_2064_HIGH_END_KVCO 68
+#define PLL_2064_LOOP_BW_DOUBLER 200
+#define PLL_2064_D30_DOUBLER 10500
+#define PLL_2064_LOOP_BW 260
+#define PLL_2064_D30 8000
+#define PLL_2064_CAL_REF_TO 8
+#define PLL_2064_MHZ 1000000
+#define PLL_2064_OPEN_LOOP_DELAY 5
+
+#define TEMPSENSE 1
+#define VBATSENSE 2
+
+#define NOISE_IF_UPD_CHK_INTERVAL 1
+#define NOISE_IF_UPD_RST_INTERVAL 60
+#define NOISE_IF_UPD_THRESHOLD_CNT 1
+#define NOISE_IF_UPD_TRHRESHOLD 50
+#define NOISE_IF_UPD_TIMEOUT 1000
+#define NOISE_IF_OFF 0
+#define NOISE_IF_CHK 1
+#define NOISE_IF_ON 2
+
+#define PAPD_BLANKING_PROFILE 3
+#define PAPD2LUT 0
+#define PAPD_CORR_NORM 0
+#define PAPD_BLANKING_THRESHOLD 0
+#define PAPD_STOP_AFTER_LAST_UPDATE 0
+
+#define LCN_TARGET_PWR 60
+
+#define LCN_VBAT_OFFSET_433X 34649679
+#define LCN_VBAT_SLOPE_433X 8258032
+
+#define LCN_VBAT_SCALE_NOM 53
+#define LCN_VBAT_SCALE_DEN 432
+
+#define LCN_TEMPSENSE_OFFSET 80812
+#define LCN_TEMPSENSE_DEN 2647
+
+#define LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT \
+ (0 + 8)
+#define LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK \
+ (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT)
+
+#define LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT \
+ (0 + 8)
+#define LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_MASK \
+ (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT)
+
+#define wlc_lcnphy_enable_tx_gain_override(pi) \
+ wlc_lcnphy_set_tx_gain_override(pi, true)
+#define wlc_lcnphy_disable_tx_gain_override(pi) \
+ wlc_lcnphy_set_tx_gain_override(pi, false)
+
+#define wlc_lcnphy_iqcal_active(pi) \
+ (read_phy_reg((pi), 0x451) & \
+ ((0x1 << 15) | (0x1 << 14)))
+
+#define txpwrctrl_off(pi) (0x7 != ((read_phy_reg(pi, 0x4a4) & 0xE000) >> 13))
+#define wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) \
+ (pi->temppwrctrl_capable)
+#define wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) \
+ (pi->hwpwrctrl_capable)
+
+#define SWCTRL_BT_TX 0x18
+#define SWCTRL_OVR_DISABLE 0x40
+
+#define AFE_CLK_INIT_MODE_TXRX2X 1
+#define AFE_CLK_INIT_MODE_PAPD 0
+
+#define LCNPHY_TBL_ID_IQLOCAL 0x00
+
+#define LCNPHY_TBL_ID_RFSEQ 0x08
+#define LCNPHY_TBL_ID_GAIN_IDX 0x0d
+#define LCNPHY_TBL_ID_SW_CTRL 0x0f
+#define LCNPHY_TBL_ID_GAIN_TBL 0x12
+#define LCNPHY_TBL_ID_SPUR 0x14
+#define LCNPHY_TBL_ID_SAMPLEPLAY 0x15
+#define LCNPHY_TBL_ID_SAMPLEPLAY1 0x16
+
+#define LCNPHY_TX_PWR_CTRL_RATE_OFFSET 832
+#define LCNPHY_TX_PWR_CTRL_MAC_OFFSET 128
+#define LCNPHY_TX_PWR_CTRL_GAIN_OFFSET 192
+#define LCNPHY_TX_PWR_CTRL_IQ_OFFSET 320
+#define LCNPHY_TX_PWR_CTRL_LO_OFFSET 448
+#define LCNPHY_TX_PWR_CTRL_PWR_OFFSET 576
+
+#define LCNPHY_TX_PWR_CTRL_START_INDEX_2G_4313 140
+
+#define LCNPHY_TX_PWR_CTRL_START_NPT 1
+#define LCNPHY_TX_PWR_CTRL_MAX_NPT 7
+
+#define LCNPHY_NOISE_SAMPLES_DEFAULT 5000
+
+#define LCNPHY_ACI_DETECT_START 1
+#define LCNPHY_ACI_DETECT_PROGRESS 2
+#define LCNPHY_ACI_DETECT_STOP 3
+
+#define LCNPHY_ACI_CRSHIFRMLO_TRSH 100
+#define LCNPHY_ACI_GLITCH_TRSH 2000
+#define LCNPHY_ACI_TMOUT 250
+#define LCNPHY_ACI_DETECT_TIMEOUT 2
+#define LCNPHY_ACI_START_DELAY 0
+
+#define wlc_lcnphy_tx_gain_override_enabled(pi) \
+ (0 != (read_phy_reg((pi), 0x43b) & (0x1 << 6)))
+
+#define wlc_lcnphy_total_tx_frames(pi) \
+ wlapi_bmac_read_shm((pi)->sh->physhim, M_UCODE_MACSTAT + offsetof(macstat_t, txallfrm))
+
+typedef struct {
+ u16 gm_gain;
+ u16 pga_gain;
+ u16 pad_gain;
+ u16 dac_gain;
+} lcnphy_txgains_t;
+
+typedef enum {
+ LCNPHY_CAL_FULL,
+ LCNPHY_CAL_RECAL,
+ LCNPHY_CAL_CURRECAL,
+ LCNPHY_CAL_DIGCAL,
+ LCNPHY_CAL_GCTRL
+} lcnphy_cal_mode_t;
+
+typedef struct {
+ lcnphy_txgains_t gains;
+ bool useindex;
+ u8 index;
+} lcnphy_txcalgains_t;
+
+typedef struct {
+ u8 chan;
+ s16 a;
+ s16 b;
+} lcnphy_rx_iqcomp_t;
+
+typedef struct {
+ s16 re;
+ s16 im;
+} lcnphy_spb_tone_t;
+
+typedef struct {
+ u16 re;
+ u16 im;
+} lcnphy_unsign16_struct;
+
+typedef struct {
+ u32 iq_prod;
+ u32 i_pwr;
+ u32 q_pwr;
+} lcnphy_iq_est_t;
+
+typedef struct {
+ u16 ptcentreTs20;
+ u16 ptcentreFactor;
+} lcnphy_sfo_cfg_t;
+
+typedef enum {
+ LCNPHY_PAPD_CAL_CW,
+ LCNPHY_PAPD_CAL_OFDM
+} lcnphy_papd_cal_type_t;
+
+typedef u16 iqcal_gain_params_lcnphy[9];
+
+static const iqcal_gain_params_lcnphy tbl_iqcal_gainparams_lcnphy_2G[] = {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0},
+};
+
+static const iqcal_gain_params_lcnphy *tbl_iqcal_gainparams_lcnphy[1] = {
+ tbl_iqcal_gainparams_lcnphy_2G,
+};
+
+static const u16 iqcal_gainparams_numgains_lcnphy[1] = {
+ sizeof(tbl_iqcal_gainparams_lcnphy_2G) /
+ sizeof(*tbl_iqcal_gainparams_lcnphy_2G),
+};
+
+static const lcnphy_sfo_cfg_t lcnphy_sfo_cfg[] = {
+ {965, 1087},
+ {967, 1085},
+ {969, 1082},
+ {971, 1080},
+ {973, 1078},
+ {975, 1076},
+ {977, 1073},
+ {979, 1071},
+ {981, 1069},
+ {983, 1067},
+ {985, 1065},
+ {987, 1063},
+ {989, 1060},
+ {994, 1055}
+};
+
+static const
+u16 lcnphy_iqcal_loft_gainladder[] = {
+ ((2 << 8) | 0),
+ ((3 << 8) | 0),
+ ((4 << 8) | 0),
+ ((6 << 8) | 0),
+ ((8 << 8) | 0),
+ ((11 << 8) | 0),
+ ((16 << 8) | 0),
+ ((16 << 8) | 1),
+ ((16 << 8) | 2),
+ ((16 << 8) | 3),
+ ((16 << 8) | 4),
+ ((16 << 8) | 5),
+ ((16 << 8) | 6),
+ ((16 << 8) | 7),
+ ((23 << 8) | 7),
+ ((32 << 8) | 7),
+ ((45 << 8) | 7),
+ ((64 << 8) | 7),
+ ((91 << 8) | 7),
+ ((128 << 8) | 7)
+};
+
+static const
+u16 lcnphy_iqcal_ir_gainladder[] = {
+ ((1 << 8) | 0),
+ ((2 << 8) | 0),
+ ((4 << 8) | 0),
+ ((6 << 8) | 0),
+ ((8 << 8) | 0),
+ ((11 << 8) | 0),
+ ((16 << 8) | 0),
+ ((23 << 8) | 0),
+ ((32 << 8) | 0),
+ ((45 << 8) | 0),
+ ((64 << 8) | 0),
+ ((64 << 8) | 1),
+ ((64 << 8) | 2),
+ ((64 << 8) | 3),
+ ((64 << 8) | 4),
+ ((64 << 8) | 5),
+ ((64 << 8) | 6),
+ ((64 << 8) | 7),
+ ((91 << 8) | 7),
+ ((128 << 8) | 7)
+};
+
+static const
+lcnphy_spb_tone_t lcnphy_spb_tone_3750[] = {
+ {88, 0},
+ {73, 49},
+ {34, 81},
+ {-17, 86},
+ {-62, 62},
+ {-86, 17},
+ {-81, -34},
+ {-49, -73},
+ {0, -88},
+ {49, -73},
+ {81, -34},
+ {86, 17},
+ {62, 62},
+ {17, 86},
+ {-34, 81},
+ {-73, 49},
+ {-88, 0},
+ {-73, -49},
+ {-34, -81},
+ {17, -86},
+ {62, -62},
+ {86, -17},
+ {81, 34},
+ {49, 73},
+ {0, 88},
+ {-49, 73},
+ {-81, 34},
+ {-86, -17},
+ {-62, -62},
+ {-17, -86},
+ {34, -81},
+ {73, -49},
+};
+
+static const
+u16 iqlo_loopback_rf_regs[20] = {
+ RADIO_2064_REG036,
+ RADIO_2064_REG11A,
+ RADIO_2064_REG03A,
+ RADIO_2064_REG025,
+ RADIO_2064_REG028,
+ RADIO_2064_REG005,
+ RADIO_2064_REG112,
+ RADIO_2064_REG0FF,
+ RADIO_2064_REG11F,
+ RADIO_2064_REG00B,
+ RADIO_2064_REG113,
+ RADIO_2064_REG007,
+ RADIO_2064_REG0FC,
+ RADIO_2064_REG0FD,
+ RADIO_2064_REG012,
+ RADIO_2064_REG057,
+ RADIO_2064_REG059,
+ RADIO_2064_REG05C,
+ RADIO_2064_REG078,
+ RADIO_2064_REG092,
+};
+
+static const
+u16 tempsense_phy_regs[14] = {
+ 0x503,
+ 0x4a4,
+ 0x4d0,
+ 0x4d9,
+ 0x4da,
+ 0x4a6,
+ 0x938,
+ 0x939,
+ 0x4d8,
+ 0x4d0,
+ 0x4d7,
+ 0x4a5,
+ 0x40d,
+ 0x4a2,
+};
+
+static const
+u16 rxiq_cal_rf_reg[11] = {
+ RADIO_2064_REG098,
+ RADIO_2064_REG116,
+ RADIO_2064_REG12C,
+ RADIO_2064_REG06A,
+ RADIO_2064_REG00B,
+ RADIO_2064_REG01B,
+ RADIO_2064_REG113,
+ RADIO_2064_REG01D,
+ RADIO_2064_REG114,
+ RADIO_2064_REG02E,
+ RADIO_2064_REG12A,
+};
+
+static const
+lcnphy_rx_iqcomp_t lcnphy_rx_iqcomp_table_rev0[] = {
+ {1, 0, 0},
+ {2, 0, 0},
+ {3, 0, 0},
+ {4, 0, 0},
+ {5, 0, 0},
+ {6, 0, 0},
+ {7, 0, 0},
+ {8, 0, 0},
+ {9, 0, 0},
+ {10, 0, 0},
+ {11, 0, 0},
+ {12, 0, 0},
+ {13, 0, 0},
+ {14, 0, 0},
+ {34, 0, 0},
+ {38, 0, 0},
+ {42, 0, 0},
+ {46, 0, 0},
+ {36, 0, 0},
+ {40, 0, 0},
+ {44, 0, 0},
+ {48, 0, 0},
+ {52, 0, 0},
+ {56, 0, 0},
+ {60, 0, 0},
+ {64, 0, 0},
+ {100, 0, 0},
+ {104, 0, 0},
+ {108, 0, 0},
+ {112, 0, 0},
+ {116, 0, 0},
+ {120, 0, 0},
+ {124, 0, 0},
+ {128, 0, 0},
+ {132, 0, 0},
+ {136, 0, 0},
+ {140, 0, 0},
+ {149, 0, 0},
+ {153, 0, 0},
+ {157, 0, 0},
+ {161, 0, 0},
+ {165, 0, 0},
+ {184, 0, 0},
+ {188, 0, 0},
+ {192, 0, 0},
+ {196, 0, 0},
+ {200, 0, 0},
+ {204, 0, 0},
+ {208, 0, 0},
+ {212, 0, 0},
+ {216, 0, 0},
+};
+
+static const u32 lcnphy_23bitgaincode_table[] = {
+ 0x200100,
+ 0x200200,
+ 0x200004,
+ 0x200014,
+ 0x200024,
+ 0x200034,
+ 0x200134,
+ 0x200234,
+ 0x200334,
+ 0x200434,
+ 0x200037,
+ 0x200137,
+ 0x200237,
+ 0x200337,
+ 0x200437,
+ 0x000035,
+ 0x000135,
+ 0x000235,
+ 0x000037,
+ 0x000137,
+ 0x000237,
+ 0x000337,
+ 0x00013f,
+ 0x00023f,
+ 0x00033f,
+ 0x00034f,
+ 0x00044f,
+ 0x00144f,
+ 0x00244f,
+ 0x00254f,
+ 0x00354f,
+ 0x00454f,
+ 0x00464f,
+ 0x01464f,
+ 0x02464f,
+ 0x03464f,
+ 0x04464f,
+};
+
+static const s8 lcnphy_gain_table[] = {
+ -16,
+ -13,
+ 10,
+ 7,
+ 4,
+ 0,
+ 3,
+ 6,
+ 9,
+ 12,
+ 15,
+ 18,
+ 21,
+ 24,
+ 27,
+ 30,
+ 33,
+ 36,
+ 39,
+ 42,
+ 45,
+ 48,
+ 50,
+ 53,
+ 56,
+ 59,
+ 62,
+ 65,
+ 68,
+ 71,
+ 74,
+ 77,
+ 80,
+ 83,
+ 86,
+ 89,
+ 92,
+};
+
+static const s8 lcnphy_gain_index_offset_for_rssi[] = {
+ 7,
+ 7,
+ 7,
+ 7,
+ 7,
+ 7,
+ 7,
+ 8,
+ 7,
+ 7,
+ 6,
+ 7,
+ 7,
+ 4,
+ 4,
+ 4,
+ 4,
+ 4,
+ 4,
+ 4,
+ 4,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 3,
+ 4,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ 2,
+ -1,
+ -2,
+ -2,
+ -2
+};
+
+extern const u8 spur_tbl_rev0[];
+extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev1;
+extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev1[];
+extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa;
+extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250;
+
+typedef struct _chan_info_2064_lcnphy {
+ uint chan;
+ uint freq;
+ u8 logen_buftune;
+ u8 logen_rccr_tx;
+ u8 txrf_mix_tune_ctrl;
+ u8 pa_input_tune_g;
+ u8 logen_rccr_rx;
+ u8 pa_rxrf_lna1_freq_tune;
+ u8 pa_rxrf_lna2_freq_tune;
+ u8 rxrf_rxrf_spare1;
+} chan_info_2064_lcnphy_t;
+
+static chan_info_2064_lcnphy_t chan_info_2064_lcnphy[] = {
+ {1, 2412, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {2, 2417, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {3, 2422, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {4, 2427, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {5, 2432, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {6, 2437, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {7, 2442, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {8, 2447, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {9, 2452, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {10, 2457, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {11, 2462, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {12, 2467, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {13, 2472, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+ {14, 2484, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
+};
+
+lcnphy_radio_regs_t lcnphy_radio_regs_2064[] = {
+ {0x00, 0, 0, 0, 0},
+ {0x01, 0x64, 0x64, 0, 0},
+ {0x02, 0x20, 0x20, 0, 0},
+ {0x03, 0x66, 0x66, 0, 0},
+ {0x04, 0xf8, 0xf8, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0x10, 0x10, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0x37, 0x37, 0, 0},
+ {0x0B, 0x6, 0x6, 0, 0},
+ {0x0C, 0x55, 0x55, 0, 0},
+ {0x0D, 0x8b, 0x8b, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0x5, 0x5, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0xe, 0xe, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0xb, 0xb, 0, 0},
+ {0x14, 0x2, 0x2, 0, 0},
+ {0x15, 0x12, 0x12, 0, 0},
+ {0x16, 0x12, 0x12, 0, 0},
+ {0x17, 0xc, 0xc, 0, 0},
+ {0x18, 0xc, 0xc, 0, 0},
+ {0x19, 0xc, 0xc, 0, 0},
+ {0x1A, 0x8, 0x8, 0, 0},
+ {0x1B, 0x2, 0x2, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0x1, 0x1, 0, 0},
+ {0x1E, 0x12, 0x12, 0, 0},
+ {0x1F, 0x6e, 0x6e, 0, 0},
+ {0x20, 0x2, 0x2, 0, 0},
+ {0x21, 0x23, 0x23, 0, 0},
+ {0x22, 0x8, 0x8, 0, 0},
+ {0x23, 0, 0, 0, 0},
+ {0x24, 0, 0, 0, 0},
+ {0x25, 0xc, 0xc, 0, 0},
+ {0x26, 0x33, 0x33, 0, 0},
+ {0x27, 0x55, 0x55, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0x30, 0x30, 0, 0},
+ {0x2A, 0xb, 0xb, 0, 0},
+ {0x2B, 0x1b, 0x1b, 0, 0},
+ {0x2C, 0x3, 0x3, 0, 0},
+ {0x2D, 0x1b, 0x1b, 0, 0},
+ {0x2E, 0, 0, 0, 0},
+ {0x2F, 0x20, 0x20, 0, 0},
+ {0x30, 0xa, 0xa, 0, 0},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0x62, 0x62, 0, 0},
+ {0x33, 0x19, 0x19, 0, 0},
+ {0x34, 0x33, 0x33, 0, 0},
+ {0x35, 0x77, 0x77, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0x70, 0x70, 0, 0},
+ {0x38, 0x3, 0x3, 0, 0},
+ {0x39, 0xf, 0xf, 0, 0},
+ {0x3A, 0x6, 0x6, 0, 0},
+ {0x3B, 0xcf, 0xcf, 0, 0},
+ {0x3C, 0x1a, 0x1a, 0, 0},
+ {0x3D, 0x6, 0x6, 0, 0},
+ {0x3E, 0x42, 0x42, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0xfb, 0xfb, 0, 0},
+ {0x41, 0x9a, 0x9a, 0, 0},
+ {0x42, 0x7a, 0x7a, 0, 0},
+ {0x43, 0x29, 0x29, 0, 0},
+ {0x44, 0, 0, 0, 0},
+ {0x45, 0x8, 0x8, 0, 0},
+ {0x46, 0xce, 0xce, 0, 0},
+ {0x47, 0x27, 0x27, 0, 0},
+ {0x48, 0x62, 0x62, 0, 0},
+ {0x49, 0x6, 0x6, 0, 0},
+ {0x4A, 0x58, 0x58, 0, 0},
+ {0x4B, 0xf7, 0xf7, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0xb3, 0xb3, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0x2, 0x2, 0, 0},
+ {0x50, 0, 0, 0, 0},
+ {0x51, 0x9, 0x9, 0, 0},
+ {0x52, 0x5, 0x5, 0, 0},
+ {0x53, 0x17, 0x17, 0, 0},
+ {0x54, 0x38, 0x38, 0, 0},
+ {0x55, 0, 0, 0, 0},
+ {0x56, 0, 0, 0, 0},
+ {0x57, 0xb, 0xb, 0, 0},
+ {0x58, 0, 0, 0, 0},
+ {0x59, 0, 0, 0, 0},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0, 0, 0, 0},
+ {0x5C, 0, 0, 0, 0},
+ {0x5D, 0, 0, 0, 0},
+ {0x5E, 0x88, 0x88, 0, 0},
+ {0x5F, 0xcc, 0xcc, 0, 0},
+ {0x60, 0x74, 0x74, 0, 0},
+ {0x61, 0x74, 0x74, 0, 0},
+ {0x62, 0x74, 0x74, 0, 0},
+ {0x63, 0x44, 0x44, 0, 0},
+ {0x64, 0x77, 0x77, 0, 0},
+ {0x65, 0x44, 0x44, 0, 0},
+ {0x66, 0x77, 0x77, 0, 0},
+ {0x67, 0x55, 0x55, 0, 0},
+ {0x68, 0x77, 0x77, 0, 0},
+ {0x69, 0x77, 0x77, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0x7f, 0x7f, 0, 0},
+ {0x6C, 0x8, 0x8, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0x88, 0x88, 0, 0},
+ {0x6F, 0x66, 0x66, 0, 0},
+ {0x70, 0x66, 0x66, 0, 0},
+ {0x71, 0x28, 0x28, 0, 0},
+ {0x72, 0x55, 0x55, 0, 0},
+ {0x73, 0x4, 0x4, 0, 0},
+ {0x74, 0, 0, 0, 0},
+ {0x75, 0, 0, 0, 0},
+ {0x76, 0, 0, 0, 0},
+ {0x77, 0x1, 0x1, 0, 0},
+ {0x78, 0xd6, 0xd6, 0, 0},
+ {0x79, 0, 0, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0xb4, 0xb4, 0, 0},
+ {0x84, 0x1, 0x1, 0, 0},
+ {0x85, 0x20, 0x20, 0, 0},
+ {0x86, 0x5, 0x5, 0, 0},
+ {0x87, 0xff, 0xff, 0, 0},
+ {0x88, 0x7, 0x7, 0, 0},
+ {0x89, 0x77, 0x77, 0, 0},
+ {0x8A, 0x77, 0x77, 0, 0},
+ {0x8B, 0x77, 0x77, 0, 0},
+ {0x8C, 0x77, 0x77, 0, 0},
+ {0x8D, 0x8, 0x8, 0, 0},
+ {0x8E, 0xa, 0xa, 0, 0},
+ {0x8F, 0x8, 0x8, 0, 0},
+ {0x90, 0x18, 0x18, 0, 0},
+ {0x91, 0x5, 0x5, 0, 0},
+ {0x92, 0x1f, 0x1f, 0, 0},
+ {0x93, 0x10, 0x10, 0, 0},
+ {0x94, 0x3, 0x3, 0, 0},
+ {0x95, 0, 0, 0, 0},
+ {0x96, 0, 0, 0, 0},
+ {0x97, 0xaa, 0xaa, 0, 0},
+ {0x98, 0, 0, 0, 0},
+ {0x99, 0x23, 0x23, 0, 0},
+ {0x9A, 0x7, 0x7, 0, 0},
+ {0x9B, 0xf, 0xf, 0, 0},
+ {0x9C, 0x10, 0x10, 0, 0},
+ {0x9D, 0x3, 0x3, 0, 0},
+ {0x9E, 0x4, 0x4, 0, 0},
+ {0x9F, 0x20, 0x20, 0, 0},
+ {0xA0, 0, 0, 0, 0},
+ {0xA1, 0, 0, 0, 0},
+ {0xA2, 0, 0, 0, 0},
+ {0xA3, 0, 0, 0, 0},
+ {0xA4, 0x1, 0x1, 0, 0},
+ {0xA5, 0x77, 0x77, 0, 0},
+ {0xA6, 0x77, 0x77, 0, 0},
+ {0xA7, 0x77, 0x77, 0, 0},
+ {0xA8, 0x77, 0x77, 0, 0},
+ {0xA9, 0x8c, 0x8c, 0, 0},
+ {0xAA, 0x88, 0x88, 0, 0},
+ {0xAB, 0x78, 0x78, 0, 0},
+ {0xAC, 0x57, 0x57, 0, 0},
+ {0xAD, 0x88, 0x88, 0, 0},
+ {0xAE, 0, 0, 0, 0},
+ {0xAF, 0x8, 0x8, 0, 0},
+ {0xB0, 0x88, 0x88, 0, 0},
+ {0xB1, 0, 0, 0, 0},
+ {0xB2, 0x1b, 0x1b, 0, 0},
+ {0xB3, 0x3, 0x3, 0, 0},
+ {0xB4, 0x24, 0x24, 0, 0},
+ {0xB5, 0x3, 0x3, 0, 0},
+ {0xB6, 0x1b, 0x1b, 0, 0},
+ {0xB7, 0x24, 0x24, 0, 0},
+ {0xB8, 0x3, 0x3, 0, 0},
+ {0xB9, 0, 0, 0, 0},
+ {0xBA, 0xaa, 0xaa, 0, 0},
+ {0xBB, 0, 0, 0, 0},
+ {0xBC, 0x4, 0x4, 0, 0},
+ {0xBD, 0, 0, 0, 0},
+ {0xBE, 0x8, 0x8, 0, 0},
+ {0xBF, 0x11, 0x11, 0, 0},
+ {0xC0, 0, 0, 0, 0},
+ {0xC1, 0, 0, 0, 0},
+ {0xC2, 0x62, 0x62, 0, 0},
+ {0xC3, 0x1e, 0x1e, 0, 0},
+ {0xC4, 0x33, 0x33, 0, 0},
+ {0xC5, 0x37, 0x37, 0, 0},
+ {0xC6, 0, 0, 0, 0},
+ {0xC7, 0x70, 0x70, 0, 0},
+ {0xC8, 0x1e, 0x1e, 0, 0},
+ {0xC9, 0x6, 0x6, 0, 0},
+ {0xCA, 0x4, 0x4, 0, 0},
+ {0xCB, 0x2f, 0x2f, 0, 0},
+ {0xCC, 0xf, 0xf, 0, 0},
+ {0xCD, 0, 0, 0, 0},
+ {0xCE, 0xff, 0xff, 0, 0},
+ {0xCF, 0x8, 0x8, 0, 0},
+ {0xD0, 0x3f, 0x3f, 0, 0},
+ {0xD1, 0x3f, 0x3f, 0, 0},
+ {0xD2, 0x3f, 0x3f, 0, 0},
+ {0xD3, 0, 0, 0, 0},
+ {0xD4, 0, 0, 0, 0},
+ {0xD5, 0, 0, 0, 0},
+ {0xD6, 0xcc, 0xcc, 0, 0},
+ {0xD7, 0, 0, 0, 0},
+ {0xD8, 0x8, 0x8, 0, 0},
+ {0xD9, 0x8, 0x8, 0, 0},
+ {0xDA, 0x8, 0x8, 0, 0},
+ {0xDB, 0x11, 0x11, 0, 0},
+ {0xDC, 0, 0, 0, 0},
+ {0xDD, 0x87, 0x87, 0, 0},
+ {0xDE, 0x88, 0x88, 0, 0},
+ {0xDF, 0x8, 0x8, 0, 0},
+ {0xE0, 0x8, 0x8, 0, 0},
+ {0xE1, 0x8, 0x8, 0, 0},
+ {0xE2, 0, 0, 0, 0},
+ {0xE3, 0, 0, 0, 0},
+ {0xE4, 0, 0, 0, 0},
+ {0xE5, 0xf5, 0xf5, 0, 0},
+ {0xE6, 0x30, 0x30, 0, 0},
+ {0xE7, 0x1, 0x1, 0, 0},
+ {0xE8, 0, 0, 0, 0},
+ {0xE9, 0xff, 0xff, 0, 0},
+ {0xEA, 0, 0, 0, 0},
+ {0xEB, 0, 0, 0, 0},
+ {0xEC, 0x22, 0x22, 0, 0},
+ {0xED, 0, 0, 0, 0},
+ {0xEE, 0, 0, 0, 0},
+ {0xEF, 0, 0, 0, 0},
+ {0xF0, 0x3, 0x3, 0, 0},
+ {0xF1, 0x1, 0x1, 0, 0},
+ {0xF2, 0, 0, 0, 0},
+ {0xF3, 0, 0, 0, 0},
+ {0xF4, 0, 0, 0, 0},
+ {0xF5, 0, 0, 0, 0},
+ {0xF6, 0, 0, 0, 0},
+ {0xF7, 0x6, 0x6, 0, 0},
+ {0xF8, 0, 0, 0, 0},
+ {0xF9, 0, 0, 0, 0},
+ {0xFA, 0x40, 0x40, 0, 0},
+ {0xFB, 0, 0, 0, 0},
+ {0xFC, 0x1, 0x1, 0, 0},
+ {0xFD, 0x80, 0x80, 0, 0},
+ {0xFE, 0x2, 0x2, 0, 0},
+ {0xFF, 0x10, 0x10, 0, 0},
+ {0x100, 0x2, 0x2, 0, 0},
+ {0x101, 0x1e, 0x1e, 0, 0},
+ {0x102, 0x1e, 0x1e, 0, 0},
+ {0x103, 0, 0, 0, 0},
+ {0x104, 0x1f, 0x1f, 0, 0},
+ {0x105, 0, 0x8, 0, 1},
+ {0x106, 0x2a, 0x2a, 0, 0},
+ {0x107, 0xf, 0xf, 0, 0},
+ {0x108, 0, 0, 0, 0},
+ {0x109, 0, 0, 0, 0},
+ {0x10A, 0, 0, 0, 0},
+ {0x10B, 0, 0, 0, 0},
+ {0x10C, 0, 0, 0, 0},
+ {0x10D, 0, 0, 0, 0},
+ {0x10E, 0, 0, 0, 0},
+ {0x10F, 0, 0, 0, 0},
+ {0x110, 0, 0, 0, 0},
+ {0x111, 0, 0, 0, 0},
+ {0x112, 0, 0, 0, 0},
+ {0x113, 0, 0, 0, 0},
+ {0x114, 0, 0, 0, 0},
+ {0x115, 0, 0, 0, 0},
+ {0x116, 0, 0, 0, 0},
+ {0x117, 0, 0, 0, 0},
+ {0x118, 0, 0, 0, 0},
+ {0x119, 0, 0, 0, 0},
+ {0x11A, 0, 0, 0, 0},
+ {0x11B, 0, 0, 0, 0},
+ {0x11C, 0x1, 0x1, 0, 0},
+ {0x11D, 0, 0, 0, 0},
+ {0x11E, 0, 0, 0, 0},
+ {0x11F, 0, 0, 0, 0},
+ {0x120, 0, 0, 0, 0},
+ {0x121, 0, 0, 0, 0},
+ {0x122, 0x80, 0x80, 0, 0},
+ {0x123, 0, 0, 0, 0},
+ {0x124, 0xf8, 0xf8, 0, 0},
+ {0x125, 0, 0, 0, 0},
+ {0x126, 0, 0, 0, 0},
+ {0x127, 0, 0, 0, 0},
+ {0x128, 0, 0, 0, 0},
+ {0x129, 0, 0, 0, 0},
+ {0x12A, 0, 0, 0, 0},
+ {0x12B, 0, 0, 0, 0},
+ {0x12C, 0, 0, 0, 0},
+ {0x12D, 0, 0, 0, 0},
+ {0x12E, 0, 0, 0, 0},
+ {0x12F, 0, 0, 0, 0},
+ {0x130, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+#define LCNPHY_NUM_DIG_FILT_COEFFS 16
+#define LCNPHY_NUM_TX_DIG_FILTERS_CCK 13
+
+u16
+ LCNPHY_txdigfiltcoeffs_cck[LCNPHY_NUM_TX_DIG_FILTERS_CCK]
+ [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = {
+ {0, 1, 415, 1874, 64, 128, 64, 792, 1656, 64, 128, 64, 778, 1582, 64,
+ 128, 64,},
+ {1, 1, 402, 1847, 259, 59, 259, 671, 1794, 68, 54, 68, 608, 1863, 93,
+ 167, 93,},
+ {2, 1, 415, 1874, 64, 128, 64, 792, 1656, 192, 384, 192, 778, 1582, 64,
+ 128, 64,},
+ {3, 1, 302, 1841, 129, 258, 129, 658, 1720, 205, 410, 205, 754, 1760,
+ 170, 340, 170,},
+ {20, 1, 360, 1884, 242, 1734, 242, 752, 1720, 205, 1845, 205, 767, 1760,
+ 256, 185, 256,},
+ {21, 1, 360, 1884, 149, 1874, 149, 752, 1720, 205, 1883, 205, 767, 1760,
+ 256, 273, 256,},
+ {22, 1, 360, 1884, 98, 1948, 98, 752, 1720, 205, 1924, 205, 767, 1760,
+ 256, 352, 256,},
+ {23, 1, 350, 1884, 116, 1966, 116, 752, 1720, 205, 2008, 205, 767, 1760,
+ 128, 233, 128,},
+ {24, 1, 325, 1884, 32, 40, 32, 756, 1720, 256, 471, 256, 766, 1760, 256,
+ 1881, 256,},
+ {25, 1, 299, 1884, 51, 64, 51, 736, 1720, 256, 471, 256, 765, 1760, 256,
+ 1881, 256,},
+ {26, 1, 277, 1943, 39, 117, 88, 637, 1838, 64, 192, 144, 614, 1864, 128,
+ 384, 288,},
+ {27, 1, 245, 1943, 49, 147, 110, 626, 1838, 256, 768, 576, 613, 1864,
+ 128, 384, 288,},
+ {30, 1, 302, 1841, 61, 122, 61, 658, 1720, 205, 410, 205, 754, 1760,
+ 170, 340, 170,},
+};
+
+#define LCNPHY_NUM_TX_DIG_FILTERS_OFDM 3
+u16
+ LCNPHY_txdigfiltcoeffs_ofdm[LCNPHY_NUM_TX_DIG_FILTERS_OFDM]
+ [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = {
+ {0, 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0, 0x0,
+ 0x278, 0xfea0, 0x80, 0x100, 0x80,},
+ {1, 0, 374, 0xFF79, 16, 32, 16, 799, 0xFE74, 50, 32, 50,
+ 750, 0xFE2B, 212, 0xFFCE, 212,},
+ {2, 0, 375, 0xFF16, 37, 76, 37, 799, 0xFE74, 32, 20, 32, 748,
+ 0xFEF2, 128, 0xFFE2, 128}
+};
+
+#define wlc_lcnphy_set_start_tx_pwr_idx(pi, idx) \
+ mod_phy_reg(pi, 0x4a4, \
+ (0x1ff << 0), \
+ (u16)(idx) << 0)
+
+#define wlc_lcnphy_set_tx_pwr_npt(pi, npt) \
+ mod_phy_reg(pi, 0x4a5, \
+ (0x7 << 8), \
+ (u16)(npt) << 8)
+
+#define wlc_lcnphy_get_tx_pwr_ctrl(pi) \
+ (read_phy_reg((pi), 0x4a4) & \
+ ((0x1 << 15) | \
+ (0x1 << 14) | \
+ (0x1 << 13)))
+
+#define wlc_lcnphy_get_tx_pwr_npt(pi) \
+ ((read_phy_reg(pi, 0x4a5) & \
+ (0x7 << 8)) >> \
+ 8)
+
+#define wlc_lcnphy_get_current_tx_pwr_idx_if_pwrctrl_on(pi) \
+ (read_phy_reg(pi, 0x473) & 0x1ff)
+
+#define wlc_lcnphy_get_target_tx_pwr(pi) \
+ ((read_phy_reg(pi, 0x4a7) & \
+ (0xff << 0)) >> \
+ 0)
+
+#define wlc_lcnphy_set_target_tx_pwr(pi, target) \
+ mod_phy_reg(pi, 0x4a7, \
+ (0xff << 0), \
+ (u16)(target) << 0)
+
+#define wlc_radio_2064_rcal_done(pi) (0 != (read_radio_reg(pi, RADIO_2064_REG05C) & 0x20))
+#define tempsense_done(pi) (0x8000 == (read_phy_reg(pi, 0x476) & 0x8000))
+
+#define LCNPHY_IQLOCC_READ(val) ((u8)(-(s8)(((val) & 0xf0) >> 4) + (s8)((val) & 0x0f)))
+#define FIXED_TXPWR 78
+#define LCNPHY_TEMPSENSE(val) ((s16)((val > 255) ? (val - 512) : val))
+
+static u32 wlc_lcnphy_qdiv_roundup(u32 divident, u32 divisor,
+ u8 precision);
+static void wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi,
+ u16 ext_lna, u16 trsw,
+ u16 biq2, u16 biq1,
+ u16 tia, u16 lna2,
+ u16 lna1);
+static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi);
+static void wlc_lcnphy_set_pa_gain(phy_info_t *pi, u16 gain);
+static void wlc_lcnphy_set_trsw_override(phy_info_t *pi, bool tx, bool rx);
+static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0);
+static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi);
+static void wlc_lcnphy_get_tx_gain(phy_info_t *pi, lcnphy_txgains_t *gains);
+static void wlc_lcnphy_set_tx_gain_override(phy_info_t *pi, bool bEnable);
+static void wlc_lcnphy_toggle_afe_pwdn(phy_info_t *pi);
+static void wlc_lcnphy_rx_gain_override_enable(phy_info_t *pi, bool enable);
+static void wlc_lcnphy_set_tx_gain(phy_info_t *pi,
+ lcnphy_txgains_t *target_gains);
+static bool wlc_lcnphy_rx_iq_est(phy_info_t *pi, u16 num_samps,
+ u8 wait_time, lcnphy_iq_est_t *iq_est);
+static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps);
+static u16 wlc_lcnphy_get_pa_gain(phy_info_t *pi);
+static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode);
+extern void wlc_lcnphy_tx_pwr_ctrl_init(wlc_phy_t *ppi);
+static void wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi,
+ u8 channel);
+
+static void wlc_lcnphy_load_tx_gain_table(phy_info_t *pi,
+ const lcnphy_tx_gain_tbl_entry *g);
+
+static void wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo,
+ u16 thresh, s16 *ptr, int mode);
+static int wlc_lcnphy_calc_floor(s16 coeff, int type);
+static void wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi,
+ u16 *values_to_save);
+static void wlc_lcnphy_tx_iqlo_loopback_cleanup(phy_info_t *pi,
+ u16 *values_to_save);
+static void wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, s16 coeff_x,
+ s16 coeff_y);
+static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type);
+static void wlc_lcnphy_a1(phy_info_t *pi, int cal_type,
+ int num_levels, int step_size_lg2);
+static void wlc_lcnphy_tx_iqlo_soft_cal_full(phy_info_t *pi);
+
+static void wlc_lcnphy_set_chanspec_tweaks(phy_info_t *pi,
+ chanspec_t chanspec);
+static void wlc_lcnphy_agc_temp_init(phy_info_t *pi);
+static void wlc_lcnphy_temp_adj(phy_info_t *pi);
+static void wlc_lcnphy_clear_papd_comptable(phy_info_t *pi);
+static void wlc_lcnphy_baseband_init(phy_info_t *pi);
+static void wlc_lcnphy_radio_init(phy_info_t *pi);
+static void wlc_lcnphy_rc_cal(phy_info_t *pi);
+static void wlc_lcnphy_rcal(phy_info_t *pi);
+static void wlc_lcnphy_txrx_spur_avoidance_mode(phy_info_t *pi, bool enable);
+static int wlc_lcnphy_load_tx_iir_filter(phy_info_t *pi, bool is_ofdm,
+ s16 filt_type);
+static void wlc_lcnphy_set_rx_iq_comp(phy_info_t *pi, u16 a, u16 b);
+
+void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti)
+{
+ wlc_phy_write_table(pi, pti, 0x455, 0x457, 0x456);
+}
+
+void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti)
+{
+ wlc_phy_read_table(pi, pti, 0x455, 0x457, 0x456);
+}
+
+static void
+wlc_lcnphy_common_read_table(phy_info_t *pi, u32 tbl_id,
+ const void *tbl_ptr, u32 tbl_len,
+ u32 tbl_width, u32 tbl_offset)
+{
+ phytbl_info_t tab;
+ tab.tbl_id = tbl_id;
+ tab.tbl_ptr = tbl_ptr;
+ tab.tbl_len = tbl_len;
+ tab.tbl_width = tbl_width;
+ tab.tbl_offset = tbl_offset;
+ wlc_lcnphy_read_table(pi, &tab);
+}
+
+static void
+wlc_lcnphy_common_write_table(phy_info_t *pi, u32 tbl_id,
+ const void *tbl_ptr, u32 tbl_len,
+ u32 tbl_width, u32 tbl_offset)
+{
+
+ phytbl_info_t tab;
+ tab.tbl_id = tbl_id;
+ tab.tbl_ptr = tbl_ptr;
+ tab.tbl_len = tbl_len;
+ tab.tbl_width = tbl_width;
+ tab.tbl_offset = tbl_offset;
+ wlc_lcnphy_write_table(pi, &tab);
+}
+
+static u32
+wlc_lcnphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
+{
+ u32 quotient, remainder, roundup, rbit;
+
+ quotient = dividend / divisor;
+ remainder = dividend % divisor;
+ rbit = divisor & 1;
+ roundup = (divisor >> 1) + rbit;
+
+ while (precision--) {
+ quotient <<= 1;
+ if (remainder >= roundup) {
+ quotient++;
+ remainder = ((remainder - roundup) << 1) + rbit;
+ } else {
+ remainder <<= 1;
+ }
+ }
+
+ if (remainder >= roundup)
+ quotient++;
+
+ return quotient;
+}
+
+static int wlc_lcnphy_calc_floor(s16 coeff_x, int type)
+{
+ int k;
+ k = 0;
+ if (type == 0) {
+ if (coeff_x < 0) {
+ k = (coeff_x - 1) / 2;
+ } else {
+ k = coeff_x / 2;
+ }
+ }
+ if (type == 1) {
+ if ((coeff_x + 1) < 0)
+ k = (coeff_x) / 2;
+ else
+ k = (coeff_x + 1) / 2;
+ }
+ return k;
+}
+
+s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi)
+{
+ s8 index;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (txpwrctrl_off(pi))
+ index = pi_lcn->lcnphy_current_index;
+ else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
+ index =
+ (s8) (wlc_lcnphy_get_current_tx_pwr_idx_if_pwrctrl_on(pi)
+ / 2);
+ else
+ index = pi_lcn->lcnphy_current_index;
+ return index;
+}
+
+static u32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, u16 nsamples)
+{
+ lcnphy_iq_est_t iq_est = { 0, 0, 0 };
+
+ if (!wlc_lcnphy_rx_iq_est(pi, nsamples, 32, &iq_est))
+ return 0;
+ return (iq_est.i_pwr + iq_est.q_pwr) / nsamples;
+}
+
+void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel)
+{
+ u16 afectrlovr, afectrlovrval;
+ afectrlovr = read_phy_reg(pi, 0x43b);
+ afectrlovrval = read_phy_reg(pi, 0x43c);
+ if (channel != 0) {
+ mod_phy_reg(pi, 0x43b, (0x1 << 1), (1) << 1);
+
+ mod_phy_reg(pi, 0x43c, (0x1 << 1), (0) << 1);
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 4), (1) << 4);
+
+ mod_phy_reg(pi, 0x43c, (0x1 << 6), (0) << 6);
+
+ write_phy_reg(pi, 0x44b, 0xffff);
+ wlc_lcnphy_tx_pu(pi, 1);
+
+ mod_phy_reg(pi, 0x634, (0xff << 8), (0) << 8);
+
+ or_phy_reg(pi, 0x6da, 0x0080);
+
+ or_phy_reg(pi, 0x00a, 0x228);
+ } else {
+ and_phy_reg(pi, 0x00a, ~(0x228));
+
+ and_phy_reg(pi, 0x6da, 0xFF7F);
+ write_phy_reg(pi, 0x43b, afectrlovr);
+ write_phy_reg(pi, 0x43c, afectrlovrval);
+ }
+}
+
+static void wlc_lcnphy_toggle_afe_pwdn(phy_info_t *pi)
+{
+ u16 save_AfeCtrlOvrVal, save_AfeCtrlOvr;
+
+ save_AfeCtrlOvrVal = read_phy_reg(pi, 0x43c);
+ save_AfeCtrlOvr = read_phy_reg(pi, 0x43b);
+
+ write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal | 0x1);
+ write_phy_reg(pi, 0x43b, save_AfeCtrlOvr | 0x1);
+
+ write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal & 0xfffe);
+ write_phy_reg(pi, 0x43b, save_AfeCtrlOvr & 0xfffe);
+
+ write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal);
+ write_phy_reg(pi, 0x43b, save_AfeCtrlOvr);
+}
+
+static void wlc_lcnphy_txrx_spur_avoidance_mode(phy_info_t *pi, bool enable)
+{
+ if (enable) {
+ write_phy_reg(pi, 0x942, 0x7);
+ write_phy_reg(pi, 0x93b, ((1 << 13) + 23));
+ write_phy_reg(pi, 0x93c, ((1 << 13) + 1989));
+
+ write_phy_reg(pi, 0x44a, 0x084);
+ write_phy_reg(pi, 0x44a, 0x080);
+ write_phy_reg(pi, 0x6d3, 0x2222);
+ write_phy_reg(pi, 0x6d3, 0x2220);
+ } else {
+ write_phy_reg(pi, 0x942, 0x0);
+ write_phy_reg(pi, 0x93b, ((0 << 13) + 23));
+ write_phy_reg(pi, 0x93c, ((0 << 13) + 1989));
+ }
+ wlapi_switch_macfreq(pi->sh->physhim, enable);
+}
+
+void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec)
+{
+ u8 channel = CHSPEC_CHANNEL(chanspec);
+
+ wlc_phy_chanspec_radio_set((wlc_phy_t *) pi, chanspec);
+
+ wlc_lcnphy_set_chanspec_tweaks(pi, pi->radio_chanspec);
+
+ or_phy_reg(pi, 0x44a, 0x44);
+ write_phy_reg(pi, 0x44a, 0x80);
+
+ if (!NORADIO_ENAB(pi->pubpi)) {
+ wlc_lcnphy_radio_2064_channel_tune_4313(pi, channel);
+ udelay(1000);
+ }
+
+ wlc_lcnphy_toggle_afe_pwdn(pi);
+
+ write_phy_reg(pi, 0x657, lcnphy_sfo_cfg[channel - 1].ptcentreTs20);
+ write_phy_reg(pi, 0x658, lcnphy_sfo_cfg[channel - 1].ptcentreFactor);
+
+ if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
+ mod_phy_reg(pi, 0x448, (0x3 << 8), (2) << 8);
+
+ wlc_lcnphy_load_tx_iir_filter(pi, false, 3);
+ } else {
+ mod_phy_reg(pi, 0x448, (0x3 << 8), (1) << 8);
+
+ wlc_lcnphy_load_tx_iir_filter(pi, false, 2);
+ }
+
+ wlc_lcnphy_load_tx_iir_filter(pi, true, 0);
+
+ mod_phy_reg(pi, 0x4eb, (0x7 << 3), (1) << 3);
+
+}
+
+static void wlc_lcnphy_set_dac_gain(phy_info_t *pi, u16 dac_gain)
+{
+ u16 dac_ctrl;
+
+ dac_ctrl = (read_phy_reg(pi, 0x439) >> 0);
+ dac_ctrl = dac_ctrl & 0xc7f;
+ dac_ctrl = dac_ctrl | (dac_gain << 7);
+ mod_phy_reg(pi, 0x439, (0xfff << 0), (dac_ctrl) << 0);
+
+}
+
+static void wlc_lcnphy_set_tx_gain_override(phy_info_t *pi, bool bEnable)
+{
+ u16 bit = bEnable ? 1 : 0;
+
+ mod_phy_reg(pi, 0x4b0, (0x1 << 7), bit << 7);
+
+ mod_phy_reg(pi, 0x4b0, (0x1 << 14), bit << 14);
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 6), bit << 6);
+}
+
+static u16 wlc_lcnphy_get_pa_gain(phy_info_t *pi)
+{
+ u16 pa_gain;
+
+ pa_gain = (read_phy_reg(pi, 0x4fb) &
+ LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK) >>
+ LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT;
+
+ return pa_gain;
+}
+
+static void
+wlc_lcnphy_set_tx_gain(phy_info_t *pi, lcnphy_txgains_t *target_gains)
+{
+ u16 pa_gain = wlc_lcnphy_get_pa_gain(pi);
+
+ mod_phy_reg(pi, 0x4b5,
+ (0xffff << 0),
+ ((target_gains->gm_gain) | (target_gains->pga_gain << 8)) <<
+ 0);
+ mod_phy_reg(pi, 0x4fb,
+ (0x7fff << 0),
+ ((target_gains->pad_gain) | (pa_gain << 8)) << 0);
+
+ mod_phy_reg(pi, 0x4fc,
+ (0xffff << 0),
+ ((target_gains->gm_gain) | (target_gains->pga_gain << 8)) <<
+ 0);
+ mod_phy_reg(pi, 0x4fd,
+ (0x7fff << 0),
+ ((target_gains->pad_gain) | (pa_gain << 8)) << 0);
+
+ wlc_lcnphy_set_dac_gain(pi, target_gains->dac_gain);
+
+ wlc_lcnphy_enable_tx_gain_override(pi);
+}
+
+static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0)
+{
+ u16 m0m1 = (u16) m0 << 8;
+ phytbl_info_t tab;
+
+ tab.tbl_ptr = &m0m1;
+ tab.tbl_len = 1;
+ tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
+ tab.tbl_offset = 87;
+ tab.tbl_width = 16;
+ wlc_lcnphy_write_table(pi, &tab);
+}
+
+static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi)
+{
+ u32 data_buf[64];
+ phytbl_info_t tab;
+
+ memset(data_buf, 0, sizeof(data_buf));
+
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_ptr = data_buf;
+
+ if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
+
+ tab.tbl_len = 30;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
+ wlc_lcnphy_write_table(pi, &tab);
+ }
+
+ tab.tbl_len = 64;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_MAC_OFFSET;
+ wlc_lcnphy_write_table(pi, &tab);
+}
+
+typedef enum {
+ LCNPHY_TSSI_PRE_PA,
+ LCNPHY_TSSI_POST_PA,
+ LCNPHY_TSSI_EXT
+} lcnphy_tssi_mode_t;
+
+static void wlc_lcnphy_set_tssi_mux(phy_info_t *pi, lcnphy_tssi_mode_t pos)
+{
+ mod_phy_reg(pi, 0x4d7, (0x1 << 0), (0x1) << 0);
+
+ mod_phy_reg(pi, 0x4d7, (0x1 << 6), (1) << 6);
+
+ if (LCNPHY_TSSI_POST_PA == pos) {
+ mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0) << 2);
+
+ mod_phy_reg(pi, 0x4d9, (0x1 << 3), (1) << 3);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+ mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
+ } else {
+ mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1);
+ mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
+ }
+ } else {
+ mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2);
+
+ mod_phy_reg(pi, 0x4d9, (0x1 << 3), (0) << 3);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+ mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
+ } else {
+ mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0);
+ mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
+ }
+ }
+ mod_phy_reg(pi, 0x637, (0x3 << 14), (0) << 14);
+
+ if (LCNPHY_TSSI_EXT == pos) {
+ write_radio_reg(pi, RADIO_2064_REG07F, 1);
+ mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 0x2);
+ mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 0x1 << 7);
+ mod_radio_reg(pi, RADIO_2064_REG028, 0x1f, 0x3);
+ }
+}
+
+static u16 wlc_lcnphy_rfseq_tbl_adc_pwrup(phy_info_t *pi)
+{
+ u16 N1, N2, N3, N4, N5, N6, N;
+ N1 = ((read_phy_reg(pi, 0x4a5) & (0xff << 0))
+ >> 0);
+ N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12))
+ >> 12);
+ N3 = ((read_phy_reg(pi, 0x40d) & (0xff << 0))
+ >> 0);
+ N4 = 1 << ((read_phy_reg(pi, 0x40d) & (0x7 << 8))
+ >> 8);
+ N5 = ((read_phy_reg(pi, 0x4a2) & (0xff << 0))
+ >> 0);
+ N6 = 1 << ((read_phy_reg(pi, 0x4a2) & (0x7 << 8))
+ >> 8);
+ N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80;
+ if (N < 1600)
+ N = 1600;
+ return N;
+}
+
+static void wlc_lcnphy_pwrctrl_rssiparams(phy_info_t *pi)
+{
+ u16 auxpga_vmid, auxpga_vmid_temp, auxpga_gain_temp;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ auxpga_vmid =
+ (2 << 8) | (pi_lcn->lcnphy_rssi_vc << 4) | pi_lcn->lcnphy_rssi_vf;
+ auxpga_vmid_temp = (2 << 8) | (8 << 4) | 4;
+ auxpga_gain_temp = 2;
+
+ mod_phy_reg(pi, 0x4d8, (0x1 << 0), (0) << 0);
+
+ mod_phy_reg(pi, 0x4d8, (0x1 << 1), (0) << 1);
+
+ mod_phy_reg(pi, 0x4d7, (0x1 << 3), (0) << 3);
+
+ mod_phy_reg(pi, 0x4db,
+ (0x3ff << 0) |
+ (0x7 << 12),
+ (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
+
+ mod_phy_reg(pi, 0x4dc,
+ (0x3ff << 0) |
+ (0x7 << 12),
+ (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
+
+ mod_phy_reg(pi, 0x40a,
+ (0x3ff << 0) |
+ (0x7 << 12),
+ (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
+
+ mod_phy_reg(pi, 0x40b,
+ (0x3ff << 0) |
+ (0x7 << 12),
+ (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
+
+ mod_phy_reg(pi, 0x40c,
+ (0x3ff << 0) |
+ (0x7 << 12),
+ (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
+
+ mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5));
+}
+
+static void wlc_lcnphy_tssi_setup(phy_info_t *pi)
+{
+ phytbl_info_t tab;
+ u32 rfseq, ind;
+
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_ptr = &ind;
+ tab.tbl_len = 1;
+ tab.tbl_offset = 0;
+ for (ind = 0; ind < 128; ind++) {
+ wlc_lcnphy_write_table(pi, &tab);
+ tab.tbl_offset++;
+ }
+ tab.tbl_offset = 704;
+ for (ind = 0; ind < 128; ind++) {
+ wlc_lcnphy_write_table(pi, &tab);
+ tab.tbl_offset++;
+ }
+ mod_phy_reg(pi, 0x503, (0x1 << 0), (0) << 0);
+
+ mod_phy_reg(pi, 0x503, (0x1 << 2), (0) << 2);
+
+ mod_phy_reg(pi, 0x503, (0x1 << 4), (1) << 4);
+
+ wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
+ mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 15), (1) << 15);
+
+ mod_phy_reg(pi, 0x4d0, (0x1 << 5), (0) << 5);
+
+ mod_phy_reg(pi, 0x4a4, (0x1ff << 0), (0) << 0);
+
+ mod_phy_reg(pi, 0x4a5, (0xff << 0), (255) << 0);
+
+ mod_phy_reg(pi, 0x4a5, (0x7 << 12), (5) << 12);
+
+ mod_phy_reg(pi, 0x4a5, (0x7 << 8), (0) << 8);
+
+ mod_phy_reg(pi, 0x40d, (0xff << 0), (64) << 0);
+
+ mod_phy_reg(pi, 0x40d, (0x7 << 8), (4) << 8);
+
+ mod_phy_reg(pi, 0x4a2, (0xff << 0), (64) << 0);
+
+ mod_phy_reg(pi, 0x4a2, (0x7 << 8), (4) << 8);
+
+ mod_phy_reg(pi, 0x4d0, (0x1ff << 6), (0) << 6);
+
+ mod_phy_reg(pi, 0x4a8, (0xff << 0), (0x1) << 0);
+
+ wlc_lcnphy_clear_tx_power_offsets(pi);
+
+ mod_phy_reg(pi, 0x4a6, (0x1 << 15), (1) << 15);
+
+ mod_phy_reg(pi, 0x4a6, (0x1ff << 0), (0xff) << 0);
+
+ mod_phy_reg(pi, 0x49a, (0x1ff << 0), (0xff) << 0);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+ mod_radio_reg(pi, RADIO_2064_REG028, 0xf, 0xe);
+ mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
+ } else {
+ mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
+ mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 1 << 3);
+ }
+
+ write_radio_reg(pi, RADIO_2064_REG025, 0xc);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+ mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
+ } else {
+ if (CHSPEC_IS2G(pi->radio_chanspec))
+ mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 1 << 1);
+ else
+ mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 0 << 1);
+ }
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2))
+ mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 1 << 1);
+ else
+ mod_radio_reg(pi, RADIO_2064_REG03A, 0x4, 1 << 2);
+
+ mod_radio_reg(pi, RADIO_2064_REG11A, 0x1, 1 << 0);
+
+ mod_radio_reg(pi, RADIO_2064_REG005, 0x8, 1 << 3);
+
+ if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
+ mod_phy_reg(pi, 0x4d7,
+ (0x1 << 3) | (0x7 << 12), 0 << 3 | 2 << 12);
+ }
+
+ rfseq = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi);
+ tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
+ tab.tbl_width = 16;
+ tab.tbl_ptr = &rfseq;
+ tab.tbl_len = 1;
+ tab.tbl_offset = 6;
+ wlc_lcnphy_write_table(pi, &tab);
+
+ mod_phy_reg(pi, 0x938, (0x1 << 2), (1) << 2);
+
+ mod_phy_reg(pi, 0x939, (0x1 << 2), (1) << 2);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
+
+ mod_phy_reg(pi, 0x4d7, (0x1 << 2), (1) << 2);
+
+ mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8);
+
+ wlc_lcnphy_pwrctrl_rssiparams(pi);
+}
+
+void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi)
+{
+ u16 tx_cnt, tx_total, npt;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ tx_total = wlc_lcnphy_total_tx_frames(pi);
+ tx_cnt = tx_total - pi_lcn->lcnphy_tssi_tx_cnt;
+ npt = wlc_lcnphy_get_tx_pwr_npt(pi);
+
+ if (tx_cnt > (1 << npt)) {
+
+ pi_lcn->lcnphy_tssi_tx_cnt = tx_total;
+
+ pi_lcn->lcnphy_tssi_idx = wlc_lcnphy_get_current_tx_pwr_idx(pi);
+ pi_lcn->lcnphy_tssi_npt = npt;
+
+ }
+}
+
+s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1)
+{
+ s32 a, b, p;
+
+ a = 32768 + (a1 * tssi);
+ b = (1024 * b0) + (64 * b1 * tssi);
+ p = ((2 * b) + a) / (2 * a);
+
+ return p;
+}
+
+static void wlc_lcnphy_txpower_reset_npt(phy_info_t *pi)
+{
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+ if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
+ return;
+
+ pi_lcn->lcnphy_tssi_idx = LCNPHY_TX_PWR_CTRL_START_INDEX_2G_4313;
+ pi_lcn->lcnphy_tssi_npt = LCNPHY_TX_PWR_CTRL_START_NPT;
+}
+
+void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi)
+{
+ phytbl_info_t tab;
+ u32 rate_table[WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM +
+ WLC_NUM_RATES_MCS_1_STREAM];
+ uint i, j;
+ if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
+ return;
+
+ for (i = 0, j = 0; i < ARRAY_SIZE(rate_table); i++, j++) {
+
+ if (i == WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM)
+ j = TXP_FIRST_MCS_20_SISO;
+
+ rate_table[i] = (u32) ((s32) (-pi->tx_power_offset[j]));
+ }
+
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_len = ARRAY_SIZE(rate_table);
+ tab.tbl_ptr = rate_table;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
+ wlc_lcnphy_write_table(pi, &tab);
+
+ if (wlc_lcnphy_get_target_tx_pwr(pi) != pi->tx_power_min) {
+ wlc_lcnphy_set_target_tx_pwr(pi, pi->tx_power_min);
+
+ wlc_lcnphy_txpower_reset_npt(pi);
+ }
+}
+
+static void wlc_lcnphy_set_tx_pwr_soft_ctrl(phy_info_t *pi, s8 index)
+{
+ u32 cck_offset[4] = { 22, 22, 22, 22 };
+ u32 ofdm_offset, reg_offset_cck;
+ int i;
+ u16 index2;
+ phytbl_info_t tab;
+
+ if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
+ return;
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x1) << 14);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x0) << 14);
+
+ or_phy_reg(pi, 0x6da, 0x0040);
+
+ reg_offset_cck = 0;
+ for (i = 0; i < 4; i++)
+ cck_offset[i] -= reg_offset_cck;
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_len = 4;
+ tab.tbl_ptr = cck_offset;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
+ wlc_lcnphy_write_table(pi, &tab);
+ ofdm_offset = 0;
+ tab.tbl_len = 1;
+ tab.tbl_ptr = &ofdm_offset;
+ for (i = 836; i < 862; i++) {
+ tab.tbl_offset = i;
+ wlc_lcnphy_write_table(pi, &tab);
+ }
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 15), (0x1) << 15);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x1) << 14);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 13), (0x1) << 13);
+
+ mod_phy_reg(pi, 0x4b0, (0x1 << 7), (0) << 7);
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 6), (0) << 6);
+
+ mod_phy_reg(pi, 0x4a9, (0x1 << 15), (1) << 15);
+
+ index2 = (u16) (index * 2);
+ mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0);
+
+ mod_phy_reg(pi, 0x6a3, (0x1 << 4), (0) << 4);
+
+}
+
+static s8 wlc_lcnphy_tempcompensated_txpwrctrl(phy_info_t *pi)
+{
+ s8 index, delta_brd, delta_temp, new_index, tempcorrx;
+ s16 manp, meas_temp, temp_diff;
+ bool neg = 0;
+ u16 temp;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
+ return pi_lcn->lcnphy_current_index;
+
+ index = FIXED_TXPWR;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return index;
+
+ if (pi_lcn->lcnphy_tempsense_slope == 0) {
+ return index;
+ }
+ temp = (u16) wlc_lcnphy_tempsense(pi, 0);
+ meas_temp = LCNPHY_TEMPSENSE(temp);
+
+ if (pi->tx_power_min != 0) {
+ delta_brd = (pi_lcn->lcnphy_measPower - pi->tx_power_min);
+ } else {
+ delta_brd = 0;
+ }
+
+ manp = LCNPHY_TEMPSENSE(pi_lcn->lcnphy_rawtempsense);
+ temp_diff = manp - meas_temp;
+ if (temp_diff < 0) {
+
+ neg = 1;
+
+ temp_diff = -temp_diff;
+ }
+
+ delta_temp = (s8) wlc_lcnphy_qdiv_roundup((u32) (temp_diff * 192),
+ (u32) (pi_lcn->
+ lcnphy_tempsense_slope
+ * 10), 0);
+ if (neg)
+ delta_temp = -delta_temp;
+
+ if (pi_lcn->lcnphy_tempsense_option == 3
+ && LCNREV_IS(pi->pubpi.phy_rev, 0))
+ delta_temp = 0;
+ if (pi_lcn->lcnphy_tempcorrx > 31)
+ tempcorrx = (s8) (pi_lcn->lcnphy_tempcorrx - 64);
+ else
+ tempcorrx = (s8) pi_lcn->lcnphy_tempcorrx;
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1))
+ tempcorrx = 4;
+ new_index =
+ index + delta_brd + delta_temp - pi_lcn->lcnphy_bandedge_corr;
+ new_index += tempcorrx;
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1))
+ index = 127;
+ if (new_index < 0 || new_index > 126) {
+ return index;
+ }
+ return new_index;
+}
+
+static u16 wlc_lcnphy_set_tx_pwr_ctrl_mode(phy_info_t *pi, u16 mode)
+{
+
+ u16 current_mode = mode;
+ if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) &&
+ mode == LCNPHY_TX_PWR_CTRL_HW)
+ current_mode = LCNPHY_TX_PWR_CTRL_TEMPBASED;
+ if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) &&
+ mode == LCNPHY_TX_PWR_CTRL_TEMPBASED)
+ current_mode = LCNPHY_TX_PWR_CTRL_HW;
+ return current_mode;
+}
+
+void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode)
+{
+ u16 old_mode = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ s8 index;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, mode);
+ old_mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, old_mode);
+
+ mod_phy_reg(pi, 0x6da, (0x1 << 6),
+ ((LCNPHY_TX_PWR_CTRL_HW == mode) ? 1 : 0) << 6);
+
+ mod_phy_reg(pi, 0x6a3, (0x1 << 4),
+ ((LCNPHY_TX_PWR_CTRL_HW == mode) ? 0 : 1) << 4);
+
+ if (old_mode != mode) {
+ if (LCNPHY_TX_PWR_CTRL_HW == old_mode) {
+
+ wlc_lcnphy_tx_pwr_update_npt(pi);
+
+ wlc_lcnphy_clear_tx_power_offsets(pi);
+ }
+ if (LCNPHY_TX_PWR_CTRL_HW == mode) {
+
+ wlc_lcnphy_txpower_recalc_target(pi);
+
+ wlc_lcnphy_set_start_tx_pwr_idx(pi,
+ pi_lcn->
+ lcnphy_tssi_idx);
+ wlc_lcnphy_set_tx_pwr_npt(pi, pi_lcn->lcnphy_tssi_npt);
+ mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 0);
+
+ pi_lcn->lcnphy_tssi_tx_cnt =
+ wlc_lcnphy_total_tx_frames(pi);
+
+ wlc_lcnphy_disable_tx_gain_override(pi);
+ pi_lcn->lcnphy_tx_power_idx_override = -1;
+ } else
+ wlc_lcnphy_enable_tx_gain_override(pi);
+
+ mod_phy_reg(pi, 0x4a4,
+ ((0x1 << 15) | (0x1 << 14) | (0x1 << 13)), mode);
+ if (mode == LCNPHY_TX_PWR_CTRL_TEMPBASED) {
+ index = wlc_lcnphy_tempcompensated_txpwrctrl(pi);
+ wlc_lcnphy_set_tx_pwr_soft_ctrl(pi, index);
+ pi_lcn->lcnphy_current_index = (s8)
+ ((read_phy_reg(pi, 0x4a9) & 0xFF) / 2);
+ }
+ }
+}
+
+static bool wlc_lcnphy_iqcal_wait(phy_info_t *pi)
+{
+ uint delay_count = 0;
+
+ while (wlc_lcnphy_iqcal_active(pi)) {
+ udelay(100);
+ delay_count++;
+
+ if (delay_count > (10 * 500))
+ break;
+ }
+
+ return (0 == wlc_lcnphy_iqcal_active(pi));
+}
+
+static void
+wlc_lcnphy_tx_iqlo_cal(phy_info_t *pi,
+ lcnphy_txgains_t *target_gains,
+ lcnphy_cal_mode_t cal_mode, bool keep_tone)
+{
+
+ lcnphy_txgains_t cal_gains, temp_gains;
+ u16 hash;
+ u8 band_idx;
+ int j;
+ u16 ncorr_override[5];
+ u16 syst_coeffs[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
+ };
+
+ u16 commands_fullcal[] = {
+ 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 };
+
+ u16 commands_recal[] = {
+ 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 };
+
+ u16 command_nums_fullcal[] = {
+ 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 };
+
+ u16 command_nums_recal[] = {
+ 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 };
+ u16 *command_nums = command_nums_fullcal;
+
+ u16 *start_coeffs = NULL, *cal_cmds = NULL, cal_type, diq_start;
+ u16 tx_pwr_ctrl_old, save_txpwrctrlrfctrl2;
+ u16 save_sslpnCalibClkEnCtrl, save_sslpnRxFeClkEnCtrl;
+ bool tx_gain_override_old;
+ lcnphy_txgains_t old_gains;
+ uint i, n_cal_cmds = 0, n_cal_start = 0;
+ u16 *values_to_save;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ values_to_save = kmalloc(sizeof(u16) * 20, GFP_ATOMIC);
+ if (NULL == values_to_save) {
+ return;
+ }
+
+ save_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
+ save_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
+
+ or_phy_reg(pi, 0x6da, 0x40);
+ or_phy_reg(pi, 0x6db, 0x3);
+
+ switch (cal_mode) {
+ case LCNPHY_CAL_FULL:
+ start_coeffs = syst_coeffs;
+ cal_cmds = commands_fullcal;
+ n_cal_cmds = ARRAY_SIZE(commands_fullcal);
+ break;
+
+ case LCNPHY_CAL_RECAL:
+ start_coeffs = syst_coeffs;
+ cal_cmds = commands_recal;
+ n_cal_cmds = ARRAY_SIZE(commands_recal);
+ command_nums = command_nums_recal;
+ break;
+
+ default:
+ break;
+ }
+
+ wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ start_coeffs, 11, 16, 64);
+
+ write_phy_reg(pi, 0x6da, 0xffff);
+ mod_phy_reg(pi, 0x503, (0x1 << 3), (1) << 3);
+
+ tx_pwr_ctrl_old = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
+
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
+
+ save_txpwrctrlrfctrl2 = read_phy_reg(pi, 0x4db);
+
+ mod_phy_reg(pi, 0x4db, (0x3ff << 0), (0x2a6) << 0);
+
+ mod_phy_reg(pi, 0x4db, (0x7 << 12), (2) << 12);
+
+ wlc_lcnphy_tx_iqlo_loopback(pi, values_to_save);
+
+ tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
+ if (tx_gain_override_old)
+ wlc_lcnphy_get_tx_gain(pi, &old_gains);
+
+ if (!target_gains) {
+ if (!tx_gain_override_old)
+ wlc_lcnphy_set_tx_pwr_by_index(pi,
+ pi_lcn->lcnphy_tssi_idx);
+ wlc_lcnphy_get_tx_gain(pi, &temp_gains);
+ target_gains = &temp_gains;
+ }
+
+ hash = (target_gains->gm_gain << 8) |
+ (target_gains->pga_gain << 4) | (target_gains->pad_gain);
+
+ band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0);
+
+ cal_gains = *target_gains;
+ memset(ncorr_override, 0, sizeof(ncorr_override));
+ for (j = 0; j < iqcal_gainparams_numgains_lcnphy[band_idx]; j++) {
+ if (hash == tbl_iqcal_gainparams_lcnphy[band_idx][j][0]) {
+ cal_gains.gm_gain =
+ tbl_iqcal_gainparams_lcnphy[band_idx][j][1];
+ cal_gains.pga_gain =
+ tbl_iqcal_gainparams_lcnphy[band_idx][j][2];
+ cal_gains.pad_gain =
+ tbl_iqcal_gainparams_lcnphy[band_idx][j][3];
+ memcpy(ncorr_override,
+ &tbl_iqcal_gainparams_lcnphy[band_idx][j][3],
+ sizeof(ncorr_override));
+ break;
+ }
+ }
+
+ wlc_lcnphy_set_tx_gain(pi, &cal_gains);
+
+ write_phy_reg(pi, 0x453, 0xaa9);
+ write_phy_reg(pi, 0x93d, 0xc0);
+
+ wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ (const void *)
+ lcnphy_iqcal_loft_gainladder,
+ ARRAY_SIZE(lcnphy_iqcal_loft_gainladder),
+ 16, 0);
+
+ wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ (const void *)lcnphy_iqcal_ir_gainladder,
+ ARRAY_SIZE(lcnphy_iqcal_ir_gainladder), 16,
+ 32);
+
+ if (pi->phy_tx_tone_freq) {
+
+ wlc_lcnphy_stop_tx_tone(pi);
+ udelay(5);
+ wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
+ } else {
+ wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
+ }
+
+ write_phy_reg(pi, 0x6da, 0xffff);
+
+ for (i = n_cal_start; i < n_cal_cmds; i++) {
+ u16 zero_diq = 0;
+ u16 best_coeffs[11];
+ u16 command_num;
+
+ cal_type = (cal_cmds[i] & 0x0f00) >> 8;
+
+ command_num = command_nums[i];
+ if (ncorr_override[cal_type])
+ command_num =
+ ncorr_override[cal_type] << 8 | (command_num &
+ 0xff);
+
+ write_phy_reg(pi, 0x452, command_num);
+
+ if ((cal_type == 3) || (cal_type == 4)) {
+
+ wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ &diq_start, 1, 16, 69);
+
+ wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ &zero_diq, 1, 16, 69);
+ }
+
+ write_phy_reg(pi, 0x451, cal_cmds[i]);
+
+ if (!wlc_lcnphy_iqcal_wait(pi)) {
+
+ goto cleanup;
+ }
+
+ wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ best_coeffs,
+ ARRAY_SIZE(best_coeffs), 16, 96);
+ wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ best_coeffs,
+ ARRAY_SIZE(best_coeffs), 16, 64);
+
+ if ((cal_type == 3) || (cal_type == 4)) {
+ wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ &diq_start, 1, 16, 69);
+ }
+ wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ pi_lcn->lcnphy_cal_results.
+ txiqlocal_bestcoeffs,
+ ARRAY_SIZE(pi_lcn->
+ lcnphy_cal_results.
+ txiqlocal_bestcoeffs),
+ 16, 96);
+ }
+
+ wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ pi_lcn->lcnphy_cal_results.
+ txiqlocal_bestcoeffs,
+ ARRAY_SIZE(pi_lcn->lcnphy_cal_results.
+ txiqlocal_bestcoeffs), 16, 96);
+ pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs_valid = true;
+
+ wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ &pi_lcn->lcnphy_cal_results.
+ txiqlocal_bestcoeffs[0], 4, 16, 80);
+
+ wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
+ &pi_lcn->lcnphy_cal_results.
+ txiqlocal_bestcoeffs[5], 2, 16, 85);
+
+ cleanup:
+ wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, values_to_save);
+ kfree(values_to_save);
+
+ if (!keep_tone)
+ wlc_lcnphy_stop_tx_tone(pi);
+
+ write_phy_reg(pi, 0x4db, save_txpwrctrlrfctrl2);
+
+ write_phy_reg(pi, 0x453, 0);
+
+ if (tx_gain_override_old)
+ wlc_lcnphy_set_tx_gain(pi, &old_gains);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl_old);
+
+ write_phy_reg(pi, 0x6da, save_sslpnCalibClkEnCtrl);
+ write_phy_reg(pi, 0x6db, save_sslpnRxFeClkEnCtrl);
+
+}
+
+static void wlc_lcnphy_idle_tssi_est(wlc_phy_t *ppi)
+{
+ bool suspend, tx_gain_override_old;
+ lcnphy_txgains_t old_gains;
+ phy_info_t *pi = (phy_info_t *) ppi;
+ u16 idleTssi, idleTssi0_2C, idleTssi0_OB, idleTssi0_regvalue_OB,
+ idleTssi0_regvalue_2C;
+ u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ u16 SAVE_lpfgain = read_radio_reg(pi, RADIO_2064_REG112);
+ u16 SAVE_jtag_bb_afe_switch =
+ read_radio_reg(pi, RADIO_2064_REG007) & 1;
+ u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10;
+ u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4;
+ idleTssi = read_phy_reg(pi, 0x4ab);
+ suspend =
+ (0 ==
+ (R_REG(&((phy_info_t *) pi)->regs->maccontrol) &
+ MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
+
+ tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
+ wlc_lcnphy_get_tx_gain(pi, &old_gains);
+
+ wlc_lcnphy_enable_tx_gain_override(pi);
+ wlc_lcnphy_set_tx_pwr_by_index(pi, 127);
+ write_radio_reg(pi, RADIO_2064_REG112, 0x6);
+ mod_radio_reg(pi, RADIO_2064_REG007, 0x1, 1);
+ mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 1 << 4);
+ mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 1 << 2);
+ wlc_lcnphy_tssi_setup(pi);
+ wlc_phy_do_dummy_tx(pi, true, OFF);
+ idleTssi = ((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
+ >> 0);
+
+ idleTssi0_2C = ((read_phy_reg(pi, 0x63e) & (0x1ff << 0))
+ >> 0);
+
+ if (idleTssi0_2C >= 256)
+ idleTssi0_OB = idleTssi0_2C - 256;
+ else
+ idleTssi0_OB = idleTssi0_2C + 256;
+
+ idleTssi0_regvalue_OB = idleTssi0_OB;
+ if (idleTssi0_regvalue_OB >= 256)
+ idleTssi0_regvalue_2C = idleTssi0_regvalue_OB - 256;
+ else
+ idleTssi0_regvalue_2C = idleTssi0_regvalue_OB + 256;
+ mod_phy_reg(pi, 0x4a6, (0x1ff << 0), (idleTssi0_regvalue_2C) << 0);
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 12), (0) << 12);
+
+ wlc_lcnphy_set_tx_gain_override(pi, tx_gain_override_old);
+ wlc_lcnphy_set_tx_gain(pi, &old_gains);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
+
+ write_radio_reg(pi, RADIO_2064_REG112, SAVE_lpfgain);
+ mod_radio_reg(pi, RADIO_2064_REG007, 0x1, SAVE_jtag_bb_afe_switch);
+ mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, SAVE_jtag_auxpga);
+ mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, SAVE_iqadc_aux_en);
+ mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1 << 7);
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+}
+
+static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
+{
+ bool suspend;
+ u16 save_txpwrCtrlEn;
+ u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain;
+ u16 auxpga_vmid;
+ phytbl_info_t tab;
+ u32 val;
+ u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025,
+ save_reg112;
+ u16 values_to_save[14];
+ s8 index;
+ int i;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+ udelay(999);
+
+ save_reg007 = (u8) read_radio_reg(pi, RADIO_2064_REG007);
+ save_reg0FF = (u8) read_radio_reg(pi, RADIO_2064_REG0FF);
+ save_reg11F = (u8) read_radio_reg(pi, RADIO_2064_REG11F);
+ save_reg005 = (u8) read_radio_reg(pi, RADIO_2064_REG005);
+ save_reg025 = (u8) read_radio_reg(pi, RADIO_2064_REG025);
+ save_reg112 = (u8) read_radio_reg(pi, RADIO_2064_REG112);
+
+ for (i = 0; i < 14; i++)
+ values_to_save[i] = read_phy_reg(pi, tempsense_phy_regs[i]);
+ suspend =
+ (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ save_txpwrCtrlEn = read_radio_reg(pi, 0x4a4);
+
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
+ index = pi_lcn->lcnphy_current_index;
+ wlc_lcnphy_set_tx_pwr_by_index(pi, 127);
+ mod_radio_reg(pi, RADIO_2064_REG007, 0x1, 0x1);
+ mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 0x1 << 4);
+ mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 0x1 << 2);
+ mod_phy_reg(pi, 0x503, (0x1 << 0), (0) << 0);
+
+ mod_phy_reg(pi, 0x503, (0x1 << 2), (0) << 2);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 15), (0) << 15);
+
+ mod_phy_reg(pi, 0x4d0, (0x1 << 5), (0) << 5);
+
+ mod_phy_reg(pi, 0x4a5, (0xff << 0), (255) << 0);
+
+ mod_phy_reg(pi, 0x4a5, (0x7 << 12), (5) << 12);
+
+ mod_phy_reg(pi, 0x4a5, (0x7 << 8), (0) << 8);
+
+ mod_phy_reg(pi, 0x40d, (0xff << 0), (64) << 0);
+
+ mod_phy_reg(pi, 0x40d, (0x7 << 8), (6) << 8);
+
+ mod_phy_reg(pi, 0x4a2, (0xff << 0), (64) << 0);
+
+ mod_phy_reg(pi, 0x4a2, (0x7 << 8), (6) << 8);
+
+ mod_phy_reg(pi, 0x4d9, (0x7 << 4), (2) << 4);
+
+ mod_phy_reg(pi, 0x4d9, (0x7 << 8), (3) << 8);
+
+ mod_phy_reg(pi, 0x4d9, (0x7 << 12), (1) << 12);
+
+ mod_phy_reg(pi, 0x4da, (0x1 << 12), (0) << 12);
+
+ mod_phy_reg(pi, 0x4da, (0x1 << 13), (1) << 13);
+
+ mod_phy_reg(pi, 0x4a6, (0x1 << 15), (1) << 15);
+
+ write_radio_reg(pi, RADIO_2064_REG025, 0xC);
+
+ mod_radio_reg(pi, RADIO_2064_REG005, 0x8, 0x1 << 3);
+
+ mod_phy_reg(pi, 0x938, (0x1 << 2), (1) << 2);
+
+ mod_phy_reg(pi, 0x939, (0x1 << 2), (1) << 2);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
+
+ val = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi);
+ tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
+ tab.tbl_width = 16;
+ tab.tbl_len = 1;
+ tab.tbl_ptr = &val;
+ tab.tbl_offset = 6;
+ wlc_lcnphy_write_table(pi, &tab);
+ if (mode == TEMPSENSE) {
+ mod_phy_reg(pi, 0x4d7, (0x1 << 3), (1) << 3);
+
+ mod_phy_reg(pi, 0x4d7, (0x7 << 12), (1) << 12);
+
+ auxpga_vmidcourse = 8;
+ auxpga_vmidfine = 0x4;
+ auxpga_gain = 2;
+ mod_radio_reg(pi, RADIO_2064_REG082, 0x20, 1 << 5);
+ } else {
+ mod_phy_reg(pi, 0x4d7, (0x1 << 3), (1) << 3);
+
+ mod_phy_reg(pi, 0x4d7, (0x7 << 12), (3) << 12);
+
+ auxpga_vmidcourse = 7;
+ auxpga_vmidfine = 0xa;
+ auxpga_gain = 2;
+ }
+ auxpga_vmid =
+ (u16) ((2 << 8) | (auxpga_vmidcourse << 4) | auxpga_vmidfine);
+ mod_phy_reg(pi, 0x4d8, (0x1 << 0), (1) << 0);
+
+ mod_phy_reg(pi, 0x4d8, (0x3ff << 2), (auxpga_vmid) << 2);
+
+ mod_phy_reg(pi, 0x4d8, (0x1 << 1), (1) << 1);
+
+ mod_phy_reg(pi, 0x4d8, (0x7 << 12), (auxpga_gain) << 12);
+
+ mod_phy_reg(pi, 0x4d0, (0x1 << 5), (1) << 5);
+
+ write_radio_reg(pi, RADIO_2064_REG112, 0x6);
+
+ wlc_phy_do_dummy_tx(pi, true, OFF);
+ if (!tempsense_done(pi))
+ udelay(10);
+
+ write_radio_reg(pi, RADIO_2064_REG007, (u16) save_reg007);
+ write_radio_reg(pi, RADIO_2064_REG0FF, (u16) save_reg0FF);
+ write_radio_reg(pi, RADIO_2064_REG11F, (u16) save_reg11F);
+ write_radio_reg(pi, RADIO_2064_REG005, (u16) save_reg005);
+ write_radio_reg(pi, RADIO_2064_REG025, (u16) save_reg025);
+ write_radio_reg(pi, RADIO_2064_REG112, (u16) save_reg112);
+ for (i = 0; i < 14; i++)
+ write_phy_reg(pi, tempsense_phy_regs[i], values_to_save[i]);
+ wlc_lcnphy_set_tx_pwr_by_index(pi, (int)index);
+
+ write_radio_reg(pi, 0x4a4, save_txpwrCtrlEn);
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+ udelay(999);
+}
+
+void WLBANDINITFN(wlc_lcnphy_tx_pwr_ctrl_init) (wlc_phy_t *ppi)
+{
+ lcnphy_txgains_t tx_gains;
+ u8 bbmult;
+ phytbl_info_t tab;
+ s32 a1, b0, b1;
+ s32 tssi, pwr, maxtargetpwr, mintargetpwr;
+ bool suspend;
+ phy_info_t *pi = (phy_info_t *) ppi;
+
+ suspend =
+ (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ if (NORADIO_ENAB(pi->pubpi)) {
+ wlc_lcnphy_set_bbmult(pi, 0x30);
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+ return;
+ }
+
+ if (!pi->hwpwrctrl_capable) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ tx_gains.gm_gain = 4;
+ tx_gains.pga_gain = 12;
+ tx_gains.pad_gain = 12;
+ tx_gains.dac_gain = 0;
+
+ bbmult = 150;
+ } else {
+ tx_gains.gm_gain = 7;
+ tx_gains.pga_gain = 15;
+ tx_gains.pad_gain = 14;
+ tx_gains.dac_gain = 0;
+
+ bbmult = 150;
+ }
+ wlc_lcnphy_set_tx_gain(pi, &tx_gains);
+ wlc_lcnphy_set_bbmult(pi, bbmult);
+ wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
+ } else {
+
+ wlc_lcnphy_idle_tssi_est(ppi);
+
+ wlc_lcnphy_clear_tx_power_offsets(pi);
+
+ b0 = pi->txpa_2g[0];
+ b1 = pi->txpa_2g[1];
+ a1 = pi->txpa_2g[2];
+ maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1);
+ mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1);
+
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_ptr = &pwr;
+ tab.tbl_len = 1;
+ tab.tbl_offset = 0;
+ for (tssi = 0; tssi < 128; tssi++) {
+ pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1);
+
+ pwr = (pwr < mintargetpwr) ? mintargetpwr : pwr;
+ wlc_lcnphy_write_table(pi, &tab);
+ tab.tbl_offset++;
+ }
+
+ mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7);
+
+ write_phy_reg(pi, 0x4a8, 10);
+
+ wlc_lcnphy_set_target_tx_pwr(pi, LCN_TARGET_PWR);
+
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
+ }
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+}
+
+static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi)
+{
+ u16 m0m1;
+ phytbl_info_t tab;
+
+ tab.tbl_ptr = &m0m1;
+ tab.tbl_len = 1;
+ tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
+ tab.tbl_offset = 87;
+ tab.tbl_width = 16;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ return (u8) ((m0m1 & 0xff00) >> 8);
+}
+
+static void wlc_lcnphy_set_pa_gain(phy_info_t *pi, u16 gain)
+{
+ mod_phy_reg(pi, 0x4fb,
+ LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK,
+ gain << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT);
+ mod_phy_reg(pi, 0x4fd,
+ LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_MASK,
+ gain << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT);
+}
+
+void
+wlc_lcnphy_get_radio_loft(phy_info_t *pi,
+ u8 *ei0, u8 *eq0, u8 *fi0, u8 *fq0)
+{
+ *ei0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG089));
+ *eq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08A));
+ *fi0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08B));
+ *fq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08C));
+}
+
+static void wlc_lcnphy_get_tx_gain(phy_info_t *pi, lcnphy_txgains_t *gains)
+{
+ u16 dac_gain;
+
+ dac_gain = read_phy_reg(pi, 0x439) >> 0;
+ gains->dac_gain = (dac_gain & 0x380) >> 7;
+
+ {
+ u16 rfgain0, rfgain1;
+
+ rfgain0 = (read_phy_reg(pi, 0x4b5) & (0xffff << 0)) >> 0;
+ rfgain1 = (read_phy_reg(pi, 0x4fb) & (0x7fff << 0)) >> 0;
+
+ gains->gm_gain = rfgain0 & 0xff;
+ gains->pga_gain = (rfgain0 >> 8) & 0xff;
+ gains->pad_gain = rfgain1 & 0xff;
+ }
+}
+
+void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b)
+{
+ phytbl_info_t tab;
+ u16 iqcc[2];
+
+ iqcc[0] = a;
+ iqcc[1] = b;
+
+ tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
+ tab.tbl_width = 16;
+ tab.tbl_ptr = iqcc;
+ tab.tbl_len = 2;
+ tab.tbl_offset = 80;
+ wlc_lcnphy_write_table(pi, &tab);
+}
+
+void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq)
+{
+ phytbl_info_t tab;
+
+ tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
+ tab.tbl_width = 16;
+ tab.tbl_ptr = &didq;
+ tab.tbl_len = 1;
+ tab.tbl_offset = 85;
+ wlc_lcnphy_write_table(pi, &tab);
+}
+
+void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index)
+{
+ phytbl_info_t tab;
+ u16 a, b;
+ u8 bb_mult;
+ u32 bbmultiqcomp, txgain, locoeffs, rfpower;
+ lcnphy_txgains_t gains;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ pi_lcn->lcnphy_tx_power_idx_override = (s8) index;
+ pi_lcn->lcnphy_current_index = (u8) index;
+
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_len = 1;
+
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
+
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + index;
+ tab.tbl_ptr = &bbmultiqcomp;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + index;
+ tab.tbl_width = 32;
+ tab.tbl_ptr = &txgain;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ gains.gm_gain = (u16) (txgain & 0xff);
+ gains.pga_gain = (u16) (txgain >> 8) & 0xff;
+ gains.pad_gain = (u16) (txgain >> 16) & 0xff;
+ gains.dac_gain = (u16) (bbmultiqcomp >> 28) & 0x07;
+ wlc_lcnphy_set_tx_gain(pi, &gains);
+ wlc_lcnphy_set_pa_gain(pi, (u16) (txgain >> 24) & 0x7f);
+
+ bb_mult = (u8) ((bbmultiqcomp >> 20) & 0xff);
+ wlc_lcnphy_set_bbmult(pi, bb_mult);
+
+ wlc_lcnphy_enable_tx_gain_override(pi);
+
+ if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
+
+ a = (u16) ((bbmultiqcomp >> 10) & 0x3ff);
+ b = (u16) (bbmultiqcomp & 0x3ff);
+ wlc_lcnphy_set_tx_iqcc(pi, a, b);
+
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + index;
+ tab.tbl_ptr = &locoeffs;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ wlc_lcnphy_set_tx_locc(pi, (u16) locoeffs);
+
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index;
+ tab.tbl_ptr = &rfpower;
+ wlc_lcnphy_read_table(pi, &tab);
+ mod_phy_reg(pi, 0x6a6, (0x1fff << 0), (rfpower * 8) << 0);
+
+ }
+}
+
+static void wlc_lcnphy_set_trsw_override(phy_info_t *pi, bool tx, bool rx)
+{
+
+ mod_phy_reg(pi, 0x44d,
+ (0x1 << 1) |
+ (0x1 << 0), (tx ? (0x1 << 1) : 0) | (rx ? (0x1 << 0) : 0));
+
+ or_phy_reg(pi, 0x44c, (0x1 << 1) | (0x1 << 0));
+}
+
+static void wlc_lcnphy_clear_papd_comptable(phy_info_t *pi)
+{
+ u32 j;
+ phytbl_info_t tab;
+ u32 temp_offset[128];
+ tab.tbl_ptr = temp_offset;
+ tab.tbl_len = 128;
+ tab.tbl_id = LCNPHY_TBL_ID_PAPDCOMPDELTATBL;
+ tab.tbl_width = 32;
+ tab.tbl_offset = 0;
+
+ memset(temp_offset, 0, sizeof(temp_offset));
+ for (j = 1; j < 128; j += 2)
+ temp_offset[j] = 0x80000;
+
+ wlc_lcnphy_write_table(pi, &tab);
+ return;
+}
+
+static void
+wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi,
+ u16 trsw,
+ u16 ext_lna,
+ u16 biq2,
+ u16 biq1,
+ u16 tia, u16 lna2, u16 lna1)
+{
+ u16 gain0_15, gain16_19;
+
+ gain16_19 = biq2 & 0xf;
+ gain0_15 = ((biq1 & 0xf) << 12) |
+ ((tia & 0xf) << 8) |
+ ((lna2 & 0x3) << 6) |
+ ((lna2 & 0x3) << 4) | ((lna1 & 0x3) << 2) | ((lna1 & 0x3) << 0);
+
+ mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
+ mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
+ mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
+
+ if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
+ mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
+ mod_phy_reg(pi, 0x4b1, (0x1 << 10), ext_lna << 10);
+ } else {
+ mod_phy_reg(pi, 0x4b1, (0x1 << 10), 0 << 10);
+
+ mod_phy_reg(pi, 0x4b1, (0x1 << 15), 0 << 15);
+
+ mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
+ }
+
+ mod_phy_reg(pi, 0x44d, (0x1 << 0), (!trsw) << 0);
+
+}
+
+static void wlc_lcnphy_rx_gain_override_enable(phy_info_t *pi, bool enable)
+{
+ u16 ebit = enable ? 1 : 0;
+
+ mod_phy_reg(pi, 0x4b0, (0x1 << 8), ebit << 8);
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 0), ebit << 0);
+
+ if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
+ mod_phy_reg(pi, 0x44c, (0x1 << 4), ebit << 4);
+ mod_phy_reg(pi, 0x44c, (0x1 << 6), ebit << 6);
+ mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5);
+ mod_phy_reg(pi, 0x4b0, (0x1 << 6), ebit << 6);
+ } else {
+ mod_phy_reg(pi, 0x4b0, (0x1 << 12), ebit << 12);
+ mod_phy_reg(pi, 0x4b0, (0x1 << 13), ebit << 13);
+ mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5);
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ mod_phy_reg(pi, 0x4b0, (0x1 << 10), ebit << 10);
+ mod_phy_reg(pi, 0x4e5, (0x1 << 3), ebit << 3);
+ }
+}
+
+void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable)
+{
+ if (!bEnable) {
+
+ and_phy_reg(pi, 0x43b, ~(u16) ((0x1 << 1) | (0x1 << 4)));
+
+ mod_phy_reg(pi, 0x43c, (0x1 << 1), 1 << 1);
+
+ and_phy_reg(pi, 0x44c,
+ ~(u16) ((0x1 << 3) |
+ (0x1 << 5) |
+ (0x1 << 12) |
+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
+
+ and_phy_reg(pi, 0x44d,
+ ~(u16) ((0x1 << 3) | (0x1 << 5) | (0x1 << 14)));
+ mod_phy_reg(pi, 0x44d, (0x1 << 2), 1 << 2);
+
+ mod_phy_reg(pi, 0x44d, (0x1 << 1) | (0x1 << 0), (0x1 << 0));
+
+ and_phy_reg(pi, 0x4f9,
+ ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
+
+ and_phy_reg(pi, 0x4fa,
+ ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
+ } else {
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
+ mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 4), 1 << 4);
+ mod_phy_reg(pi, 0x43c, (0x1 << 6), 0 << 6);
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 12), 1 << 12);
+ mod_phy_reg(pi, 0x44d, (0x1 << 14), 1 << 14);
+
+ wlc_lcnphy_set_trsw_override(pi, true, false);
+
+ mod_phy_reg(pi, 0x44d, (0x1 << 2), 0 << 2);
+ mod_phy_reg(pi, 0x44c, (0x1 << 2), 1 << 2);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 3), 1 << 3);
+ mod_phy_reg(pi, 0x44d, (0x1 << 3), 1 << 3);
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 5), 1 << 5);
+ mod_phy_reg(pi, 0x44d, (0x1 << 5), 0 << 5);
+
+ mod_phy_reg(pi, 0x4f9, (0x1 << 1), 1 << 1);
+ mod_phy_reg(pi, 0x4fa, (0x1 << 1), 1 << 1);
+
+ mod_phy_reg(pi, 0x4f9, (0x1 << 2), 1 << 2);
+ mod_phy_reg(pi, 0x4fa, (0x1 << 2), 1 << 2);
+
+ mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0x4fa, (0x1 << 0), 1 << 0);
+ } else {
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 3), 1 << 3);
+ mod_phy_reg(pi, 0x44d, (0x1 << 3), 0 << 3);
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 5), 1 << 5);
+ mod_phy_reg(pi, 0x44d, (0x1 << 5), 1 << 5);
+
+ mod_phy_reg(pi, 0x4f9, (0x1 << 1), 1 << 1);
+ mod_phy_reg(pi, 0x4fa, (0x1 << 1), 0 << 1);
+
+ mod_phy_reg(pi, 0x4f9, (0x1 << 2), 1 << 2);
+ mod_phy_reg(pi, 0x4fa, (0x1 << 2), 0 << 2);
+
+ mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
+ }
+ }
+}
+
+static void
+wlc_lcnphy_run_samples(phy_info_t *pi,
+ u16 num_samps,
+ u16 num_loops, u16 wait, bool iqcalmode)
+{
+
+ or_phy_reg(pi, 0x6da, 0x8080);
+
+ mod_phy_reg(pi, 0x642, (0x7f << 0), (num_samps - 1) << 0);
+ if (num_loops != 0xffff)
+ num_loops--;
+ mod_phy_reg(pi, 0x640, (0xffff << 0), num_loops << 0);
+
+ mod_phy_reg(pi, 0x641, (0xffff << 0), wait << 0);
+
+ if (iqcalmode) {
+
+ and_phy_reg(pi, 0x453, (u16) ~(0x1 << 15));
+ or_phy_reg(pi, 0x453, (0x1 << 15));
+ } else {
+ write_phy_reg(pi, 0x63f, 1);
+ wlc_lcnphy_tx_pu(pi, 1);
+ }
+
+ or_radio_reg(pi, RADIO_2064_REG112, 0x6);
+}
+
+void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode)
+{
+
+ u8 phybw40;
+ phybw40 = CHSPEC_IS40(pi->radio_chanspec);
+
+ if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
+ mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
+ mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
+ } else {
+ mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
+ mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
+ }
+
+ if (phybw40 == 0) {
+ mod_phy_reg((pi), 0x410,
+ (0x1 << 6) |
+ (0x1 << 5),
+ ((CHSPEC_IS2G(pi->radio_chanspec)) ? (!mode) : 0) <<
+ 6 | (!mode) << 5);
+ mod_phy_reg(pi, 0x410, (0x1 << 7), (mode) << 7);
+ }
+}
+
+void
+wlc_lcnphy_start_tx_tone(phy_info_t *pi, s32 f_kHz, u16 max_val,
+ bool iqcalmode)
+{
+ u8 phy_bw;
+ u16 num_samps, t, k;
+ u32 bw;
+ fixed theta = 0, rot = 0;
+ cs32 tone_samp;
+ u32 data_buf[64];
+ u16 i_samp, q_samp;
+ phytbl_info_t tab;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ pi->phy_tx_tone_freq = f_kHz;
+
+ wlc_lcnphy_deaf_mode(pi, true);
+
+ phy_bw = 40;
+ if (pi_lcn->lcnphy_spurmod) {
+ write_phy_reg(pi, 0x942, 0x2);
+ write_phy_reg(pi, 0x93b, 0x0);
+ write_phy_reg(pi, 0x93c, 0x0);
+ wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
+ }
+
+ if (f_kHz) {
+ k = 1;
+ do {
+ bw = phy_bw * 1000 * k;
+ num_samps = bw / ABS(f_kHz);
+ k++;
+ } while ((num_samps * (u32) (ABS(f_kHz))) != bw);
+ } else
+ num_samps = 2;
+
+ rot = FIXED((f_kHz * 36) / phy_bw) / 100;
+ theta = 0;
+
+ for (t = 0; t < num_samps; t++) {
+
+ wlc_phy_cordic(theta, &tone_samp);
+
+ theta += rot;
+
+ i_samp = (u16) (FLOAT(tone_samp.i * max_val) & 0x3ff);
+ q_samp = (u16) (FLOAT(tone_samp.q * max_val) & 0x3ff);
+ data_buf[t] = (i_samp << 10) | q_samp;
+ }
+
+ mod_phy_reg(pi, 0x6d6, (0x3 << 0), 0 << 0);
+
+ mod_phy_reg(pi, 0x6da, (0x1 << 3), 1 << 3);
+
+ tab.tbl_ptr = data_buf;
+ tab.tbl_len = num_samps;
+ tab.tbl_id = LCNPHY_TBL_ID_SAMPLEPLAY;
+ tab.tbl_offset = 0;
+ tab.tbl_width = 32;
+ wlc_lcnphy_write_table(pi, &tab);
+
+ wlc_lcnphy_run_samples(pi, num_samps, 0xffff, 0, iqcalmode);
+}
+
+void wlc_lcnphy_stop_tx_tone(phy_info_t *pi)
+{
+ s16 playback_status;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ pi->phy_tx_tone_freq = 0;
+ if (pi_lcn->lcnphy_spurmod) {
+ write_phy_reg(pi, 0x942, 0x7);
+ write_phy_reg(pi, 0x93b, 0x2017);
+ write_phy_reg(pi, 0x93c, 0x27c5);
+ wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
+ }
+
+ playback_status = read_phy_reg(pi, 0x644);
+ if (playback_status & (0x1 << 0)) {
+ wlc_lcnphy_tx_pu(pi, 0);
+ mod_phy_reg(pi, 0x63f, (0x1 << 1), 1 << 1);
+ } else if (playback_status & (0x1 << 1))
+ mod_phy_reg(pi, 0x453, (0x1 << 15), 0 << 15);
+
+ mod_phy_reg(pi, 0x6d6, (0x3 << 0), 1 << 0);
+
+ mod_phy_reg(pi, 0x6da, (0x1 << 3), 0 << 3);
+
+ mod_phy_reg(pi, 0x6da, (0x1 << 7), 0 << 7);
+
+ and_radio_reg(pi, RADIO_2064_REG112, 0xFFF9);
+
+ wlc_lcnphy_deaf_mode(pi, false);
+}
+
+static void wlc_lcnphy_clear_trsw_override(phy_info_t *pi)
+{
+
+ and_phy_reg(pi, 0x44c, (u16) ~((0x1 << 1) | (0x1 << 0)));
+}
+
+void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b)
+{
+ u16 iqcc[2];
+ phytbl_info_t tab;
+
+ tab.tbl_ptr = iqcc;
+ tab.tbl_len = 2;
+ tab.tbl_id = 0;
+ tab.tbl_offset = 80;
+ tab.tbl_width = 16;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ *a = iqcc[0];
+ *b = iqcc[1];
+}
+
+u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi)
+{
+ phytbl_info_t tab;
+ u16 didq;
+
+ tab.tbl_id = 0;
+ tab.tbl_width = 16;
+ tab.tbl_ptr = &didq;
+ tab.tbl_len = 1;
+ tab.tbl_offset = 85;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ return didq;
+}
+
+static void wlc_lcnphy_txpwrtbl_iqlo_cal(phy_info_t *pi)
+{
+
+ lcnphy_txgains_t target_gains, old_gains;
+ u8 save_bb_mult;
+ u16 a, b, didq, save_pa_gain = 0;
+ uint idx, SAVE_txpwrindex = 0xFF;
+ u32 val;
+ u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ phytbl_info_t tab;
+ u8 ei0, eq0, fi0, fq0;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ wlc_lcnphy_get_tx_gain(pi, &old_gains);
+ save_pa_gain = wlc_lcnphy_get_pa_gain(pi);
+
+ save_bb_mult = wlc_lcnphy_get_bbmult(pi);
+
+ if (SAVE_txpwrctrl == LCNPHY_TX_PWR_CTRL_OFF)
+ SAVE_txpwrindex = wlc_lcnphy_get_current_tx_pwr_idx(pi);
+
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
+
+ target_gains.gm_gain = 7;
+ target_gains.pga_gain = 0;
+ target_gains.pad_gain = 21;
+ target_gains.dac_gain = 0;
+ wlc_lcnphy_set_tx_gain(pi, &target_gains);
+ wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1) || pi_lcn->lcnphy_hw_iqcal_en) {
+
+ wlc_lcnphy_set_tx_pwr_by_index(pi, 30);
+
+ wlc_lcnphy_tx_iqlo_cal(pi, &target_gains,
+ (pi_lcn->
+ lcnphy_recal ? LCNPHY_CAL_RECAL :
+ LCNPHY_CAL_FULL), false);
+ } else {
+
+ wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
+ }
+
+ wlc_lcnphy_get_radio_loft(pi, &ei0, &eq0, &fi0, &fq0);
+ if ((ABS((s8) fi0) == 15) && (ABS((s8) fq0) == 15)) {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ target_gains.gm_gain = 255;
+ target_gains.pga_gain = 255;
+ target_gains.pad_gain = 0xf0;
+ target_gains.dac_gain = 0;
+ } else {
+ target_gains.gm_gain = 7;
+ target_gains.pga_gain = 45;
+ target_gains.pad_gain = 186;
+ target_gains.dac_gain = 0;
+ }
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1)
+ || pi_lcn->lcnphy_hw_iqcal_en) {
+
+ target_gains.pga_gain = 0;
+ target_gains.pad_gain = 30;
+ wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
+ wlc_lcnphy_tx_iqlo_cal(pi, &target_gains,
+ LCNPHY_CAL_FULL, false);
+ } else {
+
+ wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
+ }
+
+ }
+
+ wlc_lcnphy_get_tx_iqcc(pi, &a, &b);
+
+ didq = wlc_lcnphy_get_tx_locc(pi);
+
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_ptr = &val;
+
+ tab.tbl_len = 1;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
+
+ for (idx = 0; idx < 128; idx++) {
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + idx;
+
+ wlc_lcnphy_read_table(pi, &tab);
+ val = (val & 0xfff00000) |
+ ((u32) (a & 0x3FF) << 10) | (b & 0x3ff);
+ wlc_lcnphy_write_table(pi, &tab);
+
+ val = didq;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + idx;
+ wlc_lcnphy_write_table(pi, &tab);
+ }
+
+ pi_lcn->lcnphy_cal_results.txiqlocal_a = a;
+ pi_lcn->lcnphy_cal_results.txiqlocal_b = b;
+ pi_lcn->lcnphy_cal_results.txiqlocal_didq = didq;
+ pi_lcn->lcnphy_cal_results.txiqlocal_ei0 = ei0;
+ pi_lcn->lcnphy_cal_results.txiqlocal_eq0 = eq0;
+ pi_lcn->lcnphy_cal_results.txiqlocal_fi0 = fi0;
+ pi_lcn->lcnphy_cal_results.txiqlocal_fq0 = fq0;
+
+ wlc_lcnphy_set_bbmult(pi, save_bb_mult);
+ wlc_lcnphy_set_pa_gain(pi, save_pa_gain);
+ wlc_lcnphy_set_tx_gain(pi, &old_gains);
+
+ if (SAVE_txpwrctrl != LCNPHY_TX_PWR_CTRL_OFF)
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
+ else
+ wlc_lcnphy_set_tx_pwr_by_index(pi, SAVE_txpwrindex);
+}
+
+s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode)
+{
+ u16 tempsenseval1, tempsenseval2;
+ s16 avg = 0;
+ bool suspend = 0;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return -1;
+
+ if (mode == 1) {
+ suspend =
+ (0 ==
+ (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
+ }
+ tempsenseval1 = read_phy_reg(pi, 0x476) & 0x1FF;
+ tempsenseval2 = read_phy_reg(pi, 0x477) & 0x1FF;
+
+ if (tempsenseval1 > 255)
+ avg = (s16) (tempsenseval1 - 512);
+ else
+ avg = (s16) tempsenseval1;
+
+ if (tempsenseval2 > 255)
+ avg += (s16) (tempsenseval2 - 512);
+ else
+ avg += (s16) tempsenseval2;
+
+ avg /= 2;
+
+ if (mode == 1) {
+
+ mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
+
+ udelay(100);
+ mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
+
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+ }
+ return avg;
+}
+
+u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode)
+{
+ u16 tempsenseval1, tempsenseval2;
+ s32 avg = 0;
+ bool suspend = 0;
+ u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return -1;
+
+ if (mode == 1) {
+ suspend =
+ (0 ==
+ (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
+ }
+ tempsenseval1 = read_phy_reg(pi, 0x476) & 0x1FF;
+ tempsenseval2 = read_phy_reg(pi, 0x477) & 0x1FF;
+
+ if (tempsenseval1 > 255)
+ avg = (int)(tempsenseval1 - 512);
+ else
+ avg = (int)tempsenseval1;
+
+ if (pi_lcn->lcnphy_tempsense_option == 1 || pi->hwpwrctrl_capable) {
+ if (tempsenseval2 > 255)
+ avg = (int)(avg - tempsenseval2 + 512);
+ else
+ avg = (int)(avg - tempsenseval2);
+ } else {
+ if (tempsenseval2 > 255)
+ avg = (int)(avg + tempsenseval2 - 512);
+ else
+ avg = (int)(avg + tempsenseval2);
+ avg = avg / 2;
+ }
+ if (avg < 0)
+ avg = avg + 512;
+
+ if (pi_lcn->lcnphy_tempsense_option == 2)
+ avg = tempsenseval1;
+
+ if (mode)
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
+
+ if (mode == 1) {
+
+ mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
+
+ udelay(100);
+ mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
+
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+ }
+ return (u16) avg;
+}
+
+s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode)
+{
+ s32 degree = wlc_lcnphy_tempsense_new(pi, mode);
+ degree =
+ ((degree << 10) + LCN_TEMPSENSE_OFFSET + (LCN_TEMPSENSE_DEN >> 1))
+ / LCN_TEMPSENSE_DEN;
+ return (s8) degree;
+}
+
+s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode)
+{
+ u16 vbatsenseval;
+ s32 avg = 0;
+ bool suspend = 0;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return -1;
+
+ if (mode == 1) {
+ suspend =
+ (0 ==
+ (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ wlc_lcnphy_vbat_temp_sense_setup(pi, VBATSENSE);
+ }
+
+ vbatsenseval = read_phy_reg(pi, 0x475) & 0x1FF;
+
+ if (vbatsenseval > 255)
+ avg = (s32) (vbatsenseval - 512);
+ else
+ avg = (s32) vbatsenseval;
+
+ avg =
+ (avg * LCN_VBAT_SCALE_NOM +
+ (LCN_VBAT_SCALE_DEN >> 1)) / LCN_VBAT_SCALE_DEN;
+
+ if (mode == 1) {
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+ }
+ return (s8) avg;
+}
+
+static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode)
+{
+ u8 phybw40;
+ phybw40 = CHSPEC_IS40(pi->radio_chanspec);
+
+ mod_phy_reg(pi, 0x6d1, (0x1 << 7), (1) << 7);
+
+ if (((mode == AFE_CLK_INIT_MODE_PAPD) && (phybw40 == 0)) ||
+ (mode == AFE_CLK_INIT_MODE_TXRX2X))
+ write_phy_reg(pi, 0x6d0, 0x7);
+
+ wlc_lcnphy_toggle_afe_pwdn(pi);
+}
+
+static bool
+wlc_lcnphy_rx_iq_est(phy_info_t *pi,
+ u16 num_samps,
+ u8 wait_time, lcnphy_iq_est_t *iq_est)
+{
+ int wait_count = 0;
+ bool result = true;
+ u8 phybw40;
+ phybw40 = CHSPEC_IS40(pi->radio_chanspec);
+
+ mod_phy_reg(pi, 0x6da, (0x1 << 5), (1) << 5);
+
+ mod_phy_reg(pi, 0x410, (0x1 << 3), (0) << 3);
+
+ mod_phy_reg(pi, 0x482, (0xffff << 0), (num_samps) << 0);
+
+ mod_phy_reg(pi, 0x481, (0xff << 0), ((u16) wait_time) << 0);
+
+ mod_phy_reg(pi, 0x481, (0x1 << 8), (0) << 8);
+
+ mod_phy_reg(pi, 0x481, (0x1 << 9), (1) << 9);
+
+ while (read_phy_reg(pi, 0x481) & (0x1 << 9)) {
+
+ if (wait_count > (10 * 500)) {
+ result = false;
+ goto cleanup;
+ }
+ udelay(100);
+ wait_count++;
+ }
+
+ iq_est->iq_prod = ((u32) read_phy_reg(pi, 0x483) << 16) |
+ (u32) read_phy_reg(pi, 0x484);
+ iq_est->i_pwr = ((u32) read_phy_reg(pi, 0x485) << 16) |
+ (u32) read_phy_reg(pi, 0x486);
+ iq_est->q_pwr = ((u32) read_phy_reg(pi, 0x487) << 16) |
+ (u32) read_phy_reg(pi, 0x488);
+
+ cleanup:
+ mod_phy_reg(pi, 0x410, (0x1 << 3), (1) << 3);
+
+ mod_phy_reg(pi, 0x6da, (0x1 << 5), (0) << 5);
+
+ return result;
+}
+
+static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps)
+{
+#define LCNPHY_MIN_RXIQ_PWR 2
+ bool result;
+ u16 a0_new, b0_new;
+ lcnphy_iq_est_t iq_est = { 0, 0, 0 };
+ s32 a, b, temp;
+ s16 iq_nbits, qq_nbits, arsh, brsh;
+ s32 iq;
+ u32 ii, qq;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ a0_new = ((read_phy_reg(pi, 0x645) & (0x3ff << 0)) >> 0);
+ b0_new = ((read_phy_reg(pi, 0x646) & (0x3ff << 0)) >> 0);
+ mod_phy_reg(pi, 0x6d1, (0x1 << 2), (0) << 2);
+
+ mod_phy_reg(pi, 0x64b, (0x1 << 6), (1) << 6);
+
+ wlc_lcnphy_set_rx_iq_comp(pi, 0, 0);
+
+ result = wlc_lcnphy_rx_iq_est(pi, num_samps, 32, &iq_est);
+ if (!result)
+ goto cleanup;
+
+ iq = (s32) iq_est.iq_prod;
+ ii = iq_est.i_pwr;
+ qq = iq_est.q_pwr;
+
+ if ((ii + qq) < LCNPHY_MIN_RXIQ_PWR) {
+ result = false;
+ goto cleanup;
+ }
+
+ iq_nbits = wlc_phy_nbits(iq);
+ qq_nbits = wlc_phy_nbits(qq);
+
+ arsh = 10 - (30 - iq_nbits);
+ if (arsh >= 0) {
+ a = (-(iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
+ temp = (s32) (ii >> arsh);
+ if (temp == 0) {
+ return false;
+ }
+ } else {
+ a = (-(iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
+ temp = (s32) (ii << -arsh);
+ if (temp == 0) {
+ return false;
+ }
+ }
+ a /= temp;
+ brsh = qq_nbits - 31 + 20;
+ if (brsh >= 0) {
+ b = (qq << (31 - qq_nbits));
+ temp = (s32) (ii >> brsh);
+ if (temp == 0) {
+ return false;
+ }
+ } else {
+ b = (qq << (31 - qq_nbits));
+ temp = (s32) (ii << -brsh);
+ if (temp == 0) {
+ return false;
+ }
+ }
+ b /= temp;
+ b -= a * a;
+ b = (s32) int_sqrt((unsigned long) b);
+ b -= (1 << 10);
+ a0_new = (u16) (a & 0x3ff);
+ b0_new = (u16) (b & 0x3ff);
+ cleanup:
+
+ wlc_lcnphy_set_rx_iq_comp(pi, a0_new, b0_new);
+
+ mod_phy_reg(pi, 0x64b, (0x1 << 0), (1) << 0);
+
+ mod_phy_reg(pi, 0x64b, (0x1 << 3), (1) << 3);
+
+ pi_lcn->lcnphy_cal_results.rxiqcal_coeff_a0 = a0_new;
+ pi_lcn->lcnphy_cal_results.rxiqcal_coeff_b0 = b0_new;
+
+ return result;
+}
+
+static bool
+wlc_lcnphy_rx_iq_cal(phy_info_t *pi, const lcnphy_rx_iqcomp_t *iqcomp,
+ int iqcomp_sz, bool tx_switch, bool rx_switch, int module,
+ int tx_gain_idx)
+{
+ lcnphy_txgains_t old_gains;
+ u16 tx_pwr_ctrl;
+ u8 tx_gain_index_old = 0;
+ bool result = false, tx_gain_override_old = false;
+ u16 i, Core1TxControl_old, RFOverride0_old,
+ RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old,
+ rfoverride3_old, rfoverride3val_old, rfoverride4_old,
+ rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
+ int tia_gain;
+ u32 received_power, rx_pwr_threshold;
+ u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
+ u16 values_to_save[11];
+ s16 *ptr;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ ptr = kmalloc(sizeof(s16) * 131, GFP_ATOMIC);
+ if (NULL == ptr) {
+ return false;
+ }
+ if (module == 2) {
+ while (iqcomp_sz--) {
+ if (iqcomp[iqcomp_sz].chan ==
+ CHSPEC_CHANNEL(pi->radio_chanspec)) {
+
+ wlc_lcnphy_set_rx_iq_comp(pi,
+ (u16)
+ iqcomp[iqcomp_sz].a,
+ (u16)
+ iqcomp[iqcomp_sz].b);
+ result = true;
+ break;
+ }
+ }
+ goto cal_done;
+ }
+
+ if (module == 1) {
+
+ tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
+
+ for (i = 0; i < 11; i++) {
+ values_to_save[i] =
+ read_radio_reg(pi, rxiq_cal_rf_reg[i]);
+ }
+ Core1TxControl_old = read_phy_reg(pi, 0x631);
+
+ or_phy_reg(pi, 0x631, 0x0015);
+
+ RFOverride0_old = read_phy_reg(pi, 0x44c);
+ RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
+ rfoverride2_old = read_phy_reg(pi, 0x4b0);
+ rfoverride2val_old = read_phy_reg(pi, 0x4b1);
+ rfoverride3_old = read_phy_reg(pi, 0x4f9);
+ rfoverride3val_old = read_phy_reg(pi, 0x4fa);
+ rfoverride4_old = read_phy_reg(pi, 0x938);
+ rfoverride4val_old = read_phy_reg(pi, 0x939);
+ afectrlovr_old = read_phy_reg(pi, 0x43b);
+ afectrlovrval_old = read_phy_reg(pi, 0x43c);
+ old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
+ old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
+
+ tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
+ if (tx_gain_override_old) {
+ wlc_lcnphy_get_tx_gain(pi, &old_gains);
+ tx_gain_index_old = pi_lcn->lcnphy_current_index;
+ }
+
+ wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
+
+ mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
+ mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
+
+ write_radio_reg(pi, RADIO_2064_REG116, 0x06);
+ write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
+ write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
+ write_radio_reg(pi, RADIO_2064_REG098, 0x03);
+ write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
+ mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
+ write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
+ write_radio_reg(pi, RADIO_2064_REG114, 0x01);
+ write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
+ write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
+
+ mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
+ mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
+ mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
+ mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
+ mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
+ mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
+ mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
+ mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
+ mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
+
+ wlc_lcnphy_start_tx_tone(pi, 2000, 120, 0);
+ write_phy_reg(pi, 0x6da, 0xffff);
+ or_phy_reg(pi, 0x6db, 0x3);
+ wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
+ wlc_lcnphy_rx_gain_override_enable(pi, true);
+
+ tia_gain = 8;
+ rx_pwr_threshold = 950;
+ while (tia_gain > 0) {
+ tia_gain -= 1;
+ wlc_lcnphy_set_rx_gain_by_distribution(pi,
+ 0, 0, 2, 2,
+ (u16)
+ tia_gain, 1, 0);
+ udelay(500);
+
+ received_power =
+ wlc_lcnphy_measure_digital_power(pi, 2000);
+ if (received_power < rx_pwr_threshold)
+ break;
+ }
+ result = wlc_lcnphy_calc_rx_iq_comp(pi, 0xffff);
+
+ wlc_lcnphy_stop_tx_tone(pi);
+
+ write_phy_reg(pi, 0x631, Core1TxControl_old);
+
+ write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
+ write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
+ write_phy_reg(pi, 0x4b0, rfoverride2_old);
+ write_phy_reg(pi, 0x4b1, rfoverride2val_old);
+ write_phy_reg(pi, 0x4f9, rfoverride3_old);
+ write_phy_reg(pi, 0x4fa, rfoverride3val_old);
+ write_phy_reg(pi, 0x938, rfoverride4_old);
+ write_phy_reg(pi, 0x939, rfoverride4val_old);
+ write_phy_reg(pi, 0x43b, afectrlovr_old);
+ write_phy_reg(pi, 0x43c, afectrlovrval_old);
+ write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
+ write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
+
+ wlc_lcnphy_clear_trsw_override(pi);
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
+
+ for (i = 0; i < 11; i++) {
+ write_radio_reg(pi, rxiq_cal_rf_reg[i],
+ values_to_save[i]);
+ }
+
+ if (tx_gain_override_old) {
+ wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
+ } else
+ wlc_lcnphy_disable_tx_gain_override(pi);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
+
+ wlc_lcnphy_rx_gain_override_enable(pi, false);
+ }
+
+ cal_done:
+ kfree(ptr);
+ return result;
+}
+
+static void wlc_lcnphy_temp_adj(phy_info_t *pi)
+{
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+}
+
+static void wlc_lcnphy_glacial_timer_based_cal(phy_info_t *pi)
+{
+ bool suspend;
+ s8 index;
+ u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+ suspend =
+ (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ wlc_lcnphy_deaf_mode(pi, true);
+ pi->phy_lastcal = pi->sh->now;
+ pi->phy_forcecal = false;
+ index = pi_lcn->lcnphy_current_index;
+
+ wlc_lcnphy_txpwrtbl_iqlo_cal(pi);
+
+ wlc_lcnphy_set_tx_pwr_by_index(pi, index);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_pwrctrl);
+ wlc_lcnphy_deaf_mode(pi, false);
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+
+}
+
+static void wlc_lcnphy_periodic_cal(phy_info_t *pi)
+{
+ bool suspend, full_cal;
+ const lcnphy_rx_iqcomp_t *rx_iqcomp;
+ int rx_iqcomp_sz;
+ u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ s8 index;
+ phytbl_info_t tab;
+ s32 a1, b0, b1;
+ s32 tssi, pwr, maxtargetpwr, mintargetpwr;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ pi->phy_lastcal = pi->sh->now;
+ pi->phy_forcecal = false;
+ full_cal =
+ (pi_lcn->lcnphy_full_cal_channel !=
+ CHSPEC_CHANNEL(pi->radio_chanspec));
+ pi_lcn->lcnphy_full_cal_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
+ index = pi_lcn->lcnphy_current_index;
+
+ suspend =
+ (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend) {
+
+ wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ }
+ wlc_lcnphy_deaf_mode(pi, true);
+
+ wlc_lcnphy_txpwrtbl_iqlo_cal(pi);
+
+ rx_iqcomp = lcnphy_rx_iqcomp_table_rev0;
+ rx_iqcomp_sz = ARRAY_SIZE(lcnphy_rx_iqcomp_table_rev0);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1))
+ wlc_lcnphy_rx_iq_cal(pi, NULL, 0, true, false, 1, 40);
+ else
+ wlc_lcnphy_rx_iq_cal(pi, NULL, 0, true, false, 1, 127);
+
+ if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) {
+
+ wlc_lcnphy_idle_tssi_est((wlc_phy_t *) pi);
+
+ b0 = pi->txpa_2g[0];
+ b1 = pi->txpa_2g[1];
+ a1 = pi->txpa_2g[2];
+ maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1);
+ mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1);
+
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_ptr = &pwr;
+ tab.tbl_len = 1;
+ tab.tbl_offset = 0;
+ for (tssi = 0; tssi < 128; tssi++) {
+ pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1);
+ pwr = (pwr < mintargetpwr) ? mintargetpwr : pwr;
+ wlc_lcnphy_write_table(pi, &tab);
+ tab.tbl_offset++;
+ }
+ }
+
+ wlc_lcnphy_set_tx_pwr_by_index(pi, index);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_pwrctrl);
+ wlc_lcnphy_deaf_mode(pi, false);
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+}
+
+void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode)
+{
+ u16 temp_new;
+ int temp1, temp2, temp_diff;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ switch (mode) {
+ case PHY_PERICAL_CHAN:
+
+ break;
+ case PHY_FULLCAL:
+ wlc_lcnphy_periodic_cal(pi);
+ break;
+ case PHY_PERICAL_PHYINIT:
+ wlc_lcnphy_periodic_cal(pi);
+ break;
+ case PHY_PERICAL_WATCHDOG:
+ if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
+ temp_new = wlc_lcnphy_tempsense(pi, 0);
+ temp1 = LCNPHY_TEMPSENSE(temp_new);
+ temp2 = LCNPHY_TEMPSENSE(pi_lcn->lcnphy_cal_temper);
+ temp_diff = temp1 - temp2;
+ if ((pi_lcn->lcnphy_cal_counter > 90) ||
+ (temp_diff > 60) || (temp_diff < -60)) {
+ wlc_lcnphy_glacial_timer_based_cal(pi);
+ wlc_2064_vco_cal(pi);
+ pi_lcn->lcnphy_cal_temper = temp_new;
+ pi_lcn->lcnphy_cal_counter = 0;
+ } else
+ pi_lcn->lcnphy_cal_counter++;
+ }
+ break;
+ case LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL:
+ if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
+ wlc_lcnphy_tx_power_adjustment((wlc_phy_t *) pi);
+ break;
+ }
+}
+
+void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr, s8 *cck_pwr)
+{
+ s8 cck_offset;
+ u16 status;
+ status = (read_phy_reg(pi, 0x4ab));
+ if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) &&
+ (status & (0x1 << 15))) {
+ *ofdm_pwr = (s8) (((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
+ >> 0) >> 1);
+
+ if (wlc_phy_tpc_isenabled_lcnphy(pi))
+ cck_offset = pi->tx_power_offset[TXP_FIRST_CCK];
+ else
+ cck_offset = 0;
+
+ *cck_pwr = *ofdm_pwr + cck_offset;
+ } else {
+ *cck_pwr = 0;
+ *ofdm_pwr = 0;
+ }
+}
+
+void WLBANDINITFN(wlc_phy_cal_init_lcnphy) (phy_info_t *pi)
+{
+ return;
+
+}
+
+static void wlc_lcnphy_set_chanspec_tweaks(phy_info_t *pi, chanspec_t chanspec)
+{
+ u8 channel = CHSPEC_CHANNEL(chanspec);
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ if (channel == 14) {
+ mod_phy_reg(pi, 0x448, (0x3 << 8), (2) << 8);
+
+ } else {
+ mod_phy_reg(pi, 0x448, (0x3 << 8), (1) << 8);
+
+ }
+ pi_lcn->lcnphy_bandedge_corr = 2;
+ if (channel == 1)
+ pi_lcn->lcnphy_bandedge_corr = 4;
+
+ if (channel == 1 || channel == 2 || channel == 3 ||
+ channel == 4 || channel == 9 ||
+ channel == 10 || channel == 11 || channel == 12) {
+ si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03000c04);
+ si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x0);
+ si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x200005c0);
+
+ si_pmu_pllupd(pi->sh->sih);
+ write_phy_reg(pi, 0x942, 0);
+ wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
+ pi_lcn->lcnphy_spurmod = 0;
+ mod_phy_reg(pi, 0x424, (0xff << 8), (0x1b) << 8);
+
+ write_phy_reg(pi, 0x425, 0x5907);
+ } else {
+ si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03140c04);
+ si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x333333);
+ si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x202c2820);
+
+ si_pmu_pllupd(pi->sh->sih);
+ write_phy_reg(pi, 0x942, 0);
+ wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
+
+ pi_lcn->lcnphy_spurmod = 0;
+ mod_phy_reg(pi, 0x424, (0xff << 8), (0x1f) << 8);
+
+ write_phy_reg(pi, 0x425, 0x590a);
+ }
+
+ or_phy_reg(pi, 0x44a, 0x44);
+ write_phy_reg(pi, 0x44a, 0x80);
+}
+
+void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi)
+{
+ s8 index;
+ u16 index2;
+ phy_info_t *pi = (phy_info_t *) ppi;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+ u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) && SAVE_txpwrctrl) {
+ index = wlc_lcnphy_tempcompensated_txpwrctrl(pi);
+ index2 = (u16) (index * 2);
+ mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0);
+
+ pi_lcn->lcnphy_current_index = (s8)
+ ((read_phy_reg(pi, 0x4a9) & 0xFF) / 2);
+ }
+}
+
+static void wlc_lcnphy_set_rx_iq_comp(phy_info_t *pi, u16 a, u16 b)
+{
+ mod_phy_reg(pi, 0x645, (0x3ff << 0), (a) << 0);
+
+ mod_phy_reg(pi, 0x646, (0x3ff << 0), (b) << 0);
+
+ mod_phy_reg(pi, 0x647, (0x3ff << 0), (a) << 0);
+
+ mod_phy_reg(pi, 0x648, (0x3ff << 0), (b) << 0);
+
+ mod_phy_reg(pi, 0x649, (0x3ff << 0), (a) << 0);
+
+ mod_phy_reg(pi, 0x64a, (0x3ff << 0), (b) << 0);
+
+}
+
+void WLBANDINITFN(wlc_phy_init_lcnphy) (phy_info_t *pi)
+{
+ u8 phybw40;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+ phybw40 = CHSPEC_IS40(pi->radio_chanspec);
+
+ pi_lcn->lcnphy_cal_counter = 0;
+ pi_lcn->lcnphy_cal_temper = pi_lcn->lcnphy_rawtempsense;
+
+ or_phy_reg(pi, 0x44a, 0x80);
+ and_phy_reg(pi, 0x44a, 0x7f);
+
+ wlc_lcnphy_afe_clk_init(pi, AFE_CLK_INIT_MODE_TXRX2X);
+
+ write_phy_reg(pi, 0x60a, 160);
+
+ write_phy_reg(pi, 0x46a, 25);
+
+ wlc_lcnphy_baseband_init(pi);
+
+ wlc_lcnphy_radio_init(pi);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec))
+ wlc_lcnphy_tx_pwr_ctrl_init((wlc_phy_t *) pi);
+
+ wlc_phy_chanspec_set((wlc_phy_t *) pi, pi->radio_chanspec);
+
+ si_pmu_regcontrol(pi->sh->sih, 0, 0xf, 0x9);
+
+ si_pmu_chipcontrol(pi->sh->sih, 0, 0xffffffff, 0x03CDDDDD);
+
+ if ((pi->sh->boardflags & BFL_FEM)
+ && wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
+ wlc_lcnphy_set_tx_pwr_by_index(pi, FIXED_TXPWR);
+
+ wlc_lcnphy_agc_temp_init(pi);
+
+ wlc_lcnphy_temp_adj(pi);
+
+ mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
+
+ udelay(100);
+ mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
+
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
+ pi_lcn->lcnphy_noise_samples = LCNPHY_NOISE_SAMPLES_DEFAULT;
+ wlc_lcnphy_calib_modes(pi, PHY_PERICAL_PHYINIT);
+}
+
+static void
+wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, u16 *values_to_save)
+{
+ u16 vmid;
+ int i;
+ for (i = 0; i < 20; i++) {
+ values_to_save[i] =
+ read_radio_reg(pi, iqlo_loopback_rf_regs[i]);
+ }
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 12), 1 << 12);
+ mod_phy_reg(pi, 0x44d, (0x1 << 14), 1 << 14);
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 11), 1 << 11);
+ mod_phy_reg(pi, 0x44d, (0x1 << 13), 0 << 13);
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
+ mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
+
+ mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2))
+ and_radio_reg(pi, RADIO_2064_REG03A, 0xFD);
+ else
+ and_radio_reg(pi, RADIO_2064_REG03A, 0xF9);
+ or_radio_reg(pi, RADIO_2064_REG11A, 0x1);
+
+ or_radio_reg(pi, RADIO_2064_REG036, 0x01);
+ or_radio_reg(pi, RADIO_2064_REG11A, 0x18);
+ udelay(20);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+ if (CHSPEC_IS5G(pi->radio_chanspec))
+ mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0);
+ else
+ or_radio_reg(pi, RADIO_2064_REG03A, 1);
+ } else {
+ if (CHSPEC_IS5G(pi->radio_chanspec))
+ mod_radio_reg(pi, RADIO_2064_REG03A, 3, 1);
+ else
+ or_radio_reg(pi, RADIO_2064_REG03A, 0x3);
+ }
+
+ udelay(20);
+
+ write_radio_reg(pi, RADIO_2064_REG025, 0xF);
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+ if (CHSPEC_IS5G(pi->radio_chanspec))
+ mod_radio_reg(pi, RADIO_2064_REG028, 0xF, 0x4);
+ else
+ mod_radio_reg(pi, RADIO_2064_REG028, 0xF, 0x6);
+ } else {
+ if (CHSPEC_IS5G(pi->radio_chanspec))
+ mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x4 << 1);
+ else
+ mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x6 << 1);
+ }
+
+ udelay(20);
+
+ write_radio_reg(pi, RADIO_2064_REG005, 0x8);
+ or_radio_reg(pi, RADIO_2064_REG112, 0x80);
+ udelay(20);
+
+ or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
+ or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
+ udelay(20);
+
+ or_radio_reg(pi, RADIO_2064_REG00B, 0x7);
+ or_radio_reg(pi, RADIO_2064_REG113, 0x10);
+ udelay(20);
+
+ write_radio_reg(pi, RADIO_2064_REG007, 0x1);
+ udelay(20);
+
+ vmid = 0x2A6;
+ mod_radio_reg(pi, RADIO_2064_REG0FC, 0x3 << 0, (vmid >> 8) & 0x3);
+ write_radio_reg(pi, RADIO_2064_REG0FD, (vmid & 0xff));
+ or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
+ udelay(20);
+
+ or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
+ udelay(20);
+ write_radio_reg(pi, RADIO_2064_REG012, 0x02);
+ or_radio_reg(pi, RADIO_2064_REG112, 0x06);
+ write_radio_reg(pi, RADIO_2064_REG036, 0x11);
+ write_radio_reg(pi, RADIO_2064_REG059, 0xcc);
+ write_radio_reg(pi, RADIO_2064_REG05C, 0x2e);
+ write_radio_reg(pi, RADIO_2064_REG078, 0xd7);
+ write_radio_reg(pi, RADIO_2064_REG092, 0x15);
+}
+
+static void
+wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
+ s16 *ptr, int mode)
+{
+ u32 curval1, curval2, stpptr, curptr, strptr, val;
+ u16 sslpnCalibClkEnCtrl, timer;
+ u16 old_sslpnCalibClkEnCtrl;
+ s16 imag, real;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ timer = 0;
+ old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
+
+ curval1 = R_REG(&pi->regs->psm_corectlsts);
+ ptr[130] = 0;
+ W_REG(&pi->regs->psm_corectlsts, ((1 << 6) | curval1));
+
+ W_REG(&pi->regs->smpl_clct_strptr, 0x7E00);
+ W_REG(&pi->regs->smpl_clct_stpptr, 0x8000);
+ udelay(20);
+ curval2 = R_REG(&pi->regs->psm_phy_hdr_param);
+ W_REG(&pi->regs->psm_phy_hdr_param, curval2 | 0x30);
+
+ write_phy_reg(pi, 0x555, 0x0);
+ write_phy_reg(pi, 0x5a6, 0x5);
+
+ write_phy_reg(pi, 0x5a2, (u16) (mode | mode << 6));
+ write_phy_reg(pi, 0x5cf, 3);
+ write_phy_reg(pi, 0x5a5, 0x3);
+ write_phy_reg(pi, 0x583, 0x0);
+ write_phy_reg(pi, 0x584, 0x0);
+ write_phy_reg(pi, 0x585, 0x0fff);
+ write_phy_reg(pi, 0x586, 0x0000);
+
+ write_phy_reg(pi, 0x580, 0x4501);
+
+ sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
+ write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl | 0x2008));
+ stpptr = R_REG(&pi->regs->smpl_clct_stpptr);
+ curptr = R_REG(&pi->regs->smpl_clct_curptr);
+ do {
+ udelay(10);
+ curptr = R_REG(&pi->regs->smpl_clct_curptr);
+ timer++;
+ } while ((curptr != stpptr) && (timer < 500));
+
+ W_REG(&pi->regs->psm_phy_hdr_param, 0x2);
+ strptr = 0x7E00;
+ W_REG(&pi->regs->tplatewrptr, strptr);
+ while (strptr < 0x8000) {
+ val = R_REG(&pi->regs->tplatewrdata);
+ imag = ((val >> 16) & 0x3ff);
+ real = ((val) & 0x3ff);
+ if (imag > 511) {
+ imag -= 1024;
+ }
+ if (real > 511) {
+ real -= 1024;
+ }
+ if (pi_lcn->lcnphy_iqcal_swp_dis)
+ ptr[(strptr - 0x7E00) / 4] = real;
+ else
+ ptr[(strptr - 0x7E00) / 4] = imag;
+ if (clip_detect_algo) {
+ if (imag > thresh || imag < -thresh) {
+ strptr = 0x8000;
+ ptr[130] = 1;
+ }
+ }
+ strptr += 4;
+ }
+
+ write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
+ W_REG(&pi->regs->psm_phy_hdr_param, curval2);
+ W_REG(&pi->regs->psm_corectlsts, curval1);
+}
+
+static void wlc_lcnphy_tx_iqlo_soft_cal_full(phy_info_t *pi)
+{
+ lcnphy_unsign16_struct iqcc0, locc2, locc3, locc4;
+
+ wlc_lcnphy_set_cc(pi, 0, 0, 0);
+ wlc_lcnphy_set_cc(pi, 2, 0, 0);
+ wlc_lcnphy_set_cc(pi, 3, 0, 0);
+ wlc_lcnphy_set_cc(pi, 4, 0, 0);
+
+ wlc_lcnphy_a1(pi, 4, 0, 0);
+ wlc_lcnphy_a1(pi, 3, 0, 0);
+ wlc_lcnphy_a1(pi, 2, 3, 2);
+ wlc_lcnphy_a1(pi, 0, 5, 8);
+ wlc_lcnphy_a1(pi, 2, 2, 1);
+ wlc_lcnphy_a1(pi, 0, 4, 3);
+
+ iqcc0 = wlc_lcnphy_get_cc(pi, 0);
+ locc2 = wlc_lcnphy_get_cc(pi, 2);
+ locc3 = wlc_lcnphy_get_cc(pi, 3);
+ locc4 = wlc_lcnphy_get_cc(pi, 4);
+}
+
+static void
+wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, s16 coeff_x, s16 coeff_y)
+{
+ u16 di0dq0;
+ u16 x, y, data_rf;
+ int k;
+ switch (cal_type) {
+ case 0:
+ wlc_lcnphy_set_tx_iqcc(pi, coeff_x, coeff_y);
+ break;
+ case 2:
+ di0dq0 = (coeff_x & 0xff) << 8 | (coeff_y & 0xff);
+ wlc_lcnphy_set_tx_locc(pi, di0dq0);
+ break;
+ case 3:
+ k = wlc_lcnphy_calc_floor(coeff_x, 0);
+ y = 8 + k;
+ k = wlc_lcnphy_calc_floor(coeff_x, 1);
+ x = 8 - k;
+ data_rf = (x * 16 + y);
+ write_radio_reg(pi, RADIO_2064_REG089, data_rf);
+ k = wlc_lcnphy_calc_floor(coeff_y, 0);
+ y = 8 + k;
+ k = wlc_lcnphy_calc_floor(coeff_y, 1);
+ x = 8 - k;
+ data_rf = (x * 16 + y);
+ write_radio_reg(pi, RADIO_2064_REG08A, data_rf);
+ break;
+ case 4:
+ k = wlc_lcnphy_calc_floor(coeff_x, 0);
+ y = 8 + k;
+ k = wlc_lcnphy_calc_floor(coeff_x, 1);
+ x = 8 - k;
+ data_rf = (x * 16 + y);
+ write_radio_reg(pi, RADIO_2064_REG08B, data_rf);
+ k = wlc_lcnphy_calc_floor(coeff_y, 0);
+ y = 8 + k;
+ k = wlc_lcnphy_calc_floor(coeff_y, 1);
+ x = 8 - k;
+ data_rf = (x * 16 + y);
+ write_radio_reg(pi, RADIO_2064_REG08C, data_rf);
+ break;
+ }
+}
+
+static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type)
+{
+ u16 a, b, didq;
+ u8 di0, dq0, ei, eq, fi, fq;
+ lcnphy_unsign16_struct cc;
+ cc.re = 0;
+ cc.im = 0;
+ switch (cal_type) {
+ case 0:
+ wlc_lcnphy_get_tx_iqcc(pi, &a, &b);
+ cc.re = a;
+ cc.im = b;
+ break;
+ case 2:
+ didq = wlc_lcnphy_get_tx_locc(pi);
+ di0 = (((didq & 0xff00) << 16) >> 24);
+ dq0 = (((didq & 0x00ff) << 24) >> 24);
+ cc.re = (u16) di0;
+ cc.im = (u16) dq0;
+ break;
+ case 3:
+ wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq);
+ cc.re = (u16) ei;
+ cc.im = (u16) eq;
+ break;
+ case 4:
+ wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq);
+ cc.re = (u16) fi;
+ cc.im = (u16) fq;
+ break;
+ }
+ return cc;
+}
+
+static void
+wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
+{
+ const lcnphy_spb_tone_t *phy_c1;
+ lcnphy_spb_tone_t phy_c2;
+ lcnphy_unsign16_struct phy_c3;
+ int phy_c4, phy_c5, k, l, j, phy_c6;
+ u16 phy_c7, phy_c8, phy_c9;
+ s16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16;
+ s16 *ptr, phy_c17;
+ s32 phy_c18, phy_c19;
+ u32 phy_c20, phy_c21;
+ bool phy_c22, phy_c23, phy_c24, phy_c25;
+ u16 phy_c26, phy_c27;
+ u16 phy_c28, phy_c29, phy_c30;
+ u16 phy_c31;
+ u16 *phy_c32;
+ phy_c21 = 0;
+ phy_c10 = phy_c13 = phy_c14 = phy_c8 = 0;
+ ptr = kmalloc(sizeof(s16) * 131, GFP_ATOMIC);
+ if (NULL == ptr) {
+ return;
+ }
+
+ phy_c32 = kmalloc(sizeof(u16) * 20, GFP_ATOMIC);
+ if (NULL == phy_c32) {
+ kfree(ptr);
+ return;
+ }
+ phy_c26 = read_phy_reg(pi, 0x6da);
+ phy_c27 = read_phy_reg(pi, 0x6db);
+ phy_c31 = read_radio_reg(pi, RADIO_2064_REG026);
+ write_phy_reg(pi, 0x93d, 0xC0);
+
+ wlc_lcnphy_start_tx_tone(pi, 3750, 88, 0);
+ write_phy_reg(pi, 0x6da, 0xffff);
+ or_phy_reg(pi, 0x6db, 0x3);
+
+ wlc_lcnphy_tx_iqlo_loopback(pi, phy_c32);
+ udelay(500);
+ phy_c28 = read_phy_reg(pi, 0x938);
+ phy_c29 = read_phy_reg(pi, 0x4d7);
+ phy_c30 = read_phy_reg(pi, 0x4d8);
+ or_phy_reg(pi, 0x938, 0x1 << 2);
+ or_phy_reg(pi, 0x4d7, 0x1 << 2);
+ or_phy_reg(pi, 0x4d7, 0x1 << 3);
+ mod_phy_reg(pi, 0x4d7, (0x7 << 12), 0x2 << 12);
+ or_phy_reg(pi, 0x4d8, 1 << 0);
+ or_phy_reg(pi, 0x4d8, 1 << 1);
+ mod_phy_reg(pi, 0x4d8, (0x3ff << 2), 0x23A << 2);
+ mod_phy_reg(pi, 0x4d8, (0x7 << 12), 0x7 << 12);
+ phy_c1 = &lcnphy_spb_tone_3750[0];
+ phy_c4 = 32;
+
+ if (num_levels == 0) {
+ if (cal_type != 0) {
+ num_levels = 4;
+ } else {
+ num_levels = 9;
+ }
+ }
+ if (step_size_lg2 == 0) {
+ if (cal_type != 0) {
+ step_size_lg2 = 3;
+ } else {
+ step_size_lg2 = 8;
+ }
+ }
+
+ phy_c7 = (1 << step_size_lg2);
+ phy_c3 = wlc_lcnphy_get_cc(pi, cal_type);
+ phy_c15 = (s16) phy_c3.re;
+ phy_c16 = (s16) phy_c3.im;
+ if (cal_type == 2) {
+ if (phy_c3.re > 127)
+ phy_c15 = phy_c3.re - 256;
+ if (phy_c3.im > 127)
+ phy_c16 = phy_c3.im - 256;
+ }
+ wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
+ udelay(20);
+ for (phy_c8 = 0; phy_c7 != 0 && phy_c8 < num_levels; phy_c8++) {
+ phy_c23 = 1;
+ phy_c22 = 0;
+ switch (cal_type) {
+ case 0:
+ phy_c10 = 511;
+ break;
+ case 2:
+ phy_c10 = 127;
+ break;
+ case 3:
+ phy_c10 = 15;
+ break;
+ case 4:
+ phy_c10 = 15;
+ break;
+ }
+
+ phy_c9 = read_phy_reg(pi, 0x93d);
+ phy_c9 = 2 * phy_c9;
+ phy_c24 = 0;
+ phy_c5 = 7;
+ phy_c25 = 1;
+ while (1) {
+ write_radio_reg(pi, RADIO_2064_REG026,
+ (phy_c5 & 0x7) | ((phy_c5 & 0x7) << 4));
+ udelay(50);
+ phy_c22 = 0;
+ ptr[130] = 0;
+ wlc_lcnphy_samp_cap(pi, 1, phy_c9, &ptr[0], 2);
+ if (ptr[130] == 1)
+ phy_c22 = 1;
+ if (phy_c22)
+ phy_c5 -= 1;
+ if ((phy_c22 != phy_c24) && (!phy_c25))
+ break;
+ if (!phy_c22)
+ phy_c5 += 1;
+ if (phy_c5 <= 0 || phy_c5 >= 7)
+ break;
+ phy_c24 = phy_c22;
+ phy_c25 = 0;
+ }
+
+ if (phy_c5 < 0)
+ phy_c5 = 0;
+ else if (phy_c5 > 7)
+ phy_c5 = 7;
+
+ for (k = -phy_c7; k <= phy_c7; k += phy_c7) {
+ for (l = -phy_c7; l <= phy_c7; l += phy_c7) {
+ phy_c11 = phy_c15 + k;
+ phy_c12 = phy_c16 + l;
+
+ if (phy_c11 < -phy_c10)
+ phy_c11 = -phy_c10;
+ else if (phy_c11 > phy_c10)
+ phy_c11 = phy_c10;
+ if (phy_c12 < -phy_c10)
+ phy_c12 = -phy_c10;
+ else if (phy_c12 > phy_c10)
+ phy_c12 = phy_c10;
+ wlc_lcnphy_set_cc(pi, cal_type, phy_c11,
+ phy_c12);
+ udelay(20);
+ wlc_lcnphy_samp_cap(pi, 0, 0, ptr, 2);
+
+ phy_c18 = 0;
+ phy_c19 = 0;
+ for (j = 0; j < 128; j++) {
+ if (cal_type != 0) {
+ phy_c6 = j % phy_c4;
+ } else {
+ phy_c6 = (2 * j) % phy_c4;
+ }
+ phy_c2.re = phy_c1[phy_c6].re;
+ phy_c2.im = phy_c1[phy_c6].im;
+ phy_c17 = ptr[j];
+ phy_c18 = phy_c18 + phy_c17 * phy_c2.re;
+ phy_c19 = phy_c19 + phy_c17 * phy_c2.im;
+ }
+
+ phy_c18 = phy_c18 >> 10;
+ phy_c19 = phy_c19 >> 10;
+ phy_c20 =
+ ((phy_c18 * phy_c18) + (phy_c19 * phy_c19));
+
+ if (phy_c23 || phy_c20 < phy_c21) {
+ phy_c21 = phy_c20;
+ phy_c13 = phy_c11;
+ phy_c14 = phy_c12;
+ }
+ phy_c23 = 0;
+ }
+ }
+ phy_c23 = 1;
+ phy_c15 = phy_c13;
+ phy_c16 = phy_c14;
+ phy_c7 = phy_c7 >> 1;
+ wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
+ udelay(20);
+ }
+ goto cleanup;
+ cleanup:
+ wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, phy_c32);
+ wlc_lcnphy_stop_tx_tone(pi);
+ write_phy_reg(pi, 0x6da, phy_c26);
+ write_phy_reg(pi, 0x6db, phy_c27);
+ write_phy_reg(pi, 0x938, phy_c28);
+ write_phy_reg(pi, 0x4d7, phy_c29);
+ write_phy_reg(pi, 0x4d8, phy_c30);
+ write_radio_reg(pi, RADIO_2064_REG026, phy_c31);
+
+ kfree(phy_c32);
+ kfree(ptr);
+}
+
+static void
+wlc_lcnphy_tx_iqlo_loopback_cleanup(phy_info_t *pi, u16 *values_to_save)
+{
+ int i;
+
+ and_phy_reg(pi, 0x44c, 0x0 >> 11);
+
+ and_phy_reg(pi, 0x43b, 0xC);
+
+ for (i = 0; i < 20; i++) {
+ write_radio_reg(pi, iqlo_loopback_rf_regs[i],
+ values_to_save[i]);
+ }
+}
+
+static void
+WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi,
+ const lcnphy_tx_gain_tbl_entry *
+ gain_table) {
+ u32 j;
+ phytbl_info_t tab;
+ u32 val;
+ u16 pa_gain;
+ u16 gm_gain;
+
+ if (CHSPEC_IS5G(pi->radio_chanspec))
+ pa_gain = 0x70;
+ else
+ pa_gain = 0x70;
+
+ if (pi->sh->boardflags & BFL_FEM)
+ pa_gain = 0x10;
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_len = 1;
+ tab.tbl_ptr = &val;
+
+ for (j = 0; j < 128; j++) {
+ gm_gain = gain_table[j].gm;
+ val = (((u32) pa_gain << 24) |
+ (gain_table[j].pad << 16) |
+ (gain_table[j].pga << 8) | gm_gain);
+
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + j;
+ wlc_lcnphy_write_table(pi, &tab);
+
+ val = (gain_table[j].dac << 28) | (gain_table[j].bb_mult << 20);
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + j;
+ wlc_lcnphy_write_table(pi, &tab);
+ }
+}
+
+static void wlc_lcnphy_load_rfpower(phy_info_t *pi)
+{
+ phytbl_info_t tab;
+ u32 val, bbmult, rfgain;
+ u8 index;
+ u8 scale_factor = 1;
+ s16 temp, temp1, temp2, qQ, qQ1, qQ2, shift;
+
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_len = 1;
+
+ for (index = 0; index < 128; index++) {
+ tab.tbl_ptr = &bbmult;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + index;
+ wlc_lcnphy_read_table(pi, &tab);
+ bbmult = bbmult >> 20;
+
+ tab.tbl_ptr = &rfgain;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + index;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ qm_log10((s32) (bbmult), 0, &temp1, &qQ1);
+ qm_log10((s32) (1 << 6), 0, &temp2, &qQ2);
+
+ if (qQ1 < qQ2) {
+ temp2 = qm_shr16(temp2, qQ2 - qQ1);
+ qQ = qQ1;
+ } else {
+ temp1 = qm_shr16(temp1, qQ1 - qQ2);
+ qQ = qQ2;
+ }
+ temp = qm_sub16(temp1, temp2);
+
+ if (qQ >= 4)
+ shift = qQ - 4;
+ else
+ shift = 4 - qQ;
+
+ val = (((index << shift) + (5 * temp) +
+ (1 << (scale_factor + shift - 3))) >> (scale_factor +
+ shift - 2));
+
+ tab.tbl_ptr = &val;
+ tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index;
+ wlc_lcnphy_write_table(pi, &tab);
+ }
+}
+
+static void WLBANDINITFN(wlc_lcnphy_tbl_init) (phy_info_t *pi)
+{
+ uint idx;
+ u8 phybw40;
+ phytbl_info_t tab;
+ u32 val;
+
+ phybw40 = CHSPEC_IS40(pi->radio_chanspec);
+
+ for (idx = 0; idx < dot11lcnphytbl_info_sz_rev0; idx++) {
+ wlc_lcnphy_write_table(pi, &dot11lcnphytbl_info_rev0[idx]);
+ }
+
+ if (pi->sh->boardflags & BFL_FEM_BT) {
+ tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
+ tab.tbl_width = 16;
+ tab.tbl_ptr = &val;
+ tab.tbl_len = 1;
+ val = 100;
+ tab.tbl_offset = 4;
+ wlc_lcnphy_write_table(pi, &tab);
+ }
+
+ tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
+ tab.tbl_width = 16;
+ tab.tbl_ptr = &val;
+ tab.tbl_len = 1;
+
+ val = 114;
+ tab.tbl_offset = 0;
+ wlc_lcnphy_write_table(pi, &tab);
+
+ val = 130;
+ tab.tbl_offset = 1;
+ wlc_lcnphy_write_table(pi, &tab);
+
+ val = 6;
+ tab.tbl_offset = 8;
+ wlc_lcnphy_write_table(pi, &tab);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (pi->sh->boardflags & BFL_FEM)
+ wlc_lcnphy_load_tx_gain_table(pi,
+ dot11lcnphy_2GHz_extPA_gaintable_rev0);
+ else
+ wlc_lcnphy_load_tx_gain_table(pi,
+ dot11lcnphy_2GHz_gaintable_rev0);
+ }
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ for (idx = 0;
+ idx < dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
+ idx++)
+ if (pi->sh->boardflags & BFL_EXTLNA)
+ wlc_lcnphy_write_table(pi,
+ &dot11lcnphytbl_rx_gain_info_extlna_2G_rev2
+ [idx]);
+ else
+ wlc_lcnphy_write_table(pi,
+ &dot11lcnphytbl_rx_gain_info_2G_rev2
+ [idx]);
+ } else {
+ for (idx = 0;
+ idx < dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
+ idx++)
+ if (pi->sh->boardflags & BFL_EXTLNA_5GHz)
+ wlc_lcnphy_write_table(pi,
+ &dot11lcnphytbl_rx_gain_info_extlna_5G_rev2
+ [idx]);
+ else
+ wlc_lcnphy_write_table(pi,
+ &dot11lcnphytbl_rx_gain_info_5G_rev2
+ [idx]);
+ }
+ }
+
+ if ((pi->sh->boardflags & BFL_FEM)
+ && !(pi->sh->boardflags & BFL_FEM_BT))
+ wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313_epa);
+ else if (pi->sh->boardflags & BFL_FEM_BT) {
+ if (pi->sh->boardrev < 0x1250)
+ wlc_lcnphy_write_table(pi,
+ &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa);
+ else
+ wlc_lcnphy_write_table(pi,
+ &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250);
+ } else
+ wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313);
+
+ wlc_lcnphy_load_rfpower(pi);
+
+ wlc_lcnphy_clear_papd_comptable(pi);
+}
+
+static void WLBANDINITFN(wlc_lcnphy_rev0_baseband_init) (phy_info_t *pi)
+{
+ u16 afectrl1;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ write_radio_reg(pi, RADIO_2064_REG11C, 0x0);
+
+ write_phy_reg(pi, 0x43b, 0x0);
+ write_phy_reg(pi, 0x43c, 0x0);
+ write_phy_reg(pi, 0x44c, 0x0);
+ write_phy_reg(pi, 0x4e6, 0x0);
+ write_phy_reg(pi, 0x4f9, 0x0);
+ write_phy_reg(pi, 0x4b0, 0x0);
+ write_phy_reg(pi, 0x938, 0x0);
+ write_phy_reg(pi, 0x4b0, 0x0);
+ write_phy_reg(pi, 0x44e, 0);
+
+ or_phy_reg(pi, 0x567, 0x03);
+
+ or_phy_reg(pi, 0x44a, 0x44);
+ write_phy_reg(pi, 0x44a, 0x80);
+
+ if (!(pi->sh->boardflags & BFL_FEM))
+ wlc_lcnphy_set_tx_pwr_by_index(pi, 52);
+
+ if (0) {
+ afectrl1 = 0;
+ afectrl1 = (u16) ((pi_lcn->lcnphy_rssi_vf) |
+ (pi_lcn->lcnphy_rssi_vc << 4) | (pi_lcn->
+ lcnphy_rssi_gs
+ << 10));
+ write_phy_reg(pi, 0x43e, afectrl1);
+ }
+
+ mod_phy_reg(pi, 0x634, (0xff << 0), 0xC << 0);
+ if (pi->sh->boardflags & BFL_FEM) {
+ mod_phy_reg(pi, 0x634, (0xff << 0), 0xA << 0);
+
+ write_phy_reg(pi, 0x910, 0x1);
+ }
+
+ mod_phy_reg(pi, 0x448, (0x3 << 8), 1 << 8);
+ mod_phy_reg(pi, 0x608, (0xff << 0), 0x17 << 0);
+ mod_phy_reg(pi, 0x604, (0x7ff << 0), 0x3EA << 0);
+
+}
+
+static void WLBANDINITFN(wlc_lcnphy_rev2_baseband_init) (phy_info_t *pi)
+{
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ mod_phy_reg(pi, 0x416, (0xff << 0), 80 << 0);
+
+ mod_phy_reg(pi, 0x416, (0xff << 8), 80 << 8);
+ }
+}
+
+static void wlc_lcnphy_agc_temp_init(phy_info_t *pi)
+{
+ s16 temp;
+ phytbl_info_t tab;
+ u32 tableBuffer[2];
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ temp = (s16) read_phy_reg(pi, 0x4df);
+ pi_lcn->lcnphy_ofdmgainidxtableoffset = (temp & (0xff << 0)) >> 0;
+
+ if (pi_lcn->lcnphy_ofdmgainidxtableoffset > 127)
+ pi_lcn->lcnphy_ofdmgainidxtableoffset -= 256;
+
+ pi_lcn->lcnphy_dsssgainidxtableoffset = (temp & (0xff << 8)) >> 8;
+
+ if (pi_lcn->lcnphy_dsssgainidxtableoffset > 127)
+ pi_lcn->lcnphy_dsssgainidxtableoffset -= 256;
+
+ tab.tbl_ptr = tableBuffer;
+ tab.tbl_len = 2;
+ tab.tbl_id = 17;
+ tab.tbl_offset = 59;
+ tab.tbl_width = 32;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ if (tableBuffer[0] > 63)
+ tableBuffer[0] -= 128;
+ pi_lcn->lcnphy_tr_R_gain_val = tableBuffer[0];
+
+ if (tableBuffer[1] > 63)
+ tableBuffer[1] -= 128;
+ pi_lcn->lcnphy_tr_T_gain_val = tableBuffer[1];
+
+ temp = (s16) (read_phy_reg(pi, 0x434)
+ & (0xff << 0));
+ if (temp > 127)
+ temp -= 256;
+ pi_lcn->lcnphy_input_pwr_offset_db = (s8) temp;
+
+ pi_lcn->lcnphy_Med_Low_Gain_db = (read_phy_reg(pi, 0x424)
+ & (0xff << 8))
+ >> 8;
+ pi_lcn->lcnphy_Very_Low_Gain_db = (read_phy_reg(pi, 0x425)
+ & (0xff << 0))
+ >> 0;
+
+ tab.tbl_ptr = tableBuffer;
+ tab.tbl_len = 2;
+ tab.tbl_id = LCNPHY_TBL_ID_GAIN_IDX;
+ tab.tbl_offset = 28;
+ tab.tbl_width = 32;
+ wlc_lcnphy_read_table(pi, &tab);
+
+ pi_lcn->lcnphy_gain_idx_14_lowword = tableBuffer[0];
+ pi_lcn->lcnphy_gain_idx_14_hiword = tableBuffer[1];
+
+}
+
+static void WLBANDINITFN(wlc_lcnphy_bu_tweaks) (phy_info_t *pi)
+{
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ or_phy_reg(pi, 0x805, 0x1);
+
+ mod_phy_reg(pi, 0x42f, (0x7 << 0), (0x3) << 0);
+
+ mod_phy_reg(pi, 0x030, (0x7 << 0), (0x3) << 0);
+
+ write_phy_reg(pi, 0x414, 0x1e10);
+ write_phy_reg(pi, 0x415, 0x0640);
+
+ mod_phy_reg(pi, 0x4df, (0xff << 8), -9 << 8);
+
+ or_phy_reg(pi, 0x44a, 0x44);
+ write_phy_reg(pi, 0x44a, 0x80);
+ mod_phy_reg(pi, 0x434, (0xff << 0), (0xFD) << 0);
+
+ mod_phy_reg(pi, 0x420, (0xff << 0), (16) << 0);
+
+ if (!(pi->sh->boardrev < 0x1204))
+ mod_radio_reg(pi, RADIO_2064_REG09B, 0xF0, 0xF0);
+
+ write_phy_reg(pi, 0x7d6, 0x0902);
+ mod_phy_reg(pi, 0x429, (0xf << 0), (0x9) << 0);
+
+ mod_phy_reg(pi, 0x429, (0x3f << 4), (0xe) << 4);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
+ mod_phy_reg(pi, 0x423, (0xff << 0), (0x46) << 0);
+
+ mod_phy_reg(pi, 0x411, (0xff << 0), (1) << 0);
+
+ mod_phy_reg(pi, 0x434, (0xff << 0), (0xFF) << 0);
+
+ mod_phy_reg(pi, 0x656, (0xf << 0), (2) << 0);
+
+ mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
+
+ mod_radio_reg(pi, RADIO_2064_REG0F7, 0x4, 0x4);
+ mod_radio_reg(pi, RADIO_2064_REG0F1, 0x3, 0);
+ mod_radio_reg(pi, RADIO_2064_REG0F2, 0xF8, 0x90);
+ mod_radio_reg(pi, RADIO_2064_REG0F3, 0x3, 0x2);
+ mod_radio_reg(pi, RADIO_2064_REG0F3, 0xf0, 0xa0);
+
+ mod_radio_reg(pi, RADIO_2064_REG11F, 0x2, 0x2);
+
+ wlc_lcnphy_clear_tx_power_offsets(pi);
+ mod_phy_reg(pi, 0x4d0, (0x1ff << 6), (10) << 6);
+
+ }
+}
+
+static void WLBANDINITFN(wlc_lcnphy_baseband_init) (phy_info_t *pi)
+{
+
+ wlc_lcnphy_tbl_init(pi);
+ wlc_lcnphy_rev0_baseband_init(pi);
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2))
+ wlc_lcnphy_rev2_baseband_init(pi);
+ wlc_lcnphy_bu_tweaks(pi);
+}
+
+static void WLBANDINITFN(wlc_radio_2064_init) (phy_info_t *pi)
+{
+ u32 i;
+ lcnphy_radio_regs_t *lcnphyregs = NULL;
+
+ lcnphyregs = lcnphy_radio_regs_2064;
+
+ for (i = 0; lcnphyregs[i].address != 0xffff; i++)
+ if (CHSPEC_IS5G(pi->radio_chanspec) && lcnphyregs[i].do_init_a)
+ write_radio_reg(pi,
+ ((lcnphyregs[i].address & 0x3fff) |
+ RADIO_DEFAULT_CORE),
+ (u16) lcnphyregs[i].init_a);
+ else if (lcnphyregs[i].do_init_g)
+ write_radio_reg(pi,
+ ((lcnphyregs[i].address & 0x3fff) |
+ RADIO_DEFAULT_CORE),
+ (u16) lcnphyregs[i].init_g);
+
+ write_radio_reg(pi, RADIO_2064_REG032, 0x62);
+ write_radio_reg(pi, RADIO_2064_REG033, 0x19);
+
+ write_radio_reg(pi, RADIO_2064_REG090, 0x10);
+
+ write_radio_reg(pi, RADIO_2064_REG010, 0x00);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
+
+ write_radio_reg(pi, RADIO_2064_REG060, 0x7f);
+ write_radio_reg(pi, RADIO_2064_REG061, 0x72);
+ write_radio_reg(pi, RADIO_2064_REG062, 0x7f);
+ }
+
+ write_radio_reg(pi, RADIO_2064_REG01D, 0x02);
+ write_radio_reg(pi, RADIO_2064_REG01E, 0x06);
+
+ mod_phy_reg(pi, 0x4ea, (0x7 << 0), 0 << 0);
+
+ mod_phy_reg(pi, 0x4ea, (0x7 << 3), 1 << 3);
+
+ mod_phy_reg(pi, 0x4ea, (0x7 << 6), 2 << 6);
+
+ mod_phy_reg(pi, 0x4ea, (0x7 << 9), 3 << 9);
+
+ mod_phy_reg(pi, 0x4ea, (0x7 << 12), 4 << 12);
+
+ write_phy_reg(pi, 0x4ea, 0x4688);
+
+ mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
+
+ mod_phy_reg(pi, 0x4eb, (0x7 << 6), 0 << 6);
+
+ mod_phy_reg(pi, 0x46a, (0xffff << 0), 25 << 0);
+
+ wlc_lcnphy_set_tx_locc(pi, 0);
+
+ wlc_lcnphy_rcal(pi);
+
+ wlc_lcnphy_rc_cal(pi);
+}
+
+static void WLBANDINITFN(wlc_lcnphy_radio_init) (phy_info_t *pi)
+{
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ wlc_radio_2064_init(pi);
+}
+
+static void wlc_lcnphy_rcal(phy_info_t *pi)
+{
+ u8 rcal_value;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ and_radio_reg(pi, RADIO_2064_REG05B, 0xfD);
+
+ or_radio_reg(pi, RADIO_2064_REG004, 0x40);
+ or_radio_reg(pi, RADIO_2064_REG120, 0x10);
+
+ or_radio_reg(pi, RADIO_2064_REG078, 0x80);
+ or_radio_reg(pi, RADIO_2064_REG129, 0x02);
+
+ or_radio_reg(pi, RADIO_2064_REG057, 0x01);
+
+ or_radio_reg(pi, RADIO_2064_REG05B, 0x02);
+ mdelay(5);
+ SPINWAIT(!wlc_radio_2064_rcal_done(pi), 10 * 1000 * 1000);
+
+ if (wlc_radio_2064_rcal_done(pi)) {
+ rcal_value = (u8) read_radio_reg(pi, RADIO_2064_REG05C);
+ rcal_value = rcal_value & 0x1f;
+ }
+
+ and_radio_reg(pi, RADIO_2064_REG05B, 0xfD);
+
+ and_radio_reg(pi, RADIO_2064_REG057, 0xFE);
+}
+
+static void wlc_lcnphy_rc_cal(phy_info_t *pi)
+{
+ u8 dflt_rc_cal_val;
+ u16 flt_val;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ dflt_rc_cal_val = 7;
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1))
+ dflt_rc_cal_val = 11;
+ flt_val =
+ (dflt_rc_cal_val << 10) | (dflt_rc_cal_val << 5) |
+ (dflt_rc_cal_val);
+ write_phy_reg(pi, 0x933, flt_val);
+ write_phy_reg(pi, 0x934, flt_val);
+ write_phy_reg(pi, 0x935, flt_val);
+ write_phy_reg(pi, 0x936, flt_val);
+ write_phy_reg(pi, 0x937, (flt_val & 0x1FF));
+
+ return;
+}
+
+static bool wlc_phy_txpwr_srom_read_lcnphy(phy_info_t *pi)
+{
+ s8 txpwr = 0;
+ int i;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ u16 cckpo = 0;
+ u32 offset_ofdm, offset_mcs;
+
+ pi_lcn->lcnphy_tr_isolation_mid =
+ (u8) PHY_GETINTVAR(pi, "triso2g");
+
+ pi_lcn->lcnphy_rx_power_offset =
+ (u8) PHY_GETINTVAR(pi, "rxpo2g");
+
+ pi->txpa_2g[0] = (s16) PHY_GETINTVAR(pi, "pa0b0");
+ pi->txpa_2g[1] = (s16) PHY_GETINTVAR(pi, "pa0b1");
+ pi->txpa_2g[2] = (s16) PHY_GETINTVAR(pi, "pa0b2");
+
+ pi_lcn->lcnphy_rssi_vf = (u8) PHY_GETINTVAR(pi, "rssismf2g");
+ pi_lcn->lcnphy_rssi_vc = (u8) PHY_GETINTVAR(pi, "rssismc2g");
+ pi_lcn->lcnphy_rssi_gs = (u8) PHY_GETINTVAR(pi, "rssisav2g");
+
+ {
+ pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf;
+ pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc;
+ pi_lcn->lcnphy_rssi_gs_lowtemp = pi_lcn->lcnphy_rssi_gs;
+
+ pi_lcn->lcnphy_rssi_vf_hightemp =
+ pi_lcn->lcnphy_rssi_vf;
+ pi_lcn->lcnphy_rssi_vc_hightemp =
+ pi_lcn->lcnphy_rssi_vc;
+ pi_lcn->lcnphy_rssi_gs_hightemp =
+ pi_lcn->lcnphy_rssi_gs;
+ }
+
+ txpwr = (s8) PHY_GETINTVAR(pi, "maxp2ga0");
+ pi->tx_srom_max_2g = txpwr;
+
+ for (i = 0; i < PWRTBL_NUM_COEFF; i++) {
+ pi->txpa_2g_low_temp[i] = pi->txpa_2g[i];
+ pi->txpa_2g_high_temp[i] = pi->txpa_2g[i];
+ }
+
+ cckpo = (u16) PHY_GETINTVAR(pi, "cck2gpo");
+ if (cckpo) {
+ uint max_pwr_chan = txpwr;
+
+ for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++) {
+ pi->tx_srom_max_rate_2g[i] = max_pwr_chan -
+ ((cckpo & 0xf) * 2);
+ cckpo >>= 4;
+ }
+
+ offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
+ for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
+ pi->tx_srom_max_rate_2g[i] = max_pwr_chan -
+ ((offset_ofdm & 0xf) * 2);
+ offset_ofdm >>= 4;
+ }
+ } else {
+ u8 opo = 0;
+
+ opo = (u8) PHY_GETINTVAR(pi, "opo");
+
+ for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++) {
+ pi->tx_srom_max_rate_2g[i] = txpwr;
+ }
+
+ offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
+
+ for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
+ pi->tx_srom_max_rate_2g[i] = txpwr -
+ ((offset_ofdm & 0xf) * 2);
+ offset_ofdm >>= 4;
+ }
+ offset_mcs =
+ ((u16) PHY_GETINTVAR(pi, "mcs2gpo1") << 16) |
+ (u16) PHY_GETINTVAR(pi, "mcs2gpo0");
+ pi_lcn->lcnphy_mcs20_po = offset_mcs;
+ for (i = TXP_FIRST_SISO_MCS_20;
+ i <= TXP_LAST_SISO_MCS_20; i++) {
+ pi->tx_srom_max_rate_2g[i] =
+ txpwr - ((offset_mcs & 0xf) * 2);
+ offset_mcs >>= 4;
+ }
+ }
+
+ pi_lcn->lcnphy_rawtempsense =
+ (u16) PHY_GETINTVAR(pi, "rawtempsense");
+ pi_lcn->lcnphy_measPower =
+ (u8) PHY_GETINTVAR(pi, "measpower");
+ pi_lcn->lcnphy_tempsense_slope =
+ (u8) PHY_GETINTVAR(pi, "tempsense_slope");
+ pi_lcn->lcnphy_hw_iqcal_en =
+ (bool) PHY_GETINTVAR(pi, "hw_iqcal_en");
+ pi_lcn->lcnphy_iqcal_swp_dis =
+ (bool) PHY_GETINTVAR(pi, "iqcal_swp_dis");
+ pi_lcn->lcnphy_tempcorrx =
+ (u8) PHY_GETINTVAR(pi, "tempcorrx");
+ pi_lcn->lcnphy_tempsense_option =
+ (u8) PHY_GETINTVAR(pi, "tempsense_option");
+ pi_lcn->lcnphy_freqoffset_corr =
+ (u8) PHY_GETINTVAR(pi, "freqoffset_corr");
+ if ((u8) getintvar(pi->vars, "aa2g") > 1)
+ wlc_phy_ant_rxdiv_set((wlc_phy_t *) pi,
+ (u8) getintvar(pi->vars,
+ "aa2g"));
+ }
+ pi_lcn->lcnphy_cck_dig_filt_type = -1;
+ if (PHY_GETVAR(pi, "cckdigfilttype")) {
+ s16 temp;
+ temp = (s16) PHY_GETINTVAR(pi, "cckdigfilttype");
+ if (temp >= 0) {
+ pi_lcn->lcnphy_cck_dig_filt_type = temp;
+ }
+ }
+
+ return true;
+}
+
+void wlc_2064_vco_cal(phy_info_t *pi)
+{
+ u8 calnrst;
+
+ mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 1 << 3);
+ calnrst = (u8) read_radio_reg(pi, RADIO_2064_REG056) & 0xf8;
+ write_radio_reg(pi, RADIO_2064_REG056, calnrst);
+ udelay(1);
+ write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x03);
+ udelay(1);
+ write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x07);
+ udelay(300);
+ mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 0);
+}
+
+static void
+wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi, u8 channel)
+{
+ uint i;
+ const chan_info_2064_lcnphy_t *ci;
+ u8 rfpll_doubler = 0;
+ u8 pll_pwrup, pll_pwrup_ovr;
+ fixed qFxtal, qFref, qFvco, qFcal;
+ u8 d15, d16, f16, e44, e45;
+ u32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div;
+ u16 loop_bw, d30, setCount;
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+ ci = &chan_info_2064_lcnphy[0];
+ rfpll_doubler = 1;
+
+ mod_radio_reg(pi, RADIO_2064_REG09D, 0x4, 0x1 << 2);
+
+ write_radio_reg(pi, RADIO_2064_REG09E, 0xf);
+ if (!rfpll_doubler) {
+ loop_bw = PLL_2064_LOOP_BW;
+ d30 = PLL_2064_D30;
+ } else {
+ loop_bw = PLL_2064_LOOP_BW_DOUBLER;
+ d30 = PLL_2064_D30_DOUBLER;
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ for (i = 0; i < ARRAY_SIZE(chan_info_2064_lcnphy); i++)
+ if (chan_info_2064_lcnphy[i].chan == channel)
+ break;
+
+ if (i >= ARRAY_SIZE(chan_info_2064_lcnphy)) {
+ return;
+ }
+
+ ci = &chan_info_2064_lcnphy[i];
+ }
+
+ write_radio_reg(pi, RADIO_2064_REG02A, ci->logen_buftune);
+
+ mod_radio_reg(pi, RADIO_2064_REG030, 0x3, ci->logen_rccr_tx);
+
+ mod_radio_reg(pi, RADIO_2064_REG091, 0x3, ci->txrf_mix_tune_ctrl);
+
+ mod_radio_reg(pi, RADIO_2064_REG038, 0xf, ci->pa_input_tune_g);
+
+ mod_radio_reg(pi, RADIO_2064_REG030, 0x3 << 2,
+ (ci->logen_rccr_rx) << 2);
+
+ mod_radio_reg(pi, RADIO_2064_REG05E, 0xf, ci->pa_rxrf_lna1_freq_tune);
+
+ mod_radio_reg(pi, RADIO_2064_REG05E, (0xf) << 4,
+ (ci->pa_rxrf_lna2_freq_tune) << 4);
+
+ write_radio_reg(pi, RADIO_2064_REG06C, ci->rxrf_rxrf_spare1);
+
+ pll_pwrup = (u8) read_radio_reg(pi, RADIO_2064_REG044);
+ pll_pwrup_ovr = (u8) read_radio_reg(pi, RADIO_2064_REG12B);
+
+ or_radio_reg(pi, RADIO_2064_REG044, 0x07);
+
+ or_radio_reg(pi, RADIO_2064_REG12B, (0x07) << 1);
+ e44 = 0;
+ e45 = 0;
+
+ fpfd = rfpll_doubler ? (pi->xtalfreq << 1) : (pi->xtalfreq);
+ if (pi->xtalfreq > 26000000)
+ e44 = 1;
+ if (pi->xtalfreq > 52000000)
+ e45 = 1;
+ if (e44 == 0)
+ fcal_div = 1;
+ else if (e45 == 0)
+ fcal_div = 2;
+ else
+ fcal_div = 4;
+ fvco3 = (ci->freq * 3);
+ fref3 = 2 * fpfd;
+
+ qFxtal = wlc_lcnphy_qdiv_roundup(pi->xtalfreq, PLL_2064_MHZ, 16);
+ qFref = wlc_lcnphy_qdiv_roundup(fpfd, PLL_2064_MHZ, 16);
+ qFcal = pi->xtalfreq * fcal_div / PLL_2064_MHZ;
+ qFvco = wlc_lcnphy_qdiv_roundup(fvco3, 2, 16);
+
+ write_radio_reg(pi, RADIO_2064_REG04F, 0x02);
+
+ d15 = (pi->xtalfreq * fcal_div * 4 / 5) / PLL_2064_MHZ - 1;
+ write_radio_reg(pi, RADIO_2064_REG052, (0x07 & (d15 >> 2)));
+ write_radio_reg(pi, RADIO_2064_REG053, (d15 & 0x3) << 5);
+
+ d16 = (qFcal * 8 / (d15 + 1)) - 1;
+ write_radio_reg(pi, RADIO_2064_REG051, d16);
+
+ f16 = ((d16 + 1) * (d15 + 1)) / qFcal;
+ setCount = f16 * 3 * (ci->freq) / 32 - 1;
+ mod_radio_reg(pi, RADIO_2064_REG053, (0x0f << 0),
+ (u8) (setCount >> 8));
+
+ or_radio_reg(pi, RADIO_2064_REG053, 0x10);
+ write_radio_reg(pi, RADIO_2064_REG054, (u8) (setCount & 0xff));
+
+ div_int = ((fvco3 * (PLL_2064_MHZ >> 4)) / fref3) << 4;
+
+ div_frac = ((fvco3 * (PLL_2064_MHZ >> 4)) % fref3) << 4;
+ while (div_frac >= fref3) {
+ div_int++;
+ div_frac -= fref3;
+ }
+ div_frac = wlc_lcnphy_qdiv_roundup(div_frac, fref3, 20);
+
+ mod_radio_reg(pi, RADIO_2064_REG045, (0x1f << 0),
+ (u8) (div_int >> 4));
+ mod_radio_reg(pi, RADIO_2064_REG046, (0x1f << 4),
+ (u8) (div_int << 4));
+ mod_radio_reg(pi, RADIO_2064_REG046, (0x0f << 0),
+ (u8) (div_frac >> 16));
+ write_radio_reg(pi, RADIO_2064_REG047, (u8) (div_frac >> 8) & 0xff);
+ write_radio_reg(pi, RADIO_2064_REG048, (u8) div_frac & 0xff);
+
+ write_radio_reg(pi, RADIO_2064_REG040, 0xfb);
+
+ write_radio_reg(pi, RADIO_2064_REG041, 0x9A);
+ write_radio_reg(pi, RADIO_2064_REG042, 0xA3);
+ write_radio_reg(pi, RADIO_2064_REG043, 0x0C);
+
+ {
+ u8 h29, h23, c28, d29, h28_ten, e30, h30_ten, cp_current;
+ u16 c29, c38, c30, g30, d28;
+ c29 = loop_bw;
+ d29 = 200;
+ c38 = 1250;
+ h29 = d29 / c29;
+ h23 = 1;
+ c28 = 30;
+ d28 = (((PLL_2064_HIGH_END_KVCO - PLL_2064_LOW_END_KVCO) *
+ (fvco3 / 2 - PLL_2064_LOW_END_VCO)) /
+ (PLL_2064_HIGH_END_VCO - PLL_2064_LOW_END_VCO))
+ + PLL_2064_LOW_END_KVCO;
+ h28_ten = (d28 * 10) / c28;
+ c30 = 2640;
+ e30 = (d30 - 680) / 490;
+ g30 = 680 + (e30 * 490);
+ h30_ten = (g30 * 10) / c30;
+ cp_current = ((c38 * h29 * h23 * 100) / h28_ten) / h30_ten;
+ mod_radio_reg(pi, RADIO_2064_REG03C, 0x3f, cp_current);
+ }
+ if (channel >= 1 && channel <= 5)
+ write_radio_reg(pi, RADIO_2064_REG03C, 0x8);
+ else
+ write_radio_reg(pi, RADIO_2064_REG03C, 0x7);
+ write_radio_reg(pi, RADIO_2064_REG03D, 0x3);
+
+ mod_radio_reg(pi, RADIO_2064_REG044, 0x0c, 0x0c);
+ udelay(1);
+
+ wlc_2064_vco_cal(pi);
+
+ write_radio_reg(pi, RADIO_2064_REG044, pll_pwrup);
+ write_radio_reg(pi, RADIO_2064_REG12B, pll_pwrup_ovr);
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
+ write_radio_reg(pi, RADIO_2064_REG038, 3);
+ write_radio_reg(pi, RADIO_2064_REG091, 7);
+ }
+}
+
+bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi)
+{
+ if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
+ return 0;
+ else
+ return (LCNPHY_TX_PWR_CTRL_HW ==
+ wlc_lcnphy_get_tx_pwr_ctrl((pi)));
+}
+
+void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi)
+{
+ u16 pwr_ctrl;
+ if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
+ wlc_lcnphy_calib_modes(pi, LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
+ } else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) {
+
+ pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
+ wlc_lcnphy_txpower_recalc_target(pi);
+
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, pwr_ctrl);
+ } else
+ return;
+}
+
+void wlc_phy_detach_lcnphy(phy_info_t *pi)
+{
+ kfree(pi->u.pi_lcnphy);
+}
+
+bool wlc_phy_attach_lcnphy(phy_info_t *pi)
+{
+ phy_info_lcnphy_t *pi_lcn;
+
+ pi->u.pi_lcnphy = kzalloc(sizeof(phy_info_lcnphy_t), GFP_ATOMIC);
+ if (pi->u.pi_lcnphy == NULL) {
+ return false;
+ }
+
+ pi_lcn = pi->u.pi_lcnphy;
+
+ if ((0 == (pi->sh->boardflags & BFL_NOPA)) && !NORADIO_ENAB(pi->pubpi)) {
+ pi->hwpwrctrl = true;
+ pi->hwpwrctrl_capable = true;
+ }
+
+ pi->xtalfreq = si_pmu_alp_clock(pi->sh->sih);
+ pi_lcn->lcnphy_papd_rxGnCtrl_init = 0;
+
+ pi->pi_fptr.init = wlc_phy_init_lcnphy;
+ pi->pi_fptr.calinit = wlc_phy_cal_init_lcnphy;
+ pi->pi_fptr.chanset = wlc_phy_chanspec_set_lcnphy;
+ pi->pi_fptr.txpwrrecalc = wlc_phy_txpower_recalc_target_lcnphy;
+ pi->pi_fptr.txiqccget = wlc_lcnphy_get_tx_iqcc;
+ pi->pi_fptr.txiqccset = wlc_lcnphy_set_tx_iqcc;
+ pi->pi_fptr.txloccget = wlc_lcnphy_get_tx_locc;
+ pi->pi_fptr.radioloftget = wlc_lcnphy_get_radio_loft;
+ pi->pi_fptr.detach = wlc_phy_detach_lcnphy;
+
+ if (!wlc_phy_txpwr_srom_read_lcnphy(pi))
+ return false;
+
+ if ((pi->sh->boardflags & BFL_FEM) && (LCNREV_IS(pi->pubpi.phy_rev, 1))) {
+ if (pi_lcn->lcnphy_tempsense_option == 3) {
+ pi->hwpwrctrl = true;
+ pi->hwpwrctrl_capable = true;
+ pi->temppwrctrl_capable = false;
+ } else {
+ pi->hwpwrctrl = false;
+ pi->hwpwrctrl_capable = false;
+ pi->temppwrctrl_capable = true;
+ }
+ }
+
+ return true;
+}
+
+static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, u32 gain)
+{
+ u16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19;
+
+ trsw = (gain & ((u32) 1 << 28)) ? 0 : 1;
+ ext_lna = (u16) (gain >> 29) & 0x01;
+ lna1 = (u16) (gain >> 0) & 0x0f;
+ lna2 = (u16) (gain >> 4) & 0x0f;
+ tia = (u16) (gain >> 8) & 0xf;
+ biq0 = (u16) (gain >> 12) & 0xf;
+ biq1 = (u16) (gain >> 16) & 0xf;
+
+ gain0_15 = (u16) ((lna1 & 0x3) | ((lna1 & 0x3) << 2) |
+ ((lna2 & 0x3) << 4) | ((lna2 & 0x3) << 6) |
+ ((tia & 0xf) << 8) | ((biq0 & 0xf) << 12));
+ gain16_19 = biq1;
+
+ mod_phy_reg(pi, 0x44d, (0x1 << 0), trsw << 0);
+ mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
+ mod_phy_reg(pi, 0x4b1, (0x1 << 10), ext_lna << 10);
+ mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
+ mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
+ mod_phy_reg(pi, 0x4e6, (0x3 << 3), lna1 << 3);
+ }
+ wlc_lcnphy_rx_gain_override_enable(pi, true);
+}
+
+static u32 wlc_lcnphy_get_receive_power(phy_info_t *pi, s32 *gain_index)
+{
+ u32 received_power = 0;
+ s32 max_index = 0;
+ u32 gain_code = 0;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ max_index = 36;
+ if (*gain_index >= 0)
+ gain_code = lcnphy_23bitgaincode_table[*gain_index];
+
+ if (-1 == *gain_index) {
+ *gain_index = 0;
+ while ((*gain_index <= (s32) max_index)
+ && (received_power < 700)) {
+ wlc_lcnphy_set_rx_gain(pi,
+ lcnphy_23bitgaincode_table
+ [*gain_index]);
+ received_power =
+ wlc_lcnphy_measure_digital_power(pi,
+ pi_lcn->
+ lcnphy_noise_samples);
+ (*gain_index)++;
+ }
+ (*gain_index)--;
+ } else {
+ wlc_lcnphy_set_rx_gain(pi, gain_code);
+ received_power =
+ wlc_lcnphy_measure_digital_power(pi,
+ pi_lcn->
+ lcnphy_noise_samples);
+ }
+
+ return received_power;
+}
+
+s32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, s32 gain_index)
+{
+ s32 gain = 0;
+ s32 nominal_power_db;
+ s32 log_val, gain_mismatch, desired_gain, input_power_offset_db,
+ input_power_db;
+ s32 received_power, temperature;
+ uint freq;
+ phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
+
+ received_power = wlc_lcnphy_get_receive_power(pi, &gain_index);
+
+ gain = lcnphy_gain_table[gain_index];
+
+ nominal_power_db = read_phy_reg(pi, 0x425) >> 8;
+
+ {
+ u32 power = (received_power * 16);
+ u32 msb1, msb2, val1, val2, diff1, diff2;
+ msb1 = ffs(power) - 1;
+ msb2 = msb1 + 1;
+ val1 = 1 << msb1;
+ val2 = 1 << msb2;
+ diff1 = (power - val1);
+ diff2 = (val2 - power);
+ if (diff1 < diff2)
+ log_val = msb1;
+ else
+ log_val = msb2;
+ }
+
+ log_val = log_val * 3;
+
+ gain_mismatch = (nominal_power_db / 2) - (log_val);
+
+ desired_gain = gain + gain_mismatch;
+
+ input_power_offset_db = read_phy_reg(pi, 0x434) & 0xFF;
+
+ if (input_power_offset_db > 127)
+ input_power_offset_db -= 256;
+
+ input_power_db = input_power_offset_db - desired_gain;
+
+ input_power_db =
+ input_power_db + lcnphy_gain_index_offset_for_rssi[gain_index];
+
+ freq = wlc_phy_channel2freq(CHSPEC_CHANNEL(pi->radio_chanspec));
+ if ((freq > 2427) && (freq <= 2467))
+ input_power_db = input_power_db - 1;
+
+ temperature = pi_lcn->lcnphy_lastsensed_temperature;
+
+ if ((temperature - 15) < -30) {
+ input_power_db =
+ input_power_db + (((temperature - 10 - 25) * 286) >> 12) -
+ 7;
+ } else if ((temperature - 15) < 4) {
+ input_power_db =
+ input_power_db + (((temperature - 10 - 25) * 286) >> 12) -
+ 3;
+ } else {
+ input_power_db =
+ input_power_db + (((temperature - 10 - 25) * 286) >> 12);
+ }
+
+ wlc_lcnphy_rx_gain_override_enable(pi, 0);
+
+ return input_power_db;
+}
+
+static int
+wlc_lcnphy_load_tx_iir_filter(phy_info_t *pi, bool is_ofdm, s16 filt_type)
+{
+ s16 filt_index = -1;
+ int j;
+
+ u16 addr[] = {
+ 0x910,
+ 0x91e,
+ 0x91f,
+ 0x924,
+ 0x925,
+ 0x926,
+ 0x920,
+ 0x921,
+ 0x927,
+ 0x928,
+ 0x929,
+ 0x922,
+ 0x923,
+ 0x930,
+ 0x931,
+ 0x932
+ };
+
+ u16 addr_ofdm[] = {
+ 0x90f,
+ 0x900,
+ 0x901,
+ 0x906,
+ 0x907,
+ 0x908,
+ 0x902,
+ 0x903,
+ 0x909,
+ 0x90a,
+ 0x90b,
+ 0x904,
+ 0x905,
+ 0x90c,
+ 0x90d,
+ 0x90e
+ };
+
+ if (!is_ofdm) {
+ for (j = 0; j < LCNPHY_NUM_TX_DIG_FILTERS_CCK; j++) {
+ if (filt_type == LCNPHY_txdigfiltcoeffs_cck[j][0]) {
+ filt_index = (s16) j;
+ break;
+ }
+ }
+
+ if (filt_index != -1) {
+ for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, addr[j],
+ LCNPHY_txdigfiltcoeffs_cck
+ [filt_index][j + 1]);
+ }
+ }
+ } else {
+ for (j = 0; j < LCNPHY_NUM_TX_DIG_FILTERS_OFDM; j++) {
+ if (filt_type == LCNPHY_txdigfiltcoeffs_ofdm[j][0]) {
+ filt_index = (s16) j;
+ break;
+ }
+ }
+
+ if (filt_index != -1) {
+ for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, addr_ofdm[j],
+ LCNPHY_txdigfiltcoeffs_ofdm
+ [filt_index][j + 1]);
+ }
+ }
+ }
+
+ return (filt_index != -1) ? 0 : -1;
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_PHY_LCN_H_
+#define _BRCM_PHY_LCN_H_
+
+struct phy_info_lcnphy {
+ int lcnphy_txrf_sp_9_override;
+ u8 lcnphy_full_cal_channel;
+ u8 lcnphy_cal_counter;
+ u16 lcnphy_cal_temper;
+ bool lcnphy_recal;
+
+ u8 lcnphy_rc_cap;
+ u32 lcnphy_mcs20_po;
+
+ u8 lcnphy_tr_isolation_mid;
+ u8 lcnphy_tr_isolation_low;
+ u8 lcnphy_tr_isolation_hi;
+
+ u8 lcnphy_bx_arch;
+ u8 lcnphy_rx_power_offset;
+ u8 lcnphy_rssi_vf;
+ u8 lcnphy_rssi_vc;
+ u8 lcnphy_rssi_gs;
+ u8 lcnphy_tssi_val;
+ u8 lcnphy_rssi_vf_lowtemp;
+ u8 lcnphy_rssi_vc_lowtemp;
+ u8 lcnphy_rssi_gs_lowtemp;
+
+ u8 lcnphy_rssi_vf_hightemp;
+ u8 lcnphy_rssi_vc_hightemp;
+ u8 lcnphy_rssi_gs_hightemp;
+
+ s16 lcnphy_pa0b0;
+ s16 lcnphy_pa0b1;
+ s16 lcnphy_pa0b2;
+
+ u16 lcnphy_rawtempsense;
+ u8 lcnphy_measPower;
+ u8 lcnphy_tempsense_slope;
+ u8 lcnphy_freqoffset_corr;
+ u8 lcnphy_tempsense_option;
+ u8 lcnphy_tempcorrx;
+ bool lcnphy_iqcal_swp_dis;
+ bool lcnphy_hw_iqcal_en;
+ uint lcnphy_bandedge_corr;
+ bool lcnphy_spurmod;
+ u16 lcnphy_tssi_tx_cnt;
+ u16 lcnphy_tssi_idx;
+ u16 lcnphy_tssi_npt;
+
+ u16 lcnphy_target_tx_freq;
+ s8 lcnphy_tx_power_idx_override;
+ u16 lcnphy_noise_samples;
+
+ u32 lcnphy_papdRxGnIdx;
+ u32 lcnphy_papd_rxGnCtrl_init;
+
+ u32 lcnphy_gain_idx_14_lowword;
+ u32 lcnphy_gain_idx_14_hiword;
+ u32 lcnphy_gain_idx_27_lowword;
+ u32 lcnphy_gain_idx_27_hiword;
+ s16 lcnphy_ofdmgainidxtableoffset;
+ s16 lcnphy_dsssgainidxtableoffset;
+ u32 lcnphy_tr_R_gain_val;
+ u32 lcnphy_tr_T_gain_val;
+ s8 lcnphy_input_pwr_offset_db;
+ u16 lcnphy_Med_Low_Gain_db;
+ u16 lcnphy_Very_Low_Gain_db;
+ s8 lcnphy_lastsensed_temperature;
+ s8 lcnphy_pkteng_rssi_slope;
+ u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES];
+ u8 lcnphy_volt_winner;
+ u8 lcnphy_volt_low;
+ u8 lcnphy_54_48_36_24mbps_backoff;
+ u8 lcnphy_11n_backoff;
+ u8 lcnphy_lowerofdm;
+ u8 lcnphy_cck;
+ u8 lcnphy_psat_2pt3_detected;
+ s32 lcnphy_lowest_Re_div_Im;
+ s8 lcnphy_final_papd_cal_idx;
+ u16 lcnphy_extstxctrl4;
+ u16 lcnphy_extstxctrl0;
+ u16 lcnphy_extstxctrl1;
+ s16 lcnphy_cck_dig_filt_type;
+ s16 lcnphy_ofdm_dig_filt_type;
+ lcnphy_cal_results_t lcnphy_cal_results;
+
+ u8 lcnphy_psat_pwr;
+ u8 lcnphy_psat_indx;
+ s32 lcnphy_min_phase;
+ u8 lcnphy_final_idx;
+ u8 lcnphy_start_idx;
+ u8 lcnphy_current_index;
+ u16 lcnphy_logen_buf_1;
+ u16 lcnphy_local_ovr_2;
+ u16 lcnphy_local_oval_6;
+ u16 lcnphy_local_oval_5;
+ u16 lcnphy_logen_mixer_1;
+
+ u8 lcnphy_aci_stat;
+ uint lcnphy_aci_start_time;
+ s8 lcnphy_tx_power_offset[TXP_NUM_RATES];
+};
+#endif /* _BRCM_PHY_LCN_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <defs.h>
+#include <cfg.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <aiutils.h>
+#include <chipcommon.h>
+#include <pmu.h>
+
+#include <brcm_hw_ids.h>
+#include <dma.h>
+
+#include <types.h>
+#include <phy_radio.h>
+#include <phy_int.h>
+#include <phyreg_n.h>
+#include <phytbl_n.h>
+
+#define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \
+ read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
+ ((core == PHY_CORE_0) ? radio_type##_##jspace##0 : radio_type##_##jspace##1))
+#define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \
+ write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
+ ((core == PHY_CORE_0) ? radio_type##_##jspace##0 : radio_type##_##jspace##1), value);
+#define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \
+ write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value);
+
+#define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \
+ read_radio_reg(pi, ((core == PHY_CORE_0) ? radio_type##_##jspace##0##_##reg_name : \
+ radio_type##_##jspace##1##_##reg_name));
+#define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \
+ write_radio_reg(pi, ((core == PHY_CORE_0) ? radio_type##_##jspace##0##_##reg_name : \
+ radio_type##_##jspace##1##_##reg_name), value);
+#define READ_RADIO_REG4(pi, radio_type, jspace, core, reg_name) \
+ read_radio_reg(pi, ((core == PHY_CORE_0) ? radio_type##_##reg_name##_##jspace##0 : \
+ radio_type##_##reg_name##_##jspace##1));
+#define WRITE_RADIO_REG4(pi, radio_type, jspace, core, reg_name, value) \
+ write_radio_reg(pi, ((core == PHY_CORE_0) ? radio_type##_##reg_name##_##jspace##0 : \
+ radio_type##_##reg_name##_##jspace##1), value);
+
+#define NPHY_ACI_MAX_UNDETECT_WINDOW_SZ 40
+#define NPHY_ACI_CHANNEL_DELTA 5
+#define NPHY_ACI_CHANNEL_SKIP 4
+#define NPHY_ACI_40MHZ_CHANNEL_DELTA 6
+#define NPHY_ACI_40MHZ_CHANNEL_SKIP 5
+#define NPHY_ACI_40MHZ_CHANNEL_DELTA_GE_REV3 6
+#define NPHY_ACI_40MHZ_CHANNEL_SKIP_GE_REV3 5
+#define NPHY_ACI_CHANNEL_DELTA_GE_REV3 4
+#define NPHY_ACI_CHANNEL_SKIP_GE_REV3 3
+
+#define NPHY_NOISE_NOASSOC_GLITCH_TH_UP 2
+
+#define NPHY_NOISE_NOASSOC_GLITCH_TH_DN 8
+
+#define NPHY_NOISE_ASSOC_GLITCH_TH_UP 2
+
+#define NPHY_NOISE_ASSOC_GLITCH_TH_DN 8
+
+#define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_UP 2
+
+#define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_DN 8
+
+#define NPHY_NOISE_NOASSOC_ENTER_TH 400
+
+#define NPHY_NOISE_ASSOC_ENTER_TH 400
+
+#define NPHY_NOISE_ASSOC_RX_GLITCH_BADPLCP_ENTER_TH 400
+
+#define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX 44
+#define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX_REV_7 56
+
+#define NPHY_NOISE_NOASSOC_CRSIDX_INCR 16
+
+#define NPHY_NOISE_ASSOC_CRSIDX_INCR 8
+
+#define NPHY_IS_SROM_REINTERPRET NREV_GE(pi->pubpi.phy_rev, 5)
+
+#define NPHY_RSSICAL_MAXREAD 31
+
+#define NPHY_RSSICAL_NPOLL 8
+#define NPHY_RSSICAL_MAXD (1<<20)
+#define NPHY_MIN_RXIQ_PWR 2
+
+#define NPHY_RSSICAL_W1_TARGET 25
+#define NPHY_RSSICAL_W2_TARGET NPHY_RSSICAL_W1_TARGET
+#define NPHY_RSSICAL_NB_TARGET 0
+
+#define NPHY_RSSICAL_W1_TARGET_REV3 29
+#define NPHY_RSSICAL_W2_TARGET_REV3 NPHY_RSSICAL_W1_TARGET_REV3
+
+#define NPHY_CALSANITY_RSSI_NB_MAX_POS 9
+#define NPHY_CALSANITY_RSSI_NB_MAX_NEG -9
+#define NPHY_CALSANITY_RSSI_W1_MAX_POS 12
+#define NPHY_CALSANITY_RSSI_W1_MAX_NEG (NPHY_RSSICAL_W1_TARGET - NPHY_RSSICAL_MAXREAD)
+#define NPHY_CALSANITY_RSSI_W2_MAX_POS NPHY_CALSANITY_RSSI_W1_MAX_POS
+#define NPHY_CALSANITY_RSSI_W2_MAX_NEG (NPHY_RSSICAL_W2_TARGET - NPHY_RSSICAL_MAXREAD)
+#define NPHY_RSSI_SXT(x) ((s8) (-((x) & 0x20) + ((x) & 0x1f)))
+#define NPHY_RSSI_NB_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_NB_MAX_POS) || \
+ ((x) < NPHY_CALSANITY_RSSI_NB_MAX_NEG))
+#define NPHY_RSSI_W1_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W1_MAX_POS) || \
+ ((x) < NPHY_CALSANITY_RSSI_W1_MAX_NEG))
+#define NPHY_RSSI_W2_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W2_MAX_POS) || \
+ ((x) < NPHY_CALSANITY_RSSI_W2_MAX_NEG))
+
+#define NPHY_IQCAL_NUMGAINS 9
+#define NPHY_N_GCTL 0x66
+
+#define NPHY_PAPD_EPS_TBL_SIZE 64
+#define NPHY_PAPD_SCL_TBL_SIZE 64
+#define NPHY_NUM_DIG_FILT_COEFFS 15
+
+#define NPHY_PAPD_COMP_OFF 0
+#define NPHY_PAPD_COMP_ON 1
+
+#define NPHY_SROM_TEMPSHIFT 32
+#define NPHY_SROM_MAXTEMPOFFSET 16
+#define NPHY_SROM_MINTEMPOFFSET -16
+
+#define NPHY_CAL_MAXTEMPDELTA 64
+
+#define NPHY_NOISEVAR_TBLLEN40 256
+#define NPHY_NOISEVAR_TBLLEN20 128
+
+#define NPHY_ANARXLPFBW_REDUCTIONFACT 7
+
+#define NPHY_ADJUSTED_MINCRSPOWER 0x1e
+
+/* 5357 Chip specific ChipControl register bits */
+#define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */
+#define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */
+
+typedef struct _nphy_iqcal_params {
+ u16 txlpf;
+ u16 txgm;
+ u16 pga;
+ u16 pad;
+ u16 ipa;
+ u16 cal_gain;
+ u16 ncorr[5];
+} nphy_iqcal_params_t;
+
+typedef struct _nphy_txiqcal_ladder {
+ u8 percent;
+ u8 g_env;
+} nphy_txiqcal_ladder_t;
+
+typedef struct {
+ nphy_txgains_t gains;
+ bool useindex;
+ u8 index;
+} nphy_ipa_txcalgains_t;
+
+typedef struct nphy_papd_restore_state_t {
+ u16 fbmix[2];
+ u16 vga_master[2];
+ u16 intpa_master[2];
+ u16 afectrl[2];
+ u16 afeoverride[2];
+ u16 pwrup[2];
+ u16 atten[2];
+ u16 mm;
+} nphy_papd_restore_state;
+
+typedef struct _nphy_ipa_txrxgain {
+ u16 hpvga;
+ u16 lpf_biq1;
+ u16 lpf_biq0;
+ u16 lna2;
+ u16 lna1;
+ s8 txpwrindex;
+} nphy_ipa_txrxgain_t;
+
+#define NPHY_IPA_RXCAL_MAXGAININDEX (6 - 1)
+
+nphy_ipa_txrxgain_t nphy_ipa_rxcal_gaintbl_5GHz[] = { {0, 0, 0, 0, 0, 100},
+{0, 0, 0, 0, 0, 50},
+{0, 0, 0, 0, 0, -1},
+{0, 0, 0, 3, 0, -1},
+{0, 0, 3, 3, 0, -1},
+{0, 2, 3, 3, 0, -1}
+};
+
+nphy_ipa_txrxgain_t nphy_ipa_rxcal_gaintbl_2GHz[] = { {0, 0, 0, 0, 0, 128},
+{0, 0, 0, 0, 0, 70},
+{0, 0, 0, 0, 0, 20},
+{0, 0, 0, 3, 0, 20},
+{0, 0, 3, 3, 0, 20},
+{0, 2, 3, 3, 0, 20}
+};
+
+nphy_ipa_txrxgain_t nphy_ipa_rxcal_gaintbl_5GHz_rev7[] = { {0, 0, 0, 0, 0, 100},
+{0, 0, 0, 0, 0, 50},
+{0, 0, 0, 0, 0, -1},
+{0, 0, 0, 3, 0, -1},
+{0, 0, 3, 3, 0, -1},
+{0, 0, 5, 3, 0, -1}
+};
+
+nphy_ipa_txrxgain_t nphy_ipa_rxcal_gaintbl_2GHz_rev7[] = { {0, 0, 0, 0, 0, 10},
+{0, 0, 0, 1, 0, 10},
+{0, 0, 1, 2, 0, 10},
+{0, 0, 1, 3, 0, 10},
+{0, 0, 4, 3, 0, 10},
+{0, 0, 6, 3, 0, 10}
+};
+
+#define NPHY_RXCAL_TONEAMP 181
+#define NPHY_RXCAL_TONEFREQ_40MHz 4000
+#define NPHY_RXCAL_TONEFREQ_20MHz 2000
+
+enum {
+ NPHY_RXCAL_GAIN_INIT = 0,
+ NPHY_RXCAL_GAIN_UP,
+ NPHY_RXCAL_GAIN_DOWN
+};
+
+#define wlc_phy_get_papd_nphy(pi) \
+ (read_phy_reg((pi), 0x1e7) & \
+ ((0x1 << 15) | \
+ (0x1 << 14) | \
+ (0x1 << 13)))
+
+#define TXFILT_SHAPING_OFDM20 0
+#define TXFILT_SHAPING_OFDM40 1
+#define TXFILT_SHAPING_CCK 2
+#define TXFILT_DEFAULT_OFDM20 3
+#define TXFILT_DEFAULT_OFDM40 4
+
+u16 NPHY_IPA_REV4_txdigi_filtcoeffs[][NPHY_NUM_DIG_FILT_COEFFS] = {
+ {-377, 137, -407, 208, -1527, 956, 93, 186, 93,
+ 230, -44, 230, 201, -191, 201},
+ {-77, 20, -98, 49, -93, 60, 56, 111, 56, 26, -5,
+ 26, 34, -32, 34},
+ {-360, 164, -376, 164, -1533, 576, 308, -314, 308,
+ 121, -73, 121, 91, 124, 91},
+ {-295, 200, -363, 142, -1391, 826, 151, 301, 151,
+ 151, 301, 151, 602, -752, 602},
+ {-92, 58, -96, 49, -104, 44, 17, 35, 17,
+ 12, 25, 12, 13, 27, 13},
+ {-375, 136, -399, 209, -1479, 949, 130, 260, 130,
+ 230, -44, 230, 201, -191, 201},
+ {0xed9, 0xc8, 0xe95, 0x8e, 0xa91, 0x33a, 0x97, 0x12d, 0x97,
+ 0x97, 0x12d, 0x97, 0x25a, 0xd10, 0x25a}
+};
+
+typedef struct _chan_info_nphy_2055 {
+ u16 chan;
+ u16 freq;
+ uint unknown;
+ u8 RF_pll_ref;
+ u8 RF_rf_pll_mod1;
+ u8 RF_rf_pll_mod0;
+ u8 RF_vco_cap_tail;
+ u8 RF_vco_cal1;
+ u8 RF_vco_cal2;
+ u8 RF_pll_lf_c1;
+ u8 RF_pll_lf_r1;
+ u8 RF_pll_lf_c2;
+ u8 RF_lgbuf_cen_buf;
+ u8 RF_lgen_tune1;
+ u8 RF_lgen_tune2;
+ u8 RF_core1_lgbuf_a_tune;
+ u8 RF_core1_lgbuf_g_tune;
+ u8 RF_core1_rxrf_reg1;
+ u8 RF_core1_tx_pga_pad_tn;
+ u8 RF_core1_tx_mx_bgtrim;
+ u8 RF_core2_lgbuf_a_tune;
+ u8 RF_core2_lgbuf_g_tune;
+ u8 RF_core2_rxrf_reg1;
+ u8 RF_core2_tx_pga_pad_tn;
+ u8 RF_core2_tx_mx_bgtrim;
+ u16 PHY_BW1a;
+ u16 PHY_BW2;
+ u16 PHY_BW3;
+ u16 PHY_BW4;
+ u16 PHY_BW5;
+ u16 PHY_BW6;
+} chan_info_nphy_2055_t;
+
+typedef struct _chan_info_nphy_radio205x {
+ u16 chan;
+ u16 freq;
+ u8 RF_SYN_pll_vcocal1;
+ u8 RF_SYN_pll_vcocal2;
+ u8 RF_SYN_pll_refdiv;
+ u8 RF_SYN_pll_mmd2;
+ u8 RF_SYN_pll_mmd1;
+ u8 RF_SYN_pll_loopfilter1;
+ u8 RF_SYN_pll_loopfilter2;
+ u8 RF_SYN_pll_loopfilter3;
+ u8 RF_SYN_pll_loopfilter4;
+ u8 RF_SYN_pll_loopfilter5;
+ u8 RF_SYN_reserved_addr27;
+ u8 RF_SYN_reserved_addr28;
+ u8 RF_SYN_reserved_addr29;
+ u8 RF_SYN_logen_VCOBUF1;
+ u8 RF_SYN_logen_MIXER2;
+ u8 RF_SYN_logen_BUF3;
+ u8 RF_SYN_logen_BUF4;
+ u8 RF_RX0_lnaa_tune;
+ u8 RF_RX0_lnag_tune;
+ u8 RF_TX0_intpaa_boost_tune;
+ u8 RF_TX0_intpag_boost_tune;
+ u8 RF_TX0_pada_boost_tune;
+ u8 RF_TX0_padg_boost_tune;
+ u8 RF_TX0_pgaa_boost_tune;
+ u8 RF_TX0_pgag_boost_tune;
+ u8 RF_TX0_mixa_boost_tune;
+ u8 RF_TX0_mixg_boost_tune;
+ u8 RF_RX1_lnaa_tune;
+ u8 RF_RX1_lnag_tune;
+ u8 RF_TX1_intpaa_boost_tune;
+ u8 RF_TX1_intpag_boost_tune;
+ u8 RF_TX1_pada_boost_tune;
+ u8 RF_TX1_padg_boost_tune;
+ u8 RF_TX1_pgaa_boost_tune;
+ u8 RF_TX1_pgag_boost_tune;
+ u8 RF_TX1_mixa_boost_tune;
+ u8 RF_TX1_mixg_boost_tune;
+ u16 PHY_BW1a;
+ u16 PHY_BW2;
+ u16 PHY_BW3;
+ u16 PHY_BW4;
+ u16 PHY_BW5;
+ u16 PHY_BW6;
+} chan_info_nphy_radio205x_t;
+
+typedef struct _chan_info_nphy_radio2057 {
+ u16 chan;
+ u16 freq;
+ u8 RF_vcocal_countval0;
+ u8 RF_vcocal_countval1;
+ u8 RF_rfpll_refmaster_sparextalsize;
+ u8 RF_rfpll_loopfilter_r1;
+ u8 RF_rfpll_loopfilter_c2;
+ u8 RF_rfpll_loopfilter_c1;
+ u8 RF_cp_kpd_idac;
+ u8 RF_rfpll_mmd0;
+ u8 RF_rfpll_mmd1;
+ u8 RF_vcobuf_tune;
+ u8 RF_logen_mx2g_tune;
+ u8 RF_logen_mx5g_tune;
+ u8 RF_logen_indbuf2g_tune;
+ u8 RF_logen_indbuf5g_tune;
+ u8 RF_txmix2g_tune_boost_pu_core0;
+ u8 RF_pad2g_tune_pus_core0;
+ u8 RF_pga_boost_tune_core0;
+ u8 RF_txmix5g_boost_tune_core0;
+ u8 RF_pad5g_tune_misc_pus_core0;
+ u8 RF_lna2g_tune_core0;
+ u8 RF_lna5g_tune_core0;
+ u8 RF_txmix2g_tune_boost_pu_core1;
+ u8 RF_pad2g_tune_pus_core1;
+ u8 RF_pga_boost_tune_core1;
+ u8 RF_txmix5g_boost_tune_core1;
+ u8 RF_pad5g_tune_misc_pus_core1;
+ u8 RF_lna2g_tune_core1;
+ u8 RF_lna5g_tune_core1;
+ u16 PHY_BW1a;
+ u16 PHY_BW2;
+ u16 PHY_BW3;
+ u16 PHY_BW4;
+ u16 PHY_BW5;
+ u16 PHY_BW6;
+} chan_info_nphy_radio2057_t;
+
+typedef struct _chan_info_nphy_radio2057_rev5 {
+ u16 chan;
+ u16 freq;
+ u8 RF_vcocal_countval0;
+ u8 RF_vcocal_countval1;
+ u8 RF_rfpll_refmaster_sparextalsize;
+ u8 RF_rfpll_loopfilter_r1;
+ u8 RF_rfpll_loopfilter_c2;
+ u8 RF_rfpll_loopfilter_c1;
+ u8 RF_cp_kpd_idac;
+ u8 RF_rfpll_mmd0;
+ u8 RF_rfpll_mmd1;
+ u8 RF_vcobuf_tune;
+ u8 RF_logen_mx2g_tune;
+ u8 RF_logen_indbuf2g_tune;
+ u8 RF_txmix2g_tune_boost_pu_core0;
+ u8 RF_pad2g_tune_pus_core0;
+ u8 RF_lna2g_tune_core0;
+ u8 RF_txmix2g_tune_boost_pu_core1;
+ u8 RF_pad2g_tune_pus_core1;
+ u8 RF_lna2g_tune_core1;
+ u16 PHY_BW1a;
+ u16 PHY_BW2;
+ u16 PHY_BW3;
+ u16 PHY_BW4;
+ u16 PHY_BW5;
+ u16 PHY_BW6;
+} chan_info_nphy_radio2057_rev5_t;
+
+typedef struct nphy_sfo_cfg {
+ u16 PHY_BW1a;
+ u16 PHY_BW2;
+ u16 PHY_BW3;
+ u16 PHY_BW4;
+ u16 PHY_BW5;
+ u16 PHY_BW6;
+} nphy_sfo_cfg_t;
+
+static chan_info_nphy_2055_t chan_info_nphy_2055[] = {
+ {
+ 184, 4920, 3280, 0x71, 0x01, 0xEC, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7B4, 0x7B0, 0x7AC, 0x214, 0x215, 0x216},
+ {
+ 186, 4930, 3287, 0x71, 0x01, 0xED, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7B8, 0x7B4, 0x7B0, 0x213, 0x214, 0x215},
+ {
+ 188, 4940, 3293, 0x71, 0x01, 0xEE, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7BC, 0x7B8, 0x7B4, 0x212, 0x213, 0x214},
+ {
+ 190, 4950, 3300, 0x71, 0x01, 0xEF, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7C0, 0x7BC, 0x7B8, 0x211, 0x212, 0x213},
+ {
+ 192, 4960, 3307, 0x71, 0x01, 0xF0, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7C4, 0x7C0, 0x7BC, 0x20F, 0x211, 0x212},
+ {
+ 194, 4970, 3313, 0x71, 0x01, 0xF1, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7C8, 0x7C4, 0x7C0, 0x20E, 0x20F, 0x211},
+ {
+ 196, 4980, 3320, 0x71, 0x01, 0xF2, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7CC, 0x7C8, 0x7C4, 0x20D, 0x20E, 0x20F},
+ {
+ 198, 4990, 3327, 0x71, 0x01, 0xF3, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7D0, 0x7CC, 0x7C8, 0x20C, 0x20D, 0x20E},
+ {
+ 200, 5000, 3333, 0x71, 0x01, 0xF4, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7D4, 0x7D0, 0x7CC, 0x20B, 0x20C, 0x20D},
+ {
+ 202, 5010, 3340, 0x71, 0x01, 0xF5, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7D8, 0x7D4, 0x7D0, 0x20A, 0x20B, 0x20C},
+ {
+ 204, 5020, 3347, 0x71, 0x01, 0xF6, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7DC, 0x7D8, 0x7D4, 0x209, 0x20A, 0x20B},
+ {
+ 206, 5030, 3353, 0x71, 0x01, 0xF7, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7E0, 0x7DC, 0x7D8, 0x208, 0x209, 0x20A},
+ {
+ 208, 5040, 3360, 0x71, 0x01, 0xF8, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7E4, 0x7E0, 0x7DC, 0x207, 0x208, 0x209},
+ {
+ 210, 5050, 3367, 0x71, 0x01, 0xF9, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
+ 0x0F, 0x8F, 0x7E8, 0x7E4, 0x7E0, 0x206, 0x207, 0x208},
+ {
+ 212, 5060, 3373, 0x71, 0x01, 0xFA, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, 0x8E, 0xFF, 0x00, 0x0E,
+ 0x0F, 0x8E, 0x7EC, 0x7E8, 0x7E4, 0x205, 0x206, 0x207},
+ {
+ 214, 5070, 3380, 0x71, 0x01, 0xFB, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
+ 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, 0x8E, 0xFF, 0x00, 0x0E,
+ 0x0F, 0x8E, 0x7F0, 0x7EC, 0x7E8, 0x204, 0x205, 0x206},
+ {
+ 216, 5080, 3387, 0x71, 0x01, 0xFC, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
+ 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, 0x8D, 0xEE, 0x00, 0x0E,
+ 0x0F, 0x8D, 0x7F4, 0x7F0, 0x7EC, 0x203, 0x204, 0x205},
+ {
+ 218, 5090, 3393, 0x71, 0x01, 0xFD, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
+ 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, 0x8D, 0xEE, 0x00, 0x0E,
+ 0x0F, 0x8D, 0x7F8, 0x7F4, 0x7F0, 0x202, 0x203, 0x204},
+ {
+ 220, 5100, 3400, 0x71, 0x01, 0xFE, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
+ 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, 0x8D, 0xEE, 0x00, 0x0D,
+ 0x0F, 0x8D, 0x7FC, 0x7F8, 0x7F4, 0x201, 0x202, 0x203},
+ {
+ 222, 5110, 3407, 0x71, 0x01, 0xFF, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
+ 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, 0x8D, 0xEE, 0x00, 0x0D,
+ 0x0F, 0x8D, 0x800, 0x7FC, 0x7F8, 0x200, 0x201, 0x202},
+ {
+ 224, 5120, 3413, 0x71, 0x02, 0x00, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
+ 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, 0x8C, 0xDD, 0x00, 0x0D,
+ 0x0F, 0x8C, 0x804, 0x800, 0x7FC, 0x1FF, 0x200, 0x201},
+ {
+ 226, 5130, 3420, 0x71, 0x02, 0x01, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
+ 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, 0x8C, 0xDD, 0x00, 0x0D,
+ 0x0F, 0x8C, 0x808, 0x804, 0x800, 0x1FE, 0x1FF, 0x200},
+ {
+ 228, 5140, 3427, 0x71, 0x02, 0x02, 0x0C, 0xC6, 0x01, 0x04, 0x0A,
+ 0x00, 0x8D, 0x99, 0x99, 0xDD, 0x00, 0x0C, 0x0E, 0x8B, 0xDD, 0x00, 0x0C,
+ 0x0E, 0x8B, 0x80C, 0x808, 0x804, 0x1FD, 0x1FE, 0x1FF},
+ {
+ 32, 5160, 3440, 0x71, 0x02, 0x04, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
+ 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, 0x8A, 0xCC, 0x00, 0x0B,
+ 0x0D, 0x8A, 0x814, 0x810, 0x80C, 0x1FB, 0x1FC, 0x1FD},
+ {
+ 34, 5170, 3447, 0x71, 0x02, 0x05, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
+ 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, 0x8A, 0xCC, 0x00, 0x0B,
+ 0x0D, 0x8A, 0x818, 0x814, 0x810, 0x1FA, 0x1FB, 0x1FC},
+ {
+ 36, 5180, 3453, 0x71, 0x02, 0x06, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
+ 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, 0x89, 0xCC, 0x00, 0x0B,
+ 0x0C, 0x89, 0x81C, 0x818, 0x814, 0x1F9, 0x1FA, 0x1FB},
+ {
+ 38, 5190, 3460, 0x71, 0x02, 0x07, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
+ 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, 0x89, 0xCC, 0x00, 0x0B,
+ 0x0C, 0x89, 0x820, 0x81C, 0x818, 0x1F8, 0x1F9, 0x1FA},
+ {
+ 40, 5200, 3467, 0x71, 0x02, 0x08, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, 0x89, 0xBB, 0x00, 0x0A,
+ 0x0B, 0x89, 0x824, 0x820, 0x81C, 0x1F7, 0x1F8, 0x1F9},
+ {
+ 42, 5210, 3473, 0x71, 0x02, 0x09, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
+ 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, 0x89, 0xBB, 0x00, 0x0A,
+ 0x0B, 0x89, 0x828, 0x824, 0x820, 0x1F6, 0x1F7, 0x1F8},
+ {
+ 44, 5220, 3480, 0x71, 0x02, 0x0A, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
+ 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, 0x88, 0xBB, 0x00, 0x09,
+ 0x0A, 0x88, 0x82C, 0x828, 0x824, 0x1F5, 0x1F6, 0x1F7},
+ {
+ 46, 5230, 3487, 0x71, 0x02, 0x0B, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
+ 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, 0x88, 0xBB, 0x00, 0x09,
+ 0x0A, 0x88, 0x830, 0x82C, 0x828, 0x1F4, 0x1F5, 0x1F6},
+ {
+ 48, 5240, 3493, 0x71, 0x02, 0x0C, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
+ 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A, 0x87, 0xAA, 0x00, 0x09,
+ 0x0A, 0x87, 0x834, 0x830, 0x82C, 0x1F3, 0x1F4, 0x1F5},
+ {
+ 50, 5250, 3500, 0x71, 0x02, 0x0D, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
+ 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A, 0x87, 0xAA, 0x00, 0x09,
+ 0x0A, 0x87, 0x838, 0x834, 0x830, 0x1F2, 0x1F3, 0x1F4},
+ {
+ 52, 5260, 3507, 0x71, 0x02, 0x0E, 0x0A, 0x98, 0x01, 0x04, 0x0A,
+ 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09, 0x87, 0xAA, 0x00, 0x08,
+ 0x09, 0x87, 0x83C, 0x838, 0x834, 0x1F1, 0x1F2, 0x1F3},
+ {
+ 54, 5270, 3513, 0x71, 0x02, 0x0F, 0x0A, 0x98, 0x01, 0x04, 0x0A,
+ 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09, 0x87, 0xAA, 0x00, 0x08,
+ 0x09, 0x87, 0x840, 0x83C, 0x838, 0x1F0, 0x1F1, 0x1F2},
+ {
+ 56, 5280, 3520, 0x71, 0x02, 0x10, 0x09, 0x91, 0x01, 0x04, 0x0A,
+ 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08, 0x86, 0x99, 0x00, 0x08,
+ 0x08, 0x86, 0x844, 0x840, 0x83C, 0x1F0, 0x1F0, 0x1F1},
+ {
+ 58, 5290, 3527, 0x71, 0x02, 0x11, 0x09, 0x91, 0x01, 0x04, 0x0A,
+ 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08, 0x86, 0x99, 0x00, 0x08,
+ 0x08, 0x86, 0x848, 0x844, 0x840, 0x1EF, 0x1F0, 0x1F0},
+ {
+ 60, 5300, 3533, 0x71, 0x02, 0x12, 0x09, 0x8A, 0x01, 0x04, 0x0A,
+ 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07, 0x85, 0x99, 0x00, 0x08,
+ 0x07, 0x85, 0x84C, 0x848, 0x844, 0x1EE, 0x1EF, 0x1F0},
+ {
+ 62, 5310, 3540, 0x71, 0x02, 0x13, 0x09, 0x8A, 0x01, 0x04, 0x0A,
+ 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07, 0x85, 0x99, 0x00, 0x08,
+ 0x07, 0x85, 0x850, 0x84C, 0x848, 0x1ED, 0x1EE, 0x1EF},
+ {
+ 64, 5320, 3547, 0x71, 0x02, 0x14, 0x09, 0x83, 0x01, 0x04, 0x0A,
+ 0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07, 0x84, 0x88, 0x00, 0x07,
+ 0x07, 0x84, 0x854, 0x850, 0x84C, 0x1EC, 0x1ED, 0x1EE},
+ {
+ 66, 5330, 3553, 0x71, 0x02, 0x15, 0x09, 0x83, 0x01, 0x04, 0x0A,
+ 0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07, 0x84, 0x88, 0x00, 0x07,
+ 0x07, 0x84, 0x858, 0x854, 0x850, 0x1EB, 0x1EC, 0x1ED},
+ {
+ 68, 5340, 3560, 0x71, 0x02, 0x16, 0x08, 0x7C, 0x01, 0x04, 0x0A,
+ 0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06, 0x84, 0x88, 0x00, 0x07,
+ 0x06, 0x84, 0x85C, 0x858, 0x854, 0x1EA, 0x1EB, 0x1EC},
+ {
+ 70, 5350, 3567, 0x71, 0x02, 0x17, 0x08, 0x7C, 0x01, 0x04, 0x0A,
+ 0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06, 0x84, 0x88, 0x00, 0x07,
+ 0x06, 0x84, 0x860, 0x85C, 0x858, 0x1E9, 0x1EA, 0x1EB},
+ {
+ 72, 5360, 3573, 0x71, 0x02, 0x18, 0x08, 0x75, 0x01, 0x04, 0x0A,
+ 0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05, 0x83, 0x77, 0x00, 0x06,
+ 0x05, 0x83, 0x864, 0x860, 0x85C, 0x1E8, 0x1E9, 0x1EA},
+ {
+ 74, 5370, 3580, 0x71, 0x02, 0x19, 0x08, 0x75, 0x01, 0x04, 0x0A,
+ 0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05, 0x83, 0x77, 0x00, 0x06,
+ 0x05, 0x83, 0x868, 0x864, 0x860, 0x1E7, 0x1E8, 0x1E9},
+ {
+ 76, 5380, 3587, 0x71, 0x02, 0x1A, 0x08, 0x6E, 0x01, 0x04, 0x0A,
+ 0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04, 0x82, 0x77, 0x00, 0x06,
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+ 0x00, 0x80, 0x920, 0x91C, 0x918, 0x1C1, 0x1C2, 0x1C2},
+ {
+ 168, 5840, 3893, 0x71, 0x02, 0x48, 0x01, 0x0A, 0x01, 0x04, 0x0A,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x924, 0x920, 0x91C, 0x1C0, 0x1C1, 0x1C2},
+ {
+ 170, 5850, 3900, 0x71, 0x02, 0x49, 0x01, 0xE0, 0x00, 0x04, 0x0A,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x928, 0x924, 0x920, 0x1BF, 0x1C0, 0x1C1},
+ {
+ 172, 5860, 3907, 0x71, 0x02, 0x4A, 0x01, 0xDE, 0x00, 0x04, 0x0A,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x92C, 0x928, 0x924, 0x1BF, 0x1BF, 0x1C0},
+ {
+ 174, 5870, 3913, 0x71, 0x02, 0x4B, 0x00, 0xDB, 0x00, 0x04, 0x0A,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x930, 0x92C, 0x928, 0x1BE, 0x1BF, 0x1BF},
+ {
+ 176, 5880, 3920, 0x71, 0x02, 0x4C, 0x00, 0xD8, 0x00, 0x04, 0x0A,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x934, 0x930, 0x92C, 0x1BD, 0x1BE, 0x1BF},
+ {
+ 178, 5890, 3927, 0x71, 0x02, 0x4D, 0x00, 0xD6, 0x00, 0x04, 0x0A,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x938, 0x934, 0x930, 0x1BC, 0x1BD, 0x1BE},
+ {
+ 180, 5900, 3933, 0x71, 0x02, 0x4E, 0x00, 0xD3, 0x00, 0x04, 0x0A,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x93C, 0x938, 0x934, 0x1BC, 0x1BC, 0x1BD},
+ {
+ 182, 5910, 3940, 0x71, 0x02, 0x4F, 0x00, 0xD6, 0x00, 0x04, 0x0A,
+ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x80, 0x940, 0x93C, 0x938, 0x1BB, 0x1BC, 0x1BC},
+ {
+ 1, 2412, 3216, 0x73, 0x09, 0x6C, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0D, 0x0C, 0x80, 0xFF, 0x88, 0x0D,
+ 0x0C, 0x80, 0x3C9, 0x3C5, 0x3C1, 0x43A, 0x43F, 0x443},
+ {
+ 2, 2417, 3223, 0x73, 0x09, 0x71, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0B, 0x80, 0xFF, 0x88, 0x0C,
+ 0x0B, 0x80, 0x3CB, 0x3C7, 0x3C3, 0x438, 0x43D, 0x441},
+ {
+ 3, 2422, 3229, 0x73, 0x09, 0x76, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, 0x80, 0xFF, 0x88, 0x0C,
+ 0x0A, 0x80, 0x3CD, 0x3C9, 0x3C5, 0x436, 0x43A, 0x43F},
+ {
+ 4, 2427, 3236, 0x73, 0x09, 0x7B, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, 0x80, 0xFF, 0x88, 0x0C,
+ 0x0A, 0x80, 0x3CF, 0x3CB, 0x3C7, 0x434, 0x438, 0x43D},
+ {
+ 5, 2432, 3243, 0x73, 0x09, 0x80, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x09, 0x80, 0xFF, 0x88, 0x0C,
+ 0x09, 0x80, 0x3D1, 0x3CD, 0x3C9, 0x431, 0x436, 0x43A},
+ {
+ 6, 2437, 3249, 0x73, 0x09, 0x85, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0B, 0x08, 0x80, 0xFF, 0x88, 0x0B,
+ 0x08, 0x80, 0x3D3, 0x3CF, 0x3CB, 0x42F, 0x434, 0x438},
+ {
+ 7, 2442, 3256, 0x73, 0x09, 0x8A, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x07, 0x80, 0xFF, 0x88, 0x0A,
+ 0x07, 0x80, 0x3D5, 0x3D1, 0x3CD, 0x42D, 0x431, 0x436},
+ {
+ 8, 2447, 3263, 0x73, 0x09, 0x8F, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x06, 0x80, 0xFF, 0x88, 0x0A,
+ 0x06, 0x80, 0x3D7, 0x3D3, 0x3CF, 0x42B, 0x42F, 0x434},
+ {
+ 9, 2452, 3269, 0x73, 0x09, 0x94, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x09, 0x06, 0x80, 0xFF, 0x88, 0x09,
+ 0x06, 0x80, 0x3D9, 0x3D5, 0x3D1, 0x429, 0x42D, 0x431},
+ {
+ 10, 2457, 3276, 0x73, 0x09, 0x99, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x05, 0x80, 0xFF, 0x88, 0x08,
+ 0x05, 0x80, 0x3DB, 0x3D7, 0x3D3, 0x427, 0x42B, 0x42F},
+ {
+ 11, 2462, 3283, 0x73, 0x09, 0x9E, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x04, 0x80, 0xFF, 0x88, 0x08,
+ 0x04, 0x80, 0x3DD, 0x3D9, 0x3D5, 0x424, 0x429, 0x42D},
+ {
+ 12, 2467, 3289, 0x73, 0x09, 0xA3, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x03, 0x80, 0xFF, 0x88, 0x08,
+ 0x03, 0x80, 0x3DF, 0x3DB, 0x3D7, 0x422, 0x427, 0x42B},
+ {
+ 13, 2472, 3296, 0x73, 0x09, 0xA8, 0x0F, 0x00, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x03, 0x80, 0xFF, 0x88, 0x07,
+ 0x03, 0x80, 0x3E1, 0x3DD, 0x3D9, 0x420, 0x424, 0x429},
+ {
+ 14, 2484, 3312, 0x73, 0x09, 0xB4, 0x0F, 0xFF, 0x01, 0x07, 0x15,
+ 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x01, 0x80, 0xFF, 0x88, 0x07,
+ 0x01, 0x80, 0x3E6, 0x3E2, 0x3DE, 0x41B, 0x41F, 0x424}
+};
+
+static chan_info_nphy_radio205x_t chan_info_nphyrev3_2056[] = {
+ {
+ 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
+ {
+ 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
+ {
+ 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
+ {
+ 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
+ {
+ 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
+ {
+ 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
+ {
+ 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
+ {
+ 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
+ {
+ 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
+ {
+ 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
+ {
+ 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
+ {
+ 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
+ {
+ 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
+ {
+ 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
+ {
+ 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
+ {
+ 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
+ {
+ 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
+ {
+ 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
+ {
+ 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xff, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
+ {
+ 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xfc, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
+ {
+ 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xfc, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
+ {
+ 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xfc, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
+ {
+ 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xfc, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
+ {
+ 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+ 0x00, 0xfc, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
+ {
+ 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
+ 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
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+ 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+ 0x00, 0xf4, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
+ {
+ 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+ 0x00, 0xf4, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
+ {
+ 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x06, 0x00, 0xf2, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+ 0x00, 0xf2, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
+ {
+ 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+ 0x00, 0xf2, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
+ {
+ 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+ 0x00, 0xf2, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
+ {
+ 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+ 0x00, 0xf2, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
+ {
+ 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x05, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05,
+ 0x00, 0xf2, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
+ {
+ 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x05, 0x00, 0xf2, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05,
+ 0x00, 0xf2, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
+ {
+ 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
+ {
+ 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
+ {
+ 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
+ {
+ 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfd, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
+ {
+ 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfb, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfb, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
+ {
+ 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfa, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
+ {
+ 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf8, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
+ {
+ 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf7, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf7, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
+ {
+ 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf6, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf6, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0f, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
+ {
+ 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf5, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0d, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
+ {
+ 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0d, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
+ {
+ 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf3, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0d, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf2, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0d, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x05, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf0, 0x00, 0x05, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0d, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio205x_t chan_info_nphyrev4_2056_A1[] = {
+ {
+ 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
+ {
+ 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
+ {
+ 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
+ {
+ 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
+ {
+ 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
+ {
+ 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
+ {
+ 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
+ {
+ 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
+ {
+ 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
+ {
+ 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
+ {
+ 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
+ {
+ 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
+ {
+ 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
+ {
+ 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
+ {
+ 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
+ {
+ 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
+ {
+ 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+ 0x00, 0xff, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
+ {
+ 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
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+ 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f,
+ 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+ 0x00, 0xf2, 0x00, 0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5},
+ {
+ 160, 5800, 0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5},
+ {
+ 161, 5805, 0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4},
+ {
+ 162, 5810, 0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4},
+ {
+ 163, 5815, 0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
+ {
+ 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
+ {
+ 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
+ {
+ 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
+ {
+ 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
+ {
+ 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
+ {
+ 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
+ {
+ 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
+ {
+ 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
+ {
+ 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
+ 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+ 0x00, 0xf0, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
+ {
+ 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x07, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07,
+ 0x00, 0xf0, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
+ {
+ 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f,
+ 0x00, 0x07, 0x00, 0xf0, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07,
+ 0x00, 0xf0, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
+ {
+ 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
+ {
+ 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
+ {
+ 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
+ {
+ 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfd, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
+ {
+ 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfb, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfb, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
+ {
+ 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfa, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
+ {
+ 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf8, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
+ {
+ 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf7, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf7, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
+ {
+ 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf6, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf6, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
+ {
+ 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf5, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
+ {
+ 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
+ {
+ 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf3, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf2, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x04, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0e, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio205x_t chan_info_nphyrev5_2056v5[] = {
+ {
+ 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
+ 0x00, 0x0f, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
+ {
+ 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
+ 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
+ {
+ 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
+ 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
+ {
+ 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
+ 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
+ {
+ 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
+ {
+ 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
+ {
+ 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
+ {
+ 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
+ {
+ 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
+ {
+ 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
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+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8},
+ {
+ 154, 5770, 0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x20, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7},
+ {
+ 155, 5775, 0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x20, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7},
+ {
+ 156, 5780, 0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6},
+ {
+ 157, 5785, 0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6},
+ {
+ 158, 5790, 0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6},
+ {
+ 159, 5795, 0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5},
+ {
+ 160, 5800, 0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5},
+ {
+ 161, 5805, 0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4},
+ {
+ 162, 5810, 0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4},
+ {
+ 163, 5815, 0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
+ {
+ 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
+ {
+ 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, 0x10, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x82, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
+ {
+ 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x72, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
+ {
+ 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x10, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x72, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
+ {
+ 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x72, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
+ {
+ 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x72, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
+ {
+ 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x71, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
+ {
+ 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x71, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
+ {
+ 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x71, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
+ {
+ 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x71, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
+ {
+ 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+ 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+ 0x00, 0x71, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
+ {
+ 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0b, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0b, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
+ {
+ 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0a, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
+ {
+ 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0f, 0x00, 0x0a, 0x00, 0x0e, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0f, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
+ {
+ 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
+ {
+ 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x0c, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
+ {
+ 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x0b, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
+ {
+ 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x09, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
+ {
+ 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x08, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x08, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
+ {
+ 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x07, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x07, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
+ {
+ 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x06, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x06, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
+ {
+ 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x05, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x05, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
+ {
+ 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x04, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x04, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x08, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x03, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x08, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x08, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio205x_t chan_info_nphyrev6_2056v6[] = {
+ {
+ 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
+ {
+ 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
+ {
+ 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
+ {
+ 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
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+ {
+ 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio205x_t chan_info_nphyrev5n6_2056v7[] = {
+ {
+ 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
+ 0x00, 0x0f, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
+ {
+ 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
+ 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
+ {
+ 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
+ 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
+ {
+ 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
+ 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
+ {
+ 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
+ {
+ 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
+ {
+ 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
+ {
+ 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
+ {
+ 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
+ {
+ 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
+ {
+ 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x09, 0x00, 0x70,
+ 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
+ {
+ 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x09, 0x00, 0x70,
+ 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+ 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
+ {
+ 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70,
+ 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+ 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
+ {
+ 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70,
+ 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+ 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
+ {
+ 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x70,
+ 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+ 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
+ {
+ 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x70,
+ 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+ 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
+ {
+ 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
+ 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+ 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
+ {
+ 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
+ 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+ 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
+ {
+ 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
+ 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+ 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
+ {
+ 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
+ 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+ 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
+ {
+ 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
+ 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+ 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
+ {
+ 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x70,
+ 0x00, 0x0a, 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a,
+ 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
+ {
+ 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70,
+ 0x00, 0x0a, 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a,
+ 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
+ {
+ 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70,
+ 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09,
+ 0x00, 0x6e, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
+ {
+ 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x06, 0x00, 0x70,
+ 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+ 0x00, 0x6e, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
+ {
+ 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
+ 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+ 0x00, 0x6e, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
+ {
+ 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
+ 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+ 0x00, 0x6e, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
+ {
+ 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
+ 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+ 0x00, 0x6e, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
+ {
+ 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
+ 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+ 0x00, 0x6e, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
+ {
+ 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xfe, 0xfa, 0x00, 0x06, 0x00, 0x70,
+ 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+ 0x00, 0x6e, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
+ {
+ 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xea, 0x00, 0x06, 0x00, 0x70,
+ 0x00, 0x08, 0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08,
+ 0x00, 0x6e, 0x00, 0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6},
+ {
+ 48, 5240, 0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xe9, 0x00, 0x05, 0x00, 0x70,
+ 0x00, 0x08, 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+ 0x00, 0x6d, 0x00, 0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5},
+ {
+ 50, 5250, 0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xed, 0xe9, 0x00, 0x05, 0x00, 0x70,
+ 0x00, 0x08, 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+ 0x00, 0x6d, 0x00, 0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4},
+ {
+ 52, 5260, 0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, 0xed, 0xd9, 0x00, 0x05, 0x00, 0x70,
+ 0x00, 0x08, 0x00, 0x9d, 0x00, 0xd9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+ 0x00, 0x6d, 0x00, 0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3},
+ {
+ 54, 5270, 0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, 0xed, 0xd8, 0x00, 0x04, 0x00, 0x70,
+ 0x00, 0x07, 0x00, 0x9c, 0x00, 0xd8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+ 0x00, 0x6c, 0x00, 0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2},
+ {
+ 56, 5280, 0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70,
+ 0x00, 0x07, 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+ 0x00, 0x6c, 0x00, 0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1},
+ {
+ 58, 5290, 0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70,
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+ {
+ 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x76, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
+ {
+ 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x66, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
+ {
+ 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x55, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
+ {
+ 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0e, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
+ {
+ 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
+ {
+ 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
+ {
+ 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x22, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x08, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x08, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0d, 0x00, 0x08, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio205x_t chan_info_nphyrev6_2056v8[] = {
+ {
+ 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
+ {
+ 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
+ {
+ 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
+ {
+ 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
+ {
+ 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
+ {
+ 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
+ {
+ 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
+ {
+ 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
+ {
+ 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
+ {
+ 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
+ {
+ 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
+ {
+ 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
+ {
+ 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
+ {
+ 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
+ {
+ 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
+ {
+ 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
+ {
+ 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
+ {
+ 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
+ {
+ 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
+ {
+ 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
+ {
+ 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
+ {
+ 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
+ {
+ 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
+ {
+ 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
+ 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
+ {
+ 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
+ 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
+ {
+ 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
+ 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e,
+ 0x00, 0x6f, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
+ {
+ 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
+ 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
+ {
+ 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77,
+ 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
+ {
+ 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77,
+ 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
+ {
+ 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77,
+ 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+ 0x00, 0x6f, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
+ {
+ 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77,
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+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x68, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
+ {
+ 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x68, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
+ {
+ 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0b, 0x00, 0x0a, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
+ {
+ 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0b, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
+ {
+ 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x67, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0b, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
+ {
+ 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x57, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
+ {
+ 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x56, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
+ {
+ 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x46, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
+ {
+ 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
+ {
+ 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
+ {
+ 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x23, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
+ {
+ 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x12, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
+ {
+ 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
+ {
+ 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio205x_t chan_info_nphyrev6_2056v11[] = {
+ {
+ 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
+ {
+ 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
+ {
+ 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
+ {
+ 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
+ {
+ 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
+ {
+ 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
+ {
+ 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
+ {
+ 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
+ {
+ 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
+ {
+ 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
+ {
+ 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
+ {
+ 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
+ {
+ 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
+ {
+ 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
+ {
+ 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
+ {
+ 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
+ {
+ 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
+ {
+ 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
+ {
+ 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
+ {
+ 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
+ {
+ 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
+ {
+ 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
+ {
+ 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77,
+ 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+ 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
+ {
+ 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
+ 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
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+ 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x05, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+ 0x00, 0x69, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
+ {
+ 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x69, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
+ {
+ 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x69, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
+ {
+ 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x69, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
+ {
+ 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x68, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
+ {
+ 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x68, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
+ {
+ 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x68, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
+ {
+ 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x68, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
+ {
+ 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x02, 0x0c, 0x01,
+ 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+ 0x00, 0x68, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
+ {
+ 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0b, 0x00, 0x0a, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
+ {
+ 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0b, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
+ {
+ 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x67, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0b, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
+ {
+ 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x57, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
+ {
+ 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x56, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
+ {
+ 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x46, 0x00, 0x03, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
+ {
+ 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
+ {
+ 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
+ {
+ 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x23, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
+ {
+ 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x12, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x0a, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
+ {
+ 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
+ {
+ 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x06, 0x06, 0x04, 0x2b, 0x01,
+ 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+ 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio2057_t chan_info_nphyrev7_2057_rev4[] = {
+ {
+ 184, 4920, 0x68, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xec, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07b4, 0x07b0, 0x07ac, 0x0214,
+ 0x0215,
+ 0x0216,
+ },
+ {
+ 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07b8, 0x07b4, 0x07b0, 0x0213,
+ 0x0214,
+ 0x0215,
+ },
+ {
+ 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07bc, 0x07b8, 0x07b4, 0x0212,
+ 0x0213,
+ 0x0214,
+ },
+ {
+ 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c0, 0x07bc, 0x07b8, 0x0211,
+ 0x0212,
+ 0x0213,
+ },
+ {
+ 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c4, 0x07c0, 0x07bc, 0x020f,
+ 0x0211,
+ 0x0212,
+ },
+ {
+ 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c8, 0x07c4, 0x07c0, 0x020e,
+ 0x020f,
+ 0x0211,
+ },
+ {
+ 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07cc, 0x07c8, 0x07c4, 0x020d,
+ 0x020e,
+ 0x020f,
+ },
+ {
+ 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d0, 0x07cc, 0x07c8, 0x020c,
+ 0x020d,
+ 0x020e,
+ },
+ {
+ 200, 5000, 0x82, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf4, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d4, 0x07d0, 0x07cc, 0x020b,
+ 0x020c,
+ 0x020d,
+ },
+ {
+ 202, 5010, 0x86, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf5, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d8, 0x07d4, 0x07d0, 0x020a,
+ 0x020b,
+ 0x020c,
+ },
+ {
+ 204, 5020, 0x89, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf6, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07dc, 0x07d8, 0x07d4, 0x0209,
+ 0x020a,
+ 0x020b,
+ },
+ {
+ 206, 5030, 0x8c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf7, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e0, 0x07dc, 0x07d8, 0x0208,
+ 0x0209,
+ 0x020a,
+ },
+ {
+ 208, 5040, 0x90, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf8, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e4, 0x07e0, 0x07dc, 0x0207,
+ 0x0208,
+ 0x0209,
+ },
+ {
+ 210, 5050, 0x93, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf9, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e8, 0x07e4, 0x07e0, 0x0206,
+ 0x0207,
+ 0x0208,
+ },
+ {
+ 212, 5060, 0x96, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfa, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xe3, 0x00, 0xef, 0x00,
+ 0x00, 0x0f, 0x0f, 0xe3, 0x00, 0xef, 0x07ec, 0x07e8, 0x07e4, 0x0205,
+ 0x0206,
+ 0x0207,
+ },
+ {
+ 214, 5070, 0x9a, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfb, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xef, 0x00,
+ 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xef, 0x07f0, 0x07ec, 0x07e8, 0x0204,
+ 0x0205,
+ 0x0206,
+ },
+ {
+ 216, 5080, 0x9d, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfc, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xef, 0x00,
+ 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xef, 0x07f4, 0x07f0, 0x07ec, 0x0203,
+ 0x0204,
+ 0x0205,
+ },
+ {
+ 218, 5090, 0xa0, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfd, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x00,
+ 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x07f8, 0x07f4, 0x07f0, 0x0202,
+ 0x0203,
+ 0x0204,
+ },
+ {
+ 220, 5100, 0xa4, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfe, 0x01, 0x0d,
+ 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x00,
+ 0x00, 0x0e, 0x0f, 0xe3, 0x00, 0xd6, 0x07fc, 0x07f8, 0x07f4, 0x0201,
+ 0x0202,
+ 0x0203,
+ },
+ {
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+ {
+ 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0f,
+ 0x0a, 0x00, 0x0a, 0x00, 0x71, 0xa3, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x71,
+ 0xa3, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cb, 0x03c7, 0x03c3, 0x0438,
+ 0x043d,
+ 0x0441,
+ },
+ {
+ 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0f,
+ 0x09, 0x00, 0x09, 0x00, 0x71, 0x93, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x71,
+ 0x93, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cd, 0x03c9, 0x03c5, 0x0436,
+ 0x043a,
+ 0x043f,
+ },
+ {
+ 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0f,
+ 0x09, 0x00, 0x09, 0x00, 0x71, 0x93, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x71,
+ 0x93, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cf, 0x03cb, 0x03c7, 0x0434,
+ 0x0438,
+ 0x043d,
+ },
+ {
+ 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0f,
+ 0x08, 0x00, 0x08, 0x00, 0x51, 0x83, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x51,
+ 0x83, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d1, 0x03cd, 0x03c9, 0x0431,
+ 0x0436,
+ 0x043a,
+ },
+ {
+ 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0f,
+ 0x08, 0x00, 0x08, 0x00, 0x51, 0x83, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x51,
+ 0x83, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d3, 0x03cf, 0x03cb, 0x042f,
+ 0x0434,
+ 0x0438,
+ },
+ {
+ 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0f,
+ 0x07, 0x00, 0x07, 0x00, 0x51, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x51,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d5, 0x03d1, 0x03cd, 0x042d,
+ 0x0431,
+ 0x0436,
+ },
+ {
+ 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0f,
+ 0x07, 0x00, 0x07, 0x00, 0x31, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d7, 0x03d3, 0x03cf, 0x042b,
+ 0x042f,
+ 0x0434,
+ },
+ {
+ 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0f,
+ 0x07, 0x00, 0x07, 0x00, 0x31, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d9, 0x03d5, 0x03d1, 0x0429,
+ 0x042d,
+ 0x0431,
+ },
+ {
+ 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0f,
+ 0x06, 0x00, 0x06, 0x00, 0x31, 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
+ 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03db, 0x03d7, 0x03d3, 0x0427,
+ 0x042b,
+ 0x042f,
+ },
+ {
+ 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0f,
+ 0x06, 0x00, 0x06, 0x00, 0x31, 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
+ 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03dd, 0x03d9, 0x03d5, 0x0424,
+ 0x0429,
+ 0x042d,
+ },
+ {
+ 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0f,
+ 0x05, 0x00, 0x05, 0x00, 0x11, 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x11,
+ 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03df, 0x03db, 0x03d7, 0x0422,
+ 0x0427,
+ 0x042b,
+ },
+ {
+ 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0f,
+ 0x05, 0x00, 0x05, 0x00, 0x11, 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x11,
+ 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03e1, 0x03dd, 0x03d9, 0x0420,
+ 0x0424,
+ 0x0429,
+ },
+ {
+ 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
+ 0x04, 0x00, 0x04, 0x00, 0x11, 0x43, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x11,
+ 0x43, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
+ 0x041f,
+ 0x0424}
+};
+
+static chan_info_nphy_radio2057_rev5_t chan_info_nphyrev8_2057_rev5[] = {
+ {
+ 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0d,
+ 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03c9, 0x03c5, 0x03c1,
+ 0x043a, 0x043f, 0x0443},
+ {
+ 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0d,
+ 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03cb, 0x03c7, 0x03c3,
+ 0x0438, 0x043d, 0x0441},
+ {
+ 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0d,
+ 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61, 0x03, 0xef, 0x03cd, 0x03c9, 0x03c5,
+ 0x0436, 0x043a, 0x043f},
+ {
+ 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0c,
+ 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61, 0x03, 0xdf, 0x03cf, 0x03cb, 0x03c7,
+ 0x0434, 0x0438, 0x043d},
+ {
+ 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0c,
+ 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61, 0x03, 0xcf, 0x03d1, 0x03cd, 0x03c9,
+ 0x0431, 0x0436, 0x043a},
+ {
+ 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0c,
+ 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61, 0x03, 0xbf, 0x03d3, 0x03cf, 0x03cb,
+ 0x042f, 0x0434, 0x0438},
+ {
+ 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0b,
+ 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61, 0x03, 0xaf, 0x03d5, 0x03d1, 0x03cd,
+ 0x042d, 0x0431, 0x0436},
+ {
+ 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0b,
+ 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61, 0x03, 0x9f, 0x03d7, 0x03d3, 0x03cf,
+ 0x042b, 0x042f, 0x0434},
+ {
+ 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0b,
+ 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61, 0x03, 0x8f, 0x03d9, 0x03d5, 0x03d1,
+ 0x0429, 0x042d, 0x0431},
+ {
+ 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0b,
+ 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61, 0x03, 0x7f, 0x03db, 0x03d7, 0x03d3,
+ 0x0427, 0x042b, 0x042f},
+ {
+ 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0b,
+ 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61, 0x03, 0x6f, 0x03dd, 0x03d9, 0x03d5,
+ 0x0424, 0x0429, 0x042d},
+ {
+ 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0b,
+ 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61, 0x03, 0x5f, 0x03df, 0x03db, 0x03d7,
+ 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0a,
+ 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61, 0x03, 0x4f, 0x03e1, 0x03dd, 0x03d9,
+ 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0a,
+ 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61, 0x03, 0x3f, 0x03e6, 0x03e2, 0x03de,
+ 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio2057_rev5_t chan_info_nphyrev9_2057_rev5v1[] = {
+ {
+ 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0d,
+ 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03c9, 0x03c5, 0x03c1,
+ 0x043a, 0x043f, 0x0443},
+ {
+ 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0d,
+ 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03cb, 0x03c7, 0x03c3,
+ 0x0438, 0x043d, 0x0441},
+ {
+ 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0d,
+ 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61, 0x03, 0xef, 0x03cd, 0x03c9, 0x03c5,
+ 0x0436, 0x043a, 0x043f},
+ {
+ 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0c,
+ 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61, 0x03, 0xdf, 0x03cf, 0x03cb, 0x03c7,
+ 0x0434, 0x0438, 0x043d},
+ {
+ 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0c,
+ 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61, 0x03, 0xcf, 0x03d1, 0x03cd, 0x03c9,
+ 0x0431, 0x0436, 0x043a},
+ {
+ 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0c,
+ 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61, 0x03, 0xbf, 0x03d3, 0x03cf, 0x03cb,
+ 0x042f, 0x0434, 0x0438},
+ {
+ 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0b,
+ 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61, 0x03, 0xaf, 0x03d5, 0x03d1, 0x03cd,
+ 0x042d, 0x0431, 0x0436},
+ {
+ 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0b,
+ 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61, 0x03, 0x9f, 0x03d7, 0x03d3, 0x03cf,
+ 0x042b, 0x042f, 0x0434},
+ {
+ 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0b,
+ 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61, 0x03, 0x8f, 0x03d9, 0x03d5, 0x03d1,
+ 0x0429, 0x042d, 0x0431},
+ {
+ 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0b,
+ 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61, 0x03, 0x7f, 0x03db, 0x03d7, 0x03d3,
+ 0x0427, 0x042b, 0x042f},
+ {
+ 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0b,
+ 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61, 0x03, 0x6f, 0x03dd, 0x03d9, 0x03d5,
+ 0x0424, 0x0429, 0x042d},
+ {
+ 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0b,
+ 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61, 0x03, 0x5f, 0x03df, 0x03db, 0x03d7,
+ 0x0422, 0x0427, 0x042b},
+ {
+ 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0a,
+ 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61, 0x03, 0x4f, 0x03e1, 0x03dd, 0x03d9,
+ 0x0420, 0x0424, 0x0429},
+ {
+ 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0a,
+ 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61, 0x03, 0x3f, 0x03e6, 0x03e2, 0x03de,
+ 0x041b, 0x041f, 0x0424}
+};
+
+static chan_info_nphy_radio2057_t chan_info_nphyrev8_2057_rev7[] = {
+ {
+ 184, 4920, 0x68, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xec, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b4, 0x07b0, 0x07ac, 0x0214,
+ 0x0215,
+ 0x0216},
+ {
+ 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b8, 0x07b4, 0x07b0, 0x0213,
+ 0x0214,
+ 0x0215},
+ {
+ 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07bc, 0x07b8, 0x07b4, 0x0212,
+ 0x0213,
+ 0x0214},
+ {
+ 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c0, 0x07bc, 0x07b8, 0x0211,
+ 0x0212,
+ 0x0213},
+ {
+ 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c4, 0x07c0, 0x07bc, 0x020f,
+ 0x0211,
+ 0x0212},
+ {
+ 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c8, 0x07c4, 0x07c0, 0x020e,
+ 0x020f,
+ 0x0211},
+ {
+ 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07cc, 0x07c8, 0x07c4, 0x020d,
+ 0x020e,
+ 0x020f},
+ {
+ 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07d0, 0x07cc, 0x07c8, 0x020c,
+ 0x020d,
+ 0x020e},
+ {
+ 200, 5000, 0x82, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf4, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d4, 0x07d0, 0x07cc, 0x020b,
+ 0x020c,
+ 0x020d},
+ {
+ 202, 5010, 0x86, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf5, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d8, 0x07d4, 0x07d0, 0x020a,
+ 0x020b,
+ 0x020c},
+ {
+ 204, 5020, 0x89, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf6, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07dc, 0x07d8, 0x07d4, 0x0209,
+ 0x020a,
+ 0x020b},
+ {
+ 206, 5030, 0x8c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf7, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e0, 0x07dc, 0x07d8, 0x0208,
+ 0x0209,
+ 0x020a},
+ {
+ 208, 5040, 0x90, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf8, 0x01, 0x0e,
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+ 0x00, 0x04, 0x00, 0x44, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
+ 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0930, 0x092c, 0x0928, 0x01be,
+ 0x01bf,
+ 0x01bf},
+ {
+ 176, 5880, 0xa8, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4c, 0x02, 0x03,
+ 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
+ 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd,
+ 0x01be,
+ 0x01bf},
+ {
+ 178, 5890, 0xab, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4d, 0x02, 0x03,
+ 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
+ 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc,
+ 0x01bd,
+ 0x01be},
+ {
+ 180, 5900, 0xae, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4e, 0x02, 0x03,
+ 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
+ 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc,
+ 0x01bc,
+ 0x01bd},
+ {
+ 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0f,
+ 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03c9, 0x03c5, 0x03c1, 0x043a,
+ 0x043f,
+ 0x0443},
+ {
+ 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0f,
+ 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cb, 0x03c7, 0x03c3, 0x0438,
+ 0x043d,
+ 0x0441},
+ {
+ 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0f,
+ 0x09, 0x00, 0x09, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cd, 0x03c9, 0x03c5, 0x0436,
+ 0x043a,
+ 0x043f},
+ {
+ 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0f,
+ 0x09, 0x00, 0x09, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cf, 0x03cb, 0x03c7, 0x0434,
+ 0x0438,
+ 0x043d},
+ {
+ 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0f,
+ 0x08, 0x00, 0x08, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d1, 0x03cd, 0x03c9, 0x0431,
+ 0x0436,
+ 0x043a},
+ {
+ 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0f,
+ 0x08, 0x00, 0x08, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d3, 0x03cf, 0x03cb, 0x042f,
+ 0x0434,
+ 0x0438},
+ {
+ 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0f,
+ 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d5, 0x03d1, 0x03cd, 0x042d,
+ 0x0431,
+ 0x0436},
+ {
+ 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0f,
+ 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d7, 0x03d3, 0x03cf, 0x042b,
+ 0x042f,
+ 0x0434},
+ {
+ 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0f,
+ 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d9, 0x03d5, 0x03d1, 0x0429,
+ 0x042d,
+ 0x0431},
+ {
+ 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0f,
+ 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03db, 0x03d7, 0x03d3, 0x0427,
+ 0x042b,
+ 0x042f},
+ {
+ 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0f,
+ 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03dd, 0x03d9, 0x03d5, 0x0424,
+ 0x0429,
+ 0x042d},
+ {
+ 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0f,
+ 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03df, 0x03db, 0x03d7, 0x0422,
+ 0x0427,
+ 0x042b},
+ {
+ 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0f,
+ 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03e1, 0x03dd, 0x03d9, 0x0420,
+ 0x0424,
+ 0x0429},
+ {
+ 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
+ 0x04, 0x00, 0x04, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
+ 0x041f,
+ 0x0424}
+};
+
+static chan_info_nphy_radio2057_t chan_info_nphyrev8_2057_rev8[] = {
+ {
+ 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b8, 0x07b4, 0x07b0, 0x0213,
+ 0x0214,
+ 0x0215},
+ {
+ 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07bc, 0x07b8, 0x07b4, 0x0212,
+ 0x0213,
+ 0x0214},
+ {
+ 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c0, 0x07bc, 0x07b8, 0x0211,
+ 0x0212,
+ 0x0213},
+ {
+ 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c4, 0x07c0, 0x07bc, 0x020f,
+ 0x0211,
+ 0x0212},
+ {
+ 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c8, 0x07c4, 0x07c0, 0x020e,
+ 0x020f,
+ 0x0211},
+ {
+ 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07cc, 0x07c8, 0x07c4, 0x020d,
+ 0x020e,
+ 0x020f},
+ {
+ 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07d0, 0x07cc, 0x07c8, 0x020c,
+ 0x020d,
+ 0x020e},
+ {
+ 200, 5000, 0x82, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf4, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d4, 0x07d0, 0x07cc, 0x020b,
+ 0x020c,
+ 0x020d},
+ {
+ 202, 5010, 0x86, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf5, 0x01, 0x0f,
+ 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d8, 0x07d4, 0x07d0, 0x020a,
+ 0x020b,
+ 0x020c},
+ {
+ 204, 5020, 0x89, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf6, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07dc, 0x07d8, 0x07d4, 0x0209,
+ 0x020a,
+ 0x020b},
+ {
+ 206, 5030, 0x8c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf7, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e0, 0x07dc, 0x07d8, 0x0208,
+ 0x0209,
+ 0x020a},
+ {
+ 208, 5040, 0x90, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf8, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e4, 0x07e0, 0x07dc, 0x0207,
+ 0x0208,
+ 0x0209},
+ {
+ 210, 5050, 0x93, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf9, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e8, 0x07e4, 0x07e0, 0x0206,
+ 0x0207,
+ 0x0208},
+ {
+ 212, 5060, 0x96, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfa, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07ec, 0x07e8, 0x07e4, 0x0205,
+ 0x0206,
+ 0x0207},
+ {
+ 214, 5070, 0x9a, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfb, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f0, 0x07ec, 0x07e8, 0x0204,
+ 0x0205,
+ 0x0206},
+ {
+ 216, 5080, 0x9d, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfc, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f4, 0x07f0, 0x07ec, 0x0203,
+ 0x0204,
+ 0x0205},
+ {
+ 218, 5090, 0xa0, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfd, 0x01, 0x0e,
+ 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
+ 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f8, 0x07f4, 0x07f0, 0x0202,
+ 0x0203,
+ 0x0204},
+ {
+ 220, 5100, 0xa4, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfe, 0x01, 0x0d,
+ 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x07fc, 0x07f8, 0x07f4, 0x0201,
+ 0x0202,
+ 0x0203},
+ {
+ 222, 5110, 0xa7, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xff, 0x01, 0x0d,
+ 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0800, 0x07fc, 0x07f8, 0x0200,
+ 0x0201,
+ 0x0202},
+ {
+ 224, 5120, 0xaa, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x02, 0x0d,
+ 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0804, 0x0800, 0x07fc, 0x01ff,
+ 0x0200,
+ 0x0201},
+ {
+ 226, 5130, 0xae, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x01, 0x02, 0x0d,
+ 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0808, 0x0804, 0x0800, 0x01fe,
+ 0x01ff,
+ 0x0200},
+ {
+ 228, 5140, 0xb1, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x02, 0x02, 0x0d,
+ 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x080c, 0x0808, 0x0804, 0x01fd,
+ 0x01fe,
+ 0x01ff},
+ {
+ 32, 5160, 0xb8, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x04, 0x02, 0x0d,
+ 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0814, 0x0810, 0x080c, 0x01fb,
+ 0x01fc,
+ 0x01fd},
+ {
+ 34, 5170, 0xbb, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x05, 0x02, 0x0d,
+ 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0818, 0x0814, 0x0810, 0x01fa,
+ 0x01fb,
+ 0x01fc},
+ {
+ 36, 5180, 0xbe, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x06, 0x02, 0x0c,
+ 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x081c, 0x0818, 0x0814, 0x01f9,
+ 0x01fa,
+ 0x01fb},
+ {
+ 38, 5190, 0xc2, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x07, 0x02, 0x0c,
+ 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
+ 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0820, 0x081c, 0x0818, 0x01f8,
+ 0x01f9,
+ 0x01fa},
+ {
+ 40, 5200, 0xc5, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x08, 0x02, 0x0c,
+ 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0f, 0x0f, 0x93, 0x00, 0xf8, 0x00,
+ 0x00, 0x0f, 0x0f, 0x93, 0x00, 0xf8, 0x0824, 0x0820, 0x081c, 0x01f7,
+ 0x01f8,
+ 0x01f9},
+ {
+ 42, 5210, 0xc8, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x09, 0x02, 0x0c,
+ 0x00, 0x0c, 0x00, 0xcc, 0x00, 0x00, 0x0f, 0x0f, 0x93, 0x00, 0xf8, 0x00,
+ 0x00, 0x0f, 0x0f, 0x93, 0x00, 0xf8, 0x0828, 0x0824, 0x0820, 0x01f6,
+ 0x01f7,
+ 0x01f8},
+ {
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+ 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
+ 0x04, 0x00, 0x04, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x61,
+ 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
+ 0x041f,
+ 0x0424}
+};
+
+radio_regs_t regs_2055[] = {
+ {0x02, 0x80, 0x80, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0x27, 0x27, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0x27, 0x27, 0, 0},
+ {0x07, 0x7f, 0x7f, 1, 1},
+ {0x08, 0x7, 0x7, 1, 1},
+ {0x09, 0x7f, 0x7f, 1, 1},
+ {0x0A, 0x7, 0x7, 1, 1},
+ {0x0B, 0x15, 0x15, 0, 0},
+ {0x0C, 0x15, 0x15, 0, 0},
+ {0x0D, 0x4f, 0x4f, 1, 1},
+ {0x0E, 0x5, 0x5, 1, 1},
+ {0x0F, 0x4f, 0x4f, 1, 1},
+ {0x10, 0x5, 0x5, 1, 1},
+ {0x11, 0xd0, 0xd0, 0, 0},
+ {0x12, 0x2, 0x2, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0x40, 0x40, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0xc0, 0xc0, 0, 0},
+ {0x1E, 0xff, 0xff, 0, 0},
+ {0x1F, 0xc0, 0xc0, 0, 0},
+ {0x20, 0xff, 0xff, 0, 0},
+ {0x21, 0xc0, 0xc0, 0, 0},
+ {0x22, 0, 0, 0, 0},
+ {0x23, 0x2c, 0x2c, 0, 0},
+ {0x24, 0, 0, 0, 0},
+ {0x25, 0, 0, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0, 0, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0, 0, 0, 0},
+ {0x2A, 0, 0, 0, 0},
+ {0x2B, 0, 0, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0xa4, 0xa4, 0, 0},
+ {0x2E, 0x38, 0x38, 0, 0},
+ {0x2F, 0, 0, 0, 0},
+ {0x30, 0x4, 0x4, 1, 1},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0xa, 0xa, 0, 0},
+ {0x33, 0x87, 0x87, 0, 0},
+ {0x34, 0x9, 0x9, 0, 0},
+ {0x35, 0x70, 0x70, 0, 0},
+ {0x36, 0x11, 0x11, 0, 0},
+ {0x37, 0x18, 0x18, 1, 1},
+ {0x38, 0x6, 0x6, 0, 0},
+ {0x39, 0x4, 0x4, 1, 1},
+ {0x3A, 0x6, 0x6, 0, 0},
+ {0x3B, 0x9e, 0x9e, 0, 0},
+ {0x3C, 0x9, 0x9, 0, 0},
+ {0x3D, 0xc8, 0xc8, 1, 1},
+ {0x3E, 0x88, 0x88, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0, 0, 0, 0},
+ {0x42, 0x1, 0x1, 0, 0},
+ {0x43, 0x2, 0x2, 0, 0},
+ {0x44, 0x96, 0x96, 0, 0},
+ {0x45, 0x3e, 0x3e, 0, 0},
+ {0x46, 0x3e, 0x3e, 0, 0},
+ {0x47, 0x13, 0x13, 0, 0},
+ {0x48, 0x2, 0x2, 0, 0},
+ {0x49, 0x15, 0x15, 0, 0},
+ {0x4A, 0x7, 0x7, 0, 0},
+ {0x4B, 0, 0, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0, 0, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0, 0, 0, 0},
+ {0x50, 0x8, 0x8, 0, 0},
+ {0x51, 0x8, 0x8, 0, 0},
+ {0x52, 0x6, 0x6, 0, 0},
+ {0x53, 0x84, 0x84, 1, 1},
+ {0x54, 0xc3, 0xc3, 0, 0},
+ {0x55, 0x8f, 0x8f, 0, 0},
+ {0x56, 0xff, 0xff, 0, 0},
+ {0x57, 0xff, 0xff, 0, 0},
+ {0x58, 0x88, 0x88, 0, 0},
+ {0x59, 0x88, 0x88, 0, 0},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0xcc, 0xcc, 0, 0},
+ {0x5C, 0x6, 0x6, 0, 0},
+ {0x5D, 0x80, 0x80, 0, 0},
+ {0x5E, 0x80, 0x80, 0, 0},
+ {0x5F, 0xf8, 0xf8, 0, 0},
+ {0x60, 0x88, 0x88, 0, 0},
+ {0x61, 0x88, 0x88, 0, 0},
+ {0x62, 0x88, 0x8, 1, 1},
+ {0x63, 0x88, 0x88, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0x1, 0x1, 1, 1},
+ {0x66, 0x8a, 0x8a, 0, 0},
+ {0x67, 0x8, 0x8, 0, 0},
+ {0x68, 0x83, 0x83, 0, 0},
+ {0x69, 0x6, 0x6, 0, 0},
+ {0x6A, 0xa0, 0xa0, 0, 0},
+ {0x6B, 0xa, 0xa, 0, 0},
+ {0x6C, 0x87, 0x87, 1, 1},
+ {0x6D, 0x2a, 0x2a, 0, 0},
+ {0x6E, 0x2a, 0x2a, 0, 0},
+ {0x6F, 0x2a, 0x2a, 0, 0},
+ {0x70, 0x2a, 0x2a, 0, 0},
+ {0x71, 0x18, 0x18, 0, 0},
+ {0x72, 0x6a, 0x6a, 1, 1},
+ {0x73, 0xab, 0xab, 1, 1},
+ {0x74, 0x13, 0x13, 1, 1},
+ {0x75, 0xc1, 0xc1, 1, 1},
+ {0x76, 0xaa, 0xaa, 1, 1},
+ {0x77, 0x87, 0x87, 1, 1},
+ {0x78, 0, 0, 0, 0},
+ {0x79, 0x6, 0x6, 0, 0},
+ {0x7A, 0x7, 0x7, 0, 0},
+ {0x7B, 0x7, 0x7, 0, 0},
+ {0x7C, 0x15, 0x15, 0, 0},
+ {0x7D, 0x55, 0x55, 0, 0},
+ {0x7E, 0x97, 0x97, 1, 1},
+ {0x7F, 0x8, 0x8, 0, 0},
+ {0x80, 0x14, 0x14, 1, 1},
+ {0x81, 0x33, 0x33, 0, 0},
+ {0x82, 0x88, 0x88, 0, 0},
+ {0x83, 0x6, 0x6, 0, 0},
+ {0x84, 0x3, 0x3, 1, 1},
+ {0x85, 0xa, 0xa, 0, 0},
+ {0x86, 0x3, 0x3, 1, 1},
+ {0x87, 0x2a, 0x2a, 0, 0},
+ {0x88, 0xa4, 0xa4, 0, 0},
+ {0x89, 0x18, 0x18, 0, 0},
+ {0x8A, 0x28, 0x28, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0x4a, 0x4a, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0xf8, 0xf8, 0, 0},
+ {0x8F, 0x88, 0x88, 0, 0},
+ {0x90, 0x88, 0x88, 0, 0},
+ {0x91, 0x88, 0x8, 1, 1},
+ {0x92, 0x88, 0x88, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0x1, 0x1, 1, 1},
+ {0x95, 0x8a, 0x8a, 0, 0},
+ {0x96, 0x8, 0x8, 0, 0},
+ {0x97, 0x83, 0x83, 0, 0},
+ {0x98, 0x6, 0x6, 0, 0},
+ {0x99, 0xa0, 0xa0, 0, 0},
+ {0x9A, 0xa, 0xa, 0, 0},
+ {0x9B, 0x87, 0x87, 1, 1},
+ {0x9C, 0x2a, 0x2a, 0, 0},
+ {0x9D, 0x2a, 0x2a, 0, 0},
+ {0x9E, 0x2a, 0x2a, 0, 0},
+ {0x9F, 0x2a, 0x2a, 0, 0},
+ {0xA0, 0x18, 0x18, 0, 0},
+ {0xA1, 0x6a, 0x6a, 1, 1},
+ {0xA2, 0xab, 0xab, 1, 1},
+ {0xA3, 0x13, 0x13, 1, 1},
+ {0xA4, 0xc1, 0xc1, 1, 1},
+ {0xA5, 0xaa, 0xaa, 1, 1},
+ {0xA6, 0x87, 0x87, 1, 1},
+ {0xA7, 0, 0, 0, 0},
+ {0xA8, 0x6, 0x6, 0, 0},
+ {0xA9, 0x7, 0x7, 0, 0},
+ {0xAA, 0x7, 0x7, 0, 0},
+ {0xAB, 0x15, 0x15, 0, 0},
+ {0xAC, 0x55, 0x55, 0, 0},
+ {0xAD, 0x97, 0x97, 1, 1},
+ {0xAE, 0x8, 0x8, 0, 0},
+ {0xAF, 0x14, 0x14, 1, 1},
+ {0xB0, 0x33, 0x33, 0, 0},
+ {0xB1, 0x88, 0x88, 0, 0},
+ {0xB2, 0x6, 0x6, 0, 0},
+ {0xB3, 0x3, 0x3, 1, 1},
+ {0xB4, 0xa, 0xa, 0, 0},
+ {0xB5, 0x3, 0x3, 1, 1},
+ {0xB6, 0x2a, 0x2a, 0, 0},
+ {0xB7, 0xa4, 0xa4, 0, 0},
+ {0xB8, 0x18, 0x18, 0, 0},
+ {0xB9, 0x28, 0x28, 0, 0},
+ {0xBA, 0, 0, 0, 0},
+ {0xBB, 0x4a, 0x4a, 0, 0},
+ {0xBC, 0, 0, 0, 0},
+ {0xBD, 0x71, 0x71, 0, 0},
+ {0xBE, 0x72, 0x72, 0, 0},
+ {0xBF, 0x73, 0x73, 0, 0},
+ {0xC0, 0x74, 0x74, 0, 0},
+ {0xC1, 0x75, 0x75, 0, 0},
+ {0xC2, 0x76, 0x76, 0, 0},
+ {0xC3, 0x77, 0x77, 0, 0},
+ {0xC4, 0x78, 0x78, 0, 0},
+ {0xC5, 0x79, 0x79, 0, 0},
+ {0xC6, 0x7a, 0x7a, 0, 0},
+ {0xC7, 0, 0, 0, 0},
+ {0xC8, 0, 0, 0, 0},
+ {0xC9, 0, 0, 0, 0},
+ {0xCA, 0, 0, 0, 0},
+ {0xCB, 0, 0, 0, 0},
+ {0xCC, 0, 0, 0, 0},
+ {0xCD, 0, 0, 0, 0},
+ {0xCE, 0x6, 0x6, 0, 0},
+ {0xCF, 0, 0, 0, 0},
+ {0xD0, 0, 0, 0, 0},
+ {0xD1, 0x18, 0x18, 0, 0},
+ {0xD2, 0x88, 0x88, 0, 0},
+ {0xD3, 0, 0, 0, 0},
+ {0xD4, 0, 0, 0, 0},
+ {0xD5, 0, 0, 0, 0},
+ {0xD6, 0, 0, 0, 0},
+ {0xD7, 0, 0, 0, 0},
+ {0xD8, 0, 0, 0, 0},
+ {0xD9, 0, 0, 0, 0},
+ {0xDA, 0x6, 0x6, 0, 0},
+ {0xDB, 0, 0, 0, 0},
+ {0xDC, 0, 0, 0, 0},
+ {0xDD, 0x18, 0x18, 0, 0},
+ {0xDE, 0x88, 0x88, 0, 0},
+ {0xDF, 0, 0, 0, 0},
+ {0xE0, 0, 0, 0, 0},
+ {0xE1, 0, 0, 0, 0},
+ {0xE2, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_SYN_2056[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0x1, 0x1, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0x60, 0x60, 0, 0},
+ {0x23, 0x6, 0x6, 0, 0},
+ {0x24, 0xc, 0xc, 0, 0},
+ {0x25, 0, 0, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0, 0, 0, 0},
+ {0x28, 0x1, 0x1, 0, 0},
+ {0x29, 0, 0, 0, 0},
+ {0x2A, 0, 0, 0, 0},
+ {0x2B, 0, 0, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0xd, 0xd, 0, 0},
+ {0x2F, 0x1f, 0x1f, 0, 0},
+ {0x30, 0x15, 0x15, 0, 0},
+ {0x31, 0xf, 0xf, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0, 0, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0, 0, 0, 0},
+ {0x38, 0, 0, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0, 0, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x13, 0x13, 0, 0},
+ {0x3D, 0xf, 0xf, 0, 0},
+ {0x3E, 0x18, 0x18, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x20, 0x20, 0, 0},
+ {0x42, 0x20, 0x20, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x77, 0x77, 0, 0},
+ {0x45, 0x7, 0x7, 0, 0},
+ {0x46, 0x1, 0x1, 0, 0},
+ {0x47, 0x4, 0x4, 0, 0},
+ {0x48, 0xf, 0xf, 0, 0},
+ {0x49, 0x30, 0x30, 0, 0},
+ {0x4A, 0x32, 0x32, 0, 0},
+ {0x4B, 0xd, 0xd, 0, 0},
+ {0x4C, 0xd, 0xd, 0, 0},
+ {0x4D, 0x4, 0x4, 0, 0},
+ {0x4E, 0x6, 0x6, 0, 0},
+ {0x4F, 0x1, 0x1, 0, 0},
+ {0x50, 0x1c, 0x1c, 0, 0},
+ {0x51, 0x2, 0x2, 0, 0},
+ {0x52, 0x2, 0x2, 0, 0},
+ {0x53, 0xf7, 0xf7, 1, 1},
+ {0x54, 0xb4, 0xb4, 0, 0},
+ {0x55, 0xd2, 0xd2, 0, 0},
+ {0x56, 0, 0, 0, 0},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x4, 0x4, 0, 0},
+ {0x59, 0x96, 0x96, 0, 0},
+ {0x5A, 0x3e, 0x3e, 0, 0},
+ {0x5B, 0x3e, 0x3e, 0, 0},
+ {0x5C, 0x13, 0x13, 0, 0},
+ {0x5D, 0x2, 0x2, 0, 0},
+ {0x5E, 0, 0, 0, 0},
+ {0x5F, 0x7, 0x7, 0, 0},
+ {0x60, 0x7, 0x7, 1, 1},
+ {0x61, 0x8, 0x8, 0, 0},
+ {0x62, 0x3, 0x3, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0x40, 0x40, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0x1, 0x1, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0x60, 0x60, 0, 0},
+ {0x71, 0x66, 0x66, 0, 0},
+ {0x72, 0xc, 0xc, 0, 0},
+ {0x73, 0x66, 0x66, 0, 0},
+ {0x74, 0x8f, 0x8f, 1, 1},
+ {0x75, 0, 0, 0, 0},
+ {0x76, 0xcc, 0xcc, 0, 0},
+ {0x77, 0x1, 0x1, 0, 0},
+ {0x78, 0x66, 0x66, 0, 0},
+ {0x79, 0x66, 0x66, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0xff, 0xff, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0x95, 0, 0, 0, 0},
+ {0x96, 0, 0, 0, 0},
+ {0x97, 0, 0, 0, 0},
+ {0x98, 0, 0, 0, 0},
+ {0x99, 0, 0, 0, 0},
+ {0x9A, 0, 0, 0, 0},
+ {0x9B, 0, 0, 0, 0},
+ {0x9C, 0, 0, 0, 0},
+ {0x9D, 0, 0, 0, 0},
+ {0x9E, 0, 0, 0, 0},
+ {0x9F, 0x6, 0x6, 0, 0},
+ {0xA0, 0x66, 0x66, 0, 0},
+ {0xA1, 0x66, 0x66, 0, 0},
+ {0xA2, 0x66, 0x66, 0, 0},
+ {0xA3, 0x66, 0x66, 0, 0},
+ {0xA4, 0x66, 0x66, 0, 0},
+ {0xA5, 0x66, 0x66, 0, 0},
+ {0xA6, 0x66, 0x66, 0, 0},
+ {0xA7, 0x66, 0x66, 0, 0},
+ {0xA8, 0x66, 0x66, 0, 0},
+ {0xA9, 0x66, 0x66, 0, 0},
+ {0xAA, 0x66, 0x66, 0, 0},
+ {0xAB, 0x66, 0x66, 0, 0},
+ {0xAC, 0x66, 0x66, 0, 0},
+ {0xAD, 0x66, 0x66, 0, 0},
+ {0xAE, 0x66, 0x66, 0, 0},
+ {0xAF, 0x66, 0x66, 0, 0},
+ {0xB0, 0x66, 0x66, 0, 0},
+ {0xB1, 0x66, 0x66, 0, 0},
+ {0xB2, 0x66, 0x66, 0, 0},
+ {0xB3, 0xa, 0xa, 0, 0},
+ {0xB4, 0, 0, 0, 0},
+ {0xB5, 0, 0, 0, 0},
+ {0xB6, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_TX_2056[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0x88, 0x88, 0, 0},
+ {0x22, 0x88, 0x88, 0, 0},
+ {0x23, 0x88, 0x88, 0, 0},
+ {0x24, 0x88, 0x88, 0, 0},
+ {0x25, 0xc, 0xc, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0x3, 0x3, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0x3, 0x3, 0, 0},
+ {0x2A, 0x37, 0x37, 0, 0},
+ {0x2B, 0x3, 0x3, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0x1, 0x1, 0, 0},
+ {0x2F, 0x1, 0x1, 0, 0},
+ {0x30, 0, 0, 0, 0},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0x11, 0x11, 0, 0},
+ {0x34, 0x11, 0x11, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0x3, 0x3, 0, 0},
+ {0x38, 0xf, 0xf, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0x2d, 0x2d, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x6e, 0x6e, 0, 0},
+ {0x3D, 0xf0, 0xf0, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x3, 0x3, 0, 0},
+ {0x42, 0x3, 0x3, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x1e, 0x1e, 0, 0},
+ {0x45, 0, 0, 0, 0},
+ {0x46, 0x6e, 0x6e, 0, 0},
+ {0x47, 0xf0, 0xf0, 1, 1},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x2, 0x2, 0, 0},
+ {0x4A, 0xff, 0xff, 1, 1},
+ {0x4B, 0xc, 0xc, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0x38, 0x38, 0, 0},
+ {0x4E, 0x70, 0x70, 1, 1},
+ {0x4F, 0x2, 0x2, 0, 0},
+ {0x50, 0x88, 0x88, 0, 0},
+ {0x51, 0xc, 0xc, 0, 0},
+ {0x52, 0, 0, 0, 0},
+ {0x53, 0x8, 0x8, 0, 0},
+ {0x54, 0x70, 0x70, 1, 1},
+ {0x55, 0x2, 0x2, 0, 0},
+ {0x56, 0xff, 0xff, 1, 1},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x83, 0x83, 0, 0},
+ {0x59, 0x77, 0x77, 1, 1},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x88, 0x88, 0, 0},
+ {0x5D, 0, 0, 0, 0},
+ {0x5E, 0x8, 0x8, 0, 0},
+ {0x5F, 0x77, 0x77, 1, 1},
+ {0x60, 0x1, 0x1, 0, 0},
+ {0x61, 0, 0, 0, 0},
+ {0x62, 0x7, 0x7, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0x7, 0x7, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0x74, 0x74, 1, 1},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0xa, 0xa, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0x2, 0x2, 0, 0},
+ {0x72, 0, 0, 0, 0},
+ {0x73, 0, 0, 0, 0},
+ {0x74, 0xe, 0xe, 0, 0},
+ {0x75, 0xe, 0xe, 0, 0},
+ {0x76, 0xe, 0xe, 0, 0},
+ {0x77, 0x13, 0x13, 0, 0},
+ {0x78, 0x13, 0x13, 0, 0},
+ {0x79, 0x1b, 0x1b, 0, 0},
+ {0x7A, 0x1b, 0x1b, 0, 0},
+ {0x7B, 0x55, 0x55, 0, 0},
+ {0x7C, 0x5b, 0x5b, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_RX_2056[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0x3, 0x3, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0, 0, 0, 0},
+ {0x23, 0x90, 0x90, 0, 0},
+ {0x24, 0x55, 0x55, 0, 0},
+ {0x25, 0x15, 0x15, 0, 0},
+ {0x26, 0x5, 0x5, 0, 0},
+ {0x27, 0x15, 0x15, 0, 0},
+ {0x28, 0x5, 0x5, 0, 0},
+ {0x29, 0x20, 0x20, 0, 0},
+ {0x2A, 0x11, 0x11, 0, 0},
+ {0x2B, 0x90, 0x90, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0x88, 0x88, 0, 0},
+ {0x2E, 0x32, 0x32, 0, 0},
+ {0x2F, 0x77, 0x77, 0, 0},
+ {0x30, 0x17, 0x17, 1, 1},
+ {0x31, 0xff, 0xff, 1, 1},
+ {0x32, 0x20, 0x20, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0x88, 0x88, 0, 0},
+ {0x35, 0x32, 0x32, 0, 0},
+ {0x36, 0x77, 0x77, 0, 0},
+ {0x37, 0x17, 0x17, 1, 1},
+ {0x38, 0xf0, 0xf0, 1, 1},
+ {0x39, 0x20, 0x20, 0, 0},
+ {0x3A, 0x8, 0x8, 0, 0},
+ {0x3B, 0x99, 0x99, 0, 0},
+ {0x3C, 0, 0, 0, 0},
+ {0x3D, 0x44, 0x44, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0x44, 0x44, 0, 0},
+ {0x40, 0xf, 0xf, 1, 1},
+ {0x41, 0x6, 0x6, 0, 0},
+ {0x42, 0x4, 0x4, 0, 0},
+ {0x43, 0x50, 0x50, 1, 1},
+ {0x44, 0x8, 0x8, 0, 0},
+ {0x45, 0x99, 0x99, 0, 0},
+ {0x46, 0, 0, 0, 0},
+ {0x47, 0x11, 0x11, 0, 0},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x44, 0x44, 0, 0},
+ {0x4A, 0x7, 0x7, 0, 0},
+ {0x4B, 0x6, 0x6, 0, 0},
+ {0x4C, 0x4, 0x4, 0, 0},
+ {0x4D, 0, 0, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0x66, 0x66, 0, 0},
+ {0x50, 0x66, 0x66, 0, 0},
+ {0x51, 0x57, 0x57, 0, 0},
+ {0x52, 0x57, 0x57, 0, 0},
+ {0x53, 0x44, 0x44, 0, 0},
+ {0x54, 0, 0, 0, 0},
+ {0x55, 0, 0, 0, 0},
+ {0x56, 0x8, 0x8, 0, 0},
+ {0x57, 0x8, 0x8, 0, 0},
+ {0x58, 0x7, 0x7, 0, 0},
+ {0x59, 0x22, 0x22, 0, 0},
+ {0x5A, 0x22, 0x22, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x23, 0x23, 0, 0},
+ {0x5D, 0x7, 0x7, 0, 0},
+ {0x5E, 0x55, 0x55, 0, 0},
+ {0x5F, 0x23, 0x23, 0, 0},
+ {0x60, 0x41, 0x41, 0, 0},
+ {0x61, 0x1, 0x1, 0, 0},
+ {0x62, 0xa, 0xa, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0xc, 0xc, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0, 0, 0, 0},
+ {0x72, 0x22, 0x22, 0, 0},
+ {0x73, 0x22, 0x22, 0, 0},
+ {0x74, 0x2, 0x2, 0, 0},
+ {0x75, 0xa, 0xa, 0, 0},
+ {0x76, 0x1, 0x1, 0, 0},
+ {0x77, 0x22, 0x22, 0, 0},
+ {0x78, 0x30, 0x30, 0, 0},
+ {0x79, 0, 0, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_SYN_2056_A1[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0x1, 0x1, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0x60, 0x60, 0, 0},
+ {0x23, 0x6, 0x6, 0, 0},
+ {0x24, 0xc, 0xc, 0, 0},
+ {0x25, 0, 0, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0, 0, 0, 0},
+ {0x28, 0x1, 0x1, 0, 0},
+ {0x29, 0, 0, 0, 0},
+ {0x2A, 0, 0, 0, 0},
+ {0x2B, 0, 0, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0xd, 0xd, 0, 0},
+ {0x2F, 0x1f, 0x1f, 0, 0},
+ {0x30, 0x15, 0x15, 0, 0},
+ {0x31, 0xf, 0xf, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0, 0, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0, 0, 0, 0},
+ {0x38, 0, 0, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0, 0, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x13, 0x13, 0, 0},
+ {0x3D, 0xf, 0xf, 0, 0},
+ {0x3E, 0x18, 0x18, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x20, 0x20, 0, 0},
+ {0x42, 0x20, 0x20, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x77, 0x77, 0, 0},
+ {0x45, 0x7, 0x7, 0, 0},
+ {0x46, 0x1, 0x1, 0, 0},
+ {0x47, 0x4, 0x4, 0, 0},
+ {0x48, 0xf, 0xf, 0, 0},
+ {0x49, 0x30, 0x30, 0, 0},
+ {0x4A, 0x32, 0x32, 0, 0},
+ {0x4B, 0xd, 0xd, 0, 0},
+ {0x4C, 0xd, 0xd, 0, 0},
+ {0x4D, 0x4, 0x4, 0, 0},
+ {0x4E, 0x6, 0x6, 0, 0},
+ {0x4F, 0x1, 0x1, 0, 0},
+ {0x50, 0x1c, 0x1c, 0, 0},
+ {0x51, 0x2, 0x2, 0, 0},
+ {0x52, 0x2, 0x2, 0, 0},
+ {0x53, 0xf7, 0xf7, 1, 1},
+ {0x54, 0xb4, 0xb4, 0, 0},
+ {0x55, 0xd2, 0xd2, 0, 0},
+ {0x56, 0, 0, 0, 0},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x4, 0x4, 0, 0},
+ {0x59, 0x96, 0x96, 0, 0},
+ {0x5A, 0x3e, 0x3e, 0, 0},
+ {0x5B, 0x3e, 0x3e, 0, 0},
+ {0x5C, 0x13, 0x13, 0, 0},
+ {0x5D, 0x2, 0x2, 0, 0},
+ {0x5E, 0, 0, 0, 0},
+ {0x5F, 0x7, 0x7, 0, 0},
+ {0x60, 0x7, 0x7, 1, 1},
+ {0x61, 0x8, 0x8, 0, 0},
+ {0x62, 0x3, 0x3, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0x40, 0x40, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0x1, 0x1, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0x60, 0x60, 0, 0},
+ {0x71, 0x66, 0x66, 0, 0},
+ {0x72, 0xc, 0xc, 0, 0},
+ {0x73, 0x66, 0x66, 0, 0},
+ {0x74, 0x8f, 0x8f, 1, 1},
+ {0x75, 0, 0, 0, 0},
+ {0x76, 0xcc, 0xcc, 0, 0},
+ {0x77, 0x1, 0x1, 0, 0},
+ {0x78, 0x66, 0x66, 0, 0},
+ {0x79, 0x66, 0x66, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0xff, 0xff, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0x95, 0, 0, 0, 0},
+ {0x96, 0, 0, 0, 0},
+ {0x97, 0, 0, 0, 0},
+ {0x98, 0, 0, 0, 0},
+ {0x99, 0, 0, 0, 0},
+ {0x9A, 0, 0, 0, 0},
+ {0x9B, 0, 0, 0, 0},
+ {0x9C, 0, 0, 0, 0},
+ {0x9D, 0, 0, 0, 0},
+ {0x9E, 0, 0, 0, 0},
+ {0x9F, 0x6, 0x6, 0, 0},
+ {0xA0, 0x66, 0x66, 0, 0},
+ {0xA1, 0x66, 0x66, 0, 0},
+ {0xA2, 0x66, 0x66, 0, 0},
+ {0xA3, 0x66, 0x66, 0, 0},
+ {0xA4, 0x66, 0x66, 0, 0},
+ {0xA5, 0x66, 0x66, 0, 0},
+ {0xA6, 0x66, 0x66, 0, 0},
+ {0xA7, 0x66, 0x66, 0, 0},
+ {0xA8, 0x66, 0x66, 0, 0},
+ {0xA9, 0x66, 0x66, 0, 0},
+ {0xAA, 0x66, 0x66, 0, 0},
+ {0xAB, 0x66, 0x66, 0, 0},
+ {0xAC, 0x66, 0x66, 0, 0},
+ {0xAD, 0x66, 0x66, 0, 0},
+ {0xAE, 0x66, 0x66, 0, 0},
+ {0xAF, 0x66, 0x66, 0, 0},
+ {0xB0, 0x66, 0x66, 0, 0},
+ {0xB1, 0x66, 0x66, 0, 0},
+ {0xB2, 0x66, 0x66, 0, 0},
+ {0xB3, 0xa, 0xa, 0, 0},
+ {0xB4, 0, 0, 0, 0},
+ {0xB5, 0, 0, 0, 0},
+ {0xB6, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_TX_2056_A1[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0x88, 0x88, 0, 0},
+ {0x22, 0x88, 0x88, 0, 0},
+ {0x23, 0x88, 0x88, 0, 0},
+ {0x24, 0x88, 0x88, 0, 0},
+ {0x25, 0xc, 0xc, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0x3, 0x3, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0x3, 0x3, 0, 0},
+ {0x2A, 0x37, 0x37, 0, 0},
+ {0x2B, 0x3, 0x3, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0x1, 0x1, 0, 0},
+ {0x2F, 0x1, 0x1, 0, 0},
+ {0x30, 0, 0, 0, 0},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0x11, 0x11, 0, 0},
+ {0x34, 0x11, 0x11, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0x3, 0x3, 0, 0},
+ {0x38, 0xf, 0xf, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0x2d, 0x2d, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x6e, 0x6e, 0, 0},
+ {0x3D, 0xf0, 0xf0, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x3, 0x3, 0, 0},
+ {0x42, 0x3, 0x3, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x1e, 0x1e, 0, 0},
+ {0x45, 0, 0, 0, 0},
+ {0x46, 0x6e, 0x6e, 0, 0},
+ {0x47, 0xf0, 0xf0, 1, 1},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x2, 0x2, 0, 0},
+ {0x4A, 0xff, 0xff, 1, 1},
+ {0x4B, 0xc, 0xc, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0x38, 0x38, 0, 0},
+ {0x4E, 0x70, 0x70, 1, 1},
+ {0x4F, 0x2, 0x2, 0, 0},
+ {0x50, 0x88, 0x88, 0, 0},
+ {0x51, 0xc, 0xc, 0, 0},
+ {0x52, 0, 0, 0, 0},
+ {0x53, 0x8, 0x8, 0, 0},
+ {0x54, 0x70, 0x70, 1, 1},
+ {0x55, 0x2, 0x2, 0, 0},
+ {0x56, 0xff, 0xff, 1, 1},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x83, 0x83, 0, 0},
+ {0x59, 0x77, 0x77, 1, 1},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x88, 0x88, 0, 0},
+ {0x5D, 0, 0, 0, 0},
+ {0x5E, 0x8, 0x8, 0, 0},
+ {0x5F, 0x77, 0x77, 1, 1},
+ {0x60, 0x1, 0x1, 0, 0},
+ {0x61, 0, 0, 0, 0},
+ {0x62, 0x7, 0x7, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0x7, 0x7, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0x72, 0x72, 1, 1},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0xa, 0xa, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0x2, 0x2, 0, 0},
+ {0x72, 0, 0, 0, 0},
+ {0x73, 0, 0, 0, 0},
+ {0x74, 0xe, 0xe, 0, 0},
+ {0x75, 0xe, 0xe, 0, 0},
+ {0x76, 0xe, 0xe, 0, 0},
+ {0x77, 0x13, 0x13, 0, 0},
+ {0x78, 0x13, 0x13, 0, 0},
+ {0x79, 0x1b, 0x1b, 0, 0},
+ {0x7A, 0x1b, 0x1b, 0, 0},
+ {0x7B, 0x55, 0x55, 0, 0},
+ {0x7C, 0x5b, 0x5b, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_RX_2056_A1[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0x3, 0x3, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0, 0, 0, 0},
+ {0x23, 0x90, 0x90, 0, 0},
+ {0x24, 0x55, 0x55, 0, 0},
+ {0x25, 0x15, 0x15, 0, 0},
+ {0x26, 0x5, 0x5, 0, 0},
+ {0x27, 0x15, 0x15, 0, 0},
+ {0x28, 0x5, 0x5, 0, 0},
+ {0x29, 0x20, 0x20, 0, 0},
+ {0x2A, 0x11, 0x11, 0, 0},
+ {0x2B, 0x90, 0x90, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0x88, 0x88, 0, 0},
+ {0x2E, 0x32, 0x32, 0, 0},
+ {0x2F, 0x77, 0x77, 0, 0},
+ {0x30, 0x17, 0x17, 1, 1},
+ {0x31, 0xff, 0xff, 1, 1},
+ {0x32, 0x20, 0x20, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0x88, 0x88, 0, 0},
+ {0x35, 0x32, 0x32, 0, 0},
+ {0x36, 0x77, 0x77, 0, 0},
+ {0x37, 0x17, 0x17, 1, 1},
+ {0x38, 0xf0, 0xf0, 1, 1},
+ {0x39, 0x20, 0x20, 0, 0},
+ {0x3A, 0x8, 0x8, 0, 0},
+ {0x3B, 0x55, 0x55, 1, 1},
+ {0x3C, 0, 0, 0, 0},
+ {0x3D, 0x44, 0x44, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0x44, 0x44, 0, 0},
+ {0x40, 0xf, 0xf, 1, 1},
+ {0x41, 0x6, 0x6, 0, 0},
+ {0x42, 0x4, 0x4, 0, 0},
+ {0x43, 0x50, 0x50, 1, 1},
+ {0x44, 0x8, 0x8, 0, 0},
+ {0x45, 0x55, 0x55, 1, 1},
+ {0x46, 0, 0, 0, 0},
+ {0x47, 0x11, 0x11, 0, 0},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x44, 0x44, 0, 0},
+ {0x4A, 0x7, 0x7, 0, 0},
+ {0x4B, 0x6, 0x6, 0, 0},
+ {0x4C, 0x4, 0x4, 0, 0},
+ {0x4D, 0, 0, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0x26, 0x26, 1, 1},
+ {0x50, 0x26, 0x26, 1, 1},
+ {0x51, 0xf, 0xf, 1, 1},
+ {0x52, 0xf, 0xf, 1, 1},
+ {0x53, 0x44, 0x44, 0, 0},
+ {0x54, 0, 0, 0, 0},
+ {0x55, 0, 0, 0, 0},
+ {0x56, 0x8, 0x8, 0, 0},
+ {0x57, 0x8, 0x8, 0, 0},
+ {0x58, 0x7, 0x7, 0, 0},
+ {0x59, 0x22, 0x22, 0, 0},
+ {0x5A, 0x22, 0x22, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x2f, 0x2f, 1, 1},
+ {0x5D, 0x7, 0x7, 0, 0},
+ {0x5E, 0x55, 0x55, 0, 0},
+ {0x5F, 0x23, 0x23, 0, 0},
+ {0x60, 0x41, 0x41, 0, 0},
+ {0x61, 0x1, 0x1, 0, 0},
+ {0x62, 0xa, 0xa, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0xc, 0xc, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0, 0, 0, 0},
+ {0x72, 0x22, 0x22, 0, 0},
+ {0x73, 0x22, 0x22, 0, 0},
+ {0x74, 0, 0, 1, 1},
+ {0x75, 0xa, 0xa, 0, 0},
+ {0x76, 0x1, 0x1, 0, 0},
+ {0x77, 0x22, 0x22, 0, 0},
+ {0x78, 0x30, 0x30, 0, 0},
+ {0x79, 0, 0, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_SYN_2056_rev5[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0x1, 0x1, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0x60, 0x60, 0, 0},
+ {0x23, 0x6, 0x6, 0, 0},
+ {0x24, 0xc, 0xc, 0, 0},
+ {0x25, 0, 0, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0, 0, 0, 0},
+ {0x28, 0x1, 0x1, 0, 0},
+ {0x29, 0, 0, 0, 0},
+ {0x2A, 0, 0, 0, 0},
+ {0x2B, 0, 0, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0, 0, 0, 0},
+ {0x2F, 0x1f, 0x1f, 0, 0},
+ {0x30, 0x15, 0x15, 0, 0},
+ {0x31, 0xf, 0xf, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0, 0, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0, 0, 0, 0},
+ {0x38, 0, 0, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0, 0, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x13, 0x13, 0, 0},
+ {0x3D, 0xf, 0xf, 0, 0},
+ {0x3E, 0x18, 0x18, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x20, 0x20, 0, 0},
+ {0x42, 0x20, 0x20, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x77, 0x77, 0, 0},
+ {0x45, 0x7, 0x7, 0, 0},
+ {0x46, 0x1, 0x1, 0, 0},
+ {0x47, 0x4, 0x4, 0, 0},
+ {0x48, 0xf, 0xf, 0, 0},
+ {0x49, 0x30, 0x30, 0, 0},
+ {0x4A, 0x32, 0x32, 0, 0},
+ {0x4B, 0xd, 0xd, 0, 0},
+ {0x4C, 0xd, 0xd, 0, 0},
+ {0x4D, 0x4, 0x4, 0, 0},
+ {0x4E, 0x6, 0x6, 0, 0},
+ {0x4F, 0x1, 0x1, 0, 0},
+ {0x50, 0x1c, 0x1c, 0, 0},
+ {0x51, 0x2, 0x2, 0, 0},
+ {0x52, 0x2, 0x2, 0, 0},
+ {0x53, 0xf7, 0xf7, 1, 1},
+ {0x54, 0xb4, 0xb4, 0, 0},
+ {0x55, 0xd2, 0xd2, 0, 0},
+ {0x56, 0, 0, 0, 0},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x4, 0x4, 0, 0},
+ {0x59, 0x96, 0x96, 0, 0},
+ {0x5A, 0x3e, 0x3e, 0, 0},
+ {0x5B, 0x3e, 0x3e, 0, 0},
+ {0x5C, 0x13, 0x13, 0, 0},
+ {0x5D, 0x2, 0x2, 0, 0},
+ {0x5E, 0, 0, 0, 0},
+ {0x5F, 0x7, 0x7, 0, 0},
+ {0x60, 0x7, 0x7, 1, 1},
+ {0x61, 0x8, 0x8, 0, 0},
+ {0x62, 0x3, 0x3, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0x40, 0x40, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0x1, 0x1, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0x60, 0x60, 0, 0},
+ {0x71, 0x66, 0x66, 0, 0},
+ {0x72, 0xc, 0xc, 0, 0},
+ {0x73, 0x66, 0x66, 0, 0},
+ {0x74, 0x8f, 0x8f, 1, 1},
+ {0x75, 0, 0, 0, 0},
+ {0x76, 0xcc, 0xcc, 0, 0},
+ {0x77, 0x1, 0x1, 0, 0},
+ {0x78, 0x66, 0x66, 0, 0},
+ {0x79, 0x66, 0x66, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0xff, 0xff, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0x95, 0, 0, 0, 0},
+ {0x96, 0, 0, 0, 0},
+ {0x97, 0, 0, 0, 0},
+ {0x98, 0, 0, 0, 0},
+ {0x99, 0, 0, 0, 0},
+ {0x9A, 0, 0, 0, 0},
+ {0x9B, 0, 0, 0, 0},
+ {0x9C, 0, 0, 0, 0},
+ {0x9D, 0, 0, 0, 0},
+ {0x9E, 0, 0, 0, 0},
+ {0x9F, 0x6, 0x6, 0, 0},
+ {0xA0, 0x66, 0x66, 0, 0},
+ {0xA1, 0x66, 0x66, 0, 0},
+ {0xA2, 0x66, 0x66, 0, 0},
+ {0xA3, 0x66, 0x66, 0, 0},
+ {0xA4, 0x66, 0x66, 0, 0},
+ {0xA5, 0x66, 0x66, 0, 0},
+ {0xA6, 0x66, 0x66, 0, 0},
+ {0xA7, 0x66, 0x66, 0, 0},
+ {0xA8, 0x66, 0x66, 0, 0},
+ {0xA9, 0x66, 0x66, 0, 0},
+ {0xAA, 0x66, 0x66, 0, 0},
+ {0xAB, 0x66, 0x66, 0, 0},
+ {0xAC, 0x66, 0x66, 0, 0},
+ {0xAD, 0x66, 0x66, 0, 0},
+ {0xAE, 0x66, 0x66, 0, 0},
+ {0xAF, 0x66, 0x66, 0, 0},
+ {0xB0, 0x66, 0x66, 0, 0},
+ {0xB1, 0x66, 0x66, 0, 0},
+ {0xB2, 0x66, 0x66, 0, 0},
+ {0xB3, 0xa, 0xa, 0, 0},
+ {0xB4, 0, 0, 0, 0},
+ {0xB5, 0, 0, 0, 0},
+ {0xB6, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_TX_2056_rev5[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0x88, 0x88, 0, 0},
+ {0x22, 0x88, 0x88, 0, 0},
+ {0x23, 0x88, 0x88, 0, 0},
+ {0x24, 0x88, 0x88, 0, 0},
+ {0x25, 0xc, 0xc, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0x3, 0x3, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0x3, 0x3, 0, 0},
+ {0x2A, 0x37, 0x37, 0, 0},
+ {0x2B, 0x3, 0x3, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0x1, 0x1, 0, 0},
+ {0x2F, 0x1, 0x1, 0, 0},
+ {0x30, 0, 0, 0, 0},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0x11, 0x11, 0, 0},
+ {0x34, 0x11, 0x11, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0x3, 0x3, 0, 0},
+ {0x38, 0xf, 0xf, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0x2d, 0x2d, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x6e, 0x6e, 0, 0},
+ {0x3D, 0xf0, 0xf0, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x3, 0x3, 0, 0},
+ {0x42, 0x3, 0x3, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x1e, 0x1e, 0, 0},
+ {0x45, 0, 0, 0, 0},
+ {0x46, 0x6e, 0x6e, 0, 0},
+ {0x47, 0xf0, 0xf0, 1, 1},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x2, 0x2, 0, 0},
+ {0x4A, 0xff, 0xff, 1, 1},
+ {0x4B, 0xc, 0xc, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0x38, 0x38, 0, 0},
+ {0x4E, 0x70, 0x70, 1, 1},
+ {0x4F, 0x2, 0x2, 0, 0},
+ {0x50, 0x88, 0x88, 0, 0},
+ {0x51, 0xc, 0xc, 0, 0},
+ {0x52, 0, 0, 0, 0},
+ {0x53, 0x8, 0x8, 0, 0},
+ {0x54, 0x70, 0x70, 1, 1},
+ {0x55, 0x2, 0x2, 0, 0},
+ {0x56, 0xff, 0xff, 1, 1},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x83, 0x83, 0, 0},
+ {0x59, 0x77, 0x77, 1, 1},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x88, 0x88, 0, 0},
+ {0x5D, 0, 0, 0, 0},
+ {0x5E, 0x8, 0x8, 0, 0},
+ {0x5F, 0x77, 0x77, 1, 1},
+ {0x60, 0x1, 0x1, 0, 0},
+ {0x61, 0, 0, 0, 0},
+ {0x62, 0x7, 0x7, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0x7, 0x7, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 1, 1},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0xa, 0xa, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0x2, 0x2, 0, 0},
+ {0x72, 0, 0, 0, 0},
+ {0x73, 0, 0, 0, 0},
+ {0x74, 0xe, 0xe, 0, 0},
+ {0x75, 0xe, 0xe, 0, 0},
+ {0x76, 0xe, 0xe, 0, 0},
+ {0x77, 0x13, 0x13, 0, 0},
+ {0x78, 0x13, 0x13, 0, 0},
+ {0x79, 0x1b, 0x1b, 0, 0},
+ {0x7A, 0x1b, 0x1b, 0, 0},
+ {0x7B, 0x55, 0x55, 0, 0},
+ {0x7C, 0x5b, 0x5b, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0x70, 0x70, 0, 0},
+ {0x94, 0x70, 0x70, 0, 0},
+ {0x95, 0x71, 0x71, 1, 1},
+ {0x96, 0x71, 0x71, 1, 1},
+ {0x97, 0x72, 0x72, 1, 1},
+ {0x98, 0x73, 0x73, 1, 1},
+ {0x99, 0x74, 0x74, 1, 1},
+ {0x9A, 0x75, 0x75, 1, 1},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_RX_2056_rev5[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0x3, 0x3, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0, 0, 0, 0},
+ {0x23, 0x90, 0x90, 0, 0},
+ {0x24, 0x55, 0x55, 0, 0},
+ {0x25, 0x15, 0x15, 0, 0},
+ {0x26, 0x5, 0x5, 0, 0},
+ {0x27, 0x15, 0x15, 0, 0},
+ {0x28, 0x5, 0x5, 0, 0},
+ {0x29, 0x20, 0x20, 0, 0},
+ {0x2A, 0x11, 0x11, 0, 0},
+ {0x2B, 0x90, 0x90, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0x88, 0x88, 0, 0},
+ {0x2E, 0x32, 0x32, 0, 0},
+ {0x2F, 0x77, 0x77, 0, 0},
+ {0x30, 0x17, 0x17, 1, 1},
+ {0x31, 0xff, 0xff, 1, 1},
+ {0x32, 0x20, 0x20, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0x88, 0x88, 0, 0},
+ {0x35, 0x32, 0x32, 0, 0},
+ {0x36, 0x77, 0x77, 0, 0},
+ {0x37, 0x17, 0x17, 1, 1},
+ {0x38, 0xf0, 0xf0, 1, 1},
+ {0x39, 0x20, 0x20, 0, 0},
+ {0x3A, 0x8, 0x8, 0, 0},
+ {0x3B, 0x55, 0x55, 1, 1},
+ {0x3C, 0, 0, 0, 0},
+ {0x3D, 0x88, 0x88, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 1, 1},
+ {0x40, 0x7, 0x7, 1, 1},
+ {0x41, 0x6, 0x6, 0, 0},
+ {0x42, 0x4, 0x4, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x8, 0x8, 0, 0},
+ {0x45, 0x55, 0x55, 1, 1},
+ {0x46, 0, 0, 0, 0},
+ {0x47, 0x11, 0x11, 0, 0},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0, 0, 1, 1},
+ {0x4A, 0x7, 0x7, 0, 0},
+ {0x4B, 0x6, 0x6, 0, 0},
+ {0x4C, 0x4, 0x4, 0, 0},
+ {0x4D, 0, 0, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0x26, 0x26, 1, 1},
+ {0x50, 0x26, 0x26, 1, 1},
+ {0x51, 0xf, 0xf, 1, 1},
+ {0x52, 0xf, 0xf, 1, 1},
+ {0x53, 0x44, 0x44, 0, 0},
+ {0x54, 0, 0, 0, 0},
+ {0x55, 0, 0, 0, 0},
+ {0x56, 0x8, 0x8, 0, 0},
+ {0x57, 0x8, 0x8, 0, 0},
+ {0x58, 0x7, 0x7, 0, 0},
+ {0x59, 0x22, 0x22, 0, 0},
+ {0x5A, 0x22, 0x22, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x4, 0x4, 1, 1},
+ {0x5D, 0x7, 0x7, 0, 0},
+ {0x5E, 0x55, 0x55, 0, 0},
+ {0x5F, 0x23, 0x23, 0, 0},
+ {0x60, 0x41, 0x41, 0, 0},
+ {0x61, 0x1, 0x1, 0, 0},
+ {0x62, 0xa, 0xa, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0xc, 0xc, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0, 0, 0, 0},
+ {0x72, 0x22, 0x22, 0, 0},
+ {0x73, 0x22, 0x22, 0, 0},
+ {0x74, 0, 0, 1, 1},
+ {0x75, 0xa, 0xa, 0, 0},
+ {0x76, 0x1, 0x1, 0, 0},
+ {0x77, 0x22, 0x22, 0, 0},
+ {0x78, 0x30, 0x30, 0, 0},
+ {0x79, 0, 0, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_SYN_2056_rev6[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0x1, 0x1, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0x60, 0x60, 0, 0},
+ {0x23, 0x6, 0x6, 0, 0},
+ {0x24, 0xc, 0xc, 0, 0},
+ {0x25, 0, 0, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0, 0, 0, 0},
+ {0x28, 0x1, 0x1, 0, 0},
+ {0x29, 0, 0, 0, 0},
+ {0x2A, 0, 0, 0, 0},
+ {0x2B, 0, 0, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0, 0, 0, 0},
+ {0x2F, 0x1f, 0x1f, 0, 0},
+ {0x30, 0x15, 0x15, 0, 0},
+ {0x31, 0xf, 0xf, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0, 0, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0, 0, 0, 0},
+ {0x38, 0, 0, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0, 0, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x13, 0x13, 0, 0},
+ {0x3D, 0xf, 0xf, 0, 0},
+ {0x3E, 0x18, 0x18, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x20, 0x20, 0, 0},
+ {0x42, 0x20, 0x20, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x77, 0x77, 0, 0},
+ {0x45, 0x7, 0x7, 0, 0},
+ {0x46, 0x1, 0x1, 0, 0},
+ {0x47, 0x4, 0x4, 0, 0},
+ {0x48, 0xf, 0xf, 0, 0},
+ {0x49, 0x30, 0x30, 0, 0},
+ {0x4A, 0x32, 0x32, 0, 0},
+ {0x4B, 0xd, 0xd, 0, 0},
+ {0x4C, 0xd, 0xd, 0, 0},
+ {0x4D, 0x4, 0x4, 0, 0},
+ {0x4E, 0x6, 0x6, 0, 0},
+ {0x4F, 0x1, 0x1, 0, 0},
+ {0x50, 0x1c, 0x1c, 0, 0},
+ {0x51, 0x2, 0x2, 0, 0},
+ {0x52, 0x2, 0x2, 0, 0},
+ {0x53, 0xf7, 0xf7, 1, 1},
+ {0x54, 0xb4, 0xb4, 0, 0},
+ {0x55, 0xd2, 0xd2, 0, 0},
+ {0x56, 0, 0, 0, 0},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x4, 0x4, 0, 0},
+ {0x59, 0x96, 0x96, 0, 0},
+ {0x5A, 0x3e, 0x3e, 0, 0},
+ {0x5B, 0x3e, 0x3e, 0, 0},
+ {0x5C, 0x13, 0x13, 0, 0},
+ {0x5D, 0x2, 0x2, 0, 0},
+ {0x5E, 0, 0, 0, 0},
+ {0x5F, 0x7, 0x7, 0, 0},
+ {0x60, 0x7, 0x7, 1, 1},
+ {0x61, 0x8, 0x8, 0, 0},
+ {0x62, 0x3, 0x3, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0x40, 0x40, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0x1, 0x1, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0x60, 0x60, 0, 0},
+ {0x71, 0x66, 0x66, 0, 0},
+ {0x72, 0xc, 0xc, 0, 0},
+ {0x73, 0x66, 0x66, 0, 0},
+ {0x74, 0x8f, 0x8f, 1, 1},
+ {0x75, 0, 0, 0, 0},
+ {0x76, 0xcc, 0xcc, 0, 0},
+ {0x77, 0x1, 0x1, 0, 0},
+ {0x78, 0x66, 0x66, 0, 0},
+ {0x79, 0x66, 0x66, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0xff, 0xff, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0x95, 0, 0, 0, 0},
+ {0x96, 0, 0, 0, 0},
+ {0x97, 0, 0, 0, 0},
+ {0x98, 0, 0, 0, 0},
+ {0x99, 0, 0, 0, 0},
+ {0x9A, 0, 0, 0, 0},
+ {0x9B, 0, 0, 0, 0},
+ {0x9C, 0, 0, 0, 0},
+ {0x9D, 0, 0, 0, 0},
+ {0x9E, 0, 0, 0, 0},
+ {0x9F, 0x6, 0x6, 0, 0},
+ {0xA0, 0x66, 0x66, 0, 0},
+ {0xA1, 0x66, 0x66, 0, 0},
+ {0xA2, 0x66, 0x66, 0, 0},
+ {0xA3, 0x66, 0x66, 0, 0},
+ {0xA4, 0x66, 0x66, 0, 0},
+ {0xA5, 0x66, 0x66, 0, 0},
+ {0xA6, 0x66, 0x66, 0, 0},
+ {0xA7, 0x66, 0x66, 0, 0},
+ {0xA8, 0x66, 0x66, 0, 0},
+ {0xA9, 0x66, 0x66, 0, 0},
+ {0xAA, 0x66, 0x66, 0, 0},
+ {0xAB, 0x66, 0x66, 0, 0},
+ {0xAC, 0x66, 0x66, 0, 0},
+ {0xAD, 0x66, 0x66, 0, 0},
+ {0xAE, 0x66, 0x66, 0, 0},
+ {0xAF, 0x66, 0x66, 0, 0},
+ {0xB0, 0x66, 0x66, 0, 0},
+ {0xB1, 0x66, 0x66, 0, 0},
+ {0xB2, 0x66, 0x66, 0, 0},
+ {0xB3, 0xa, 0xa, 0, 0},
+ {0xB4, 0, 0, 0, 0},
+ {0xB5, 0, 0, 0, 0},
+ {0xB6, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_TX_2056_rev6[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0x88, 0x88, 0, 0},
+ {0x22, 0x88, 0x88, 0, 0},
+ {0x23, 0x88, 0x88, 0, 0},
+ {0x24, 0x88, 0x88, 0, 0},
+ {0x25, 0xc, 0xc, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0x3, 0x3, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0x3, 0x3, 0, 0},
+ {0x2A, 0x37, 0x37, 0, 0},
+ {0x2B, 0x3, 0x3, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0x1, 0x1, 0, 0},
+ {0x2F, 0x1, 0x1, 0, 0},
+ {0x30, 0, 0, 0, 0},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0x11, 0x11, 0, 0},
+ {0x34, 0xee, 0xee, 1, 1},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0x3, 0x3, 0, 0},
+ {0x38, 0x50, 0x50, 1, 1},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0x50, 0x50, 1, 1},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x6e, 0x6e, 0, 0},
+ {0x3D, 0xf0, 0xf0, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x3, 0x3, 0, 0},
+ {0x42, 0x3, 0x3, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x1e, 0x1e, 0, 0},
+ {0x45, 0, 0, 0, 0},
+ {0x46, 0x6e, 0x6e, 0, 0},
+ {0x47, 0xf0, 0xf0, 1, 1},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x2, 0x2, 0, 0},
+ {0x4A, 0xff, 0xff, 1, 1},
+ {0x4B, 0xc, 0xc, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0x38, 0x38, 0, 0},
+ {0x4E, 0x70, 0x70, 1, 1},
+ {0x4F, 0x2, 0x2, 0, 0},
+ {0x50, 0x88, 0x88, 0, 0},
+ {0x51, 0xc, 0xc, 0, 0},
+ {0x52, 0, 0, 0, 0},
+ {0x53, 0x8, 0x8, 0, 0},
+ {0x54, 0x70, 0x70, 1, 1},
+ {0x55, 0x2, 0x2, 0, 0},
+ {0x56, 0xff, 0xff, 1, 1},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x83, 0x83, 0, 0},
+ {0x59, 0x77, 0x77, 1, 1},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x88, 0x88, 0, 0},
+ {0x5D, 0, 0, 0, 0},
+ {0x5E, 0x8, 0x8, 0, 0},
+ {0x5F, 0x77, 0x77, 1, 1},
+ {0x60, 0x1, 0x1, 0, 0},
+ {0x61, 0, 0, 0, 0},
+ {0x62, 0x7, 0x7, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0x7, 0x7, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 1, 1},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0xa, 0xa, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0x2, 0x2, 0, 0},
+ {0x72, 0, 0, 0, 0},
+ {0x73, 0, 0, 0, 0},
+ {0x74, 0xe, 0xe, 0, 0},
+ {0x75, 0xe, 0xe, 0, 0},
+ {0x76, 0xe, 0xe, 0, 0},
+ {0x77, 0x13, 0x13, 0, 0},
+ {0x78, 0x13, 0x13, 0, 0},
+ {0x79, 0x1b, 0x1b, 0, 0},
+ {0x7A, 0x1b, 0x1b, 0, 0},
+ {0x7B, 0x55, 0x55, 0, 0},
+ {0x7C, 0x5b, 0x5b, 0, 0},
+ {0x7D, 0x30, 0x30, 1, 1},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0x70, 0x70, 0, 0},
+ {0x94, 0x70, 0x70, 0, 0},
+ {0x95, 0x70, 0x70, 0, 0},
+ {0x96, 0x70, 0x70, 0, 0},
+ {0x97, 0x70, 0x70, 0, 0},
+ {0x98, 0x70, 0x70, 0, 0},
+ {0x99, 0x70, 0x70, 0, 0},
+ {0x9A, 0x70, 0x70, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_RX_2056_rev6[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0x3, 0x3, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0, 0, 0, 0},
+ {0x23, 0x90, 0x90, 0, 0},
+ {0x24, 0x55, 0x55, 0, 0},
+ {0x25, 0x15, 0x15, 0, 0},
+ {0x26, 0x5, 0x5, 0, 0},
+ {0x27, 0x15, 0x15, 0, 0},
+ {0x28, 0x5, 0x5, 0, 0},
+ {0x29, 0x20, 0x20, 0, 0},
+ {0x2A, 0x11, 0x11, 0, 0},
+ {0x2B, 0x90, 0x90, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0x88, 0x88, 0, 0},
+ {0x2E, 0x32, 0x32, 0, 0},
+ {0x2F, 0x77, 0x77, 0, 0},
+ {0x30, 0x17, 0x17, 1, 1},
+ {0x31, 0xff, 0xff, 1, 1},
+ {0x32, 0x20, 0x20, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0x88, 0x88, 0, 0},
+ {0x35, 0x32, 0x32, 0, 0},
+ {0x36, 0x77, 0x77, 0, 0},
+ {0x37, 0x17, 0x17, 1, 1},
+ {0x38, 0xf0, 0xf0, 1, 1},
+ {0x39, 0x20, 0x20, 0, 0},
+ {0x3A, 0x8, 0x8, 0, 0},
+ {0x3B, 0x55, 0x55, 1, 1},
+ {0x3C, 0, 0, 0, 0},
+ {0x3D, 0x88, 0x88, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0x44, 0x44, 0, 0},
+ {0x40, 0x7, 0x7, 1, 1},
+ {0x41, 0x6, 0x6, 0, 0},
+ {0x42, 0x4, 0x4, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x8, 0x8, 0, 0},
+ {0x45, 0x55, 0x55, 1, 1},
+ {0x46, 0, 0, 0, 0},
+ {0x47, 0x11, 0x11, 0, 0},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x44, 0x44, 0, 0},
+ {0x4A, 0x7, 0x7, 0, 0},
+ {0x4B, 0x6, 0x6, 0, 0},
+ {0x4C, 0x4, 0x4, 0, 0},
+ {0x4D, 0, 0, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0x26, 0x26, 1, 1},
+ {0x50, 0x26, 0x26, 1, 1},
+ {0x51, 0xf, 0xf, 1, 1},
+ {0x52, 0xf, 0xf, 1, 1},
+ {0x53, 0x44, 0x44, 0, 0},
+ {0x54, 0, 0, 0, 0},
+ {0x55, 0, 0, 0, 0},
+ {0x56, 0x8, 0x8, 0, 0},
+ {0x57, 0x8, 0x8, 0, 0},
+ {0x58, 0x7, 0x7, 0, 0},
+ {0x59, 0x22, 0x22, 0, 0},
+ {0x5A, 0x22, 0x22, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x4, 0x4, 1, 1},
+ {0x5D, 0x7, 0x7, 0, 0},
+ {0x5E, 0x55, 0x55, 0, 0},
+ {0x5F, 0x23, 0x23, 0, 0},
+ {0x60, 0x41, 0x41, 0, 0},
+ {0x61, 0x1, 0x1, 0, 0},
+ {0x62, 0xa, 0xa, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0xc, 0xc, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0, 0, 0, 0},
+ {0x72, 0x22, 0x22, 0, 0},
+ {0x73, 0x22, 0x22, 0, 0},
+ {0x74, 0, 0, 1, 1},
+ {0x75, 0xa, 0xa, 0, 0},
+ {0x76, 0x1, 0x1, 0, 0},
+ {0x77, 0x22, 0x22, 0, 0},
+ {0x78, 0x30, 0x30, 0, 0},
+ {0x79, 0, 0, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0x5, 0x5, 1, 1},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0}
+};
+
+radio_regs_t regs_SYN_2056_rev7[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0x1, 0x1, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0x60, 0x60, 0, 0},
+ {0x23, 0x6, 0x6, 0, 0},
+ {0x24, 0xc, 0xc, 0, 0},
+ {0x25, 0, 0, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0, 0, 0, 0},
+ {0x28, 0x1, 0x1, 0, 0},
+ {0x29, 0, 0, 0, 0},
+ {0x2A, 0, 0, 0, 0},
+ {0x2B, 0, 0, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0, 0, 0, 0},
+ {0x2F, 0x1f, 0x1f, 0, 0},
+ {0x30, 0x15, 0x15, 0, 0},
+ {0x31, 0xf, 0xf, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0, 0, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0, 0, 0, 0},
+ {0x38, 0, 0, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0, 0, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x13, 0x13, 0, 0},
+ {0x3D, 0xf, 0xf, 0, 0},
+ {0x3E, 0x18, 0x18, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x20, 0x20, 0, 0},
+ {0x42, 0x20, 0x20, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x77, 0x77, 0, 0},
+ {0x45, 0x7, 0x7, 0, 0},
+ {0x46, 0x1, 0x1, 0, 0},
+ {0x47, 0x4, 0x4, 0, 0},
+ {0x48, 0xf, 0xf, 0, 0},
+ {0x49, 0x30, 0x30, 0, 0},
+ {0x4A, 0x32, 0x32, 0, 0},
+ {0x4B, 0xd, 0xd, 0, 0},
+ {0x4C, 0xd, 0xd, 0, 0},
+ {0x4D, 0x4, 0x4, 0, 0},
+ {0x4E, 0x6, 0x6, 0, 0},
+ {0x4F, 0x1, 0x1, 0, 0},
+ {0x50, 0x1c, 0x1c, 0, 0},
+ {0x51, 0x2, 0x2, 0, 0},
+ {0x52, 0x2, 0x2, 0, 0},
+ {0x53, 0xf7, 0xf7, 1, 1},
+ {0x54, 0xb4, 0xb4, 0, 0},
+ {0x55, 0xd2, 0xd2, 0, 0},
+ {0x56, 0, 0, 0, 0},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x4, 0x4, 0, 0},
+ {0x59, 0x96, 0x96, 0, 0},
+ {0x5A, 0x3e, 0x3e, 0, 0},
+ {0x5B, 0x3e, 0x3e, 0, 0},
+ {0x5C, 0x13, 0x13, 0, 0},
+ {0x5D, 0x2, 0x2, 0, 0},
+ {0x5E, 0, 0, 0, 0},
+ {0x5F, 0x7, 0x7, 0, 0},
+ {0x60, 0x7, 0x7, 1, 1},
+ {0x61, 0x8, 0x8, 0, 0},
+ {0x62, 0x3, 0x3, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0x40, 0x40, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0x1, 0x1, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0x60, 0x60, 0, 0},
+ {0x71, 0x66, 0x66, 0, 0},
+ {0x72, 0xc, 0xc, 0, 0},
+ {0x73, 0x66, 0x66, 0, 0},
+ {0x74, 0x8f, 0x8f, 1, 1},
+ {0x75, 0, 0, 0, 0},
+ {0x76, 0xcc, 0xcc, 0, 0},
+ {0x77, 0x1, 0x1, 0, 0},
+ {0x78, 0x66, 0x66, 0, 0},
+ {0x79, 0x66, 0x66, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0xff, 0xff, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0x95, 0, 0, 0, 0},
+ {0x96, 0, 0, 0, 0},
+ {0x97, 0, 0, 0, 0},
+ {0x98, 0, 0, 0, 0},
+ {0x99, 0, 0, 0, 0},
+ {0x9A, 0, 0, 0, 0},
+ {0x9B, 0, 0, 0, 0},
+ {0x9C, 0, 0, 0, 0},
+ {0x9D, 0, 0, 0, 0},
+ {0x9E, 0, 0, 0, 0},
+ {0x9F, 0x6, 0x6, 0, 0},
+ {0xA0, 0x66, 0x66, 0, 0},
+ {0xA1, 0x66, 0x66, 0, 0},
+ {0xA2, 0x66, 0x66, 0, 0},
+ {0xA3, 0x66, 0x66, 0, 0},
+ {0xA4, 0x66, 0x66, 0, 0},
+ {0xA5, 0x66, 0x66, 0, 0},
+ {0xA6, 0x66, 0x66, 0, 0},
+ {0xA7, 0x66, 0x66, 0, 0},
+ {0xA8, 0x66, 0x66, 0, 0},
+ {0xA9, 0x66, 0x66, 0, 0},
+ {0xAA, 0x66, 0x66, 0, 0},
+ {0xAB, 0x66, 0x66, 0, 0},
+ {0xAC, 0x66, 0x66, 0, 0},
+ {0xAD, 0x66, 0x66, 0, 0},
+ {0xAE, 0x66, 0x66, 0, 0},
+ {0xAF, 0x66, 0x66, 0, 0},
+ {0xB0, 0x66, 0x66, 0, 0},
+ {0xB1, 0x66, 0x66, 0, 0},
+ {0xB2, 0x66, 0x66, 0, 0},
+ {0xB3, 0xa, 0xa, 0, 0},
+ {0xB4, 0, 0, 0, 0},
+ {0xB5, 0, 0, 0, 0},
+ {0xB6, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_TX_2056_rev7[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0x88, 0x88, 0, 0},
+ {0x22, 0x88, 0x88, 0, 0},
+ {0x23, 0x88, 0x88, 0, 0},
+ {0x24, 0x88, 0x88, 0, 0},
+ {0x25, 0xc, 0xc, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0x3, 0x3, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0x3, 0x3, 0, 0},
+ {0x2A, 0x37, 0x37, 0, 0},
+ {0x2B, 0x3, 0x3, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0x1, 0x1, 0, 0},
+ {0x2F, 0x1, 0x1, 0, 0},
+ {0x30, 0, 0, 0, 0},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0x11, 0x11, 0, 0},
+ {0x34, 0xee, 0xee, 1, 1},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0x3, 0x3, 0, 0},
+ {0x38, 0x50, 0x50, 1, 1},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0x50, 0x50, 1, 1},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x6e, 0x6e, 0, 0},
+ {0x3D, 0xf0, 0xf0, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x3, 0x3, 0, 0},
+ {0x42, 0x3, 0x3, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x1e, 0x1e, 0, 0},
+ {0x45, 0, 0, 0, 0},
+ {0x46, 0x6e, 0x6e, 0, 0},
+ {0x47, 0xf0, 0xf0, 1, 1},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x2, 0x2, 0, 0},
+ {0x4A, 0xff, 0xff, 1, 1},
+ {0x4B, 0xc, 0xc, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0x38, 0x38, 0, 0},
+ {0x4E, 0x70, 0x70, 1, 1},
+ {0x4F, 0x2, 0x2, 0, 0},
+ {0x50, 0x88, 0x88, 0, 0},
+ {0x51, 0xc, 0xc, 0, 0},
+ {0x52, 0, 0, 0, 0},
+ {0x53, 0x8, 0x8, 0, 0},
+ {0x54, 0x70, 0x70, 1, 1},
+ {0x55, 0x2, 0x2, 0, 0},
+ {0x56, 0xff, 0xff, 1, 1},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x83, 0x83, 0, 0},
+ {0x59, 0x77, 0x77, 1, 1},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x88, 0x88, 0, 0},
+ {0x5D, 0, 0, 0, 0},
+ {0x5E, 0x8, 0x8, 0, 0},
+ {0x5F, 0x77, 0x77, 1, 1},
+ {0x60, 0x1, 0x1, 0, 0},
+ {0x61, 0, 0, 0, 0},
+ {0x62, 0x7, 0x7, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0x7, 0x7, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 1, 1},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0xa, 0xa, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0x2, 0x2, 0, 0},
+ {0x72, 0, 0, 0, 0},
+ {0x73, 0, 0, 0, 0},
+ {0x74, 0xe, 0xe, 0, 0},
+ {0x75, 0xe, 0xe, 0, 0},
+ {0x76, 0xe, 0xe, 0, 0},
+ {0x77, 0x13, 0x13, 0, 0},
+ {0x78, 0x13, 0x13, 0, 0},
+ {0x79, 0x1b, 0x1b, 0, 0},
+ {0x7A, 0x1b, 0x1b, 0, 0},
+ {0x7B, 0x55, 0x55, 0, 0},
+ {0x7C, 0x5b, 0x5b, 0, 0},
+ {0x7D, 0x30, 0x30, 1, 1},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0x70, 0x70, 0, 0},
+ {0x94, 0x70, 0x70, 0, 0},
+ {0x95, 0x71, 0x71, 1, 1},
+ {0x96, 0x71, 0x71, 1, 1},
+ {0x97, 0x72, 0x72, 1, 1},
+ {0x98, 0x73, 0x73, 1, 1},
+ {0x99, 0x74, 0x74, 1, 1},
+ {0x9A, 0x75, 0x75, 1, 1},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_RX_2056_rev7[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0x3, 0x3, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0, 0, 0, 0},
+ {0x23, 0x90, 0x90, 0, 0},
+ {0x24, 0x55, 0x55, 0, 0},
+ {0x25, 0x15, 0x15, 0, 0},
+ {0x26, 0x5, 0x5, 0, 0},
+ {0x27, 0x15, 0x15, 0, 0},
+ {0x28, 0x5, 0x5, 0, 0},
+ {0x29, 0x20, 0x20, 0, 0},
+ {0x2A, 0x11, 0x11, 0, 0},
+ {0x2B, 0x90, 0x90, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0x88, 0x88, 0, 0},
+ {0x2E, 0x32, 0x32, 0, 0},
+ {0x2F, 0x77, 0x77, 0, 0},
+ {0x30, 0x17, 0x17, 1, 1},
+ {0x31, 0xff, 0xff, 1, 1},
+ {0x32, 0x20, 0x20, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0x88, 0x88, 0, 0},
+ {0x35, 0x32, 0x32, 0, 0},
+ {0x36, 0x77, 0x77, 0, 0},
+ {0x37, 0x17, 0x17, 1, 1},
+ {0x38, 0xf0, 0xf0, 1, 1},
+ {0x39, 0x20, 0x20, 0, 0},
+ {0x3A, 0x8, 0x8, 0, 0},
+ {0x3B, 0x55, 0x55, 1, 1},
+ {0x3C, 0, 0, 0, 0},
+ {0x3D, 0x88, 0x88, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 1, 1},
+ {0x40, 0x7, 0x7, 1, 1},
+ {0x41, 0x6, 0x6, 0, 0},
+ {0x42, 0x4, 0x4, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x8, 0x8, 0, 0},
+ {0x45, 0x55, 0x55, 1, 1},
+ {0x46, 0, 0, 0, 0},
+ {0x47, 0x11, 0x11, 0, 0},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0, 0, 1, 1},
+ {0x4A, 0x7, 0x7, 0, 0},
+ {0x4B, 0x6, 0x6, 0, 0},
+ {0x4C, 0x4, 0x4, 0, 0},
+ {0x4D, 0, 0, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0x26, 0x26, 1, 1},
+ {0x50, 0x26, 0x26, 1, 1},
+ {0x51, 0xf, 0xf, 1, 1},
+ {0x52, 0xf, 0xf, 1, 1},
+ {0x53, 0x44, 0x44, 0, 0},
+ {0x54, 0, 0, 0, 0},
+ {0x55, 0, 0, 0, 0},
+ {0x56, 0x8, 0x8, 0, 0},
+ {0x57, 0x8, 0x8, 0, 0},
+ {0x58, 0x7, 0x7, 0, 0},
+ {0x59, 0x22, 0x22, 0, 0},
+ {0x5A, 0x22, 0x22, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x4, 0x4, 1, 1},
+ {0x5D, 0x7, 0x7, 0, 0},
+ {0x5E, 0x55, 0x55, 0, 0},
+ {0x5F, 0x23, 0x23, 0, 0},
+ {0x60, 0x41, 0x41, 0, 0},
+ {0x61, 0x1, 0x1, 0, 0},
+ {0x62, 0xa, 0xa, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0xc, 0xc, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0, 0, 0, 0},
+ {0x72, 0x22, 0x22, 0, 0},
+ {0x73, 0x22, 0x22, 0, 0},
+ {0x74, 0, 0, 1, 1},
+ {0x75, 0xa, 0xa, 0, 0},
+ {0x76, 0x1, 0x1, 0, 0},
+ {0x77, 0x22, 0x22, 0, 0},
+ {0x78, 0x30, 0x30, 0, 0},
+ {0x79, 0, 0, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_SYN_2056_rev8[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0x1, 0x1, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0x60, 0x60, 0, 0},
+ {0x23, 0x6, 0x6, 0, 0},
+ {0x24, 0xc, 0xc, 0, 0},
+ {0x25, 0, 0, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0, 0, 0, 0},
+ {0x28, 0x1, 0x1, 0, 0},
+ {0x29, 0, 0, 0, 0},
+ {0x2A, 0, 0, 0, 0},
+ {0x2B, 0, 0, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0, 0, 0, 0},
+ {0x2F, 0x1f, 0x1f, 0, 0},
+ {0x30, 0x15, 0x15, 0, 0},
+ {0x31, 0xf, 0xf, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0, 0, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0, 0, 0, 0},
+ {0x38, 0, 0, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0, 0, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x13, 0x13, 0, 0},
+ {0x3D, 0xf, 0xf, 0, 0},
+ {0x3E, 0x18, 0x18, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x20, 0x20, 0, 0},
+ {0x42, 0x20, 0x20, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x77, 0x77, 0, 0},
+ {0x45, 0x7, 0x7, 0, 0},
+ {0x46, 0x1, 0x1, 0, 0},
+ {0x47, 0x4, 0x4, 0, 0},
+ {0x48, 0xf, 0xf, 0, 0},
+ {0x49, 0x30, 0x30, 0, 0},
+ {0x4A, 0x32, 0x32, 0, 0},
+ {0x4B, 0xd, 0xd, 0, 0},
+ {0x4C, 0xd, 0xd, 0, 0},
+ {0x4D, 0x4, 0x4, 0, 0},
+ {0x4E, 0x6, 0x6, 0, 0},
+ {0x4F, 0x1, 0x1, 0, 0},
+ {0x50, 0x1c, 0x1c, 0, 0},
+ {0x51, 0x2, 0x2, 0, 0},
+ {0x52, 0x2, 0x2, 0, 0},
+ {0x53, 0xf7, 0xf7, 1, 1},
+ {0x54, 0xb4, 0xb4, 0, 0},
+ {0x55, 0xd2, 0xd2, 0, 0},
+ {0x56, 0, 0, 0, 0},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x4, 0x4, 0, 0},
+ {0x59, 0x96, 0x96, 0, 0},
+ {0x5A, 0x3e, 0x3e, 0, 0},
+ {0x5B, 0x3e, 0x3e, 0, 0},
+ {0x5C, 0x13, 0x13, 0, 0},
+ {0x5D, 0x2, 0x2, 0, 0},
+ {0x5E, 0, 0, 0, 0},
+ {0x5F, 0x7, 0x7, 0, 0},
+ {0x60, 0x7, 0x7, 1, 1},
+ {0x61, 0x8, 0x8, 0, 0},
+ {0x62, 0x3, 0x3, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0x40, 0x40, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0x1, 0x1, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0x60, 0x60, 0, 0},
+ {0x71, 0x66, 0x66, 0, 0},
+ {0x72, 0xc, 0xc, 0, 0},
+ {0x73, 0x66, 0x66, 0, 0},
+ {0x74, 0x8f, 0x8f, 1, 1},
+ {0x75, 0, 0, 0, 0},
+ {0x76, 0xcc, 0xcc, 0, 0},
+ {0x77, 0x1, 0x1, 0, 0},
+ {0x78, 0x66, 0x66, 0, 0},
+ {0x79, 0x66, 0x66, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0xff, 0xff, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0x95, 0, 0, 0, 0},
+ {0x96, 0, 0, 0, 0},
+ {0x97, 0, 0, 0, 0},
+ {0x98, 0, 0, 0, 0},
+ {0x99, 0, 0, 0, 0},
+ {0x9A, 0, 0, 0, 0},
+ {0x9B, 0, 0, 0, 0},
+ {0x9C, 0, 0, 0, 0},
+ {0x9D, 0, 0, 0, 0},
+ {0x9E, 0, 0, 0, 0},
+ {0x9F, 0x6, 0x6, 0, 0},
+ {0xA0, 0x66, 0x66, 0, 0},
+ {0xA1, 0x66, 0x66, 0, 0},
+ {0xA2, 0x66, 0x66, 0, 0},
+ {0xA3, 0x66, 0x66, 0, 0},
+ {0xA4, 0x66, 0x66, 0, 0},
+ {0xA5, 0x66, 0x66, 0, 0},
+ {0xA6, 0x66, 0x66, 0, 0},
+ {0xA7, 0x66, 0x66, 0, 0},
+ {0xA8, 0x66, 0x66, 0, 0},
+ {0xA9, 0x66, 0x66, 0, 0},
+ {0xAA, 0x66, 0x66, 0, 0},
+ {0xAB, 0x66, 0x66, 0, 0},
+ {0xAC, 0x66, 0x66, 0, 0},
+ {0xAD, 0x66, 0x66, 0, 0},
+ {0xAE, 0x66, 0x66, 0, 0},
+ {0xAF, 0x66, 0x66, 0, 0},
+ {0xB0, 0x66, 0x66, 0, 0},
+ {0xB1, 0x66, 0x66, 0, 0},
+ {0xB2, 0x66, 0x66, 0, 0},
+ {0xB3, 0xa, 0xa, 0, 0},
+ {0xB4, 0, 0, 0, 0},
+ {0xB5, 0, 0, 0, 0},
+ {0xB6, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_TX_2056_rev8[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0x88, 0x88, 0, 0},
+ {0x22, 0x88, 0x88, 0, 0},
+ {0x23, 0x88, 0x88, 0, 0},
+ {0x24, 0x88, 0x88, 0, 0},
+ {0x25, 0xc, 0xc, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0x3, 0x3, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0x3, 0x3, 0, 0},
+ {0x2A, 0x37, 0x37, 0, 0},
+ {0x2B, 0x3, 0x3, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0x1, 0x1, 0, 0},
+ {0x2F, 0x1, 0x1, 0, 0},
+ {0x30, 0, 0, 0, 0},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0x11, 0x11, 0, 0},
+ {0x34, 0xee, 0xee, 1, 1},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0x3, 0x3, 0, 0},
+ {0x38, 0x50, 0x50, 1, 1},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0x50, 0x50, 1, 1},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x6e, 0x6e, 0, 0},
+ {0x3D, 0xf0, 0xf0, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x3, 0x3, 0, 0},
+ {0x42, 0x3, 0x3, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x1e, 0x1e, 0, 0},
+ {0x45, 0, 0, 0, 0},
+ {0x46, 0x6e, 0x6e, 0, 0},
+ {0x47, 0xf0, 0xf0, 1, 1},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x2, 0x2, 0, 0},
+ {0x4A, 0xff, 0xff, 1, 1},
+ {0x4B, 0xc, 0xc, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0x38, 0x38, 0, 0},
+ {0x4E, 0x70, 0x70, 1, 1},
+ {0x4F, 0x2, 0x2, 0, 0},
+ {0x50, 0x88, 0x88, 0, 0},
+ {0x51, 0xc, 0xc, 0, 0},
+ {0x52, 0, 0, 0, 0},
+ {0x53, 0x8, 0x8, 0, 0},
+ {0x54, 0x70, 0x70, 1, 1},
+ {0x55, 0x2, 0x2, 0, 0},
+ {0x56, 0xff, 0xff, 1, 1},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x83, 0x83, 0, 0},
+ {0x59, 0x77, 0x77, 1, 1},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x88, 0x88, 0, 0},
+ {0x5D, 0, 0, 0, 0},
+ {0x5E, 0x8, 0x8, 0, 0},
+ {0x5F, 0x77, 0x77, 1, 1},
+ {0x60, 0x1, 0x1, 0, 0},
+ {0x61, 0, 0, 0, 0},
+ {0x62, 0x7, 0x7, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0x7, 0x7, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 1, 1},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0xa, 0xa, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0x2, 0x2, 0, 0},
+ {0x72, 0, 0, 0, 0},
+ {0x73, 0, 0, 0, 0},
+ {0x74, 0xe, 0xe, 0, 0},
+ {0x75, 0xe, 0xe, 0, 0},
+ {0x76, 0xe, 0xe, 0, 0},
+ {0x77, 0x13, 0x13, 0, 0},
+ {0x78, 0x13, 0x13, 0, 0},
+ {0x79, 0x1b, 0x1b, 0, 0},
+ {0x7A, 0x1b, 0x1b, 0, 0},
+ {0x7B, 0x55, 0x55, 0, 0},
+ {0x7C, 0x5b, 0x5b, 0, 0},
+ {0x7D, 0x30, 0x30, 1, 1},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0x70, 0x70, 0, 0},
+ {0x94, 0x70, 0x70, 0, 0},
+ {0x95, 0x70, 0x70, 0, 0},
+ {0x96, 0x70, 0x70, 0, 0},
+ {0x97, 0x70, 0x70, 0, 0},
+ {0x98, 0x70, 0x70, 0, 0},
+ {0x99, 0x70, 0x70, 0, 0},
+ {0x9A, 0x70, 0x70, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_RX_2056_rev8[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0x3, 0x3, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0, 0, 0, 0},
+ {0x23, 0x90, 0x90, 0, 0},
+ {0x24, 0x55, 0x55, 0, 0},
+ {0x25, 0x15, 0x15, 0, 0},
+ {0x26, 0x5, 0x5, 0, 0},
+ {0x27, 0x15, 0x15, 0, 0},
+ {0x28, 0x5, 0x5, 0, 0},
+ {0x29, 0x20, 0x20, 0, 0},
+ {0x2A, 0x11, 0x11, 0, 0},
+ {0x2B, 0x90, 0x90, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0x88, 0x88, 0, 0},
+ {0x2E, 0x32, 0x32, 0, 0},
+ {0x2F, 0x77, 0x77, 0, 0},
+ {0x30, 0x17, 0x17, 1, 1},
+ {0x31, 0xff, 0xff, 1, 1},
+ {0x32, 0x20, 0x20, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0x88, 0x88, 0, 0},
+ {0x35, 0x32, 0x32, 0, 0},
+ {0x36, 0x77, 0x77, 0, 0},
+ {0x37, 0x17, 0x17, 1, 1},
+ {0x38, 0xf0, 0xf0, 1, 1},
+ {0x39, 0x20, 0x20, 0, 0},
+ {0x3A, 0x8, 0x8, 0, 0},
+ {0x3B, 0x55, 0x55, 1, 1},
+ {0x3C, 0, 0, 0, 0},
+ {0x3D, 0x88, 0x88, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0x44, 0x44, 0, 0},
+ {0x40, 0x7, 0x7, 1, 1},
+ {0x41, 0x6, 0x6, 0, 0},
+ {0x42, 0x4, 0x4, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x8, 0x8, 0, 0},
+ {0x45, 0x55, 0x55, 1, 1},
+ {0x46, 0, 0, 0, 0},
+ {0x47, 0x11, 0x11, 0, 0},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x44, 0x44, 0, 0},
+ {0x4A, 0x7, 0x7, 0, 0},
+ {0x4B, 0x6, 0x6, 0, 0},
+ {0x4C, 0x4, 0x4, 0, 0},
+ {0x4D, 0, 0, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0x26, 0x26, 1, 1},
+ {0x50, 0x26, 0x26, 1, 1},
+ {0x51, 0xf, 0xf, 1, 1},
+ {0x52, 0xf, 0xf, 1, 1},
+ {0x53, 0x44, 0x44, 0, 0},
+ {0x54, 0, 0, 0, 0},
+ {0x55, 0, 0, 0, 0},
+ {0x56, 0x8, 0x8, 0, 0},
+ {0x57, 0x8, 0x8, 0, 0},
+ {0x58, 0x7, 0x7, 0, 0},
+ {0x59, 0x22, 0x22, 0, 0},
+ {0x5A, 0x22, 0x22, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x4, 0x4, 1, 1},
+ {0x5D, 0x7, 0x7, 0, 0},
+ {0x5E, 0x55, 0x55, 0, 0},
+ {0x5F, 0x23, 0x23, 0, 0},
+ {0x60, 0x41, 0x41, 0, 0},
+ {0x61, 0x1, 0x1, 0, 0},
+ {0x62, 0xa, 0xa, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0xc, 0xc, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0, 0, 0, 0},
+ {0x72, 0x22, 0x22, 0, 0},
+ {0x73, 0x22, 0x22, 0, 0},
+ {0x74, 0, 0, 1, 1},
+ {0x75, 0xa, 0xa, 0, 0},
+ {0x76, 0x1, 0x1, 0, 0},
+ {0x77, 0x22, 0x22, 0, 0},
+ {0x78, 0x30, 0x30, 0, 0},
+ {0x79, 0, 0, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0x5, 0x5, 1, 1},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_SYN_2056_rev11[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0x1, 0x1, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0x60, 0x60, 0, 0},
+ {0x23, 0x6, 0x6, 0, 0},
+ {0x24, 0xc, 0xc, 0, 0},
+ {0x25, 0, 0, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0, 0, 0, 0},
+ {0x28, 0x1, 0x1, 0, 0},
+ {0x29, 0, 0, 0, 0},
+ {0x2A, 0, 0, 0, 0},
+ {0x2B, 0, 0, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0, 0, 0, 0},
+ {0x2F, 0x1f, 0x1f, 0, 0},
+ {0x30, 0x15, 0x15, 0, 0},
+ {0x31, 0xf, 0xf, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0, 0, 0, 0},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0, 0, 0, 0},
+ {0x38, 0, 0, 0, 0},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0, 0, 0, 0},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x13, 0x13, 0, 0},
+ {0x3D, 0xf, 0xf, 0, 0},
+ {0x3E, 0x18, 0x18, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x20, 0x20, 0, 0},
+ {0x42, 0x20, 0x20, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x77, 0x77, 0, 0},
+ {0x45, 0x7, 0x7, 0, 0},
+ {0x46, 0x1, 0x1, 0, 0},
+ {0x47, 0x6, 0x6, 1, 1},
+ {0x48, 0xf, 0xf, 0, 0},
+ {0x49, 0x3f, 0x3f, 1, 1},
+ {0x4A, 0x32, 0x32, 0, 0},
+ {0x4B, 0x6, 0x6, 1, 1},
+ {0x4C, 0x6, 0x6, 1, 1},
+ {0x4D, 0x4, 0x4, 0, 0},
+ {0x4E, 0x2b, 0x2b, 1, 1},
+ {0x4F, 0x1, 0x1, 0, 0},
+ {0x50, 0x1c, 0x1c, 0, 0},
+ {0x51, 0x2, 0x2, 0, 0},
+ {0x52, 0x2, 0x2, 0, 0},
+ {0x53, 0xf7, 0xf7, 1, 1},
+ {0x54, 0xb4, 0xb4, 0, 0},
+ {0x55, 0xd2, 0xd2, 0, 0},
+ {0x56, 0, 0, 0, 0},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x4, 0x4, 0, 0},
+ {0x59, 0x96, 0x96, 0, 0},
+ {0x5A, 0x3e, 0x3e, 0, 0},
+ {0x5B, 0x3e, 0x3e, 0, 0},
+ {0x5C, 0x13, 0x13, 0, 0},
+ {0x5D, 0x2, 0x2, 0, 0},
+ {0x5E, 0, 0, 0, 0},
+ {0x5F, 0x7, 0x7, 0, 0},
+ {0x60, 0x7, 0x7, 1, 1},
+ {0x61, 0x8, 0x8, 0, 0},
+ {0x62, 0x3, 0x3, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0x40, 0x40, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0x1, 0x1, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0x60, 0x60, 0, 0},
+ {0x71, 0x66, 0x66, 0, 0},
+ {0x72, 0xc, 0xc, 0, 0},
+ {0x73, 0x66, 0x66, 0, 0},
+ {0x74, 0x8f, 0x8f, 1, 1},
+ {0x75, 0, 0, 0, 0},
+ {0x76, 0xcc, 0xcc, 0, 0},
+ {0x77, 0x1, 0x1, 0, 0},
+ {0x78, 0x66, 0x66, 0, 0},
+ {0x79, 0x66, 0x66, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0, 0, 0, 0},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0xff, 0xff, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0x95, 0, 0, 0, 0},
+ {0x96, 0, 0, 0, 0},
+ {0x97, 0, 0, 0, 0},
+ {0x98, 0, 0, 0, 0},
+ {0x99, 0, 0, 0, 0},
+ {0x9A, 0, 0, 0, 0},
+ {0x9B, 0, 0, 0, 0},
+ {0x9C, 0, 0, 0, 0},
+ {0x9D, 0, 0, 0, 0},
+ {0x9E, 0, 0, 0, 0},
+ {0x9F, 0x6, 0x6, 0, 0},
+ {0xA0, 0x66, 0x66, 0, 0},
+ {0xA1, 0x66, 0x66, 0, 0},
+ {0xA2, 0x66, 0x66, 0, 0},
+ {0xA3, 0x66, 0x66, 0, 0},
+ {0xA4, 0x66, 0x66, 0, 0},
+ {0xA5, 0x66, 0x66, 0, 0},
+ {0xA6, 0x66, 0x66, 0, 0},
+ {0xA7, 0x66, 0x66, 0, 0},
+ {0xA8, 0x66, 0x66, 0, 0},
+ {0xA9, 0x66, 0x66, 0, 0},
+ {0xAA, 0x66, 0x66, 0, 0},
+ {0xAB, 0x66, 0x66, 0, 0},
+ {0xAC, 0x66, 0x66, 0, 0},
+ {0xAD, 0x66, 0x66, 0, 0},
+ {0xAE, 0x66, 0x66, 0, 0},
+ {0xAF, 0x66, 0x66, 0, 0},
+ {0xB0, 0x66, 0x66, 0, 0},
+ {0xB1, 0x66, 0x66, 0, 0},
+ {0xB2, 0x66, 0x66, 0, 0},
+ {0xB3, 0xa, 0xa, 0, 0},
+ {0xB4, 0, 0, 0, 0},
+ {0xB5, 0, 0, 0, 0},
+ {0xB6, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_TX_2056_rev11[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0, 0, 0, 0},
+ {0x21, 0x88, 0x88, 0, 0},
+ {0x22, 0x88, 0x88, 0, 0},
+ {0x23, 0x88, 0x88, 0, 0},
+ {0x24, 0x88, 0x88, 0, 0},
+ {0x25, 0xc, 0xc, 0, 0},
+ {0x26, 0, 0, 0, 0},
+ {0x27, 0x3, 0x3, 0, 0},
+ {0x28, 0, 0, 0, 0},
+ {0x29, 0x3, 0x3, 0, 0},
+ {0x2A, 0x37, 0x37, 0, 0},
+ {0x2B, 0x3, 0x3, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0, 0, 0, 0},
+ {0x2E, 0x1, 0x1, 0, 0},
+ {0x2F, 0x1, 0x1, 0, 0},
+ {0x30, 0, 0, 0, 0},
+ {0x31, 0, 0, 0, 0},
+ {0x32, 0, 0, 0, 0},
+ {0x33, 0x11, 0x11, 0, 0},
+ {0x34, 0xee, 0xee, 1, 1},
+ {0x35, 0, 0, 0, 0},
+ {0x36, 0, 0, 0, 0},
+ {0x37, 0x3, 0x3, 0, 0},
+ {0x38, 0x50, 0x50, 1, 1},
+ {0x39, 0, 0, 0, 0},
+ {0x3A, 0x50, 0x50, 1, 1},
+ {0x3B, 0, 0, 0, 0},
+ {0x3C, 0x6e, 0x6e, 0, 0},
+ {0x3D, 0xf0, 0xf0, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0, 0, 0, 0},
+ {0x40, 0, 0, 0, 0},
+ {0x41, 0x3, 0x3, 0, 0},
+ {0x42, 0x3, 0x3, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x1e, 0x1e, 0, 0},
+ {0x45, 0, 0, 0, 0},
+ {0x46, 0x6e, 0x6e, 0, 0},
+ {0x47, 0xf0, 0xf0, 1, 1},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x2, 0x2, 0, 0},
+ {0x4A, 0xff, 0xff, 1, 1},
+ {0x4B, 0xc, 0xc, 0, 0},
+ {0x4C, 0, 0, 0, 0},
+ {0x4D, 0x38, 0x38, 0, 0},
+ {0x4E, 0x70, 0x70, 1, 1},
+ {0x4F, 0x2, 0x2, 0, 0},
+ {0x50, 0x88, 0x88, 0, 0},
+ {0x51, 0xc, 0xc, 0, 0},
+ {0x52, 0, 0, 0, 0},
+ {0x53, 0x8, 0x8, 0, 0},
+ {0x54, 0x70, 0x70, 1, 1},
+ {0x55, 0x2, 0x2, 0, 0},
+ {0x56, 0xff, 0xff, 1, 1},
+ {0x57, 0, 0, 0, 0},
+ {0x58, 0x83, 0x83, 0, 0},
+ {0x59, 0x77, 0x77, 1, 1},
+ {0x5A, 0, 0, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x88, 0x88, 0, 0},
+ {0x5D, 0, 0, 0, 0},
+ {0x5E, 0x8, 0x8, 0, 0},
+ {0x5F, 0x77, 0x77, 1, 1},
+ {0x60, 0x1, 0x1, 0, 0},
+ {0x61, 0, 0, 0, 0},
+ {0x62, 0x7, 0x7, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0x7, 0x7, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 1, 1},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0xa, 0xa, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0, 0, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0x2, 0x2, 0, 0},
+ {0x72, 0, 0, 0, 0},
+ {0x73, 0, 0, 0, 0},
+ {0x74, 0xe, 0xe, 0, 0},
+ {0x75, 0xe, 0xe, 0, 0},
+ {0x76, 0xe, 0xe, 0, 0},
+ {0x77, 0x13, 0x13, 0, 0},
+ {0x78, 0x13, 0x13, 0, 0},
+ {0x79, 0x1b, 0x1b, 0, 0},
+ {0x7A, 0x1b, 0x1b, 0, 0},
+ {0x7B, 0x55, 0x55, 0, 0},
+ {0x7C, 0x5b, 0x5b, 0, 0},
+ {0x7D, 0x30, 0x30, 1, 1},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0x70, 0x70, 0, 0},
+ {0x94, 0x70, 0x70, 0, 0},
+ {0x95, 0x70, 0x70, 0, 0},
+ {0x96, 0x70, 0x70, 0, 0},
+ {0x97, 0x70, 0x70, 0, 0},
+ {0x98, 0x70, 0x70, 0, 0},
+ {0x99, 0x70, 0x70, 0, 0},
+ {0x9A, 0x70, 0x70, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_regs_t regs_RX_2056_rev11[] = {
+ {0x02, 0, 0, 0, 0},
+ {0x03, 0, 0, 0, 0},
+ {0x04, 0, 0, 0, 0},
+ {0x05, 0, 0, 0, 0},
+ {0x06, 0, 0, 0, 0},
+ {0x07, 0, 0, 0, 0},
+ {0x08, 0, 0, 0, 0},
+ {0x09, 0, 0, 0, 0},
+ {0x0A, 0, 0, 0, 0},
+ {0x0B, 0, 0, 0, 0},
+ {0x0C, 0, 0, 0, 0},
+ {0x0D, 0, 0, 0, 0},
+ {0x0E, 0, 0, 0, 0},
+ {0x0F, 0, 0, 0, 0},
+ {0x10, 0, 0, 0, 0},
+ {0x11, 0, 0, 0, 0},
+ {0x12, 0, 0, 0, 0},
+ {0x13, 0, 0, 0, 0},
+ {0x14, 0, 0, 0, 0},
+ {0x15, 0, 0, 0, 0},
+ {0x16, 0, 0, 0, 0},
+ {0x17, 0, 0, 0, 0},
+ {0x18, 0, 0, 0, 0},
+ {0x19, 0, 0, 0, 0},
+ {0x1A, 0, 0, 0, 0},
+ {0x1B, 0, 0, 0, 0},
+ {0x1C, 0, 0, 0, 0},
+ {0x1D, 0, 0, 0, 0},
+ {0x1E, 0, 0, 0, 0},
+ {0x1F, 0, 0, 0, 0},
+ {0x20, 0x3, 0x3, 0, 0},
+ {0x21, 0, 0, 0, 0},
+ {0x22, 0, 0, 0, 0},
+ {0x23, 0x90, 0x90, 0, 0},
+ {0x24, 0x55, 0x55, 0, 0},
+ {0x25, 0x15, 0x15, 0, 0},
+ {0x26, 0x5, 0x5, 0, 0},
+ {0x27, 0x15, 0x15, 0, 0},
+ {0x28, 0x5, 0x5, 0, 0},
+ {0x29, 0x20, 0x20, 0, 0},
+ {0x2A, 0x11, 0x11, 0, 0},
+ {0x2B, 0x90, 0x90, 0, 0},
+ {0x2C, 0, 0, 0, 0},
+ {0x2D, 0x88, 0x88, 0, 0},
+ {0x2E, 0x32, 0x32, 0, 0},
+ {0x2F, 0x77, 0x77, 0, 0},
+ {0x30, 0x17, 0x17, 1, 1},
+ {0x31, 0xff, 0xff, 1, 1},
+ {0x32, 0x20, 0x20, 0, 0},
+ {0x33, 0, 0, 0, 0},
+ {0x34, 0x88, 0x88, 0, 0},
+ {0x35, 0x32, 0x32, 0, 0},
+ {0x36, 0x77, 0x77, 0, 0},
+ {0x37, 0x17, 0x17, 1, 1},
+ {0x38, 0xf0, 0xf0, 1, 1},
+ {0x39, 0x20, 0x20, 0, 0},
+ {0x3A, 0x8, 0x8, 0, 0},
+ {0x3B, 0x55, 0x55, 1, 1},
+ {0x3C, 0, 0, 0, 0},
+ {0x3D, 0x88, 0x88, 1, 1},
+ {0x3E, 0, 0, 0, 0},
+ {0x3F, 0x44, 0x44, 0, 0},
+ {0x40, 0x7, 0x7, 1, 1},
+ {0x41, 0x6, 0x6, 0, 0},
+ {0x42, 0x4, 0x4, 0, 0},
+ {0x43, 0, 0, 0, 0},
+ {0x44, 0x8, 0x8, 0, 0},
+ {0x45, 0x55, 0x55, 1, 1},
+ {0x46, 0, 0, 0, 0},
+ {0x47, 0x11, 0x11, 0, 0},
+ {0x48, 0, 0, 0, 0},
+ {0x49, 0x44, 0x44, 0, 0},
+ {0x4A, 0x7, 0x7, 0, 0},
+ {0x4B, 0x6, 0x6, 0, 0},
+ {0x4C, 0x4, 0x4, 0, 0},
+ {0x4D, 0, 0, 0, 0},
+ {0x4E, 0, 0, 0, 0},
+ {0x4F, 0x26, 0x26, 1, 1},
+ {0x50, 0x26, 0x26, 1, 1},
+ {0x51, 0xf, 0xf, 1, 1},
+ {0x52, 0xf, 0xf, 1, 1},
+ {0x53, 0x44, 0x44, 0, 0},
+ {0x54, 0, 0, 0, 0},
+ {0x55, 0, 0, 0, 0},
+ {0x56, 0x8, 0x8, 0, 0},
+ {0x57, 0x8, 0x8, 0, 0},
+ {0x58, 0x7, 0x7, 0, 0},
+ {0x59, 0x22, 0x22, 0, 0},
+ {0x5A, 0x22, 0x22, 0, 0},
+ {0x5B, 0x2, 0x2, 0, 0},
+ {0x5C, 0x4, 0x4, 1, 1},
+ {0x5D, 0x7, 0x7, 0, 0},
+ {0x5E, 0x55, 0x55, 0, 0},
+ {0x5F, 0x23, 0x23, 0, 0},
+ {0x60, 0x41, 0x41, 0, 0},
+ {0x61, 0x1, 0x1, 0, 0},
+ {0x62, 0xa, 0xa, 0, 0},
+ {0x63, 0, 0, 0, 0},
+ {0x64, 0, 0, 0, 0},
+ {0x65, 0, 0, 0, 0},
+ {0x66, 0, 0, 0, 0},
+ {0x67, 0, 0, 0, 0},
+ {0x68, 0, 0, 0, 0},
+ {0x69, 0, 0, 0, 0},
+ {0x6A, 0, 0, 0, 0},
+ {0x6B, 0xc, 0xc, 0, 0},
+ {0x6C, 0, 0, 0, 0},
+ {0x6D, 0, 0, 0, 0},
+ {0x6E, 0, 0, 0, 0},
+ {0x6F, 0, 0, 0, 0},
+ {0x70, 0, 0, 0, 0},
+ {0x71, 0, 0, 0, 0},
+ {0x72, 0x22, 0x22, 0, 0},
+ {0x73, 0x22, 0x22, 0, 0},
+ {0x74, 0, 0, 1, 1},
+ {0x75, 0xa, 0xa, 0, 0},
+ {0x76, 0x1, 0x1, 0, 0},
+ {0x77, 0x22, 0x22, 0, 0},
+ {0x78, 0x30, 0x30, 0, 0},
+ {0x79, 0, 0, 0, 0},
+ {0x7A, 0, 0, 0, 0},
+ {0x7B, 0, 0, 0, 0},
+ {0x7C, 0, 0, 0, 0},
+ {0x7D, 0x5, 0x5, 1, 1},
+ {0x7E, 0, 0, 0, 0},
+ {0x7F, 0, 0, 0, 0},
+ {0x80, 0, 0, 0, 0},
+ {0x81, 0, 0, 0, 0},
+ {0x82, 0, 0, 0, 0},
+ {0x83, 0, 0, 0, 0},
+ {0x84, 0, 0, 0, 0},
+ {0x85, 0, 0, 0, 0},
+ {0x86, 0, 0, 0, 0},
+ {0x87, 0, 0, 0, 0},
+ {0x88, 0, 0, 0, 0},
+ {0x89, 0, 0, 0, 0},
+ {0x8A, 0, 0, 0, 0},
+ {0x8B, 0, 0, 0, 0},
+ {0x8C, 0, 0, 0, 0},
+ {0x8D, 0, 0, 0, 0},
+ {0x8E, 0, 0, 0, 0},
+ {0x8F, 0, 0, 0, 0},
+ {0x90, 0, 0, 0, 0},
+ {0x91, 0, 0, 0, 0},
+ {0x92, 0, 0, 0, 0},
+ {0x93, 0, 0, 0, 0},
+ {0x94, 0, 0, 0, 0},
+ {0xFFFF, 0, 0, 0, 0},
+};
+
+radio_20xx_regs_t regs_2057_rev4[] = {
+ {0x00, 0x84, 0},
+ {0x01, 0, 0},
+ {0x02, 0x60, 0},
+ {0x03, 0x1f, 0},
+ {0x04, 0x4, 0},
+ {0x05, 0x2, 0},
+ {0x06, 0x1, 0},
+ {0x07, 0x1, 0},
+ {0x08, 0x1, 0},
+ {0x09, 0x69, 0},
+ {0x0A, 0x66, 0},
+ {0x0B, 0x6, 0},
+ {0x0C, 0x18, 0},
+ {0x0D, 0x3, 0},
+ {0x0E, 0x20, 1},
+ {0x0F, 0x20, 0},
+ {0x10, 0, 0},
+ {0x11, 0x7c, 0},
+ {0x12, 0x42, 0},
+ {0x13, 0xbd, 0},
+ {0x14, 0x7, 0},
+ {0x15, 0xf7, 0},
+ {0x16, 0x8, 0},
+ {0x17, 0x17, 0},
+ {0x18, 0x7, 0},
+ {0x19, 0, 0},
+ {0x1A, 0x2, 0},
+ {0x1B, 0x13, 0},
+ {0x1C, 0x3e, 0},
+ {0x1D, 0x3e, 0},
+ {0x1E, 0x96, 0},
+ {0x1F, 0x4, 0},
+ {0x20, 0, 0},
+ {0x21, 0, 0},
+ {0x22, 0x17, 0},
+ {0x23, 0x4, 0},
+ {0x24, 0x1, 0},
+ {0x25, 0x6, 0},
+ {0x26, 0x4, 0},
+ {0x27, 0xd, 0},
+ {0x28, 0xd, 0},
+ {0x29, 0x30, 0},
+ {0x2A, 0x32, 0},
+ {0x2B, 0x8, 0},
+ {0x2C, 0x1c, 0},
+ {0x2D, 0x2, 0},
+ {0x2E, 0x4, 0},
+ {0x2F, 0x7f, 0},
+ {0x30, 0x27, 0},
+ {0x31, 0, 1},
+ {0x32, 0, 1},
+ {0x33, 0, 1},
+ {0x34, 0, 0},
+ {0x35, 0x26, 1},
+ {0x36, 0x18, 0},
+ {0x37, 0x7, 0},
+ {0x38, 0x66, 0},
+ {0x39, 0x66, 0},
+ {0x3A, 0x66, 0},
+ {0x3B, 0x66, 0},
+ {0x3C, 0xff, 1},
+ {0x3D, 0xff, 1},
+ {0x3E, 0xff, 1},
+ {0x3F, 0xff, 1},
+ {0x40, 0x16, 0},
+ {0x41, 0x7, 0},
+ {0x42, 0x19, 0},
+ {0x43, 0x7, 0},
+ {0x44, 0x6, 0},
+ {0x45, 0x3, 0},
+ {0x46, 0x1, 0},
+ {0x47, 0x7, 0},
+ {0x48, 0x33, 0},
+ {0x49, 0x5, 0},
+ {0x4A, 0x77, 0},
+ {0x4B, 0x66, 0},
+ {0x4C, 0x66, 0},
+ {0x4D, 0, 0},
+ {0x4E, 0x4, 0},
+ {0x4F, 0xc, 0},
+ {0x50, 0, 0},
+ {0x51, 0x75, 0},
+ {0x56, 0x7, 0},
+ {0x57, 0, 0},
+ {0x58, 0, 0},
+ {0x59, 0xa8, 0},
+ {0x5A, 0, 0},
+ {0x5B, 0x1f, 0},
+ {0x5C, 0x30, 0},
+ {0x5D, 0x1, 0},
+ {0x5E, 0x30, 0},
+ {0x5F, 0x70, 0},
+ {0x60, 0, 0},
+ {0x61, 0, 0},
+ {0x62, 0x33, 1},
+ {0x63, 0x19, 0},
+ {0x64, 0x62, 0},
+ {0x65, 0, 0},
+ {0x66, 0x11, 0},
+ {0x69, 0, 0},
+ {0x6A, 0x7e, 0},
+ {0x6B, 0x3f, 0},
+ {0x6C, 0x7f, 0},
+ {0x6D, 0x78, 0},
+ {0x6E, 0xc8, 0},
+ {0x6F, 0x88, 0},
+ {0x70, 0x8, 0},
+ {0x71, 0xf, 0},
+ {0x72, 0xbc, 0},
+ {0x73, 0x8, 0},
+ {0x74, 0x60, 0},
+ {0x75, 0x1e, 0},
+ {0x76, 0x70, 0},
+ {0x77, 0, 0},
+ {0x78, 0, 0},
+ {0x79, 0, 0},
+ {0x7A, 0x33, 0},
+ {0x7B, 0x1e, 0},
+ {0x7C, 0x62, 0},
+ {0x7D, 0x11, 0},
+ {0x80, 0x3c, 0},
+ {0x81, 0x9c, 0},
+ {0x82, 0xa, 0},
+ {0x83, 0x9d, 0},
+ {0x84, 0xa, 0},
+ {0x85, 0, 0},
+ {0x86, 0x40, 0},
+ {0x87, 0x40, 0},
+ {0x88, 0x88, 0},
+ {0x89, 0x10, 0},
+ {0x8A, 0xf0, 1},
+ {0x8B, 0x10, 1},
+ {0x8C, 0xf0, 1},
+ {0x8D, 0, 0},
+ {0x8E, 0, 0},
+ {0x8F, 0x10, 0},
+ {0x90, 0x55, 0},
+ {0x91, 0x3f, 1},
+ {0x92, 0x36, 1},
+ {0x93, 0, 0},
+ {0x94, 0, 0},
+ {0x95, 0, 0},
+ {0x96, 0x87, 0},
+ {0x97, 0x11, 0},
+ {0x98, 0, 0},
+ {0x99, 0x33, 0},
+ {0x9A, 0x88, 0},
+ {0x9B, 0, 0},
+ {0x9C, 0x87, 0},
+ {0x9D, 0x11, 0},
+ {0x9E, 0, 0},
+ {0x9F, 0x33, 0},
+ {0xA0, 0x88, 0},
+ {0xA1, 0xe1, 0},
+ {0xA2, 0x3f, 0},
+ {0xA3, 0x44, 0},
+ {0xA4, 0x8c, 1},
+ {0xA5, 0x6d, 0},
+ {0xA6, 0x22, 0},
+ {0xA7, 0xbe, 0},
+ {0xA8, 0x55, 1},
+ {0xA9, 0xc, 0},
+ {0xAA, 0xc, 0},
+ {0xAB, 0xaa, 0},
+ {0xAC, 0x2, 0},
+ {0xAD, 0, 0},
+ {0xAE, 0x10, 0},
+ {0xAF, 0x1, 1},
+ {0xB0, 0, 0},
+ {0xB1, 0, 0},
+ {0xB2, 0x80, 0},
+ {0xB3, 0x60, 0},
+ {0xB4, 0x44, 0},
+ {0xB5, 0x55, 0},
+ {0xB6, 0x1, 0},
+ {0xB7, 0x55, 0},
+ {0xB8, 0x1, 0},
+ {0xB9, 0x5, 0},
+ {0xBA, 0x55, 0},
+ {0xBB, 0x55, 0},
+ {0xC1, 0, 0},
+ {0xC2, 0, 0},
+ {0xC3, 0, 0},
+ {0xC4, 0, 0},
+ {0xC5, 0, 0},
+ {0xC6, 0, 0},
+ {0xC7, 0, 0},
+ {0xC8, 0, 0},
+ {0xC9, 0, 0},
+ {0xCA, 0, 0},
+ {0xCB, 0, 0},
+ {0xCC, 0, 0},
+ {0xCD, 0, 0},
+ {0xCE, 0x5e, 0},
+ {0xCF, 0xc, 0},
+ {0xD0, 0xc, 0},
+ {0xD1, 0xc, 0},
+ {0xD2, 0, 0},
+ {0xD3, 0x2b, 0},
+ {0xD4, 0xc, 0},
+ {0xD5, 0, 0},
+ {0xD6, 0x75, 0},
+ {0xDB, 0x7, 0},
+ {0xDC, 0, 0},
+ {0xDD, 0, 0},
+ {0xDE, 0xa8, 0},
+ {0xDF, 0, 0},
+ {0xE0, 0x1f, 0},
+ {0xE1, 0x30, 0},
+ {0xE2, 0x1, 0},
+ {0xE3, 0x30, 0},
+ {0xE4, 0x70, 0},
+ {0xE5, 0, 0},
+ {0xE6, 0, 0},
+ {0xE7, 0x33, 0},
+ {0xE8, 0x19, 0},
+ {0xE9, 0x62, 0},
+ {0xEA, 0, 0},
+ {0xEB, 0x11, 0},
+ {0xEE, 0, 0},
+ {0xEF, 0x7e, 0},
+ {0xF0, 0x3f, 0},
+ {0xF1, 0x7f, 0},
+ {0xF2, 0x78, 0},
+ {0xF3, 0xc8, 0},
+ {0xF4, 0x88, 0},
+ {0xF5, 0x8, 0},
+ {0xF6, 0xf, 0},
+ {0xF7, 0xbc, 0},
+ {0xF8, 0x8, 0},
+ {0xF9, 0x60, 0},
+ {0xFA, 0x1e, 0},
+ {0xFB, 0x70, 0},
+ {0xFC, 0, 0},
+ {0xFD, 0, 0},
+ {0xFE, 0, 0},
+ {0xFF, 0x33, 0},
+ {0x100, 0x1e, 0},
+ {0x101, 0x62, 0},
+ {0x102, 0x11, 0},
+ {0x105, 0x3c, 0},
+ {0x106, 0x9c, 0},
+ {0x107, 0xa, 0},
+ {0x108, 0x9d, 0},
+ {0x109, 0xa, 0},
+ {0x10A, 0, 0},
+ {0x10B, 0x40, 0},
+ {0x10C, 0x40, 0},
+ {0x10D, 0x88, 0},
+ {0x10E, 0x10, 0},
+ {0x10F, 0xf0, 1},
+ {0x110, 0x10, 1},
+ {0x111, 0xf0, 1},
+ {0x112, 0, 0},
+ {0x113, 0, 0},
+ {0x114, 0x10, 0},
+ {0x115, 0x55, 0},
+ {0x116, 0x3f, 1},
+ {0x117, 0x36, 1},
+ {0x118, 0, 0},
+ {0x119, 0, 0},
+ {0x11A, 0, 0},
+ {0x11B, 0x87, 0},
+ {0x11C, 0x11, 0},
+ {0x11D, 0, 0},
+ {0x11E, 0x33, 0},
+ {0x11F, 0x88, 0},
+ {0x120, 0, 0},
+ {0x121, 0x87, 0},
+ {0x122, 0x11, 0},
+ {0x123, 0, 0},
+ {0x124, 0x33, 0},
+ {0x125, 0x88, 0},
+ {0x126, 0xe1, 0},
+ {0x127, 0x3f, 0},
+ {0x128, 0x44, 0},
+ {0x129, 0x8c, 1},
+ {0x12A, 0x6d, 0},
+ {0x12B, 0x22, 0},
+ {0x12C, 0xbe, 0},
+ {0x12D, 0x55, 1},
+ {0x12E, 0xc, 0},
+ {0x12F, 0xc, 0},
+ {0x130, 0xaa, 0},
+ {0x131, 0x2, 0},
+ {0x132, 0, 0},
+ {0x133, 0x10, 0},
+ {0x134, 0x1, 1},
+ {0x135, 0, 0},
+ {0x136, 0, 0},
+ {0x137, 0x80, 0},
+ {0x138, 0x60, 0},
+ {0x139, 0x44, 0},
+ {0x13A, 0x55, 0},
+ {0x13B, 0x1, 0},
+ {0x13C, 0x55, 0},
+ {0x13D, 0x1, 0},
+ {0x13E, 0x5, 0},
+ {0x13F, 0x55, 0},
+ {0x140, 0x55, 0},
+ {0x146, 0, 0},
+ {0x147, 0, 0},
+ {0x148, 0, 0},
+ {0x149, 0, 0},
+ {0x14A, 0, 0},
+ {0x14B, 0, 0},
+ {0x14C, 0, 0},
+ {0x14D, 0, 0},
+ {0x14E, 0, 0},
+ {0x14F, 0, 0},
+ {0x150, 0, 0},
+ {0x151, 0, 0},
+ {0x152, 0, 0},
+ {0x153, 0, 0},
+ {0x154, 0xc, 0},
+ {0x155, 0xc, 0},
+ {0x156, 0xc, 0},
+ {0x157, 0, 0},
+ {0x158, 0x2b, 0},
+ {0x159, 0x84, 0},
+ {0x15A, 0x15, 0},
+ {0x15B, 0xf, 0},
+ {0x15C, 0, 0},
+ {0x15D, 0, 0},
+ {0x15E, 0, 1},
+ {0x15F, 0, 1},
+ {0x160, 0, 1},
+ {0x161, 0, 1},
+ {0x162, 0, 1},
+ {0x163, 0, 1},
+ {0x164, 0, 0},
+ {0x165, 0, 0},
+ {0x166, 0, 0},
+ {0x167, 0, 0},
+ {0x168, 0, 0},
+ {0x169, 0x2, 1},
+ {0x16A, 0, 1},
+ {0x16B, 0, 1},
+ {0x16C, 0, 1},
+ {0x16D, 0, 0},
+ {0x170, 0, 0},
+ {0x171, 0x77, 0},
+ {0x172, 0x77, 0},
+ {0x173, 0x77, 0},
+ {0x174, 0x77, 0},
+ {0x175, 0, 0},
+ {0x176, 0x3, 0},
+ {0x177, 0x37, 0},
+ {0x178, 0x3, 0},
+ {0x179, 0, 0},
+ {0x17A, 0x21, 0},
+ {0x17B, 0x21, 0},
+ {0x17C, 0, 0},
+ {0x17D, 0xaa, 0},
+ {0x17E, 0, 0},
+ {0x17F, 0xaa, 0},
+ {0x180, 0, 0},
+ {0x190, 0, 0},
+ {0x191, 0x77, 0},
+ {0x192, 0x77, 0},
+ {0x193, 0x77, 0},
+ {0x194, 0x77, 0},
+ {0x195, 0, 0},
+ {0x196, 0x3, 0},
+ {0x197, 0x37, 0},
+ {0x198, 0x3, 0},
+ {0x199, 0, 0},
+ {0x19A, 0x21, 0},
+ {0x19B, 0x21, 0},
+ {0x19C, 0, 0},
+ {0x19D, 0xaa, 0},
+ {0x19E, 0, 0},
+ {0x19F, 0xaa, 0},
+ {0x1A0, 0, 0},
+ {0x1A1, 0x2, 0},
+ {0x1A2, 0xf, 0},
+ {0x1A3, 0xf, 0},
+ {0x1A4, 0, 1},
+ {0x1A5, 0, 1},
+ {0x1A6, 0, 1},
+ {0x1A7, 0x2, 0},
+ {0x1A8, 0xf, 0},
+ {0x1A9, 0xf, 0},
+ {0x1AA, 0, 1},
+ {0x1AB, 0, 1},
+ {0x1AC, 0, 1},
+ {0xFFFF, 0, 0},
+};
+
+radio_20xx_regs_t regs_2057_rev5[] = {
+ {0x00, 0, 1},
+ {0x01, 0x57, 1},
+ {0x02, 0x20, 1},
+ {0x03, 0x1f, 0},
+ {0x04, 0x4, 0},
+ {0x05, 0x2, 0},
+ {0x06, 0x1, 0},
+ {0x07, 0x1, 0},
+ {0x08, 0x1, 0},
+ {0x09, 0x69, 0},
+ {0x0A, 0x66, 0},
+ {0x0B, 0x6, 0},
+ {0x0C, 0x18, 0},
+ {0x0D, 0x3, 0},
+ {0x0E, 0x20, 0},
+ {0x0F, 0x20, 0},
+ {0x10, 0, 0},
+ {0x11, 0x7c, 0},
+ {0x12, 0x42, 0},
+ {0x13, 0xbd, 0},
+ {0x14, 0x7, 0},
+ {0x15, 0x87, 0},
+ {0x16, 0x8, 0},
+ {0x17, 0x17, 0},
+ {0x18, 0x7, 0},
+ {0x19, 0, 0},
+ {0x1A, 0x2, 0},
+ {0x1B, 0x13, 0},
+ {0x1C, 0x3e, 0},
+ {0x1D, 0x3e, 0},
+ {0x1E, 0x96, 0},
+ {0x1F, 0x4, 0},
+ {0x20, 0, 0},
+ {0x21, 0, 0},
+ {0x22, 0x17, 0},
+ {0x23, 0x6, 1},
+ {0x24, 0x1, 0},
+ {0x25, 0x6, 0},
+ {0x26, 0x4, 0},
+ {0x27, 0xd, 0},
+ {0x28, 0xd, 0},
+ {0x29, 0x30, 0},
+ {0x2A, 0x32, 0},
+ {0x2B, 0x8, 0},
+ {0x2C, 0x1c, 0},
+ {0x2D, 0x2, 0},
+ {0x2E, 0x4, 0},
+ {0x2F, 0x7f, 0},
+ {0x30, 0x27, 0},
+ {0x31, 0, 1},
+ {0x32, 0, 1},
+ {0x33, 0, 1},
+ {0x34, 0, 0},
+ {0x35, 0x20, 0},
+ {0x36, 0x18, 0},
+ {0x37, 0x7, 0},
+ {0x38, 0x66, 0},
+ {0x39, 0x66, 0},
+ {0x3C, 0xff, 0},
+ {0x3D, 0xff, 0},
+ {0x40, 0x16, 0},
+ {0x41, 0x7, 0},
+ {0x45, 0x3, 0},
+ {0x46, 0x1, 0},
+ {0x47, 0x7, 0},
+ {0x4B, 0x66, 0},
+ {0x4C, 0x66, 0},
+ {0x4D, 0, 0},
+ {0x4E, 0x4, 0},
+ {0x4F, 0xc, 0},
+ {0x50, 0, 0},
+ {0x51, 0x70, 1},
+ {0x56, 0x7, 0},
+ {0x57, 0, 0},
+ {0x58, 0, 0},
+ {0x59, 0x88, 1},
+ {0x5A, 0, 0},
+ {0x5B, 0x1f, 0},
+ {0x5C, 0x20, 1},
+ {0x5D, 0x1, 0},
+ {0x5E, 0x30, 0},
+ {0x5F, 0x70, 0},
+ {0x60, 0, 0},
+ {0x61, 0, 0},
+ {0x62, 0x33, 1},
+ {0x63, 0xf, 1},
+ {0x64, 0xf, 1},
+ {0x65, 0, 0},
+ {0x66, 0x11, 0},
+ {0x80, 0x3c, 0},
+ {0x81, 0x1, 1},
+ {0x82, 0xa, 0},
+ {0x85, 0, 0},
+ {0x86, 0x40, 0},
+ {0x87, 0x40, 0},
+ {0x88, 0x88, 0},
+ {0x89, 0x10, 0},
+ {0x8A, 0xf0, 0},
+ {0x8B, 0x10, 0},
+ {0x8C, 0xf0, 0},
+ {0x8F, 0x10, 0},
+ {0x90, 0x55, 0},
+ {0x91, 0x3f, 1},
+ {0x92, 0x36, 1},
+ {0x93, 0, 0},
+ {0x94, 0, 0},
+ {0x95, 0, 0},
+ {0x96, 0x87, 0},
+ {0x97, 0x11, 0},
+ {0x98, 0, 0},
+ {0x99, 0x33, 0},
+ {0x9A, 0x88, 0},
+ {0xA1, 0x20, 1},
+ {0xA2, 0x3f, 0},
+ {0xA3, 0x44, 0},
+ {0xA4, 0x8c, 0},
+ {0xA5, 0x6c, 0},
+ {0xA6, 0x22, 0},
+ {0xA7, 0xbe, 0},
+ {0xA8, 0x55, 0},
+ {0xAA, 0xc, 0},
+ {0xAB, 0xaa, 0},
+ {0xAC, 0x2, 0},
+ {0xAD, 0, 0},
+ {0xAE, 0x10, 0},
+ {0xAF, 0x1, 0},
+ {0xB0, 0, 0},
+ {0xB1, 0, 0},
+ {0xB2, 0x80, 0},
+ {0xB3, 0x60, 0},
+ {0xB4, 0x44, 0},
+ {0xB5, 0x55, 0},
+ {0xB6, 0x1, 0},
+ {0xB7, 0x55, 0},
+ {0xB8, 0x1, 0},
+ {0xB9, 0x5, 0},
+ {0xBA, 0x55, 0},
+ {0xBB, 0x55, 0},
+ {0xC3, 0, 0},
+ {0xC4, 0, 0},
+ {0xC5, 0, 0},
+ {0xC6, 0, 0},
+ {0xC7, 0, 0},
+ {0xC8, 0, 0},
+ {0xC9, 0, 0},
+ {0xCA, 0, 0},
+ {0xCB, 0, 0},
+ {0xCD, 0, 0},
+ {0xCE, 0x5e, 0},
+ {0xCF, 0xc, 0},
+ {0xD0, 0xc, 0},
+ {0xD1, 0xc, 0},
+ {0xD2, 0, 0},
+ {0xD3, 0x2b, 0},
+ {0xD4, 0xc, 0},
+ {0xD5, 0, 0},
+ {0xD6, 0x70, 1},
+ {0xDB, 0x7, 0},
+ {0xDC, 0, 0},
+ {0xDD, 0, 0},
+ {0xDE, 0x88, 1},
+ {0xDF, 0, 0},
+ {0xE0, 0x1f, 0},
+ {0xE1, 0x20, 1},
+ {0xE2, 0x1, 0},
+ {0xE3, 0x30, 0},
+ {0xE4, 0x70, 0},
+ {0xE5, 0, 0},
+ {0xE6, 0, 0},
+ {0xE7, 0x33, 0},
+ {0xE8, 0xf, 1},
+ {0xE9, 0xf, 1},
+ {0xEA, 0, 0},
+ {0xEB, 0x11, 0},
+ {0x105, 0x3c, 0},
+ {0x106, 0x1, 1},
+ {0x107, 0xa, 0},
+ {0x10A, 0, 0},
+ {0x10B, 0x40, 0},
+ {0x10C, 0x40, 0},
+ {0x10D, 0x88, 0},
+ {0x10E, 0x10, 0},
+ {0x10F, 0xf0, 0},
+ {0x110, 0x10, 0},
+ {0x111, 0xf0, 0},
+ {0x114, 0x10, 0},
+ {0x115, 0x55, 0},
+ {0x116, 0x3f, 1},
+ {0x117, 0x36, 1},
+ {0x118, 0, 0},
+ {0x119, 0, 0},
+ {0x11A, 0, 0},
+ {0x11B, 0x87, 0},
+ {0x11C, 0x11, 0},
+ {0x11D, 0, 0},
+ {0x11E, 0x33, 0},
+ {0x11F, 0x88, 0},
+ {0x126, 0x20, 1},
+ {0x127, 0x3f, 0},
+ {0x128, 0x44, 0},
+ {0x129, 0x8c, 0},
+ {0x12A, 0x6c, 0},
+ {0x12B, 0x22, 0},
+ {0x12C, 0xbe, 0},
+ {0x12D, 0x55, 0},
+ {0x12F, 0xc, 0},
+ {0x130, 0xaa, 0},
+ {0x131, 0x2, 0},
+ {0x132, 0, 0},
+ {0x133, 0x10, 0},
+ {0x134, 0x1, 0},
+ {0x135, 0, 0},
+ {0x136, 0, 0},
+ {0x137, 0x80, 0},
+ {0x138, 0x60, 0},
+ {0x139, 0x44, 0},
+ {0x13A, 0x55, 0},
+ {0x13B, 0x1, 0},
+ {0x13C, 0x55, 0},
+ {0x13D, 0x1, 0},
+ {0x13E, 0x5, 0},
+ {0x13F, 0x55, 0},
+ {0x140, 0x55, 0},
+ {0x148, 0, 0},
+ {0x149, 0, 0},
+ {0x14A, 0, 0},
+ {0x14B, 0, 0},
+ {0x14C, 0, 0},
+ {0x14D, 0, 0},
+ {0x14E, 0, 0},
+ {0x14F, 0, 0},
+ {0x150, 0, 0},
+ {0x154, 0xc, 0},
+ {0x155, 0xc, 0},
+ {0x156, 0xc, 0},
+ {0x157, 0, 0},
+ {0x158, 0x2b, 0},
+ {0x159, 0x84, 0},
+ {0x15A, 0x15, 0},
+ {0x15B, 0xf, 0},
+ {0x15C, 0, 0},
+ {0x15D, 0, 0},
+ {0x15E, 0, 1},
+ {0x15F, 0, 1},
+ {0x160, 0, 1},
+ {0x161, 0, 1},
+ {0x162, 0, 1},
+ {0x163, 0, 1},
+ {0x164, 0, 0},
+ {0x165, 0, 0},
+ {0x166, 0, 0},
+ {0x167, 0, 0},
+ {0x168, 0, 0},
+ {0x169, 0, 0},
+ {0x16A, 0, 1},
+ {0x16B, 0, 1},
+ {0x16C, 0, 1},
+ {0x16D, 0, 0},
+ {0x170, 0, 0},
+ {0x171, 0x77, 0},
+ {0x172, 0x77, 0},
+ {0x173, 0x77, 0},
+ {0x174, 0x77, 0},
+ {0x175, 0, 0},
+ {0x176, 0x3, 0},
+ {0x177, 0x37, 0},
+ {0x178, 0x3, 0},
+ {0x179, 0, 0},
+ {0x17B, 0x21, 0},
+ {0x17C, 0, 0},
+ {0x17D, 0xaa, 0},
+ {0x17E, 0, 0},
+ {0x190, 0, 0},
+ {0x191, 0x77, 0},
+ {0x192, 0x77, 0},
+ {0x193, 0x77, 0},
+ {0x194, 0x77, 0},
+ {0x195, 0, 0},
+ {0x196, 0x3, 0},
+ {0x197, 0x37, 0},
+ {0x198, 0x3, 0},
+ {0x199, 0, 0},
+ {0x19B, 0x21, 0},
+ {0x19C, 0, 0},
+ {0x19D, 0xaa, 0},
+ {0x19E, 0, 0},
+ {0x1A1, 0x2, 0},
+ {0x1A2, 0xf, 0},
+ {0x1A3, 0xf, 0},
+ {0x1A4, 0, 1},
+ {0x1A5, 0, 1},
+ {0x1A6, 0, 1},
+ {0x1A7, 0x2, 0},
+ {0x1A8, 0xf, 0},
+ {0x1A9, 0xf, 0},
+ {0x1AA, 0, 1},
+ {0x1AB, 0, 1},
+ {0x1AC, 0, 1},
+ {0x1AD, 0x84, 0},
+ {0x1AE, 0x60, 0},
+ {0x1AF, 0x47, 0},
+ {0x1B0, 0x47, 0},
+ {0x1B1, 0, 0},
+ {0x1B2, 0, 0},
+ {0x1B3, 0, 0},
+ {0x1B4, 0, 0},
+ {0x1B5, 0, 0},
+ {0x1B6, 0, 0},
+ {0x1B7, 0xc, 1},
+ {0x1B8, 0, 0},
+ {0x1B9, 0, 0},
+ {0x1BA, 0, 0},
+ {0x1BB, 0, 0},
+ {0x1BC, 0, 0},
+ {0x1BD, 0, 0},
+ {0x1BE, 0, 0},
+ {0x1BF, 0, 0},
+ {0x1C0, 0, 0},
+ {0x1C1, 0x1, 1},
+ {0x1C2, 0x80, 1},
+ {0x1C3, 0, 0},
+ {0x1C4, 0, 0},
+ {0x1C5, 0, 0},
+ {0x1C6, 0, 0},
+ {0x1C7, 0, 0},
+ {0x1C8, 0, 0},
+ {0x1C9, 0, 0},
+ {0x1CA, 0, 0},
+ {0xFFFF, 0, 0}
+};
+
+radio_20xx_regs_t regs_2057_rev5v1[] = {
+ {0x00, 0x15, 1},
+ {0x01, 0x57, 1},
+ {0x02, 0x20, 1},
+ {0x03, 0x1f, 0},
+ {0x04, 0x4, 0},
+ {0x05, 0x2, 0},
+ {0x06, 0x1, 0},
+ {0x07, 0x1, 0},
+ {0x08, 0x1, 0},
+ {0x09, 0x69, 0},
+ {0x0A, 0x66, 0},
+ {0x0B, 0x6, 0},
+ {0x0C, 0x18, 0},
+ {0x0D, 0x3, 0},
+ {0x0E, 0x20, 0},
+ {0x0F, 0x20, 0},
+ {0x10, 0, 0},
+ {0x11, 0x7c, 0},
+ {0x12, 0x42, 0},
+ {0x13, 0xbd, 0},
+ {0x14, 0x7, 0},
+ {0x15, 0x87, 0},
+ {0x16, 0x8, 0},
+ {0x17, 0x17, 0},
+ {0x18, 0x7, 0},
+ {0x19, 0, 0},
+ {0x1A, 0x2, 0},
+ {0x1B, 0x13, 0},
+ {0x1C, 0x3e, 0},
+ {0x1D, 0x3e, 0},
+ {0x1E, 0x96, 0},
+ {0x1F, 0x4, 0},
+ {0x20, 0, 0},
+ {0x21, 0, 0},
+ {0x22, 0x17, 0},
+ {0x23, 0x6, 1},
+ {0x24, 0x1, 0},
+ {0x25, 0x6, 0},
+ {0x26, 0x4, 0},
+ {0x27, 0xd, 0},
+ {0x28, 0xd, 0},
+ {0x29, 0x30, 0},
+ {0x2A, 0x32, 0},
+ {0x2B, 0x8, 0},
+ {0x2C, 0x1c, 0},
+ {0x2D, 0x2, 0},
+ {0x2E, 0x4, 0},
+ {0x2F, 0x7f, 0},
+ {0x30, 0x27, 0},
+ {0x31, 0, 1},
+ {0x32, 0, 1},
+ {0x33, 0, 1},
+ {0x34, 0, 0},
+ {0x35, 0x20, 0},
+ {0x36, 0x18, 0},
+ {0x37, 0x7, 0},
+ {0x38, 0x66, 0},
+ {0x39, 0x66, 0},
+ {0x3C, 0xff, 0},
+ {0x3D, 0xff, 0},
+ {0x40, 0x16, 0},
+ {0x41, 0x7, 0},
+ {0x45, 0x3, 0},
+ {0x46, 0x1, 0},
+ {0x47, 0x7, 0},
+ {0x4B, 0x66, 0},
+ {0x4C, 0x66, 0},
+ {0x4D, 0, 0},
+ {0x4E, 0x4, 0},
+ {0x4F, 0xc, 0},
+ {0x50, 0, 0},
+ {0x51, 0x70, 1},
+ {0x56, 0x7, 0},
+ {0x57, 0, 0},
+ {0x58, 0, 0},
+ {0x59, 0x88, 1},
+ {0x5A, 0, 0},
+ {0x5B, 0x1f, 0},
+ {0x5C, 0x20, 1},
+ {0x5D, 0x1, 0},
+ {0x5E, 0x30, 0},
+ {0x5F, 0x70, 0},
+ {0x60, 0, 0},
+ {0x61, 0, 0},
+ {0x62, 0x33, 1},
+ {0x63, 0xf, 1},
+ {0x64, 0xf, 1},
+ {0x65, 0, 0},
+ {0x66, 0x11, 0},
+ {0x80, 0x3c, 0},
+ {0x81, 0x1, 1},
+ {0x82, 0xa, 0},
+ {0x85, 0, 0},
+ {0x86, 0x40, 0},
+ {0x87, 0x40, 0},
+ {0x88, 0x88, 0},
+ {0x89, 0x10, 0},
+ {0x8A, 0xf0, 0},
+ {0x8B, 0x10, 0},
+ {0x8C, 0xf0, 0},
+ {0x8F, 0x10, 0},
+ {0x90, 0x55, 0},
+ {0x91, 0x3f, 1},
+ {0x92, 0x36, 1},
+ {0x93, 0, 0},
+ {0x94, 0, 0},
+ {0x95, 0, 0},
+ {0x96, 0x87, 0},
+ {0x97, 0x11, 0},
+ {0x98, 0, 0},
+ {0x99, 0x33, 0},
+ {0x9A, 0x88, 0},
+ {0xA1, 0x20, 1},
+ {0xA2, 0x3f, 0},
+ {0xA3, 0x44, 0},
+ {0xA4, 0x8c, 0},
+ {0xA5, 0x6c, 0},
+ {0xA6, 0x22, 0},
+ {0xA7, 0xbe, 0},
+ {0xA8, 0x55, 0},
+ {0xAA, 0xc, 0},
+ {0xAB, 0xaa, 0},
+ {0xAC, 0x2, 0},
+ {0xAD, 0, 0},
+ {0xAE, 0x10, 0},
+ {0xAF, 0x1, 0},
+ {0xB0, 0, 0},
+ {0xB1, 0, 0},
+ {0xB2, 0x80, 0},
+ {0xB3, 0x60, 0},
+ {0xB4, 0x44, 0},
+ {0xB5, 0x55, 0},
+ {0xB6, 0x1, 0},
+ {0xB7, 0x55, 0},
+ {0xB8, 0x1, 0},
+ {0xB9, 0x5, 0},
+ {0xBA, 0x55, 0},
+ {0xBB, 0x55, 0},
+ {0xC3, 0, 0},
+ {0xC4, 0, 0},
+ {0xC5, 0, 0},
+ {0xC6, 0, 0},
+ {0xC7, 0, 0},
+ {0xC8, 0, 0},
+ {0xC9, 0x1, 1},
+ {0xCA, 0, 0},
+ {0xCB, 0, 0},
+ {0xCD, 0, 0},
+ {0xCE, 0x5e, 0},
+ {0xCF, 0xc, 0},
+ {0xD0, 0xc, 0},
+ {0xD1, 0xc, 0},
+ {0xD2, 0, 0},
+ {0xD3, 0x2b, 0},
+ {0xD4, 0xc, 0},
+ {0xD5, 0, 0},
+ {0xD6, 0x70, 1},
+ {0xDB, 0x7, 0},
+ {0xDC, 0, 0},
+ {0xDD, 0, 0},
+ {0xDE, 0x88, 1},
+ {0xDF, 0, 0},
+ {0xE0, 0x1f, 0},
+ {0xE1, 0x20, 1},
+ {0xE2, 0x1, 0},
+ {0xE3, 0x30, 0},
+ {0xE4, 0x70, 0},
+ {0xE5, 0, 0},
+ {0xE6, 0, 0},
+ {0xE7, 0x33, 0},
+ {0xE8, 0xf, 1},
+ {0xE9, 0xf, 1},
+ {0xEA, 0, 0},
+ {0xEB, 0x11, 0},
+ {0x105, 0x3c, 0},
+ {0x106, 0x1, 1},
+ {0x107, 0xa, 0},
+ {0x10A, 0, 0},
+ {0x10B, 0x40, 0},
+ {0x10C, 0x40, 0},
+ {0x10D, 0x88, 0},
+ {0x10E, 0x10, 0},
+ {0x10F, 0xf0, 0},
+ {0x110, 0x10, 0},
+ {0x111, 0xf0, 0},
+ {0x114, 0x10, 0},
+ {0x115, 0x55, 0},
+ {0x116, 0x3f, 1},
+ {0x117, 0x36, 1},
+ {0x118, 0, 0},
+ {0x119, 0, 0},
+ {0x11A, 0, 0},
+ {0x11B, 0x87, 0},
+ {0x11C, 0x11, 0},
+ {0x11D, 0, 0},
+ {0x11E, 0x33, 0},
+ {0x11F, 0x88, 0},
+ {0x126, 0x20, 1},
+ {0x127, 0x3f, 0},
+ {0x128, 0x44, 0},
+ {0x129, 0x8c, 0},
+ {0x12A, 0x6c, 0},
+ {0x12B, 0x22, 0},
+ {0x12C, 0xbe, 0},
+ {0x12D, 0x55, 0},
+ {0x12F, 0xc, 0},
+ {0x130, 0xaa, 0},
+ {0x131, 0x2, 0},
+ {0x132, 0, 0},
+ {0x133, 0x10, 0},
+ {0x134, 0x1, 0},
+ {0x135, 0, 0},
+ {0x136, 0, 0},
+ {0x137, 0x80, 0},
+ {0x138, 0x60, 0},
+ {0x139, 0x44, 0},
+ {0x13A, 0x55, 0},
+ {0x13B, 0x1, 0},
+ {0x13C, 0x55, 0},
+ {0x13D, 0x1, 0},
+ {0x13E, 0x5, 0},
+ {0x13F, 0x55, 0},
+ {0x140, 0x55, 0},
+ {0x148, 0, 0},
+ {0x149, 0, 0},
+ {0x14A, 0, 0},
+ {0x14B, 0, 0},
+ {0x14C, 0, 0},
+ {0x14D, 0, 0},
+ {0x14E, 0x1, 1},
+ {0x14F, 0, 0},
+ {0x150, 0, 0},
+ {0x154, 0xc, 0},
+ {0x155, 0xc, 0},
+ {0x156, 0xc, 0},
+ {0x157, 0, 0},
+ {0x158, 0x2b, 0},
+ {0x159, 0x84, 0},
+ {0x15A, 0x15, 0},
+ {0x15B, 0xf, 0},
+ {0x15C, 0, 0},
+ {0x15D, 0, 0},
+ {0x15E, 0, 1},
+ {0x15F, 0, 1},
+ {0x160, 0, 1},
+ {0x161, 0, 1},
+ {0x162, 0, 1},
+ {0x163, 0, 1},
+ {0x164, 0, 0},
+ {0x165, 0, 0},
+ {0x166, 0, 0},
+ {0x167, 0, 0},
+ {0x168, 0, 0},
+ {0x169, 0, 0},
+ {0x16A, 0, 1},
+ {0x16B, 0, 1},
+ {0x16C, 0, 1},
+ {0x16D, 0, 0},
+ {0x170, 0, 0},
+ {0x171, 0x77, 0},
+ {0x172, 0x77, 0},
+ {0x173, 0x77, 0},
+ {0x174, 0x77, 0},
+ {0x175, 0, 0},
+ {0x176, 0x3, 0},
+ {0x177, 0x37, 0},
+ {0x178, 0x3, 0},
+ {0x179, 0, 0},
+ {0x17B, 0x21, 0},
+ {0x17C, 0, 0},
+ {0x17D, 0xaa, 0},
+ {0x17E, 0, 0},
+ {0x190, 0, 0},
+ {0x191, 0x77, 0},
+ {0x192, 0x77, 0},
+ {0x193, 0x77, 0},
+ {0x194, 0x77, 0},
+ {0x195, 0, 0},
+ {0x196, 0x3, 0},
+ {0x197, 0x37, 0},
+ {0x198, 0x3, 0},
+ {0x199, 0, 0},
+ {0x19B, 0x21, 0},
+ {0x19C, 0, 0},
+ {0x19D, 0xaa, 0},
+ {0x19E, 0, 0},
+ {0x1A1, 0x2, 0},
+ {0x1A2, 0xf, 0},
+ {0x1A3, 0xf, 0},
+ {0x1A4, 0, 1},
+ {0x1A5, 0, 1},
+ {0x1A6, 0, 1},
+ {0x1A7, 0x2, 0},
+ {0x1A8, 0xf, 0},
+ {0x1A9, 0xf, 0},
+ {0x1AA, 0, 1},
+ {0x1AB, 0, 1},
+ {0x1AC, 0, 1},
+ {0x1AD, 0x84, 0},
+ {0x1AE, 0x60, 0},
+ {0x1AF, 0x47, 0},
+ {0x1B0, 0x47, 0},
+ {0x1B1, 0, 0},
+ {0x1B2, 0, 0},
+ {0x1B3, 0, 0},
+ {0x1B4, 0, 0},
+ {0x1B5, 0, 0},
+ {0x1B6, 0, 0},
+ {0x1B7, 0xc, 1},
+ {0x1B8, 0, 0},
+ {0x1B9, 0, 0},
+ {0x1BA, 0, 0},
+ {0x1BB, 0, 0},
+ {0x1BC, 0, 0},
+ {0x1BD, 0, 0},
+ {0x1BE, 0, 0},
+ {0x1BF, 0, 0},
+ {0x1C0, 0, 0},
+ {0x1C1, 0x1, 1},
+ {0x1C2, 0x80, 1},
+ {0x1C3, 0, 0},
+ {0x1C4, 0, 0},
+ {0x1C5, 0, 0},
+ {0x1C6, 0, 0},
+ {0x1C7, 0, 0},
+ {0x1C8, 0, 0},
+ {0x1C9, 0, 0},
+ {0x1CA, 0, 0},
+ {0xFFFF, 0, 0}
+};
+
+radio_20xx_regs_t regs_2057_rev7[] = {
+ {0x00, 0, 1},
+ {0x01, 0x57, 1},
+ {0x02, 0x20, 1},
+ {0x03, 0x1f, 0},
+ {0x04, 0x4, 0},
+ {0x05, 0x2, 0},
+ {0x06, 0x1, 0},
+ {0x07, 0x1, 0},
+ {0x08, 0x1, 0},
+ {0x09, 0x69, 0},
+ {0x0A, 0x66, 0},
+ {0x0B, 0x6, 0},
+ {0x0C, 0x18, 0},
+ {0x0D, 0x3, 0},
+ {0x0E, 0x20, 0},
+ {0x0F, 0x20, 0},
+ {0x10, 0, 0},
+ {0x11, 0x7c, 0},
+ {0x12, 0x42, 0},
+ {0x13, 0xbd, 0},
+ {0x14, 0x7, 0},
+ {0x15, 0x87, 0},
+ {0x16, 0x8, 0},
+ {0x17, 0x17, 0},
+ {0x18, 0x7, 0},
+ {0x19, 0, 0},
+ {0x1A, 0x2, 0},
+ {0x1B, 0x13, 0},
+ {0x1C, 0x3e, 0},
+ {0x1D, 0x3e, 0},
+ {0x1E, 0x96, 0},
+ {0x1F, 0x4, 0},
+ {0x20, 0, 0},
+ {0x21, 0, 0},
+ {0x22, 0x17, 0},
+ {0x23, 0x6, 0},
+ {0x24, 0x1, 0},
+ {0x25, 0x6, 0},
+ {0x26, 0x4, 0},
+ {0x27, 0xd, 0},
+ {0x28, 0xd, 0},
+ {0x29, 0x30, 0},
+ {0x2A, 0x32, 0},
+ {0x2B, 0x8, 0},
+ {0x2C, 0x1c, 0},
+ {0x2D, 0x2, 0},
+ {0x2E, 0x4, 0},
+ {0x2F, 0x7f, 0},
+ {0x30, 0x27, 0},
+ {0x31, 0, 1},
+ {0x32, 0, 1},
+ {0x33, 0, 1},
+ {0x34, 0, 0},
+ {0x35, 0x20, 0},
+ {0x36, 0x18, 0},
+ {0x37, 0x7, 0},
+ {0x38, 0x66, 0},
+ {0x39, 0x66, 0},
+ {0x3A, 0x66, 0},
+ {0x3B, 0x66, 0},
+ {0x3C, 0xff, 0},
+ {0x3D, 0xff, 0},
+ {0x3E, 0xff, 0},
+ {0x3F, 0xff, 0},
+ {0x40, 0x16, 0},
+ {0x41, 0x7, 0},
+ {0x42, 0x19, 0},
+ {0x43, 0x7, 0},
+ {0x44, 0x6, 0},
+ {0x45, 0x3, 0},
+ {0x46, 0x1, 0},
+ {0x47, 0x7, 0},
+ {0x48, 0x33, 0},
+ {0x49, 0x5, 0},
+ {0x4A, 0x77, 0},
+ {0x4B, 0x66, 0},
+ {0x4C, 0x66, 0},
+ {0x4D, 0, 0},
+ {0x4E, 0x4, 0},
+ {0x4F, 0xc, 0},
+ {0x50, 0, 0},
+ {0x51, 0x70, 1},
+ {0x56, 0x7, 0},
+ {0x57, 0, 0},
+ {0x58, 0, 0},
+ {0x59, 0x88, 1},
+ {0x5A, 0, 0},
+ {0x5B, 0x1f, 0},
+ {0x5C, 0x20, 1},
+ {0x5D, 0x1, 0},
+ {0x5E, 0x30, 0},
+ {0x5F, 0x70, 0},
+ {0x60, 0, 0},
+ {0x61, 0, 0},
+ {0x62, 0x33, 1},
+ {0x63, 0xf, 1},
+ {0x64, 0x13, 1},
+ {0x65, 0, 0},
+ {0x66, 0xee, 1},
+ {0x69, 0, 0},
+ {0x6A, 0x7e, 0},
+ {0x6B, 0x3f, 0},
+ {0x6C, 0x7f, 0},
+ {0x6D, 0x78, 0},
+ {0x6E, 0x58, 1},
+ {0x6F, 0x88, 0},
+ {0x70, 0x8, 0},
+ {0x71, 0xf, 0},
+ {0x72, 0xbc, 0},
+ {0x73, 0x8, 0},
+ {0x74, 0x60, 0},
+ {0x75, 0x13, 1},
+ {0x76, 0x70, 0},
+ {0x77, 0, 0},
+ {0x78, 0, 0},
+ {0x79, 0, 0},
+ {0x7A, 0x33, 0},
+ {0x7B, 0x13, 1},
+ {0x7C, 0x14, 1},
+ {0x7D, 0xee, 1},
+ {0x80, 0x3c, 0},
+ {0x81, 0x1, 1},
+ {0x82, 0xa, 0},
+ {0x83, 0x9d, 0},
+ {0x84, 0xa, 0},
+ {0x85, 0, 0},
+ {0x86, 0x40, 0},
+ {0x87, 0x40, 0},
+ {0x88, 0x88, 0},
+ {0x89, 0x10, 0},
+ {0x8A, 0xf0, 0},
+ {0x8B, 0x10, 0},
+ {0x8C, 0xf0, 0},
+ {0x8D, 0, 0},
+ {0x8E, 0, 0},
+ {0x8F, 0x10, 0},
+ {0x90, 0x55, 0},
+ {0x91, 0x3f, 1},
+ {0x92, 0x36, 1},
+ {0x93, 0, 0},
+ {0x94, 0, 0},
+ {0x95, 0, 0},
+ {0x96, 0x87, 0},
+ {0x97, 0x11, 0},
+ {0x98, 0, 0},
+ {0x99, 0x33, 0},
+ {0x9A, 0x88, 0},
+ {0x9B, 0, 0},
+ {0x9C, 0x87, 0},
+ {0x9D, 0x11, 0},
+ {0x9E, 0, 0},
+ {0x9F, 0x33, 0},
+ {0xA0, 0x88, 0},
+ {0xA1, 0x20, 1},
+ {0xA2, 0x3f, 0},
+ {0xA3, 0x44, 0},
+ {0xA4, 0x8c, 0},
+ {0xA5, 0x6c, 0},
+ {0xA6, 0x22, 0},
+ {0xA7, 0xbe, 0},
+ {0xA8, 0x55, 0},
+ {0xAA, 0xc, 0},
+ {0xAB, 0xaa, 0},
+ {0xAC, 0x2, 0},
+ {0xAD, 0, 0},
+ {0xAE, 0x10, 0},
+ {0xAF, 0x1, 0},
+ {0xB0, 0, 0},
+ {0xB1, 0, 0},
+ {0xB2, 0x80, 0},
+ {0xB3, 0x60, 0},
+ {0xB4, 0x44, 0},
+ {0xB5, 0x55, 0},
+ {0xB6, 0x1, 0},
+ {0xB7, 0x55, 0},
+ {0xB8, 0x1, 0},
+ {0xB9, 0x5, 0},
+ {0xBA, 0x55, 0},
+ {0xBB, 0x55, 0},
+ {0xC1, 0, 0},
+ {0xC2, 0, 0},
+ {0xC3, 0, 0},
+ {0xC4, 0, 0},
+ {0xC5, 0, 0},
+ {0xC6, 0, 0},
+ {0xC7, 0, 0},
+ {0xC8, 0, 0},
+ {0xC9, 0, 0},
+ {0xCA, 0, 0},
+ {0xCB, 0, 0},
+ {0xCC, 0, 0},
+ {0xCD, 0, 0},
+ {0xCE, 0x5e, 0},
+ {0xCF, 0xc, 0},
+ {0xD0, 0xc, 0},
+ {0xD1, 0xc, 0},
+ {0xD2, 0, 0},
+ {0xD3, 0x2b, 0},
+ {0xD4, 0xc, 0},
+ {0xD5, 0, 0},
+ {0xD6, 0x70, 1},
+ {0xDB, 0x7, 0},
+ {0xDC, 0, 0},
+ {0xDD, 0, 0},
+ {0xDE, 0x88, 1},
+ {0xDF, 0, 0},
+ {0xE0, 0x1f, 0},
+ {0xE1, 0x20, 1},
+ {0xE2, 0x1, 0},
+ {0xE3, 0x30, 0},
+ {0xE4, 0x70, 0},
+ {0xE5, 0, 0},
+ {0xE6, 0, 0},
+ {0xE7, 0x33, 0},
+ {0xE8, 0xf, 1},
+ {0xE9, 0x13, 1},
+ {0xEA, 0, 0},
+ {0xEB, 0xee, 1},
+ {0xEE, 0, 0},
+ {0xEF, 0x7e, 0},
+ {0xF0, 0x3f, 0},
+ {0xF1, 0x7f, 0},
+ {0xF2, 0x78, 0},
+ {0xF3, 0x58, 1},
+ {0xF4, 0x88, 0},
+ {0xF5, 0x8, 0},
+ {0xF6, 0xf, 0},
+ {0xF7, 0xbc, 0},
+ {0xF8, 0x8, 0},
+ {0xF9, 0x60, 0},
+ {0xFA, 0x13, 1},
+ {0xFB, 0x70, 0},
+ {0xFC, 0, 0},
+ {0xFD, 0, 0},
+ {0xFE, 0, 0},
+ {0xFF, 0x33, 0},
+ {0x100, 0x13, 1},
+ {0x101, 0x14, 1},
+ {0x102, 0xee, 1},
+ {0x105, 0x3c, 0},
+ {0x106, 0x1, 1},
+ {0x107, 0xa, 0},
+ {0x108, 0x9d, 0},
+ {0x109, 0xa, 0},
+ {0x10A, 0, 0},
+ {0x10B, 0x40, 0},
+ {0x10C, 0x40, 0},
+ {0x10D, 0x88, 0},
+ {0x10E, 0x10, 0},
+ {0x10F, 0xf0, 0},
+ {0x110, 0x10, 0},
+ {0x111, 0xf0, 0},
+ {0x112, 0, 0},
+ {0x113, 0, 0},
+ {0x114, 0x10, 0},
+ {0x115, 0x55, 0},
+ {0x116, 0x3f, 1},
+ {0x117, 0x36, 1},
+ {0x118, 0, 0},
+ {0x119, 0, 0},
+ {0x11A, 0, 0},
+ {0x11B, 0x87, 0},
+ {0x11C, 0x11, 0},
+ {0x11D, 0, 0},
+ {0x11E, 0x33, 0},
+ {0x11F, 0x88, 0},
+ {0x120, 0, 0},
+ {0x121, 0x87, 0},
+ {0x122, 0x11, 0},
+ {0x123, 0, 0},
+ {0x124, 0x33, 0},
+ {0x125, 0x88, 0},
+ {0x126, 0x20, 1},
+ {0x127, 0x3f, 0},
+ {0x128, 0x44, 0},
+ {0x129, 0x8c, 0},
+ {0x12A, 0x6c, 0},
+ {0x12B, 0x22, 0},
+ {0x12C, 0xbe, 0},
+ {0x12D, 0x55, 0},
+ {0x12F, 0xc, 0},
+ {0x130, 0xaa, 0},
+ {0x131, 0x2, 0},
+ {0x132, 0, 0},
+ {0x133, 0x10, 0},
+ {0x134, 0x1, 0},
+ {0x135, 0, 0},
+ {0x136, 0, 0},
+ {0x137, 0x80, 0},
+ {0x138, 0x60, 0},
+ {0x139, 0x44, 0},
+ {0x13A, 0x55, 0},
+ {0x13B, 0x1, 0},
+ {0x13C, 0x55, 0},
+ {0x13D, 0x1, 0},
+ {0x13E, 0x5, 0},
+ {0x13F, 0x55, 0},
+ {0x140, 0x55, 0},
+ {0x146, 0, 0},
+ {0x147, 0, 0},
+ {0x148, 0, 0},
+ {0x149, 0, 0},
+ {0x14A, 0, 0},
+ {0x14B, 0, 0},
+ {0x14C, 0, 0},
+ {0x14D, 0, 0},
+ {0x14E, 0, 0},
+ {0x14F, 0, 0},
+ {0x150, 0, 0},
+ {0x151, 0, 0},
+ {0x154, 0xc, 0},
+ {0x155, 0xc, 0},
+ {0x156, 0xc, 0},
+ {0x157, 0, 0},
+ {0x158, 0x2b, 0},
+ {0x159, 0x84, 0},
+ {0x15A, 0x15, 0},
+ {0x15B, 0xf, 0},
+ {0x15C, 0, 0},
+ {0x15D, 0, 0},
+ {0x15E, 0, 1},
+ {0x15F, 0, 1},
+ {0x160, 0, 1},
+ {0x161, 0, 1},
+ {0x162, 0, 1},
+ {0x163, 0, 1},
+ {0x164, 0, 0},
+ {0x165, 0, 0},
+ {0x166, 0, 0},
+ {0x167, 0, 0},
+ {0x168, 0, 0},
+ {0x169, 0, 0},
+ {0x16A, 0, 1},
+ {0x16B, 0, 1},
+ {0x16C, 0, 1},
+ {0x16D, 0, 0},
+ {0x170, 0, 0},
+ {0x171, 0x77, 0},
+ {0x172, 0x77, 0},
+ {0x173, 0x77, 0},
+ {0x174, 0x77, 0},
+ {0x175, 0, 0},
+ {0x176, 0x3, 0},
+ {0x177, 0x37, 0},
+ {0x178, 0x3, 0},
+ {0x179, 0, 0},
+ {0x17A, 0x21, 0},
+ {0x17B, 0x21, 0},
+ {0x17C, 0, 0},
+ {0x17D, 0xaa, 0},
+ {0x17E, 0, 0},
+ {0x17F, 0xaa, 0},
+ {0x180, 0, 0},
+ {0x190, 0, 0},
+ {0x191, 0x77, 0},
+ {0x192, 0x77, 0},
+ {0x193, 0x77, 0},
+ {0x194, 0x77, 0},
+ {0x195, 0, 0},
+ {0x196, 0x3, 0},
+ {0x197, 0x37, 0},
+ {0x198, 0x3, 0},
+ {0x199, 0, 0},
+ {0x19A, 0x21, 0},
+ {0x19B, 0x21, 0},
+ {0x19C, 0, 0},
+ {0x19D, 0xaa, 0},
+ {0x19E, 0, 0},
+ {0x19F, 0xaa, 0},
+ {0x1A0, 0, 0},
+ {0x1A1, 0x2, 0},
+ {0x1A2, 0xf, 0},
+ {0x1A3, 0xf, 0},
+ {0x1A4, 0, 1},
+ {0x1A5, 0, 1},
+ {0x1A6, 0, 1},
+ {0x1A7, 0x2, 0},
+ {0x1A8, 0xf, 0},
+ {0x1A9, 0xf, 0},
+ {0x1AA, 0, 1},
+ {0x1AB, 0, 1},
+ {0x1AC, 0, 1},
+ {0x1AD, 0x84, 0},
+ {0x1AE, 0x60, 0},
+ {0x1AF, 0x47, 0},
+ {0x1B0, 0x47, 0},
+ {0x1B1, 0, 0},
+ {0x1B2, 0, 0},
+ {0x1B3, 0, 0},
+ {0x1B4, 0, 0},
+ {0x1B5, 0, 0},
+ {0x1B6, 0, 0},
+ {0x1B7, 0x5, 1},
+ {0x1B8, 0, 0},
+ {0x1B9, 0, 0},
+ {0x1BA, 0, 0},
+ {0x1BB, 0, 0},
+ {0x1BC, 0, 0},
+ {0x1BD, 0, 0},
+ {0x1BE, 0, 0},
+ {0x1BF, 0, 0},
+ {0x1C0, 0, 0},
+ {0x1C1, 0, 0},
+ {0x1C2, 0xa0, 1},
+ {0x1C3, 0, 0},
+ {0x1C4, 0, 0},
+ {0x1C5, 0, 0},
+ {0x1C6, 0, 0},
+ {0x1C7, 0, 0},
+ {0x1C8, 0, 0},
+ {0x1C9, 0, 0},
+ {0x1CA, 0, 0},
+ {0xFFFF, 0, 0}
+};
+
+radio_20xx_regs_t regs_2057_rev8[] = {
+ {0x00, 0x8, 1},
+ {0x01, 0x57, 1},
+ {0x02, 0x20, 1},
+ {0x03, 0x1f, 0},
+ {0x04, 0x4, 0},
+ {0x05, 0x2, 0},
+ {0x06, 0x1, 0},
+ {0x07, 0x1, 0},
+ {0x08, 0x1, 0},
+ {0x09, 0x69, 0},
+ {0x0A, 0x66, 0},
+ {0x0B, 0x6, 0},
+ {0x0C, 0x18, 0},
+ {0x0D, 0x3, 0},
+ {0x0E, 0x20, 0},
+ {0x0F, 0x20, 0},
+ {0x10, 0, 0},
+ {0x11, 0x7c, 0},
+ {0x12, 0x42, 0},
+ {0x13, 0xbd, 0},
+ {0x14, 0x7, 0},
+ {0x15, 0x87, 0},
+ {0x16, 0x8, 0},
+ {0x17, 0x17, 0},
+ {0x18, 0x7, 0},
+ {0x19, 0, 0},
+ {0x1A, 0x2, 0},
+ {0x1B, 0x13, 0},
+ {0x1C, 0x3e, 0},
+ {0x1D, 0x3e, 0},
+ {0x1E, 0x96, 0},
+ {0x1F, 0x4, 0},
+ {0x20, 0, 0},
+ {0x21, 0, 0},
+ {0x22, 0x17, 0},
+ {0x23, 0x6, 0},
+ {0x24, 0x1, 0},
+ {0x25, 0x6, 0},
+ {0x26, 0x4, 0},
+ {0x27, 0xd, 0},
+ {0x28, 0xd, 0},
+ {0x29, 0x30, 0},
+ {0x2A, 0x32, 0},
+ {0x2B, 0x8, 0},
+ {0x2C, 0x1c, 0},
+ {0x2D, 0x2, 0},
+ {0x2E, 0x4, 0},
+ {0x2F, 0x7f, 0},
+ {0x30, 0x27, 0},
+ {0x31, 0, 1},
+ {0x32, 0, 1},
+ {0x33, 0, 1},
+ {0x34, 0, 0},
+ {0x35, 0x20, 0},
+ {0x36, 0x18, 0},
+ {0x37, 0x7, 0},
+ {0x38, 0x66, 0},
+ {0x39, 0x66, 0},
+ {0x3A, 0x66, 0},
+ {0x3B, 0x66, 0},
+ {0x3C, 0xff, 0},
+ {0x3D, 0xff, 0},
+ {0x3E, 0xff, 0},
+ {0x3F, 0xff, 0},
+ {0x40, 0x16, 0},
+ {0x41, 0x7, 0},
+ {0x42, 0x19, 0},
+ {0x43, 0x7, 0},
+ {0x44, 0x6, 0},
+ {0x45, 0x3, 0},
+ {0x46, 0x1, 0},
+ {0x47, 0x7, 0},
+ {0x48, 0x33, 0},
+ {0x49, 0x5, 0},
+ {0x4A, 0x77, 0},
+ {0x4B, 0x66, 0},
+ {0x4C, 0x66, 0},
+ {0x4D, 0, 0},
+ {0x4E, 0x4, 0},
+ {0x4F, 0xc, 0},
+ {0x50, 0, 0},
+ {0x51, 0x70, 1},
+ {0x56, 0x7, 0},
+ {0x57, 0, 0},
+ {0x58, 0, 0},
+ {0x59, 0x88, 1},
+ {0x5A, 0, 0},
+ {0x5B, 0x1f, 0},
+ {0x5C, 0x20, 1},
+ {0x5D, 0x1, 0},
+ {0x5E, 0x30, 0},
+ {0x5F, 0x70, 0},
+ {0x60, 0, 0},
+ {0x61, 0, 0},
+ {0x62, 0x33, 1},
+ {0x63, 0xf, 1},
+ {0x64, 0xf, 1},
+ {0x65, 0, 0},
+ {0x66, 0x11, 0},
+ {0x69, 0, 0},
+ {0x6A, 0x7e, 0},
+ {0x6B, 0x3f, 0},
+ {0x6C, 0x7f, 0},
+ {0x6D, 0x78, 0},
+ {0x6E, 0x58, 1},
+ {0x6F, 0x88, 0},
+ {0x70, 0x8, 0},
+ {0x71, 0xf, 0},
+ {0x72, 0xbc, 0},
+ {0x73, 0x8, 0},
+ {0x74, 0x60, 0},
+ {0x75, 0x13, 1},
+ {0x76, 0x70, 0},
+ {0x77, 0, 0},
+ {0x78, 0, 0},
+ {0x79, 0, 0},
+ {0x7A, 0x33, 0},
+ {0x7B, 0x13, 1},
+ {0x7C, 0xf, 1},
+ {0x7D, 0xee, 1},
+ {0x80, 0x3c, 0},
+ {0x81, 0x1, 1},
+ {0x82, 0xa, 0},
+ {0x83, 0x9d, 0},
+ {0x84, 0xa, 0},
+ {0x85, 0, 0},
+ {0x86, 0x40, 0},
+ {0x87, 0x40, 0},
+ {0x88, 0x88, 0},
+ {0x89, 0x10, 0},
+ {0x8A, 0xf0, 0},
+ {0x8B, 0x10, 0},
+ {0x8C, 0xf0, 0},
+ {0x8D, 0, 0},
+ {0x8E, 0, 0},
+ {0x8F, 0x10, 0},
+ {0x90, 0x55, 0},
+ {0x91, 0x3f, 1},
+ {0x92, 0x36, 1},
+ {0x93, 0, 0},
+ {0x94, 0, 0},
+ {0x95, 0, 0},
+ {0x96, 0x87, 0},
+ {0x97, 0x11, 0},
+ {0x98, 0, 0},
+ {0x99, 0x33, 0},
+ {0x9A, 0x88, 0},
+ {0x9B, 0, 0},
+ {0x9C, 0x87, 0},
+ {0x9D, 0x11, 0},
+ {0x9E, 0, 0},
+ {0x9F, 0x33, 0},
+ {0xA0, 0x88, 0},
+ {0xA1, 0x20, 1},
+ {0xA2, 0x3f, 0},
+ {0xA3, 0x44, 0},
+ {0xA4, 0x8c, 0},
+ {0xA5, 0x6c, 0},
+ {0xA6, 0x22, 0},
+ {0xA7, 0xbe, 0},
+ {0xA8, 0x55, 0},
+ {0xAA, 0xc, 0},
+ {0xAB, 0xaa, 0},
+ {0xAC, 0x2, 0},
+ {0xAD, 0, 0},
+ {0xAE, 0x10, 0},
+ {0xAF, 0x1, 0},
+ {0xB0, 0, 0},
+ {0xB1, 0, 0},
+ {0xB2, 0x80, 0},
+ {0xB3, 0x60, 0},
+ {0xB4, 0x44, 0},
+ {0xB5, 0x55, 0},
+ {0xB6, 0x1, 0},
+ {0xB7, 0x55, 0},
+ {0xB8, 0x1, 0},
+ {0xB9, 0x5, 0},
+ {0xBA, 0x55, 0},
+ {0xBB, 0x55, 0},
+ {0xC1, 0, 0},
+ {0xC2, 0, 0},
+ {0xC3, 0, 0},
+ {0xC4, 0, 0},
+ {0xC5, 0, 0},
+ {0xC6, 0, 0},
+ {0xC7, 0, 0},
+ {0xC8, 0, 0},
+ {0xC9, 0x1, 1},
+ {0xCA, 0, 0},
+ {0xCB, 0, 0},
+ {0xCC, 0, 0},
+ {0xCD, 0, 0},
+ {0xCE, 0x5e, 0},
+ {0xCF, 0xc, 0},
+ {0xD0, 0xc, 0},
+ {0xD1, 0xc, 0},
+ {0xD2, 0, 0},
+ {0xD3, 0x2b, 0},
+ {0xD4, 0xc, 0},
+ {0xD5, 0, 0},
+ {0xD6, 0x70, 1},
+ {0xDB, 0x7, 0},
+ {0xDC, 0, 0},
+ {0xDD, 0, 0},
+ {0xDE, 0x88, 1},
+ {0xDF, 0, 0},
+ {0xE0, 0x1f, 0},
+ {0xE1, 0x20, 1},
+ {0xE2, 0x1, 0},
+ {0xE3, 0x30, 0},
+ {0xE4, 0x70, 0},
+ {0xE5, 0, 0},
+ {0xE6, 0, 0},
+ {0xE7, 0x33, 0},
+ {0xE8, 0xf, 1},
+ {0xE9, 0xf, 1},
+ {0xEA, 0, 0},
+ {0xEB, 0x11, 0},
+ {0xEE, 0, 0},
+ {0xEF, 0x7e, 0},
+ {0xF0, 0x3f, 0},
+ {0xF1, 0x7f, 0},
+ {0xF2, 0x78, 0},
+ {0xF3, 0x58, 1},
+ {0xF4, 0x88, 0},
+ {0xF5, 0x8, 0},
+ {0xF6, 0xf, 0},
+ {0xF7, 0xbc, 0},
+ {0xF8, 0x8, 0},
+ {0xF9, 0x60, 0},
+ {0xFA, 0x13, 1},
+ {0xFB, 0x70, 0},
+ {0xFC, 0, 0},
+ {0xFD, 0, 0},
+ {0xFE, 0, 0},
+ {0xFF, 0x33, 0},
+ {0x100, 0x13, 1},
+ {0x101, 0xf, 1},
+ {0x102, 0xee, 1},
+ {0x105, 0x3c, 0},
+ {0x106, 0x1, 1},
+ {0x107, 0xa, 0},
+ {0x108, 0x9d, 0},
+ {0x109, 0xa, 0},
+ {0x10A, 0, 0},
+ {0x10B, 0x40, 0},
+ {0x10C, 0x40, 0},
+ {0x10D, 0x88, 0},
+ {0x10E, 0x10, 0},
+ {0x10F, 0xf0, 0},
+ {0x110, 0x10, 0},
+ {0x111, 0xf0, 0},
+ {0x112, 0, 0},
+ {0x113, 0, 0},
+ {0x114, 0x10, 0},
+ {0x115, 0x55, 0},
+ {0x116, 0x3f, 1},
+ {0x117, 0x36, 1},
+ {0x118, 0, 0},
+ {0x119, 0, 0},
+ {0x11A, 0, 0},
+ {0x11B, 0x87, 0},
+ {0x11C, 0x11, 0},
+ {0x11D, 0, 0},
+ {0x11E, 0x33, 0},
+ {0x11F, 0x88, 0},
+ {0x120, 0, 0},
+ {0x121, 0x87, 0},
+ {0x122, 0x11, 0},
+ {0x123, 0, 0},
+ {0x124, 0x33, 0},
+ {0x125, 0x88, 0},
+ {0x126, 0x20, 1},
+ {0x127, 0x3f, 0},
+ {0x128, 0x44, 0},
+ {0x129, 0x8c, 0},
+ {0x12A, 0x6c, 0},
+ {0x12B, 0x22, 0},
+ {0x12C, 0xbe, 0},
+ {0x12D, 0x55, 0},
+ {0x12F, 0xc, 0},
+ {0x130, 0xaa, 0},
+ {0x131, 0x2, 0},
+ {0x132, 0, 0},
+ {0x133, 0x10, 0},
+ {0x134, 0x1, 0},
+ {0x135, 0, 0},
+ {0x136, 0, 0},
+ {0x137, 0x80, 0},
+ {0x138, 0x60, 0},
+ {0x139, 0x44, 0},
+ {0x13A, 0x55, 0},
+ {0x13B, 0x1, 0},
+ {0x13C, 0x55, 0},
+ {0x13D, 0x1, 0},
+ {0x13E, 0x5, 0},
+ {0x13F, 0x55, 0},
+ {0x140, 0x55, 0},
+ {0x146, 0, 0},
+ {0x147, 0, 0},
+ {0x148, 0, 0},
+ {0x149, 0, 0},
+ {0x14A, 0, 0},
+ {0x14B, 0, 0},
+ {0x14C, 0, 0},
+ {0x14D, 0, 0},
+ {0x14E, 0x1, 1},
+ {0x14F, 0, 0},
+ {0x150, 0, 0},
+ {0x151, 0, 0},
+ {0x154, 0xc, 0},
+ {0x155, 0xc, 0},
+ {0x156, 0xc, 0},
+ {0x157, 0, 0},
+ {0x158, 0x2b, 0},
+ {0x159, 0x84, 0},
+ {0x15A, 0x15, 0},
+ {0x15B, 0xf, 0},
+ {0x15C, 0, 0},
+ {0x15D, 0, 0},
+ {0x15E, 0, 1},
+ {0x15F, 0, 1},
+ {0x160, 0, 1},
+ {0x161, 0, 1},
+ {0x162, 0, 1},
+ {0x163, 0, 1},
+ {0x164, 0, 0},
+ {0x165, 0, 0},
+ {0x166, 0, 0},
+ {0x167, 0, 0},
+ {0x168, 0, 0},
+ {0x169, 0, 0},
+ {0x16A, 0, 1},
+ {0x16B, 0, 1},
+ {0x16C, 0, 1},
+ {0x16D, 0, 0},
+ {0x170, 0, 0},
+ {0x171, 0x77, 0},
+ {0x172, 0x77, 0},
+ {0x173, 0x77, 0},
+ {0x174, 0x77, 0},
+ {0x175, 0, 0},
+ {0x176, 0x3, 0},
+ {0x177, 0x37, 0},
+ {0x178, 0x3, 0},
+ {0x179, 0, 0},
+ {0x17A, 0x21, 0},
+ {0x17B, 0x21, 0},
+ {0x17C, 0, 0},
+ {0x17D, 0xaa, 0},
+ {0x17E, 0, 0},
+ {0x17F, 0xaa, 0},
+ {0x180, 0, 0},
+ {0x190, 0, 0},
+ {0x191, 0x77, 0},
+ {0x192, 0x77, 0},
+ {0x193, 0x77, 0},
+ {0x194, 0x77, 0},
+ {0x195, 0, 0},
+ {0x196, 0x3, 0},
+ {0x197, 0x37, 0},
+ {0x198, 0x3, 0},
+ {0x199, 0, 0},
+ {0x19A, 0x21, 0},
+ {0x19B, 0x21, 0},
+ {0x19C, 0, 0},
+ {0x19D, 0xaa, 0},
+ {0x19E, 0, 0},
+ {0x19F, 0xaa, 0},
+ {0x1A0, 0, 0},
+ {0x1A1, 0x2, 0},
+ {0x1A2, 0xf, 0},
+ {0x1A3, 0xf, 0},
+ {0x1A4, 0, 1},
+ {0x1A5, 0, 1},
+ {0x1A6, 0, 1},
+ {0x1A7, 0x2, 0},
+ {0x1A8, 0xf, 0},
+ {0x1A9, 0xf, 0},
+ {0x1AA, 0, 1},
+ {0x1AB, 0, 1},
+ {0x1AC, 0, 1},
+ {0x1AD, 0x84, 0},
+ {0x1AE, 0x60, 0},
+ {0x1AF, 0x47, 0},
+ {0x1B0, 0x47, 0},
+ {0x1B1, 0, 0},
+ {0x1B2, 0, 0},
+ {0x1B3, 0, 0},
+ {0x1B4, 0, 0},
+ {0x1B5, 0, 0},
+ {0x1B6, 0, 0},
+ {0x1B7, 0x5, 1},
+ {0x1B8, 0, 0},
+ {0x1B9, 0, 0},
+ {0x1BA, 0, 0},
+ {0x1BB, 0, 0},
+ {0x1BC, 0, 0},
+ {0x1BD, 0, 0},
+ {0x1BE, 0, 0},
+ {0x1BF, 0, 0},
+ {0x1C0, 0, 0},
+ {0x1C1, 0, 0},
+ {0x1C2, 0xa0, 1},
+ {0x1C3, 0, 0},
+ {0x1C4, 0, 0},
+ {0x1C5, 0, 0},
+ {0x1C6, 0, 0},
+ {0x1C7, 0, 0},
+ {0x1C8, 0, 0},
+ {0x1C9, 0, 0},
+ {0x1CA, 0, 0},
+ {0xFFFF, 0, 0}
+};
+
+static s16 nphy_def_lnagains[] = { -2, 10, 19, 25 };
+
+static s32 nphy_lnagain_est0[] = { -315, 40370 };
+static s32 nphy_lnagain_est1[] = { -224, 23242 };
+
+static const u16 tbl_iqcal_gainparams_nphy[2][NPHY_IQCAL_NUMGAINS][8] = {
+ {
+ {0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69},
+ {0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69},
+ {0x710, 7, 1, 0, 0x68, 0x68, 0x68, 0x68},
+ {0x720, 7, 2, 0, 0x67, 0x67, 0x67, 0x67},
+ {0x730, 7, 3, 0, 0x66, 0x66, 0x66, 0x66},
+ {0x740, 7, 4, 0, 0x65, 0x65, 0x65, 0x65},
+ {0x741, 7, 4, 1, 0x65, 0x65, 0x65, 0x65},
+ {0x742, 7, 4, 2, 0x65, 0x65, 0x65, 0x65},
+ {0x743, 7, 4, 3, 0x65, 0x65, 0x65, 0x65}
+ },
+ {
+ {0x000, 7, 0, 0, 0x79, 0x79, 0x79, 0x79},
+ {0x700, 7, 0, 0, 0x79, 0x79, 0x79, 0x79},
+ {0x710, 7, 1, 0, 0x79, 0x79, 0x79, 0x79},
+ {0x720, 7, 2, 0, 0x78, 0x78, 0x78, 0x78},
+ {0x730, 7, 3, 0, 0x78, 0x78, 0x78, 0x78},
+ {0x740, 7, 4, 0, 0x78, 0x78, 0x78, 0x78},
+ {0x741, 7, 4, 1, 0x78, 0x78, 0x78, 0x78},
+ {0x742, 7, 4, 2, 0x78, 0x78, 0x78, 0x78},
+ {0x743, 7, 4, 3, 0x78, 0x78, 0x78, 0x78}
+ }
+};
+
+static const u32 nphy_tpc_txgain[] = {
+ 0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
+ 0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
+ 0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
+ 0x03c82842, 0x03c42b44, 0x03c42b42, 0x03c42a44,
+ 0x03c42a42, 0x03c42944, 0x03c42942, 0x03c42844,
+ 0x03c42842, 0x03c42744, 0x03c42742, 0x03c42644,
+ 0x03c42642, 0x03c42544, 0x03c42542, 0x03c42444,
+ 0x03c42442, 0x03c02b44, 0x03c02b42, 0x03c02a44,
+ 0x03c02a42, 0x03c02944, 0x03c02942, 0x03c02844,
+ 0x03c02842, 0x03c02744, 0x03c02742, 0x03b02b44,
+ 0x03b02b42, 0x03b02a44, 0x03b02a42, 0x03b02944,
+ 0x03b02942, 0x03b02844, 0x03b02842, 0x03b02744,
+ 0x03b02742, 0x03b02644, 0x03b02642, 0x03b02544,
+ 0x03b02542, 0x03a02b44, 0x03a02b42, 0x03a02a44,
+ 0x03a02a42, 0x03a02944, 0x03a02942, 0x03a02844,
+ 0x03a02842, 0x03a02744, 0x03a02742, 0x03902b44,
+ 0x03902b42, 0x03902a44, 0x03902a42, 0x03902944,
+ 0x03902942, 0x03902844, 0x03902842, 0x03902744,
+ 0x03902742, 0x03902644, 0x03902642, 0x03902544,
+ 0x03902542, 0x03802b44, 0x03802b42, 0x03802a44,
+ 0x03802a42, 0x03802944, 0x03802942, 0x03802844,
+ 0x03802842, 0x03802744, 0x03802742, 0x03802644,
+ 0x03802642, 0x03802544, 0x03802542, 0x03802444,
+ 0x03802442, 0x03802344, 0x03802342, 0x03802244,
+ 0x03802242, 0x03802144, 0x03802142, 0x03802044,
+ 0x03802042, 0x03801f44, 0x03801f42, 0x03801e44,
+ 0x03801e42, 0x03801d44, 0x03801d42, 0x03801c44,
+ 0x03801c42, 0x03801b44, 0x03801b42, 0x03801a44,
+ 0x03801a42, 0x03801944, 0x03801942, 0x03801844,
+ 0x03801842, 0x03801744, 0x03801742, 0x03801644,
+ 0x03801642, 0x03801544, 0x03801542, 0x03801444,
+ 0x03801442, 0x03801344, 0x03801342, 0x00002b00
+};
+
+static const u16 nphy_tpc_loscale[] = {
+ 256, 256, 271, 271, 287, 256, 256, 271,
+ 271, 287, 287, 304, 304, 256, 256, 271,
+ 271, 287, 287, 304, 304, 322, 322, 341,
+ 341, 362, 362, 383, 383, 256, 256, 271,
+ 271, 287, 287, 304, 304, 322, 322, 256,
+ 256, 271, 271, 287, 287, 304, 304, 322,
+ 322, 341, 341, 362, 362, 256, 256, 271,
+ 271, 287, 287, 304, 304, 322, 322, 256,
+ 256, 271, 271, 287, 287, 304, 304, 322,
+ 322, 341, 341, 362, 362, 256, 256, 271,
+ 271, 287, 287, 304, 304, 322, 322, 341,
+ 341, 362, 362, 383, 383, 406, 406, 430,
+ 430, 455, 455, 482, 482, 511, 511, 541,
+ 541, 573, 573, 607, 607, 643, 643, 681,
+ 681, 722, 722, 764, 764, 810, 810, 858,
+ 858, 908, 908, 962, 962, 1019, 1019, 256
+};
+
+static u32 nphy_tpc_txgain_ipa[] = {
+ 0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
+ 0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
+ 0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
+ 0x5ef70028, 0x5ef70027, 0x5ef70026, 0x5ef70025,
+ 0x5df7002d, 0x5df7002b, 0x5df7002a, 0x5df70029,
+ 0x5df70028, 0x5df70027, 0x5df70026, 0x5df70025,
+ 0x5cf7002d, 0x5cf7002b, 0x5cf7002a, 0x5cf70029,
+ 0x5cf70028, 0x5cf70027, 0x5cf70026, 0x5cf70025,
+ 0x5bf7002d, 0x5bf7002b, 0x5bf7002a, 0x5bf70029,
+ 0x5bf70028, 0x5bf70027, 0x5bf70026, 0x5bf70025,
+ 0x5af7002d, 0x5af7002b, 0x5af7002a, 0x5af70029,
+ 0x5af70028, 0x5af70027, 0x5af70026, 0x5af70025,
+ 0x59f7002d, 0x59f7002b, 0x59f7002a, 0x59f70029,
+ 0x59f70028, 0x59f70027, 0x59f70026, 0x59f70025,
+ 0x58f7002d, 0x58f7002b, 0x58f7002a, 0x58f70029,
+ 0x58f70028, 0x58f70027, 0x58f70026, 0x58f70025,
+ 0x57f7002d, 0x57f7002b, 0x57f7002a, 0x57f70029,
+ 0x57f70028, 0x57f70027, 0x57f70026, 0x57f70025,
+ 0x56f7002d, 0x56f7002b, 0x56f7002a, 0x56f70029,
+ 0x56f70028, 0x56f70027, 0x56f70026, 0x56f70025,
+ 0x55f7002d, 0x55f7002b, 0x55f7002a, 0x55f70029,
+ 0x55f70028, 0x55f70027, 0x55f70026, 0x55f70025,
+ 0x54f7002d, 0x54f7002b, 0x54f7002a, 0x54f70029,
+ 0x54f70028, 0x54f70027, 0x54f70026, 0x54f70025,
+ 0x53f7002d, 0x53f7002b, 0x53f7002a, 0x53f70029,
+ 0x53f70028, 0x53f70027, 0x53f70026, 0x53f70025,
+ 0x52f7002d, 0x52f7002b, 0x52f7002a, 0x52f70029,
+ 0x52f70028, 0x52f70027, 0x52f70026, 0x52f70025,
+ 0x51f7002d, 0x51f7002b, 0x51f7002a, 0x51f70029,
+ 0x51f70028, 0x51f70027, 0x51f70026, 0x51f70025,
+ 0x50f7002d, 0x50f7002b, 0x50f7002a, 0x50f70029,
+ 0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025
+};
+
+static u32 nphy_tpc_txgain_ipa_rev5[] = {
+ 0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
+ 0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
+ 0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
+ 0x1ef70028, 0x1ef70027, 0x1ef70026, 0x1ef70025,
+ 0x1df7002d, 0x1df7002b, 0x1df7002a, 0x1df70029,
+ 0x1df70028, 0x1df70027, 0x1df70026, 0x1df70025,
+ 0x1cf7002d, 0x1cf7002b, 0x1cf7002a, 0x1cf70029,
+ 0x1cf70028, 0x1cf70027, 0x1cf70026, 0x1cf70025,
+ 0x1bf7002d, 0x1bf7002b, 0x1bf7002a, 0x1bf70029,
+ 0x1bf70028, 0x1bf70027, 0x1bf70026, 0x1bf70025,
+ 0x1af7002d, 0x1af7002b, 0x1af7002a, 0x1af70029,
+ 0x1af70028, 0x1af70027, 0x1af70026, 0x1af70025,
+ 0x19f7002d, 0x19f7002b, 0x19f7002a, 0x19f70029,
+ 0x19f70028, 0x19f70027, 0x19f70026, 0x19f70025,
+ 0x18f7002d, 0x18f7002b, 0x18f7002a, 0x18f70029,
+ 0x18f70028, 0x18f70027, 0x18f70026, 0x18f70025,
+ 0x17f7002d, 0x17f7002b, 0x17f7002a, 0x17f70029,
+ 0x17f70028, 0x17f70027, 0x17f70026, 0x17f70025,
+ 0x16f7002d, 0x16f7002b, 0x16f7002a, 0x16f70029,
+ 0x16f70028, 0x16f70027, 0x16f70026, 0x16f70025,
+ 0x15f7002d, 0x15f7002b, 0x15f7002a, 0x15f70029,
+ 0x15f70028, 0x15f70027, 0x15f70026, 0x15f70025,
+ 0x14f7002d, 0x14f7002b, 0x14f7002a, 0x14f70029,
+ 0x14f70028, 0x14f70027, 0x14f70026, 0x14f70025,
+ 0x13f7002d, 0x13f7002b, 0x13f7002a, 0x13f70029,
+ 0x13f70028, 0x13f70027, 0x13f70026, 0x13f70025,
+ 0x12f7002d, 0x12f7002b, 0x12f7002a, 0x12f70029,
+ 0x12f70028, 0x12f70027, 0x12f70026, 0x12f70025,
+ 0x11f7002d, 0x11f7002b, 0x11f7002a, 0x11f70029,
+ 0x11f70028, 0x11f70027, 0x11f70026, 0x11f70025,
+ 0x10f7002d, 0x10f7002b, 0x10f7002a, 0x10f70029,
+ 0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025
+};
+
+static u32 nphy_tpc_txgain_ipa_rev6[] = {
+ 0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
+ 0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
+ 0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
+ 0x0ef70028, 0x0ef70027, 0x0ef70026, 0x0ef70025,
+ 0x0df7002d, 0x0df7002b, 0x0df7002a, 0x0df70029,
+ 0x0df70028, 0x0df70027, 0x0df70026, 0x0df70025,
+ 0x0cf7002d, 0x0cf7002b, 0x0cf7002a, 0x0cf70029,
+ 0x0cf70028, 0x0cf70027, 0x0cf70026, 0x0cf70025,
+ 0x0bf7002d, 0x0bf7002b, 0x0bf7002a, 0x0bf70029,
+ 0x0bf70028, 0x0bf70027, 0x0bf70026, 0x0bf70025,
+ 0x0af7002d, 0x0af7002b, 0x0af7002a, 0x0af70029,
+ 0x0af70028, 0x0af70027, 0x0af70026, 0x0af70025,
+ 0x09f7002d, 0x09f7002b, 0x09f7002a, 0x09f70029,
+ 0x09f70028, 0x09f70027, 0x09f70026, 0x09f70025,
+ 0x08f7002d, 0x08f7002b, 0x08f7002a, 0x08f70029,
+ 0x08f70028, 0x08f70027, 0x08f70026, 0x08f70025,
+ 0x07f7002d, 0x07f7002b, 0x07f7002a, 0x07f70029,
+ 0x07f70028, 0x07f70027, 0x07f70026, 0x07f70025,
+ 0x06f7002d, 0x06f7002b, 0x06f7002a, 0x06f70029,
+ 0x06f70028, 0x06f70027, 0x06f70026, 0x06f70025,
+ 0x05f7002d, 0x05f7002b, 0x05f7002a, 0x05f70029,
+ 0x05f70028, 0x05f70027, 0x05f70026, 0x05f70025,
+ 0x04f7002d, 0x04f7002b, 0x04f7002a, 0x04f70029,
+ 0x04f70028, 0x04f70027, 0x04f70026, 0x04f70025,
+ 0x03f7002d, 0x03f7002b, 0x03f7002a, 0x03f70029,
+ 0x03f70028, 0x03f70027, 0x03f70026, 0x03f70025,
+ 0x02f7002d, 0x02f7002b, 0x02f7002a, 0x02f70029,
+ 0x02f70028, 0x02f70027, 0x02f70026, 0x02f70025,
+ 0x01f7002d, 0x01f7002b, 0x01f7002a, 0x01f70029,
+ 0x01f70028, 0x01f70027, 0x01f70026, 0x01f70025,
+ 0x00f7002d, 0x00f7002b, 0x00f7002a, 0x00f70029,
+ 0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025
+};
+
+static u32 nphy_tpc_txgain_ipa_2g_2057rev3[] = {
+ 0x70ff0040, 0x70f7003e, 0x70ef003b, 0x70e70039,
+ 0x70df0037, 0x70d70036, 0x70cf0033, 0x70c70032,
+ 0x70bf0031, 0x70b7002f, 0x70af002e, 0x70a7002d,
+ 0x709f002d, 0x7097002c, 0x708f002c, 0x7087002c,
+ 0x707f002b, 0x7077002c, 0x706f002c, 0x7067002d,
+ 0x705f002e, 0x705f002b, 0x705f0029, 0x7057002a,
+ 0x70570028, 0x704f002a, 0x7047002c, 0x7047002a,
+ 0x70470028, 0x70470026, 0x70470024, 0x70470022,
+ 0x7047001f, 0x70370027, 0x70370024, 0x70370022,
+ 0x70370020, 0x7037001f, 0x7037001d, 0x7037001b,
+ 0x7037001a, 0x70370018, 0x70370017, 0x7027001e,
+ 0x7027001d, 0x7027001a, 0x701f0024, 0x701f0022,
+ 0x701f0020, 0x701f001f, 0x701f001d, 0x701f001b,
+ 0x701f001a, 0x701f0018, 0x701f0017, 0x701f0015,
+ 0x701f0014, 0x701f0013, 0x701f0012, 0x701f0011,
+ 0x70170019, 0x70170018, 0x70170016, 0x70170015,
+ 0x70170014, 0x70170013, 0x70170012, 0x70170010,
+ 0x70170010, 0x7017000f, 0x700f001d, 0x700f001b,
+ 0x700f001a, 0x700f0018, 0x700f0017, 0x700f0015,
+ 0x700f0015, 0x700f0013, 0x700f0013, 0x700f0011,
+ 0x700f0010, 0x700f0010, 0x700f000f, 0x700f000e,
+ 0x700f000d, 0x700f000c, 0x700f000b, 0x700f000b,
+ 0x700f000b, 0x700f000a, 0x700f0009, 0x700f0009,
+ 0x700f0009, 0x700f0008, 0x700f0007, 0x700f0007,
+ 0x700f0006, 0x700f0006, 0x700f0006, 0x700f0006,
+ 0x700f0005, 0x700f0005, 0x700f0005, 0x700f0004,
+ 0x700f0004, 0x700f0004, 0x700f0004, 0x700f0004,
+ 0x700f0004, 0x700f0003, 0x700f0003, 0x700f0003,
+ 0x700f0003, 0x700f0002, 0x700f0002, 0x700f0002,
+ 0x700f0002, 0x700f0002, 0x700f0002, 0x700f0001,
+ 0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001,
+ 0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001
+};
+
+static u32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = {
+ 0xf0ff0040, 0xf0f7003e, 0xf0ef003b, 0xf0e70039,
+ 0xf0df0037, 0xf0d70036, 0xf0cf0033, 0xf0c70032,
+ 0xf0bf0031, 0xf0b7002f, 0xf0af002e, 0xf0a7002d,
+ 0xf09f002d, 0xf097002c, 0xf08f002c, 0xf087002c,
+ 0xf07f002b, 0xf077002c, 0xf06f002c, 0xf067002d,
+ 0xf05f002e, 0xf05f002b, 0xf05f0029, 0xf057002a,
+ 0xf0570028, 0xf04f002a, 0xf047002c, 0xf047002a,
+ 0xf0470028, 0xf0470026, 0xf0470024, 0xf0470022,
+ 0xf047001f, 0xf0370027, 0xf0370024, 0xf0370022,
+ 0xf0370020, 0xf037001f, 0xf037001d, 0xf037001b,
+ 0xf037001a, 0xf0370018, 0xf0370017, 0xf027001e,
+ 0xf027001d, 0xf027001a, 0xf01f0024, 0xf01f0022,
+ 0xf01f0020, 0xf01f001f, 0xf01f001d, 0xf01f001b,
+ 0xf01f001a, 0xf01f0018, 0xf01f0017, 0xf01f0015,
+ 0xf01f0014, 0xf01f0013, 0xf01f0012, 0xf01f0011,
+ 0xf0170019, 0xf0170018, 0xf0170016, 0xf0170015,
+ 0xf0170014, 0xf0170013, 0xf0170012, 0xf0170010,
+ 0xf0170010, 0xf017000f, 0xf00f001d, 0xf00f001b,
+ 0xf00f001a, 0xf00f0018, 0xf00f0017, 0xf00f0015,
+ 0xf00f0015, 0xf00f0013, 0xf00f0013, 0xf00f0011,
+ 0xf00f0010, 0xf00f0010, 0xf00f000f, 0xf00f000e,
+ 0xf00f000d, 0xf00f000c, 0xf00f000b, 0xf00f000b,
+ 0xf00f000b, 0xf00f000a, 0xf00f0009, 0xf00f0009,
+ 0xf00f0009, 0xf00f0008, 0xf00f0007, 0xf00f0007,
+ 0xf00f0006, 0xf00f0006, 0xf00f0006, 0xf00f0006,
+ 0xf00f0005, 0xf00f0005, 0xf00f0005, 0xf00f0004,
+ 0xf00f0004, 0xf00f0004, 0xf00f0004, 0xf00f0004,
+ 0xf00f0004, 0xf00f0003, 0xf00f0003, 0xf00f0003,
+ 0xf00f0003, 0xf00f0002, 0xf00f0002, 0xf00f0002,
+ 0xf00f0002, 0xf00f0002, 0xf00f0002, 0xf00f0001,
+ 0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001,
+ 0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001
+};
+
+static u32 nphy_tpc_txgain_ipa_2g_2057rev5[] = {
+ 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
+ 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
+ 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
+ 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d,
+ 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c,
+ 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d,
+ 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a,
+ 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029,
+ 0x30270027, 0x30270025, 0x30270023, 0x301f002c,
+ 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024,
+ 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b,
+ 0x30170028, 0x30170026, 0x30170024, 0x30170022,
+ 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b,
+ 0x3017001a, 0x30170018, 0x30170017, 0x30170015,
+ 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024,
+ 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d,
+ 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017,
+ 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215,
+ 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
+};
+
+static u32 nphy_tpc_txgain_ipa_2g_2057rev7[] = {
+ 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
+ 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
+ 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
+ 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d,
+ 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c,
+ 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d,
+ 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a,
+ 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029,
+ 0x30270027, 0x30270025, 0x30270023, 0x301f002c,
+ 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024,
+ 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b,
+ 0x30170028, 0x30170026, 0x30170024, 0x30170022,
+ 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b,
+ 0x3017001a, 0x30170018, 0x30170017, 0x30170015,
+ 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024,
+ 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d,
+ 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017,
+ 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215,
+ 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
+ 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
+};
+
+static u32 nphy_tpc_txgain_ipa_5g[] = {
+ 0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
+ 0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
+ 0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
+ 0x7ff70026, 0x7ff70024, 0x7ff70023, 0x7ff70022,
+ 0x7ef70028, 0x7ef70027, 0x7ef70026, 0x7ef70025,
+ 0x7ef70024, 0x7ef70023, 0x7df70028, 0x7df70027,
+ 0x7df70026, 0x7df70025, 0x7df70024, 0x7df70023,
+ 0x7df70022, 0x7cf70029, 0x7cf70028, 0x7cf70027,
+ 0x7cf70026, 0x7cf70025, 0x7cf70023, 0x7cf70022,
+ 0x7bf70029, 0x7bf70028, 0x7bf70026, 0x7bf70025,
+ 0x7bf70024, 0x7bf70023, 0x7bf70022, 0x7bf70021,
+ 0x7af70029, 0x7af70028, 0x7af70027, 0x7af70026,
+ 0x7af70025, 0x7af70024, 0x7af70023, 0x7af70022,
+ 0x79f70029, 0x79f70028, 0x79f70027, 0x79f70026,
+ 0x79f70025, 0x79f70024, 0x79f70023, 0x79f70022,
+ 0x78f70029, 0x78f70028, 0x78f70027, 0x78f70026,
+ 0x78f70025, 0x78f70024, 0x78f70023, 0x78f70022,
+ 0x77f70029, 0x77f70028, 0x77f70027, 0x77f70026,
+ 0x77f70025, 0x77f70024, 0x77f70023, 0x77f70022,
+ 0x76f70029, 0x76f70028, 0x76f70027, 0x76f70026,
+ 0x76f70024, 0x76f70023, 0x76f70022, 0x76f70021,
+ 0x75f70029, 0x75f70028, 0x75f70027, 0x75f70026,
+ 0x75f70025, 0x75f70024, 0x75f70023, 0x74f70029,
+ 0x74f70028, 0x74f70026, 0x74f70025, 0x74f70024,
+ 0x74f70023, 0x74f70022, 0x73f70029, 0x73f70027,
+ 0x73f70026, 0x73f70025, 0x73f70024, 0x73f70023,
+ 0x73f70022, 0x72f70028, 0x72f70027, 0x72f70026,
+ 0x72f70025, 0x72f70024, 0x72f70023, 0x72f70022,
+ 0x71f70028, 0x71f70027, 0x71f70026, 0x71f70025,
+ 0x71f70024, 0x71f70023, 0x70f70028, 0x70f70027,
+ 0x70f70026, 0x70f70024, 0x70f70023, 0x70f70022,
+ 0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f
+};
+
+static u32 nphy_tpc_txgain_ipa_5g_2057[] = {
+ 0x7f7f0044, 0x7f7f0040, 0x7f7f003c, 0x7f7f0039,
+ 0x7f7f0036, 0x7e7f003c, 0x7e7f0038, 0x7e7f0035,
+ 0x7d7f003c, 0x7d7f0039, 0x7d7f0036, 0x7d7f0033,
+ 0x7c7f003b, 0x7c7f0037, 0x7c7f0034, 0x7b7f003a,
+ 0x7b7f0036, 0x7b7f0033, 0x7a7f003c, 0x7a7f0039,
+ 0x7a7f0036, 0x7a7f0033, 0x797f003b, 0x797f0038,
+ 0x797f0035, 0x797f0032, 0x787f003b, 0x787f0038,
+ 0x787f0035, 0x787f0032, 0x777f003a, 0x777f0037,
+ 0x777f0034, 0x777f0031, 0x767f003a, 0x767f0036,
+ 0x767f0033, 0x767f0031, 0x757f003a, 0x757f0037,
+ 0x757f0034, 0x747f003c, 0x747f0039, 0x747f0036,
+ 0x747f0033, 0x737f003b, 0x737f0038, 0x737f0035,
+ 0x737f0032, 0x727f0039, 0x727f0036, 0x727f0033,
+ 0x727f0030, 0x717f003a, 0x717f0037, 0x717f0034,
+ 0x707f003b, 0x707f0038, 0x707f0035, 0x707f0032,
+ 0x707f002f, 0x707f002d, 0x707f002a, 0x707f0028,
+ 0x707f0025, 0x707f0023, 0x707f0021, 0x707f0020,
+ 0x707f001e, 0x707f001c, 0x707f001b, 0x707f0019,
+ 0x707f0018, 0x707f0016, 0x707f0015, 0x707f0014,
+ 0x707f0013, 0x707f0012, 0x707f0011, 0x707f0010,
+ 0x707f000f, 0x707f000e, 0x707f000d, 0x707f000d,
+ 0x707f000c, 0x707f000b, 0x707f000b, 0x707f000a,
+ 0x707f0009, 0x707f0009, 0x707f0008, 0x707f0008,
+ 0x707f0007, 0x707f0007, 0x707f0007, 0x707f0006,
+ 0x707f0006, 0x707f0006, 0x707f0005, 0x707f0005,
+ 0x707f0005, 0x707f0004, 0x707f0004, 0x707f0004,
+ 0x707f0004, 0x707f0004, 0x707f0003, 0x707f0003,
+ 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003,
+ 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002,
+ 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002,
+ 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001,
+ 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001
+};
+
+static u32 nphy_tpc_txgain_ipa_5g_2057rev7[] = {
+ 0x6f7f0031, 0x6f7f002e, 0x6f7f002c, 0x6f7f002a,
+ 0x6f7f0027, 0x6e7f002e, 0x6e7f002c, 0x6e7f002a,
+ 0x6d7f0030, 0x6d7f002d, 0x6d7f002a, 0x6d7f0028,
+ 0x6c7f0030, 0x6c7f002d, 0x6c7f002b, 0x6b7f002e,
+ 0x6b7f002c, 0x6b7f002a, 0x6b7f0027, 0x6a7f002e,
+ 0x6a7f002c, 0x6a7f002a, 0x697f0030, 0x697f002e,
+ 0x697f002b, 0x697f0029, 0x687f002f, 0x687f002d,
+ 0x687f002a, 0x687f0027, 0x677f002f, 0x677f002d,
+ 0x677f002a, 0x667f0031, 0x667f002e, 0x667f002c,
+ 0x667f002a, 0x657f0030, 0x657f002e, 0x657f002b,
+ 0x657f0029, 0x647f0030, 0x647f002d, 0x647f002b,
+ 0x647f0029, 0x637f002f, 0x637f002d, 0x637f002a,
+ 0x627f0030, 0x627f002d, 0x627f002b, 0x627f0029,
+ 0x617f0030, 0x617f002e, 0x617f002b, 0x617f0029,
+ 0x607f002f, 0x607f002d, 0x607f002a, 0x607f0027,
+ 0x607f0026, 0x607f0023, 0x607f0021, 0x607f0020,
+ 0x607f001e, 0x607f001c, 0x607f001a, 0x607f0019,
+ 0x607f0018, 0x607f0016, 0x607f0015, 0x607f0014,
+ 0x607f0012, 0x607f0012, 0x607f0011, 0x607f000f,
+ 0x607f000f, 0x607f000e, 0x607f000d, 0x607f000c,
+ 0x607f000c, 0x607f000b, 0x607f000b, 0x607f000a,
+ 0x607f0009, 0x607f0009, 0x607f0008, 0x607f0008,
+ 0x607f0008, 0x607f0007, 0x607f0007, 0x607f0006,
+ 0x607f0006, 0x607f0005, 0x607f0005, 0x607f0005,
+ 0x607f0005, 0x607f0005, 0x607f0004, 0x607f0004,
+ 0x607f0004, 0x607f0004, 0x607f0003, 0x607f0003,
+ 0x607f0003, 0x607f0003, 0x607f0002, 0x607f0002,
+ 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
+ 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
+ 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
+ 0x607f0002, 0x607f0001, 0x607f0001, 0x607f0001,
+ 0x607f0001, 0x607f0001, 0x607f0001, 0x607f0001
+};
+
+static s8 nphy_papd_pga_gain_delta_ipa_2g[] = {
+ -114, -108, -98, -91, -84, -78, -70, -62,
+ -54, -46, -39, -31, -23, -15, -8, 0
+};
+
+static s8 nphy_papd_pga_gain_delta_ipa_5g[] = {
+ -100, -95, -89, -83, -77, -70, -63, -56,
+ -48, -41, -33, -25, -19, -12, -6, 0
+};
+
+static s16 nphy_papd_padgain_dlt_2g_2057rev3n4[] = {
+ -159, -113, -86, -72, -62, -54, -48, -43,
+ -39, -35, -31, -28, -25, -23, -20, -18,
+ -17, -15, -13, -11, -10, -8, -7, -6,
+ -5, -4, -3, -3, -2, -1, -1, 0
+};
+
+static s16 nphy_papd_padgain_dlt_2g_2057rev5[] = {
+ -109, -109, -82, -68, -58, -50, -44, -39,
+ -35, -31, -28, -26, -23, -21, -19, -17,
+ -16, -14, -13, -11, -10, -9, -8, -7,
+ -5, -5, -4, -3, -2, -1, -1, 0
+};
+
+static s16 nphy_papd_padgain_dlt_2g_2057rev7[] = {
+ -122, -122, -95, -80, -69, -61, -54, -49,
+ -43, -39, -35, -32, -28, -26, -23, -21,
+ -18, -16, -15, -13, -11, -10, -8, -7,
+ -6, -5, -4, -3, -2, -1, -1, 0
+};
+
+static s8 nphy_papd_pgagain_dlt_5g_2057[] = {
+ -107, -101, -92, -85, -78, -71, -62, -55,
+ -47, -39, -32, -24, -19, -12, -6, 0
+};
+
+static s8 nphy_papd_pgagain_dlt_5g_2057rev7[] = {
+ -110, -104, -95, -88, -81, -74, -66, -58,
+ -50, -44, -36, -28, -23, -15, -8, 0
+};
+
+static u8 pad_gain_codes_used_2057rev5[] = {
+ 20, 19, 18, 17, 16, 15, 14, 13, 12, 11,
+ 10, 9, 8, 7, 6, 5, 4, 3, 2, 1
+};
+
+static u8 pad_gain_codes_used_2057rev7[] = {
+ 15, 14, 13, 12, 11, 10, 9, 8, 7, 6,
+ 5, 4, 3, 2, 1
+};
+
+static u8 pad_all_gain_codes_2057[] = {
+ 31, 30, 29, 28, 27, 26, 25, 24, 23, 22,
+ 21, 20, 19, 18, 17, 16, 15, 14, 13, 12,
+ 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
+ 1, 0
+};
+
+static u8 pga_all_gain_codes_2057[] = {
+ 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
+};
+
+static u32 nphy_papd_scaltbl[] = {
+ 0x0ae2002f, 0x0a3b0032, 0x09a70035, 0x09220038,
+ 0x0887003c, 0x081f003f, 0x07a20043, 0x07340047,
+ 0x06d2004b, 0x067a004f, 0x06170054, 0x05bf0059,
+ 0x0571005e, 0x051e0064, 0x04d3006a, 0x04910070,
+ 0x044c0077, 0x040f007e, 0x03d90085, 0x03a1008d,
+ 0x036f0095, 0x033d009e, 0x030b00a8, 0x02e000b2,
+ 0x02b900bc, 0x029200c7, 0x026d00d3, 0x024900e0,
+ 0x022900ed, 0x020a00fb, 0x01ec010a, 0x01d0011a,
+ 0x01b7012a, 0x019e013c, 0x0187014f, 0x01720162,
+ 0x015d0177, 0x0149018e, 0x013701a5, 0x012601be,
+ 0x011501d9, 0x010501f5, 0x00f70212, 0x00e90232,
+ 0x00dc0253, 0x00d00276, 0x00c4029c, 0x00b902c3,
+ 0x00af02ed, 0x00a5031a, 0x009c0349, 0x0093037a,
+ 0x008b03af, 0x008303e7, 0x007c0422, 0x00750461,
+ 0x006e04a3, 0x006804ea, 0x00620534, 0x005d0583,
+ 0x005805d7, 0x0053062f, 0x004e068d, 0x004a06f1
+};
+
+static u32 nphy_tpc_txgain_rev3[] = {
+ 0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
+ 0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
+ 0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
+ 0x1e41003c, 0x1e41003b, 0x1e410039, 0x1e410037,
+ 0x1d410044, 0x1d410042, 0x1d410040, 0x1d41003e,
+ 0x1d41003c, 0x1d41003b, 0x1d410039, 0x1d410037,
+ 0x1c410044, 0x1c410042, 0x1c410040, 0x1c41003e,
+ 0x1c41003c, 0x1c41003b, 0x1c410039, 0x1c410037,
+ 0x1b410044, 0x1b410042, 0x1b410040, 0x1b41003e,
+ 0x1b41003c, 0x1b41003b, 0x1b410039, 0x1b410037,
+ 0x1a410044, 0x1a410042, 0x1a410040, 0x1a41003e,
+ 0x1a41003c, 0x1a41003b, 0x1a410039, 0x1a410037,
+ 0x19410044, 0x19410042, 0x19410040, 0x1941003e,
+ 0x1941003c, 0x1941003b, 0x19410039, 0x19410037,
+ 0x18410044, 0x18410042, 0x18410040, 0x1841003e,
+ 0x1841003c, 0x1841003b, 0x18410039, 0x18410037,
+ 0x17410044, 0x17410042, 0x17410040, 0x1741003e,
+ 0x1741003c, 0x1741003b, 0x17410039, 0x17410037,
+ 0x16410044, 0x16410042, 0x16410040, 0x1641003e,
+ 0x1641003c, 0x1641003b, 0x16410039, 0x16410037,
+ 0x15410044, 0x15410042, 0x15410040, 0x1541003e,
+ 0x1541003c, 0x1541003b, 0x15410039, 0x15410037,
+ 0x14410044, 0x14410042, 0x14410040, 0x1441003e,
+ 0x1441003c, 0x1441003b, 0x14410039, 0x14410037,
+ 0x13410044, 0x13410042, 0x13410040, 0x1341003e,
+ 0x1341003c, 0x1341003b, 0x13410039, 0x13410037,
+ 0x12410044, 0x12410042, 0x12410040, 0x1241003e,
+ 0x1241003c, 0x1241003b, 0x12410039, 0x12410037,
+ 0x11410044, 0x11410042, 0x11410040, 0x1141003e,
+ 0x1141003c, 0x1141003b, 0x11410039, 0x11410037,
+ 0x10410044, 0x10410042, 0x10410040, 0x1041003e,
+ 0x1041003c, 0x1041003b, 0x10410039, 0x10410037
+};
+
+static u32 nphy_tpc_txgain_HiPwrEPA[] = {
+ 0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e,
+ 0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037,
+ 0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e,
+ 0x0e41003c, 0x0e41003b, 0x0e410039, 0x0e410037,
+ 0x0d410044, 0x0d410042, 0x0d410040, 0x0d41003e,
+ 0x0d41003c, 0x0d41003b, 0x0d410039, 0x0d410037,
+ 0x0c410044, 0x0c410042, 0x0c410040, 0x0c41003e,
+ 0x0c41003c, 0x0c41003b, 0x0c410039, 0x0c410037,
+ 0x0b410044, 0x0b410042, 0x0b410040, 0x0b41003e,
+ 0x0b41003c, 0x0b41003b, 0x0b410039, 0x0b410037,
+ 0x0a410044, 0x0a410042, 0x0a410040, 0x0a41003e,
+ 0x0a41003c, 0x0a41003b, 0x0a410039, 0x0a410037,
+ 0x09410044, 0x09410042, 0x09410040, 0x0941003e,
+ 0x0941003c, 0x0941003b, 0x09410039, 0x09410037,
+ 0x08410044, 0x08410042, 0x08410040, 0x0841003e,
+ 0x0841003c, 0x0841003b, 0x08410039, 0x08410037,
+ 0x07410044, 0x07410042, 0x07410040, 0x0741003e,
+ 0x0741003c, 0x0741003b, 0x07410039, 0x07410037,
+ 0x06410044, 0x06410042, 0x06410040, 0x0641003e,
+ 0x0641003c, 0x0641003b, 0x06410039, 0x06410037,
+ 0x05410044, 0x05410042, 0x05410040, 0x0541003e,
+ 0x0541003c, 0x0541003b, 0x05410039, 0x05410037,
+ 0x04410044, 0x04410042, 0x04410040, 0x0441003e,
+ 0x0441003c, 0x0441003b, 0x04410039, 0x04410037,
+ 0x03410044, 0x03410042, 0x03410040, 0x0341003e,
+ 0x0341003c, 0x0341003b, 0x03410039, 0x03410037,
+ 0x02410044, 0x02410042, 0x02410040, 0x0241003e,
+ 0x0241003c, 0x0241003b, 0x02410039, 0x02410037,
+ 0x01410044, 0x01410042, 0x01410040, 0x0141003e,
+ 0x0141003c, 0x0141003b, 0x01410039, 0x01410037,
+ 0x00410044, 0x00410042, 0x00410040, 0x0041003e,
+ 0x0041003c, 0x0041003b, 0x00410039, 0x00410037
+};
+
+static u32 nphy_tpc_txgain_epa_2057rev3[] = {
+ 0x80f90040, 0x80e10040, 0x80e1003c, 0x80c9003d,
+ 0x80b9003c, 0x80a9003d, 0x80a1003c, 0x8099003b,
+ 0x8091003b, 0x8089003a, 0x8081003a, 0x80790039,
+ 0x80710039, 0x8069003a, 0x8061003b, 0x8059003d,
+ 0x8051003f, 0x80490042, 0x8049003e, 0x8049003b,
+ 0x8041003e, 0x8041003b, 0x8039003e, 0x8039003b,
+ 0x80390038, 0x80390035, 0x8031003a, 0x80310036,
+ 0x80310033, 0x8029003a, 0x80290037, 0x80290034,
+ 0x80290031, 0x80210039, 0x80210036, 0x80210033,
+ 0x80210030, 0x8019003c, 0x80190039, 0x80190036,
+ 0x80190033, 0x80190030, 0x8019002d, 0x8019002b,
+ 0x80190028, 0x8011003a, 0x80110036, 0x80110033,
+ 0x80110030, 0x8011002e, 0x8011002b, 0x80110029,
+ 0x80110027, 0x80110024, 0x80110022, 0x80110020,
+ 0x8011001f, 0x8011001d, 0x8009003a, 0x80090037,
+ 0x80090034, 0x80090031, 0x8009002e, 0x8009002c,
+ 0x80090029, 0x80090027, 0x80090025, 0x80090023,
+ 0x80090021, 0x8009001f, 0x8009001d, 0x8009011d,
+ 0x8009021d, 0x8009031d, 0x8009041d, 0x8009051d,
+ 0x8009061d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
+ 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d
+};
+
+static u32 nphy_tpc_txgain_epa_2057rev5[] = {
+ 0x10f90040, 0x10e10040, 0x10e1003c, 0x10c9003d,
+ 0x10b9003c, 0x10a9003d, 0x10a1003c, 0x1099003b,
+ 0x1091003b, 0x1089003a, 0x1081003a, 0x10790039,
+ 0x10710039, 0x1069003a, 0x1061003b, 0x1059003d,
+ 0x1051003f, 0x10490042, 0x1049003e, 0x1049003b,
+ 0x1041003e, 0x1041003b, 0x1039003e, 0x1039003b,
+ 0x10390038, 0x10390035, 0x1031003a, 0x10310036,
+ 0x10310033, 0x1029003a, 0x10290037, 0x10290034,
+ 0x10290031, 0x10210039, 0x10210036, 0x10210033,
+ 0x10210030, 0x1019003c, 0x10190039, 0x10190036,
+ 0x10190033, 0x10190030, 0x1019002d, 0x1019002b,
+ 0x10190028, 0x1011003a, 0x10110036, 0x10110033,
+ 0x10110030, 0x1011002e, 0x1011002b, 0x10110029,
+ 0x10110027, 0x10110024, 0x10110022, 0x10110020,
+ 0x1011001f, 0x1011001d, 0x1009003a, 0x10090037,
+ 0x10090034, 0x10090031, 0x1009002e, 0x1009002c,
+ 0x10090029, 0x10090027, 0x10090025, 0x10090023,
+ 0x10090021, 0x1009001f, 0x1009001d, 0x1009001b,
+ 0x1009001a, 0x10090018, 0x10090017, 0x10090016,
+ 0x10090015, 0x10090013, 0x10090012, 0x10090011,
+ 0x10090010, 0x1009000f, 0x1009000f, 0x1009000e,
+ 0x1009000d, 0x1009000c, 0x1009000c, 0x1009000b,
+ 0x1009000a, 0x1009000a, 0x10090009, 0x10090009,
+ 0x10090008, 0x10090008, 0x10090007, 0x10090007,
+ 0x10090007, 0x10090006, 0x10090006, 0x10090005,
+ 0x10090005, 0x10090005, 0x10090005, 0x10090004,
+ 0x10090004, 0x10090004, 0x10090004, 0x10090003,
+ 0x10090003, 0x10090003, 0x10090003, 0x10090003,
+ 0x10090003, 0x10090002, 0x10090002, 0x10090002,
+ 0x10090002, 0x10090002, 0x10090002, 0x10090002,
+ 0x10090002, 0x10090002, 0x10090001, 0x10090001,
+ 0x10090001, 0x10090001, 0x10090001, 0x10090001
+};
+
+static u32 nphy_tpc_5GHz_txgain_rev3[] = {
+ 0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
+ 0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
+ 0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
+ 0xcef7003c, 0xcef7003b, 0xcef70039, 0xcef70037,
+ 0xcdf70044, 0xcdf70042, 0xcdf70040, 0xcdf7003e,
+ 0xcdf7003c, 0xcdf7003b, 0xcdf70039, 0xcdf70037,
+ 0xccf70044, 0xccf70042, 0xccf70040, 0xccf7003e,
+ 0xccf7003c, 0xccf7003b, 0xccf70039, 0xccf70037,
+ 0xcbf70044, 0xcbf70042, 0xcbf70040, 0xcbf7003e,
+ 0xcbf7003c, 0xcbf7003b, 0xcbf70039, 0xcbf70037,
+ 0xcaf70044, 0xcaf70042, 0xcaf70040, 0xcaf7003e,
+ 0xcaf7003c, 0xcaf7003b, 0xcaf70039, 0xcaf70037,
+ 0xc9f70044, 0xc9f70042, 0xc9f70040, 0xc9f7003e,
+ 0xc9f7003c, 0xc9f7003b, 0xc9f70039, 0xc9f70037,
+ 0xc8f70044, 0xc8f70042, 0xc8f70040, 0xc8f7003e,
+ 0xc8f7003c, 0xc8f7003b, 0xc8f70039, 0xc8f70037,
+ 0xc7f70044, 0xc7f70042, 0xc7f70040, 0xc7f7003e,
+ 0xc7f7003c, 0xc7f7003b, 0xc7f70039, 0xc7f70037,
+ 0xc6f70044, 0xc6f70042, 0xc6f70040, 0xc6f7003e,
+ 0xc6f7003c, 0xc6f7003b, 0xc6f70039, 0xc6f70037,
+ 0xc5f70044, 0xc5f70042, 0xc5f70040, 0xc5f7003e,
+ 0xc5f7003c, 0xc5f7003b, 0xc5f70039, 0xc5f70037,
+ 0xc4f70044, 0xc4f70042, 0xc4f70040, 0xc4f7003e,
+ 0xc4f7003c, 0xc4f7003b, 0xc4f70039, 0xc4f70037,
+ 0xc3f70044, 0xc3f70042, 0xc3f70040, 0xc3f7003e,
+ 0xc3f7003c, 0xc3f7003b, 0xc3f70039, 0xc3f70037,
+ 0xc2f70044, 0xc2f70042, 0xc2f70040, 0xc2f7003e,
+ 0xc2f7003c, 0xc2f7003b, 0xc2f70039, 0xc2f70037,
+ 0xc1f70044, 0xc1f70042, 0xc1f70040, 0xc1f7003e,
+ 0xc1f7003c, 0xc1f7003b, 0xc1f70039, 0xc1f70037,
+ 0xc0f70044, 0xc0f70042, 0xc0f70040, 0xc0f7003e,
+ 0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037
+};
+
+static u32 nphy_tpc_5GHz_txgain_rev4[] = {
+ 0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
+ 0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
+ 0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
+ 0x2ef2003c, 0x2ef2003b, 0x2ef20039, 0x2ef20037,
+ 0x2df20044, 0x2df20042, 0x2df20040, 0x2df2003e,
+ 0x2df2003c, 0x2df2003b, 0x2df20039, 0x2df20037,
+ 0x2cf20044, 0x2cf20042, 0x2cf20040, 0x2cf2003e,
+ 0x2cf2003c, 0x2cf2003b, 0x2cf20039, 0x2cf20037,
+ 0x2bf20044, 0x2bf20042, 0x2bf20040, 0x2bf2003e,
+ 0x2bf2003c, 0x2bf2003b, 0x2bf20039, 0x2bf20037,
+ 0x2af20044, 0x2af20042, 0x2af20040, 0x2af2003e,
+ 0x2af2003c, 0x2af2003b, 0x2af20039, 0x2af20037,
+ 0x29f20044, 0x29f20042, 0x29f20040, 0x29f2003e,
+ 0x29f2003c, 0x29f2003b, 0x29f20039, 0x29f20037,
+ 0x28f20044, 0x28f20042, 0x28f20040, 0x28f2003e,
+ 0x28f2003c, 0x28f2003b, 0x28f20039, 0x28f20037,
+ 0x27f20044, 0x27f20042, 0x27f20040, 0x27f2003e,
+ 0x27f2003c, 0x27f2003b, 0x27f20039, 0x27f20037,
+ 0x26f20044, 0x26f20042, 0x26f20040, 0x26f2003e,
+ 0x26f2003c, 0x26f2003b, 0x26f20039, 0x26f20037,
+ 0x25f20044, 0x25f20042, 0x25f20040, 0x25f2003e,
+ 0x25f2003c, 0x25f2003b, 0x25f20039, 0x25f20037,
+ 0x24f20044, 0x24f20042, 0x24f20040, 0x24f2003e,
+ 0x24f2003c, 0x24f2003b, 0x24f20039, 0x24f20038,
+ 0x23f20041, 0x23f20040, 0x23f2003f, 0x23f2003e,
+ 0x23f2003c, 0x23f2003b, 0x23f20039, 0x23f20037,
+ 0x22f20044, 0x22f20042, 0x22f20040, 0x22f2003e,
+ 0x22f2003c, 0x22f2003b, 0x22f20039, 0x22f20037,
+ 0x21f20044, 0x21f20042, 0x21f20040, 0x21f2003e,
+ 0x21f2003c, 0x21f2003b, 0x21f20039, 0x21f20037,
+ 0x20d20043, 0x20d20041, 0x20d2003e, 0x20d2003c,
+ 0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034
+};
+
+static u32 nphy_tpc_5GHz_txgain_rev5[] = {
+ 0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
+ 0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
+ 0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
+ 0x0e62003c, 0x0e62003d, 0x0e62003b, 0x0e62003a,
+ 0x0d620043, 0x0d620041, 0x0d620040, 0x0d62003e,
+ 0x0d62003d, 0x0d62003c, 0x0d62003b, 0x0d62003a,
+ 0x0c620041, 0x0c620040, 0x0c62003f, 0x0c62003e,
+ 0x0c62003c, 0x0c62003b, 0x0c620039, 0x0c620037,
+ 0x0b620046, 0x0b620044, 0x0b620042, 0x0b620040,
+ 0x0b62003e, 0x0b62003c, 0x0b62003b, 0x0b62003a,
+ 0x0a620041, 0x0a620040, 0x0a62003e, 0x0a62003c,
+ 0x0a62003b, 0x0a62003a, 0x0a620039, 0x0a620038,
+ 0x0962003e, 0x0962003d, 0x0962003c, 0x0962003b,
+ 0x09620039, 0x09620037, 0x09620035, 0x09620033,
+ 0x08620044, 0x08620042, 0x08620040, 0x0862003e,
+ 0x0862003c, 0x0862003b, 0x0862003a, 0x08620039,
+ 0x07620043, 0x07620042, 0x07620040, 0x0762003f,
+ 0x0762003d, 0x0762003b, 0x0762003a, 0x07620039,
+ 0x0662003e, 0x0662003d, 0x0662003c, 0x0662003b,
+ 0x06620039, 0x06620037, 0x06620035, 0x06620033,
+ 0x05620046, 0x05620044, 0x05620042, 0x05620040,
+ 0x0562003e, 0x0562003c, 0x0562003b, 0x05620039,
+ 0x04620044, 0x04620042, 0x04620040, 0x0462003e,
+ 0x0462003c, 0x0462003b, 0x04620039, 0x04620038,
+ 0x0362003c, 0x0362003b, 0x0362003a, 0x03620039,
+ 0x03620038, 0x03620037, 0x03620035, 0x03620033,
+ 0x0262004c, 0x0262004a, 0x02620048, 0x02620047,
+ 0x02620046, 0x02620044, 0x02620043, 0x02620042,
+ 0x0162004a, 0x01620048, 0x01620046, 0x01620044,
+ 0x01620043, 0x01620042, 0x01620041, 0x01620040,
+ 0x00620042, 0x00620040, 0x0062003e, 0x0062003c,
+ 0x0062003b, 0x00620039, 0x00620037, 0x00620035
+};
+
+static u32 nphy_tpc_5GHz_txgain_HiPwrEPA[] = {
+ 0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e,
+ 0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037,
+ 0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e,
+ 0x2ef1003c, 0x2ef1003b, 0x2ef10039, 0x2ef10037,
+ 0x2df10044, 0x2df10042, 0x2df10040, 0x2df1003e,
+ 0x2df1003c, 0x2df1003b, 0x2df10039, 0x2df10037,
+ 0x2cf10044, 0x2cf10042, 0x2cf10040, 0x2cf1003e,
+ 0x2cf1003c, 0x2cf1003b, 0x2cf10039, 0x2cf10037,
+ 0x2bf10044, 0x2bf10042, 0x2bf10040, 0x2bf1003e,
+ 0x2bf1003c, 0x2bf1003b, 0x2bf10039, 0x2bf10037,
+ 0x2af10044, 0x2af10042, 0x2af10040, 0x2af1003e,
+ 0x2af1003c, 0x2af1003b, 0x2af10039, 0x2af10037,
+ 0x29f10044, 0x29f10042, 0x29f10040, 0x29f1003e,
+ 0x29f1003c, 0x29f1003b, 0x29f10039, 0x29f10037,
+ 0x28f10044, 0x28f10042, 0x28f10040, 0x28f1003e,
+ 0x28f1003c, 0x28f1003b, 0x28f10039, 0x28f10037,
+ 0x27f10044, 0x27f10042, 0x27f10040, 0x27f1003e,
+ 0x27f1003c, 0x27f1003b, 0x27f10039, 0x27f10037,
+ 0x26f10044, 0x26f10042, 0x26f10040, 0x26f1003e,
+ 0x26f1003c, 0x26f1003b, 0x26f10039, 0x26f10037,
+ 0x25f10044, 0x25f10042, 0x25f10040, 0x25f1003e,
+ 0x25f1003c, 0x25f1003b, 0x25f10039, 0x25f10037,
+ 0x24f10044, 0x24f10042, 0x24f10040, 0x24f1003e,
+ 0x24f1003c, 0x24f1003b, 0x24f10039, 0x24f10038,
+ 0x23f10041, 0x23f10040, 0x23f1003f, 0x23f1003e,
+ 0x23f1003c, 0x23f1003b, 0x23f10039, 0x23f10037,
+ 0x22f10044, 0x22f10042, 0x22f10040, 0x22f1003e,
+ 0x22f1003c, 0x22f1003b, 0x22f10039, 0x22f10037,
+ 0x21f10044, 0x21f10042, 0x21f10040, 0x21f1003e,
+ 0x21f1003c, 0x21f1003b, 0x21f10039, 0x21f10037,
+ 0x20d10043, 0x20d10041, 0x20d1003e, 0x20d1003c,
+ 0x20d1003a, 0x20d10038, 0x20d10036, 0x20d10034
+};
+
+static u8 ant_sw_ctrl_tbl_rev8_2o3[] = { 0x14, 0x18 };
+static u8 ant_sw_ctrl_tbl_rev8[] = { 0x4, 0x8, 0x4, 0x8, 0x11, 0x12 };
+static u8 ant_sw_ctrl_tbl_rev8_2057v7_core0[] = {
+ 0x09, 0x0a, 0x15, 0x16, 0x09, 0x0a };
+static u8 ant_sw_ctrl_tbl_rev8_2057v7_core1[] = {
+ 0x09, 0x0a, 0x09, 0x0a, 0x15, 0x16 };
+
+static bool wlc_phy_chan2freq_nphy(phy_info_t *pi, uint channel, int *f,
+ chan_info_nphy_radio2057_t **t0,
+ chan_info_nphy_radio205x_t **t1,
+ chan_info_nphy_radio2057_rev5_t **t2,
+ chan_info_nphy_2055_t **t3);
+static void wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chans,
+ const nphy_sfo_cfg_t *c);
+
+static void wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi,
+ u16 reduction_factr);
+static void wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *,
+ u32 *buf);
+static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr);
+static void wlc_phy_txlpfbw_nphy(phy_info_t *pi);
+static void wlc_phy_spurwar_nphy(phy_info_t *pi);
+
+static void wlc_phy_radio_preinit_2055(phy_info_t *pi);
+static void wlc_phy_radio_init_2055(phy_info_t *pi);
+static void wlc_phy_radio_postinit_2055(phy_info_t *pi);
+static void wlc_phy_radio_preinit_205x(phy_info_t *pi);
+static void wlc_phy_radio_init_2056(phy_info_t *pi);
+static void wlc_phy_radio_postinit_2056(phy_info_t *pi);
+static void wlc_phy_radio_init_2057(phy_info_t *pi);
+static void wlc_phy_radio_postinit_2057(phy_info_t *pi);
+static void wlc_phy_workarounds_nphy(phy_info_t *pi);
+static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi);
+static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(phy_info_t *pi);
+static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi);
+static void wlc_phy_adjust_lnagaintbl_nphy(phy_info_t *pi);
+
+static void wlc_phy_restore_rssical_nphy(phy_info_t *pi);
+static void wlc_phy_reapply_txcal_coeffs_nphy(phy_info_t *pi);
+static void wlc_phy_tx_iq_war_nphy(phy_info_t *pi);
+static int wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t tg,
+ u8 type, bool d);
+static void wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rxcore,
+ u16 *rg, u8 type);
+static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, s32 preamble);
+static void wlc_phy_savecal_nphy(phy_info_t *pi);
+static void wlc_phy_restorecal_nphy(phy_info_t *pi);
+static void wlc_phy_resetcca_nphy(phy_info_t *pi);
+
+static void wlc_phy_txpwrctrl_config_nphy(phy_info_t *pi);
+static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi);
+static void wlc_phy_precal_txgain_nphy(phy_info_t *pi);
+static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core);
+
+static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi);
+static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi);
+static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi);
+static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi);
+static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1);
+static u32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi);
+
+static void wlc_phy_a1_nphy(phy_info_t *pi, u8 core, u32 winsz, u32,
+ u32 e);
+static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core);
+static void wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *,
+ phy_cal_mode_t, u8);
+static void wlc_phy_papd_cal_cleanup_nphy(phy_info_t *pi,
+ nphy_papd_restore_state *state);
+static void wlc_phy_papd_cal_setup_nphy(phy_info_t *pi,
+ nphy_papd_restore_state *state, u8);
+
+static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, u16 *vals);
+
+static void wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *evts,
+ u8 *dlys, u8 len);
+
+static u16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, u16 offset);
+
+static void
+wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, u16 field, u16 value,
+ u8 core_mask, u8 off,
+ u8 override_id);
+
+static void wlc_phy_rssi_cal_nphy_rev2(phy_info_t *pi, u8 rssi_type);
+static void wlc_phy_rssi_cal_nphy_rev3(phy_info_t *pi);
+
+static bool wlc_phy_txpwr_srom_read_nphy(phy_info_t *pi);
+static void wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max,
+ u16 *pwr_offset,
+ u8 tmp_max_pwr, u8 rate_start,
+ u8 rate_end);
+
+static void wlc_phy_txpwr_limit_to_tbl_nphy(phy_info_t *pi);
+static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi);
+static void wlc_phy_txpwrctrl_idle_tssi_nphy(phy_info_t *pi);
+static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi);
+
+static bool wlc_phy_txpwr_ison_nphy(phy_info_t *pi);
+static u8 wlc_phy_txpwr_idx_cur_get_nphy(phy_info_t *pi, u8 core);
+static void wlc_phy_txpwr_idx_cur_set_nphy(phy_info_t *pi, u8 idx0,
+ u8 idx1);
+static void wlc_phy_a4(phy_info_t *pi, bool full_cal);
+
+static u16 wlc_phy_radio205x_rcal(phy_info_t *pi);
+
+static u16 wlc_phy_radio2057_rccal(phy_info_t *pi);
+
+static u16 wlc_phy_gen_load_samples_nphy(phy_info_t *pi, u32 f_kHz,
+ u16 max_val,
+ u8 dac_test_mode);
+static void wlc_phy_loadsampletable_nphy(phy_info_t *pi, cs32 *tone_buf,
+ u16 num_samps);
+static void wlc_phy_runsamples_nphy(phy_info_t *pi, u16 n, u16 lps,
+ u16 wait, u8 iq, u8 dac_test_mode,
+ bool modify_bbmult);
+
+bool wlc_phy_bist_check_phy(wlc_phy_t *pih)
+{
+ phy_info_t *pi = (phy_info_t *) pih;
+ u32 phybist0, phybist1, phybist2, phybist3, phybist4;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 16))
+ return true;
+
+ phybist0 = read_phy_reg(pi, 0x0e);
+ phybist1 = read_phy_reg(pi, 0x0f);
+ phybist2 = read_phy_reg(pi, 0xea);
+ phybist3 = read_phy_reg(pi, 0xeb);
+ phybist4 = read_phy_reg(pi, 0x156);
+
+ if ((phybist0 == 0) && (phybist1 == 0x4000) && (phybist2 == 0x1fe0) &&
+ (phybist3 == 0) && (phybist4 == 0)) {
+ return true;
+ }
+
+ return false;
+}
+
+static void WLBANDINITFN(wlc_phy_bphy_init_nphy) (phy_info_t *pi)
+{
+ u16 addr, val;
+
+ val = 0x1e1f;
+ for (addr = (NPHY_TO_BPHY_OFF + BPHY_RSSI_LUT);
+ addr <= (NPHY_TO_BPHY_OFF + BPHY_RSSI_LUT_END); addr++) {
+ write_phy_reg(pi, addr, val);
+ if (addr == (NPHY_TO_BPHY_OFF + 0x97))
+ val = 0x3e3f;
+ else
+ val -= 0x0202;
+ }
+
+ if (NORADIO_ENAB(pi->pubpi)) {
+
+ write_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_PHYCRSTH, 0x3206);
+
+ write_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_RSSI_TRESH, 0x281e);
+
+ or_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_LNA_GAIN_RANGE, 0x1a);
+
+ } else {
+
+ write_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_STEP, 0x668);
+ }
+}
+
+void
+wlc_phy_table_write_nphy(phy_info_t *pi, u32 id, u32 len, u32 offset,
+ u32 width, const void *data)
+{
+ mimophytbl_info_t tbl;
+
+ tbl.tbl_id = id;
+ tbl.tbl_len = len;
+ tbl.tbl_offset = offset;
+ tbl.tbl_width = width;
+ tbl.tbl_ptr = data;
+ wlc_phy_write_table_nphy(pi, &tbl);
+}
+
+void
+wlc_phy_table_read_nphy(phy_info_t *pi, u32 id, u32 len, u32 offset,
+ u32 width, void *data)
+{
+ mimophytbl_info_t tbl;
+
+ tbl.tbl_id = id;
+ tbl.tbl_len = len;
+ tbl.tbl_offset = offset;
+ tbl.tbl_width = width;
+ tbl.tbl_ptr = data;
+ wlc_phy_read_table_nphy(pi, &tbl);
+}
+
+static void WLBANDINITFN(wlc_phy_static_table_download_nphy) (phy_info_t *pi)
+{
+ uint idx;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 16)) {
+ for (idx = 0; idx < mimophytbl_info_sz_rev16; idx++)
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev16[idx]);
+ } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ for (idx = 0; idx < mimophytbl_info_sz_rev7; idx++)
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev7[idx]);
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ for (idx = 0; idx < mimophytbl_info_sz_rev3; idx++)
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev3[idx]);
+ } else {
+ for (idx = 0; idx < mimophytbl_info_sz_rev0; idx++)
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev0[idx]);
+ }
+}
+
+static void WLBANDINITFN(wlc_phy_tbl_init_nphy) (phy_info_t *pi)
+{
+ uint idx = 0;
+ u8 antswctrllut;
+
+ if (pi->phy_init_por)
+ wlc_phy_static_table_download_nphy(pi);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ antswctrllut = CHSPEC_IS2G(pi->radio_chanspec) ?
+ pi->srom_fem2g.antswctrllut : pi->srom_fem5g.antswctrllut;
+
+ switch (antswctrllut) {
+ case 0:
+
+ break;
+
+ case 1:
+
+ if (pi->aa2g == 7) {
+
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x21, 8,
+ &ant_sw_ctrl_tbl_rev8_2o3
+ [0]);
+ } else {
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x21, 8,
+ &ant_sw_ctrl_tbl_rev8
+ [0]);
+ }
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x25, 8,
+ &ant_sw_ctrl_tbl_rev8[2]);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x29, 8,
+ &ant_sw_ctrl_tbl_rev8[4]);
+ break;
+
+ case 2:
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x1, 8,
+ &ant_sw_ctrl_tbl_rev8_2057v7_core0
+ [0]);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x5, 8,
+ &ant_sw_ctrl_tbl_rev8_2057v7_core0
+ [2]);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x9, 8,
+ &ant_sw_ctrl_tbl_rev8_2057v7_core0
+ [4]);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x21, 8,
+ &ant_sw_ctrl_tbl_rev8_2057v7_core1
+ [0]);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x25, 8,
+ &ant_sw_ctrl_tbl_rev8_2057v7_core1
+ [2]);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 2, 0x29, 8,
+ &ant_sw_ctrl_tbl_rev8_2057v7_core1
+ [4]);
+ break;
+
+ default:
+ break;
+ }
+
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ for (idx = 0; idx < mimophytbl_info_sz_rev3_volatile; idx++) {
+
+ if (idx == ANT_SWCTRL_TBL_REV3_IDX) {
+ antswctrllut = CHSPEC_IS2G(pi->radio_chanspec) ?
+ pi->srom_fem2g.antswctrllut : pi->
+ srom_fem5g.antswctrllut;
+ switch (antswctrllut) {
+ case 0:
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev3_volatile
+ [idx]);
+ break;
+ case 1:
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev3_volatile1
+ [idx]);
+ break;
+ case 2:
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev3_volatile2
+ [idx]);
+ break;
+ case 3:
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev3_volatile3
+ [idx]);
+ break;
+ default:
+ break;
+ }
+ } else {
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev3_volatile
+ [idx]);
+ }
+ }
+ } else {
+ for (idx = 0; idx < mimophytbl_info_sz_rev0_volatile; idx++) {
+ wlc_phy_write_table_nphy(pi,
+ &mimophytbl_info_rev0_volatile
+ [idx]);
+ }
+ }
+}
+
+static void
+wlc_phy_write_txmacreg_nphy(phy_info_t *pi, u16 holdoff, u16 delay)
+{
+ write_phy_reg(pi, 0x77, holdoff);
+ write_phy_reg(pi, 0xb4, delay);
+}
+
+void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs)
+{
+ u16 holdoff, delay;
+
+ if (rifs) {
+
+ holdoff = 0x10;
+ delay = 0x258;
+ } else {
+
+ holdoff = 0x15;
+ delay = 0x320;
+ }
+
+ wlc_phy_write_txmacreg_nphy(pi, holdoff, delay);
+
+ if (pi && pi->sh && (pi->sh->_rifs_phy != rifs)) {
+ pi->sh->_rifs_phy = rifs;
+ }
+}
+
+bool wlc_phy_attach_nphy(phy_info_t *pi)
+{
+ uint i;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 6)) {
+ pi->phyhang_avoid = true;
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
+
+ pi->nphy_gband_spurwar_en = true;
+
+ if (pi->sh->boardflags2 & BFL2_SPUR_WAR) {
+ pi->nphy_aband_spurwar_en = true;
+ }
+ }
+ if (NREV_GE(pi->pubpi.phy_rev, 6) && NREV_LT(pi->pubpi.phy_rev, 7)) {
+
+ if (pi->sh->boardflags2 & BFL2_2G_SPUR_WAR) {
+ pi->nphy_gband_spurwar2_en = true;
+ }
+ }
+
+ pi->n_preamble_override = AUTO;
+ if (NREV_IS(pi->pubpi.phy_rev, 3) || NREV_IS(pi->pubpi.phy_rev, 4))
+ pi->n_preamble_override = WLC_N_PREAMBLE_MIXEDMODE;
+
+ pi->nphy_txrx_chain = AUTO;
+ pi->phy_scraminit = AUTO;
+
+ pi->nphy_rxcalparams = 0x010100B5;
+
+ pi->nphy_perical = PHY_PERICAL_MPHASE;
+ pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
+ pi->mphase_txcal_numcmds = MPHASE_TXCAL_NUMCMDS;
+
+ pi->nphy_gain_boost = true;
+ pi->nphy_elna_gain_config = false;
+ pi->radio_is_on = false;
+
+ for (i = 0; i < pi->pubpi.phy_corenum; i++) {
+ pi->nphy_txpwrindex[i].index = AUTO;
+ }
+
+ wlc_phy_txpwrctrl_config_nphy(pi);
+ if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
+ pi->hwpwrctrl_capable = true;
+
+ pi->pi_fptr.init = wlc_phy_init_nphy;
+ pi->pi_fptr.calinit = wlc_phy_cal_init_nphy;
+ pi->pi_fptr.chanset = wlc_phy_chanspec_set_nphy;
+ pi->pi_fptr.txpwrrecalc = wlc_phy_txpower_recalc_target_nphy;
+
+ if (!wlc_phy_txpwr_srom_read_nphy(pi))
+ return false;
+
+ return true;
+}
+
+static void wlc_phy_txpwrctrl_config_nphy(phy_info_t *pi)
+{
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ pi->nphy_txpwrctrl = PHY_TPC_HW_ON;
+ pi->phy_5g_pwrgain = true;
+ return;
+ }
+
+ pi->nphy_txpwrctrl = PHY_TPC_HW_OFF;
+ pi->phy_5g_pwrgain = false;
+
+ if ((pi->sh->boardflags2 & BFL2_TXPWRCTRL_EN) &&
+ NREV_GE(pi->pubpi.phy_rev, 2) && (pi->sh->sromrev >= 4))
+ pi->nphy_txpwrctrl = PHY_TPC_HW_ON;
+ else if ((pi->sh->sromrev >= 4)
+ && (pi->sh->boardflags2 & BFL2_5G_PWRGAIN))
+ pi->phy_5g_pwrgain = true;
+}
+
+void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
+{
+ u16 val;
+ u16 clip1_ths[2];
+ nphy_txgains_t target_gain;
+ u8 tx_pwr_ctrl_state;
+ bool do_nphy_cal = false;
+ uint core;
+ uint origidx, intr_val;
+ d11regs_t *regs;
+ u32 d11_clk_ctl_st;
+
+ core = 0;
+
+ if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN)) {
+ pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
+ }
+
+ if ((ISNPHY(pi)) && (NREV_GE(pi->pubpi.phy_rev, 5)) &&
+ ((pi->sh->chippkg == BCM4717_PKG_ID) ||
+ (pi->sh->chippkg == BCM4718_PKG_ID))) {
+ if ((pi->sh->boardflags & BFL_EXTLNA) &&
+ (CHSPEC_IS2G(pi->radio_chanspec))) {
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol), 0x40,
+ 0x40);
+ }
+ }
+
+ if ((!PHY_IPA(pi)) && (pi->sh->chip == BCM5357_CHIP_ID)) {
+ si_pmu_chipcontrol(pi->sh->sih, 1, CCTRL5357_EXTPA,
+ CCTRL5357_EXTPA);
+ }
+
+ if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
+ CHSPEC_IS40(pi->radio_chanspec)) {
+
+ regs = (d11regs_t *) ai_switch_core(pi->sh->sih, D11_CORE_ID,
+ &origidx, &intr_val);
+ d11_clk_ctl_st = R_REG(®s->clk_ctl_st);
+ AND_REG(®s->clk_ctl_st,
+ ~(CCS_FORCEHT | CCS_HTAREQ));
+
+ W_REG(®s->clk_ctl_st, d11_clk_ctl_st);
+
+ ai_restore_core(pi->sh->sih, origidx, intr_val);
+ }
+
+ pi->use_int_tx_iqlo_cal_nphy =
+ (PHY_IPA(pi) ||
+ (NREV_GE(pi->pubpi.phy_rev, 7) ||
+ (NREV_GE(pi->pubpi.phy_rev, 5)
+ && pi->sh->boardflags2 & BFL2_INTERNDET_TXIQCAL)));
+
+ pi->internal_tx_iqlo_cal_tapoff_intpa_nphy = false;
+
+ pi->nphy_deaf_count = 0;
+
+ wlc_phy_tbl_init_nphy(pi);
+
+ pi->nphy_crsminpwr_adjusted = false;
+ pi->nphy_noisevars_adjusted = false;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ write_phy_reg(pi, 0xe7, 0);
+ write_phy_reg(pi, 0xec, 0);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ write_phy_reg(pi, 0x342, 0);
+ write_phy_reg(pi, 0x343, 0);
+ write_phy_reg(pi, 0x346, 0);
+ write_phy_reg(pi, 0x347, 0);
+ }
+ write_phy_reg(pi, 0xe5, 0);
+ write_phy_reg(pi, 0xe6, 0);
+ } else {
+ write_phy_reg(pi, 0xec, 0);
+ }
+
+ write_phy_reg(pi, 0x91, 0);
+ write_phy_reg(pi, 0x92, 0);
+ if (NREV_LT(pi->pubpi.phy_rev, 6)) {
+ write_phy_reg(pi, 0x93, 0);
+ write_phy_reg(pi, 0x94, 0);
+ }
+
+ and_phy_reg(pi, 0xa1, ~3);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ write_phy_reg(pi, 0x8f, 0);
+ write_phy_reg(pi, 0xa5, 0);
+ } else {
+ write_phy_reg(pi, 0xa5, 0);
+ }
+
+ if (NREV_IS(pi->pubpi.phy_rev, 2))
+ mod_phy_reg(pi, 0xdc, 0x00ff, 0x3b);
+ else if (NREV_LT(pi->pubpi.phy_rev, 2))
+ mod_phy_reg(pi, 0xdc, 0x00ff, 0x40);
+
+ write_phy_reg(pi, 0x203, 32);
+ write_phy_reg(pi, 0x201, 32);
+
+ if (pi->sh->boardflags2 & BFL2_SKWRKFEM_BRD)
+ write_phy_reg(pi, 0x20d, 160);
+ else
+ write_phy_reg(pi, 0x20d, 184);
+
+ write_phy_reg(pi, 0x13a, 200);
+
+ write_phy_reg(pi, 0x70, 80);
+
+ write_phy_reg(pi, 0x1ff, 48);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 8)) {
+ wlc_phy_update_mimoconfig_nphy(pi, pi->n_preamble_override);
+ }
+
+ wlc_phy_stf_chain_upd_nphy(pi);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+ write_phy_reg(pi, 0x180, 0xaa8);
+ write_phy_reg(pi, 0x181, 0x9a4);
+ }
+
+ if (PHY_IPA(pi)) {
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (1) << 0);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x298 :
+ 0x29c, (0x1ff << 7),
+ (pi->nphy_papd_epsilon_offset[core]) << 7);
+
+ }
+
+ wlc_phy_ipa_set_tx_digi_filts_nphy(pi);
+ } else {
+
+ if (NREV_GE(pi->pubpi.phy_rev, 5)) {
+ wlc_phy_extpa_set_tx_digi_filts_nphy(pi);
+ }
+ }
+
+ wlc_phy_workarounds_nphy(pi);
+
+ wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
+
+ val = read_phy_reg(pi, 0x01);
+ write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
+ write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
+ wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
+
+ wlapi_bmac_macphyclk_set(pi->sh->physhim, ON);
+
+ wlc_phy_pa_override_nphy(pi, OFF);
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX);
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
+ wlc_phy_pa_override_nphy(pi, ON);
+
+ wlc_phy_classifier_nphy(pi, 0, 0);
+ wlc_phy_clip_det_nphy(pi, 0, clip1_ths);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec))
+ wlc_phy_bphy_init_nphy(pi);
+
+ tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
+ wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
+
+ wlc_phy_txpwr_fixpower_nphy(pi);
+
+ wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
+
+ wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ u32 *tx_pwrctrl_tbl = NULL;
+ u16 idx;
+ s16 pga_gn = 0;
+ s16 pad_gn = 0;
+ s32 rfpwr_offset = 0;
+
+ if (PHY_IPA(pi)) {
+ tx_pwrctrl_tbl = wlc_phy_get_ipa_gaintbl_nphy(pi);
+ } else {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if NREV_IS
+ (pi->pubpi.phy_rev, 3) {
+ tx_pwrctrl_tbl =
+ nphy_tpc_5GHz_txgain_rev3;
+ } else if NREV_IS
+ (pi->pubpi.phy_rev, 4) {
+ tx_pwrctrl_tbl =
+ (pi->srom_fem5g.extpagain == 3) ?
+ nphy_tpc_5GHz_txgain_HiPwrEPA :
+ nphy_tpc_5GHz_txgain_rev4;
+ } else {
+ tx_pwrctrl_tbl =
+ nphy_tpc_5GHz_txgain_rev5;
+ }
+
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (pi->pubpi.radiorev == 5) {
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_epa_2057rev5;
+ } else if (pi->pubpi.radiorev == 3) {
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_epa_2057rev3;
+ }
+
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 5) &&
+ (pi->srom_fem2g.extpagain == 3)) {
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_HiPwrEPA;
+ } else {
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_rev3;
+ }
+ }
+ }
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 128,
+ 192, 32, tx_pwrctrl_tbl);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128,
+ 192, 32, tx_pwrctrl_tbl);
+
+ pi->nphy_gmval = (u16) ((*tx_pwrctrl_tbl >> 16) & 0x7000);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ for (idx = 0; idx < 128; idx++) {
+ pga_gn = (tx_pwrctrl_tbl[idx] >> 24) & 0xf;
+ pad_gn = (tx_pwrctrl_tbl[idx] >> 19) & 0x1f;
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if ((pi->pubpi.radiorev == 3) ||
+ (pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+ rfpwr_offset = (s16)
+ nphy_papd_padgain_dlt_2g_2057rev3n4
+ [pad_gn];
+ } else if (pi->pubpi.radiorev == 5) {
+ rfpwr_offset = (s16)
+ nphy_papd_padgain_dlt_2g_2057rev5
+ [pad_gn];
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev ==
+ 8)) {
+ rfpwr_offset = (s16)
+ nphy_papd_padgain_dlt_2g_2057rev7
+ [pad_gn];
+ }
+ } else {
+ if ((pi->pubpi.radiorev == 3) ||
+ (pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+ rfpwr_offset = (s16)
+ nphy_papd_pgagain_dlt_5g_2057
+ [pga_gn];
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev ==
+ 8)) {
+ rfpwr_offset = (s16)
+ nphy_papd_pgagain_dlt_5g_2057rev7
+ [pga_gn];
+ }
+ }
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_CORE1TXPWRCTL,
+ 1, 576 + idx, 32,
+ &rfpwr_offset);
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_CORE2TXPWRCTL,
+ 1, 576 + idx, 32,
+ &rfpwr_offset);
+ }
+ } else {
+
+ for (idx = 0; idx < 128; idx++) {
+ pga_gn = (tx_pwrctrl_tbl[idx] >> 24) & 0xf;
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ rfpwr_offset = (s16)
+ nphy_papd_pga_gain_delta_ipa_2g
+ [pga_gn];
+ } else {
+ rfpwr_offset = (s16)
+ nphy_papd_pga_gain_delta_ipa_5g
+ [pga_gn];
+ }
+
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_CORE1TXPWRCTL,
+ 1, 576 + idx, 32,
+ &rfpwr_offset);
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_CORE2TXPWRCTL,
+ 1, 576 + idx, 32,
+ &rfpwr_offset);
+ }
+
+ }
+ } else {
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 128,
+ 192, 32, nphy_tpc_txgain);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128,
+ 192, 32, nphy_tpc_txgain);
+ }
+
+ if (pi->sh->phyrxchain != 0x3) {
+ wlc_phy_rxcore_setstate_nphy((wlc_phy_t *) pi,
+ pi->sh->phyrxchain);
+ }
+
+ if (PHY_PERICAL_MPHASE_PENDING(pi)) {
+ wlc_phy_cal_perical_mphase_restart(pi);
+ }
+
+ if (!NORADIO_ENAB(pi->pubpi)) {
+ bool do_rssi_cal = false;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ do_rssi_cal = (CHSPEC_IS2G(pi->radio_chanspec)) ?
+ (pi->nphy_rssical_chanspec_2G == 0) :
+ (pi->nphy_rssical_chanspec_5G == 0);
+
+ if (do_rssi_cal) {
+ wlc_phy_rssi_cal_nphy(pi);
+ } else {
+ wlc_phy_restore_rssical_nphy(pi);
+ }
+ } else {
+ wlc_phy_rssi_cal_nphy(pi);
+ }
+
+ if (!SCAN_RM_IN_PROGRESS(pi)) {
+ do_nphy_cal = (CHSPEC_IS2G(pi->radio_chanspec)) ?
+ (pi->nphy_iqcal_chanspec_2G == 0) :
+ (pi->nphy_iqcal_chanspec_5G == 0);
+ }
+
+ if (!pi->do_initcal)
+ do_nphy_cal = false;
+
+ if (do_nphy_cal) {
+
+ target_gain = wlc_phy_get_tx_gain_nphy(pi);
+
+ if (pi->antsel_type == ANTSEL_2x3)
+ wlc_phy_antsel_init((wlc_phy_t *) pi, true);
+
+ if (pi->nphy_perical != PHY_PERICAL_MPHASE) {
+ wlc_phy_rssi_cal_nphy(pi);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ pi->nphy_cal_orig_pwr_idx[0] =
+ pi->nphy_txpwrindex[PHY_CORE_0].
+ index_internal;
+ pi->nphy_cal_orig_pwr_idx[1] =
+ pi->nphy_txpwrindex[PHY_CORE_1].
+ index_internal;
+
+ wlc_phy_precal_txgain_nphy(pi);
+ target_gain =
+ wlc_phy_get_tx_gain_nphy(pi);
+ }
+
+ if (wlc_phy_cal_txiqlo_nphy
+ (pi, target_gain, true, false) == 0) {
+ if (wlc_phy_cal_rxiq_nphy
+ (pi, target_gain, 2,
+ false) == 0) {
+ wlc_phy_savecal_nphy(pi);
+
+ }
+ }
+ } else if (pi->mphase_cal_phase_id ==
+ MPHASE_CAL_STATE_IDLE) {
+
+ wlc_phy_cal_perical((wlc_phy_t *) pi,
+ PHY_PERICAL_PHYINIT);
+ }
+ } else {
+ wlc_phy_restorecal_nphy(pi);
+ }
+ }
+
+ wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
+
+ wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
+
+ wlc_phy_nphy_tkip_rifs_war(pi, pi->sh->_rifs_phy);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LE(pi->pubpi.phy_rev, 6))
+
+ write_phy_reg(pi, 0x70, 50);
+
+ wlc_phy_txlpfbw_nphy(pi);
+
+ wlc_phy_spurwar_nphy(pi);
+
+}
+
+static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, s32 preamble)
+{
+ bool gf_preamble = false;
+ u16 val;
+
+ if (preamble == WLC_N_PREAMBLE_GF) {
+ gf_preamble = true;
+ }
+
+ val = read_phy_reg(pi, 0xed);
+
+ val |= RX_GF_MM_AUTO;
+ val &= ~RX_GF_OR_MM;
+ if (gf_preamble)
+ val |= RX_GF_OR_MM;
+
+ write_phy_reg(pi, 0xed, val);
+}
+
+static void wlc_phy_resetcca_nphy(phy_info_t *pi)
+{
+ u16 val;
+
+ wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
+
+ val = read_phy_reg(pi, 0x01);
+ write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
+ udelay(1);
+ write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
+
+ wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
+
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
+}
+
+void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en)
+{
+ u16 rfctrlintc_override_val;
+
+ if (!en) {
+
+ pi->rfctrlIntc1_save = read_phy_reg(pi, 0x91);
+ pi->rfctrlIntc2_save = read_phy_reg(pi, 0x92);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ rfctrlintc_override_val = 0x1480;
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ rfctrlintc_override_val =
+ CHSPEC_IS5G(pi->radio_chanspec) ? 0x600 : 0x480;
+ } else {
+ rfctrlintc_override_val =
+ CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120;
+ }
+
+ write_phy_reg(pi, 0x91, rfctrlintc_override_val);
+ write_phy_reg(pi, 0x92, rfctrlintc_override_val);
+ } else {
+
+ write_phy_reg(pi, 0x91, pi->rfctrlIntc1_save);
+ write_phy_reg(pi, 0x92, pi->rfctrlIntc2_save);
+ }
+
+}
+
+void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi)
+{
+
+ u16 txrx_chain =
+ (NPHY_RfseqCoreActv_TxRxChain0 | NPHY_RfseqCoreActv_TxRxChain1);
+ bool CoreActv_override = false;
+
+ if (pi->nphy_txrx_chain == WLC_N_TXRX_CHAIN0) {
+ txrx_chain = NPHY_RfseqCoreActv_TxRxChain0;
+ CoreActv_override = true;
+
+ if (NREV_LE(pi->pubpi.phy_rev, 2)) {
+ and_phy_reg(pi, 0xa0, ~0x20);
+ }
+ } else if (pi->nphy_txrx_chain == WLC_N_TXRX_CHAIN1) {
+ txrx_chain = NPHY_RfseqCoreActv_TxRxChain1;
+ CoreActv_override = true;
+
+ if (NREV_LE(pi->pubpi.phy_rev, 2)) {
+ or_phy_reg(pi, 0xa0, 0x20);
+ }
+ }
+
+ mod_phy_reg(pi, 0xa2, ((0xf << 0) | (0xf << 4)), txrx_chain);
+
+ if (CoreActv_override) {
+
+ pi->nphy_perical = PHY_PERICAL_DISABLE;
+ or_phy_reg(pi, 0xa1, NPHY_RfseqMode_CoreActv_override);
+ } else {
+ pi->nphy_perical = PHY_PERICAL_MPHASE;
+ and_phy_reg(pi, 0xa1, ~NPHY_RfseqMode_CoreActv_override);
+ }
+}
+
+void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask)
+{
+ u16 regval;
+ u16 tbl_buf[16];
+ uint i;
+ phy_info_t *pi = (phy_info_t *) pih;
+ u16 tbl_opcode;
+ bool suspend;
+
+ pi->sh->phyrxchain = rxcore_bitmask;
+
+ if (!pi->sh->clk)
+ return;
+
+ suspend =
+ (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!suspend)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ regval = read_phy_reg(pi, 0xa2);
+ regval &= ~(0xf << 4);
+ regval |= ((u16) (rxcore_bitmask & 0x3)) << 4;
+ write_phy_reg(pi, 0xa2, regval);
+
+ if ((rxcore_bitmask & 0x3) != 0x3) {
+
+ write_phy_reg(pi, 0x20e, 1);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (pi->rx2tx_biasentry == -1) {
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ ARRAY_SIZE(tbl_buf), 80,
+ 16, tbl_buf);
+
+ for (i = 0; i < ARRAY_SIZE(tbl_buf); i++) {
+ if (tbl_buf[i] ==
+ NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS) {
+
+ pi->rx2tx_biasentry = (u8) i;
+ tbl_opcode =
+ NPHY_REV3_RFSEQ_CMD_NOP;
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_RFSEQ,
+ 1, i,
+ 16,
+ &tbl_opcode);
+ break;
+ } else if (tbl_buf[i] ==
+ NPHY_REV3_RFSEQ_CMD_END) {
+ break;
+ }
+ }
+ }
+ }
+ } else {
+
+ write_phy_reg(pi, 0x20e, 30);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (pi->rx2tx_biasentry != -1) {
+ tbl_opcode = NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1, pi->rx2tx_biasentry,
+ 16, &tbl_opcode);
+ pi->rx2tx_biasentry = -1;
+ }
+ }
+ }
+
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+
+ if (!suspend)
+ wlapi_enable_mac(pi->sh->physhim);
+}
+
+u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih)
+{
+ u16 regval, rxen_bits;
+ phy_info_t *pi = (phy_info_t *) pih;
+
+ regval = read_phy_reg(pi, 0xa2);
+ rxen_bits = (regval >> 4) & 0xf;
+
+ return (u8) rxen_bits;
+}
+
+bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pi)
+{
+ return PHY_IPA(pi);
+}
+
+static void wlc_phy_txpwr_limit_to_tbl_nphy(phy_info_t *pi)
+{
+ u8 idx, idx2, i, delta_ind;
+
+ for (idx = TXP_FIRST_CCK; idx <= TXP_LAST_CCK; idx++) {
+ pi->adj_pwr_tbl_nphy[idx] = pi->tx_power_offset[idx];
+ }
+
+ for (i = 0; i < 4; i++) {
+ idx2 = 0;
+
+ delta_ind = 0;
+
+ switch (i) {
+ case 0:
+
+ if (CHSPEC_IS40(pi->radio_chanspec)
+ && NPHY_IS_SROM_REINTERPRET) {
+ idx = TXP_FIRST_MCS_40_SISO;
+ } else {
+ idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
+ TXP_FIRST_OFDM_40_SISO : TXP_FIRST_OFDM;
+ delta_ind = 1;
+ }
+ break;
+
+ case 1:
+
+ idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
+ TXP_FIRST_MCS_40_CDD : TXP_FIRST_MCS_20_CDD;
+ break;
+
+ case 2:
+
+ idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
+ TXP_FIRST_MCS_40_STBC : TXP_FIRST_MCS_20_STBC;
+ break;
+
+ case 3:
+
+ idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
+ TXP_FIRST_MCS_40_SDM : TXP_FIRST_MCS_20_SDM;
+ break;
+ }
+
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ idx = idx + delta_ind;
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx++];
+
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx++];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx++];
+
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx++];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx++];
+
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx++];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ idx = idx + 1 - delta_ind;
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
+ pi->tx_power_offset[idx];
+ }
+}
+
+void wlc_phy_cal_init_nphy(phy_info_t *pi)
+{
+}
+
+static void wlc_phy_war_force_trsw_to_R_cliplo_nphy(phy_info_t *pi, u8 core)
+{
+ if (core == PHY_CORE_0) {
+ write_phy_reg(pi, 0x38, 0x4);
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ write_phy_reg(pi, 0x37, 0x0060);
+ } else {
+ write_phy_reg(pi, 0x37, 0x1080);
+ }
+ } else if (core == PHY_CORE_1) {
+ write_phy_reg(pi, 0x2ae, 0x4);
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ write_phy_reg(pi, 0x2ad, 0x0060);
+ } else {
+ write_phy_reg(pi, 0x2ad, 0x1080);
+ }
+ }
+}
+
+static void wlc_phy_war_txchain_upd_nphy(phy_info_t *pi, u8 txchain)
+{
+ u8 txchain0, txchain1;
+
+ txchain0 = txchain & 0x1;
+ txchain1 = (txchain & 0x2) >> 1;
+ if (!txchain0) {
+ wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_0);
+ }
+
+ if (!txchain1) {
+ wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_1);
+ }
+}
+
+static void wlc_phy_workarounds_nphy(phy_info_t *pi)
+{
+ u8 rfseq_rx2tx_events[] = {
+ NPHY_RFSEQ_CMD_NOP,
+ NPHY_RFSEQ_CMD_RXG_FBW,
+ NPHY_RFSEQ_CMD_TR_SWITCH,
+ NPHY_RFSEQ_CMD_CLR_HIQ_DIS,
+ NPHY_RFSEQ_CMD_RXPD_TXPD,
+ NPHY_RFSEQ_CMD_TX_GAIN,
+ NPHY_RFSEQ_CMD_EXT_PA
+ };
+ u8 rfseq_rx2tx_dlys[] = { 8, 6, 6, 2, 4, 60, 1 };
+ u8 rfseq_tx2rx_events[] = {
+ NPHY_RFSEQ_CMD_NOP,
+ NPHY_RFSEQ_CMD_EXT_PA,
+ NPHY_RFSEQ_CMD_TX_GAIN,
+ NPHY_RFSEQ_CMD_RXPD_TXPD,
+ NPHY_RFSEQ_CMD_TR_SWITCH,
+ NPHY_RFSEQ_CMD_RXG_FBW,
+ NPHY_RFSEQ_CMD_CLR_HIQ_DIS
+ };
+ u8 rfseq_tx2rx_dlys[] = { 8, 6, 2, 4, 4, 6, 1 };
+ u8 rfseq_tx2rx_events_rev3[] = {
+ NPHY_REV3_RFSEQ_CMD_EXT_PA,
+ NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
+ NPHY_REV3_RFSEQ_CMD_TX_GAIN,
+ NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
+ NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
+ NPHY_REV3_RFSEQ_CMD_RXG_FBW,
+ NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
+ NPHY_REV3_RFSEQ_CMD_END
+ };
+ u8 rfseq_tx2rx_dlys_rev3[] = { 8, 4, 2, 2, 4, 4, 6, 1 };
+ u8 rfseq_rx2tx_events_rev3[] = {
+ NPHY_REV3_RFSEQ_CMD_NOP,
+ NPHY_REV3_RFSEQ_CMD_RXG_FBW,
+ NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
+ NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
+ NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
+ NPHY_REV3_RFSEQ_CMD_TX_GAIN,
+ NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
+ NPHY_REV3_RFSEQ_CMD_EXT_PA,
+ NPHY_REV3_RFSEQ_CMD_END
+ };
+ u8 rfseq_rx2tx_dlys_rev3[] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
+
+ u8 rfseq_rx2tx_events_rev3_ipa[] = {
+ NPHY_REV3_RFSEQ_CMD_NOP,
+ NPHY_REV3_RFSEQ_CMD_RXG_FBW,
+ NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
+ NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
+ NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
+ NPHY_REV3_RFSEQ_CMD_TX_GAIN,
+ NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS,
+ NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
+ NPHY_REV3_RFSEQ_CMD_END
+ };
+ u8 rfseq_rx2tx_dlys_rev3_ipa[] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
+ u16 rfseq_rx2tx_dacbufpu_rev7[] = { 0x10f, 0x10f };
+
+ s16 alpha0, alpha1, alpha2;
+ s16 beta0, beta1, beta2;
+ u32 leg_data_weights, ht_data_weights, nss1_data_weights,
+ stbc_data_weights;
+ u8 chan_freq_range = 0;
+ u16 dac_control = 0x0002;
+ u16 aux_adc_vmid_rev7_core0[] = { 0x8e, 0x96, 0x96, 0x96 };
+ u16 aux_adc_vmid_rev7_core1[] = { 0x8f, 0x9f, 0x9f, 0x96 };
+ u16 aux_adc_vmid_rev4[] = { 0xa2, 0xb4, 0xb4, 0x89 };
+ u16 aux_adc_vmid_rev3[] = { 0xa2, 0xb4, 0xb4, 0x89 };
+ u16 *aux_adc_vmid;
+ u16 aux_adc_gain_rev7[] = { 0x02, 0x02, 0x02, 0x02 };
+ u16 aux_adc_gain_rev4[] = { 0x02, 0x02, 0x02, 0x00 };
+ u16 aux_adc_gain_rev3[] = { 0x02, 0x02, 0x02, 0x00 };
+ u16 *aux_adc_gain;
+ u16 sk_adc_vmid[] = { 0xb4, 0xb4, 0xb4, 0x24 };
+ u16 sk_adc_gain[] = { 0x02, 0x02, 0x02, 0x02 };
+ s32 min_nvar_val = 0x18d;
+ s32 min_nvar_offset_6mbps = 20;
+ u8 pdetrange;
+ u8 triso;
+ u16 regval;
+ u16 afectrl_adc_ctrl1_rev7 = 0x20;
+ u16 afectrl_adc_ctrl2_rev7 = 0x0;
+ u16 rfseq_rx2tx_lpf_h_hpc_rev7 = 0x77;
+ u16 rfseq_tx2rx_lpf_h_hpc_rev7 = 0x77;
+ u16 rfseq_pktgn_lpf_h_hpc_rev7 = 0x77;
+ u16 rfseq_htpktgn_lpf_hpc_rev7[] = { 0x77, 0x11, 0x11 };
+ u16 rfseq_pktgn_lpf_hpc_rev7[] = { 0x11, 0x11 };
+ u16 rfseq_cckpktgn_lpf_hpc_rev7[] = { 0x11, 0x11 };
+ u16 ipalvlshift_3p3_war_en = 0;
+ u16 rccal_bcap_val, rccal_scap_val;
+ u16 rccal_tx20_11b_bcap = 0;
+ u16 rccal_tx20_11b_scap = 0;
+ u16 rccal_tx20_11n_bcap = 0;
+ u16 rccal_tx20_11n_scap = 0;
+ u16 rccal_tx40_11n_bcap = 0;
+ u16 rccal_tx40_11n_scap = 0;
+ u16 rx2tx_lpf_rc_lut_tx20_11b = 0;
+ u16 rx2tx_lpf_rc_lut_tx20_11n = 0;
+ u16 rx2tx_lpf_rc_lut_tx40_11n = 0;
+ u16 tx_lpf_bw_ofdm_20mhz = 0;
+ u16 tx_lpf_bw_ofdm_40mhz = 0;
+ u16 tx_lpf_bw_11b = 0;
+ u16 ipa2g_mainbias, ipa2g_casconv, ipa2g_biasfilt;
+ u16 txgm_idac_bleed = 0;
+ bool rccal_ovrd = false;
+ u16 freq;
+ int coreNum;
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_cck_en, 0);
+ } else {
+ wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_cck_en, 1);
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ if (!ISSIM_ENAB(pi->sh->sih)) {
+ or_phy_reg(pi, 0xb1, NPHY_IQFlip_ADC1 | NPHY_IQFlip_ADC2);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)) {
+ mod_phy_reg(pi, 0x221, (0x1 << 4), (1 << 4));
+
+ mod_phy_reg(pi, 0x160, (0x7f << 0), (32 << 0));
+ mod_phy_reg(pi, 0x160, (0x7f << 8), (39 << 8));
+ mod_phy_reg(pi, 0x161, (0x7f << 0), (46 << 0));
+ mod_phy_reg(pi, 0x161, (0x7f << 8), (51 << 8));
+ mod_phy_reg(pi, 0x162, (0x7f << 0), (55 << 0));
+ mod_phy_reg(pi, 0x162, (0x7f << 8), (58 << 8));
+ mod_phy_reg(pi, 0x163, (0x7f << 0), (60 << 0));
+ mod_phy_reg(pi, 0x163, (0x7f << 8), (62 << 8));
+ mod_phy_reg(pi, 0x164, (0x7f << 0), (62 << 0));
+ mod_phy_reg(pi, 0x164, (0x7f << 8), (63 << 8));
+ mod_phy_reg(pi, 0x165, (0x7f << 0), (63 << 0));
+ mod_phy_reg(pi, 0x165, (0x7f << 8), (64 << 8));
+ mod_phy_reg(pi, 0x166, (0x7f << 0), (64 << 0));
+ mod_phy_reg(pi, 0x166, (0x7f << 8), (64 << 8));
+ mod_phy_reg(pi, 0x167, (0x7f << 0), (64 << 0));
+ mod_phy_reg(pi, 0x167, (0x7f << 8), (64 << 8));
+ }
+
+ if (NREV_LE(pi->pubpi.phy_rev, 8)) {
+ write_phy_reg(pi, 0x23f, 0x1b0);
+ write_phy_reg(pi, 0x240, 0x1b0);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 8)) {
+ mod_phy_reg(pi, 0xbd, (0xff << 0), (114 << 0));
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x00, 16,
+ &dac_control);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x10, 16,
+ &dac_control);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
+ 1, 0, 32, &leg_data_weights);
+ leg_data_weights = leg_data_weights & 0xffffff;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
+ 1, 0, 32, &leg_data_weights);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 2, 0x15e, 16,
+ rfseq_rx2tx_dacbufpu_rev7);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x16e, 16,
+ rfseq_rx2tx_dacbufpu_rev7);
+
+ if (PHY_IPA(pi)) {
+ wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
+ rfseq_rx2tx_events_rev3_ipa,
+ rfseq_rx2tx_dlys_rev3_ipa,
+ sizeof
+ (rfseq_rx2tx_events_rev3_ipa) /
+ sizeof
+ (rfseq_rx2tx_events_rev3_ipa
+ [0]));
+ }
+
+ mod_phy_reg(pi, 0x299, (0x3 << 14), (0x1 << 14));
+ mod_phy_reg(pi, 0x29d, (0x3 << 14), (0x1 << 14));
+
+ tx_lpf_bw_ofdm_20mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x154);
+ tx_lpf_bw_ofdm_40mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x159);
+ tx_lpf_bw_11b = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x152);
+
+ if (PHY_IPA(pi)) {
+
+ if (((pi->pubpi.radiorev == 5)
+ && (CHSPEC_IS40(pi->radio_chanspec) == 1))
+ || (pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ rccal_bcap_val =
+ read_radio_reg(pi,
+ RADIO_2057_RCCAL_BCAP_VAL);
+ rccal_scap_val =
+ read_radio_reg(pi,
+ RADIO_2057_RCCAL_SCAP_VAL);
+
+ rccal_tx20_11b_bcap = rccal_bcap_val;
+ rccal_tx20_11b_scap = rccal_scap_val;
+
+ if ((pi->pubpi.radiorev == 5) &&
+ (CHSPEC_IS40(pi->radio_chanspec) == 1)) {
+
+ rccal_tx20_11n_bcap = rccal_bcap_val;
+ rccal_tx20_11n_scap = rccal_scap_val;
+ rccal_tx40_11n_bcap = 0xc;
+ rccal_tx40_11n_scap = 0xc;
+
+ rccal_ovrd = true;
+
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ tx_lpf_bw_ofdm_20mhz = 4;
+ tx_lpf_bw_11b = 1;
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ rccal_tx20_11n_bcap = 0xc;
+ rccal_tx20_11n_scap = 0xc;
+ rccal_tx40_11n_bcap = 0xa;
+ rccal_tx40_11n_scap = 0xa;
+ } else {
+ rccal_tx20_11n_bcap = 0x14;
+ rccal_tx20_11n_scap = 0x14;
+ rccal_tx40_11n_bcap = 0xf;
+ rccal_tx40_11n_scap = 0xf;
+ }
+
+ rccal_ovrd = true;
+ }
+ }
+
+ } else {
+
+ if (pi->pubpi.radiorev == 5) {
+
+ tx_lpf_bw_ofdm_20mhz = 1;
+ tx_lpf_bw_ofdm_40mhz = 3;
+
+ rccal_bcap_val =
+ read_radio_reg(pi,
+ RADIO_2057_RCCAL_BCAP_VAL);
+ rccal_scap_val =
+ read_radio_reg(pi,
+ RADIO_2057_RCCAL_SCAP_VAL);
+
+ rccal_tx20_11b_bcap = rccal_bcap_val;
+ rccal_tx20_11b_scap = rccal_scap_val;
+
+ rccal_tx20_11n_bcap = 0x13;
+ rccal_tx20_11n_scap = 0x11;
+ rccal_tx40_11n_bcap = 0x13;
+ rccal_tx40_11n_scap = 0x11;
+
+ rccal_ovrd = true;
+ }
+ }
+
+ if (rccal_ovrd) {
+
+ rx2tx_lpf_rc_lut_tx20_11b = (rccal_tx20_11b_bcap << 8) |
+ (rccal_tx20_11b_scap << 3) | tx_lpf_bw_11b;
+ rx2tx_lpf_rc_lut_tx20_11n = (rccal_tx20_11n_bcap << 8) |
+ (rccal_tx20_11n_scap << 3) | tx_lpf_bw_ofdm_20mhz;
+ rx2tx_lpf_rc_lut_tx40_11n = (rccal_tx40_11n_bcap << 8) |
+ (rccal_tx40_11n_scap << 3) | tx_lpf_bw_ofdm_40mhz;
+
+ for (coreNum = 0; coreNum <= 1; coreNum++) {
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1,
+ 0x152 + coreNum * 0x10,
+ 16,
+ &rx2tx_lpf_rc_lut_tx20_11b);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1,
+ 0x153 + coreNum * 0x10,
+ 16,
+ &rx2tx_lpf_rc_lut_tx20_11n);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1,
+ 0x154 + coreNum * 0x10,
+ 16,
+ &rx2tx_lpf_rc_lut_tx20_11n);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1,
+ 0x155 + coreNum * 0x10,
+ 16,
+ &rx2tx_lpf_rc_lut_tx40_11n);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1,
+ 0x156 + coreNum * 0x10,
+ 16,
+ &rx2tx_lpf_rc_lut_tx40_11n);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1,
+ 0x157 + coreNum * 0x10,
+ 16,
+ &rx2tx_lpf_rc_lut_tx40_11n);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1,
+ 0x158 + coreNum * 0x10,
+ 16,
+ &rx2tx_lpf_rc_lut_tx40_11n);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 1,
+ 0x159 + coreNum * 0x10,
+ 16,
+ &rx2tx_lpf_rc_lut_tx40_11n);
+ }
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4),
+ 1, 0x3, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ }
+
+ if (!NORADIO_ENAB(pi->pubpi)) {
+ write_phy_reg(pi, 0x32f, 0x3);
+ }
+
+ if ((pi->pubpi.radiorev == 4) || (pi->pubpi.radiorev == 6)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
+ 1, 0x3, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ }
+
+ if ((pi->pubpi.radiorev == 3) || (pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+ if ((pi->sh->sromrev >= 8)
+ && (pi->sh->boardflags2 & BFL2_IPALVLSHIFT_3P3))
+ ipalvlshift_3p3_war_en = 1;
+
+ if (ipalvlshift_3p3_war_en) {
+ write_radio_reg(pi, RADIO_2057_GPAIO_CONFIG,
+ 0x5);
+ write_radio_reg(pi, RADIO_2057_GPAIO_SEL1,
+ 0x30);
+ write_radio_reg(pi, RADIO_2057_GPAIO_SEL0, 0x0);
+ or_radio_reg(pi,
+ RADIO_2057_RXTXBIAS_CONFIG_CORE0,
+ 0x1);
+ or_radio_reg(pi,
+ RADIO_2057_RXTXBIAS_CONFIG_CORE1,
+ 0x1);
+
+ ipa2g_mainbias = 0x1f;
+
+ ipa2g_casconv = 0x6f;
+
+ ipa2g_biasfilt = 0xaa;
+ } else {
+
+ ipa2g_mainbias = 0x2b;
+
+ ipa2g_casconv = 0x7f;
+
+ ipa2g_biasfilt = 0xee;
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ for (coreNum = 0; coreNum <= 1; coreNum++) {
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
+ coreNum, IPA2G_IMAIN,
+ ipa2g_mainbias);
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
+ coreNum, IPA2G_CASCONV,
+ ipa2g_casconv);
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
+ coreNum,
+ IPA2G_BIAS_FILTER,
+ ipa2g_biasfilt);
+ }
+ }
+ }
+
+ if (PHY_IPA(pi)) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if ((pi->pubpi.radiorev == 3)
+ || (pi->pubpi.radiorev == 4)
+ || (pi->pubpi.radiorev == 6)) {
+
+ txgm_idac_bleed = 0x7f;
+ }
+
+ for (coreNum = 0; coreNum <= 1; coreNum++) {
+ if (txgm_idac_bleed != 0)
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, coreNum,
+ TXGM_IDAC_BLEED,
+ txgm_idac_bleed);
+ }
+
+ if (pi->pubpi.radiorev == 5) {
+
+ for (coreNum = 0; coreNum <= 1;
+ coreNum++) {
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, coreNum,
+ IPA2G_CASCONV,
+ 0x13);
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, coreNum,
+ IPA2G_IMAIN,
+ 0x1f);
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, coreNum,
+ IPA2G_BIAS_FILTER,
+ 0xee);
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, coreNum,
+ PAD2G_IDACS,
+ 0x8a);
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, coreNum,
+ PAD_BIAS_FILTER_BWS,
+ 0x3e);
+ }
+
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ if (CHSPEC_IS40(pi->radio_chanspec) ==
+ 0) {
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, 0,
+ IPA2G_IMAIN,
+ 0x14);
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, 1,
+ IPA2G_IMAIN,
+ 0x12);
+ } else {
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, 0,
+ IPA2G_IMAIN,
+ 0x16);
+ WRITE_RADIO_REG4(pi, RADIO_2057,
+ CORE, 1,
+ IPA2G_IMAIN,
+ 0x16);
+ }
+ }
+
+ } else {
+ freq =
+ CHAN5G_FREQ(CHSPEC_CHANNEL
+ (pi->radio_chanspec));
+ if (((freq >= 5180) && (freq <= 5230))
+ || ((freq >= 5745) && (freq <= 5805))) {
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
+ 0, IPA5G_BIAS_FILTER,
+ 0xff);
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
+ 1, IPA5G_BIAS_FILTER,
+ 0xff);
+ }
+ }
+ } else {
+
+ if (pi->pubpi.radiorev != 5) {
+ for (coreNum = 0; coreNum <= 1; coreNum++) {
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
+ coreNum,
+ TXMIX2G_TUNE_BOOST_PU,
+ 0x61);
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
+ coreNum,
+ TXGM_IDAC_BLEED, 0x70);
+ }
+ }
+ }
+
+ if (pi->pubpi.radiorev == 4) {
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
+ 0x05, 16,
+ &afectrl_adc_ctrl1_rev7);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
+ 0x15, 16,
+ &afectrl_adc_ctrl1_rev7);
+
+ for (coreNum = 0; coreNum <= 1; coreNum++) {
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
+ AFE_VCM_CAL_MASTER, 0x0);
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
+ AFE_SET_VCM_I, 0x3f);
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
+ AFE_SET_VCM_Q, 0x3f);
+ }
+ } else {
+ mod_phy_reg(pi, 0xa6, (0x1 << 2), (0x1 << 2));
+ mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
+ mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
+ mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
+
+ mod_phy_reg(pi, 0xa6, (0x1 << 0), 0);
+ mod_phy_reg(pi, 0x8f, (0x1 << 0), (0x1 << 0));
+ mod_phy_reg(pi, 0xa7, (0x1 << 0), 0);
+ mod_phy_reg(pi, 0xa5, (0x1 << 0), (0x1 << 0));
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
+ 0x05, 16,
+ &afectrl_adc_ctrl2_rev7);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
+ 0x15, 16,
+ &afectrl_adc_ctrl2_rev7);
+
+ mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
+ mod_phy_reg(pi, 0x8f, (0x1 << 2), 0);
+ mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
+ mod_phy_reg(pi, 0xa5, (0x1 << 2), 0);
+ }
+
+ write_phy_reg(pi, 0x6a, 0x2);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 256, 32,
+ &min_nvar_offset_6mbps);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x138, 16,
+ &rfseq_pktgn_lpf_hpc_rev7);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x141, 16,
+ &rfseq_pktgn_lpf_h_hpc_rev7);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 3, 0x133, 16,
+ &rfseq_htpktgn_lpf_hpc_rev7);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x146, 16,
+ &rfseq_cckpktgn_lpf_hpc_rev7);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x123, 16,
+ &rfseq_tx2rx_lpf_h_hpc_rev7);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x12A, 16,
+ &rfseq_rx2tx_lpf_h_hpc_rev7);
+
+ if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
+ 32, &min_nvar_val);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
+ 127, 32, &min_nvar_val);
+ } else {
+ min_nvar_val = noise_var_tbl_rev7[3];
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
+ 32, &min_nvar_val);
+
+ min_nvar_val = noise_var_tbl_rev7[127];
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
+ 127, 32, &min_nvar_val);
+ }
+
+ wlc_phy_workarounds_nphy_gainctrl(pi);
+
+ pdetrange =
+ (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
+ pdetrange : pi->srom_fem2g.pdetrange;
+
+ if (pdetrange == 0) {
+ chan_freq_range =
+ wlc_phy_get_chan_freq_range_nphy(pi, 0);
+ if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
+ aux_adc_vmid_rev7_core0[3] = 0x70;
+ aux_adc_vmid_rev7_core1[3] = 0x70;
+ aux_adc_gain_rev7[3] = 2;
+ } else {
+ aux_adc_vmid_rev7_core0[3] = 0x80;
+ aux_adc_vmid_rev7_core1[3] = 0x80;
+ aux_adc_gain_rev7[3] = 3;
+ }
+ } else if (pdetrange == 1) {
+ if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
+ aux_adc_vmid_rev7_core0[3] = 0x7c;
+ aux_adc_vmid_rev7_core1[3] = 0x7c;
+ aux_adc_gain_rev7[3] = 2;
+ } else {
+ aux_adc_vmid_rev7_core0[3] = 0x8c;
+ aux_adc_vmid_rev7_core1[3] = 0x8c;
+ aux_adc_gain_rev7[3] = 1;
+ }
+ } else if (pdetrange == 2) {
+ if (pi->pubpi.radioid == BCM2057_ID) {
+ if ((pi->pubpi.radiorev == 5)
+ || (pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+ if (chan_freq_range ==
+ WL_CHAN_FREQ_RANGE_2G) {
+ aux_adc_vmid_rev7_core0[3] =
+ 0x8c;
+ aux_adc_vmid_rev7_core1[3] =
+ 0x8c;
+ aux_adc_gain_rev7[3] = 0;
+ } else {
+ aux_adc_vmid_rev7_core0[3] =
+ 0x96;
+ aux_adc_vmid_rev7_core1[3] =
+ 0x96;
+ aux_adc_gain_rev7[3] = 0;
+ }
+ }
+ }
+
+ } else if (pdetrange == 3) {
+ if (chan_freq_range == WL_CHAN_FREQ_RANGE_2G) {
+ aux_adc_vmid_rev7_core0[3] = 0x89;
+ aux_adc_vmid_rev7_core1[3] = 0x89;
+ aux_adc_gain_rev7[3] = 0;
+ }
+
+ } else if (pdetrange == 5) {
+
+ if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
+ aux_adc_vmid_rev7_core0[3] = 0x80;
+ aux_adc_vmid_rev7_core1[3] = 0x80;
+ aux_adc_gain_rev7[3] = 3;
+ } else {
+ aux_adc_vmid_rev7_core0[3] = 0x70;
+ aux_adc_vmid_rev7_core1[3] = 0x70;
+ aux_adc_gain_rev7[3] = 2;
+ }
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x08, 16,
+ &aux_adc_vmid_rev7_core0);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x18, 16,
+ &aux_adc_vmid_rev7_core1);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x0c, 16,
+ &aux_adc_gain_rev7);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x1c, 16,
+ &aux_adc_gain_rev7);
+
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ write_phy_reg(pi, 0x23f, 0x1f8);
+ write_phy_reg(pi, 0x240, 0x1f8);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
+ 1, 0, 32, &leg_data_weights);
+ leg_data_weights = leg_data_weights & 0xffffff;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
+ 1, 0, 32, &leg_data_weights);
+
+ alpha0 = 293;
+ alpha1 = 435;
+ alpha2 = 261;
+ beta0 = 366;
+ beta1 = 205;
+ beta2 = 32;
+ write_phy_reg(pi, 0x145, alpha0);
+ write_phy_reg(pi, 0x146, alpha1);
+ write_phy_reg(pi, 0x147, alpha2);
+ write_phy_reg(pi, 0x148, beta0);
+ write_phy_reg(pi, 0x149, beta1);
+ write_phy_reg(pi, 0x14a, beta2);
+
+ write_phy_reg(pi, 0x38, 0xC);
+ write_phy_reg(pi, 0x2ae, 0xC);
+
+ wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_TX2RX,
+ rfseq_tx2rx_events_rev3,
+ rfseq_tx2rx_dlys_rev3,
+ sizeof(rfseq_tx2rx_events_rev3) /
+ sizeof(rfseq_tx2rx_events_rev3[0]));
+
+ if (PHY_IPA(pi)) {
+ wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
+ rfseq_rx2tx_events_rev3_ipa,
+ rfseq_rx2tx_dlys_rev3_ipa,
+ sizeof
+ (rfseq_rx2tx_events_rev3_ipa) /
+ sizeof
+ (rfseq_rx2tx_events_rev3_ipa
+ [0]));
+ }
+
+ if ((pi->sh->hw_phyrxchain != 0x3) &&
+ (pi->sh->hw_phyrxchain != pi->sh->hw_phytxchain)) {
+
+ if (PHY_IPA(pi)) {
+ rfseq_rx2tx_dlys_rev3[5] = 59;
+ rfseq_rx2tx_dlys_rev3[6] = 1;
+ rfseq_rx2tx_events_rev3[7] =
+ NPHY_REV3_RFSEQ_CMD_END;
+ }
+
+ wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
+ rfseq_rx2tx_events_rev3,
+ rfseq_rx2tx_dlys_rev3,
+ sizeof(rfseq_rx2tx_events_rev3) /
+ sizeof(rfseq_rx2tx_events_rev3
+ [0]));
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ write_phy_reg(pi, 0x6a, 0x2);
+ } else {
+ write_phy_reg(pi, 0x6a, 0x9c40);
+ }
+
+ mod_phy_reg(pi, 0x294, (0xf << 8), (7 << 8));
+
+ if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
+ 32, &min_nvar_val);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
+ 127, 32, &min_nvar_val);
+ } else {
+ min_nvar_val = noise_var_tbl_rev3[3];
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
+ 32, &min_nvar_val);
+
+ min_nvar_val = noise_var_tbl_rev3[127];
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
+ 127, 32, &min_nvar_val);
+ }
+
+ wlc_phy_workarounds_nphy_gainctrl(pi);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x00, 16,
+ &dac_control);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x10, 16,
+ &dac_control);
+
+ pdetrange =
+ (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
+ pdetrange : pi->srom_fem2g.pdetrange;
+
+ if (pdetrange == 0) {
+ if (NREV_GE(pi->pubpi.phy_rev, 4)) {
+ aux_adc_vmid = aux_adc_vmid_rev4;
+ aux_adc_gain = aux_adc_gain_rev4;
+ } else {
+ aux_adc_vmid = aux_adc_vmid_rev3;
+ aux_adc_gain = aux_adc_gain_rev3;
+ }
+ chan_freq_range =
+ wlc_phy_get_chan_freq_range_nphy(pi, 0);
+ if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
+ switch (chan_freq_range) {
+ case WL_CHAN_FREQ_RANGE_5GL:
+ aux_adc_vmid[3] = 0x89;
+ aux_adc_gain[3] = 0;
+ break;
+ case WL_CHAN_FREQ_RANGE_5GM:
+ aux_adc_vmid[3] = 0x89;
+ aux_adc_gain[3] = 0;
+ break;
+ case WL_CHAN_FREQ_RANGE_5GH:
+ aux_adc_vmid[3] = 0x89;
+ aux_adc_gain[3] = 0;
+ break;
+ default:
+ break;
+ }
+ }
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x08, 16, aux_adc_vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x18, 16, aux_adc_vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x0c, 16, aux_adc_gain);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x1c, 16, aux_adc_gain);
+ } else if (pdetrange == 1) {
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x08, 16, sk_adc_vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x18, 16, sk_adc_vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x0c, 16, sk_adc_gain);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x1c, 16, sk_adc_gain);
+ } else if (pdetrange == 2) {
+
+ u16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x74 };
+ u16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x04 };
+
+ if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+ chan_freq_range =
+ wlc_phy_get_chan_freq_range_nphy(pi, 0);
+ if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
+ bcm_adc_vmid[3] = 0x8e;
+ bcm_adc_gain[3] = 0x03;
+ } else {
+ bcm_adc_vmid[3] = 0x94;
+ bcm_adc_gain[3] = 0x03;
+ }
+ } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+ bcm_adc_vmid[3] = 0x84;
+ bcm_adc_gain[3] = 0x02;
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x08, 16, bcm_adc_vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x18, 16, bcm_adc_vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x0c, 16, bcm_adc_gain);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x1c, 16, bcm_adc_gain);
+ } else if (pdetrange == 3) {
+ chan_freq_range =
+ wlc_phy_get_chan_freq_range_nphy(pi, 0);
+ if ((NREV_GE(pi->pubpi.phy_rev, 4))
+ && (chan_freq_range == WL_CHAN_FREQ_RANGE_2G)) {
+
+ u16 auxadc_vmid[] = {
+ 0xa2, 0xb4, 0xb4, 0x270 };
+ u16 auxadc_gain[] = {
+ 0x02, 0x02, 0x02, 0x00 };
+
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_AFECTRL, 4,
+ 0x08, 16, auxadc_vmid);
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_AFECTRL, 4,
+ 0x18, 16, auxadc_vmid);
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_AFECTRL, 4,
+ 0x0c, 16, auxadc_gain);
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_AFECTRL, 4,
+ 0x1c, 16, auxadc_gain);
+ }
+ } else if ((pdetrange == 4) || (pdetrange == 5)) {
+ u16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x0 };
+ u16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x0 };
+ u16 Vmid[2], Av[2];
+
+ chan_freq_range =
+ wlc_phy_get_chan_freq_range_nphy(pi, 0);
+ if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
+ Vmid[0] = (pdetrange == 4) ? 0x8e : 0x89;
+ Vmid[1] = (pdetrange == 4) ? 0x96 : 0x89;
+ Av[0] = (pdetrange == 4) ? 2 : 0;
+ Av[1] = (pdetrange == 4) ? 2 : 0;
+ } else {
+ Vmid[0] = (pdetrange == 4) ? 0x89 : 0x74;
+ Vmid[1] = (pdetrange == 4) ? 0x8b : 0x70;
+ Av[0] = (pdetrange == 4) ? 2 : 0;
+ Av[1] = (pdetrange == 4) ? 2 : 0;
+ }
+
+ bcm_adc_vmid[3] = Vmid[0];
+ bcm_adc_gain[3] = Av[0];
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x08, 16, bcm_adc_vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x0c, 16, bcm_adc_gain);
+
+ bcm_adc_vmid[3] = Vmid[1];
+ bcm_adc_gain[3] = Av[1];
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x18, 16, bcm_adc_vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
+ 0x1c, 16, bcm_adc_gain);
+ }
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_MAST_BIAS | RADIO_2056_RX0),
+ 0x0);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_MAST_BIAS | RADIO_2056_RX1),
+ 0x0);
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_BIAS_MAIN | RADIO_2056_RX0),
+ 0x6);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_BIAS_MAIN | RADIO_2056_RX1),
+ 0x6);
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_BIAS_AUX | RADIO_2056_RX0),
+ 0x7);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_BIAS_AUX | RADIO_2056_RX1),
+ 0x7);
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_LOB_BIAS | RADIO_2056_RX0),
+ 0x88);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_LOB_BIAS | RADIO_2056_RX1),
+ 0x88);
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_CMFB_IDAC | RADIO_2056_RX0),
+ 0x0);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXA_CMFB_IDAC | RADIO_2056_RX1),
+ 0x0);
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXG_CMFB_IDAC | RADIO_2056_RX0),
+ 0x0);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_MIXG_CMFB_IDAC | RADIO_2056_RX1),
+ 0x0);
+
+ triso =
+ (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
+ triso : pi->srom_fem2g.triso;
+ if (triso == 7) {
+ wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_0);
+ wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_1);
+ }
+
+ wlc_phy_war_txchain_upd_nphy(pi, pi->sh->hw_phytxchain);
+
+ if (((pi->sh->boardflags2 & BFL2_APLL_WAR) &&
+ (CHSPEC_IS5G(pi->radio_chanspec))) ||
+ (((pi->sh->boardflags2 & BFL2_GPLL_WAR) ||
+ (pi->sh->boardflags2 & BFL2_GPLL_WAR2)) &&
+ (CHSPEC_IS2G(pi->radio_chanspec)))) {
+ nss1_data_weights = 0x00088888;
+ ht_data_weights = 0x00088888;
+ stbc_data_weights = 0x00088888;
+ } else {
+ nss1_data_weights = 0x88888888;
+ ht_data_weights = 0x88888888;
+ stbc_data_weights = 0x88888888;
+ }
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
+ 1, 1, 32, &nss1_data_weights);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
+ 1, 2, 32, &ht_data_weights);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
+ 1, 3, 32, &stbc_data_weights);
+
+ if (NREV_IS(pi->pubpi.phy_rev, 4)) {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ write_radio_reg(pi,
+ RADIO_2056_TX_GMBB_IDAC |
+ RADIO_2056_TX0, 0x70);
+ write_radio_reg(pi,
+ RADIO_2056_TX_GMBB_IDAC |
+ RADIO_2056_TX1, 0x70);
+ }
+ }
+
+ if (!pi->edcrs_threshold_lock) {
+ write_phy_reg(pi, 0x224, 0x3eb);
+ write_phy_reg(pi, 0x225, 0x3eb);
+ write_phy_reg(pi, 0x226, 0x341);
+ write_phy_reg(pi, 0x227, 0x341);
+ write_phy_reg(pi, 0x228, 0x42b);
+ write_phy_reg(pi, 0x229, 0x42b);
+ write_phy_reg(pi, 0x22a, 0x381);
+ write_phy_reg(pi, 0x22b, 0x381);
+ write_phy_reg(pi, 0x22c, 0x42b);
+ write_phy_reg(pi, 0x22d, 0x42b);
+ write_phy_reg(pi, 0x22e, 0x381);
+ write_phy_reg(pi, 0x22f, 0x381);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+
+ if (pi->sh->boardflags2 & BFL2_SINGLEANT_CCK) {
+ wlapi_bmac_mhf(pi->sh->physhim, MHF4,
+ MHF4_BPHY_TXCORE0,
+ MHF4_BPHY_TXCORE0, WLC_BAND_ALL);
+ }
+ }
+ } else {
+
+ if (pi->sh->boardflags2 & BFL2_SKWRKFEM_BRD ||
+ (pi->sh->boardtype == 0x8b)) {
+ uint i;
+ u8 war_dlys[] = { 1, 6, 6, 2, 4, 20, 1 };
+ for (i = 0; i < ARRAY_SIZE(rfseq_rx2tx_dlys); i++)
+ rfseq_rx2tx_dlys[i] = war_dlys[i];
+ }
+
+ if (CHSPEC_IS5G(pi->radio_chanspec) && pi->phy_5g_pwrgain) {
+ and_radio_reg(pi, RADIO_2055_CORE1_TX_RF_SPARE, 0xf7);
+ and_radio_reg(pi, RADIO_2055_CORE2_TX_RF_SPARE, 0xf7);
+ } else {
+ or_radio_reg(pi, RADIO_2055_CORE1_TX_RF_SPARE, 0x8);
+ or_radio_reg(pi, RADIO_2055_CORE2_TX_RF_SPARE, 0x8);
+ }
+
+ regval = 0x000a;
+ wlc_phy_table_write_nphy(pi, 8, 1, 0, 16, ®val);
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x10, 16, ®val);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 3)) {
+ regval = 0xcdaa;
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x02, 16, ®val);
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x12, 16, ®val);
+ }
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+ regval = 0x0000;
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x08, 16, ®val);
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x18, 16, ®val);
+
+ regval = 0x7aab;
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x07, 16, ®val);
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x17, 16, ®val);
+
+ regval = 0x0800;
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x06, 16, ®val);
+ wlc_phy_table_write_nphy(pi, 8, 1, 0x16, 16, ®val);
+ }
+
+ write_phy_reg(pi, 0xf8, 0x02d8);
+ write_phy_reg(pi, 0xf9, 0x0301);
+ write_phy_reg(pi, 0xfa, 0x02d8);
+ write_phy_reg(pi, 0xfb, 0x0301);
+
+ wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX, rfseq_rx2tx_events,
+ rfseq_rx2tx_dlys,
+ sizeof(rfseq_rx2tx_events) /
+ sizeof(rfseq_rx2tx_events[0]));
+
+ wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_TX2RX, rfseq_tx2rx_events,
+ rfseq_tx2rx_dlys,
+ sizeof(rfseq_tx2rx_events) /
+ sizeof(rfseq_tx2rx_events[0]));
+
+ wlc_phy_workarounds_nphy_gainctrl(pi);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+
+ if (read_phy_reg(pi, 0xa0) & NPHY_MLenable)
+ wlapi_bmac_mhf(pi->sh->physhim, MHF3,
+ MHF3_NPHY_MLADV_WAR,
+ MHF3_NPHY_MLADV_WAR,
+ WLC_BAND_ALL);
+
+ } else if (NREV_IS(pi->pubpi.phy_rev, 2)) {
+ write_phy_reg(pi, 0x1e3, 0x0);
+ write_phy_reg(pi, 0x1e4, 0x0);
+ }
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2))
+ mod_phy_reg(pi, 0x90, (0x1 << 7), 0);
+
+ alpha0 = 293;
+ alpha1 = 435;
+ alpha2 = 261;
+ beta0 = 366;
+ beta1 = 205;
+ beta2 = 32;
+ write_phy_reg(pi, 0x145, alpha0);
+ write_phy_reg(pi, 0x146, alpha1);
+ write_phy_reg(pi, 0x147, alpha2);
+ write_phy_reg(pi, 0x148, beta0);
+ write_phy_reg(pi, 0x149, beta1);
+ write_phy_reg(pi, 0x14a, beta2);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 3)) {
+ mod_phy_reg(pi, 0x142, (0xf << 12), 0);
+
+ write_phy_reg(pi, 0x192, 0xb5);
+ write_phy_reg(pi, 0x193, 0xa4);
+ write_phy_reg(pi, 0x194, 0x0);
+ }
+
+ if (NREV_IS(pi->pubpi.phy_rev, 2)) {
+ mod_phy_reg(pi, 0x221,
+ NPHY_FORCESIG_DECODEGATEDCLKS,
+ NPHY_FORCESIG_DECODEGATEDCLKS);
+ }
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi)
+{
+ u16 w1th, hpf_code, currband;
+ int ctr;
+ u8 rfseq_updategainu_events[] = {
+ NPHY_RFSEQ_CMD_RX_GAIN,
+ NPHY_RFSEQ_CMD_CLR_HIQ_DIS,
+ NPHY_RFSEQ_CMD_SET_HPF_BW
+ };
+ u8 rfseq_updategainu_dlys[] = { 10, 30, 1 };
+ s8 lna1G_gain_db[] = { 7, 11, 16, 23 };
+ s8 lna1G_gain_db_rev4[] = { 8, 12, 17, 25 };
+ s8 lna1G_gain_db_rev5[] = { 9, 13, 18, 26 };
+ s8 lna1G_gain_db_rev6[] = { 8, 13, 18, 25 };
+ s8 lna1G_gain_db_rev6_224B0[] = { 10, 14, 19, 27 };
+ s8 lna1A_gain_db[] = { 7, 11, 17, 23 };
+ s8 lna1A_gain_db_rev4[] = { 8, 12, 18, 23 };
+ s8 lna1A_gain_db_rev5[] = { 6, 10, 16, 21 };
+ s8 lna1A_gain_db_rev6[] = { 6, 10, 16, 21 };
+ s8 *lna1_gain_db = NULL;
+ s8 lna2G_gain_db[] = { -5, 6, 10, 14 };
+ s8 lna2G_gain_db_rev5[] = { -3, 7, 11, 16 };
+ s8 lna2G_gain_db_rev6[] = { -5, 6, 10, 14 };
+ s8 lna2G_gain_db_rev6_224B0[] = { -5, 6, 10, 15 };
+ s8 lna2A_gain_db[] = { -6, 2, 6, 10 };
+ s8 lna2A_gain_db_rev4[] = { -5, 2, 6, 10 };
+ s8 lna2A_gain_db_rev5[] = { -7, 0, 4, 8 };
+ s8 lna2A_gain_db_rev6[] = { -7, 0, 4, 8 };
+ s8 *lna2_gain_db = NULL;
+ s8 tiaG_gain_db[] = {
+ 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A };
+ s8 tiaA_gain_db[] = {
+ 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 };
+ s8 tiaA_gain_db_rev4[] = {
+ 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
+ s8 tiaA_gain_db_rev5[] = {
+ 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
+ s8 tiaA_gain_db_rev6[] = {
+ 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
+ s8 *tia_gain_db;
+ s8 tiaG_gainbits[] = {
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
+ s8 tiaA_gainbits[] = {
+ 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 };
+ s8 tiaA_gainbits_rev4[] = {
+ 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
+ s8 tiaA_gainbits_rev5[] = {
+ 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
+ s8 tiaA_gainbits_rev6[] = {
+ 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
+ s8 *tia_gainbits;
+ s8 lpf_gain_db[] = { 0x00, 0x06, 0x0c, 0x12, 0x12, 0x12 };
+ s8 lpf_gainbits[] = { 0x00, 0x01, 0x02, 0x03, 0x03, 0x03 };
+ u16 rfseqG_init_gain[] = { 0x613f, 0x613f, 0x613f, 0x613f };
+ u16 rfseqG_init_gain_rev4[] = { 0x513f, 0x513f, 0x513f, 0x513f };
+ u16 rfseqG_init_gain_rev5[] = { 0x413f, 0x413f, 0x413f, 0x413f };
+ u16 rfseqG_init_gain_rev5_elna[] = {
+ 0x013f, 0x013f, 0x013f, 0x013f };
+ u16 rfseqG_init_gain_rev6[] = { 0x513f, 0x513f };
+ u16 rfseqG_init_gain_rev6_224B0[] = { 0x413f, 0x413f };
+ u16 rfseqG_init_gain_rev6_elna[] = { 0x113f, 0x113f };
+ u16 rfseqA_init_gain[] = { 0x516f, 0x516f, 0x516f, 0x516f };
+ u16 rfseqA_init_gain_rev4[] = { 0x614f, 0x614f, 0x614f, 0x614f };
+ u16 rfseqA_init_gain_rev4_elna[] = {
+ 0x314f, 0x314f, 0x314f, 0x314f };
+ u16 rfseqA_init_gain_rev5[] = { 0x714f, 0x714f, 0x714f, 0x714f };
+ u16 rfseqA_init_gain_rev6[] = { 0x714f, 0x714f };
+ u16 *rfseq_init_gain;
+ u16 initG_gaincode = 0x627e;
+ u16 initG_gaincode_rev4 = 0x527e;
+ u16 initG_gaincode_rev5 = 0x427e;
+ u16 initG_gaincode_rev5_elna = 0x027e;
+ u16 initG_gaincode_rev6 = 0x527e;
+ u16 initG_gaincode_rev6_224B0 = 0x427e;
+ u16 initG_gaincode_rev6_elna = 0x127e;
+ u16 initA_gaincode = 0x52de;
+ u16 initA_gaincode_rev4 = 0x629e;
+ u16 initA_gaincode_rev4_elna = 0x329e;
+ u16 initA_gaincode_rev5 = 0x729e;
+ u16 initA_gaincode_rev6 = 0x729e;
+ u16 init_gaincode;
+ u16 clip1hiG_gaincode = 0x107e;
+ u16 clip1hiG_gaincode_rev4 = 0x007e;
+ u16 clip1hiG_gaincode_rev5 = 0x1076;
+ u16 clip1hiG_gaincode_rev6 = 0x007e;
+ u16 clip1hiA_gaincode = 0x00de;
+ u16 clip1hiA_gaincode_rev4 = 0x029e;
+ u16 clip1hiA_gaincode_rev5 = 0x029e;
+ u16 clip1hiA_gaincode_rev6 = 0x029e;
+ u16 clip1hi_gaincode;
+ u16 clip1mdG_gaincode = 0x0066;
+ u16 clip1mdA_gaincode = 0x00ca;
+ u16 clip1mdA_gaincode_rev4 = 0x1084;
+ u16 clip1mdA_gaincode_rev5 = 0x2084;
+ u16 clip1mdA_gaincode_rev6 = 0x2084;
+ u16 clip1md_gaincode = 0;
+ u16 clip1loG_gaincode = 0x0074;
+ u16 clip1loG_gaincode_rev5[] = {
+ 0x0062, 0x0064, 0x006a, 0x106a, 0x106c, 0x1074, 0x107c, 0x207c
+ };
+ u16 clip1loG_gaincode_rev6[] = {
+ 0x106a, 0x106c, 0x1074, 0x107c, 0x007e, 0x107e, 0x207e, 0x307e
+ };
+ u16 clip1loG_gaincode_rev6_224B0 = 0x1074;
+ u16 clip1loA_gaincode = 0x00cc;
+ u16 clip1loA_gaincode_rev4 = 0x0086;
+ u16 clip1loA_gaincode_rev5 = 0x2086;
+ u16 clip1loA_gaincode_rev6 = 0x2086;
+ u16 clip1lo_gaincode;
+ u8 crsminG_th = 0x18;
+ u8 crsminG_th_rev5 = 0x18;
+ u8 crsminG_th_rev6 = 0x18;
+ u8 crsminA_th = 0x1e;
+ u8 crsminA_th_rev4 = 0x24;
+ u8 crsminA_th_rev5 = 0x24;
+ u8 crsminA_th_rev6 = 0x24;
+ u8 crsmin_th;
+ u8 crsminlG_th = 0x18;
+ u8 crsminlG_th_rev5 = 0x18;
+ u8 crsminlG_th_rev6 = 0x18;
+ u8 crsminlA_th = 0x1e;
+ u8 crsminlA_th_rev4 = 0x24;
+ u8 crsminlA_th_rev5 = 0x24;
+ u8 crsminlA_th_rev6 = 0x24;
+ u8 crsminl_th = 0;
+ u8 crsminuG_th = 0x18;
+ u8 crsminuG_th_rev5 = 0x18;
+ u8 crsminuG_th_rev6 = 0x18;
+ u8 crsminuA_th = 0x1e;
+ u8 crsminuA_th_rev4 = 0x24;
+ u8 crsminuA_th_rev5 = 0x24;
+ u8 crsminuA_th_rev6 = 0x24;
+ u8 crsminuA_th_rev6_224B0 = 0x2d;
+ u8 crsminu_th;
+ u16 nbclipG_th = 0x20d;
+ u16 nbclipG_th_rev4 = 0x1a1;
+ u16 nbclipG_th_rev5 = 0x1d0;
+ u16 nbclipG_th_rev6 = 0x1d0;
+ u16 nbclipA_th = 0x1a1;
+ u16 nbclipA_th_rev4 = 0x107;
+ u16 nbclipA_th_rev5 = 0x0a9;
+ u16 nbclipA_th_rev6 = 0x0f0;
+ u16 nbclip_th = 0;
+ u8 w1clipG_th = 5;
+ u8 w1clipG_th_rev5 = 9;
+ u8 w1clipG_th_rev6 = 5;
+ u8 w1clipA_th = 25, w1clip_th;
+ u8 rssi_gain_default = 0x50;
+ u8 rssiG_gain_rev6_224B0 = 0x50;
+ u8 rssiA_gain_rev5 = 0x90;
+ u8 rssiA_gain_rev6 = 0x90;
+ u8 rssi_gain;
+ u16 regval[21];
+ u8 triso;
+
+ triso = (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.triso :
+ pi->srom_fem2g.triso;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (pi->pubpi.radiorev == 5) {
+
+ wlc_phy_workarounds_nphy_gainctrl_2057_rev5(pi);
+ } else if (pi->pubpi.radiorev == 7) {
+ wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
+
+ mod_phy_reg(pi, 0x283, (0xff << 0), (0x44 << 0));
+ mod_phy_reg(pi, 0x280, (0xff << 0), (0x44 << 0));
+
+ } else if ((pi->pubpi.radiorev == 3)
+ || (pi->pubpi.radiorev == 8)) {
+ wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
+
+ if (pi->pubpi.radiorev == 8) {
+ mod_phy_reg(pi, 0x283,
+ (0xff << 0), (0x44 << 0));
+ mod_phy_reg(pi, 0x280,
+ (0xff << 0), (0x44 << 0));
+ }
+ } else {
+ wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
+ }
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ mod_phy_reg(pi, 0xa0, (0x1 << 6), (1 << 6));
+
+ mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
+ mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
+
+ currband =
+ read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
+ if (currband == 0) {
+ if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+ if (pi->pubpi.radiorev == 11) {
+ lna1_gain_db = lna1G_gain_db_rev6_224B0;
+ lna2_gain_db = lna2G_gain_db_rev6_224B0;
+ rfseq_init_gain =
+ rfseqG_init_gain_rev6_224B0;
+ init_gaincode =
+ initG_gaincode_rev6_224B0;
+ clip1hi_gaincode =
+ clip1hiG_gaincode_rev6;
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6_224B0;
+ nbclip_th = nbclipG_th_rev6;
+ w1clip_th = w1clipG_th_rev6;
+ crsmin_th = crsminG_th_rev6;
+ crsminl_th = crsminlG_th_rev6;
+ crsminu_th = crsminuG_th_rev6;
+ rssi_gain = rssiG_gain_rev6_224B0;
+ } else {
+ lna1_gain_db = lna1G_gain_db_rev6;
+ lna2_gain_db = lna2G_gain_db_rev6;
+ if (pi->sh->boardflags & BFL_EXTLNA) {
+
+ rfseq_init_gain =
+ rfseqG_init_gain_rev6_elna;
+ init_gaincode =
+ initG_gaincode_rev6_elna;
+ } else {
+ rfseq_init_gain =
+ rfseqG_init_gain_rev6;
+ init_gaincode =
+ initG_gaincode_rev6;
+ }
+ clip1hi_gaincode =
+ clip1hiG_gaincode_rev6;
+ switch (triso) {
+ case 0:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6[0];
+ break;
+ case 1:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6[1];
+ break;
+ case 2:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6[2];
+ break;
+ case 3:
+ default:
+
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6[3];
+ break;
+ case 4:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6[4];
+ break;
+ case 5:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6[5];
+ break;
+ case 6:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6[6];
+ break;
+ case 7:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev6[7];
+ break;
+ }
+ nbclip_th = nbclipG_th_rev6;
+ w1clip_th = w1clipG_th_rev6;
+ crsmin_th = crsminG_th_rev6;
+ crsminl_th = crsminlG_th_rev6;
+ crsminu_th = crsminuG_th_rev6;
+ rssi_gain = rssi_gain_default;
+ }
+ } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+ lna1_gain_db = lna1G_gain_db_rev5;
+ lna2_gain_db = lna2G_gain_db_rev5;
+ if (pi->sh->boardflags & BFL_EXTLNA) {
+
+ rfseq_init_gain =
+ rfseqG_init_gain_rev5_elna;
+ init_gaincode =
+ initG_gaincode_rev5_elna;
+ } else {
+ rfseq_init_gain = rfseqG_init_gain_rev5;
+ init_gaincode = initG_gaincode_rev5;
+ }
+ clip1hi_gaincode = clip1hiG_gaincode_rev5;
+ switch (triso) {
+ case 0:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[0];
+ break;
+ case 1:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[1];
+ break;
+ case 2:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[2];
+ break;
+ case 3:
+
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[3];
+ break;
+ case 4:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[4];
+ break;
+ case 5:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[5];
+ break;
+ case 6:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[6];
+ break;
+ case 7:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[7];
+ break;
+ default:
+ clip1lo_gaincode =
+ clip1loG_gaincode_rev5[3];
+ break;
+ }
+ nbclip_th = nbclipG_th_rev5;
+ w1clip_th = w1clipG_th_rev5;
+ crsmin_th = crsminG_th_rev5;
+ crsminl_th = crsminlG_th_rev5;
+ crsminu_th = crsminuG_th_rev5;
+ rssi_gain = rssi_gain_default;
+ } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
+ lna1_gain_db = lna1G_gain_db_rev4;
+ lna2_gain_db = lna2G_gain_db;
+ rfseq_init_gain = rfseqG_init_gain_rev4;
+ init_gaincode = initG_gaincode_rev4;
+ clip1hi_gaincode = clip1hiG_gaincode_rev4;
+ clip1lo_gaincode = clip1loG_gaincode;
+ nbclip_th = nbclipG_th_rev4;
+ w1clip_th = w1clipG_th;
+ crsmin_th = crsminG_th;
+ crsminl_th = crsminlG_th;
+ crsminu_th = crsminuG_th;
+ rssi_gain = rssi_gain_default;
+ } else {
+ lna1_gain_db = lna1G_gain_db;
+ lna2_gain_db = lna2G_gain_db;
+ rfseq_init_gain = rfseqG_init_gain;
+ init_gaincode = initG_gaincode;
+ clip1hi_gaincode = clip1hiG_gaincode;
+ clip1lo_gaincode = clip1loG_gaincode;
+ nbclip_th = nbclipG_th;
+ w1clip_th = w1clipG_th;
+ crsmin_th = crsminG_th;
+ crsminl_th = crsminlG_th;
+ crsminu_th = crsminuG_th;
+ rssi_gain = rssi_gain_default;
+ }
+ tia_gain_db = tiaG_gain_db;
+ tia_gainbits = tiaG_gainbits;
+ clip1md_gaincode = clip1mdG_gaincode;
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+ lna1_gain_db = lna1A_gain_db_rev6;
+ lna2_gain_db = lna2A_gain_db_rev6;
+ tia_gain_db = tiaA_gain_db_rev6;
+ tia_gainbits = tiaA_gainbits_rev6;
+ rfseq_init_gain = rfseqA_init_gain_rev6;
+ init_gaincode = initA_gaincode_rev6;
+ clip1hi_gaincode = clip1hiA_gaincode_rev6;
+ clip1md_gaincode = clip1mdA_gaincode_rev6;
+ clip1lo_gaincode = clip1loA_gaincode_rev6;
+ crsmin_th = crsminA_th_rev6;
+ crsminl_th = crsminlA_th_rev6;
+ if ((pi->pubpi.radiorev == 11) &&
+ (CHSPEC_IS40(pi->radio_chanspec) == 0)) {
+ crsminu_th = crsminuA_th_rev6_224B0;
+ } else {
+ crsminu_th = crsminuA_th_rev6;
+ }
+ nbclip_th = nbclipA_th_rev6;
+ rssi_gain = rssiA_gain_rev6;
+ } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+ lna1_gain_db = lna1A_gain_db_rev5;
+ lna2_gain_db = lna2A_gain_db_rev5;
+ tia_gain_db = tiaA_gain_db_rev5;
+ tia_gainbits = tiaA_gainbits_rev5;
+ rfseq_init_gain = rfseqA_init_gain_rev5;
+ init_gaincode = initA_gaincode_rev5;
+ clip1hi_gaincode = clip1hiA_gaincode_rev5;
+ clip1md_gaincode = clip1mdA_gaincode_rev5;
+ clip1lo_gaincode = clip1loA_gaincode_rev5;
+ crsmin_th = crsminA_th_rev5;
+ crsminl_th = crsminlA_th_rev5;
+ crsminu_th = crsminuA_th_rev5;
+ nbclip_th = nbclipA_th_rev5;
+ rssi_gain = rssiA_gain_rev5;
+ } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
+ lna1_gain_db = lna1A_gain_db_rev4;
+ lna2_gain_db = lna2A_gain_db_rev4;
+ tia_gain_db = tiaA_gain_db_rev4;
+ tia_gainbits = tiaA_gainbits_rev4;
+ if (pi->sh->boardflags & BFL_EXTLNA_5GHz) {
+
+ rfseq_init_gain =
+ rfseqA_init_gain_rev4_elna;
+ init_gaincode =
+ initA_gaincode_rev4_elna;
+ } else {
+ rfseq_init_gain = rfseqA_init_gain_rev4;
+ init_gaincode = initA_gaincode_rev4;
+ }
+ clip1hi_gaincode = clip1hiA_gaincode_rev4;
+ clip1md_gaincode = clip1mdA_gaincode_rev4;
+ clip1lo_gaincode = clip1loA_gaincode_rev4;
+ crsmin_th = crsminA_th_rev4;
+ crsminl_th = crsminlA_th_rev4;
+ crsminu_th = crsminuA_th_rev4;
+ nbclip_th = nbclipA_th_rev4;
+ rssi_gain = rssi_gain_default;
+ } else {
+ lna1_gain_db = lna1A_gain_db;
+ lna2_gain_db = lna2A_gain_db;
+ tia_gain_db = tiaA_gain_db;
+ tia_gainbits = tiaA_gainbits;
+ rfseq_init_gain = rfseqA_init_gain;
+ init_gaincode = initA_gaincode;
+ clip1hi_gaincode = clip1hiA_gaincode;
+ clip1md_gaincode = clip1mdA_gaincode;
+ clip1lo_gaincode = clip1loA_gaincode;
+ crsmin_th = crsminA_th;
+ crsminl_th = crsminlA_th;
+ crsminu_th = crsminuA_th;
+ nbclip_th = nbclipA_th;
+ rssi_gain = rssi_gain_default;
+ }
+ w1clip_th = w1clipA_th;
+ }
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_BIASPOLE_LNAG1_IDAC |
+ RADIO_2056_RX0), 0x17);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_BIASPOLE_LNAG1_IDAC |
+ RADIO_2056_RX1), 0x17);
+
+ write_radio_reg(pi, (RADIO_2056_RX_LNAG2_IDAC | RADIO_2056_RX0),
+ 0xf0);
+ write_radio_reg(pi, (RADIO_2056_RX_LNAG2_IDAC | RADIO_2056_RX1),
+ 0xf0);
+
+ write_radio_reg(pi, (RADIO_2056_RX_RSSI_POLE | RADIO_2056_RX0),
+ 0x0);
+ write_radio_reg(pi, (RADIO_2056_RX_RSSI_POLE | RADIO_2056_RX1),
+ 0x0);
+
+ write_radio_reg(pi, (RADIO_2056_RX_RSSI_GAIN | RADIO_2056_RX0),
+ rssi_gain);
+ write_radio_reg(pi, (RADIO_2056_RX_RSSI_GAIN | RADIO_2056_RX1),
+ rssi_gain);
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_BIASPOLE_LNAA1_IDAC |
+ RADIO_2056_RX0), 0x17);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_BIASPOLE_LNAA1_IDAC |
+ RADIO_2056_RX1), 0x17);
+
+ write_radio_reg(pi, (RADIO_2056_RX_LNAA2_IDAC | RADIO_2056_RX0),
+ 0xFF);
+ write_radio_reg(pi, (RADIO_2056_RX_LNAA2_IDAC | RADIO_2056_RX1),
+ 0xFF);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8,
+ 8, lna1_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8,
+ 8, lna1_gain_db);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10,
+ 8, lna2_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10,
+ 8, lna2_gain_db);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20,
+ 8, tia_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20,
+ 8, tia_gain_db);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20,
+ 8, tia_gainbits);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20,
+ 8, tia_gainbits);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 6, 0x40,
+ 8, &lpf_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 6, 0x40,
+ 8, &lpf_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 6, 0x40,
+ 8, &lpf_gainbits);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 6, 0x40,
+ 8, &lpf_gainbits);
+
+ write_phy_reg(pi, 0x20, init_gaincode);
+ write_phy_reg(pi, 0x2a7, init_gaincode);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ pi->pubpi.phy_corenum, 0x106, 16,
+ rfseq_init_gain);
+
+ write_phy_reg(pi, 0x22, clip1hi_gaincode);
+ write_phy_reg(pi, 0x2a9, clip1hi_gaincode);
+
+ write_phy_reg(pi, 0x24, clip1md_gaincode);
+ write_phy_reg(pi, 0x2ab, clip1md_gaincode);
+
+ write_phy_reg(pi, 0x37, clip1lo_gaincode);
+ write_phy_reg(pi, 0x2ad, clip1lo_gaincode);
+
+ mod_phy_reg(pi, 0x27d, (0xff << 0), (crsmin_th << 0));
+ mod_phy_reg(pi, 0x280, (0xff << 0), (crsminl_th << 0));
+ mod_phy_reg(pi, 0x283, (0xff << 0), (crsminu_th << 0));
+
+ write_phy_reg(pi, 0x2b, nbclip_th);
+ write_phy_reg(pi, 0x41, nbclip_th);
+
+ mod_phy_reg(pi, 0x27, (0x3f << 0), (w1clip_th << 0));
+ mod_phy_reg(pi, 0x3d, (0x3f << 0), (w1clip_th << 0));
+
+ write_phy_reg(pi, 0x150, 0x809c);
+
+ } else {
+
+ mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
+ mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
+
+ write_phy_reg(pi, 0x2b, 0x84);
+ write_phy_reg(pi, 0x41, 0x84);
+
+ if (CHSPEC_IS20(pi->radio_chanspec)) {
+ write_phy_reg(pi, 0x6b, 0x2b);
+ write_phy_reg(pi, 0x6c, 0x2b);
+ write_phy_reg(pi, 0x6d, 0x9);
+ write_phy_reg(pi, 0x6e, 0x9);
+ }
+
+ w1th = NPHY_RSSICAL_W1_TARGET - 4;
+ mod_phy_reg(pi, 0x27, (0x3f << 0), (w1th << 0));
+ mod_phy_reg(pi, 0x3d, (0x3f << 0), (w1th << 0));
+
+ if (CHSPEC_IS20(pi->radio_chanspec)) {
+ mod_phy_reg(pi, 0x1c, (0x1f << 0), (0x1 << 0));
+ mod_phy_reg(pi, 0x32, (0x1f << 0), (0x1 << 0));
+
+ mod_phy_reg(pi, 0x1d, (0x1f << 0), (0x1 << 0));
+ mod_phy_reg(pi, 0x33, (0x1f << 0), (0x1 << 0));
+ }
+
+ write_phy_reg(pi, 0x150, 0x809c);
+
+ if (pi->nphy_gain_boost)
+ if ((CHSPEC_IS2G(pi->radio_chanspec)) &&
+ (CHSPEC_IS40(pi->radio_chanspec)))
+ hpf_code = 4;
+ else
+ hpf_code = 5;
+ else if (CHSPEC_IS40(pi->radio_chanspec))
+ hpf_code = 6;
+ else
+ hpf_code = 7;
+
+ mod_phy_reg(pi, 0x20, (0x1f << 7), (hpf_code << 7));
+ mod_phy_reg(pi, 0x36, (0x1f << 7), (hpf_code << 7));
+
+ for (ctr = 0; ctr < 4; ctr++) {
+ regval[ctr] = (hpf_code << 8) | 0x7c;
+ }
+ wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);
+
+ wlc_phy_adjust_lnagaintbl_nphy(pi);
+
+ if (pi->nphy_elna_gain_config) {
+ regval[0] = 0;
+ regval[1] = 1;
+ regval[2] = 1;
+ regval[3] = 1;
+ wlc_phy_table_write_nphy(pi, 2, 4, 8, 16, regval);
+ wlc_phy_table_write_nphy(pi, 3, 4, 8, 16, regval);
+
+ for (ctr = 0; ctr < 4; ctr++) {
+ regval[ctr] = (hpf_code << 8) | 0x74;
+ }
+ wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);
+ }
+
+ if (NREV_IS(pi->pubpi.phy_rev, 2)) {
+ for (ctr = 0; ctr < 21; ctr++) {
+ regval[ctr] = 3 * ctr;
+ }
+ wlc_phy_table_write_nphy(pi, 0, 21, 32, 16, regval);
+ wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval);
+
+ for (ctr = 0; ctr < 21; ctr++) {
+ regval[ctr] = (u16) ctr;
+ }
+ wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval);
+ wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval);
+ }
+
+ wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_UPDATEGAINU,
+ rfseq_updategainu_events,
+ rfseq_updategainu_dlys,
+ sizeof(rfseq_updategainu_events) /
+ sizeof(rfseq_updategainu_events[0]));
+
+ mod_phy_reg(pi, 0x153, (0xff << 8), (90 << 8));
+
+ if (CHSPEC_IS2G(pi->radio_chanspec))
+ mod_phy_reg(pi,
+ (NPHY_TO_BPHY_OFF + BPHY_OPTIONAL_MODES),
+ 0x7f, 0x4);
+ }
+}
+
+static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(phy_info_t *pi)
+{
+ s8 lna1_gain_db[] = { 8, 13, 17, 22 };
+ s8 lna2_gain_db[] = { -2, 7, 11, 15 };
+ s8 tia_gain_db[] = { -4, -1, 2, 5, 5, 5, 5, 5, 5, 5 };
+ s8 tia_gainbits[] = {
+ 0x0, 0x01, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
+
+ mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
+ mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
+
+ mod_phy_reg(pi, 0x289, (0xff << 0), (0x46 << 0));
+
+ mod_phy_reg(pi, 0x283, (0xff << 0), (0x3c << 0));
+ mod_phy_reg(pi, 0x280, (0xff << 0), (0x3c << 0));
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x8, 8,
+ lna1_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x8, 8,
+ lna1_gain_db);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10, 8,
+ lna2_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10, 8,
+ lna2_gain_db);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20, 8,
+ tia_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20, 8,
+ tia_gain_db);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20, 8,
+ tia_gainbits);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20, 8,
+ tia_gainbits);
+
+ write_phy_reg(pi, 0x37, 0x74);
+ write_phy_reg(pi, 0x2ad, 0x74);
+ write_phy_reg(pi, 0x38, 0x18);
+ write_phy_reg(pi, 0x2ae, 0x18);
+
+ write_phy_reg(pi, 0x2b, 0xe8);
+ write_phy_reg(pi, 0x41, 0xe8);
+
+ if (CHSPEC_IS20(pi->radio_chanspec)) {
+
+ mod_phy_reg(pi, 0x300, (0x3f << 0), (0x12 << 0));
+ mod_phy_reg(pi, 0x301, (0x3f << 0), (0x12 << 0));
+ } else {
+
+ mod_phy_reg(pi, 0x300, (0x3f << 0), (0x10 << 0));
+ mod_phy_reg(pi, 0x301, (0x3f << 0), (0x10 << 0));
+ }
+}
+
+static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi)
+{
+ u16 currband;
+ s8 lna1G_gain_db_rev7[] = { 9, 14, 19, 24 };
+ s8 *lna1_gain_db = NULL;
+ s8 *lna1_gain_db_2 = NULL;
+ s8 *lna2_gain_db = NULL;
+ s8 tiaA_gain_db_rev7[] = { -9, -6, -3, 0, 3, 3, 3, 3, 3, 3 };
+ s8 *tia_gain_db;
+ s8 tiaA_gainbits_rev7[] = { 0, 1, 2, 3, 4, 4, 4, 4, 4, 4 };
+ s8 *tia_gainbits;
+ u16 rfseqA_init_gain_rev7[] = { 0x624f, 0x624f };
+ u16 *rfseq_init_gain;
+ u16 init_gaincode;
+ u16 clip1hi_gaincode;
+ u16 clip1md_gaincode = 0;
+ u16 clip1md_gaincode_B;
+ u16 clip1lo_gaincode;
+ u16 clip1lo_gaincode_B;
+ u8 crsminl_th = 0;
+ u8 crsminu_th;
+ u16 nbclip_th = 0;
+ u8 w1clip_th;
+ u16 freq;
+ s8 nvar_baseline_offset0 = 0, nvar_baseline_offset1 = 0;
+ u8 chg_nbclip_th = 0;
+
+ mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
+ mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
+
+ currband = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
+ if (currband == 0) {
+
+ lna1_gain_db = lna1G_gain_db_rev7;
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8, 8,
+ lna1_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8, 8,
+ lna1_gain_db);
+
+ mod_phy_reg(pi, 0x283, (0xff << 0), (0x40 << 0));
+
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ mod_phy_reg(pi, 0x280, (0xff << 0), (0x3e << 0));
+ mod_phy_reg(pi, 0x283, (0xff << 0), (0x3e << 0));
+ }
+
+ mod_phy_reg(pi, 0x289, (0xff << 0), (0x46 << 0));
+
+ if (CHSPEC_IS20(pi->radio_chanspec)) {
+ mod_phy_reg(pi, 0x300, (0x3f << 0), (13 << 0));
+ mod_phy_reg(pi, 0x301, (0x3f << 0), (13 << 0));
+ }
+ } else {
+
+ init_gaincode = 0x9e;
+ clip1hi_gaincode = 0x9e;
+ clip1md_gaincode_B = 0x24;
+ clip1lo_gaincode = 0x8a;
+ clip1lo_gaincode_B = 8;
+ rfseq_init_gain = rfseqA_init_gain_rev7;
+
+ tia_gain_db = tiaA_gain_db_rev7;
+ tia_gainbits = tiaA_gainbits_rev7;
+
+ freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec));
+ if (CHSPEC_IS20(pi->radio_chanspec)) {
+
+ w1clip_th = 25;
+ clip1md_gaincode = 0x82;
+
+ if ((freq <= 5080) || (freq == 5825)) {
+
+ s8 lna1A_gain_db_rev7[] = { 11, 16, 20, 24 };
+ s8 lna1A_gain_db_2_rev7[] = {
+ 11, 17, 22, 25 };
+ s8 lna2A_gain_db_rev7[] = { -1, 6, 10, 14 };
+
+ crsminu_th = 0x3e;
+ lna1_gain_db = lna1A_gain_db_rev7;
+ lna1_gain_db_2 = lna1A_gain_db_2_rev7;
+ lna2_gain_db = lna2A_gain_db_rev7;
+ } else if ((freq >= 5500) && (freq <= 5700)) {
+
+ s8 lna1A_gain_db_rev7[] = { 11, 17, 21, 25 };
+ s8 lna1A_gain_db_2_rev7[] = {
+ 12, 18, 22, 26 };
+ s8 lna2A_gain_db_rev7[] = { 1, 8, 12, 16 };
+
+ crsminu_th = 0x45;
+ clip1md_gaincode_B = 0x14;
+ nbclip_th = 0xff;
+ chg_nbclip_th = 1;
+ lna1_gain_db = lna1A_gain_db_rev7;
+ lna1_gain_db_2 = lna1A_gain_db_2_rev7;
+ lna2_gain_db = lna2A_gain_db_rev7;
+ } else {
+
+ s8 lna1A_gain_db_rev7[] = { 12, 18, 22, 26 };
+ s8 lna1A_gain_db_2_rev7[] = {
+ 12, 18, 22, 26 };
+ s8 lna2A_gain_db_rev7[] = { -1, 6, 10, 14 };
+
+ crsminu_th = 0x41;
+ lna1_gain_db = lna1A_gain_db_rev7;
+ lna1_gain_db_2 = lna1A_gain_db_2_rev7;
+ lna2_gain_db = lna2A_gain_db_rev7;
+ }
+
+ if (freq <= 4920) {
+ nvar_baseline_offset0 = 5;
+ nvar_baseline_offset1 = 5;
+ } else if ((freq > 4920) && (freq <= 5320)) {
+ nvar_baseline_offset0 = 3;
+ nvar_baseline_offset1 = 5;
+ } else if ((freq > 5320) && (freq <= 5700)) {
+ nvar_baseline_offset0 = 3;
+ nvar_baseline_offset1 = 2;
+ } else {
+ nvar_baseline_offset0 = 4;
+ nvar_baseline_offset1 = 0;
+ }
+ } else {
+
+ crsminu_th = 0x3a;
+ crsminl_th = 0x3a;
+ w1clip_th = 20;
+
+ if ((freq >= 4920) && (freq <= 5320)) {
+ nvar_baseline_offset0 = 4;
+ nvar_baseline_offset1 = 5;
+ } else if ((freq > 5320) && (freq <= 5550)) {
+ nvar_baseline_offset0 = 4;
+ nvar_baseline_offset1 = 2;
+ } else {
+ nvar_baseline_offset0 = 5;
+ nvar_baseline_offset1 = 3;
+ }
+ }
+
+ write_phy_reg(pi, 0x20, init_gaincode);
+ write_phy_reg(pi, 0x2a7, init_gaincode);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ pi->pubpi.phy_corenum, 0x106, 16,
+ rfseq_init_gain);
+
+ write_phy_reg(pi, 0x22, clip1hi_gaincode);
+ write_phy_reg(pi, 0x2a9, clip1hi_gaincode);
+
+ write_phy_reg(pi, 0x36, clip1md_gaincode_B);
+ write_phy_reg(pi, 0x2ac, clip1md_gaincode_B);
+
+ write_phy_reg(pi, 0x37, clip1lo_gaincode);
+ write_phy_reg(pi, 0x2ad, clip1lo_gaincode);
+ write_phy_reg(pi, 0x38, clip1lo_gaincode_B);
+ write_phy_reg(pi, 0x2ae, clip1lo_gaincode_B);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20, 8,
+ tia_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20, 8,
+ tia_gain_db);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20, 8,
+ tia_gainbits);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20, 8,
+ tia_gainbits);
+
+ mod_phy_reg(pi, 0x283, (0xff << 0), (crsminu_th << 0));
+
+ if (chg_nbclip_th == 1) {
+ write_phy_reg(pi, 0x2b, nbclip_th);
+ write_phy_reg(pi, 0x41, nbclip_th);
+ }
+
+ mod_phy_reg(pi, 0x300, (0x3f << 0), (w1clip_th << 0));
+ mod_phy_reg(pi, 0x301, (0x3f << 0), (w1clip_th << 0));
+
+ mod_phy_reg(pi, 0x2e4,
+ (0x3f << 0), (nvar_baseline_offset0 << 0));
+
+ mod_phy_reg(pi, 0x2e4,
+ (0x3f << 6), (nvar_baseline_offset1 << 6));
+
+ if (CHSPEC_IS20(pi->radio_chanspec)) {
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8, 8,
+ lna1_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8, 8,
+ lna1_gain_db_2);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10,
+ 8, lna2_gain_db);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10,
+ 8, lna2_gain_db);
+
+ write_phy_reg(pi, 0x24, clip1md_gaincode);
+ write_phy_reg(pi, 0x2ab, clip1md_gaincode);
+ } else {
+ mod_phy_reg(pi, 0x280, (0xff << 0), (crsminl_th << 0));
+ }
+
+ }
+
+}
+
+static void wlc_phy_adjust_lnagaintbl_nphy(phy_info_t *pi)
+{
+ uint core;
+ int ctr;
+ s16 gain_delta[2];
+ u8 curr_channel;
+ u16 minmax_gain[2];
+ u16 regval[4];
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ if (pi->nphy_gain_boost) {
+ if ((CHSPEC_IS2G(pi->radio_chanspec))) {
+
+ gain_delta[0] = 6;
+ gain_delta[1] = 6;
+ } else {
+
+ curr_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
+ gain_delta[0] =
+ (s16)
+ PHY_HW_ROUND(((nphy_lnagain_est0[0] *
+ curr_channel) +
+ nphy_lnagain_est0[1]), 13);
+ gain_delta[1] =
+ (s16)
+ PHY_HW_ROUND(((nphy_lnagain_est1[0] *
+ curr_channel) +
+ nphy_lnagain_est1[1]), 13);
+ }
+ } else {
+
+ gain_delta[0] = 0;
+ gain_delta[1] = 0;
+ }
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ if (pi->nphy_elna_gain_config) {
+
+ regval[0] = nphy_def_lnagains[2] + gain_delta[core];
+ regval[1] = nphy_def_lnagains[3] + gain_delta[core];
+ regval[2] = nphy_def_lnagains[3] + gain_delta[core];
+ regval[3] = nphy_def_lnagains[3] + gain_delta[core];
+ } else {
+ for (ctr = 0; ctr < 4; ctr++) {
+ regval[ctr] =
+ nphy_def_lnagains[ctr] + gain_delta[core];
+ }
+ }
+ wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval);
+
+ minmax_gain[core] =
+ (u16) (nphy_def_lnagains[2] + gain_delta[core] + 4);
+ }
+
+ mod_phy_reg(pi, 0x1e, (0xff << 0), (minmax_gain[0] << 0));
+ mod_phy_reg(pi, 0x34, (0xff << 0), (minmax_gain[1] << 0));
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+void wlc_phy_switch_radio_nphy(phy_info_t *pi, bool on)
+{
+ if (on) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (!pi->radio_is_on) {
+ wlc_phy_radio_preinit_205x(pi);
+ wlc_phy_radio_init_2057(pi);
+ wlc_phy_radio_postinit_2057(pi);
+ }
+
+ wlc_phy_chanspec_set((wlc_phy_t *) pi,
+ pi->radio_chanspec);
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ wlc_phy_radio_preinit_205x(pi);
+ wlc_phy_radio_init_2056(pi);
+ wlc_phy_radio_postinit_2056(pi);
+
+ wlc_phy_chanspec_set((wlc_phy_t *) pi,
+ pi->radio_chanspec);
+ } else {
+ wlc_phy_radio_preinit_2055(pi);
+ wlc_phy_radio_init_2055(pi);
+ wlc_phy_radio_postinit_2055(pi);
+ }
+
+ pi->radio_is_on = true;
+
+ } else {
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)
+ && NREV_LT(pi->pubpi.phy_rev, 7)) {
+ and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
+ mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x0);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_PADA_BOOST_TUNE |
+ RADIO_2056_TX0, 0);
+ write_radio_reg(pi,
+ RADIO_2056_TX_PADG_BOOST_TUNE |
+ RADIO_2056_TX0, 0);
+ write_radio_reg(pi,
+ RADIO_2056_TX_PGAA_BOOST_TUNE |
+ RADIO_2056_TX0, 0);
+ write_radio_reg(pi,
+ RADIO_2056_TX_PGAG_BOOST_TUNE |
+ RADIO_2056_TX0, 0);
+ mod_radio_reg(pi,
+ RADIO_2056_TX_MIXA_BOOST_TUNE |
+ RADIO_2056_TX0, 0xf0, 0);
+ write_radio_reg(pi,
+ RADIO_2056_TX_MIXG_BOOST_TUNE |
+ RADIO_2056_TX0, 0);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_PADA_BOOST_TUNE |
+ RADIO_2056_TX1, 0);
+ write_radio_reg(pi,
+ RADIO_2056_TX_PADG_BOOST_TUNE |
+ RADIO_2056_TX1, 0);
+ write_radio_reg(pi,
+ RADIO_2056_TX_PGAA_BOOST_TUNE |
+ RADIO_2056_TX1, 0);
+ write_radio_reg(pi,
+ RADIO_2056_TX_PGAG_BOOST_TUNE |
+ RADIO_2056_TX1, 0);
+ mod_radio_reg(pi,
+ RADIO_2056_TX_MIXA_BOOST_TUNE |
+ RADIO_2056_TX1, 0xf0, 0);
+ write_radio_reg(pi,
+ RADIO_2056_TX_MIXG_BOOST_TUNE |
+ RADIO_2056_TX1, 0);
+
+ pi->radio_is_on = false;
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 8)) {
+ and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
+ pi->radio_is_on = false;
+ }
+
+ }
+}
+
+static void wlc_phy_radio_preinit_2055(phy_info_t *pi)
+{
+
+ and_phy_reg(pi, 0x78, ~RFCC_POR_FORCE);
+ or_phy_reg(pi, 0x78, RFCC_CHIP0_PU | RFCC_OE_POR_FORCE);
+
+ or_phy_reg(pi, 0x78, RFCC_POR_FORCE);
+}
+
+static void wlc_phy_radio_init_2055(phy_info_t *pi)
+{
+ wlc_phy_init_radio_regs(pi, regs_2055, RADIO_DEFAULT_CORE);
+}
+
+static void wlc_phy_radio_postinit_2055(phy_info_t *pi)
+{
+
+ and_radio_reg(pi, RADIO_2055_MASTER_CNTRL1,
+ ~(RADIO_2055_JTAGCTRL_MASK | RADIO_2055_JTAGSYNC_MASK));
+
+ if (((pi->sh->sromrev >= 4)
+ && !(pi->sh->boardflags2 & BFL2_RXBB_INT_REG_DIS))
+ || ((pi->sh->sromrev < 4))) {
+ and_radio_reg(pi, RADIO_2055_CORE1_RXBB_REGULATOR, 0x7F);
+ and_radio_reg(pi, RADIO_2055_CORE2_RXBB_REGULATOR, 0x7F);
+ }
+
+ mod_radio_reg(pi, RADIO_2055_RRCCAL_N_OPT_SEL, 0x3F, 0x2C);
+ write_radio_reg(pi, RADIO_2055_CAL_MISC, 0x3C);
+
+ and_radio_reg(pi, RADIO_2055_CAL_MISC,
+ ~(RADIO_2055_RRCAL_START | RADIO_2055_RRCAL_RST_N));
+
+ or_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL, RADIO_2055_CAL_LPO_ENABLE);
+
+ or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_RST_N);
+
+ udelay(1000);
+
+ or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_START);
+
+ SPINWAIT(((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
+ RADIO_2055_RCAL_DONE) != RADIO_2055_RCAL_DONE), 2000);
+
+ if (WARN((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
+ RADIO_2055_RCAL_DONE) != RADIO_2055_RCAL_DONE,
+ "HW error: radio calibration1\n"))
+ return;
+
+ and_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL,
+ ~(RADIO_2055_CAL_LPO_ENABLE));
+
+ wlc_phy_chanspec_set((wlc_phy_t *) pi, pi->radio_chanspec);
+
+ write_radio_reg(pi, RADIO_2055_CORE1_RXBB_LPF, 9);
+ write_radio_reg(pi, RADIO_2055_CORE2_RXBB_LPF, 9);
+
+ write_radio_reg(pi, RADIO_2055_CORE1_RXBB_MIDAC_HIPAS, 0x83);
+ write_radio_reg(pi, RADIO_2055_CORE2_RXBB_MIDAC_HIPAS, 0x83);
+
+ mod_radio_reg(pi, RADIO_2055_CORE1_LNA_GAINBST,
+ RADIO_2055_GAINBST_VAL_MASK, RADIO_2055_GAINBST_CODE);
+ mod_radio_reg(pi, RADIO_2055_CORE2_LNA_GAINBST,
+ RADIO_2055_GAINBST_VAL_MASK, RADIO_2055_GAINBST_CODE);
+ if (pi->nphy_gain_boost) {
+ and_radio_reg(pi, RADIO_2055_CORE1_RXRF_SPC1,
+ ~(RADIO_2055_GAINBST_DISABLE));
+ and_radio_reg(pi, RADIO_2055_CORE2_RXRF_SPC1,
+ ~(RADIO_2055_GAINBST_DISABLE));
+ } else {
+ or_radio_reg(pi, RADIO_2055_CORE1_RXRF_SPC1,
+ RADIO_2055_GAINBST_DISABLE);
+ or_radio_reg(pi, RADIO_2055_CORE2_RXRF_SPC1,
+ RADIO_2055_GAINBST_DISABLE);
+ }
+
+ udelay(2);
+}
+
+static void wlc_phy_radio_preinit_205x(phy_info_t *pi)
+{
+
+ and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
+ and_phy_reg(pi, 0x78, RFCC_OE_POR_FORCE);
+
+ or_phy_reg(pi, 0x78, ~RFCC_OE_POR_FORCE);
+ or_phy_reg(pi, 0x78, RFCC_CHIP0_PU);
+
+}
+
+static void wlc_phy_radio_init_2056(phy_info_t *pi)
+{
+ radio_regs_t *regs_SYN_2056_ptr = NULL;
+ radio_regs_t *regs_TX_2056_ptr = NULL;
+ radio_regs_t *regs_RX_2056_ptr = NULL;
+
+ if (NREV_IS(pi->pubpi.phy_rev, 3)) {
+ regs_SYN_2056_ptr = regs_SYN_2056;
+ regs_TX_2056_ptr = regs_TX_2056;
+ regs_RX_2056_ptr = regs_RX_2056;
+ } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
+ regs_SYN_2056_ptr = regs_SYN_2056_A1;
+ regs_TX_2056_ptr = regs_TX_2056_A1;
+ regs_RX_2056_ptr = regs_RX_2056_A1;
+ } else {
+ switch (pi->pubpi.radiorev) {
+ case 5:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev5;
+ regs_TX_2056_ptr = regs_TX_2056_rev5;
+ regs_RX_2056_ptr = regs_RX_2056_rev5;
+ break;
+
+ case 6:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev6;
+ regs_TX_2056_ptr = regs_TX_2056_rev6;
+ regs_RX_2056_ptr = regs_RX_2056_rev6;
+ break;
+
+ case 7:
+ case 9:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev7;
+ regs_TX_2056_ptr = regs_TX_2056_rev7;
+ regs_RX_2056_ptr = regs_RX_2056_rev7;
+ break;
+
+ case 8:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev8;
+ regs_TX_2056_ptr = regs_TX_2056_rev8;
+ regs_RX_2056_ptr = regs_RX_2056_rev8;
+ break;
+
+ case 11:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev11;
+ regs_TX_2056_ptr = regs_TX_2056_rev11;
+ regs_RX_2056_ptr = regs_RX_2056_rev11;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ wlc_phy_init_radio_regs(pi, regs_SYN_2056_ptr, (u16) RADIO_2056_SYN);
+
+ wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX0);
+
+ wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX1);
+
+ wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX0);
+
+ wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX1);
+}
+
+static void wlc_phy_radio_postinit_2056(phy_info_t *pi)
+{
+ mod_radio_reg(pi, RADIO_2056_SYN_COM_CTRL, 0xb, 0xb);
+
+ mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x2);
+ mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x2);
+ udelay(1000);
+ mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x0);
+
+ if ((pi->sh->boardflags2 & BFL2_LEGACY)
+ || (pi->sh->boardflags2 & BFL2_XTALBUFOUTEN)) {
+
+ mod_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2, 0xf4, 0x0);
+ } else {
+
+ mod_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2, 0xfc, 0x0);
+ }
+
+ mod_radio_reg(pi, RADIO_2056_SYN_RCCAL_CTRL0, 0x1, 0x0);
+
+ if (pi->phy_init_por) {
+ wlc_phy_radio205x_rcal(pi);
+ }
+}
+
+static void wlc_phy_radio_init_2057(phy_info_t *pi)
+{
+ radio_20xx_regs_t *regs_2057_ptr = NULL;
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)) {
+
+ regs_2057_ptr = regs_2057_rev4;
+ } else if (NREV_IS(pi->pubpi.phy_rev, 8)
+ || NREV_IS(pi->pubpi.phy_rev, 9)) {
+ switch (pi->pubpi.radiorev) {
+ case 5:
+
+ if (pi->pubpi.radiover == 0x0) {
+
+ regs_2057_ptr = regs_2057_rev5;
+
+ } else if (pi->pubpi.radiover == 0x1) {
+
+ regs_2057_ptr = regs_2057_rev5v1;
+ } else {
+ break;
+ }
+
+ case 7:
+
+ regs_2057_ptr = regs_2057_rev7;
+ break;
+
+ case 8:
+
+ regs_2057_ptr = regs_2057_rev8;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ wlc_phy_init_radio_regs_allbands(pi, regs_2057_ptr);
+}
+
+static void wlc_phy_radio_postinit_2057(phy_info_t *pi)
+{
+
+ mod_radio_reg(pi, RADIO_2057_XTALPUOVR_PINCTRL, 0x1, 0x1);
+
+ if (pi->sh->chip == !BCM6362_CHIP_ID) {
+
+ mod_radio_reg(pi, RADIO_2057_XTALPUOVR_PINCTRL, 0x2, 0x2);
+ }
+
+ mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x78);
+ mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x80);
+ mdelay(2);
+ mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x0);
+ mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x0);
+
+ if (pi->phy_init_por) {
+ wlc_phy_radio205x_rcal(pi);
+ wlc_phy_radio2057_rccal(pi);
+ }
+
+ mod_radio_reg(pi, RADIO_2057_RFPLL_MASTER, 0x8, 0x0);
+}
+
+static bool
+wlc_phy_chan2freq_nphy(phy_info_t *pi, uint channel, int *f,
+ chan_info_nphy_radio2057_t **t0,
+ chan_info_nphy_radio205x_t **t1,
+ chan_info_nphy_radio2057_rev5_t **t2,
+ chan_info_nphy_2055_t **t3)
+{
+ uint i;
+ chan_info_nphy_radio2057_t *chan_info_tbl_p_0 = NULL;
+ chan_info_nphy_radio205x_t *chan_info_tbl_p_1 = NULL;
+ chan_info_nphy_radio2057_rev5_t *chan_info_tbl_p_2 = NULL;
+ u32 tbl_len = 0;
+
+ int freq = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)) {
+
+ chan_info_tbl_p_0 = chan_info_nphyrev7_2057_rev4;
+ tbl_len = ARRAY_SIZE(chan_info_nphyrev7_2057_rev4);
+
+ } else if (NREV_IS(pi->pubpi.phy_rev, 8)
+ || NREV_IS(pi->pubpi.phy_rev, 9)) {
+ switch (pi->pubpi.radiorev) {
+
+ case 5:
+
+ if (pi->pubpi.radiover == 0x0) {
+
+ chan_info_tbl_p_2 =
+ chan_info_nphyrev8_2057_rev5;
+ tbl_len =
+ ARRAY_SIZE
+ (chan_info_nphyrev8_2057_rev5);
+
+ } else if (pi->pubpi.radiover == 0x1) {
+
+ chan_info_tbl_p_2 =
+ chan_info_nphyrev9_2057_rev5v1;
+ tbl_len =
+ ARRAY_SIZE
+ (chan_info_nphyrev9_2057_rev5v1);
+
+ }
+ break;
+
+ case 7:
+ chan_info_tbl_p_0 =
+ chan_info_nphyrev8_2057_rev7;
+ tbl_len =
+ ARRAY_SIZE(chan_info_nphyrev8_2057_rev7);
+ break;
+
+ case 8:
+ chan_info_tbl_p_0 =
+ chan_info_nphyrev8_2057_rev8;
+ tbl_len =
+ ARRAY_SIZE(chan_info_nphyrev8_2057_rev8);
+ break;
+
+ default:
+ if (NORADIO_ENAB(pi->pubpi)) {
+ goto fail;
+ }
+ break;
+ }
+ } else if (NREV_IS(pi->pubpi.phy_rev, 16)) {
+
+ chan_info_tbl_p_0 = chan_info_nphyrev8_2057_rev8;
+ tbl_len = ARRAY_SIZE(chan_info_nphyrev8_2057_rev8);
+ } else {
+ goto fail;
+ }
+
+ for (i = 0; i < tbl_len; i++) {
+ if (pi->pubpi.radiorev == 5) {
+
+ if (chan_info_tbl_p_2[i].chan == channel)
+ break;
+ } else {
+
+ if (chan_info_tbl_p_0[i].chan == channel)
+ break;
+ }
+ }
+
+ if (i >= tbl_len) {
+ goto fail;
+ }
+ if (pi->pubpi.radiorev == 5) {
+ *t2 = &chan_info_tbl_p_2[i];
+ freq = chan_info_tbl_p_2[i].freq;
+ } else {
+ *t0 = &chan_info_tbl_p_0[i];
+ freq = chan_info_tbl_p_0[i].freq;
+ }
+
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (NREV_IS(pi->pubpi.phy_rev, 3)) {
+ chan_info_tbl_p_1 = chan_info_nphyrev3_2056;
+ tbl_len = ARRAY_SIZE(chan_info_nphyrev3_2056);
+ } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
+ chan_info_tbl_p_1 = chan_info_nphyrev4_2056_A1;
+ tbl_len = ARRAY_SIZE(chan_info_nphyrev4_2056_A1);
+ } else if (NREV_IS(pi->pubpi.phy_rev, 5)
+ || NREV_IS(pi->pubpi.phy_rev, 6)) {
+ switch (pi->pubpi.radiorev) {
+ case 5:
+ chan_info_tbl_p_1 = chan_info_nphyrev5_2056v5;
+ tbl_len = ARRAY_SIZE(chan_info_nphyrev5_2056v5);
+ break;
+ case 6:
+ chan_info_tbl_p_1 = chan_info_nphyrev6_2056v6;
+ tbl_len = ARRAY_SIZE(chan_info_nphyrev6_2056v6);
+ break;
+ case 7:
+ case 9:
+ chan_info_tbl_p_1 = chan_info_nphyrev5n6_2056v7;
+ tbl_len =
+ ARRAY_SIZE(chan_info_nphyrev5n6_2056v7);
+ break;
+ case 8:
+ chan_info_tbl_p_1 = chan_info_nphyrev6_2056v8;
+ tbl_len = ARRAY_SIZE(chan_info_nphyrev6_2056v8);
+ break;
+ case 11:
+ chan_info_tbl_p_1 = chan_info_nphyrev6_2056v11;
+ tbl_len = ARRAY_SIZE(chan_info_nphyrev6_2056v11);
+ break;
+ default:
+ if (NORADIO_ENAB(pi->pubpi)) {
+ goto fail;
+ }
+ break;
+ }
+ }
+
+ for (i = 0; i < tbl_len; i++) {
+ if (chan_info_tbl_p_1[i].chan == channel)
+ break;
+ }
+
+ if (i >= tbl_len) {
+ goto fail;
+ }
+ *t1 = &chan_info_tbl_p_1[i];
+ freq = chan_info_tbl_p_1[i].freq;
+
+ } else {
+ for (i = 0; i < ARRAY_SIZE(chan_info_nphy_2055); i++)
+ if (chan_info_nphy_2055[i].chan == channel)
+ break;
+
+ if (i >= ARRAY_SIZE(chan_info_nphy_2055)) {
+ goto fail;
+ }
+ *t3 = &chan_info_nphy_2055[i];
+ freq = chan_info_nphy_2055[i].freq;
+ }
+
+ *f = freq;
+ return true;
+
+ fail:
+ *f = WL_CHAN_FREQ_RANGE_2G;
+ return false;
+}
+
+u8 wlc_phy_get_chan_freq_range_nphy(phy_info_t *pi, uint channel)
+{
+ int freq;
+ chan_info_nphy_radio2057_t *t0 = NULL;
+ chan_info_nphy_radio205x_t *t1 = NULL;
+ chan_info_nphy_radio2057_rev5_t *t2 = NULL;
+ chan_info_nphy_2055_t *t3 = NULL;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return WL_CHAN_FREQ_RANGE_2G;
+
+ if (channel == 0)
+ channel = CHSPEC_CHANNEL(pi->radio_chanspec);
+
+ wlc_phy_chan2freq_nphy(pi, channel, &freq, &t0, &t1, &t2, &t3);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec))
+ return WL_CHAN_FREQ_RANGE_2G;
+
+ if ((freq >= BASE_LOW_5G_CHAN) && (freq < BASE_MID_5G_CHAN)) {
+ return WL_CHAN_FREQ_RANGE_5GL;
+ } else if ((freq >= BASE_MID_5G_CHAN) && (freq < BASE_HIGH_5G_CHAN)) {
+ return WL_CHAN_FREQ_RANGE_5GM;
+ } else {
+ return WL_CHAN_FREQ_RANGE_5GH;
+ }
+}
+
+static void
+wlc_phy_chanspec_radio2055_setup(phy_info_t *pi, chan_info_nphy_2055_t *ci)
+{
+
+ write_radio_reg(pi, RADIO_2055_PLL_REF, ci->RF_pll_ref);
+ write_radio_reg(pi, RADIO_2055_RF_PLL_MOD0, ci->RF_rf_pll_mod0);
+ write_radio_reg(pi, RADIO_2055_RF_PLL_MOD1, ci->RF_rf_pll_mod1);
+ write_radio_reg(pi, RADIO_2055_VCO_CAP_TAIL, ci->RF_vco_cap_tail);
+
+ WLC_PHY_WAR_PR51571(pi);
+
+ write_radio_reg(pi, RADIO_2055_VCO_CAL1, ci->RF_vco_cal1);
+ write_radio_reg(pi, RADIO_2055_VCO_CAL2, ci->RF_vco_cal2);
+ write_radio_reg(pi, RADIO_2055_PLL_LF_C1, ci->RF_pll_lf_c1);
+ write_radio_reg(pi, RADIO_2055_PLL_LF_R1, ci->RF_pll_lf_r1);
+
+ WLC_PHY_WAR_PR51571(pi);
+
+ write_radio_reg(pi, RADIO_2055_PLL_LF_C2, ci->RF_pll_lf_c2);
+ write_radio_reg(pi, RADIO_2055_LGBUF_CEN_BUF, ci->RF_lgbuf_cen_buf);
+ write_radio_reg(pi, RADIO_2055_LGEN_TUNE1, ci->RF_lgen_tune1);
+ write_radio_reg(pi, RADIO_2055_LGEN_TUNE2, ci->RF_lgen_tune2);
+
+ WLC_PHY_WAR_PR51571(pi);
+
+ write_radio_reg(pi, RADIO_2055_CORE1_LGBUF_A_TUNE,
+ ci->RF_core1_lgbuf_a_tune);
+ write_radio_reg(pi, RADIO_2055_CORE1_LGBUF_G_TUNE,
+ ci->RF_core1_lgbuf_g_tune);
+ write_radio_reg(pi, RADIO_2055_CORE1_RXRF_REG1, ci->RF_core1_rxrf_reg1);
+ write_radio_reg(pi, RADIO_2055_CORE1_TX_PGA_PAD_TN,
+ ci->RF_core1_tx_pga_pad_tn);
+
+ WLC_PHY_WAR_PR51571(pi);
+
+ write_radio_reg(pi, RADIO_2055_CORE1_TX_MX_BGTRIM,
+ ci->RF_core1_tx_mx_bgtrim);
+ write_radio_reg(pi, RADIO_2055_CORE2_LGBUF_A_TUNE,
+ ci->RF_core2_lgbuf_a_tune);
+ write_radio_reg(pi, RADIO_2055_CORE2_LGBUF_G_TUNE,
+ ci->RF_core2_lgbuf_g_tune);
+ write_radio_reg(pi, RADIO_2055_CORE2_RXRF_REG1, ci->RF_core2_rxrf_reg1);
+
+ WLC_PHY_WAR_PR51571(pi);
+
+ write_radio_reg(pi, RADIO_2055_CORE2_TX_PGA_PAD_TN,
+ ci->RF_core2_tx_pga_pad_tn);
+ write_radio_reg(pi, RADIO_2055_CORE2_TX_MX_BGTRIM,
+ ci->RF_core2_tx_mx_bgtrim);
+
+ udelay(50);
+
+ write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x05);
+ write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x45);
+
+ WLC_PHY_WAR_PR51571(pi);
+
+ write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x65);
+
+ udelay(300);
+}
+
+static void
+wlc_phy_chanspec_radio2056_setup(phy_info_t *pi,
+ const chan_info_nphy_radio205x_t *ci)
+{
+ radio_regs_t *regs_SYN_2056_ptr = NULL;
+
+ write_radio_reg(pi,
+ RADIO_2056_SYN_PLL_VCOCAL1 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_vcocal1);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_VCOCAL2 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_vcocal2);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_REFDIV | RADIO_2056_SYN,
+ ci->RF_SYN_pll_refdiv);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_MMD2 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_mmd2);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_MMD1 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_mmd1);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_loopfilter1);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_loopfilter2);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER3 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_loopfilter3);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER4 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_loopfilter4);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER5 | RADIO_2056_SYN,
+ ci->RF_SYN_pll_loopfilter5);
+ write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR27 | RADIO_2056_SYN,
+ ci->RF_SYN_reserved_addr27);
+ write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR28 | RADIO_2056_SYN,
+ ci->RF_SYN_reserved_addr28);
+ write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR29 | RADIO_2056_SYN,
+ ci->RF_SYN_reserved_addr29);
+ write_radio_reg(pi, RADIO_2056_SYN_LOGEN_VCOBUF1 | RADIO_2056_SYN,
+ ci->RF_SYN_logen_VCOBUF1);
+ write_radio_reg(pi, RADIO_2056_SYN_LOGEN_MIXER2 | RADIO_2056_SYN,
+ ci->RF_SYN_logen_MIXER2);
+ write_radio_reg(pi, RADIO_2056_SYN_LOGEN_BUF3 | RADIO_2056_SYN,
+ ci->RF_SYN_logen_BUF3);
+ write_radio_reg(pi, RADIO_2056_SYN_LOGEN_BUF4 | RADIO_2056_SYN,
+ ci->RF_SYN_logen_BUF4);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAA_TUNE | RADIO_2056_RX0,
+ ci->RF_RX0_lnaa_tune);
+ write_radio_reg(pi, RADIO_2056_RX_LNAG_TUNE | RADIO_2056_RX0,
+ ci->RF_RX0_lnag_tune);
+ write_radio_reg(pi, RADIO_2056_TX_INTPAA_BOOST_TUNE | RADIO_2056_TX0,
+ ci->RF_TX0_intpaa_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_INTPAG_BOOST_TUNE | RADIO_2056_TX0,
+ ci->RF_TX0_intpag_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_PADA_BOOST_TUNE | RADIO_2056_TX0,
+ ci->RF_TX0_pada_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_PADG_BOOST_TUNE | RADIO_2056_TX0,
+ ci->RF_TX0_padg_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_PGAA_BOOST_TUNE | RADIO_2056_TX0,
+ ci->RF_TX0_pgaa_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_PGAG_BOOST_TUNE | RADIO_2056_TX0,
+ ci->RF_TX0_pgag_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_MIXA_BOOST_TUNE | RADIO_2056_TX0,
+ ci->RF_TX0_mixa_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_MIXG_BOOST_TUNE | RADIO_2056_TX0,
+ ci->RF_TX0_mixg_boost_tune);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAA_TUNE | RADIO_2056_RX1,
+ ci->RF_RX1_lnaa_tune);
+ write_radio_reg(pi, RADIO_2056_RX_LNAG_TUNE | RADIO_2056_RX1,
+ ci->RF_RX1_lnag_tune);
+ write_radio_reg(pi, RADIO_2056_TX_INTPAA_BOOST_TUNE | RADIO_2056_TX1,
+ ci->RF_TX1_intpaa_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_INTPAG_BOOST_TUNE | RADIO_2056_TX1,
+ ci->RF_TX1_intpag_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_PADA_BOOST_TUNE | RADIO_2056_TX1,
+ ci->RF_TX1_pada_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_PADG_BOOST_TUNE | RADIO_2056_TX1,
+ ci->RF_TX1_padg_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_PGAA_BOOST_TUNE | RADIO_2056_TX1,
+ ci->RF_TX1_pgaa_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_PGAG_BOOST_TUNE | RADIO_2056_TX1,
+ ci->RF_TX1_pgag_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_MIXA_BOOST_TUNE | RADIO_2056_TX1,
+ ci->RF_TX1_mixa_boost_tune);
+ write_radio_reg(pi, RADIO_2056_TX_MIXG_BOOST_TUNE | RADIO_2056_TX1,
+ ci->RF_TX1_mixg_boost_tune);
+
+ if (NREV_IS(pi->pubpi.phy_rev, 3))
+ regs_SYN_2056_ptr = regs_SYN_2056;
+ else if (NREV_IS(pi->pubpi.phy_rev, 4))
+ regs_SYN_2056_ptr = regs_SYN_2056_A1;
+ else {
+ switch (pi->pubpi.radiorev) {
+ case 5:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev5;
+ break;
+ case 6:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev6;
+ break;
+ case 7:
+ case 9:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev7;
+ break;
+ case 8:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev8;
+ break;
+ case 11:
+ regs_SYN_2056_ptr = regs_SYN_2056_rev11;
+ break;
+ }
+ }
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
+ RADIO_2056_SYN,
+ (u16) regs_SYN_2056_ptr[0x49 - 2].init_g);
+ } else {
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
+ RADIO_2056_SYN,
+ (u16) regs_SYN_2056_ptr[0x49 - 2].init_a);
+ }
+
+ if (pi->sh->boardflags2 & BFL2_GPLL_WAR) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 |
+ RADIO_2056_SYN, 0x1f);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
+ RADIO_2056_SYN, 0x1f);
+
+ if ((pi->sh->chip == BCM4716_CHIP_ID) ||
+ (pi->sh->chip == BCM47162_CHIP_ID)) {
+
+ write_radio_reg(pi,
+ RADIO_2056_SYN_PLL_LOOPFILTER4 |
+ RADIO_2056_SYN, 0x14);
+ write_radio_reg(pi,
+ RADIO_2056_SYN_PLL_CP2 |
+ RADIO_2056_SYN, 0x00);
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_SYN_PLL_LOOPFILTER4 |
+ RADIO_2056_SYN, 0xb);
+ write_radio_reg(pi,
+ RADIO_2056_SYN_PLL_CP2 |
+ RADIO_2056_SYN, 0x14);
+ }
+ }
+ }
+
+ if ((pi->sh->boardflags2 & BFL2_GPLL_WAR2) &&
+ (CHSPEC_IS2G(pi->radio_chanspec))) {
+ write_radio_reg(pi,
+ RADIO_2056_SYN_PLL_LOOPFILTER1 | RADIO_2056_SYN,
+ 0x1f);
+ write_radio_reg(pi,
+ RADIO_2056_SYN_PLL_LOOPFILTER2 | RADIO_2056_SYN,
+ 0x1f);
+ write_radio_reg(pi,
+ RADIO_2056_SYN_PLL_LOOPFILTER4 | RADIO_2056_SYN,
+ 0xb);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 | RADIO_2056_SYN,
+ 0x20);
+ }
+
+ if (pi->sh->boardflags2 & BFL2_APLL_WAR) {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 |
+ RADIO_2056_SYN, 0x1f);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
+ RADIO_2056_SYN, 0x1f);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER4 |
+ RADIO_2056_SYN, 0x5);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
+ RADIO_2056_SYN, 0xc);
+ }
+ }
+
+ if (PHY_IPA(pi) && CHSPEC_IS2G(pi->radio_chanspec)) {
+ u16 pag_boost_tune;
+ u16 padg_boost_tune;
+ u16 pgag_boost_tune;
+ u16 mixg_boost_tune;
+ u16 bias, cascbias;
+ uint core;
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+
+ if (NREV_GE(pi->pubpi.phy_rev, 5)) {
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ PADG_IDAC, 0xcc);
+
+ if ((pi->sh->chip == BCM4716_CHIP_ID) ||
+ (pi->sh->chip ==
+ BCM47162_CHIP_ID)) {
+ bias = 0x40;
+ cascbias = 0x45;
+ pag_boost_tune = 0x5;
+ pgag_boost_tune = 0x33;
+ padg_boost_tune = 0x77;
+ mixg_boost_tune = 0x55;
+ } else {
+ bias = 0x25;
+ cascbias = 0x20;
+
+ if ((pi->sh->chip ==
+ BCM43224_CHIP_ID)
+ || (pi->sh->chip ==
+ BCM43225_CHIP_ID)
+ || (pi->sh->chip ==
+ BCM43421_CHIP_ID)) {
+ if (pi->sh->chippkg ==
+ BCM43224_FAB_SMIC) {
+ bias = 0x2a;
+ cascbias = 0x38;
+ }
+ }
+
+ pag_boost_tune = 0x4;
+ pgag_boost_tune = 0x03;
+ padg_boost_tune = 0x77;
+ mixg_boost_tune = 0x65;
+ }
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_IMAIN_STAT, bias);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_IAUX_STAT, bias);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_CASCBIAS, cascbias);
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_BOOST_TUNE,
+ pag_boost_tune);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ PGAG_BOOST_TUNE,
+ pgag_boost_tune);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ PADG_BOOST_TUNE,
+ padg_boost_tune);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ MIXG_BOOST_TUNE,
+ mixg_boost_tune);
+ } else {
+
+ bias = IS40MHZ(pi) ? 0x40 : 0x20;
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_IMAIN_STAT, bias);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_IAUX_STAT, bias);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_CASCBIAS, 0x30);
+ }
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, PA_SPARE1,
+ 0xee);
+ }
+ }
+
+ if (PHY_IPA(pi) && NREV_IS(pi->pubpi.phy_rev, 6)
+ && CHSPEC_IS5G(pi->radio_chanspec)) {
+ u16 paa_boost_tune;
+ u16 pada_boost_tune;
+ u16 pgaa_boost_tune;
+ u16 mixa_boost_tune;
+ u16 freq, pabias, cascbias;
+ uint core;
+
+ freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec));
+
+ if (freq < 5150) {
+
+ paa_boost_tune = 0xa;
+ pada_boost_tune = 0x77;
+ pgaa_boost_tune = 0xf;
+ mixa_boost_tune = 0xf;
+ } else if (freq < 5340) {
+
+ paa_boost_tune = 0x8;
+ pada_boost_tune = 0x77;
+ pgaa_boost_tune = 0xfb;
+ mixa_boost_tune = 0xf;
+ } else if (freq < 5650) {
+
+ paa_boost_tune = 0x0;
+ pada_boost_tune = 0x77;
+ pgaa_boost_tune = 0xb;
+ mixa_boost_tune = 0xf;
+ } else {
+
+ paa_boost_tune = 0x0;
+ pada_boost_tune = 0x77;
+ if (freq != 5825) {
+ pgaa_boost_tune = -(int)(freq - 18) / 36 + 168;
+ } else {
+ pgaa_boost_tune = 6;
+ }
+ mixa_boost_tune = 0xf;
+ }
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAA_BOOST_TUNE, paa_boost_tune);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ PADA_BOOST_TUNE, pada_boost_tune);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ PGAA_BOOST_TUNE, pgaa_boost_tune);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ MIXA_BOOST_TUNE, mixa_boost_tune);
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ TXSPARE1, 0x30);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ PA_SPARE2, 0xee);
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ PADA_CASCBIAS, 0x3);
+
+ cascbias = 0x30;
+
+ if ((pi->sh->chip == BCM43224_CHIP_ID) ||
+ (pi->sh->chip == BCM43225_CHIP_ID) ||
+ (pi->sh->chip == BCM43421_CHIP_ID)) {
+ if (pi->sh->chippkg == BCM43224_FAB_SMIC) {
+ cascbias = 0x35;
+ }
+ }
+
+ pabias = (pi->phy_pabias == 0) ? 0x30 : pi->phy_pabias;
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAA_IAUX_STAT, pabias);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAA_IMAIN_STAT, pabias);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAA_CASCBIAS, cascbias);
+ }
+ }
+
+ udelay(50);
+
+ wlc_phy_radio205x_vcocal_nphy(pi);
+}
+
+void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi)
+{
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_EN, 0x01, 0x0);
+ mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x04, 0x0);
+ mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x04,
+ (1 << 2));
+ mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_EN, 0x01, 0x01);
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_VCOCAL12, 0x0);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x38);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x18);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x38);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x39);
+ }
+
+ udelay(300);
+}
+
+#define MAX_205x_RCAL_WAITLOOPS 10000
+
+static u16 wlc_phy_radio205x_rcal(phy_info_t *pi)
+{
+ u16 rcal_reg = 0;
+ int i;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ if (pi->pubpi.radiorev == 5) {
+
+ and_phy_reg(pi, 0x342, ~(0x1 << 1));
+
+ udelay(10);
+
+ mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x1);
+ mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
+ 0x1);
+ }
+ mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x1);
+
+ udelay(10);
+
+ mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x3, 0x3);
+
+ for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
+ rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS);
+ if (rcal_reg & 0x1) {
+ break;
+ }
+ udelay(100);
+ }
+
+ if (WARN(i == MAX_205x_RCAL_WAITLOOPS,
+ "HW error: radio calib2"))
+ return 0;
+
+ mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x2, 0x0);
+
+ rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS) & 0x3e;
+
+ mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x0);
+ if (pi->pubpi.radiorev == 5) {
+
+ mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x0);
+ mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
+ 0x0);
+ }
+
+ if ((pi->pubpi.radiorev <= 4) || (pi->pubpi.radiorev == 6)) {
+
+ mod_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG, 0x3c,
+ rcal_reg);
+ mod_radio_reg(pi, RADIO_2057_BANDGAP_RCAL_TRIM, 0xf0,
+ rcal_reg << 2);
+ }
+
+ } else if (NREV_IS(pi->pubpi.phy_rev, 3)) {
+ u16 savereg;
+
+ savereg =
+ read_radio_reg(pi,
+ RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN);
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
+ savereg | 0x7);
+ udelay(10);
+
+ write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
+ 0x1);
+ udelay(10);
+
+ write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
+ 0x9);
+
+ for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
+ rcal_reg = read_radio_reg(pi,
+ RADIO_2056_SYN_RCAL_CODE_OUT |
+ RADIO_2056_SYN);
+ if (rcal_reg & 0x80) {
+ break;
+ }
+ udelay(100);
+ }
+
+ if (WARN(i == MAX_205x_RCAL_WAITLOOPS,
+ "HW error: radio calib3"))
+ return 0;
+
+ write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
+ 0x1);
+
+ rcal_reg =
+ read_radio_reg(pi,
+ RADIO_2056_SYN_RCAL_CODE_OUT |
+ RADIO_2056_SYN);
+
+ write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
+ 0x0);
+
+ write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
+ savereg);
+
+ return rcal_reg & 0x1f;
+ }
+ return rcal_reg & 0x3e;
+}
+
+static void
+wlc_phy_chanspec_radio2057_setup(phy_info_t *pi,
+ const chan_info_nphy_radio2057_t *ci,
+ const chan_info_nphy_radio2057_rev5_t *ci2)
+{
+ int coreNum;
+ u16 txmix2g_tune_boost_pu = 0;
+ u16 pad2g_tune_pus = 0;
+
+ if (pi->pubpi.radiorev == 5) {
+
+ write_radio_reg(pi,
+ RADIO_2057_VCOCAL_COUNTVAL0,
+ ci2->RF_vcocal_countval0);
+ write_radio_reg(pi, RADIO_2057_VCOCAL_COUNTVAL1,
+ ci2->RF_vcocal_countval1);
+ write_radio_reg(pi, RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE,
+ ci2->RF_rfpll_refmaster_sparextalsize);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
+ ci2->RF_rfpll_loopfilter_r1);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
+ ci2->RF_rfpll_loopfilter_c2);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
+ ci2->RF_rfpll_loopfilter_c1);
+ write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC,
+ ci2->RF_cp_kpd_idac);
+ write_radio_reg(pi, RADIO_2057_RFPLL_MMD0, ci2->RF_rfpll_mmd0);
+ write_radio_reg(pi, RADIO_2057_RFPLL_MMD1, ci2->RF_rfpll_mmd1);
+ write_radio_reg(pi,
+ RADIO_2057_VCOBUF_TUNE, ci2->RF_vcobuf_tune);
+ write_radio_reg(pi,
+ RADIO_2057_LOGEN_MX2G_TUNE,
+ ci2->RF_logen_mx2g_tune);
+ write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF2G_TUNE,
+ ci2->RF_logen_indbuf2g_tune);
+
+ write_radio_reg(pi,
+ RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
+ ci2->RF_txmix2g_tune_boost_pu_core0);
+ write_radio_reg(pi,
+ RADIO_2057_PAD2G_TUNE_PUS_CORE0,
+ ci2->RF_pad2g_tune_pus_core0);
+ write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE0,
+ ci2->RF_lna2g_tune_core0);
+
+ write_radio_reg(pi,
+ RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
+ ci2->RF_txmix2g_tune_boost_pu_core1);
+ write_radio_reg(pi,
+ RADIO_2057_PAD2G_TUNE_PUS_CORE1,
+ ci2->RF_pad2g_tune_pus_core1);
+ write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE1,
+ ci2->RF_lna2g_tune_core1);
+
+ } else {
+
+ write_radio_reg(pi,
+ RADIO_2057_VCOCAL_COUNTVAL0,
+ ci->RF_vcocal_countval0);
+ write_radio_reg(pi, RADIO_2057_VCOCAL_COUNTVAL1,
+ ci->RF_vcocal_countval1);
+ write_radio_reg(pi, RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE,
+ ci->RF_rfpll_refmaster_sparextalsize);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
+ ci->RF_rfpll_loopfilter_r1);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
+ ci->RF_rfpll_loopfilter_c2);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
+ ci->RF_rfpll_loopfilter_c1);
+ write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, ci->RF_cp_kpd_idac);
+ write_radio_reg(pi, RADIO_2057_RFPLL_MMD0, ci->RF_rfpll_mmd0);
+ write_radio_reg(pi, RADIO_2057_RFPLL_MMD1, ci->RF_rfpll_mmd1);
+ write_radio_reg(pi, RADIO_2057_VCOBUF_TUNE, ci->RF_vcobuf_tune);
+ write_radio_reg(pi,
+ RADIO_2057_LOGEN_MX2G_TUNE,
+ ci->RF_logen_mx2g_tune);
+ write_radio_reg(pi, RADIO_2057_LOGEN_MX5G_TUNE,
+ ci->RF_logen_mx5g_tune);
+ write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF2G_TUNE,
+ ci->RF_logen_indbuf2g_tune);
+ write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF5G_TUNE,
+ ci->RF_logen_indbuf5g_tune);
+
+ write_radio_reg(pi,
+ RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
+ ci->RF_txmix2g_tune_boost_pu_core0);
+ write_radio_reg(pi,
+ RADIO_2057_PAD2G_TUNE_PUS_CORE0,
+ ci->RF_pad2g_tune_pus_core0);
+ write_radio_reg(pi, RADIO_2057_PGA_BOOST_TUNE_CORE0,
+ ci->RF_pga_boost_tune_core0);
+ write_radio_reg(pi, RADIO_2057_TXMIX5G_BOOST_TUNE_CORE0,
+ ci->RF_txmix5g_boost_tune_core0);
+ write_radio_reg(pi, RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE0,
+ ci->RF_pad5g_tune_misc_pus_core0);
+ write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE0,
+ ci->RF_lna2g_tune_core0);
+ write_radio_reg(pi, RADIO_2057_LNA5G_TUNE_CORE0,
+ ci->RF_lna5g_tune_core0);
+
+ write_radio_reg(pi,
+ RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
+ ci->RF_txmix2g_tune_boost_pu_core1);
+ write_radio_reg(pi,
+ RADIO_2057_PAD2G_TUNE_PUS_CORE1,
+ ci->RF_pad2g_tune_pus_core1);
+ write_radio_reg(pi, RADIO_2057_PGA_BOOST_TUNE_CORE1,
+ ci->RF_pga_boost_tune_core1);
+ write_radio_reg(pi, RADIO_2057_TXMIX5G_BOOST_TUNE_CORE1,
+ ci->RF_txmix5g_boost_tune_core1);
+ write_radio_reg(pi, RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE1,
+ ci->RF_pad5g_tune_misc_pus_core1);
+ write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE1,
+ ci->RF_lna2g_tune_core1);
+ write_radio_reg(pi, RADIO_2057_LNA5G_TUNE_CORE1,
+ ci->RF_lna5g_tune_core1);
+ }
+
+ if ((pi->pubpi.radiorev <= 4) || (pi->pubpi.radiorev == 6)) {
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
+ 0x3f);
+ write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
+ 0x8);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
+ 0x8);
+ } else {
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
+ 0x1f);
+ write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
+ 0x8);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
+ 0x8);
+ }
+ } else if ((pi->pubpi.radiorev == 5) || (pi->pubpi.radiorev == 7) ||
+ (pi->pubpi.radiorev == 8)) {
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
+ 0x1b);
+ write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x30);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
+ 0xa);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
+ 0xa);
+ } else {
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
+ 0x1f);
+ write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
+ 0x8);
+ write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
+ 0x8);
+ }
+
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (PHY_IPA(pi)) {
+ if (pi->pubpi.radiorev == 3) {
+ txmix2g_tune_boost_pu = 0x6b;
+ }
+
+ if (pi->pubpi.radiorev == 5)
+ pad2g_tune_pus = 0x73;
+
+ } else {
+ if (pi->pubpi.radiorev != 5) {
+ pad2g_tune_pus = 0x3;
+
+ txmix2g_tune_boost_pu = 0x61;
+ }
+ }
+
+ for (coreNum = 0; coreNum <= 1; coreNum++) {
+
+ if (txmix2g_tune_boost_pu != 0)
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
+ TXMIX2G_TUNE_BOOST_PU,
+ txmix2g_tune_boost_pu);
+
+ if (pad2g_tune_pus != 0)
+ WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
+ PAD2G_TUNE_PUS,
+ pad2g_tune_pus);
+ }
+ }
+
+ udelay(50);
+
+ wlc_phy_radio205x_vcocal_nphy(pi);
+}
+
+static u16 wlc_phy_radio2057_rccal(phy_info_t *pi)
+{
+ u16 rccal_valid;
+ int i;
+ bool chip43226_6362A0;
+
+ chip43226_6362A0 = ((pi->pubpi.radiorev == 3)
+ || (pi->pubpi.radiorev == 4)
+ || (pi->pubpi.radiorev == 6));
+
+ rccal_valid = 0;
+ if (chip43226_6362A0) {
+ write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x61);
+ write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xc0);
+ } else {
+ write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x61);
+
+ write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xe9);
+ }
+ write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
+ write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
+
+ for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
+ rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
+ if (rccal_valid & 0x2) {
+ break;
+ }
+ udelay(500);
+ }
+
+ write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
+
+ rccal_valid = 0;
+ if (chip43226_6362A0) {
+ write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x69);
+ write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xb0);
+ } else {
+ write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x69);
+
+ write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xd5);
+ }
+ write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
+ write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
+
+ for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
+ rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
+ if (rccal_valid & 0x2) {
+ break;
+ }
+ udelay(500);
+ }
+
+ write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
+
+ rccal_valid = 0;
+ if (chip43226_6362A0) {
+ write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x73);
+
+ write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x28);
+ write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xb0);
+ } else {
+ write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x73);
+ write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
+ write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0x99);
+ }
+ write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
+
+ for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
+ rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
+ if (rccal_valid & 0x2) {
+ break;
+ }
+ udelay(500);
+ }
+
+ if (WARN(!(rccal_valid & 0x2), "HW error: radio calib4"))
+ return 0;
+
+ write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
+
+ return rccal_valid;
+}
+
+static void
+wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, u16 reduction_factr)
+{
+ if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
+ if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) &&
+ CHSPEC_IS40(pi->radio_chanspec)) {
+ if (!pi->nphy_anarxlpf_adjusted) {
+ write_radio_reg(pi,
+ (RADIO_2056_RX_RXLPF_RCCAL_LPC |
+ RADIO_2056_RX0),
+ ((pi->nphy_rccal_value +
+ reduction_factr) | 0x80));
+
+ pi->nphy_anarxlpf_adjusted = true;
+ }
+ } else {
+ if (pi->nphy_anarxlpf_adjusted) {
+ write_radio_reg(pi,
+ (RADIO_2056_RX_RXLPF_RCCAL_LPC |
+ RADIO_2056_RX0),
+ (pi->nphy_rccal_value | 0x80));
+
+ pi->nphy_anarxlpf_adjusted = false;
+ }
+ }
+ }
+}
+
+static void
+wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *tone_id_buf,
+ u32 *noise_var_buf)
+{
+ int i;
+ u32 offset;
+ int tone_id;
+ int tbllen =
+ CHSPEC_IS40(pi->
+ radio_chanspec) ? NPHY_NOISEVAR_TBLLEN40 :
+ NPHY_NOISEVAR_TBLLEN20;
+
+ if (pi->nphy_noisevars_adjusted) {
+ for (i = 0; i < pi->nphy_saved_noisevars.bufcount; i++) {
+ tone_id = pi->nphy_saved_noisevars.tone_id[i];
+ offset = (tone_id >= 0) ?
+ ((tone_id * 2) + 1) : (tbllen + (tone_id * 2) + 1);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
+ offset, 32,
+ (void *)&pi->
+ nphy_saved_noisevars.
+ min_noise_vars[i]);
+ }
+
+ pi->nphy_saved_noisevars.bufcount = 0;
+ pi->nphy_noisevars_adjusted = false;
+ }
+
+ if ((noise_var_buf != NULL) && (tone_id_buf != NULL)) {
+ pi->nphy_saved_noisevars.bufcount = 0;
+
+ for (i = 0; i < ntones; i++) {
+ tone_id = tone_id_buf[i];
+ offset = (tone_id >= 0) ?
+ ((tone_id * 2) + 1) : (tbllen + (tone_id * 2) + 1);
+ pi->nphy_saved_noisevars.tone_id[i] = tone_id;
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
+ offset, 32,
+ &pi->nphy_saved_noisevars.
+ min_noise_vars[i]);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
+ offset, 32,
+ (void *)&noise_var_buf[i]);
+ pi->nphy_saved_noisevars.bufcount++;
+ }
+
+ pi->nphy_noisevars_adjusted = true;
+ }
+}
+
+static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr)
+{
+ u16 regval;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) &&
+ CHSPEC_IS40(pi->radio_chanspec)) {
+ if (!pi->nphy_crsminpwr_adjusted) {
+ regval = read_phy_reg(pi, 0x27d);
+ pi->nphy_crsminpwr[0] = regval & 0xff;
+ regval &= 0xff00;
+ regval |= (u16) minpwr;
+ write_phy_reg(pi, 0x27d, regval);
+
+ regval = read_phy_reg(pi, 0x280);
+ pi->nphy_crsminpwr[1] = regval & 0xff;
+ regval &= 0xff00;
+ regval |= (u16) minpwr;
+ write_phy_reg(pi, 0x280, regval);
+
+ regval = read_phy_reg(pi, 0x283);
+ pi->nphy_crsminpwr[2] = regval & 0xff;
+ regval &= 0xff00;
+ regval |= (u16) minpwr;
+ write_phy_reg(pi, 0x283, regval);
+
+ pi->nphy_crsminpwr_adjusted = true;
+ }
+ } else {
+ if (pi->nphy_crsminpwr_adjusted) {
+ regval = read_phy_reg(pi, 0x27d);
+ regval &= 0xff00;
+ regval |= pi->nphy_crsminpwr[0];
+ write_phy_reg(pi, 0x27d, regval);
+
+ regval = read_phy_reg(pi, 0x280);
+ regval &= 0xff00;
+ regval |= pi->nphy_crsminpwr[1];
+ write_phy_reg(pi, 0x280, regval);
+
+ regval = read_phy_reg(pi, 0x283);
+ regval &= 0xff00;
+ regval |= pi->nphy_crsminpwr[2];
+ write_phy_reg(pi, 0x283, regval);
+
+ pi->nphy_crsminpwr_adjusted = false;
+ }
+ }
+ }
+}
+
+static void wlc_phy_txlpfbw_nphy(phy_info_t *pi)
+{
+ u8 tx_lpf_bw = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ tx_lpf_bw = 3;
+ } else {
+ tx_lpf_bw = 1;
+ }
+
+ if (PHY_IPA(pi)) {
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ tx_lpf_bw = 5;
+ } else {
+ tx_lpf_bw = 4;
+ }
+ }
+ write_phy_reg(pi, 0xe8,
+ (tx_lpf_bw << 0) |
+ (tx_lpf_bw << 3) |
+ (tx_lpf_bw << 6) | (tx_lpf_bw << 9));
+
+ if (PHY_IPA(pi)) {
+
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ tx_lpf_bw = 4;
+ } else {
+ tx_lpf_bw = 1;
+ }
+
+ write_phy_reg(pi, 0xe9,
+ (tx_lpf_bw << 0) |
+ (tx_lpf_bw << 3) |
+ (tx_lpf_bw << 6) | (tx_lpf_bw << 9));
+ }
+ }
+}
+
+static void wlc_phy_spurwar_nphy(phy_info_t *pi)
+{
+ u16 cur_channel = 0;
+ int nphy_adj_tone_id_buf[] = { 57, 58 };
+ u32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff };
+ bool isAdjustNoiseVar = false;
+ uint numTonesAdjust = 0;
+ u32 tempval = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ cur_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
+
+ if (pi->nphy_gband_spurwar_en) {
+
+ wlc_phy_adjust_rx_analpfbw_nphy(pi,
+ NPHY_ANARXLPFBW_REDUCTIONFACT);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if ((cur_channel == 11)
+ && CHSPEC_IS40(pi->radio_chanspec)) {
+
+ wlc_phy_adjust_min_noisevar_nphy(pi, 2,
+ nphy_adj_tone_id_buf,
+ nphy_adj_noise_var_buf);
+ } else {
+
+ wlc_phy_adjust_min_noisevar_nphy(pi, 0,
+ NULL,
+ NULL);
+ }
+ }
+ wlc_phy_adjust_crsminpwr_nphy(pi,
+ NPHY_ADJUSTED_MINCRSPOWER);
+ }
+
+ if ((pi->nphy_gband_spurwar2_en)
+ && CHSPEC_IS2G(pi->radio_chanspec)) {
+
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ switch (cur_channel) {
+ case 3:
+ nphy_adj_tone_id_buf[0] = 57;
+ nphy_adj_tone_id_buf[1] = 58;
+ nphy_adj_noise_var_buf[0] = 0x22f;
+ nphy_adj_noise_var_buf[1] = 0x25f;
+ isAdjustNoiseVar = true;
+ break;
+ case 4:
+ nphy_adj_tone_id_buf[0] = 41;
+ nphy_adj_tone_id_buf[1] = 42;
+ nphy_adj_noise_var_buf[0] = 0x22f;
+ nphy_adj_noise_var_buf[1] = 0x25f;
+ isAdjustNoiseVar = true;
+ break;
+ case 5:
+ nphy_adj_tone_id_buf[0] = 25;
+ nphy_adj_tone_id_buf[1] = 26;
+ nphy_adj_noise_var_buf[0] = 0x24f;
+ nphy_adj_noise_var_buf[1] = 0x25f;
+ isAdjustNoiseVar = true;
+ break;
+ case 6:
+ nphy_adj_tone_id_buf[0] = 9;
+ nphy_adj_tone_id_buf[1] = 10;
+ nphy_adj_noise_var_buf[0] = 0x22f;
+ nphy_adj_noise_var_buf[1] = 0x24f;
+ isAdjustNoiseVar = true;
+ break;
+ case 7:
+ nphy_adj_tone_id_buf[0] = 121;
+ nphy_adj_tone_id_buf[1] = 122;
+ nphy_adj_noise_var_buf[0] = 0x18f;
+ nphy_adj_noise_var_buf[1] = 0x24f;
+ isAdjustNoiseVar = true;
+ break;
+ case 8:
+ nphy_adj_tone_id_buf[0] = 105;
+ nphy_adj_tone_id_buf[1] = 106;
+ nphy_adj_noise_var_buf[0] = 0x22f;
+ nphy_adj_noise_var_buf[1] = 0x25f;
+ isAdjustNoiseVar = true;
+ break;
+ case 9:
+ nphy_adj_tone_id_buf[0] = 89;
+ nphy_adj_tone_id_buf[1] = 90;
+ nphy_adj_noise_var_buf[0] = 0x22f;
+ nphy_adj_noise_var_buf[1] = 0x24f;
+ isAdjustNoiseVar = true;
+ break;
+ case 10:
+ nphy_adj_tone_id_buf[0] = 73;
+ nphy_adj_tone_id_buf[1] = 74;
+ nphy_adj_noise_var_buf[0] = 0x22f;
+ nphy_adj_noise_var_buf[1] = 0x24f;
+ isAdjustNoiseVar = true;
+ break;
+ default:
+ isAdjustNoiseVar = false;
+ break;
+ }
+ }
+
+ if (isAdjustNoiseVar) {
+ numTonesAdjust = sizeof(nphy_adj_tone_id_buf) /
+ sizeof(nphy_adj_tone_id_buf[0]);
+
+ wlc_phy_adjust_min_noisevar_nphy(pi,
+ numTonesAdjust,
+ nphy_adj_tone_id_buf,
+ nphy_adj_noise_var_buf);
+
+ tempval = 0;
+
+ } else {
+
+ wlc_phy_adjust_min_noisevar_nphy(pi, 0, NULL,
+ NULL);
+ }
+ }
+
+ if ((pi->nphy_aband_spurwar_en) &&
+ (CHSPEC_IS5G(pi->radio_chanspec))) {
+ switch (cur_channel) {
+ case 54:
+ nphy_adj_tone_id_buf[0] = 32;
+ nphy_adj_noise_var_buf[0] = 0x25f;
+ break;
+ case 38:
+ case 102:
+ case 118:
+ if ((pi->sh->chip == BCM4716_CHIP_ID) &&
+ (pi->sh->chippkg == BCM4717_PKG_ID)) {
+ nphy_adj_tone_id_buf[0] = 32;
+ nphy_adj_noise_var_buf[0] = 0x21f;
+ } else {
+ nphy_adj_tone_id_buf[0] = 0;
+ nphy_adj_noise_var_buf[0] = 0x0;
+ }
+ break;
+ case 134:
+ nphy_adj_tone_id_buf[0] = 32;
+ nphy_adj_noise_var_buf[0] = 0x21f;
+ break;
+ case 151:
+ nphy_adj_tone_id_buf[0] = 16;
+ nphy_adj_noise_var_buf[0] = 0x23f;
+ break;
+ case 153:
+ case 161:
+ nphy_adj_tone_id_buf[0] = 48;
+ nphy_adj_noise_var_buf[0] = 0x23f;
+ break;
+ default:
+ nphy_adj_tone_id_buf[0] = 0;
+ nphy_adj_noise_var_buf[0] = 0x0;
+ break;
+ }
+
+ if (nphy_adj_tone_id_buf[0]
+ && nphy_adj_noise_var_buf[0]) {
+ wlc_phy_adjust_min_noisevar_nphy(pi, 1,
+ nphy_adj_tone_id_buf,
+ nphy_adj_noise_var_buf);
+ } else {
+ wlc_phy_adjust_min_noisevar_nphy(pi, 0, NULL,
+ NULL);
+ }
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+ }
+}
+
+static void
+wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec,
+ const nphy_sfo_cfg_t *ci)
+{
+ u16 val;
+
+ val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
+ if (CHSPEC_IS5G(chanspec) && !val) {
+
+ val = R_REG(&pi->regs->psm_phy_hdr_param);
+ W_REG(&pi->regs->psm_phy_hdr_param,
+ (val | MAC_PHY_FORCE_CLK));
+
+ or_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
+ (BBCFG_RESETCCA | BBCFG_RESETRX));
+
+ W_REG(&pi->regs->psm_phy_hdr_param, val);
+
+ or_phy_reg(pi, 0x09, NPHY_BandControl_currentBand);
+ } else if (!CHSPEC_IS5G(chanspec) && val) {
+
+ and_phy_reg(pi, 0x09, ~NPHY_BandControl_currentBand);
+
+ val = R_REG(&pi->regs->psm_phy_hdr_param);
+ W_REG(&pi->regs->psm_phy_hdr_param,
+ (val | MAC_PHY_FORCE_CLK));
+
+ and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
+ (u16) (~(BBCFG_RESETCCA | BBCFG_RESETRX)));
+
+ W_REG(&pi->regs->psm_phy_hdr_param, val);
+ }
+
+ write_phy_reg(pi, 0x1ce, ci->PHY_BW1a);
+ write_phy_reg(pi, 0x1cf, ci->PHY_BW2);
+ write_phy_reg(pi, 0x1d0, ci->PHY_BW3);
+
+ write_phy_reg(pi, 0x1d1, ci->PHY_BW4);
+ write_phy_reg(pi, 0x1d2, ci->PHY_BW5);
+ write_phy_reg(pi, 0x1d3, ci->PHY_BW6);
+
+ if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
+ wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_ofdm_en, 0);
+
+ or_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, 0x800);
+ } else {
+ wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_ofdm_en,
+ NPHY_ClassifierCtrl_ofdm_en);
+
+ if (CHSPEC_IS2G(chanspec))
+ and_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, ~0x840);
+ }
+
+ if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
+ wlc_phy_txpwr_fixpower_nphy(pi);
+ }
+
+ if (NREV_LT(pi->pubpi.phy_rev, 3)) {
+
+ wlc_phy_adjust_lnagaintbl_nphy(pi);
+ }
+
+ wlc_phy_txlpfbw_nphy(pi);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)
+ && (pi->phy_spuravoid != SPURAVOID_DISABLE)) {
+ u8 spuravoid = 0;
+
+ val = CHSPEC_CHANNEL(chanspec);
+ if (!CHSPEC_IS40(pi->radio_chanspec)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if ((val == 13) || (val == 14) || (val == 153)) {
+ spuravoid = 1;
+ }
+ } else {
+
+ if (((val >= 5) && (val <= 8)) || (val == 13)
+ || (val == 14)) {
+ spuravoid = 1;
+ }
+ }
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (val == 54) {
+ spuravoid = 1;
+ }
+ } else {
+
+ if (pi->nphy_aband_spurwar_en &&
+ ((val == 38) || (val == 102)
+ || (val == 118))) {
+ if ((pi->sh->chip ==
+ BCM4716_CHIP_ID)
+ && (pi->sh->chippkg ==
+ BCM4717_PKG_ID)) {
+ spuravoid = 0;
+ } else {
+ spuravoid = 1;
+ }
+ }
+ }
+ }
+
+ if (pi->phy_spuravoid == SPURAVOID_FORCEON)
+ spuravoid = 1;
+
+ if ((pi->sh->chip == BCM4716_CHIP_ID) ||
+ (pi->sh->chip == BCM47162_CHIP_ID)) {
+ si_pmu_spuravoid(pi->sh->sih, spuravoid);
+ } else {
+ wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
+ si_pmu_spuravoid(pi->sh->sih, spuravoid);
+ wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
+ }
+
+ if ((pi->sh->chip == BCM43224_CHIP_ID) ||
+ (pi->sh->chip == BCM43225_CHIP_ID) ||
+ (pi->sh->chip == BCM43421_CHIP_ID)) {
+
+ if (spuravoid == 1) {
+
+ W_REG(&pi->regs->tsf_clk_frac_l,
+ 0x5341);
+ W_REG(&pi->regs->tsf_clk_frac_h,
+ 0x8);
+ } else {
+
+ W_REG(&pi->regs->tsf_clk_frac_l,
+ 0x8889);
+ W_REG(&pi->regs->tsf_clk_frac_h,
+ 0x8);
+ }
+ }
+
+ if (!((pi->sh->chip == BCM4716_CHIP_ID) ||
+ (pi->sh->chip == BCM47162_CHIP_ID))) {
+ wlapi_bmac_core_phypll_reset(pi->sh->physhim);
+ }
+
+ mod_phy_reg(pi, 0x01, (0x1 << 15),
+ ((spuravoid > 0) ? (0x1 << 15) : 0));
+
+ wlc_phy_resetcca_nphy(pi);
+
+ pi->phy_isspuravoid = (spuravoid > 0);
+ }
+
+ if (NREV_LT(pi->pubpi.phy_rev, 7))
+ write_phy_reg(pi, 0x17e, 0x3830);
+
+ wlc_phy_spurwar_nphy(pi);
+}
+
+void wlc_phy_chanspec_set_nphy(phy_info_t *pi, chanspec_t chanspec)
+{
+ int freq;
+ chan_info_nphy_radio2057_t *t0 = NULL;
+ chan_info_nphy_radio205x_t *t1 = NULL;
+ chan_info_nphy_radio2057_rev5_t *t2 = NULL;
+ chan_info_nphy_2055_t *t3 = NULL;
+
+ if (NORADIO_ENAB(pi->pubpi)) {
+ return;
+ }
+
+ if (!wlc_phy_chan2freq_nphy
+ (pi, CHSPEC_CHANNEL(chanspec), &freq, &t0, &t1, &t2, &t3))
+ return;
+
+ wlc_phy_chanspec_radio_set((wlc_phy_t *) pi, chanspec);
+
+ if (CHSPEC_BW(chanspec) != pi->bw)
+ wlapi_bmac_bw_set(pi->sh->physhim, CHSPEC_BW(chanspec));
+
+ if (CHSPEC_IS40(chanspec)) {
+ if (CHSPEC_SB_UPPER(chanspec)) {
+ or_phy_reg(pi, 0xa0, BPHY_BAND_SEL_UP20);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ or_phy_reg(pi, 0x310, PRIM_SEL_UP20);
+ }
+ } else {
+ and_phy_reg(pi, 0xa0, ~BPHY_BAND_SEL_UP20);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ and_phy_reg(pi, 0x310,
+ (~PRIM_SEL_UP20 & 0xffff));
+ }
+ }
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ if ((pi->pubpi.radiorev <= 4)
+ || (pi->pubpi.radiorev == 6)) {
+ mod_radio_reg(pi, RADIO_2057_TIA_CONFIG_CORE0,
+ 0x2,
+ (CHSPEC_IS5G(chanspec) ? (1 << 1)
+ : 0));
+ mod_radio_reg(pi, RADIO_2057_TIA_CONFIG_CORE1,
+ 0x2,
+ (CHSPEC_IS5G(chanspec) ? (1 << 1)
+ : 0));
+ }
+
+ wlc_phy_chanspec_radio2057_setup(pi, t0, t2);
+ wlc_phy_chanspec_nphy_setup(pi, chanspec,
+ (pi->pubpi.radiorev ==
+ 5) ? (const nphy_sfo_cfg_t
+ *)&(t2->
+ PHY_BW1a)
+ : (const nphy_sfo_cfg_t *)
+ &(t0->PHY_BW1a));
+
+ } else {
+
+ mod_radio_reg(pi,
+ RADIO_2056_SYN_COM_CTRL | RADIO_2056_SYN,
+ 0x4,
+ (CHSPEC_IS5G(chanspec) ? (0x1 << 2) : 0));
+ wlc_phy_chanspec_radio2056_setup(pi, t1);
+
+ wlc_phy_chanspec_nphy_setup(pi, chanspec,
+ (const nphy_sfo_cfg_t *)
+ &(t1->PHY_BW1a));
+ }
+
+ } else {
+
+ mod_radio_reg(pi, RADIO_2055_MASTER_CNTRL1, 0x70,
+ (CHSPEC_IS5G(chanspec) ? (0x02 << 4)
+ : (0x05 << 4)));
+
+ wlc_phy_chanspec_radio2055_setup(pi, t3);
+ wlc_phy_chanspec_nphy_setup(pi, chanspec,
+ (const nphy_sfo_cfg_t *)&(t3->
+ PHY_BW1a));
+ }
+
+}
+
+static void wlc_phy_savecal_nphy(phy_info_t *pi)
+{
+ void *tbl_ptr;
+ int coreNum;
+ u16 *txcal_radio_regs = NULL;
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+
+ wlc_phy_rx_iq_coeffs_nphy(pi, 0,
+ &pi->calibration_cache.
+ rxcal_coeffs_2G);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ txcal_radio_regs =
+ pi->calibration_cache.txcal_radio_regs_2G;
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ pi->calibration_cache.txcal_radio_regs_2G[0] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_I |
+ RADIO_2056_TX0);
+ pi->calibration_cache.txcal_radio_regs_2G[1] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_Q |
+ RADIO_2056_TX0);
+ pi->calibration_cache.txcal_radio_regs_2G[2] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_I |
+ RADIO_2056_TX1);
+ pi->calibration_cache.txcal_radio_regs_2G[3] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_Q |
+ RADIO_2056_TX1);
+
+ pi->calibration_cache.txcal_radio_regs_2G[4] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_I |
+ RADIO_2056_TX0);
+ pi->calibration_cache.txcal_radio_regs_2G[5] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_Q |
+ RADIO_2056_TX0);
+ pi->calibration_cache.txcal_radio_regs_2G[6] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_I |
+ RADIO_2056_TX1);
+ pi->calibration_cache.txcal_radio_regs_2G[7] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_Q |
+ RADIO_2056_TX1);
+ } else {
+ pi->calibration_cache.txcal_radio_regs_2G[0] =
+ read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
+ pi->calibration_cache.txcal_radio_regs_2G[1] =
+ read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
+ pi->calibration_cache.txcal_radio_regs_2G[2] =
+ read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
+ pi->calibration_cache.txcal_radio_regs_2G[3] =
+ read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
+ }
+
+ pi->nphy_iqcal_chanspec_2G = pi->radio_chanspec;
+ tbl_ptr = pi->calibration_cache.txcal_coeffs_2G;
+ } else {
+
+ wlc_phy_rx_iq_coeffs_nphy(pi, 0,
+ &pi->calibration_cache.
+ rxcal_coeffs_5G);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ txcal_radio_regs =
+ pi->calibration_cache.txcal_radio_regs_5G;
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ pi->calibration_cache.txcal_radio_regs_5G[0] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_I |
+ RADIO_2056_TX0);
+ pi->calibration_cache.txcal_radio_regs_5G[1] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_Q |
+ RADIO_2056_TX0);
+ pi->calibration_cache.txcal_radio_regs_5G[2] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_I |
+ RADIO_2056_TX1);
+ pi->calibration_cache.txcal_radio_regs_5G[3] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_Q |
+ RADIO_2056_TX1);
+
+ pi->calibration_cache.txcal_radio_regs_5G[4] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_I |
+ RADIO_2056_TX0);
+ pi->calibration_cache.txcal_radio_regs_5G[5] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_Q |
+ RADIO_2056_TX0);
+ pi->calibration_cache.txcal_radio_regs_5G[6] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_I |
+ RADIO_2056_TX1);
+ pi->calibration_cache.txcal_radio_regs_5G[7] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_Q |
+ RADIO_2056_TX1);
+ } else {
+ pi->calibration_cache.txcal_radio_regs_5G[0] =
+ read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
+ pi->calibration_cache.txcal_radio_regs_5G[1] =
+ read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
+ pi->calibration_cache.txcal_radio_regs_5G[2] =
+ read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
+ pi->calibration_cache.txcal_radio_regs_5G[3] =
+ read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
+ }
+
+ pi->nphy_iqcal_chanspec_5G = pi->radio_chanspec;
+ tbl_ptr = pi->calibration_cache.txcal_coeffs_5G;
+ }
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ for (coreNum = 0; coreNum <= 1; coreNum++) {
+
+ txcal_radio_regs[2 * coreNum] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
+ LOFT_FINE_I);
+ txcal_radio_regs[2 * coreNum + 1] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
+ LOFT_FINE_Q);
+
+ txcal_radio_regs[2 * coreNum + 4] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
+ LOFT_COARSE_I);
+ txcal_radio_regs[2 * coreNum + 5] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
+ LOFT_COARSE_Q);
+ }
+ }
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 8, 80, 16, tbl_ptr);
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+static void wlc_phy_restorecal_nphy(phy_info_t *pi)
+{
+ u16 *loft_comp;
+ u16 txcal_coeffs_bphy[4];
+ u16 *tbl_ptr;
+ int coreNum;
+ u16 *txcal_radio_regs = NULL;
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (pi->nphy_iqcal_chanspec_2G == 0)
+ return;
+
+ tbl_ptr = pi->calibration_cache.txcal_coeffs_2G;
+ loft_comp = &pi->calibration_cache.txcal_coeffs_2G[5];
+ } else {
+ if (pi->nphy_iqcal_chanspec_5G == 0)
+ return;
+
+ tbl_ptr = pi->calibration_cache.txcal_coeffs_5G;
+ loft_comp = &pi->calibration_cache.txcal_coeffs_5G[5];
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80, 16,
+ (void *)tbl_ptr);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ txcal_coeffs_bphy[0] = tbl_ptr[0];
+ txcal_coeffs_bphy[1] = tbl_ptr[1];
+ txcal_coeffs_bphy[2] = tbl_ptr[2];
+ txcal_coeffs_bphy[3] = tbl_ptr[3];
+ } else {
+ txcal_coeffs_bphy[0] = 0;
+ txcal_coeffs_bphy[1] = 0;
+ txcal_coeffs_bphy[2] = 0;
+ txcal_coeffs_bphy[3] = 0;
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88, 16,
+ txcal_coeffs_bphy);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85, 16, loft_comp);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93, 16, loft_comp);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2))
+ wlc_phy_tx_iq_war_nphy(pi);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ txcal_radio_regs =
+ pi->calibration_cache.txcal_radio_regs_2G;
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_I |
+ RADIO_2056_TX0,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[0]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_Q |
+ RADIO_2056_TX0,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[1]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_I |
+ RADIO_2056_TX1,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[2]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_Q |
+ RADIO_2056_TX1,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[3]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_I |
+ RADIO_2056_TX0,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[4]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_Q |
+ RADIO_2056_TX0,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[5]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_I |
+ RADIO_2056_TX1,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[6]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_Q |
+ RADIO_2056_TX1,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[7]);
+ } else {
+ write_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[0]);
+ write_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[1]);
+ write_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[2]);
+ write_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM,
+ pi->calibration_cache.
+ txcal_radio_regs_2G[3]);
+ }
+
+ wlc_phy_rx_iq_coeffs_nphy(pi, 1,
+ &pi->calibration_cache.
+ rxcal_coeffs_2G);
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ txcal_radio_regs =
+ pi->calibration_cache.txcal_radio_regs_5G;
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_I |
+ RADIO_2056_TX0,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[0]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_Q |
+ RADIO_2056_TX0,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[1]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_I |
+ RADIO_2056_TX1,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[2]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_FINE_Q |
+ RADIO_2056_TX1,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[3]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_I |
+ RADIO_2056_TX0,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[4]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_Q |
+ RADIO_2056_TX0,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[5]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_I |
+ RADIO_2056_TX1,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[6]);
+ write_radio_reg(pi,
+ RADIO_2056_TX_LOFT_COARSE_Q |
+ RADIO_2056_TX1,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[7]);
+ } else {
+ write_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[0]);
+ write_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[1]);
+ write_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[2]);
+ write_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM,
+ pi->calibration_cache.
+ txcal_radio_regs_5G[3]);
+ }
+
+ wlc_phy_rx_iq_coeffs_nphy(pi, 1,
+ &pi->calibration_cache.
+ rxcal_coeffs_5G);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ for (coreNum = 0; coreNum <= 1; coreNum++) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
+ LOFT_FINE_I,
+ txcal_radio_regs[2 * coreNum]);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
+ LOFT_FINE_Q,
+ txcal_radio_regs[2 * coreNum + 1]);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
+ LOFT_COARSE_I,
+ txcal_radio_regs[2 * coreNum + 4]);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
+ LOFT_COARSE_Q,
+ txcal_radio_regs[2 * coreNum + 5]);
+ }
+ }
+}
+
+void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init)
+{
+ phy_info_t *pi = (phy_info_t *) ppi;
+ u16 mask = 0xfc00;
+ u32 mc = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7))
+ return;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ u16 v0 = 0x211, v1 = 0x222, v2 = 0x144, v3 = 0x188;
+
+ if (lut_init == false)
+ return;
+
+ if (pi->srom_fem2g.antswctrllut == 0) {
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 1, 0x02, 16, &v0);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 1, 0x03, 16, &v1);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 1, 0x08, 16, &v2);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 1, 0x0C, 16, &v3);
+ }
+
+ if (pi->srom_fem5g.antswctrllut == 0) {
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 1, 0x12, 16, &v0);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 1, 0x13, 16, &v1);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 1, 0x18, 16, &v2);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
+ 1, 0x1C, 16, &v3);
+ }
+ } else {
+
+ write_phy_reg(pi, 0xc8, 0x0);
+ write_phy_reg(pi, 0xc9, 0x0);
+
+ ai_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
+
+ mc = R_REG(&pi->regs->maccontrol);
+ mc &= ~MCTL_GPOUT_SEL_MASK;
+ W_REG(&pi->regs->maccontrol, mc);
+
+ OR_REG(&pi->regs->psm_gpio_oe, mask);
+
+ AND_REG(&pi->regs->psm_gpio_out, ~mask);
+
+ if (lut_init) {
+ write_phy_reg(pi, 0xf8, 0x02d8);
+ write_phy_reg(pi, 0xf9, 0x0301);
+ write_phy_reg(pi, 0xfa, 0x02d8);
+ write_phy_reg(pi, 0xfb, 0x0301);
+ }
+ }
+}
+
+u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val)
+{
+ u16 curr_ctl, new_ctl;
+ bool suspended = false;
+
+ if (D11REV_IS(pi->sh->corerev, 16)) {
+ suspended =
+ (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) ?
+ false : true;
+ if (!suspended)
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ }
+
+ curr_ctl = read_phy_reg(pi, 0xb0) & (0x7 << 0);
+
+ new_ctl = (curr_ctl & (~mask)) | (val & mask);
+
+ mod_phy_reg(pi, 0xb0, (0x7 << 0), new_ctl);
+
+ if (D11REV_IS(pi->sh->corerev, 16) && !suspended)
+ wlapi_enable_mac(pi->sh->physhim);
+
+ return new_ctl;
+}
+
+static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, u16 *vals)
+{
+
+ if (write == 0) {
+ vals[0] = read_phy_reg(pi, 0x2c);
+ vals[1] = read_phy_reg(pi, 0x42);
+ } else {
+ write_phy_reg(pi, 0x2c, vals[0]);
+ write_phy_reg(pi, 0x42, vals[1]);
+ }
+}
+
+void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd)
+{
+ u16 trigger_mask, status_mask;
+ u16 orig_RfseqCoreActv;
+
+ switch (cmd) {
+ case NPHY_RFSEQ_RX2TX:
+ trigger_mask = NPHY_RfseqTrigger_rx2tx;
+ status_mask = NPHY_RfseqStatus_rx2tx;
+ break;
+ case NPHY_RFSEQ_TX2RX:
+ trigger_mask = NPHY_RfseqTrigger_tx2rx;
+ status_mask = NPHY_RfseqStatus_tx2rx;
+ break;
+ case NPHY_RFSEQ_RESET2RX:
+ trigger_mask = NPHY_RfseqTrigger_reset2rx;
+ status_mask = NPHY_RfseqStatus_reset2rx;
+ break;
+ case NPHY_RFSEQ_UPDATEGAINH:
+ trigger_mask = NPHY_RfseqTrigger_updategainh;
+ status_mask = NPHY_RfseqStatus_updategainh;
+ break;
+ case NPHY_RFSEQ_UPDATEGAINL:
+ trigger_mask = NPHY_RfseqTrigger_updategainl;
+ status_mask = NPHY_RfseqStatus_updategainl;
+ break;
+ case NPHY_RFSEQ_UPDATEGAINU:
+ trigger_mask = NPHY_RfseqTrigger_updategainu;
+ status_mask = NPHY_RfseqStatus_updategainu;
+ break;
+ default:
+ return;
+ }
+
+ orig_RfseqCoreActv = read_phy_reg(pi, 0xa1);
+ or_phy_reg(pi, 0xa1,
+ (NPHY_RfseqMode_CoreActv_override |
+ NPHY_RfseqMode_Trigger_override));
+ or_phy_reg(pi, 0xa3, trigger_mask);
+ SPINWAIT((read_phy_reg(pi, 0xa4) & status_mask), 200000);
+ write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
+ WARN(read_phy_reg(pi, 0xa4) & status_mask, "HW error in rf");
+}
+
+static void
+wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *events, u8 *dlys,
+ u8 len)
+{
+ u32 t1_offset, t2_offset;
+ u8 ctr;
+ u8 end_event =
+ NREV_GE(pi->pubpi.phy_rev,
+ 3) ? NPHY_REV3_RFSEQ_CMD_END : NPHY_RFSEQ_CMD_END;
+ u8 end_dly = 1;
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ t1_offset = cmd << 4;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, len, t1_offset, 8,
+ events);
+ t2_offset = t1_offset + 0x080;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, len, t2_offset, 8,
+ dlys);
+
+ for (ctr = len; ctr < 16; ctr++) {
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
+ t1_offset + ctr, 8, &end_event);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
+ t2_offset + ctr, 8, &end_dly);
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+static u16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, u16 offset)
+{
+ u16 lpf_bw_ctl_val = 0;
+ u16 rx2tx_lpf_rc_lut_offset = 0;
+
+ if (offset == 0) {
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ rx2tx_lpf_rc_lut_offset = 0x159;
+ } else {
+ rx2tx_lpf_rc_lut_offset = 0x154;
+ }
+ } else {
+ rx2tx_lpf_rc_lut_offset = offset;
+ }
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
+ (u32) rx2tx_lpf_rc_lut_offset, 16,
+ &lpf_bw_ctl_val);
+
+ lpf_bw_ctl_val = lpf_bw_ctl_val & 0x7;
+
+ return lpf_bw_ctl_val;
+}
+
+static void
+wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, u16 field, u16 value,
+ u8 core_mask, u8 off, u8 override_id)
+{
+ u8 core_num;
+ u16 addr = 0, en_addr = 0, val_addr = 0, en_mask = 0, val_mask = 0;
+ u8 val_shift = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ en_mask = field;
+ for (core_num = 0; core_num < 2; core_num++) {
+ if (override_id == NPHY_REV7_RFCTRLOVERRIDE_ID0) {
+
+ switch (field) {
+ case (0x1 << 2):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a :
+ 0x7d;
+ val_mask = (0x1 << 1);
+ val_shift = 1;
+ break;
+ case (0x1 << 3):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a :
+ 0x7d;
+ val_mask = (0x1 << 2);
+ val_shift = 2;
+ break;
+ case (0x1 << 4):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a :
+ 0x7d;
+ val_mask = (0x1 << 4);
+ val_shift = 4;
+ break;
+ case (0x1 << 5):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a :
+ 0x7d;
+ val_mask = (0x1 << 5);
+ val_shift = 5;
+ break;
+ case (0x1 << 6):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a :
+ 0x7d;
+ val_mask = (0x1 << 6);
+ val_shift = 6;
+ break;
+ case (0x1 << 7):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a :
+ 0x7d;
+ val_mask = (0x1 << 7);
+ val_shift = 7;
+ break;
+ case (0x1 << 10):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0xf8 :
+ 0xfa;
+ val_mask = (0x7 << 4);
+ val_shift = 4;
+ break;
+ case (0x1 << 11):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7b :
+ 0x7e;
+ val_mask = (0xffff << 0);
+ val_shift = 0;
+ break;
+ case (0x1 << 12):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7c :
+ 0x7f;
+ val_mask = (0xffff << 0);
+ val_shift = 0;
+ break;
+ case (0x3 << 13):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x348 :
+ 0x349;
+ val_mask = (0xff << 0);
+ val_shift = 0;
+ break;
+ case (0x1 << 13):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x348 :
+ 0x349;
+ val_mask = (0xf << 0);
+ val_shift = 0;
+ break;
+ default:
+ addr = 0xffff;
+ break;
+ }
+ } else if (override_id == NPHY_REV7_RFCTRLOVERRIDE_ID1) {
+
+ switch (field) {
+ case (0x1 << 1):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 1);
+ val_shift = 1;
+ break;
+ case (0x1 << 3):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 3);
+ val_shift = 3;
+ break;
+ case (0x1 << 5):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 5);
+ val_shift = 5;
+ break;
+ case (0x1 << 4):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 4);
+ val_shift = 4;
+ break;
+ case (0x1 << 2):
+
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 2);
+ val_shift = 2;
+ break;
+ case (0x1 << 7):
+
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x7 << 8);
+ val_shift = 8;
+ break;
+ case (0x1 << 11):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 14);
+ val_shift = 14;
+ break;
+ case (0x1 << 10):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 13);
+ val_shift = 13;
+ break;
+ case (0x1 << 9):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 12);
+ val_shift = 12;
+ break;
+ case (0x1 << 8):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 11);
+ val_shift = 11;
+ break;
+ case (0x1 << 6):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 6);
+ val_shift = 6;
+ break;
+ case (0x1 << 0):
+ en_addr = (core_num == 0) ? 0x342 :
+ 0x343;
+ val_addr = (core_num == 0) ? 0x340 :
+ 0x341;
+ val_mask = (0x1 << 0);
+ val_shift = 0;
+ break;
+ default:
+ addr = 0xffff;
+ break;
+ }
+ } else if (override_id == NPHY_REV7_RFCTRLOVERRIDE_ID2) {
+
+ switch (field) {
+ case (0x1 << 3):
+ en_addr = (core_num == 0) ? 0x346 :
+ 0x347;
+ val_addr = (core_num == 0) ? 0x344 :
+ 0x345;
+ val_mask = (0x1 << 3);
+ val_shift = 3;
+ break;
+ case (0x1 << 1):
+ en_addr = (core_num == 0) ? 0x346 :
+ 0x347;
+ val_addr = (core_num == 0) ? 0x344 :
+ 0x345;
+ val_mask = (0x1 << 1);
+ val_shift = 1;
+ break;
+ case (0x1 << 0):
+ en_addr = (core_num == 0) ? 0x346 :
+ 0x347;
+ val_addr = (core_num == 0) ? 0x344 :
+ 0x345;
+ val_mask = (0x1 << 0);
+ val_shift = 0;
+ break;
+ case (0x1 << 2):
+ en_addr = (core_num == 0) ? 0x346 :
+ 0x347;
+ val_addr = (core_num == 0) ? 0x344 :
+ 0x345;
+ val_mask = (0x1 << 2);
+ val_shift = 2;
+ break;
+ case (0x1 << 4):
+ en_addr = (core_num == 0) ? 0x346 :
+ 0x347;
+ val_addr = (core_num == 0) ? 0x344 :
+ 0x345;
+ val_mask = (0x1 << 4);
+ val_shift = 4;
+ break;
+ default:
+ addr = 0xffff;
+ break;
+ }
+ }
+
+ if (off) {
+ and_phy_reg(pi, en_addr, ~en_mask);
+ and_phy_reg(pi, val_addr, ~val_mask);
+ } else {
+
+ if ((core_mask == 0)
+ || (core_mask & (1 << core_num))) {
+ or_phy_reg(pi, en_addr, en_mask);
+
+ if (addr != 0xffff) {
+ mod_phy_reg(pi, val_addr,
+ val_mask,
+ (value <<
+ val_shift));
+ }
+ }
+ }
+ }
+ }
+}
+
+static void
+wlc_phy_rfctrl_override_nphy(phy_info_t *pi, u16 field, u16 value,
+ u8 core_mask, u8 off)
+{
+ u8 core_num;
+ u16 addr = 0, mask = 0, en_addr = 0, val_addr = 0, en_mask =
+ 0, val_mask = 0;
+ u8 shift = 0, val_shift = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
+
+ en_mask = field;
+ for (core_num = 0; core_num < 2; core_num++) {
+
+ switch (field) {
+ case (0x1 << 1):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x1 << 0);
+ val_shift = 0;
+ break;
+ case (0x1 << 2):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x1 << 1);
+ val_shift = 1;
+ break;
+ case (0x1 << 3):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x1 << 2);
+ val_shift = 2;
+ break;
+ case (0x1 << 4):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x1 << 4);
+ val_shift = 4;
+ break;
+ case (0x1 << 5):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x1 << 5);
+ val_shift = 5;
+ break;
+ case (0x1 << 6):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x1 << 6);
+ val_shift = 6;
+ break;
+ case (0x1 << 7):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x1 << 7);
+ val_shift = 7;
+ break;
+ case (0x1 << 8):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x7 << 8);
+ val_shift = 8;
+ break;
+ case (0x1 << 11):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7a : 0x7d;
+ val_mask = (0x7 << 13);
+ val_shift = 13;
+ break;
+
+ case (0x1 << 9):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0xf8 : 0xfa;
+ val_mask = (0x7 << 0);
+ val_shift = 0;
+ break;
+
+ case (0x1 << 10):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0xf8 : 0xfa;
+ val_mask = (0x7 << 4);
+ val_shift = 4;
+ break;
+
+ case (0x1 << 12):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7b : 0x7e;
+ val_mask = (0xffff << 0);
+ val_shift = 0;
+ break;
+ case (0x1 << 13):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0x7c : 0x7f;
+ val_mask = (0xffff << 0);
+ val_shift = 0;
+ break;
+ case (0x1 << 14):
+ en_addr = (core_num == 0) ? 0xe7 : 0xec;
+ val_addr = (core_num == 0) ? 0xf9 : 0xfb;
+ val_mask = (0x3 << 6);
+ val_shift = 6;
+ break;
+ case (0x1 << 0):
+ en_addr = (core_num == 0) ? 0xe5 : 0xe6;
+ val_addr = (core_num == 0) ? 0xf9 : 0xfb;
+ val_mask = (0x1 << 15);
+ val_shift = 15;
+ break;
+ default:
+ addr = 0xffff;
+ break;
+ }
+
+ if (off) {
+ and_phy_reg(pi, en_addr, ~en_mask);
+ and_phy_reg(pi, val_addr, ~val_mask);
+ } else {
+
+ if ((core_mask == 0)
+ || (core_mask & (1 << core_num))) {
+ or_phy_reg(pi, en_addr, en_mask);
+
+ if (addr != 0xffff) {
+ mod_phy_reg(pi, val_addr,
+ val_mask,
+ (value <<
+ val_shift));
+ }
+ }
+ }
+ }
+ } else {
+
+ if (off) {
+ and_phy_reg(pi, 0xec, ~field);
+ value = 0x0;
+ } else {
+ or_phy_reg(pi, 0xec, field);
+ }
+
+ for (core_num = 0; core_num < 2; core_num++) {
+
+ switch (field) {
+ case (0x1 << 1):
+ case (0x1 << 9):
+ case (0x1 << 12):
+ case (0x1 << 13):
+ case (0x1 << 14):
+ addr = 0x78;
+
+ core_mask = 0x1;
+ break;
+ case (0x1 << 2):
+ case (0x1 << 3):
+ case (0x1 << 4):
+ case (0x1 << 5):
+ case (0x1 << 6):
+ case (0x1 << 7):
+ case (0x1 << 8):
+ addr = (core_num == 0) ? 0x7a : 0x7d;
+ break;
+ case (0x1 << 10):
+ addr = (core_num == 0) ? 0x7b : 0x7e;
+ break;
+ case (0x1 << 11):
+ addr = (core_num == 0) ? 0x7c : 0x7f;
+ break;
+ default:
+ addr = 0xffff;
+ }
+
+ switch (field) {
+ case (0x1 << 1):
+ mask = (0x7 << 3);
+ shift = 3;
+ break;
+ case (0x1 << 9):
+ mask = (0x1 << 2);
+ shift = 2;
+ break;
+ case (0x1 << 12):
+ mask = (0x1 << 8);
+ shift = 8;
+ break;
+ case (0x1 << 13):
+ mask = (0x1 << 9);
+ shift = 9;
+ break;
+ case (0x1 << 14):
+ mask = (0xf << 12);
+ shift = 12;
+ break;
+ case (0x1 << 2):
+ mask = (0x1 << 0);
+ shift = 0;
+ break;
+ case (0x1 << 3):
+ mask = (0x1 << 1);
+ shift = 1;
+ break;
+ case (0x1 << 4):
+ mask = (0x1 << 2);
+ shift = 2;
+ break;
+ case (0x1 << 5):
+ mask = (0x3 << 4);
+ shift = 4;
+ break;
+ case (0x1 << 6):
+ mask = (0x3 << 6);
+ shift = 6;
+ break;
+ case (0x1 << 7):
+ mask = (0x1 << 8);
+ shift = 8;
+ break;
+ case (0x1 << 8):
+ mask = (0x1 << 9);
+ shift = 9;
+ break;
+ case (0x1 << 10):
+ mask = 0x1fff;
+ shift = 0x0;
+ break;
+ case (0x1 << 11):
+ mask = 0x1fff;
+ shift = 0x0;
+ break;
+ default:
+ mask = 0x0;
+ shift = 0x0;
+ break;
+ }
+
+ if ((addr != 0xffff) && (core_mask & (1 << core_num))) {
+ mod_phy_reg(pi, addr, mask, (value << shift));
+ }
+ }
+
+ or_phy_reg(pi, 0xec, (0x1 << 0));
+ or_phy_reg(pi, 0x78, (0x1 << 0));
+ udelay(1);
+ and_phy_reg(pi, 0xec, ~(0x1 << 0));
+ }
+}
+
+static void
+wlc_phy_rfctrl_override_1tomany_nphy(phy_info_t *pi, u16 cmd, u16 value,
+ u8 core_mask, u8 off)
+{
+ u16 rfmxgain = 0, lpfgain = 0;
+ u16 tgain = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ switch (cmd) {
+ case NPHY_REV7_RfctrlOverride_cmd_rxrf_pu:
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5),
+ value, core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), value,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), value,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ break;
+ case NPHY_REV7_RfctrlOverride_cmd_rx_pu:
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
+ value, core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), value,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), value,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), value,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ break;
+ case NPHY_REV7_RfctrlOverride_cmd_tx_pu:
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
+ value, core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), value,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), value,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), value,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 1,
+ core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ break;
+ case NPHY_REV7_RfctrlOverride_cmd_rxgain:
+ rfmxgain = value & 0x000ff;
+ lpfgain = value & 0x0ff00;
+ lpfgain = lpfgain >> 8;
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11),
+ rfmxgain, core_mask,
+ off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x3 << 13),
+ lpfgain, core_mask,
+ off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ break;
+ case NPHY_REV7_RfctrlOverride_cmd_txgain:
+ tgain = value & 0x7fff;
+ lpfgain = value & 0x8000;
+ lpfgain = lpfgain >> 14;
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
+ tgain, core_mask, off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 13),
+ lpfgain, core_mask,
+ off,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ break;
+ }
+ }
+}
+
+static void
+wlc_phy_scale_offset_rssi_nphy(phy_info_t *pi, u16 scale, s8 offset,
+ u8 coresel, u8 rail, u8 rssi_type)
+{
+ u16 valuetostuff;
+
+ offset = (offset > NPHY_RSSICAL_MAXREAD) ?
+ NPHY_RSSICAL_MAXREAD : offset;
+ offset = (offset < (-NPHY_RSSICAL_MAXREAD - 1)) ?
+ -NPHY_RSSICAL_MAXREAD - 1 : offset;
+
+ valuetostuff = ((scale & 0x3f) << 8) | (offset & 0x3f);
+
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_NB)) {
+ write_phy_reg(pi, 0x1a6, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_NB)) {
+ write_phy_reg(pi, 0x1ac, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_NB)) {
+ write_phy_reg(pi, 0x1b2, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_NB)) {
+ write_phy_reg(pi, 0x1b8, valuetostuff);
+ }
+
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W1)) {
+ write_phy_reg(pi, 0x1a4, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W1)) {
+ write_phy_reg(pi, 0x1aa, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W1)) {
+ write_phy_reg(pi, 0x1b0, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W1)) {
+ write_phy_reg(pi, 0x1b6, valuetostuff);
+ }
+
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W2)) {
+ write_phy_reg(pi, 0x1a5, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W2)) {
+ write_phy_reg(pi, 0x1ab, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W2)) {
+ write_phy_reg(pi, 0x1b1, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W2)) {
+ write_phy_reg(pi, 0x1b7, valuetostuff);
+ }
+
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_TBD)) {
+ write_phy_reg(pi, 0x1a7, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_TBD)) {
+ write_phy_reg(pi, 0x1ad, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_TBD)) {
+ write_phy_reg(pi, 0x1b3, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_TBD)) {
+ write_phy_reg(pi, 0x1b9, valuetostuff);
+ }
+
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_IQ)) {
+ write_phy_reg(pi, 0x1a8, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_IQ)) {
+ write_phy_reg(pi, 0x1ae, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_IQ)) {
+ write_phy_reg(pi, 0x1b4, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_IQ)) {
+ write_phy_reg(pi, 0x1ba, valuetostuff);
+ }
+
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rssi_type == NPHY_RSSI_SEL_TSSI_2G)) {
+ write_phy_reg(pi, 0x1a9, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rssi_type == NPHY_RSSI_SEL_TSSI_2G)) {
+ write_phy_reg(pi, 0x1b5, valuetostuff);
+ }
+
+ if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rssi_type == NPHY_RSSI_SEL_TSSI_5G)) {
+ write_phy_reg(pi, 0x1af, valuetostuff);
+ }
+ if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
+ (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
+ (rssi_type == NPHY_RSSI_SEL_TSSI_5G)) {
+ write_phy_reg(pi, 0x1bb, valuetostuff);
+ }
+}
+
+void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core_code, u8 rssi_type)
+{
+ u16 mask, val;
+ u16 afectrlovr_rssi_val, rfctrlcmd_rxen_val, rfctrlcmd_coresel_val,
+ startseq;
+ u16 rfctrlovr_rssi_val, rfctrlovr_rxen_val, rfctrlovr_coresel_val,
+ rfctrlovr_trigger_val;
+ u16 afectrlovr_rssi_mask, rfctrlcmd_mask, rfctrlovr_mask;
+ u16 rfctrlcmd_val, rfctrlovr_val;
+ u8 core;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (core_code == RADIO_MIMO_CORESEL_OFF) {
+ mod_phy_reg(pi, 0x8f, (0x1 << 9), 0);
+ mod_phy_reg(pi, 0xa5, (0x1 << 9), 0);
+
+ mod_phy_reg(pi, 0xa6, (0x3 << 8), 0);
+ mod_phy_reg(pi, 0xa7, (0x3 << 8), 0);
+
+ mod_phy_reg(pi, 0xe5, (0x1 << 5), 0);
+ mod_phy_reg(pi, 0xe6, (0x1 << 5), 0);
+
+ mask = (0x1 << 2) |
+ (0x1 << 3) | (0x1 << 4) | (0x1 << 5);
+ mod_phy_reg(pi, 0xf9, mask, 0);
+ mod_phy_reg(pi, 0xfb, mask, 0);
+
+ } else {
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ if (core_code == RADIO_MIMO_CORESEL_CORE1
+ && core == PHY_CORE_1)
+ continue;
+ else if (core_code == RADIO_MIMO_CORESEL_CORE2
+ && core == PHY_CORE_0)
+ continue;
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ?
+ 0x8f : 0xa5, (0x1 << 9), 1 << 9);
+
+ if (rssi_type == NPHY_RSSI_SEL_W1 ||
+ rssi_type == NPHY_RSSI_SEL_W2 ||
+ rssi_type == NPHY_RSSI_SEL_NB) {
+
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xa6 : 0xa7,
+ (0x3 << 8), 0);
+
+ mask = (0x1 << 2) |
+ (0x1 << 3) |
+ (0x1 << 4) | (0x1 << 5);
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xf9 : 0xfb,
+ mask, 0);
+
+ if (rssi_type == NPHY_RSSI_SEL_W1) {
+ if (CHSPEC_IS5G
+ (pi->radio_chanspec)) {
+ mask = (0x1 << 2);
+ val = 1 << 2;
+ } else {
+ mask = (0x1 << 3);
+ val = 1 << 3;
+ }
+ } else if (rssi_type ==
+ NPHY_RSSI_SEL_W2) {
+ mask = (0x1 << 4);
+ val = 1 << 4;
+ } else {
+ mask = (0x1 << 5);
+ val = 1 << 5;
+ }
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xf9 : 0xfb,
+ mask, val);
+
+ mask = (0x1 << 5);
+ val = 1 << 5;
+ mod_phy_reg(pi, (core == PHY_CORE_0) ?
+ 0xe5 : 0xe6, mask, val);
+ } else {
+ if (rssi_type == NPHY_RSSI_SEL_TBD) {
+
+ mask = (0x3 << 8);
+ val = 1 << 8;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xa6
+ : 0xa7, mask, val);
+ mask = (0x3 << 10);
+ val = 1 << 10;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xa6
+ : 0xa7, mask, val);
+ } else if (rssi_type ==
+ NPHY_RSSI_SEL_IQ) {
+
+ mask = (0x3 << 8);
+ val = 2 << 8;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xa6
+ : 0xa7, mask, val);
+ mask = (0x3 << 10);
+ val = 2 << 10;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xa6
+ : 0xa7, mask, val);
+ } else {
+
+ mask = (0x3 << 8);
+ val = 3 << 8;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xa6
+ : 0xa7, mask, val);
+ mask = (0x3 << 10);
+ val = 3 << 10;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xa6
+ : 0xa7, mask, val);
+
+ if (PHY_IPA(pi)) {
+ if (NREV_GE
+ (pi->pubpi.phy_rev,
+ 7)) {
+
+ write_radio_reg
+ (pi,
+ ((core ==
+ PHY_CORE_0)
+ ?
+ RADIO_2057_TX0_TX_SSI_MUX
+ :
+ RADIO_2057_TX1_TX_SSI_MUX),
+ (CHSPEC_IS5G
+ (pi->
+ radio_chanspec)
+ ? 0xc :
+ 0xe));
+ } else {
+ write_radio_reg
+ (pi,
+ RADIO_2056_TX_TX_SSI_MUX
+ |
+ ((core ==
+ PHY_CORE_0)
+ ?
+ RADIO_2056_TX0
+ :
+ RADIO_2056_TX1),
+ (CHSPEC_IS5G
+ (pi->
+ radio_chanspec)
+ ? 0xc :
+ 0xe));
+ }
+ } else {
+
+ if (NREV_GE
+ (pi->pubpi.phy_rev,
+ 7)) {
+ write_radio_reg
+ (pi,
+ ((core ==
+ PHY_CORE_0)
+ ?
+ RADIO_2057_TX0_TX_SSI_MUX
+ :
+ RADIO_2057_TX1_TX_SSI_MUX),
+ 0x11);
+
+ if (pi->pubpi.
+ radioid ==
+ BCM2057_ID)
+ write_radio_reg
+ (pi,
+ RADIO_2057_IQTEST_SEL_PU,
+ 0x1);
+
+ } else {
+ write_radio_reg
+ (pi,
+ RADIO_2056_TX_TX_SSI_MUX
+ |
+ ((core ==
+ PHY_CORE_0)
+ ?
+ RADIO_2056_TX0
+ :
+ RADIO_2056_TX1),
+ 0x11);
+ }
+ }
+
+ afectrlovr_rssi_val = 1 << 9;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x8f
+ : 0xa5, (0x1 << 9),
+ afectrlovr_rssi_val);
+ }
+ }
+ }
+ }
+ } else {
+
+ if ((rssi_type == NPHY_RSSI_SEL_W1) ||
+ (rssi_type == NPHY_RSSI_SEL_W2) ||
+ (rssi_type == NPHY_RSSI_SEL_NB)) {
+
+ val = 0x0;
+ } else if (rssi_type == NPHY_RSSI_SEL_TBD) {
+
+ val = 0x1;
+ } else if (rssi_type == NPHY_RSSI_SEL_IQ) {
+
+ val = 0x2;
+ } else {
+
+ val = 0x3;
+ }
+ mask = ((0x3 << 12) | (0x3 << 14));
+ val = (val << 12) | (val << 14);
+ mod_phy_reg(pi, 0xa6, mask, val);
+ mod_phy_reg(pi, 0xa7, mask, val);
+
+ if ((rssi_type == NPHY_RSSI_SEL_W1) ||
+ (rssi_type == NPHY_RSSI_SEL_W2) ||
+ (rssi_type == NPHY_RSSI_SEL_NB)) {
+ if (rssi_type == NPHY_RSSI_SEL_W1) {
+ val = 0x1;
+ }
+ if (rssi_type == NPHY_RSSI_SEL_W2) {
+ val = 0x2;
+ }
+ if (rssi_type == NPHY_RSSI_SEL_NB) {
+ val = 0x3;
+ }
+ mask = (0x3 << 4);
+ val = (val << 4);
+ mod_phy_reg(pi, 0x7a, mask, val);
+ mod_phy_reg(pi, 0x7d, mask, val);
+ }
+
+ if (core_code == RADIO_MIMO_CORESEL_OFF) {
+ afectrlovr_rssi_val = 0;
+ rfctrlcmd_rxen_val = 0;
+ rfctrlcmd_coresel_val = 0;
+ rfctrlovr_rssi_val = 0;
+ rfctrlovr_rxen_val = 0;
+ rfctrlovr_coresel_val = 0;
+ rfctrlovr_trigger_val = 0;
+ startseq = 0;
+ } else {
+ afectrlovr_rssi_val = 1;
+ rfctrlcmd_rxen_val = 1;
+ rfctrlcmd_coresel_val = core_code;
+ rfctrlovr_rssi_val = 1;
+ rfctrlovr_rxen_val = 1;
+ rfctrlovr_coresel_val = 1;
+ rfctrlovr_trigger_val = 1;
+ startseq = 1;
+ }
+
+ afectrlovr_rssi_mask = ((0x1 << 12) | (0x1 << 13));
+ afectrlovr_rssi_val = (afectrlovr_rssi_val <<
+ 12) | (afectrlovr_rssi_val << 13);
+ mod_phy_reg(pi, 0xa5, afectrlovr_rssi_mask,
+ afectrlovr_rssi_val);
+
+ if ((rssi_type == NPHY_RSSI_SEL_W1) ||
+ (rssi_type == NPHY_RSSI_SEL_W2) ||
+ (rssi_type == NPHY_RSSI_SEL_NB)) {
+ rfctrlcmd_mask = ((0x1 << 8) | (0x7 << 3));
+ rfctrlcmd_val = (rfctrlcmd_rxen_val << 8) |
+ (rfctrlcmd_coresel_val << 3);
+
+ rfctrlovr_mask = ((0x1 << 5) |
+ (0x1 << 12) |
+ (0x1 << 1) | (0x1 << 0));
+ rfctrlovr_val = (rfctrlovr_rssi_val <<
+ 5) |
+ (rfctrlovr_rxen_val << 12) |
+ (rfctrlovr_coresel_val << 1) |
+ (rfctrlovr_trigger_val << 0);
+
+ mod_phy_reg(pi, 0x78, rfctrlcmd_mask, rfctrlcmd_val);
+ mod_phy_reg(pi, 0xec, rfctrlovr_mask, rfctrlovr_val);
+
+ mod_phy_reg(pi, 0x78, (0x1 << 0), (startseq << 0));
+ udelay(20);
+
+ mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
+ }
+ }
+}
+
+int
+wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type, s32 *rssi_buf,
+ u8 nsamps)
+{
+ s16 rssi0, rssi1;
+ u16 afectrlCore1_save = 0;
+ u16 afectrlCore2_save = 0;
+ u16 afectrlOverride1_save = 0;
+ u16 afectrlOverride2_save = 0;
+ u16 rfctrlOverrideAux0_save = 0;
+ u16 rfctrlOverrideAux1_save = 0;
+ u16 rfctrlMiscReg1_save = 0;
+ u16 rfctrlMiscReg2_save = 0;
+ u16 rfctrlcmd_save = 0;
+ u16 rfctrloverride_save = 0;
+ u16 rfctrlrssiothers1_save = 0;
+ u16 rfctrlrssiothers2_save = 0;
+ s8 tmp_buf[4];
+ u8 ctr = 0, samp = 0;
+ s32 rssi_out_val;
+ u16 gpiosel_orig;
+
+ afectrlCore1_save = read_phy_reg(pi, 0xa6);
+ afectrlCore2_save = read_phy_reg(pi, 0xa7);
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ rfctrlMiscReg1_save = read_phy_reg(pi, 0xf9);
+ rfctrlMiscReg2_save = read_phy_reg(pi, 0xfb);
+ afectrlOverride1_save = read_phy_reg(pi, 0x8f);
+ afectrlOverride2_save = read_phy_reg(pi, 0xa5);
+ rfctrlOverrideAux0_save = read_phy_reg(pi, 0xe5);
+ rfctrlOverrideAux1_save = read_phy_reg(pi, 0xe6);
+ } else {
+ afectrlOverride1_save = read_phy_reg(pi, 0xa5);
+ rfctrlcmd_save = read_phy_reg(pi, 0x78);
+ rfctrloverride_save = read_phy_reg(pi, 0xec);
+ rfctrlrssiothers1_save = read_phy_reg(pi, 0x7a);
+ rfctrlrssiothers2_save = read_phy_reg(pi, 0x7d);
+ }
+
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_ALLRX, rssi_type);
+
+ gpiosel_orig = read_phy_reg(pi, 0xca);
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+ write_phy_reg(pi, 0xca, 5);
+ }
+
+ for (ctr = 0; ctr < 4; ctr++) {
+ rssi_buf[ctr] = 0;
+ }
+
+ for (samp = 0; samp < nsamps; samp++) {
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+ rssi0 = read_phy_reg(pi, 0x1c9);
+ rssi1 = read_phy_reg(pi, 0x1ca);
+ } else {
+ rssi0 = read_phy_reg(pi, 0x219);
+ rssi1 = read_phy_reg(pi, 0x21a);
+ }
+
+ ctr = 0;
+ tmp_buf[ctr++] = ((s8) ((rssi0 & 0x3f) << 2)) >> 2;
+ tmp_buf[ctr++] = ((s8) (((rssi0 >> 8) & 0x3f) << 2)) >> 2;
+ tmp_buf[ctr++] = ((s8) ((rssi1 & 0x3f) << 2)) >> 2;
+ tmp_buf[ctr++] = ((s8) (((rssi1 >> 8) & 0x3f) << 2)) >> 2;
+
+ for (ctr = 0; ctr < 4; ctr++) {
+ rssi_buf[ctr] += tmp_buf[ctr];
+ }
+
+ }
+
+ rssi_out_val = rssi_buf[3] & 0xff;
+ rssi_out_val |= (rssi_buf[2] & 0xff) << 8;
+ rssi_out_val |= (rssi_buf[1] & 0xff) << 16;
+ rssi_out_val |= (rssi_buf[0] & 0xff) << 24;
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+ write_phy_reg(pi, 0xca, gpiosel_orig);
+ }
+
+ write_phy_reg(pi, 0xa6, afectrlCore1_save);
+ write_phy_reg(pi, 0xa7, afectrlCore2_save);
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ write_phy_reg(pi, 0xf9, rfctrlMiscReg1_save);
+ write_phy_reg(pi, 0xfb, rfctrlMiscReg2_save);
+ write_phy_reg(pi, 0x8f, afectrlOverride1_save);
+ write_phy_reg(pi, 0xa5, afectrlOverride2_save);
+ write_phy_reg(pi, 0xe5, rfctrlOverrideAux0_save);
+ write_phy_reg(pi, 0xe6, rfctrlOverrideAux1_save);
+ } else {
+ write_phy_reg(pi, 0xa5, afectrlOverride1_save);
+ write_phy_reg(pi, 0x78, rfctrlcmd_save);
+ write_phy_reg(pi, 0xec, rfctrloverride_save);
+ write_phy_reg(pi, 0x7a, rfctrlrssiothers1_save);
+ write_phy_reg(pi, 0x7d, rfctrlrssiothers2_save);
+ }
+
+ return rssi_out_val;
+}
+
+s16 wlc_phy_tempsense_nphy(phy_info_t *pi)
+{
+ u16 core1_txrf_iqcal1_save, core1_txrf_iqcal2_save;
+ u16 core2_txrf_iqcal1_save, core2_txrf_iqcal2_save;
+ u16 pwrdet_rxtx_core1_save;
+ u16 pwrdet_rxtx_core2_save;
+ u16 afectrlCore1_save;
+ u16 afectrlCore2_save;
+ u16 afectrlOverride_save;
+ u16 afectrlOverride2_save;
+ u16 pd_pll_ts_save;
+ u16 gpioSel_save;
+ s32 radio_temp[4];
+ s32 radio_temp2[4];
+ u16 syn_tempprocsense_save;
+ s16 offset = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ u16 auxADC_Vmid, auxADC_Av, auxADC_Vmid_save, auxADC_Av_save;
+ u16 auxADC_rssi_ctrlL_save, auxADC_rssi_ctrlH_save;
+ u16 auxADC_rssi_ctrlL, auxADC_rssi_ctrlH;
+ s32 auxADC_Vl;
+ u16 RfctrlOverride5_save, RfctrlOverride6_save;
+ u16 RfctrlMiscReg5_save, RfctrlMiscReg6_save;
+ u16 RSSIMultCoef0QPowerDet_save;
+ u16 tempsense_Rcal;
+
+ syn_tempprocsense_save =
+ read_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG);
+
+ afectrlCore1_save = read_phy_reg(pi, 0xa6);
+ afectrlCore2_save = read_phy_reg(pi, 0xa7);
+ afectrlOverride_save = read_phy_reg(pi, 0x8f);
+ afectrlOverride2_save = read_phy_reg(pi, 0xa5);
+ RSSIMultCoef0QPowerDet_save = read_phy_reg(pi, 0x1ae);
+ RfctrlOverride5_save = read_phy_reg(pi, 0x346);
+ RfctrlOverride6_save = read_phy_reg(pi, 0x347);
+ RfctrlMiscReg5_save = read_phy_reg(pi, 0x344);
+ RfctrlMiscReg6_save = read_phy_reg(pi, 0x345);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
+ &auxADC_Vmid_save);
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
+ &auxADC_Av_save);
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
+ &auxADC_rssi_ctrlL_save);
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
+ &auxADC_rssi_ctrlH_save);
+
+ write_phy_reg(pi, 0x1ae, 0x0);
+
+ auxADC_rssi_ctrlL = 0x0;
+ auxADC_rssi_ctrlH = 0x20;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
+ &auxADC_rssi_ctrlL);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
+ &auxADC_rssi_ctrlH);
+
+ tempsense_Rcal = syn_tempprocsense_save & 0x1c;
+
+ write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
+ tempsense_Rcal | 0x01);
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1),
+ 1, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ mod_phy_reg(pi, 0xa6, (0x1 << 7), 0);
+ mod_phy_reg(pi, 0xa7, (0x1 << 7), 0);
+ mod_phy_reg(pi, 0x8f, (0x1 << 7), (0x1 << 7));
+ mod_phy_reg(pi, 0xa5, (0x1 << 7), (0x1 << 7));
+
+ mod_phy_reg(pi, 0xa6, (0x1 << 2), (0x1 << 2));
+ mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
+ mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
+ mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
+ udelay(5);
+ mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
+ mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
+ mod_phy_reg(pi, 0xa6, (0x1 << 3), 0);
+ mod_phy_reg(pi, 0xa7, (0x1 << 3), 0);
+ mod_phy_reg(pi, 0x8f, (0x1 << 3), (0x1 << 3));
+ mod_phy_reg(pi, 0xa5, (0x1 << 3), (0x1 << 3));
+ mod_phy_reg(pi, 0xa6, (0x1 << 6), 0);
+ mod_phy_reg(pi, 0xa7, (0x1 << 6), 0);
+ mod_phy_reg(pi, 0x8f, (0x1 << 6), (0x1 << 6));
+ mod_phy_reg(pi, 0xa5, (0x1 << 6), (0x1 << 6));
+
+ auxADC_Vmid = 0xA3;
+ auxADC_Av = 0x0;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
+ &auxADC_Vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
+ &auxADC_Av);
+
+ udelay(3);
+
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
+ write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
+ tempsense_Rcal | 0x03);
+
+ udelay(5);
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
+
+ auxADC_Av = 0x7;
+ if (radio_temp[1] + radio_temp2[1] < -30) {
+ auxADC_Vmid = 0x45;
+ auxADC_Vl = 263;
+ } else if (radio_temp[1] + radio_temp2[1] < -9) {
+ auxADC_Vmid = 0x200;
+ auxADC_Vl = 467;
+ } else if (radio_temp[1] + radio_temp2[1] < 11) {
+ auxADC_Vmid = 0x266;
+ auxADC_Vl = 634;
+ } else {
+ auxADC_Vmid = 0x2D5;
+ auxADC_Vl = 816;
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
+ &auxADC_Vmid);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
+ &auxADC_Av);
+
+ udelay(3);
+
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
+ write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
+ tempsense_Rcal | 0x01);
+
+ udelay(5);
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
+
+ write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
+ syn_tempprocsense_save);
+
+ write_phy_reg(pi, 0xa6, afectrlCore1_save);
+ write_phy_reg(pi, 0xa7, afectrlCore2_save);
+ write_phy_reg(pi, 0x8f, afectrlOverride_save);
+ write_phy_reg(pi, 0xa5, afectrlOverride2_save);
+ write_phy_reg(pi, 0x1ae, RSSIMultCoef0QPowerDet_save);
+ write_phy_reg(pi, 0x346, RfctrlOverride5_save);
+ write_phy_reg(pi, 0x347, RfctrlOverride6_save);
+ write_phy_reg(pi, 0x344, RfctrlMiscReg5_save);
+ write_phy_reg(pi, 0x345, RfctrlMiscReg5_save);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
+ &auxADC_Vmid_save);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
+ &auxADC_Av_save);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
+ &auxADC_rssi_ctrlL_save);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
+ &auxADC_rssi_ctrlH_save);
+
+ if (pi->sh->chip == BCM5357_CHIP_ID) {
+ radio_temp[0] = (193 * (radio_temp[1] + radio_temp2[1])
+ + 88 * (auxADC_Vl) - 27111 +
+ 128) / 256;
+ } else if (pi->sh->chip == BCM43236_CHIP_ID) {
+ radio_temp[0] = (198 * (radio_temp[1] + radio_temp2[1])
+ + 91 * (auxADC_Vl) - 27243 +
+ 128) / 256;
+ } else {
+ radio_temp[0] = (179 * (radio_temp[1] + radio_temp2[1])
+ + 82 * (auxADC_Vl) - 28861 +
+ 128) / 256;
+ }
+
+ offset = (s16) pi->phy_tempsense_offset;
+
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ syn_tempprocsense_save =
+ read_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE);
+
+ afectrlCore1_save = read_phy_reg(pi, 0xa6);
+ afectrlCore2_save = read_phy_reg(pi, 0xa7);
+ afectrlOverride_save = read_phy_reg(pi, 0x8f);
+ afectrlOverride2_save = read_phy_reg(pi, 0xa5);
+ gpioSel_save = read_phy_reg(pi, 0xca);
+
+ write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x01);
+
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ } else {
+ write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x05);
+ }
+
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG, 0x01);
+ } else {
+ write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x01);
+ }
+
+ radio_temp[0] =
+ (126 * (radio_temp[1] + radio_temp2[1]) + 3987) / 64;
+
+ write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE,
+ syn_tempprocsense_save);
+
+ write_phy_reg(pi, 0xca, gpioSel_save);
+ write_phy_reg(pi, 0xa6, afectrlCore1_save);
+ write_phy_reg(pi, 0xa7, afectrlCore2_save);
+ write_phy_reg(pi, 0x8f, afectrlOverride_save);
+ write_phy_reg(pi, 0xa5, afectrlOverride2_save);
+
+ offset = (s16) pi->phy_tempsense_offset;
+ } else {
+
+ pwrdet_rxtx_core1_save =
+ read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
+ pwrdet_rxtx_core2_save =
+ read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
+ core1_txrf_iqcal1_save =
+ read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
+ core1_txrf_iqcal2_save =
+ read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
+ core2_txrf_iqcal1_save =
+ read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
+ core2_txrf_iqcal2_save =
+ read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
+ pd_pll_ts_save = read_radio_reg(pi, RADIO_2055_PD_PLL_TS);
+
+ afectrlCore1_save = read_phy_reg(pi, 0xa6);
+ afectrlCore2_save = read_phy_reg(pi, 0xa7);
+ afectrlOverride_save = read_phy_reg(pi, 0xa5);
+ gpioSel_save = read_phy_reg(pi, 0xca);
+
+ write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1, 0x01);
+ write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1, 0x01);
+ write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2, 0x08);
+ write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2, 0x08);
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x04);
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x04);
+ write_radio_reg(pi, RADIO_2055_PD_PLL_TS, 0x00);
+
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
+ xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
+
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
+ xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
+
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
+ xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
+
+ radio_temp[0] = (radio_temp[0] + radio_temp2[0]);
+ radio_temp[1] = (radio_temp[1] + radio_temp2[1]);
+ radio_temp[2] = (radio_temp[2] + radio_temp2[2]);
+ radio_temp[3] = (radio_temp[3] + radio_temp2[3]);
+
+ radio_temp[0] =
+ (radio_temp[0] + radio_temp[1] + radio_temp[2] +
+ radio_temp[3]);
+
+ radio_temp[0] =
+ (radio_temp[0] + (8 * 32)) * (950 - 350) / 63 + (350 * 8);
+
+ radio_temp[0] = (radio_temp[0] - (8 * 420)) / 38;
+
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1,
+ pwrdet_rxtx_core1_save);
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2,
+ pwrdet_rxtx_core2_save);
+ write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1,
+ core1_txrf_iqcal1_save);
+ write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1,
+ core2_txrf_iqcal1_save);
+ write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2,
+ core1_txrf_iqcal2_save);
+ write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2,
+ core2_txrf_iqcal2_save);
+ write_radio_reg(pi, RADIO_2055_PD_PLL_TS, pd_pll_ts_save);
+
+ write_phy_reg(pi, 0xca, gpioSel_save);
+ write_phy_reg(pi, 0xa6, afectrlCore1_save);
+ write_phy_reg(pi, 0xa7, afectrlCore2_save);
+ write_phy_reg(pi, 0xa5, afectrlOverride_save);
+ }
+
+ return (s16) radio_temp[0] + offset;
+}
+
+static void
+wlc_phy_set_rssi_2055_vcm(phy_info_t *pi, u8 rssi_type, u8 *vcm_buf)
+{
+ u8 core;
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ if (rssi_type == NPHY_RSSI_SEL_NB) {
+ if (core == PHY_CORE_0) {
+ mod_radio_reg(pi,
+ RADIO_2055_CORE1_B0_NBRSSI_VCM,
+ RADIO_2055_NBRSSI_VCM_I_MASK,
+ vcm_buf[2 *
+ core] <<
+ RADIO_2055_NBRSSI_VCM_I_SHIFT);
+ mod_radio_reg(pi,
+ RADIO_2055_CORE1_RXBB_RSSI_CTRL5,
+ RADIO_2055_NBRSSI_VCM_Q_MASK,
+ vcm_buf[2 * core +
+ 1] <<
+ RADIO_2055_NBRSSI_VCM_Q_SHIFT);
+ } else {
+ mod_radio_reg(pi,
+ RADIO_2055_CORE2_B0_NBRSSI_VCM,
+ RADIO_2055_NBRSSI_VCM_I_MASK,
+ vcm_buf[2 *
+ core] <<
+ RADIO_2055_NBRSSI_VCM_I_SHIFT);
+ mod_radio_reg(pi,
+ RADIO_2055_CORE2_RXBB_RSSI_CTRL5,
+ RADIO_2055_NBRSSI_VCM_Q_MASK,
+ vcm_buf[2 * core +
+ 1] <<
+ RADIO_2055_NBRSSI_VCM_Q_SHIFT);
+ }
+ } else {
+
+ if (core == PHY_CORE_0) {
+ mod_radio_reg(pi,
+ RADIO_2055_CORE1_RXBB_RSSI_CTRL5,
+ RADIO_2055_WBRSSI_VCM_IQ_MASK,
+ vcm_buf[2 *
+ core] <<
+ RADIO_2055_WBRSSI_VCM_IQ_SHIFT);
+ } else {
+ mod_radio_reg(pi,
+ RADIO_2055_CORE2_RXBB_RSSI_CTRL5,
+ RADIO_2055_WBRSSI_VCM_IQ_MASK,
+ vcm_buf[2 *
+ core] <<
+ RADIO_2055_WBRSSI_VCM_IQ_SHIFT);
+ }
+ }
+ }
+}
+
+void wlc_phy_rssi_cal_nphy(phy_info_t *pi)
+{
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ wlc_phy_rssi_cal_nphy_rev3(pi);
+ } else {
+ wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_NB);
+ wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_W1);
+ wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_W2);
+ }
+}
+
+static void wlc_phy_rssi_cal_nphy_rev2(phy_info_t *pi, u8 rssi_type)
+{
+ s32 target_code;
+ u16 classif_state;
+ u16 clip_state[2];
+ u16 rssi_ctrl_state[2], pd_state[2];
+ u16 rfctrlintc_state[2], rfpdcorerxtx_state[2];
+ u16 rfctrlintc_override_val;
+ u16 clip_off[] = { 0xffff, 0xffff };
+ u16 rf_pd_val, pd_mask, rssi_ctrl_mask;
+ u8 vcm, min_vcm, vcm_tmp[4];
+ u8 vcm_final[4] = { 0, 0, 0, 0 };
+ u8 result_idx, ctr;
+ s32 poll_results[4][4] = {
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0}
+ };
+ s32 poll_miniq[4][2] = {
+ {0, 0},
+ {0, 0},
+ {0, 0},
+ {0, 0}
+ };
+ s32 min_d, curr_d;
+ s32 fine_digital_offset[4];
+ s32 poll_results_min[4] = { 0, 0, 0, 0 };
+ s32 min_poll;
+
+ switch (rssi_type) {
+ case NPHY_RSSI_SEL_NB:
+ target_code = NPHY_RSSICAL_NB_TARGET;
+ break;
+ case NPHY_RSSI_SEL_W1:
+ target_code = NPHY_RSSICAL_W1_TARGET;
+ break;
+ case NPHY_RSSI_SEL_W2:
+ target_code = NPHY_RSSICAL_W2_TARGET;
+ break;
+ default:
+ return;
+ break;
+ }
+
+ classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
+ wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
+ wlc_phy_clip_det_nphy(pi, 0, clip_state);
+ wlc_phy_clip_det_nphy(pi, 1, clip_off);
+
+ rf_pd_val = (rssi_type == NPHY_RSSI_SEL_NB) ? 0x6 : 0x4;
+ rfctrlintc_override_val =
+ CHSPEC_IS5G(pi->radio_chanspec) ? 0x140 : 0x110;
+
+ rfctrlintc_state[0] = read_phy_reg(pi, 0x91);
+ rfpdcorerxtx_state[0] = read_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX);
+ write_phy_reg(pi, 0x91, rfctrlintc_override_val);
+ write_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX, rf_pd_val);
+
+ rfctrlintc_state[1] = read_phy_reg(pi, 0x92);
+ rfpdcorerxtx_state[1] = read_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX);
+ write_phy_reg(pi, 0x92, rfctrlintc_override_val);
+ write_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX, rf_pd_val);
+
+ pd_mask = RADIO_2055_NBRSSI_PD | RADIO_2055_WBRSSI_G1_PD |
+ RADIO_2055_WBRSSI_G2_PD;
+ pd_state[0] =
+ read_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC) & pd_mask;
+ pd_state[1] =
+ read_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC) & pd_mask;
+ mod_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC, pd_mask, 0);
+ mod_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC, pd_mask, 0);
+ rssi_ctrl_mask = RADIO_2055_NBRSSI_SEL | RADIO_2055_WBRSSI_G1_SEL |
+ RADIO_2055_WBRSSI_G2_SEL;
+ rssi_ctrl_state[0] =
+ read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE1) & rssi_ctrl_mask;
+ rssi_ctrl_state[1] =
+ read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE2) & rssi_ctrl_mask;
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_ALLRX, rssi_type);
+
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0, RADIO_MIMO_CORESEL_ALLRX,
+ NPHY_RAIL_I, rssi_type);
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0, RADIO_MIMO_CORESEL_ALLRX,
+ NPHY_RAIL_Q, rssi_type);
+
+ for (vcm = 0; vcm < 4; vcm++) {
+
+ vcm_tmp[0] = vcm_tmp[1] = vcm_tmp[2] = vcm_tmp[3] = vcm;
+ if (rssi_type != NPHY_RSSI_SEL_W2) {
+ wlc_phy_set_rssi_2055_vcm(pi, rssi_type, vcm_tmp);
+ }
+
+ wlc_phy_poll_rssi_nphy(pi, rssi_type, &poll_results[vcm][0],
+ NPHY_RSSICAL_NPOLL);
+
+ if ((rssi_type == NPHY_RSSI_SEL_W1)
+ || (rssi_type == NPHY_RSSI_SEL_W2)) {
+ for (ctr = 0; ctr < 2; ctr++) {
+ poll_miniq[vcm][ctr] =
+ min(poll_results[vcm][ctr * 2 + 0],
+ poll_results[vcm][ctr * 2 + 1]);
+ }
+ }
+ }
+
+ for (result_idx = 0; result_idx < 4; result_idx++) {
+ min_d = NPHY_RSSICAL_MAXD;
+ min_vcm = 0;
+ min_poll = NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL + 1;
+ for (vcm = 0; vcm < 4; vcm++) {
+ curr_d = ABS(((rssi_type == NPHY_RSSI_SEL_NB) ?
+ poll_results[vcm][result_idx] :
+ poll_miniq[vcm][result_idx / 2]) -
+ (target_code * NPHY_RSSICAL_NPOLL));
+ if (curr_d < min_d) {
+ min_d = curr_d;
+ min_vcm = vcm;
+ }
+ if (poll_results[vcm][result_idx] < min_poll) {
+ min_poll = poll_results[vcm][result_idx];
+ }
+ }
+ vcm_final[result_idx] = min_vcm;
+ poll_results_min[result_idx] = min_poll;
+ }
+
+ if (rssi_type != NPHY_RSSI_SEL_W2) {
+ wlc_phy_set_rssi_2055_vcm(pi, rssi_type, vcm_final);
+ }
+
+ for (result_idx = 0; result_idx < 4; result_idx++) {
+ fine_digital_offset[result_idx] =
+ (target_code * NPHY_RSSICAL_NPOLL) -
+ poll_results[vcm_final[result_idx]][result_idx];
+ if (fine_digital_offset[result_idx] < 0) {
+ fine_digital_offset[result_idx] =
+ ABS(fine_digital_offset[result_idx]);
+ fine_digital_offset[result_idx] +=
+ (NPHY_RSSICAL_NPOLL / 2);
+ fine_digital_offset[result_idx] /= NPHY_RSSICAL_NPOLL;
+ fine_digital_offset[result_idx] =
+ -fine_digital_offset[result_idx];
+ } else {
+ fine_digital_offset[result_idx] +=
+ (NPHY_RSSICAL_NPOLL / 2);
+ fine_digital_offset[result_idx] /= NPHY_RSSICAL_NPOLL;
+ }
+
+ if (poll_results_min[result_idx] ==
+ NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL) {
+ fine_digital_offset[result_idx] =
+ (target_code - NPHY_RSSICAL_MAXREAD - 1);
+ }
+
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0,
+ (s8)
+ fine_digital_offset[result_idx],
+ (result_idx / 2 ==
+ 0) ? RADIO_MIMO_CORESEL_CORE1 :
+ RADIO_MIMO_CORESEL_CORE2,
+ (result_idx % 2 ==
+ 0) ? NPHY_RAIL_I : NPHY_RAIL_Q,
+ rssi_type);
+ }
+
+ mod_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC, pd_mask, pd_state[0]);
+ mod_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC, pd_mask, pd_state[1]);
+ if (rssi_ctrl_state[0] == RADIO_2055_NBRSSI_SEL) {
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
+ NPHY_RSSI_SEL_NB);
+ } else if (rssi_ctrl_state[0] == RADIO_2055_WBRSSI_G1_SEL) {
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
+ NPHY_RSSI_SEL_W1);
+ } else if (rssi_ctrl_state[0] == RADIO_2055_WBRSSI_G2_SEL) {
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
+ NPHY_RSSI_SEL_W2);
+ } else {
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
+ NPHY_RSSI_SEL_W2);
+ }
+ if (rssi_ctrl_state[1] == RADIO_2055_NBRSSI_SEL) {
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
+ NPHY_RSSI_SEL_NB);
+ } else if (rssi_ctrl_state[1] == RADIO_2055_WBRSSI_G1_SEL) {
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
+ NPHY_RSSI_SEL_W1);
+ } else if (rssi_ctrl_state[1] == RADIO_2055_WBRSSI_G2_SEL) {
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
+ NPHY_RSSI_SEL_W2);
+ } else {
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
+ NPHY_RSSI_SEL_W2);
+ }
+
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_OFF, rssi_type);
+
+ write_phy_reg(pi, 0x91, rfctrlintc_state[0]);
+ write_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX, rfpdcorerxtx_state[0]);
+ write_phy_reg(pi, 0x92, rfctrlintc_state[1]);
+ write_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX, rfpdcorerxtx_state[1]);
+
+ wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
+ wlc_phy_clip_det_nphy(pi, 1, clip_state);
+
+ wlc_phy_resetcca_nphy(pi);
+}
+
+int
+wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh)
+{
+ d11rxhdr_t *rxh = &wlc_rxh->rxhdr;
+ s16 rxpwr, rxpwr0, rxpwr1;
+ s16 phyRx0_l, phyRx2_l;
+
+ rxpwr = 0;
+ rxpwr0 = le16_to_cpu(rxh->PhyRxStatus_1) & PRXS1_nphy_PWR0_MASK;
+ rxpwr1 = (le16_to_cpu(rxh->PhyRxStatus_1) & PRXS1_nphy_PWR1_MASK) >> 8;
+
+ if (rxpwr0 > 127)
+ rxpwr0 -= 256;
+ if (rxpwr1 > 127)
+ rxpwr1 -= 256;
+
+ phyRx0_l = le16_to_cpu(rxh->PhyRxStatus_0) & 0x00ff;
+ phyRx2_l = le16_to_cpu(rxh->PhyRxStatus_2) & 0x00ff;
+ if (phyRx2_l > 127)
+ phyRx2_l -= 256;
+
+ if (((rxpwr0 == 16) || (rxpwr0 == 32))) {
+ rxpwr0 = rxpwr1;
+ rxpwr1 = phyRx2_l;
+ }
+
+ wlc_rxh->rxpwr[0] = (s8) rxpwr0;
+ wlc_rxh->rxpwr[1] = (s8) rxpwr1;
+ wlc_rxh->do_rssi_ma = 0;
+
+ if (pi->sh->rssi_mode == RSSI_ANT_MERGE_MAX)
+ rxpwr = (rxpwr0 > rxpwr1) ? rxpwr0 : rxpwr1;
+ else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_MIN)
+ rxpwr = (rxpwr0 < rxpwr1) ? rxpwr0 : rxpwr1;
+ else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_AVG)
+ rxpwr = (rxpwr0 + rxpwr1) >> 1;
+
+ return rxpwr;
+}
+
+static void
+wlc_phy_rfctrlintc_override_nphy(phy_info_t *pi, u8 field, u16 value,
+ u8 core_code)
+{
+ u16 mask;
+ u16 val;
+ u8 core;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ if (core_code == RADIO_MIMO_CORESEL_CORE1
+ && core == PHY_CORE_1)
+ continue;
+ else if (core_code == RADIO_MIMO_CORESEL_CORE2
+ && core == PHY_CORE_0)
+ continue;
+
+ if (NREV_LT(pi->pubpi.phy_rev, 7)) {
+
+ mask = (0x1 << 10);
+ val = 1 << 10;
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x91 :
+ 0x92, mask, val);
+ }
+
+ if (field == NPHY_RfctrlIntc_override_OFF) {
+
+ write_phy_reg(pi, (core == PHY_CORE_0) ? 0x91 :
+ 0x92, 0);
+
+ wlc_phy_force_rfseq_nphy(pi,
+ NPHY_RFSEQ_RESET2RX);
+ } else if (field == NPHY_RfctrlIntc_override_TRSW) {
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ mask = (0x1 << 6) | (0x1 << 7);
+
+ val = value << 6;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ mask, val);
+
+ or_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ (0x1 << 10));
+
+ and_phy_reg(pi, 0x2ff, (u16)
+ ~(0x3 << 14));
+ or_phy_reg(pi, 0x2ff, (0x1 << 13));
+ or_phy_reg(pi, 0x2ff, (0x1 << 0));
+ } else {
+
+ mask = (0x1 << 6) |
+ (0x1 << 7) |
+ (0x1 << 8) | (0x1 << 9);
+ val = value << 6;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ mask, val);
+
+ mask = (0x1 << 0);
+ val = 1 << 0;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xe7 : 0xec,
+ mask, val);
+
+ mask = (core == PHY_CORE_0) ? (0x1 << 0)
+ : (0x1 << 1);
+ val = 1 << ((core == PHY_CORE_0) ?
+ 0 : 1);
+ mod_phy_reg(pi, 0x78, mask, val);
+
+ SPINWAIT(((read_phy_reg(pi, 0x78) & val)
+ != 0), 10000);
+ if (WARN(read_phy_reg(pi, 0x78) & val,
+ "HW error: override failed"))
+ return;
+
+ mask = (0x1 << 0);
+ val = 0 << 0;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xe7 : 0xec,
+ mask, val);
+ }
+ } else if (field == NPHY_RfctrlIntc_override_PA) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ mask = (0x1 << 4) | (0x1 << 5);
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ val = value << 5;
+ } else {
+ val = value << 4;
+ }
+
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ mask, val);
+
+ or_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ (0x1 << 12));
+ } else {
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ mask = (0x1 << 5);
+ val = value << 5;
+ } else {
+ mask = (0x1 << 4);
+ val = value << 4;
+ }
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ mask, val);
+ }
+ } else if (field == NPHY_RfctrlIntc_override_EXT_LNA_PU) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+
+ mask = (0x1 << 0);
+ val = value << 0;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91
+ : 0x92, mask, val);
+
+ mask = (0x1 << 2);
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91
+ : 0x92, mask, 0);
+ } else {
+
+ mask = (0x1 << 2);
+ val = value << 2;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91
+ : 0x92, mask, val);
+
+ mask = (0x1 << 0);
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91
+ : 0x92, mask, 0);
+ }
+
+ mask = (0x1 << 11);
+ val = 1 << 11;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ mask, val);
+ } else {
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ mask = (0x1 << 0);
+ val = value << 0;
+ } else {
+ mask = (0x1 << 2);
+ val = value << 2;
+ }
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ mask, val);
+ }
+ } else if (field ==
+ NPHY_RfctrlIntc_override_EXT_LNA_GAIN) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+
+ mask = (0x1 << 1);
+ val = value << 1;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91
+ : 0x92, mask, val);
+
+ mask = (0x1 << 3);
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91
+ : 0x92, mask, 0);
+ } else {
+
+ mask = (0x1 << 3);
+ val = value << 3;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91
+ : 0x92, mask, val);
+
+ mask = (0x1 << 1);
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91
+ : 0x92, mask, 0);
+ }
+
+ mask = (0x1 << 11);
+ val = 1 << 11;
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ mask, val);
+ } else {
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ mask = (0x1 << 1);
+ val = value << 1;
+ } else {
+ mask = (0x1 << 3);
+ val = value << 3;
+ }
+ mod_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0x91 : 0x92,
+ mask, val);
+ }
+ }
+ }
+ } else {
+ return;
+ }
+}
+
+static void wlc_phy_rssi_cal_nphy_rev3(phy_info_t *pi)
+{
+ u16 classif_state;
+ u16 clip_state[2];
+ u16 clip_off[] = { 0xffff, 0xffff };
+ s32 target_code;
+ u8 vcm, min_vcm;
+ u8 vcm_final = 0;
+ u8 result_idx;
+ s32 poll_results[8][4] = {
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0}
+ };
+ s32 poll_result_core[4] = { 0, 0, 0, 0 };
+ s32 min_d = NPHY_RSSICAL_MAXD, curr_d;
+ s32 fine_digital_offset[4];
+ s32 poll_results_min[4] = { 0, 0, 0, 0 };
+ s32 min_poll;
+ u8 vcm_level_max;
+ u8 core;
+ u8 wb_cnt;
+ u8 rssi_type;
+ u16 NPHY_Rfctrlintc1_save, NPHY_Rfctrlintc2_save;
+ u16 NPHY_AfectrlOverride1_save, NPHY_AfectrlOverride2_save;
+ u16 NPHY_AfectrlCore1_save, NPHY_AfectrlCore2_save;
+ u16 NPHY_RfctrlOverride0_save, NPHY_RfctrlOverride1_save;
+ u16 NPHY_RfctrlOverrideAux0_save, NPHY_RfctrlOverrideAux1_save;
+ u16 NPHY_RfctrlCmd_save;
+ u16 NPHY_RfctrlMiscReg1_save, NPHY_RfctrlMiscReg2_save;
+ u16 NPHY_RfctrlRSSIOTHERS1_save, NPHY_RfctrlRSSIOTHERS2_save;
+ u8 rxcore_state;
+ u16 NPHY_REV7_RfctrlOverride3_save, NPHY_REV7_RfctrlOverride4_save;
+ u16 NPHY_REV7_RfctrlOverride5_save, NPHY_REV7_RfctrlOverride6_save;
+ u16 NPHY_REV7_RfctrlMiscReg3_save, NPHY_REV7_RfctrlMiscReg4_save;
+ u16 NPHY_REV7_RfctrlMiscReg5_save, NPHY_REV7_RfctrlMiscReg6_save;
+
+ NPHY_REV7_RfctrlOverride3_save = NPHY_REV7_RfctrlOverride4_save =
+ NPHY_REV7_RfctrlOverride5_save = NPHY_REV7_RfctrlOverride6_save =
+ NPHY_REV7_RfctrlMiscReg3_save = NPHY_REV7_RfctrlMiscReg4_save =
+ NPHY_REV7_RfctrlMiscReg5_save = NPHY_REV7_RfctrlMiscReg6_save = 0;
+
+ classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
+ wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
+ wlc_phy_clip_det_nphy(pi, 0, clip_state);
+ wlc_phy_clip_det_nphy(pi, 1, clip_off);
+
+ NPHY_Rfctrlintc1_save = read_phy_reg(pi, 0x91);
+ NPHY_Rfctrlintc2_save = read_phy_reg(pi, 0x92);
+ NPHY_AfectrlOverride1_save = read_phy_reg(pi, 0x8f);
+ NPHY_AfectrlOverride2_save = read_phy_reg(pi, 0xa5);
+ NPHY_AfectrlCore1_save = read_phy_reg(pi, 0xa6);
+ NPHY_AfectrlCore2_save = read_phy_reg(pi, 0xa7);
+ NPHY_RfctrlOverride0_save = read_phy_reg(pi, 0xe7);
+ NPHY_RfctrlOverride1_save = read_phy_reg(pi, 0xec);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ NPHY_REV7_RfctrlOverride3_save = read_phy_reg(pi, 0x342);
+ NPHY_REV7_RfctrlOverride4_save = read_phy_reg(pi, 0x343);
+ NPHY_REV7_RfctrlOverride5_save = read_phy_reg(pi, 0x346);
+ NPHY_REV7_RfctrlOverride6_save = read_phy_reg(pi, 0x347);
+ }
+ NPHY_RfctrlOverrideAux0_save = read_phy_reg(pi, 0xe5);
+ NPHY_RfctrlOverrideAux1_save = read_phy_reg(pi, 0xe6);
+ NPHY_RfctrlCmd_save = read_phy_reg(pi, 0x78);
+ NPHY_RfctrlMiscReg1_save = read_phy_reg(pi, 0xf9);
+ NPHY_RfctrlMiscReg2_save = read_phy_reg(pi, 0xfb);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ NPHY_REV7_RfctrlMiscReg3_save = read_phy_reg(pi, 0x340);
+ NPHY_REV7_RfctrlMiscReg4_save = read_phy_reg(pi, 0x341);
+ NPHY_REV7_RfctrlMiscReg5_save = read_phy_reg(pi, 0x344);
+ NPHY_REV7_RfctrlMiscReg6_save = read_phy_reg(pi, 0x345);
+ }
+ NPHY_RfctrlRSSIOTHERS1_save = read_phy_reg(pi, 0x7a);
+ NPHY_RfctrlRSSIOTHERS2_save = read_phy_reg(pi, 0x7d);
+
+ wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_OFF, 0,
+ RADIO_MIMO_CORESEL_ALLRXTX);
+ wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_TRSW, 1,
+ RADIO_MIMO_CORESEL_ALLRXTX);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_rxrf_pu,
+ 0, 0, 0);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0, 0);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_rx_pu,
+ 1, 0, 0);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 1, 0, 0);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
+ 1, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 6), 1, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 7), 1, 0, 0);
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 6), 1, 0, 0);
+ }
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5),
+ 0, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 1, 0,
+ 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 5), 0, 0, 0);
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 4), 1, 0, 0);
+ }
+
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4),
+ 0, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 1, 0,
+ 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 4), 0, 0, 0);
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 5), 1, 0, 0);
+ }
+ }
+
+ rxcore_state = wlc_phy_rxcore_getstate_nphy((wlc_phy_t *) pi);
+
+ vcm_level_max = 8;
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+
+ if ((rxcore_state & (1 << core)) == 0)
+ continue;
+
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
+ core ==
+ PHY_CORE_0 ?
+ RADIO_MIMO_CORESEL_CORE1 :
+ RADIO_MIMO_CORESEL_CORE2,
+ NPHY_RAIL_I, NPHY_RSSI_SEL_NB);
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
+ core ==
+ PHY_CORE_0 ?
+ RADIO_MIMO_CORESEL_CORE1 :
+ RADIO_MIMO_CORESEL_CORE2,
+ NPHY_RAIL_Q, NPHY_RSSI_SEL_NB);
+
+ for (vcm = 0; vcm < vcm_level_max; vcm++) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ mod_radio_reg(pi, (core == PHY_CORE_0) ?
+ RADIO_2057_NB_MASTER_CORE0 :
+ RADIO_2057_NB_MASTER_CORE1,
+ RADIO_2057_VCM_MASK, vcm);
+ } else {
+
+ mod_radio_reg(pi, RADIO_2056_RX_RSSI_MISC |
+ ((core ==
+ PHY_CORE_0) ? RADIO_2056_RX0 :
+ RADIO_2056_RX1),
+ RADIO_2056_VCM_MASK,
+ vcm << RADIO_2056_RSSI_VCM_SHIFT);
+ }
+
+ wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_NB,
+ &poll_results[vcm][0],
+ NPHY_RSSICAL_NPOLL);
+ }
+
+ for (result_idx = 0; result_idx < 4; result_idx++) {
+ if ((core == result_idx / 2) && (result_idx % 2 == 0)) {
+
+ min_d = NPHY_RSSICAL_MAXD;
+ min_vcm = 0;
+ min_poll =
+ NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL +
+ 1;
+ for (vcm = 0; vcm < vcm_level_max; vcm++) {
+ curr_d = poll_results[vcm][result_idx] *
+ poll_results[vcm][result_idx] +
+ poll_results[vcm][result_idx + 1] *
+ poll_results[vcm][result_idx + 1];
+ if (curr_d < min_d) {
+ min_d = curr_d;
+ min_vcm = vcm;
+ }
+ if (poll_results[vcm][result_idx] <
+ min_poll) {
+ min_poll =
+ poll_results[vcm]
+ [result_idx];
+ }
+ }
+ vcm_final = min_vcm;
+ poll_results_min[result_idx] = min_poll;
+ }
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ mod_radio_reg(pi, (core == PHY_CORE_0) ?
+ RADIO_2057_NB_MASTER_CORE0 :
+ RADIO_2057_NB_MASTER_CORE1,
+ RADIO_2057_VCM_MASK, vcm_final);
+ } else {
+ mod_radio_reg(pi, RADIO_2056_RX_RSSI_MISC |
+ ((core ==
+ PHY_CORE_0) ? RADIO_2056_RX0 :
+ RADIO_2056_RX1), RADIO_2056_VCM_MASK,
+ vcm_final << RADIO_2056_RSSI_VCM_SHIFT);
+ }
+
+ for (result_idx = 0; result_idx < 4; result_idx++) {
+ if (core == result_idx / 2) {
+ fine_digital_offset[result_idx] =
+ (NPHY_RSSICAL_NB_TARGET *
+ NPHY_RSSICAL_NPOLL) -
+ poll_results[vcm_final][result_idx];
+ if (fine_digital_offset[result_idx] < 0) {
+ fine_digital_offset[result_idx] =
+ ABS(fine_digital_offset
+ [result_idx]);
+ fine_digital_offset[result_idx] +=
+ (NPHY_RSSICAL_NPOLL / 2);
+ fine_digital_offset[result_idx] /=
+ NPHY_RSSICAL_NPOLL;
+ fine_digital_offset[result_idx] =
+ -fine_digital_offset[result_idx];
+ } else {
+ fine_digital_offset[result_idx] +=
+ (NPHY_RSSICAL_NPOLL / 2);
+ fine_digital_offset[result_idx] /=
+ NPHY_RSSICAL_NPOLL;
+ }
+
+ if (poll_results_min[result_idx] ==
+ NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL) {
+ fine_digital_offset[result_idx] =
+ (NPHY_RSSICAL_NB_TARGET -
+ NPHY_RSSICAL_MAXREAD - 1);
+ }
+
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0,
+ (s8)
+ fine_digital_offset
+ [result_idx],
+ (result_idx /
+ 2 ==
+ 0) ?
+ RADIO_MIMO_CORESEL_CORE1
+ :
+ RADIO_MIMO_CORESEL_CORE2,
+ (result_idx %
+ 2 ==
+ 0) ? NPHY_RAIL_I
+ : NPHY_RAIL_Q,
+ NPHY_RSSI_SEL_NB);
+ }
+ }
+
+ }
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+
+ if ((rxcore_state & (1 << core)) == 0)
+ continue;
+
+ for (wb_cnt = 0; wb_cnt < 2; wb_cnt++) {
+ if (wb_cnt == 0) {
+ rssi_type = NPHY_RSSI_SEL_W1;
+ target_code = NPHY_RSSICAL_W1_TARGET_REV3;
+ } else {
+ rssi_type = NPHY_RSSI_SEL_W2;
+ target_code = NPHY_RSSICAL_W2_TARGET_REV3;
+ }
+
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
+ core ==
+ PHY_CORE_0 ?
+ RADIO_MIMO_CORESEL_CORE1
+ :
+ RADIO_MIMO_CORESEL_CORE2,
+ NPHY_RAIL_I, rssi_type);
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
+ core ==
+ PHY_CORE_0 ?
+ RADIO_MIMO_CORESEL_CORE1
+ :
+ RADIO_MIMO_CORESEL_CORE2,
+ NPHY_RAIL_Q, rssi_type);
+
+ wlc_phy_poll_rssi_nphy(pi, rssi_type, poll_result_core,
+ NPHY_RSSICAL_NPOLL);
+
+ for (result_idx = 0; result_idx < 4; result_idx++) {
+ if (core == result_idx / 2) {
+ fine_digital_offset[result_idx] =
+ (target_code * NPHY_RSSICAL_NPOLL) -
+ poll_result_core[result_idx];
+ if (fine_digital_offset[result_idx] < 0) {
+ fine_digital_offset[result_idx]
+ =
+ ABS(fine_digital_offset
+ [result_idx]);
+ fine_digital_offset[result_idx]
+ += (NPHY_RSSICAL_NPOLL / 2);
+ fine_digital_offset[result_idx]
+ /= NPHY_RSSICAL_NPOLL;
+ fine_digital_offset[result_idx]
+ =
+ -fine_digital_offset
+ [result_idx];
+ } else {
+ fine_digital_offset[result_idx]
+ += (NPHY_RSSICAL_NPOLL / 2);
+ fine_digital_offset[result_idx]
+ /= NPHY_RSSICAL_NPOLL;
+ }
+
+ wlc_phy_scale_offset_rssi_nphy(pi, 0x0,
+ (s8)
+ fine_digital_offset
+ [core *
+ 2],
+ (core ==
+ PHY_CORE_0)
+ ?
+ RADIO_MIMO_CORESEL_CORE1
+ :
+ RADIO_MIMO_CORESEL_CORE2,
+ (result_idx
+ % 2 ==
+ 0) ?
+ NPHY_RAIL_I
+ :
+ NPHY_RAIL_Q,
+ rssi_type);
+ }
+ }
+
+ }
+ }
+
+ write_phy_reg(pi, 0x91, NPHY_Rfctrlintc1_save);
+ write_phy_reg(pi, 0x92, NPHY_Rfctrlintc2_save);
+
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
+
+ mod_phy_reg(pi, 0xe7, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0x78, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0xe7, (0x1 << 0), 0);
+
+ mod_phy_reg(pi, 0xec, (0x1 << 0), 1 << 0);
+ mod_phy_reg(pi, 0x78, (0x1 << 1), 1 << 1);
+ mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
+
+ write_phy_reg(pi, 0x8f, NPHY_AfectrlOverride1_save);
+ write_phy_reg(pi, 0xa5, NPHY_AfectrlOverride2_save);
+ write_phy_reg(pi, 0xa6, NPHY_AfectrlCore1_save);
+ write_phy_reg(pi, 0xa7, NPHY_AfectrlCore2_save);
+ write_phy_reg(pi, 0xe7, NPHY_RfctrlOverride0_save);
+ write_phy_reg(pi, 0xec, NPHY_RfctrlOverride1_save);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ write_phy_reg(pi, 0x342, NPHY_REV7_RfctrlOverride3_save);
+ write_phy_reg(pi, 0x343, NPHY_REV7_RfctrlOverride4_save);
+ write_phy_reg(pi, 0x346, NPHY_REV7_RfctrlOverride5_save);
+ write_phy_reg(pi, 0x347, NPHY_REV7_RfctrlOverride6_save);
+ }
+ write_phy_reg(pi, 0xe5, NPHY_RfctrlOverrideAux0_save);
+ write_phy_reg(pi, 0xe6, NPHY_RfctrlOverrideAux1_save);
+ write_phy_reg(pi, 0x78, NPHY_RfctrlCmd_save);
+ write_phy_reg(pi, 0xf9, NPHY_RfctrlMiscReg1_save);
+ write_phy_reg(pi, 0xfb, NPHY_RfctrlMiscReg2_save);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ write_phy_reg(pi, 0x340, NPHY_REV7_RfctrlMiscReg3_save);
+ write_phy_reg(pi, 0x341, NPHY_REV7_RfctrlMiscReg4_save);
+ write_phy_reg(pi, 0x344, NPHY_REV7_RfctrlMiscReg5_save);
+ write_phy_reg(pi, 0x345, NPHY_REV7_RfctrlMiscReg6_save);
+ }
+ write_phy_reg(pi, 0x7a, NPHY_RfctrlRSSIOTHERS1_save);
+ write_phy_reg(pi, 0x7d, NPHY_RfctrlRSSIOTHERS2_save);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ pi->rssical_cache.rssical_radio_regs_2G[0] =
+ read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
+ pi->rssical_cache.rssical_radio_regs_2G[1] =
+ read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
+ } else {
+ pi->rssical_cache.rssical_radio_regs_2G[0] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_RSSI_MISC |
+ RADIO_2056_RX0);
+ pi->rssical_cache.rssical_radio_regs_2G[1] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_RSSI_MISC |
+ RADIO_2056_RX1);
+ }
+
+ pi->rssical_cache.rssical_phyregs_2G[0] =
+ read_phy_reg(pi, 0x1a6);
+ pi->rssical_cache.rssical_phyregs_2G[1] =
+ read_phy_reg(pi, 0x1ac);
+ pi->rssical_cache.rssical_phyregs_2G[2] =
+ read_phy_reg(pi, 0x1b2);
+ pi->rssical_cache.rssical_phyregs_2G[3] =
+ read_phy_reg(pi, 0x1b8);
+ pi->rssical_cache.rssical_phyregs_2G[4] =
+ read_phy_reg(pi, 0x1a4);
+ pi->rssical_cache.rssical_phyregs_2G[5] =
+ read_phy_reg(pi, 0x1aa);
+ pi->rssical_cache.rssical_phyregs_2G[6] =
+ read_phy_reg(pi, 0x1b0);
+ pi->rssical_cache.rssical_phyregs_2G[7] =
+ read_phy_reg(pi, 0x1b6);
+ pi->rssical_cache.rssical_phyregs_2G[8] =
+ read_phy_reg(pi, 0x1a5);
+ pi->rssical_cache.rssical_phyregs_2G[9] =
+ read_phy_reg(pi, 0x1ab);
+ pi->rssical_cache.rssical_phyregs_2G[10] =
+ read_phy_reg(pi, 0x1b1);
+ pi->rssical_cache.rssical_phyregs_2G[11] =
+ read_phy_reg(pi, 0x1b7);
+
+ pi->nphy_rssical_chanspec_2G = pi->radio_chanspec;
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ pi->rssical_cache.rssical_radio_regs_5G[0] =
+ read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
+ pi->rssical_cache.rssical_radio_regs_5G[1] =
+ read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
+ } else {
+ pi->rssical_cache.rssical_radio_regs_5G[0] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_RSSI_MISC |
+ RADIO_2056_RX0);
+ pi->rssical_cache.rssical_radio_regs_5G[1] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_RSSI_MISC |
+ RADIO_2056_RX1);
+ }
+
+ pi->rssical_cache.rssical_phyregs_5G[0] =
+ read_phy_reg(pi, 0x1a6);
+ pi->rssical_cache.rssical_phyregs_5G[1] =
+ read_phy_reg(pi, 0x1ac);
+ pi->rssical_cache.rssical_phyregs_5G[2] =
+ read_phy_reg(pi, 0x1b2);
+ pi->rssical_cache.rssical_phyregs_5G[3] =
+ read_phy_reg(pi, 0x1b8);
+ pi->rssical_cache.rssical_phyregs_5G[4] =
+ read_phy_reg(pi, 0x1a4);
+ pi->rssical_cache.rssical_phyregs_5G[5] =
+ read_phy_reg(pi, 0x1aa);
+ pi->rssical_cache.rssical_phyregs_5G[6] =
+ read_phy_reg(pi, 0x1b0);
+ pi->rssical_cache.rssical_phyregs_5G[7] =
+ read_phy_reg(pi, 0x1b6);
+ pi->rssical_cache.rssical_phyregs_5G[8] =
+ read_phy_reg(pi, 0x1a5);
+ pi->rssical_cache.rssical_phyregs_5G[9] =
+ read_phy_reg(pi, 0x1ab);
+ pi->rssical_cache.rssical_phyregs_5G[10] =
+ read_phy_reg(pi, 0x1b1);
+ pi->rssical_cache.rssical_phyregs_5G[11] =
+ read_phy_reg(pi, 0x1b7);
+
+ pi->nphy_rssical_chanspec_5G = pi->radio_chanspec;
+ }
+
+ wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
+ wlc_phy_clip_det_nphy(pi, 1, clip_state);
+}
+
+static void wlc_phy_restore_rssical_nphy(phy_info_t *pi)
+{
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (pi->nphy_rssical_chanspec_2G == 0)
+ return;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0,
+ RADIO_2057_VCM_MASK,
+ pi->rssical_cache.
+ rssical_radio_regs_2G[0]);
+ mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1,
+ RADIO_2057_VCM_MASK,
+ pi->rssical_cache.
+ rssical_radio_regs_2G[1]);
+ } else {
+ mod_radio_reg(pi,
+ RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX0,
+ RADIO_2056_VCM_MASK,
+ pi->rssical_cache.
+ rssical_radio_regs_2G[0]);
+ mod_radio_reg(pi,
+ RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX1,
+ RADIO_2056_VCM_MASK,
+ pi->rssical_cache.
+ rssical_radio_regs_2G[1]);
+ }
+
+ write_phy_reg(pi, 0x1a6,
+ pi->rssical_cache.rssical_phyregs_2G[0]);
+ write_phy_reg(pi, 0x1ac,
+ pi->rssical_cache.rssical_phyregs_2G[1]);
+ write_phy_reg(pi, 0x1b2,
+ pi->rssical_cache.rssical_phyregs_2G[2]);
+ write_phy_reg(pi, 0x1b8,
+ pi->rssical_cache.rssical_phyregs_2G[3]);
+ write_phy_reg(pi, 0x1a4,
+ pi->rssical_cache.rssical_phyregs_2G[4]);
+ write_phy_reg(pi, 0x1aa,
+ pi->rssical_cache.rssical_phyregs_2G[5]);
+ write_phy_reg(pi, 0x1b0,
+ pi->rssical_cache.rssical_phyregs_2G[6]);
+ write_phy_reg(pi, 0x1b6,
+ pi->rssical_cache.rssical_phyregs_2G[7]);
+ write_phy_reg(pi, 0x1a5,
+ pi->rssical_cache.rssical_phyregs_2G[8]);
+ write_phy_reg(pi, 0x1ab,
+ pi->rssical_cache.rssical_phyregs_2G[9]);
+ write_phy_reg(pi, 0x1b1,
+ pi->rssical_cache.rssical_phyregs_2G[10]);
+ write_phy_reg(pi, 0x1b7,
+ pi->rssical_cache.rssical_phyregs_2G[11]);
+
+ } else {
+ if (pi->nphy_rssical_chanspec_5G == 0)
+ return;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0,
+ RADIO_2057_VCM_MASK,
+ pi->rssical_cache.
+ rssical_radio_regs_5G[0]);
+ mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1,
+ RADIO_2057_VCM_MASK,
+ pi->rssical_cache.
+ rssical_radio_regs_5G[1]);
+ } else {
+ mod_radio_reg(pi,
+ RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX0,
+ RADIO_2056_VCM_MASK,
+ pi->rssical_cache.
+ rssical_radio_regs_5G[0]);
+ mod_radio_reg(pi,
+ RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX1,
+ RADIO_2056_VCM_MASK,
+ pi->rssical_cache.
+ rssical_radio_regs_5G[1]);
+ }
+
+ write_phy_reg(pi, 0x1a6,
+ pi->rssical_cache.rssical_phyregs_5G[0]);
+ write_phy_reg(pi, 0x1ac,
+ pi->rssical_cache.rssical_phyregs_5G[1]);
+ write_phy_reg(pi, 0x1b2,
+ pi->rssical_cache.rssical_phyregs_5G[2]);
+ write_phy_reg(pi, 0x1b8,
+ pi->rssical_cache.rssical_phyregs_5G[3]);
+ write_phy_reg(pi, 0x1a4,
+ pi->rssical_cache.rssical_phyregs_5G[4]);
+ write_phy_reg(pi, 0x1aa,
+ pi->rssical_cache.rssical_phyregs_5G[5]);
+ write_phy_reg(pi, 0x1b0,
+ pi->rssical_cache.rssical_phyregs_5G[6]);
+ write_phy_reg(pi, 0x1b6,
+ pi->rssical_cache.rssical_phyregs_5G[7]);
+ write_phy_reg(pi, 0x1a5,
+ pi->rssical_cache.rssical_phyregs_5G[8]);
+ write_phy_reg(pi, 0x1ab,
+ pi->rssical_cache.rssical_phyregs_5G[9]);
+ write_phy_reg(pi, 0x1b1,
+ pi->rssical_cache.rssical_phyregs_5G[10]);
+ write_phy_reg(pi, 0x1b7,
+ pi->rssical_cache.rssical_phyregs_5G[11]);
+ }
+}
+
+static u16
+wlc_phy_gen_load_samples_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
+ u8 dac_test_mode)
+{
+ u8 phy_bw, is_phybw40;
+ u16 num_samps, t, spur;
+ fixed theta = 0, rot = 0;
+ u32 tbl_len;
+ cs32 *tone_buf = NULL;
+
+ is_phybw40 = CHSPEC_IS40(pi->radio_chanspec);
+ phy_bw = (is_phybw40 == 1) ? 40 : 20;
+ tbl_len = (phy_bw << 3);
+
+ if (dac_test_mode == 1) {
+ spur = read_phy_reg(pi, 0x01);
+ spur = (spur >> 15) & 1;
+ phy_bw = (spur == 1) ? 82 : 80;
+ phy_bw = (is_phybw40 == 1) ? (phy_bw << 1) : phy_bw;
+
+ tbl_len = (phy_bw << 1);
+ }
+
+ tone_buf = kmalloc(sizeof(cs32) * tbl_len, GFP_ATOMIC);
+ if (tone_buf == NULL) {
+ return 0;
+ }
+
+ num_samps = (u16) tbl_len;
+ rot = FIXED((f_kHz * 36) / phy_bw) / 100;
+ theta = 0;
+
+ for (t = 0; t < num_samps; t++) {
+
+ wlc_phy_cordic(theta, &tone_buf[t]);
+
+ theta += rot;
+
+ tone_buf[t].q = (s32) FLOAT(tone_buf[t].q * max_val);
+ tone_buf[t].i = (s32) FLOAT(tone_buf[t].i * max_val);
+ }
+
+ wlc_phy_loadsampletable_nphy(pi, tone_buf, num_samps);
+
+ kfree(tone_buf);
+
+ return num_samps;
+}
+
+int
+wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
+ u8 iqmode, u8 dac_test_mode, bool modify_bbmult)
+{
+ u16 num_samps;
+ u16 loops = 0xffff;
+ u16 wait = 0;
+
+ num_samps =
+ wlc_phy_gen_load_samples_nphy(pi, f_kHz, max_val, dac_test_mode);
+ if (num_samps == 0) {
+ return -EBADE;
+ }
+
+ wlc_phy_runsamples_nphy(pi, num_samps, loops, wait, iqmode,
+ dac_test_mode, modify_bbmult);
+
+ return 0;
+}
+
+static void
+wlc_phy_loadsampletable_nphy(phy_info_t *pi, cs32 *tone_buf,
+ u16 num_samps)
+{
+ u16 t;
+ u32 *data_buf = NULL;
+
+ data_buf = kmalloc(sizeof(u32) * num_samps, GFP_ATOMIC);
+ if (data_buf == NULL) {
+ return;
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ for (t = 0; t < num_samps; t++) {
+ data_buf[t] = ((((unsigned int)tone_buf[t].i) & 0x3ff) << 10) |
+ (((unsigned int)tone_buf[t].q) & 0x3ff);
+ }
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SAMPLEPLAY, num_samps, 0, 32,
+ data_buf);
+
+ kfree(data_buf);
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+static void
+wlc_phy_runsamples_nphy(phy_info_t *pi, u16 num_samps, u16 loops,
+ u16 wait, u8 iqmode, u8 dac_test_mode,
+ bool modify_bbmult)
+{
+ u16 bb_mult;
+ u8 phy_bw, sample_cmd;
+ u16 orig_RfseqCoreActv;
+ u16 lpf_bw_ctl_override3, lpf_bw_ctl_override4, lpf_bw_ctl_miscreg3,
+ lpf_bw_ctl_miscreg4;
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ phy_bw = 20;
+ if (CHSPEC_IS40(pi->radio_chanspec))
+ phy_bw = 40;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ lpf_bw_ctl_override3 = read_phy_reg(pi, 0x342) & (0x1 << 7);
+ lpf_bw_ctl_override4 = read_phy_reg(pi, 0x343) & (0x1 << 7);
+ if (lpf_bw_ctl_override3 | lpf_bw_ctl_override4) {
+ lpf_bw_ctl_miscreg3 = read_phy_reg(pi, 0x340) &
+ (0x7 << 8);
+ lpf_bw_ctl_miscreg4 = read_phy_reg(pi, 0x341) &
+ (0x7 << 8);
+ } else {
+ wlc_phy_rfctrl_override_nphy_rev7(pi,
+ (0x1 << 7),
+ wlc_phy_read_lpf_bw_ctl_nphy
+ (pi, 0), 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+
+ pi->nphy_sample_play_lpf_bw_ctl_ovr = true;
+
+ lpf_bw_ctl_miscreg3 = read_phy_reg(pi, 0x340) &
+ (0x7 << 8);
+ lpf_bw_ctl_miscreg4 = read_phy_reg(pi, 0x341) &
+ (0x7 << 8);
+ }
+ }
+
+ if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) == 0) {
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
+ &bb_mult);
+ pi->nphy_bb_mult_save =
+ BB_MULT_VALID_MASK | (bb_mult & BB_MULT_MASK);
+ }
+
+ if (modify_bbmult) {
+ bb_mult = (phy_bw == 20) ? 100 : 71;
+ bb_mult = (bb_mult << 8) + bb_mult;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
+ &bb_mult);
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+
+ write_phy_reg(pi, 0xc6, num_samps - 1);
+
+ if (loops != 0xffff) {
+ write_phy_reg(pi, 0xc4, loops - 1);
+ } else {
+ write_phy_reg(pi, 0xc4, loops);
+ }
+ write_phy_reg(pi, 0xc5, wait);
+
+ orig_RfseqCoreActv = read_phy_reg(pi, 0xa1);
+ or_phy_reg(pi, 0xa1, NPHY_RfseqMode_CoreActv_override);
+ if (iqmode) {
+
+ and_phy_reg(pi, 0xc2, 0x7FFF);
+
+ or_phy_reg(pi, 0xc2, 0x8000);
+ } else {
+
+ sample_cmd = (dac_test_mode == 1) ? 0x5 : 0x1;
+ write_phy_reg(pi, 0xc3, sample_cmd);
+ }
+
+ SPINWAIT(((read_phy_reg(pi, 0xa4) & 0x1) == 1), 1000);
+
+ write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
+}
+
+void wlc_phy_stopplayback_nphy(phy_info_t *pi)
+{
+ u16 playback_status;
+ u16 bb_mult;
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ playback_status = read_phy_reg(pi, 0xc7);
+ if (playback_status & 0x1) {
+ or_phy_reg(pi, 0xc3, NPHY_sampleCmd_STOP);
+ } else if (playback_status & 0x2) {
+
+ and_phy_reg(pi, 0xc2,
+ (u16) ~NPHY_iqloCalCmdGctl_IQLO_CAL_EN);
+ }
+
+ and_phy_reg(pi, 0xc3, (u16) ~(0x1 << 2));
+
+ if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) != 0) {
+
+ bb_mult = pi->nphy_bb_mult_save & BB_MULT_MASK;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
+ &bb_mult);
+
+ pi->nphy_bb_mult_save = 0;
+ }
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7) || NREV_GE(pi->pubpi.phy_rev, 8)) {
+ if (pi->nphy_sample_play_lpf_bw_ctl_ovr) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi,
+ (0x1 << 7),
+ 0, 0, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ pi->nphy_sample_play_lpf_bw_ctl_ovr = false;
+ }
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi)
+{
+ u16 base_idx[2], curr_gain[2];
+ u8 core_no;
+ nphy_txgains_t target_gain;
+ u32 *tx_pwrctrl_tbl = NULL;
+
+ if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
+ curr_gain);
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+
+ for (core_no = 0; core_no < 2; core_no++) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ target_gain.ipa[core_no] =
+ curr_gain[core_no] & 0x0007;
+ target_gain.pad[core_no] =
+ ((curr_gain[core_no] & 0x00F8) >> 3);
+ target_gain.pga[core_no] =
+ ((curr_gain[core_no] & 0x0F00) >> 8);
+ target_gain.txgm[core_no] =
+ ((curr_gain[core_no] & 0x7000) >> 12);
+ target_gain.txlpf[core_no] =
+ ((curr_gain[core_no] & 0x8000) >> 15);
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ target_gain.ipa[core_no] =
+ curr_gain[core_no] & 0x000F;
+ target_gain.pad[core_no] =
+ ((curr_gain[core_no] & 0x00F0) >> 4);
+ target_gain.pga[core_no] =
+ ((curr_gain[core_no] & 0x0F00) >> 8);
+ target_gain.txgm[core_no] =
+ ((curr_gain[core_no] & 0x7000) >> 12);
+ } else {
+ target_gain.ipa[core_no] =
+ curr_gain[core_no] & 0x0003;
+ target_gain.pad[core_no] =
+ ((curr_gain[core_no] & 0x000C) >> 2);
+ target_gain.pga[core_no] =
+ ((curr_gain[core_no] & 0x0070) >> 4);
+ target_gain.txgm[core_no] =
+ ((curr_gain[core_no] & 0x0380) >> 7);
+ }
+ }
+ } else {
+ base_idx[0] = (read_phy_reg(pi, 0x1ed) >> 8) & 0x7f;
+ base_idx[1] = (read_phy_reg(pi, 0x1ee) >> 8) & 0x7f;
+ for (core_no = 0; core_no < 2; core_no++) {
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (PHY_IPA(pi)) {
+ tx_pwrctrl_tbl =
+ wlc_phy_get_ipa_gaintbl_nphy(pi);
+ } else {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if NREV_IS
+ (pi->pubpi.phy_rev, 3) {
+ tx_pwrctrl_tbl =
+ nphy_tpc_5GHz_txgain_rev3;
+ } else if NREV_IS
+ (pi->pubpi.phy_rev, 4) {
+ tx_pwrctrl_tbl =
+ (pi->srom_fem5g.
+ extpagain ==
+ 3) ?
+ nphy_tpc_5GHz_txgain_HiPwrEPA
+ :
+ nphy_tpc_5GHz_txgain_rev4;
+ } else {
+ tx_pwrctrl_tbl =
+ nphy_tpc_5GHz_txgain_rev5;
+ }
+ } else {
+ if (NREV_GE
+ (pi->pubpi.phy_rev, 7)) {
+ if (pi->pubpi.
+ radiorev == 3) {
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_epa_2057rev3;
+ } else if (pi->pubpi.
+ radiorev ==
+ 5) {
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_epa_2057rev5;
+ }
+
+ } else {
+ if (NREV_GE
+ (pi->pubpi.phy_rev,
+ 5)
+ && (pi->srom_fem2g.
+ extpagain ==
+ 3)) {
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_HiPwrEPA;
+ } else {
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_rev3;
+ }
+ }
+ }
+ }
+ if NREV_GE
+ (pi->pubpi.phy_rev, 7) {
+ target_gain.ipa[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 16) & 0x7;
+ target_gain.pad[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 19) & 0x1f;
+ target_gain.pga[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 24) & 0xf;
+ target_gain.txgm[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 28) & 0x7;
+ target_gain.txlpf[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 31) & 0x1;
+ } else {
+ target_gain.ipa[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 16) & 0xf;
+ target_gain.pad[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 20) & 0xf;
+ target_gain.pga[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 24) & 0xf;
+ target_gain.txgm[core_no] =
+ (tx_pwrctrl_tbl[base_idx[core_no]]
+ >> 28) & 0x7;
+ }
+ } else {
+ target_gain.ipa[core_no] =
+ (nphy_tpc_txgain[base_idx[core_no]] >> 16) &
+ 0x3;
+ target_gain.pad[core_no] =
+ (nphy_tpc_txgain[base_idx[core_no]] >> 18) &
+ 0x3;
+ target_gain.pga[core_no] =
+ (nphy_tpc_txgain[base_idx[core_no]] >> 20) &
+ 0x7;
+ target_gain.txgm[core_no] =
+ (nphy_tpc_txgain[base_idx[core_no]] >> 23) &
+ 0x7;
+ }
+ }
+ }
+
+ return target_gain;
+}
+
+static void
+wlc_phy_iqcal_gainparams_nphy(phy_info_t *pi, u16 core_no,
+ nphy_txgains_t target_gain,
+ nphy_iqcal_params_t *params)
+{
+ u8 k;
+ int idx;
+ u16 gain_index;
+ u8 band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ params->txlpf = target_gain.txlpf[core_no];
+ }
+ params->txgm = target_gain.txgm[core_no];
+ params->pga = target_gain.pga[core_no];
+ params->pad = target_gain.pad[core_no];
+ params->ipa = target_gain.ipa[core_no];
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ params->cal_gain =
+ ((params->txlpf << 15) | (params->
+ txgm << 12) | (params->
+ pga << 8) |
+ (params->pad << 3) | (params->ipa));
+ } else {
+ params->cal_gain =
+ ((params->txgm << 12) | (params->
+ pga << 8) | (params->
+ pad << 4) |
+ (params->ipa));
+ }
+ params->ncorr[0] = 0x79;
+ params->ncorr[1] = 0x79;
+ params->ncorr[2] = 0x79;
+ params->ncorr[3] = 0x79;
+ params->ncorr[4] = 0x79;
+ } else {
+
+ gain_index = ((target_gain.pad[core_no] << 0) |
+ (target_gain.pga[core_no] << 4) | (target_gain.
+ txgm[core_no]
+ << 8));
+
+ idx = -1;
+ for (k = 0; k < NPHY_IQCAL_NUMGAINS; k++) {
+ if (tbl_iqcal_gainparams_nphy[band_idx][k][0] ==
+ gain_index) {
+ idx = k;
+ break;
+ }
+ }
+
+ params->txgm = tbl_iqcal_gainparams_nphy[band_idx][k][1];
+ params->pga = tbl_iqcal_gainparams_nphy[band_idx][k][2];
+ params->pad = tbl_iqcal_gainparams_nphy[band_idx][k][3];
+ params->cal_gain = ((params->txgm << 7) | (params->pga << 4) |
+ (params->pad << 2));
+ params->ncorr[0] = tbl_iqcal_gainparams_nphy[band_idx][k][4];
+ params->ncorr[1] = tbl_iqcal_gainparams_nphy[band_idx][k][5];
+ params->ncorr[2] = tbl_iqcal_gainparams_nphy[band_idx][k][6];
+ params->ncorr[3] = tbl_iqcal_gainparams_nphy[band_idx][k][7];
+ }
+}
+
+static void wlc_phy_txcal_radio_setup_nphy(phy_info_t *pi)
+{
+ u16 jtag_core, core;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ for (core = 0; core <= 1; core++) {
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 0] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MASTER);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 1] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ IQCAL_VCM_HG);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 2] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ IQCAL_IDAC);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 3] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 4] = 0;
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 5] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MUX);
+
+ if (pi->pubpi.radiorev != 5)
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 6] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSIA);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 7] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core, TSSIG);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 8] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSI_MISC1);
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MASTER, 0x0a);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ IQCAL_VCM_HG, 0x43);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ IQCAL_IDAC, 0x55);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSI_VCM, 0x00);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSIG, 0x00);
+ if (pi->use_int_tx_iqlo_cal_nphy) {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX,
+ core, TX_SSI_MUX, 0x4);
+ if (!
+ (pi->
+ internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057,
+ TX, core,
+ TSSIA, 0x31);
+ } else {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057,
+ TX, core,
+ TSSIA, 0x21);
+ }
+ }
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSI_MISC1, 0x00);
+ } else {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MASTER, 0x06);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ IQCAL_VCM_HG, 0x43);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ IQCAL_IDAC, 0x55);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSI_VCM, 0x00);
+
+ if (pi->pubpi.radiorev != 5)
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX,
+ core, TSSIA, 0x00);
+ if (pi->use_int_tx_iqlo_cal_nphy) {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX,
+ core, TX_SSI_MUX,
+ 0x06);
+ if (!
+ (pi->
+ internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057,
+ TX, core,
+ TSSIG, 0x31);
+ } else {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057,
+ TX, core,
+ TSSIG, 0x21);
+ }
+ }
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSI_MISC1, 0x00);
+ }
+ }
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ for (core = 0; core <= 1; core++) {
+ jtag_core =
+ (core ==
+ PHY_CORE_0) ? RADIO_2056_TX0 : RADIO_2056_TX1;
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 0] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MASTER |
+ jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 1] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_IQCAL_VCM_HG |
+ jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 2] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_IQCAL_IDAC |
+ jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 3] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TSSI_VCM | jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 4] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TX_AMP_DET |
+ jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 5] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MUX |
+ jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 6] =
+ read_radio_reg(pi, RADIO_2056_TX_TSSIA | jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 7] =
+ read_radio_reg(pi, RADIO_2056_TX_TSSIG | jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 8] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC1 |
+ jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 9] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC2 |
+ jtag_core);
+
+ pi->tx_rx_cal_radio_saveregs[(core * 11) + 10] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC3 |
+ jtag_core);
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MASTER |
+ jtag_core, 0x0a);
+ write_radio_reg(pi,
+ RADIO_2056_TX_IQCAL_VCM_HG |
+ jtag_core, 0x40);
+ write_radio_reg(pi,
+ RADIO_2056_TX_IQCAL_IDAC |
+ jtag_core, 0x55);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_VCM |
+ jtag_core, 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_AMP_DET |
+ jtag_core, 0x00);
+
+ if (PHY_IPA(pi)) {
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MUX
+ | jtag_core, 0x4);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSIA |
+ jtag_core, 0x1);
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MUX
+ | jtag_core, 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSIA |
+ jtag_core, 0x2f);
+ }
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSIG | jtag_core,
+ 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC1 |
+ jtag_core, 0x00);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC2 |
+ jtag_core, 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC3 |
+ jtag_core, 0x00);
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MASTER |
+ jtag_core, 0x06);
+ write_radio_reg(pi,
+ RADIO_2056_TX_IQCAL_VCM_HG |
+ jtag_core, 0x40);
+ write_radio_reg(pi,
+ RADIO_2056_TX_IQCAL_IDAC |
+ jtag_core, 0x55);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_VCM |
+ jtag_core, 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_AMP_DET |
+ jtag_core, 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSIA | jtag_core,
+ 0x00);
+
+ if (PHY_IPA(pi)) {
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MUX
+ | jtag_core, 0x06);
+ if (NREV_LT(pi->pubpi.phy_rev, 5)) {
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSIG
+ | jtag_core,
+ 0x11);
+ } else {
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSIG
+ | jtag_core,
+ 0x1);
+ }
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MUX
+ | jtag_core, 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSIG |
+ jtag_core, 0x20);
+ }
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC1 |
+ jtag_core, 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC2 |
+ jtag_core, 0x00);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC3 |
+ jtag_core, 0x00);
+ }
+ }
+ } else {
+
+ pi->tx_rx_cal_radio_saveregs[0] =
+ read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
+ write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1, 0x29);
+ pi->tx_rx_cal_radio_saveregs[1] =
+ read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
+ write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2, 0x54);
+
+ pi->tx_rx_cal_radio_saveregs[2] =
+ read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
+ write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1, 0x29);
+ pi->tx_rx_cal_radio_saveregs[3] =
+ read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
+ write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2, 0x54);
+
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
+ pi->tx_rx_cal_radio_saveregs[5] =
+ read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
+
+ if ((read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand) ==
+ 0) {
+
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x04);
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x04);
+ } else {
+
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x20);
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x20);
+ }
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+
+ or_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM, 0x20);
+ or_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM, 0x20);
+ } else {
+
+ and_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM, 0xdf);
+ and_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM, 0xdf);
+ }
+ }
+}
+
+static void wlc_phy_txcal_radio_cleanup_nphy(phy_info_t *pi)
+{
+ u16 jtag_core, core;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ for (core = 0; core <= 1; core++) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MASTER,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 0]);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_VCM_HG,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 1]);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_IDAC,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 2]);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 3]);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TX_SSI_MUX,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 5]);
+
+ if (pi->pubpi.radiorev != 5)
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSIA,
+ pi->
+ tx_rx_cal_radio_saveregs[(core
+ *
+ 11) +
+ 6]);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSIG,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 7]);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_MISC1,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 8]);
+ }
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ for (core = 0; core <= 1; core++) {
+ jtag_core =
+ (core ==
+ PHY_CORE_0) ? RADIO_2056_TX0 : RADIO_2056_TX1;
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MASTER | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 0]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_IQCAL_VCM_HG | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 1]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_IQCAL_IDAC | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 2]);
+
+ write_radio_reg(pi, RADIO_2056_TX_TSSI_VCM | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 3]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_AMP_DET | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 4]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MUX | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 5]);
+
+ write_radio_reg(pi, RADIO_2056_TX_TSSIA | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 6]);
+
+ write_radio_reg(pi, RADIO_2056_TX_TSSIG | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 7]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC1 | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 8]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC2 | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 9]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TSSI_MISC3 | jtag_core,
+ pi->
+ tx_rx_cal_radio_saveregs[(core * 11) +
+ 10]);
+ }
+ } else {
+
+ write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1,
+ pi->tx_rx_cal_radio_saveregs[0]);
+ write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2,
+ pi->tx_rx_cal_radio_saveregs[1]);
+ write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1,
+ pi->tx_rx_cal_radio_saveregs[2]);
+ write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2,
+ pi->tx_rx_cal_radio_saveregs[3]);
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1,
+ pi->tx_rx_cal_radio_saveregs[4]);
+ write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2,
+ pi->tx_rx_cal_radio_saveregs[5]);
+ }
+}
+
+static void wlc_phy_txcal_physetup_nphy(phy_info_t *pi)
+{
+ u16 val, mask;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6);
+ pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 0xa7);
+
+ mask = ((0x3 << 8) | (0x3 << 10));
+ val = (0x2 << 8);
+ val |= (0x2 << 10);
+ mod_phy_reg(pi, 0xa6, mask, val);
+ mod_phy_reg(pi, 0xa7, mask, val);
+
+ val = read_phy_reg(pi, 0x8f);
+ pi->tx_rx_cal_phy_saveregs[2] = val;
+ val |= ((0x1 << 9) | (0x1 << 10));
+ write_phy_reg(pi, 0x8f, val);
+
+ val = read_phy_reg(pi, 0xa5);
+ pi->tx_rx_cal_phy_saveregs[3] = val;
+ val |= ((0x1 << 9) | (0x1 << 10));
+ write_phy_reg(pi, 0xa5, val);
+
+ pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 0x01);
+ mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
+ &val);
+ pi->tx_rx_cal_phy_saveregs[5] = val;
+ val = 0;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
+ &val);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
+ &val);
+ pi->tx_rx_cal_phy_saveregs[6] = val;
+ val = 0;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
+ &val);
+
+ pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 0x91);
+ pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 0x92);
+
+ if (!(pi->use_int_tx_iqlo_cal_nphy)) {
+
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_PA,
+ 1,
+ RADIO_MIMO_CORESEL_CORE1
+ |
+ RADIO_MIMO_CORESEL_CORE2);
+ } else {
+
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_PA,
+ 0,
+ RADIO_MIMO_CORESEL_CORE1
+ |
+ RADIO_MIMO_CORESEL_CORE2);
+ }
+
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ 0x2, RADIO_MIMO_CORESEL_CORE1);
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ 0x8, RADIO_MIMO_CORESEL_CORE2);
+
+ pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 0x297);
+ pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 0x29b);
+ mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (0) << 0);
+
+ mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (0) << 0);
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)
+ || NREV_GE(pi->pubpi.phy_rev, 8)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
+ wlc_phy_read_lpf_bw_ctl_nphy
+ (pi, 0), 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ }
+
+ if (pi->use_int_tx_iqlo_cal_nphy
+ && !(pi->internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)) {
+
+ mod_radio_reg(pi, RADIO_2057_OVR_REG0, 1 << 4,
+ 1 << 4);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ mod_radio_reg(pi,
+ RADIO_2057_PAD2G_TUNE_PUS_CORE0,
+ 1, 0);
+ mod_radio_reg(pi,
+ RADIO_2057_PAD2G_TUNE_PUS_CORE1,
+ 1, 0);
+ } else {
+ mod_radio_reg(pi,
+ RADIO_2057_IPA5G_CASCOFFV_PU_CORE0,
+ 1, 0);
+ mod_radio_reg(pi,
+ RADIO_2057_IPA5G_CASCOFFV_PU_CORE1,
+ 1, 0);
+ }
+ } else if (NREV_GE(pi->pubpi.phy_rev, 8)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi,
+ (0x1 << 3), 0,
+ 0x3, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ }
+ }
+ } else {
+ pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6);
+ pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 0xa7);
+
+ mask = ((0x3 << 12) | (0x3 << 14));
+ val = (0x2 << 12);
+ val |= (0x2 << 14);
+ mod_phy_reg(pi, 0xa6, mask, val);
+ mod_phy_reg(pi, 0xa7, mask, val);
+
+ val = read_phy_reg(pi, 0xa5);
+ pi->tx_rx_cal_phy_saveregs[2] = val;
+ val |= ((0x1 << 12) | (0x1 << 13));
+ write_phy_reg(pi, 0xa5, val);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
+ &val);
+ pi->tx_rx_cal_phy_saveregs[3] = val;
+ val |= 0x2000;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
+ &val);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
+ &val);
+ pi->tx_rx_cal_phy_saveregs[4] = val;
+ val |= 0x2000;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
+ &val);
+
+ pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 0x91);
+ pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 0x92);
+ val = CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120;
+ write_phy_reg(pi, 0x91, val);
+ write_phy_reg(pi, 0x92, val);
+ }
+}
+
+static void wlc_phy_txcal_phycleanup_nphy(phy_info_t *pi)
+{
+ u16 mask;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ write_phy_reg(pi, 0xa6, pi->tx_rx_cal_phy_saveregs[0]);
+ write_phy_reg(pi, 0xa7, pi->tx_rx_cal_phy_saveregs[1]);
+ write_phy_reg(pi, 0x8f, pi->tx_rx_cal_phy_saveregs[2]);
+ write_phy_reg(pi, 0xa5, pi->tx_rx_cal_phy_saveregs[3]);
+ write_phy_reg(pi, 0x01, pi->tx_rx_cal_phy_saveregs[4]);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
+ &pi->tx_rx_cal_phy_saveregs[5]);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
+ &pi->tx_rx_cal_phy_saveregs[6]);
+
+ write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[7]);
+ write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[8]);
+
+ write_phy_reg(pi, 0x297, pi->tx_rx_cal_phy_saveregs[9]);
+ write_phy_reg(pi, 0x29b, pi->tx_rx_cal_phy_saveregs[10]);
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)
+ || NREV_GE(pi->pubpi.phy_rev, 8)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7), 0, 0,
+ 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ }
+
+ wlc_phy_resetcca_nphy(pi);
+
+ if (pi->use_int_tx_iqlo_cal_nphy
+ && !(pi->internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ mod_radio_reg(pi,
+ RADIO_2057_PAD2G_TUNE_PUS_CORE0,
+ 1, 1);
+ mod_radio_reg(pi,
+ RADIO_2057_PAD2G_TUNE_PUS_CORE1,
+ 1, 1);
+ } else {
+ mod_radio_reg(pi,
+ RADIO_2057_IPA5G_CASCOFFV_PU_CORE0,
+ 1, 1);
+ mod_radio_reg(pi,
+ RADIO_2057_IPA5G_CASCOFFV_PU_CORE1,
+ 1, 1);
+ }
+
+ mod_radio_reg(pi, RADIO_2057_OVR_REG0, 1 << 4,
+ 0);
+ } else if (NREV_GE(pi->pubpi.phy_rev, 8)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi,
+ (0x1 << 3), 0,
+ 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ }
+ }
+ } else {
+ mask = ((0x3 << 12) | (0x3 << 14));
+ mod_phy_reg(pi, 0xa6, mask, pi->tx_rx_cal_phy_saveregs[0]);
+ mod_phy_reg(pi, 0xa7, mask, pi->tx_rx_cal_phy_saveregs[1]);
+ write_phy_reg(pi, 0xa5, pi->tx_rx_cal_phy_saveregs[2]);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
+ &pi->tx_rx_cal_phy_saveregs[3]);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
+ &pi->tx_rx_cal_phy_saveregs[4]);
+
+ write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[5]);
+ write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[6]);
+ }
+}
+
+#define NPHY_CAL_TSSISAMPS 64
+#define NPHY_TEST_TONE_FREQ_40MHz 4000
+#define NPHY_TEST_TONE_FREQ_20MHz 2500
+
+void
+wlc_phy_est_tonepwr_nphy(phy_info_t *pi, s32 *qdBm_pwrbuf, u8 num_samps)
+{
+ u16 tssi_reg;
+ s32 temp, pwrindex[2];
+ s32 idle_tssi[2];
+ s32 rssi_buf[4];
+ s32 tssival[2];
+ u8 tssi_type;
+
+ tssi_reg = read_phy_reg(pi, 0x1e9);
+
+ temp = (s32) (tssi_reg & 0x3f);
+ idle_tssi[0] = (temp <= 31) ? temp : (temp - 64);
+
+ temp = (s32) ((tssi_reg >> 8) & 0x3f);
+ idle_tssi[1] = (temp <= 31) ? temp : (temp - 64);
+
+ tssi_type =
+ CHSPEC_IS5G(pi->radio_chanspec) ?
+ (u8)NPHY_RSSI_SEL_TSSI_5G:(u8)NPHY_RSSI_SEL_TSSI_2G;
+
+ wlc_phy_poll_rssi_nphy(pi, tssi_type, rssi_buf, num_samps);
+
+ tssival[0] = rssi_buf[0] / ((s32) num_samps);
+ tssival[1] = rssi_buf[2] / ((s32) num_samps);
+
+ pwrindex[0] = idle_tssi[0] - tssival[0] + 64;
+ pwrindex[1] = idle_tssi[1] - tssival[1] + 64;
+
+ if (pwrindex[0] < 0) {
+ pwrindex[0] = 0;
+ } else if (pwrindex[0] > 63) {
+ pwrindex[0] = 63;
+ }
+
+ if (pwrindex[1] < 0) {
+ pwrindex[1] = 0;
+ } else if (pwrindex[1] > 63) {
+ pwrindex[1] = 63;
+ }
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 1,
+ (u32) pwrindex[0], 32, &qdBm_pwrbuf[0]);
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 1,
+ (u32) pwrindex[1], 32, &qdBm_pwrbuf[1]);
+}
+
+static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi)
+{
+ u16 txcal_gain[2];
+
+ pi->nphy_txcal_pwr_idx[0] = pi->nphy_cal_orig_pwr_idx[0];
+ pi->nphy_txcal_pwr_idx[1] = pi->nphy_cal_orig_pwr_idx[0];
+ wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_cal_orig_pwr_idx[0], true);
+ wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_cal_orig_pwr_idx[1], true);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
+ txcal_gain);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ txcal_gain[0] = (txcal_gain[0] & 0xF000) | 0x0F40;
+ txcal_gain[1] = (txcal_gain[1] & 0xF000) | 0x0F40;
+ } else {
+ txcal_gain[0] = (txcal_gain[0] & 0xF000) | 0x0F60;
+ txcal_gain[1] = (txcal_gain[1] & 0xF000) | 0x0F60;
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
+ txcal_gain);
+}
+
+static void wlc_phy_precal_txgain_nphy(phy_info_t *pi)
+{
+ bool save_bbmult = false;
+ u8 txcal_index_2057_rev5n7 = 0;
+ u8 txcal_index_2057_rev3n4n6 = 10;
+
+ if (pi->use_int_tx_iqlo_cal_nphy) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if ((pi->pubpi.radiorev == 3) ||
+ (pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+
+ pi->nphy_txcal_pwr_idx[0] =
+ txcal_index_2057_rev3n4n6;
+ pi->nphy_txcal_pwr_idx[1] =
+ txcal_index_2057_rev3n4n6;
+ wlc_phy_txpwr_index_nphy(pi, 3,
+ txcal_index_2057_rev3n4n6,
+ false);
+ } else {
+
+ pi->nphy_txcal_pwr_idx[0] =
+ txcal_index_2057_rev5n7;
+ pi->nphy_txcal_pwr_idx[1] =
+ txcal_index_2057_rev5n7;
+ wlc_phy_txpwr_index_nphy(pi, 3,
+ txcal_index_2057_rev5n7,
+ false);
+ }
+ save_bbmult = true;
+
+ } else if (NREV_LT(pi->pubpi.phy_rev, 5)) {
+ wlc_phy_cal_txgainctrl_nphy(pi, 11, false);
+ if (pi->sh->hw_phytxchain != 3) {
+ pi->nphy_txcal_pwr_idx[1] =
+ pi->nphy_txcal_pwr_idx[0];
+ wlc_phy_txpwr_index_nphy(pi, 3,
+ pi->
+ nphy_txcal_pwr_idx[0],
+ true);
+ save_bbmult = true;
+ }
+
+ } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+ if (PHY_IPA(pi)) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ wlc_phy_cal_txgainctrl_nphy(pi, 12,
+ false);
+ } else {
+ pi->nphy_txcal_pwr_idx[0] = 80;
+ pi->nphy_txcal_pwr_idx[1] = 80;
+ wlc_phy_txpwr_index_nphy(pi, 3, 80,
+ false);
+ save_bbmult = true;
+ }
+ } else {
+
+ wlc_phy_internal_cal_txgain_nphy(pi);
+ save_bbmult = true;
+ }
+
+ } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
+ if (PHY_IPA(pi)) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ wlc_phy_cal_txgainctrl_nphy(pi, 12,
+ false);
+ } else {
+ wlc_phy_cal_txgainctrl_nphy(pi, 14,
+ false);
+ }
+ } else {
+
+ wlc_phy_internal_cal_txgain_nphy(pi);
+ save_bbmult = true;
+ }
+ }
+
+ } else {
+ wlc_phy_cal_txgainctrl_nphy(pi, 10, false);
+ }
+
+ if (save_bbmult) {
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16,
+ &pi->nphy_txcal_bbmult);
+ }
+}
+
+void
+wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower, bool debug)
+{
+ int gainctrl_loopidx;
+ uint core;
+ u16 m0m1, curr_m0m1;
+ s32 delta_power;
+ s32 txpwrindex;
+ s32 qdBm_power[2];
+ u16 orig_BBConfig;
+ u16 phy_saveregs[4];
+ u32 freq_test;
+ u16 ampl_test = 250;
+ uint stepsize;
+ bool phyhang_avoid_state = false;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ stepsize = 2;
+ } else {
+
+ stepsize = 1;
+ }
+
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ freq_test = 5000;
+ } else {
+ freq_test = 2500;
+ }
+
+ wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_cal_orig_pwr_idx[0], true);
+ wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_cal_orig_pwr_idx[1], true);
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ phyhang_avoid_state = pi->phyhang_avoid;
+ pi->phyhang_avoid = false;
+
+ phy_saveregs[0] = read_phy_reg(pi, 0x91);
+ phy_saveregs[1] = read_phy_reg(pi, 0x92);
+ phy_saveregs[2] = read_phy_reg(pi, 0xe7);
+ phy_saveregs[3] = read_phy_reg(pi, 0xec);
+ wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_PA, 1,
+ RADIO_MIMO_CORESEL_CORE1 |
+ RADIO_MIMO_CORESEL_CORE2);
+
+ if (!debug) {
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ 0x2, RADIO_MIMO_CORESEL_CORE1);
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ 0x8, RADIO_MIMO_CORESEL_CORE2);
+ } else {
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ 0x1, RADIO_MIMO_CORESEL_CORE1);
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ 0x7, RADIO_MIMO_CORESEL_CORE2);
+ }
+
+ orig_BBConfig = read_phy_reg(pi, 0x01);
+ mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
+
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1);
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ txpwrindex = (s32) pi->nphy_cal_orig_pwr_idx[core];
+
+ for (gainctrl_loopidx = 0; gainctrl_loopidx < 2;
+ gainctrl_loopidx++) {
+ wlc_phy_tx_tone_nphy(pi, freq_test, ampl_test, 0, 0,
+ false);
+
+ if (core == PHY_CORE_0) {
+ curr_m0m1 = m0m1 & 0xff00;
+ } else {
+ curr_m0m1 = m0m1 & 0x00ff;
+ }
+
+ wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &curr_m0m1);
+ wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &curr_m0m1);
+
+ udelay(50);
+
+ wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
+ NPHY_CAL_TSSISAMPS);
+
+ pi->nphy_bb_mult_save = 0;
+ wlc_phy_stopplayback_nphy(pi);
+
+ delta_power = (dBm_targetpower * 4) - qdBm_power[core];
+
+ txpwrindex -= stepsize * delta_power;
+ if (txpwrindex < 0) {
+ txpwrindex = 0;
+ } else if (txpwrindex > 127) {
+ txpwrindex = 127;
+ }
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if (NREV_IS(pi->pubpi.phy_rev, 4) &&
+ (pi->srom_fem5g.extpagain == 3)) {
+ if (txpwrindex < 30) {
+ txpwrindex = 30;
+ }
+ }
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 5) &&
+ (pi->srom_fem2g.extpagain == 3)) {
+ if (txpwrindex < 50) {
+ txpwrindex = 50;
+ }
+ }
+ }
+
+ wlc_phy_txpwr_index_nphy(pi, (1 << core),
+ (u8) txpwrindex, true);
+ }
+
+ pi->nphy_txcal_pwr_idx[core] = (u8) txpwrindex;
+
+ if (debug) {
+ u16 radio_gain;
+ u16 dbg_m0m1;
+
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
+
+ wlc_phy_tx_tone_nphy(pi, freq_test, ampl_test, 0, 0,
+ false);
+
+ wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
+ wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &dbg_m0m1);
+
+ udelay(100);
+
+ wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
+ NPHY_CAL_TSSISAMPS);
+
+ wlc_phy_table_read_nphy(pi, 7, 1, (0x110 + core), 16,
+ &radio_gain);
+
+ mdelay(4000);
+ pi->nphy_bb_mult_save = 0;
+ wlc_phy_stopplayback_nphy(pi);
+ }
+ }
+
+ wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_txcal_pwr_idx[0], true);
+ wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_txcal_pwr_idx[1], true);
+
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &pi->nphy_txcal_bbmult);
+
+ write_phy_reg(pi, 0x01, orig_BBConfig);
+
+ write_phy_reg(pi, 0x91, phy_saveregs[0]);
+ write_phy_reg(pi, 0x92, phy_saveregs[1]);
+ write_phy_reg(pi, 0xe7, phy_saveregs[2]);
+ write_phy_reg(pi, 0xec, phy_saveregs[3]);
+
+ pi->phyhang_avoid = phyhang_avoid_state;
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core)
+{
+ int index;
+ u32 bbmult_scale;
+ u16 bbmult;
+ u16 tblentry;
+
+ nphy_txiqcal_ladder_t ladder_lo[] = {
+ {3, 0}, {4, 0}, {6, 0}, {9, 0}, {13, 0}, {18, 0},
+ {25, 0}, {25, 1}, {25, 2}, {25, 3}, {25, 4}, {25, 5},
+ {25, 6}, {25, 7}, {35, 7}, {50, 7}, {71, 7}, {100, 7}
+ };
+
+ nphy_txiqcal_ladder_t ladder_iq[] = {
+ {3, 0}, {4, 0}, {6, 0}, {9, 0}, {13, 0}, {18, 0},
+ {25, 0}, {35, 0}, {50, 0}, {71, 0}, {100, 0}, {100, 1},
+ {100, 2}, {100, 3}, {100, 4}, {100, 5}, {100, 6}, {100, 7}
+ };
+
+ bbmult = (core == PHY_CORE_0) ?
+ ((pi->nphy_txcal_bbmult >> 8) & 0xff) : (pi->
+ nphy_txcal_bbmult & 0xff);
+
+ for (index = 0; index < 18; index++) {
+ bbmult_scale = ladder_lo[index].percent * bbmult;
+ bbmult_scale /= 100;
+
+ tblentry =
+ ((bbmult_scale & 0xff) << 8) | ladder_lo[index].g_env;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, index, 16,
+ &tblentry);
+
+ bbmult_scale = ladder_iq[index].percent * bbmult;
+ bbmult_scale /= 100;
+
+ tblentry =
+ ((bbmult_scale & 0xff) << 8) | ladder_iq[index].g_env;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, index + 32,
+ 16, &tblentry);
+ }
+}
+
+void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype)
+{
+ nphy_txgains_t target_gain;
+ u8 tx_pwr_ctrl_state;
+ bool fullcal = true;
+ bool restore_tx_gain = false;
+ bool mphase;
+
+ if (NORADIO_ENAB(pi->pubpi)) {
+ wlc_phy_cal_perical_mphase_reset(pi);
+ return;
+ }
+
+ if (PHY_MUTED(pi))
+ return;
+
+ if (caltype == PHY_PERICAL_AUTO)
+ fullcal = (pi->radio_chanspec != pi->nphy_txiqlocal_chanspec);
+ else if (caltype == PHY_PERICAL_PARTIAL)
+ fullcal = false;
+
+ if (pi->cal_type_override != PHY_PERICAL_AUTO) {
+ fullcal =
+ (pi->cal_type_override == PHY_PERICAL_FULL) ? true : false;
+ }
+
+ if ((pi->mphase_cal_phase_id > MPHASE_CAL_STATE_INIT)) {
+ if (pi->nphy_txiqlocal_chanspec != pi->radio_chanspec)
+ wlc_phy_cal_perical_mphase_restart(pi);
+ }
+
+ if ((pi->mphase_cal_phase_id == MPHASE_CAL_STATE_RXCAL)) {
+ wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
+ }
+
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ wlc_phyreg_enter((wlc_phy_t *) pi);
+
+ if ((pi->mphase_cal_phase_id == MPHASE_CAL_STATE_IDLE) ||
+ (pi->mphase_cal_phase_id == MPHASE_CAL_STATE_INIT)) {
+ pi->nphy_cal_orig_pwr_idx[0] =
+ (u8) ((read_phy_reg(pi, 0x1ed) >> 8) & 0x7f);
+ pi->nphy_cal_orig_pwr_idx[1] =
+ (u8) ((read_phy_reg(pi, 0x1ee) >> 8) & 0x7f);
+
+ if (pi->nphy_txpwrctrl != PHY_TPC_HW_OFF) {
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2,
+ 0x110, 16,
+ pi->nphy_cal_orig_tx_gain);
+ } else {
+ pi->nphy_cal_orig_tx_gain[0] = 0;
+ pi->nphy_cal_orig_tx_gain[1] = 0;
+ }
+ }
+ target_gain = wlc_phy_get_tx_gain_nphy(pi);
+ tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
+ wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
+
+ if (pi->antsel_type == ANTSEL_2x3)
+ wlc_phy_antsel_init((wlc_phy_t *) pi, true);
+
+ mphase = (pi->mphase_cal_phase_id != MPHASE_CAL_STATE_IDLE);
+ if (!mphase) {
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ wlc_phy_precal_txgain_nphy(pi);
+ pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi);
+ restore_tx_gain = true;
+
+ target_gain = pi->nphy_cal_target_gain;
+ }
+ if (0 ==
+ wlc_phy_cal_txiqlo_nphy(pi, target_gain, fullcal, mphase)) {
+ if (PHY_IPA(pi))
+ wlc_phy_a4(pi, true);
+
+ wlc_phyreg_exit((wlc_phy_t *) pi);
+ wlapi_enable_mac(pi->sh->physhim);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION,
+ 10000);
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ wlc_phyreg_enter((wlc_phy_t *) pi);
+
+ if (0 == wlc_phy_cal_rxiq_nphy(pi, target_gain,
+ (pi->
+ first_cal_after_assoc
+ || (pi->
+ cal_type_override
+ ==
+ PHY_PERICAL_FULL))
+ ? 2 : 0, false)) {
+ wlc_phy_savecal_nphy(pi);
+
+ wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
+
+ pi->nphy_perical_last = pi->sh->now;
+ }
+ }
+ if (caltype != PHY_PERICAL_AUTO) {
+ wlc_phy_rssi_cal_nphy(pi);
+ }
+
+ if (pi->first_cal_after_assoc
+ || (pi->cal_type_override == PHY_PERICAL_FULL)) {
+ pi->first_cal_after_assoc = false;
+ wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
+ wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ wlc_phy_radio205x_vcocal_nphy(pi);
+ }
+ } else {
+ switch (pi->mphase_cal_phase_id) {
+ case MPHASE_CAL_STATE_INIT:
+ pi->nphy_perical_last = pi->sh->now;
+ pi->nphy_txiqlocal_chanspec = pi->radio_chanspec;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ wlc_phy_precal_txgain_nphy(pi);
+ }
+ pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi);
+ pi->mphase_cal_phase_id++;
+ break;
+
+ case MPHASE_CAL_STATE_TXPHASE0:
+ case MPHASE_CAL_STATE_TXPHASE1:
+ case MPHASE_CAL_STATE_TXPHASE2:
+ case MPHASE_CAL_STATE_TXPHASE3:
+ case MPHASE_CAL_STATE_TXPHASE4:
+ case MPHASE_CAL_STATE_TXPHASE5:
+ if ((pi->radar_percal_mask & 0x10) != 0)
+ pi->nphy_rxcal_active = true;
+
+ if (wlc_phy_cal_txiqlo_nphy
+ (pi, pi->nphy_cal_target_gain, fullcal,
+ true) != 0) {
+
+ wlc_phy_cal_perical_mphase_reset(pi);
+ break;
+ }
+
+ if (NREV_LE(pi->pubpi.phy_rev, 2) &&
+ (pi->mphase_cal_phase_id ==
+ MPHASE_CAL_STATE_TXPHASE4)) {
+ pi->mphase_cal_phase_id += 2;
+ } else {
+ pi->mphase_cal_phase_id++;
+ }
+ break;
+
+ case MPHASE_CAL_STATE_PAPDCAL:
+ if ((pi->radar_percal_mask & 0x2) != 0)
+ pi->nphy_rxcal_active = true;
+
+ if (PHY_IPA(pi)) {
+ wlc_phy_a4(pi, true);
+ }
+ pi->mphase_cal_phase_id++;
+ break;
+
+ case MPHASE_CAL_STATE_RXCAL:
+ if ((pi->radar_percal_mask & 0x1) != 0)
+ pi->nphy_rxcal_active = true;
+ if (wlc_phy_cal_rxiq_nphy(pi, target_gain,
+ (pi->first_cal_after_assoc ||
+ (pi->cal_type_override ==
+ PHY_PERICAL_FULL)) ? 2 : 0,
+ false) == 0) {
+ wlc_phy_savecal_nphy(pi);
+ }
+
+ pi->mphase_cal_phase_id++;
+ break;
+
+ case MPHASE_CAL_STATE_RSSICAL:
+ if ((pi->radar_percal_mask & 0x4) != 0)
+ pi->nphy_rxcal_active = true;
+ wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
+ wlc_phy_rssi_cal_nphy(pi);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ wlc_phy_radio205x_vcocal_nphy(pi);
+ }
+ restore_tx_gain = true;
+
+ if (pi->first_cal_after_assoc) {
+ pi->mphase_cal_phase_id++;
+ } else {
+ wlc_phy_cal_perical_mphase_reset(pi);
+ }
+
+ break;
+
+ case MPHASE_CAL_STATE_IDLETSSI:
+ if ((pi->radar_percal_mask & 0x8) != 0)
+ pi->nphy_rxcal_active = true;
+
+ if (pi->first_cal_after_assoc) {
+ pi->first_cal_after_assoc = false;
+ wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
+ wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
+ }
+
+ wlc_phy_cal_perical_mphase_reset(pi);
+ break;
+
+ default:
+ wlc_phy_cal_perical_mphase_reset(pi);
+ break;
+ }
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (restore_tx_gain) {
+ if (tx_pwr_ctrl_state != PHY_TPC_HW_OFF) {
+
+ wlc_phy_txpwr_index_nphy(pi, 1,
+ pi->
+ nphy_cal_orig_pwr_idx
+ [0], false);
+ wlc_phy_txpwr_index_nphy(pi, 2,
+ pi->
+ nphy_cal_orig_pwr_idx
+ [1], false);
+
+ pi->nphy_txpwrindex[0].index = -1;
+ pi->nphy_txpwrindex[1].index = -1;
+ } else {
+ wlc_phy_txpwr_index_nphy(pi, (1 << 0),
+ (s8) (pi->
+ nphy_txpwrindex
+ [0].
+ index_internal),
+ false);
+ wlc_phy_txpwr_index_nphy(pi, (1 << 1),
+ (s8) (pi->
+ nphy_txpwrindex
+ [1].
+ index_internal),
+ false);
+ }
+ }
+ }
+
+ wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
+ wlc_phyreg_exit((wlc_phy_t *) pi);
+ wlapi_enable_mac(pi->sh->physhim);
+}
+
+int
+wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
+ bool fullcal, bool mphase)
+{
+ u16 val;
+ u16 tbl_buf[11];
+ u8 cal_cnt;
+ u16 cal_cmd;
+ u8 num_cals, max_cal_cmds;
+ u16 core_no, cal_type;
+ u16 diq_start = 0;
+ u8 phy_bw;
+ u16 max_val;
+ u16 tone_freq;
+ u16 gain_save[2];
+ u16 cal_gain[2];
+ nphy_iqcal_params_t cal_params[2];
+ u32 tbl_len;
+ void *tbl_ptr;
+ bool ladder_updated[2];
+ u8 mphase_cal_lastphase = 0;
+ int bcmerror = 0;
+ bool phyhang_avoid_state = false;
+
+ u16 tbl_tx_iqlo_cal_loft_ladder_20[] = {
+ 0x0300, 0x0500, 0x0700, 0x0900, 0x0d00, 0x1100, 0x1900, 0x1901,
+ 0x1902,
+ 0x1903, 0x1904, 0x1905, 0x1906, 0x1907, 0x2407, 0x3207, 0x4607,
+ 0x6407
+ };
+
+ u16 tbl_tx_iqlo_cal_iqimb_ladder_20[] = {
+ 0x0200, 0x0300, 0x0600, 0x0900, 0x0d00, 0x1100, 0x1900, 0x2400,
+ 0x3200,
+ 0x4600, 0x6400, 0x6401, 0x6402, 0x6403, 0x6404, 0x6405, 0x6406,
+ 0x6407
+ };
+
+ u16 tbl_tx_iqlo_cal_loft_ladder_40[] = {
+ 0x0200, 0x0300, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1201,
+ 0x1202,
+ 0x1203, 0x1204, 0x1205, 0x1206, 0x1207, 0x1907, 0x2307, 0x3207,
+ 0x4707
+ };
+
+ u16 tbl_tx_iqlo_cal_iqimb_ladder_40[] = {
+ 0x0100, 0x0200, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1900,
+ 0x2300,
+ 0x3200, 0x4700, 0x4701, 0x4702, 0x4703, 0x4704, 0x4705, 0x4706,
+ 0x4707
+ };
+
+ u16 tbl_tx_iqlo_cal_startcoefs[] = {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000
+ };
+
+ u16 tbl_tx_iqlo_cal_cmds_fullcal[] = {
+ 0x8123, 0x8264, 0x8086, 0x8245, 0x8056,
+ 0x9123, 0x9264, 0x9086, 0x9245, 0x9056
+ };
+
+ u16 tbl_tx_iqlo_cal_cmds_recal[] = {
+ 0x8101, 0x8253, 0x8053, 0x8234, 0x8034,
+ 0x9101, 0x9253, 0x9053, 0x9234, 0x9034
+ };
+
+ u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[] = {
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000
+ };
+
+ u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = {
+ 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234,
+ 0x9434, 0x9334, 0x9084, 0x9267, 0x9056, 0x9234
+ };
+
+ u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = {
+ 0x8423, 0x8323, 0x8073, 0x8256, 0x8045, 0x8223,
+ 0x9423, 0x9323, 0x9073, 0x9256, 0x9045, 0x9223
+ };
+
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 4)) {
+ phyhang_avoid_state = pi->phyhang_avoid;
+ pi->phyhang_avoid = false;
+ }
+
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ phy_bw = 40;
+ } else {
+ phy_bw = 20;
+ }
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
+
+ for (core_no = 0; core_no <= 1; core_no++) {
+ wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
+ &cal_params[core_no]);
+ cal_gain[core_no] = cal_params[core_no].cal_gain;
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
+
+ wlc_phy_txcal_radio_setup_nphy(pi);
+
+ wlc_phy_txcal_physetup_nphy(pi);
+
+ ladder_updated[0] = ladder_updated[1] = false;
+ if (!(NREV_GE(pi->pubpi.phy_rev, 6) ||
+ (NREV_IS(pi->pubpi.phy_rev, 5) && PHY_IPA(pi)
+ && (CHSPEC_IS2G(pi->radio_chanspec))))) {
+
+ if (phy_bw == 40) {
+ tbl_ptr = tbl_tx_iqlo_cal_loft_ladder_40;
+ tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_loft_ladder_40);
+ } else {
+ tbl_ptr = tbl_tx_iqlo_cal_loft_ladder_20;
+ tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_loft_ladder_20);
+ }
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 0,
+ 16, tbl_ptr);
+
+ if (phy_bw == 40) {
+ tbl_ptr = tbl_tx_iqlo_cal_iqimb_ladder_40;
+ tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_iqimb_ladder_40);
+ } else {
+ tbl_ptr = tbl_tx_iqlo_cal_iqimb_ladder_20;
+ tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_iqimb_ladder_20);
+ }
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 32,
+ 16, tbl_ptr);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ write_phy_reg(pi, 0xc2, 0x8ad9);
+ } else {
+ write_phy_reg(pi, 0xc2, 0x8aa9);
+ }
+
+ max_val = 250;
+ tone_freq = (phy_bw == 20) ? 2500 : 5000;
+
+ if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
+ wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff, 0, 1, 0, false);
+ bcmerror = 0;
+ } else {
+ bcmerror =
+ wlc_phy_tx_tone_nphy(pi, tone_freq, max_val, 1, 0, false);
+ }
+
+ if (bcmerror == 0) {
+
+ if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
+ tbl_ptr = pi->mphase_txcal_bestcoeffs;
+ tbl_len = ARRAY_SIZE(pi->mphase_txcal_bestcoeffs);
+ if (NREV_LT(pi->pubpi.phy_rev, 3)) {
+
+ tbl_len -= 2;
+ }
+ } else {
+ if ((!fullcal) && (pi->nphy_txiqlocal_coeffsvalid)) {
+
+ tbl_ptr = pi->nphy_txiqlocal_bestc;
+ tbl_len = ARRAY_SIZE(pi->nphy_txiqlocal_bestc);
+ if (NREV_LT(pi->pubpi.phy_rev, 3)) {
+
+ tbl_len -= 2;
+ }
+ } else {
+
+ fullcal = true;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ tbl_ptr =
+ tbl_tx_iqlo_cal_startcoefs_nphyrev3;
+ tbl_len =
+ ARRAY_SIZE
+ (tbl_tx_iqlo_cal_startcoefs_nphyrev3);
+ } else {
+ tbl_ptr = tbl_tx_iqlo_cal_startcoefs;
+ tbl_len =
+ ARRAY_SIZE
+ (tbl_tx_iqlo_cal_startcoefs);
+ }
+ }
+ }
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 64,
+ 16, tbl_ptr);
+
+ if (fullcal) {
+ max_cal_cmds = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
+ ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3) :
+ ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_fullcal);
+ } else {
+ max_cal_cmds = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
+ ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_recal_nphyrev3) :
+ ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_recal);
+ }
+
+ if (mphase) {
+ cal_cnt = pi->mphase_txcal_cmdidx;
+ if ((cal_cnt + pi->mphase_txcal_numcmds) < max_cal_cmds) {
+ num_cals = cal_cnt + pi->mphase_txcal_numcmds;
+ } else {
+ num_cals = max_cal_cmds;
+ }
+ } else {
+ cal_cnt = 0;
+ num_cals = max_cal_cmds;
+ }
+
+ for (; cal_cnt < num_cals; cal_cnt++) {
+
+ if (fullcal) {
+ cal_cmd = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
+ tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3
+ [cal_cnt] :
+ tbl_tx_iqlo_cal_cmds_fullcal[cal_cnt];
+ } else {
+ cal_cmd = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
+ tbl_tx_iqlo_cal_cmds_recal_nphyrev3[cal_cnt]
+ : tbl_tx_iqlo_cal_cmds_recal[cal_cnt];
+ }
+
+ core_no = ((cal_cmd & 0x3000) >> 12);
+ cal_type = ((cal_cmd & 0x0F00) >> 8);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 6) ||
+ (NREV_IS(pi->pubpi.phy_rev, 5) &&
+ PHY_IPA(pi)
+ && (CHSPEC_IS2G(pi->radio_chanspec)))) {
+ if (!ladder_updated[core_no]) {
+ wlc_phy_update_txcal_ladder_nphy(pi,
+ core_no);
+ ladder_updated[core_no] = true;
+ }
+ }
+
+ val =
+ (cal_params[core_no].
+ ncorr[cal_type] << 8) | NPHY_N_GCTL;
+ write_phy_reg(pi, 0xc1, val);
+
+ if ((cal_type == 1) || (cal_type == 3)
+ || (cal_type == 4)) {
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
+ 1, 69 + core_no, 16,
+ tbl_buf);
+
+ diq_start = tbl_buf[0];
+
+ tbl_buf[0] = 0;
+ wlc_phy_table_write_nphy(pi,
+ NPHY_TBL_ID_IQLOCAL, 1,
+ 69 + core_no, 16,
+ tbl_buf);
+ }
+
+ write_phy_reg(pi, 0xc0, cal_cmd);
+
+ SPINWAIT(((read_phy_reg(pi, 0xc0) & 0xc000) != 0),
+ 20000);
+ if (WARN(read_phy_reg(pi, 0xc0) & 0xc000,
+ "HW error: txiq calib"))
+ return -EIO;
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
+ tbl_len, 96, 16, tbl_buf);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL,
+ tbl_len, 64, 16, tbl_buf);
+
+ if ((cal_type == 1) || (cal_type == 3)
+ || (cal_type == 4)) {
+
+ tbl_buf[0] = diq_start;
+
+ }
+
+ }
+
+ if (mphase) {
+ pi->mphase_txcal_cmdidx = num_cals;
+ if (pi->mphase_txcal_cmdidx >= max_cal_cmds)
+ pi->mphase_txcal_cmdidx = 0;
+ }
+
+ mphase_cal_lastphase =
+ (NREV_LE(pi->pubpi.phy_rev, 2)) ?
+ MPHASE_CAL_STATE_TXPHASE4 : MPHASE_CAL_STATE_TXPHASE5;
+
+ if (!mphase
+ || (pi->mphase_cal_phase_id == mphase_cal_lastphase)) {
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 96,
+ 16, tbl_buf);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80,
+ 16, tbl_buf);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+
+ tbl_buf[0] = 0;
+ tbl_buf[1] = 0;
+ tbl_buf[2] = 0;
+ tbl_buf[3] = 0;
+
+ }
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88,
+ 16, tbl_buf);
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 101,
+ 16, tbl_buf);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85,
+ 16, tbl_buf);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93,
+ 16, tbl_buf);
+
+ tbl_len = ARRAY_SIZE(pi->nphy_txiqlocal_bestc);
+ if (NREV_LT(pi->pubpi.phy_rev, 3)) {
+
+ tbl_len -= 2;
+ }
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
+ tbl_len, 96, 16,
+ pi->nphy_txiqlocal_bestc);
+
+ pi->nphy_txiqlocal_coeffsvalid = true;
+ pi->nphy_txiqlocal_chanspec = pi->radio_chanspec;
+ } else {
+ tbl_len = ARRAY_SIZE(pi->mphase_txcal_bestcoeffs);
+ if (NREV_LT(pi->pubpi.phy_rev, 3)) {
+
+ tbl_len -= 2;
+ }
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
+ tbl_len, 96, 16,
+ pi->mphase_txcal_bestcoeffs);
+ }
+
+ wlc_phy_stopplayback_nphy(pi);
+
+ write_phy_reg(pi, 0xc2, 0x0000);
+
+ }
+
+ wlc_phy_txcal_phycleanup_nphy(pi);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
+ gain_save);
+
+ wlc_phy_txcal_radio_cleanup_nphy(pi);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+ if (!mphase
+ || (pi->mphase_cal_phase_id == mphase_cal_lastphase))
+ wlc_phy_tx_iq_war_nphy(pi);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 4)) {
+ pi->phyhang_avoid = phyhang_avoid_state;
+ }
+
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+
+ return bcmerror;
+}
+
+static void wlc_phy_reapply_txcal_coeffs_nphy(phy_info_t *pi)
+{
+ u16 tbl_buf[7];
+
+ if ((pi->nphy_txiqlocal_chanspec == pi->radio_chanspec) &&
+ (pi->nphy_txiqlocal_coeffsvalid)) {
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
+ ARRAY_SIZE(tbl_buf), 80, 16, tbl_buf);
+
+ if ((pi->nphy_txiqlocal_bestc[0] != tbl_buf[0]) ||
+ (pi->nphy_txiqlocal_bestc[1] != tbl_buf[1]) ||
+ (pi->nphy_txiqlocal_bestc[2] != tbl_buf[2]) ||
+ (pi->nphy_txiqlocal_bestc[3] != tbl_buf[3])) {
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80,
+ 16, pi->nphy_txiqlocal_bestc);
+
+ tbl_buf[0] = 0;
+ tbl_buf[1] = 0;
+ tbl_buf[2] = 0;
+ tbl_buf[3] = 0;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88,
+ 16, tbl_buf);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85,
+ 16,
+ &pi->nphy_txiqlocal_bestc[5]);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93,
+ 16,
+ &pi->nphy_txiqlocal_bestc[5]);
+ }
+ }
+}
+
+static void wlc_phy_tx_iq_war_nphy(phy_info_t *pi)
+{
+ nphy_iq_comp_t tx_comp;
+
+ wlc_phy_table_read_nphy(pi, 15, 4, 0x50, 16, (void *)&tx_comp);
+
+ wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ, tx_comp.a0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 2, tx_comp.b0);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 4, tx_comp.a1);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 6, tx_comp.b1);
+}
+
+void
+wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write, nphy_iq_comp_t *pcomp)
+{
+ if (write) {
+ write_phy_reg(pi, 0x9a, pcomp->a0);
+ write_phy_reg(pi, 0x9b, pcomp->b0);
+ write_phy_reg(pi, 0x9c, pcomp->a1);
+ write_phy_reg(pi, 0x9d, pcomp->b1);
+ } else {
+ pcomp->a0 = read_phy_reg(pi, 0x9a);
+ pcomp->b0 = read_phy_reg(pi, 0x9b);
+ pcomp->a1 = read_phy_reg(pi, 0x9c);
+ pcomp->b1 = read_phy_reg(pi, 0x9d);
+ }
+}
+
+void
+wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est, u16 num_samps,
+ u8 wait_time, u8 wait_for_crs)
+{
+ u8 core;
+
+ write_phy_reg(pi, 0x12b, num_samps);
+ mod_phy_reg(pi, 0x12a, (0xff << 0), (wait_time << 0));
+ mod_phy_reg(pi, 0x129, NPHY_IqestCmd_iqMode,
+ (wait_for_crs) ? NPHY_IqestCmd_iqMode : 0);
+
+ mod_phy_reg(pi, 0x129, NPHY_IqestCmd_iqstart, NPHY_IqestCmd_iqstart);
+
+ SPINWAIT(((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) != 0),
+ 10000);
+ if (WARN(read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart,
+ "HW error: rxiq est"))
+ return;
+
+ if ((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) == 0) {
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ est[core].i_pwr =
+ (read_phy_reg(pi, NPHY_IqestipwrAccHi(core)) << 16)
+ | read_phy_reg(pi, NPHY_IqestipwrAccLo(core));
+ est[core].q_pwr =
+ (read_phy_reg(pi, NPHY_IqestqpwrAccHi(core)) << 16)
+ | read_phy_reg(pi, NPHY_IqestqpwrAccLo(core));
+ est[core].iq_prod =
+ (read_phy_reg(pi, NPHY_IqestIqAccHi(core)) << 16) |
+ read_phy_reg(pi, NPHY_IqestIqAccLo(core));
+ }
+ }
+}
+
+#define CAL_RETRY_CNT 2
+static void wlc_phy_calc_rx_iq_comp_nphy(phy_info_t *pi, u8 core_mask)
+{
+ u8 curr_core;
+ phy_iq_est_t est[PHY_CORE_MAX];
+ nphy_iq_comp_t old_comp, new_comp;
+ s32 iq = 0;
+ u32 ii = 0, qq = 0;
+ s16 iq_nbits, qq_nbits, brsh, arsh;
+ s32 a, b, temp;
+ int bcmerror = 0;
+ uint cal_retry = 0;
+
+ if (core_mask == 0x0)
+ return;
+
+ wlc_phy_rx_iq_coeffs_nphy(pi, 0, &old_comp);
+ new_comp.a0 = new_comp.b0 = new_comp.a1 = new_comp.b1 = 0x0;
+ wlc_phy_rx_iq_coeffs_nphy(pi, 1, &new_comp);
+
+ cal_try:
+ wlc_phy_rx_iq_est_nphy(pi, est, 0x4000, 32, 0);
+
+ new_comp = old_comp;
+
+ for (curr_core = 0; curr_core < pi->pubpi.phy_corenum; curr_core++) {
+
+ if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
+ iq = est[curr_core].iq_prod;
+ ii = est[curr_core].i_pwr;
+ qq = est[curr_core].q_pwr;
+ } else if ((curr_core == PHY_CORE_1) && (core_mask & 0x2)) {
+ iq = est[curr_core].iq_prod;
+ ii = est[curr_core].i_pwr;
+ qq = est[curr_core].q_pwr;
+ } else {
+ continue;
+ }
+
+ if ((ii + qq) < NPHY_MIN_RXIQ_PWR) {
+ bcmerror = -EBADE;
+ break;
+ }
+
+ iq_nbits = wlc_phy_nbits(iq);
+ qq_nbits = wlc_phy_nbits(qq);
+
+ arsh = 10 - (30 - iq_nbits);
+ if (arsh >= 0) {
+ a = (-(iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
+ temp = (s32) (ii >> arsh);
+ if (temp == 0) {
+ bcmerror = -EBADE;
+ break;
+ }
+ } else {
+ a = (-(iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
+ temp = (s32) (ii << -arsh);
+ if (temp == 0) {
+ bcmerror = -EBADE;
+ break;
+ }
+ }
+
+ a /= temp;
+
+ brsh = qq_nbits - 31 + 20;
+ if (brsh >= 0) {
+ b = (qq << (31 - qq_nbits));
+ temp = (s32) (ii >> brsh);
+ if (temp == 0) {
+ bcmerror = -EBADE;
+ break;
+ }
+ } else {
+ b = (qq << (31 - qq_nbits));
+ temp = (s32) (ii << -brsh);
+ if (temp == 0) {
+ bcmerror = -EBADE;
+ break;
+ }
+ }
+ b /= temp;
+ b -= a * a;
+ b = (s32) int_sqrt((unsigned long) b);
+ b -= (1 << 10);
+
+ if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ new_comp.a0 = (s16) a & 0x3ff;
+ new_comp.b0 = (s16) b & 0x3ff;
+ } else {
+
+ new_comp.a0 = (s16) b & 0x3ff;
+ new_comp.b0 = (s16) a & 0x3ff;
+ }
+ }
+ if ((curr_core == PHY_CORE_1) && (core_mask & 0x2)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ new_comp.a1 = (s16) a & 0x3ff;
+ new_comp.b1 = (s16) b & 0x3ff;
+ } else {
+
+ new_comp.a1 = (s16) b & 0x3ff;
+ new_comp.b1 = (s16) a & 0x3ff;
+ }
+ }
+ }
+
+ if (bcmerror != 0) {
+ printk("%s: Failed, cnt = %d\n", __func__, cal_retry);
+
+ if (cal_retry < CAL_RETRY_CNT) {
+ cal_retry++;
+ goto cal_try;
+ }
+
+ new_comp = old_comp;
+ } else if (cal_retry > 0) {
+ }
+
+ wlc_phy_rx_iq_coeffs_nphy(pi, 1, &new_comp);
+}
+
+static void wlc_phy_rxcal_radio_setup_nphy(phy_info_t *pi, u8 rx_core)
+{
+ u16 offtune_val;
+ u16 bias_g = 0;
+ u16 bias_a = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (rx_core == PHY_CORE_0) {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ pi->tx_rx_cal_radio_saveregs[0] =
+ read_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP);
+ pi->tx_rx_cal_radio_saveregs[1] =
+ read_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN);
+
+ write_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP,
+ 0x3);
+ write_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN,
+ 0xaf);
+
+ } else {
+ pi->tx_rx_cal_radio_saveregs[0] =
+ read_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP);
+ pi->tx_rx_cal_radio_saveregs[1] =
+ read_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN);
+
+ write_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP,
+ 0x3);
+ write_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN,
+ 0x7f);
+ }
+
+ } else {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ pi->tx_rx_cal_radio_saveregs[0] =
+ read_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP);
+ pi->tx_rx_cal_radio_saveregs[1] =
+ read_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN);
+
+ write_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP,
+ 0x3);
+ write_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN,
+ 0xaf);
+
+ } else {
+ pi->tx_rx_cal_radio_saveregs[0] =
+ read_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP);
+ pi->tx_rx_cal_radio_saveregs[1] =
+ read_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN);
+
+ write_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP,
+ 0x3);
+ write_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN,
+ 0x7f);
+ }
+ }
+
+ } else {
+ if (rx_core == PHY_CORE_0) {
+ pi->tx_rx_cal_radio_saveregs[0] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_RXIQCAL_TXMUX |
+ RADIO_2056_TX1);
+ pi->tx_rx_cal_radio_saveregs[1] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_RXIQCAL_RXMUX |
+ RADIO_2056_RX0);
+
+ if (pi->pubpi.radiorev >= 5) {
+ pi->tx_rx_cal_radio_saveregs[2] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_RXSPARE2 |
+ RADIO_2056_RX0);
+ pi->tx_rx_cal_radio_saveregs[3] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TXSPARE2 |
+ RADIO_2056_TX1);
+ }
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+
+ if (pi->pubpi.radiorev >= 5) {
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_LNAA_MASTER
+ | RADIO_2056_RX0);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAA_MASTER
+ | RADIO_2056_RX0, 0x40);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TXSPARE2 |
+ RADIO_2056_TX1, bias_a);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXSPARE2 |
+ RADIO_2056_RX0, bias_a);
+ } else {
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_LNAA_TUNE
+ | RADIO_2056_RX0);
+
+ offtune_val =
+ (pi->
+ tx_rx_cal_radio_saveregs[2] & 0xF0)
+ >> 8;
+ offtune_val =
+ (offtune_val <= 0x7) ? 0xF : 0;
+
+ mod_radio_reg(pi,
+ RADIO_2056_RX_LNAA_TUNE |
+ RADIO_2056_RX0, 0xF0,
+ (offtune_val << 8));
+ }
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_RXIQCAL_TXMUX |
+ RADIO_2056_TX1, 0x9);
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXIQCAL_RXMUX |
+ RADIO_2056_RX0, 0x9);
+ } else {
+ if (pi->pubpi.radiorev >= 5) {
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_LNAG_MASTER
+ | RADIO_2056_RX0);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAG_MASTER
+ | RADIO_2056_RX0, 0x40);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TXSPARE2 |
+ RADIO_2056_TX1, bias_g);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXSPARE2 |
+ RADIO_2056_RX0, bias_g);
+
+ } else {
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_LNAG_TUNE
+ | RADIO_2056_RX0);
+
+ offtune_val =
+ (pi->
+ tx_rx_cal_radio_saveregs[2] & 0xF0)
+ >> 8;
+ offtune_val =
+ (offtune_val <= 0x7) ? 0xF : 0;
+
+ mod_radio_reg(pi,
+ RADIO_2056_RX_LNAG_TUNE |
+ RADIO_2056_RX0, 0xF0,
+ (offtune_val << 8));
+ }
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_RXIQCAL_TXMUX |
+ RADIO_2056_TX1, 0x6);
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXIQCAL_RXMUX |
+ RADIO_2056_RX0, 0x6);
+ }
+
+ } else {
+ pi->tx_rx_cal_radio_saveregs[0] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_RXIQCAL_TXMUX |
+ RADIO_2056_TX0);
+ pi->tx_rx_cal_radio_saveregs[1] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_RXIQCAL_RXMUX |
+ RADIO_2056_RX1);
+
+ if (pi->pubpi.radiorev >= 5) {
+ pi->tx_rx_cal_radio_saveregs[2] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_RXSPARE2 |
+ RADIO_2056_RX1);
+ pi->tx_rx_cal_radio_saveregs[3] =
+ read_radio_reg(pi,
+ RADIO_2056_TX_TXSPARE2 |
+ RADIO_2056_TX0);
+ }
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+
+ if (pi->pubpi.radiorev >= 5) {
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_LNAA_MASTER
+ | RADIO_2056_RX1);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAA_MASTER
+ | RADIO_2056_RX1, 0x40);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TXSPARE2 |
+ RADIO_2056_TX0, bias_a);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXSPARE2 |
+ RADIO_2056_RX1, bias_a);
+ } else {
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_LNAA_TUNE
+ | RADIO_2056_RX1);
+
+ offtune_val =
+ (pi->
+ tx_rx_cal_radio_saveregs[2] & 0xF0)
+ >> 8;
+ offtune_val =
+ (offtune_val <= 0x7) ? 0xF : 0;
+
+ mod_radio_reg(pi,
+ RADIO_2056_RX_LNAA_TUNE |
+ RADIO_2056_RX1, 0xF0,
+ (offtune_val << 8));
+ }
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_RXIQCAL_TXMUX |
+ RADIO_2056_TX0, 0x9);
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXIQCAL_RXMUX |
+ RADIO_2056_RX1, 0x9);
+ } else {
+ if (pi->pubpi.radiorev >= 5) {
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_LNAG_MASTER
+ | RADIO_2056_RX1);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAG_MASTER
+ | RADIO_2056_RX1, 0x40);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TXSPARE2 |
+ RADIO_2056_TX0, bias_g);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXSPARE2 |
+ RADIO_2056_RX1, bias_g);
+ } else {
+ pi->tx_rx_cal_radio_saveregs[4] =
+ read_radio_reg(pi,
+ RADIO_2056_RX_LNAG_TUNE
+ | RADIO_2056_RX1);
+
+ offtune_val =
+ (pi->
+ tx_rx_cal_radio_saveregs[2] & 0xF0)
+ >> 8;
+ offtune_val =
+ (offtune_val <= 0x7) ? 0xF : 0;
+
+ mod_radio_reg(pi,
+ RADIO_2056_RX_LNAG_TUNE |
+ RADIO_2056_RX1, 0xF0,
+ (offtune_val << 8));
+ }
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_RXIQCAL_TXMUX |
+ RADIO_2056_TX0, 0x6);
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXIQCAL_RXMUX |
+ RADIO_2056_RX1, 0x6);
+ }
+ }
+ }
+}
+
+static void wlc_phy_rxcal_radio_cleanup_nphy(phy_info_t *pi, u8 rx_core)
+{
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (rx_core == PHY_CORE_0) {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ write_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP,
+ pi->
+ tx_rx_cal_radio_saveregs[0]);
+ write_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN,
+ pi->
+ tx_rx_cal_radio_saveregs[1]);
+
+ } else {
+ write_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP,
+ pi->
+ tx_rx_cal_radio_saveregs[0]);
+ write_radio_reg(pi,
+ RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN,
+ pi->
+ tx_rx_cal_radio_saveregs[1]);
+ }
+
+ } else {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ write_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP,
+ pi->
+ tx_rx_cal_radio_saveregs[0]);
+ write_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN,
+ pi->
+ tx_rx_cal_radio_saveregs[1]);
+
+ } else {
+ write_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP,
+ pi->
+ tx_rx_cal_radio_saveregs[0]);
+ write_radio_reg(pi,
+ RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN,
+ pi->
+ tx_rx_cal_radio_saveregs[1]);
+ }
+ }
+
+ } else {
+ if (rx_core == PHY_CORE_0) {
+ write_radio_reg(pi,
+ RADIO_2056_TX_RXIQCAL_TXMUX |
+ RADIO_2056_TX1,
+ pi->tx_rx_cal_radio_saveregs[0]);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXIQCAL_RXMUX |
+ RADIO_2056_RX0,
+ pi->tx_rx_cal_radio_saveregs[1]);
+
+ if (pi->pubpi.radiorev >= 5) {
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXSPARE2 |
+ RADIO_2056_RX0,
+ pi->
+ tx_rx_cal_radio_saveregs[2]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TXSPARE2 |
+ RADIO_2056_TX1,
+ pi->
+ tx_rx_cal_radio_saveregs[3]);
+ }
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if (pi->pubpi.radiorev >= 5) {
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAA_MASTER
+ | RADIO_2056_RX0,
+ pi->
+ tx_rx_cal_radio_saveregs
+ [4]);
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAA_TUNE
+ | RADIO_2056_RX0,
+ pi->
+ tx_rx_cal_radio_saveregs
+ [4]);
+ }
+ } else {
+ if (pi->pubpi.radiorev >= 5) {
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAG_MASTER
+ | RADIO_2056_RX0,
+ pi->
+ tx_rx_cal_radio_saveregs
+ [4]);
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAG_TUNE
+ | RADIO_2056_RX0,
+ pi->
+ tx_rx_cal_radio_saveregs
+ [4]);
+ }
+ }
+
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_TX_RXIQCAL_TXMUX |
+ RADIO_2056_TX0,
+ pi->tx_rx_cal_radio_saveregs[0]);
+
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXIQCAL_RXMUX |
+ RADIO_2056_RX1,
+ pi->tx_rx_cal_radio_saveregs[1]);
+
+ if (pi->pubpi.radiorev >= 5) {
+ write_radio_reg(pi,
+ RADIO_2056_RX_RXSPARE2 |
+ RADIO_2056_RX1,
+ pi->
+ tx_rx_cal_radio_saveregs[2]);
+
+ write_radio_reg(pi,
+ RADIO_2056_TX_TXSPARE2 |
+ RADIO_2056_TX0,
+ pi->
+ tx_rx_cal_radio_saveregs[3]);
+ }
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if (pi->pubpi.radiorev >= 5) {
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAA_MASTER
+ | RADIO_2056_RX1,
+ pi->
+ tx_rx_cal_radio_saveregs
+ [4]);
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAA_TUNE
+ | RADIO_2056_RX1,
+ pi->
+ tx_rx_cal_radio_saveregs
+ [4]);
+ }
+ } else {
+ if (pi->pubpi.radiorev >= 5) {
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAG_MASTER
+ | RADIO_2056_RX1,
+ pi->
+ tx_rx_cal_radio_saveregs
+ [4]);
+ } else {
+ write_radio_reg(pi,
+ RADIO_2056_RX_LNAG_TUNE
+ | RADIO_2056_RX1,
+ pi->
+ tx_rx_cal_radio_saveregs
+ [4]);
+ }
+ }
+ }
+ }
+}
+
+static void wlc_phy_rxcal_physetup_nphy(phy_info_t *pi, u8 rx_core)
+{
+ u8 tx_core;
+ u16 rx_antval, tx_antval;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ tx_core = rx_core;
+ } else {
+ tx_core = (rx_core == PHY_CORE_0) ? 1 : 0;
+ }
+
+ pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa2);
+ pi->tx_rx_cal_phy_saveregs[1] =
+ read_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 : 0xa7);
+ pi->tx_rx_cal_phy_saveregs[2] =
+ read_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5);
+ pi->tx_rx_cal_phy_saveregs[3] = read_phy_reg(pi, 0x91);
+ pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 0x92);
+ pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 0x7a);
+ pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 0x7d);
+ pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 0xe7);
+ pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 0xec);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ pi->tx_rx_cal_phy_saveregs[11] = read_phy_reg(pi, 0x342);
+ pi->tx_rx_cal_phy_saveregs[12] = read_phy_reg(pi, 0x343);
+ pi->tx_rx_cal_phy_saveregs[13] = read_phy_reg(pi, 0x346);
+ pi->tx_rx_cal_phy_saveregs[14] = read_phy_reg(pi, 0x347);
+ }
+
+ pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 0x297);
+ pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 0x29b);
+ mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (0) << 0);
+
+ mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (0) << 0);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
+
+ mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << (1 - rx_core)) << 12);
+
+ } else {
+
+ mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << tx_core) << 12);
+ mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
+ mod_phy_reg(pi, 0xa2, (0xf << 4), (1 << rx_core) << 4);
+ mod_phy_reg(pi, 0xa2, (0xf << 8), (1 << rx_core) << 8);
+ }
+
+ mod_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7), (0x1 << 2), 0);
+ mod_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5,
+ (0x1 << 2), (0x1 << 2));
+ if (NREV_LT(pi->pubpi.phy_rev, 7)) {
+ mod_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7),
+ (0x1 << 0) | (0x1 << 1), 0);
+ mod_phy_reg(pi, (rx_core == PHY_CORE_0) ?
+ 0x8f : 0xa5,
+ (0x1 << 0) | (0x1 << 1), (0x1 << 0) | (0x1 << 1));
+ }
+
+ wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_PA, 0,
+ RADIO_MIMO_CORESEL_CORE1 |
+ RADIO_MIMO_CORESEL_CORE2);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
+ 0, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 0, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 1, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 1, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi,
+ (0x1 << 7),
+ 2, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ } else {
+ wlc_phy_rfctrl_override_nphy_rev7(pi,
+ (0x1 << 7),
+ 0, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ }
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
+ 0, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 0, 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 3, 0);
+ }
+
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ 0x1, rx_core + 1);
+ } else {
+
+ if (rx_core == PHY_CORE_0) {
+ rx_antval = 0x1;
+ tx_antval = 0x8;
+ } else {
+ rx_antval = 0x4;
+ tx_antval = 0x2;
+ }
+
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ rx_antval, rx_core + 1);
+ wlc_phy_rfctrlintc_override_nphy(pi,
+ NPHY_RfctrlIntc_override_TRSW,
+ tx_antval, tx_core + 1);
+ }
+}
+
+static void wlc_phy_rxcal_phycleanup_nphy(phy_info_t *pi, u8 rx_core)
+{
+
+ write_phy_reg(pi, 0xa2, pi->tx_rx_cal_phy_saveregs[0]);
+ write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 : 0xa7,
+ pi->tx_rx_cal_phy_saveregs[1]);
+ write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5,
+ pi->tx_rx_cal_phy_saveregs[2]);
+ write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[3]);
+ write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[4]);
+
+ write_phy_reg(pi, 0x7a, pi->tx_rx_cal_phy_saveregs[5]);
+ write_phy_reg(pi, 0x7d, pi->tx_rx_cal_phy_saveregs[6]);
+ write_phy_reg(pi, 0xe7, pi->tx_rx_cal_phy_saveregs[7]);
+ write_phy_reg(pi, 0xec, pi->tx_rx_cal_phy_saveregs[8]);
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ write_phy_reg(pi, 0x342, pi->tx_rx_cal_phy_saveregs[11]);
+ write_phy_reg(pi, 0x343, pi->tx_rx_cal_phy_saveregs[12]);
+ write_phy_reg(pi, 0x346, pi->tx_rx_cal_phy_saveregs[13]);
+ write_phy_reg(pi, 0x347, pi->tx_rx_cal_phy_saveregs[14]);
+ }
+
+ write_phy_reg(pi, 0x297, pi->tx_rx_cal_phy_saveregs[9]);
+ write_phy_reg(pi, 0x29b, pi->tx_rx_cal_phy_saveregs[10]);
+}
+
+static void
+wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core,
+ u16 *rxgain, u8 cal_type)
+{
+
+ u16 num_samps;
+ phy_iq_est_t est[PHY_CORE_MAX];
+ u8 tx_core;
+ nphy_iq_comp_t save_comp, zero_comp;
+ u32 i_pwr, q_pwr, curr_pwr, optim_pwr = 0, prev_pwr = 0, thresh_pwr =
+ 10000;
+ s16 desired_log2_pwr, actual_log2_pwr, delta_pwr;
+ bool gainctrl_done = false;
+ u8 mix_tia_gain = 3;
+ s8 optim_gaintbl_index = 0, prev_gaintbl_index = 0;
+ s8 curr_gaintbl_index = 3;
+ u8 gainctrl_dirn = NPHY_RXCAL_GAIN_INIT;
+ nphy_ipa_txrxgain_t *nphy_rxcal_gaintbl;
+ u16 hpvga, lpf_biq1, lpf_biq0, lna2, lna1;
+ int fine_gain_idx;
+ s8 txpwrindex;
+ u16 nphy_rxcal_txgain[2];
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ tx_core = rx_core;
+ } else {
+ tx_core = 1 - rx_core;
+ }
+
+ num_samps = 1024;
+ desired_log2_pwr = (cal_type == 0) ? 13 : 13;
+
+ wlc_phy_rx_iq_coeffs_nphy(pi, 0, &save_comp);
+ zero_comp.a0 = zero_comp.b0 = zero_comp.a1 = zero_comp.b1 = 0x0;
+ wlc_phy_rx_iq_coeffs_nphy(pi, 1, &zero_comp);
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ mix_tia_gain = 3;
+ } else if (NREV_GE(pi->pubpi.phy_rev, 4)) {
+ mix_tia_gain = 4;
+ } else {
+ mix_tia_gain = 6;
+ }
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_5GHz_rev7;
+ } else {
+ nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_5GHz;
+ }
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_2GHz_rev7;
+ } else {
+ nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_2GHz;
+ }
+ }
+
+ do {
+
+ hpvga = (NREV_GE(pi->pubpi.phy_rev, 7)) ?
+ 0 : nphy_rxcal_gaintbl[curr_gaintbl_index].hpvga;
+ lpf_biq1 = nphy_rxcal_gaintbl[curr_gaintbl_index].lpf_biq1;
+ lpf_biq0 = nphy_rxcal_gaintbl[curr_gaintbl_index].lpf_biq0;
+ lna2 = nphy_rxcal_gaintbl[curr_gaintbl_index].lna2;
+ lna1 = nphy_rxcal_gaintbl[curr_gaintbl_index].lna1;
+ txpwrindex = nphy_rxcal_gaintbl[curr_gaintbl_index].txpwrindex;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_rxgain,
+ ((lpf_biq1 << 12) |
+ (lpf_biq0 << 8) |
+ (mix_tia_gain <<
+ 4) | (lna2 << 2)
+ | lna1), 0x3, 0);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12),
+ ((hpvga << 12) |
+ (lpf_biq1 << 10) |
+ (lpf_biq0 << 8) |
+ (mix_tia_gain << 4) |
+ (lna2 << 2) | lna1), 0x3,
+ 0);
+ }
+
+ pi->nphy_rxcal_pwr_idx[tx_core] = txpwrindex;
+
+ if (txpwrindex == -1) {
+ nphy_rxcal_txgain[0] = 0x8ff0 | pi->nphy_gmval;
+ nphy_rxcal_txgain[1] = 0x8ff0 | pi->nphy_gmval;
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
+ 2, 0x110, 16,
+ nphy_rxcal_txgain);
+ } else {
+ wlc_phy_txpwr_index_nphy(pi, tx_core + 1, txpwrindex,
+ false);
+ }
+
+ wlc_phy_tx_tone_nphy(pi, (CHSPEC_IS40(pi->radio_chanspec)) ?
+ NPHY_RXCAL_TONEFREQ_40MHz :
+ NPHY_RXCAL_TONEFREQ_20MHz,
+ NPHY_RXCAL_TONEAMP, 0, cal_type, false);
+
+ wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
+ i_pwr = (est[rx_core].i_pwr + num_samps / 2) / num_samps;
+ q_pwr = (est[rx_core].q_pwr + num_samps / 2) / num_samps;
+ curr_pwr = i_pwr + q_pwr;
+
+ switch (gainctrl_dirn) {
+ case NPHY_RXCAL_GAIN_INIT:
+ if (curr_pwr > thresh_pwr) {
+ gainctrl_dirn = NPHY_RXCAL_GAIN_DOWN;
+ prev_gaintbl_index = curr_gaintbl_index;
+ curr_gaintbl_index--;
+ } else {
+ gainctrl_dirn = NPHY_RXCAL_GAIN_UP;
+ prev_gaintbl_index = curr_gaintbl_index;
+ curr_gaintbl_index++;
+ }
+ break;
+
+ case NPHY_RXCAL_GAIN_UP:
+ if (curr_pwr > thresh_pwr) {
+ gainctrl_done = true;
+ optim_pwr = prev_pwr;
+ optim_gaintbl_index = prev_gaintbl_index;
+ } else {
+ prev_gaintbl_index = curr_gaintbl_index;
+ curr_gaintbl_index++;
+ }
+ break;
+
+ case NPHY_RXCAL_GAIN_DOWN:
+ if (curr_pwr > thresh_pwr) {
+ prev_gaintbl_index = curr_gaintbl_index;
+ curr_gaintbl_index--;
+ } else {
+ gainctrl_done = true;
+ optim_pwr = curr_pwr;
+ optim_gaintbl_index = curr_gaintbl_index;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ if ((curr_gaintbl_index < 0) ||
+ (curr_gaintbl_index > NPHY_IPA_RXCAL_MAXGAININDEX)) {
+ gainctrl_done = true;
+ optim_pwr = curr_pwr;
+ optim_gaintbl_index = prev_gaintbl_index;
+ } else {
+ prev_pwr = curr_pwr;
+ }
+
+ wlc_phy_stopplayback_nphy(pi);
+ } while (!gainctrl_done);
+
+ hpvga = nphy_rxcal_gaintbl[optim_gaintbl_index].hpvga;
+ lpf_biq1 = nphy_rxcal_gaintbl[optim_gaintbl_index].lpf_biq1;
+ lpf_biq0 = nphy_rxcal_gaintbl[optim_gaintbl_index].lpf_biq0;
+ lna2 = nphy_rxcal_gaintbl[optim_gaintbl_index].lna2;
+ lna1 = nphy_rxcal_gaintbl[optim_gaintbl_index].lna1;
+ txpwrindex = nphy_rxcal_gaintbl[optim_gaintbl_index].txpwrindex;
+
+ actual_log2_pwr = wlc_phy_nbits(optim_pwr);
+ delta_pwr = desired_log2_pwr - actual_log2_pwr;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ fine_gain_idx = (int)lpf_biq1 + delta_pwr;
+
+ if (fine_gain_idx + (int)lpf_biq0 > 10) {
+ lpf_biq1 = 10 - lpf_biq0;
+ } else {
+ lpf_biq1 = (u16) max(fine_gain_idx, 0);
+ }
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_rxgain,
+ ((lpf_biq1 << 12) |
+ (lpf_biq0 << 8) |
+ (mix_tia_gain << 4) |
+ (lna2 << 2) | lna1), 0x3,
+ 0);
+ } else {
+ hpvga = (u16) max(min(((int)hpvga) + delta_pwr, 10), 0);
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12),
+ ((hpvga << 12) | (lpf_biq1 << 10) |
+ (lpf_biq0 << 8) | (mix_tia_gain <<
+ 4) | (lna2 <<
+ 2) |
+ lna1), 0x3, 0);
+
+ }
+
+ if (rxgain != NULL) {
+ *rxgain++ = lna1;
+ *rxgain++ = lna2;
+ *rxgain++ = mix_tia_gain;
+ *rxgain++ = lpf_biq0;
+ *rxgain++ = lpf_biq1;
+ *rxgain = hpvga;
+ }
+
+ wlc_phy_rx_iq_coeffs_nphy(pi, 1, &save_comp);
+}
+
+static void
+wlc_phy_rxcal_gainctrl_nphy(phy_info_t *pi, u8 rx_core, u16 *rxgain,
+ u8 cal_type)
+{
+ wlc_phy_rxcal_gainctrl_nphy_rev5(pi, rx_core, rxgain, cal_type);
+}
+
+static u8
+wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
+{
+ u32 target_bws[2] = { 9500, 21000 };
+ u32 ref_tones[2] = { 3000, 6000 };
+ u32 target_bw, ref_tone;
+
+ u32 target_pwr_ratios[2] = { 28606, 18468 };
+ u32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0;
+
+ u16 start_rccal_ovr_val = 128;
+ u16 txlpf_rccal_lpc_ovr_val = 128;
+ u16 rxlpf_rccal_hpc_ovr_val = 159;
+
+ u16 orig_txlpf_rccal_lpc_ovr_val;
+ u16 orig_rxlpf_rccal_hpc_ovr_val;
+ u16 radio_addr_offset_rx;
+ u16 radio_addr_offset_tx;
+ u16 orig_dcBypass;
+ u16 orig_RxStrnFilt40Num[6];
+ u16 orig_RxStrnFilt40Den[4];
+ u16 orig_rfctrloverride[2];
+ u16 orig_rfctrlauxreg[2];
+ u16 orig_rfctrlrssiothers;
+ u16 tx_lpf_bw = 4;
+
+ u16 rx_lpf_bw, rx_lpf_bws[2] = { 2, 4 };
+ u16 lpf_hpc = 7, hpvga_hpc = 7;
+
+ s8 rccal_stepsize;
+ u16 rccal_val, last_rccal_val = 0, best_rccal_val = 0;
+ u32 ref_iq_vals = 0, target_iq_vals = 0;
+ u16 num_samps, log_num_samps = 10;
+ phy_iq_est_t est[PHY_CORE_MAX];
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ return 0;
+ }
+
+ num_samps = (1 << log_num_samps);
+
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ target_bw = target_bws[1];
+ target_pwr_ratio = target_pwr_ratios[1];
+ ref_tone = ref_tones[1];
+ rx_lpf_bw = rx_lpf_bws[1];
+ } else {
+ target_bw = target_bws[0];
+ target_pwr_ratio = target_pwr_ratios[0];
+ ref_tone = ref_tones[0];
+ rx_lpf_bw = rx_lpf_bws[0];
+ }
+
+ if (core_idx == 0) {
+ radio_addr_offset_rx = RADIO_2056_RX0;
+ radio_addr_offset_tx =
+ (loopback_type == 0) ? RADIO_2056_TX0 : RADIO_2056_TX1;
+ } else {
+ radio_addr_offset_rx = RADIO_2056_RX1;
+ radio_addr_offset_tx =
+ (loopback_type == 0) ? RADIO_2056_TX1 : RADIO_2056_TX0;
+ }
+
+ orig_txlpf_rccal_lpc_ovr_val =
+ read_radio_reg(pi,
+ (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx));
+ orig_rxlpf_rccal_hpc_ovr_val =
+ read_radio_reg(pi,
+ (RADIO_2056_RX_RXLPF_RCCAL_HPC |
+ radio_addr_offset_rx));
+
+ orig_dcBypass = ((read_phy_reg(pi, 0x48) >> 8) & 1);
+
+ orig_RxStrnFilt40Num[0] = read_phy_reg(pi, 0x267);
+ orig_RxStrnFilt40Num[1] = read_phy_reg(pi, 0x268);
+ orig_RxStrnFilt40Num[2] = read_phy_reg(pi, 0x269);
+ orig_RxStrnFilt40Den[0] = read_phy_reg(pi, 0x26a);
+ orig_RxStrnFilt40Den[1] = read_phy_reg(pi, 0x26b);
+ orig_RxStrnFilt40Num[3] = read_phy_reg(pi, 0x26c);
+ orig_RxStrnFilt40Num[4] = read_phy_reg(pi, 0x26d);
+ orig_RxStrnFilt40Num[5] = read_phy_reg(pi, 0x26e);
+ orig_RxStrnFilt40Den[2] = read_phy_reg(pi, 0x26f);
+ orig_RxStrnFilt40Den[3] = read_phy_reg(pi, 0x270);
+
+ orig_rfctrloverride[0] = read_phy_reg(pi, 0xe7);
+ orig_rfctrloverride[1] = read_phy_reg(pi, 0xec);
+ orig_rfctrlauxreg[0] = read_phy_reg(pi, 0xf8);
+ orig_rfctrlauxreg[1] = read_phy_reg(pi, 0xfa);
+ orig_rfctrlrssiothers = read_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d);
+
+ write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx),
+ txlpf_rccal_lpc_ovr_val);
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_RXLPF_RCCAL_HPC | radio_addr_offset_rx),
+ rxlpf_rccal_hpc_ovr_val);
+
+ mod_phy_reg(pi, 0x48, (0x1 << 8), (0x1 << 8));
+
+ write_phy_reg(pi, 0x267, 0x02d4);
+ write_phy_reg(pi, 0x268, 0x0000);
+ write_phy_reg(pi, 0x269, 0x0000);
+ write_phy_reg(pi, 0x26a, 0x0000);
+ write_phy_reg(pi, 0x26b, 0x0000);
+ write_phy_reg(pi, 0x26c, 0x02d4);
+ write_phy_reg(pi, 0x26d, 0x0000);
+ write_phy_reg(pi, 0x26e, 0x0000);
+ write_phy_reg(pi, 0x26f, 0x0000);
+ write_phy_reg(pi, 0x270, 0x0000);
+
+ or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 8));
+ or_phy_reg(pi, (core_idx == 0) ? 0xec : 0xe7, (0x1 << 15));
+ or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 9));
+ or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 10));
+
+ mod_phy_reg(pi, (core_idx == 0) ? 0xfa : 0xf8,
+ (0x7 << 10), (tx_lpf_bw << 10));
+ mod_phy_reg(pi, (core_idx == 0) ? 0xf8 : 0xfa,
+ (0x7 << 0), (hpvga_hpc << 0));
+ mod_phy_reg(pi, (core_idx == 0) ? 0xf8 : 0xfa,
+ (0x7 << 4), (lpf_hpc << 4));
+ mod_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d,
+ (0x7 << 8), (rx_lpf_bw << 8));
+
+ rccal_stepsize = 16;
+ rccal_val = start_rccal_ovr_val + rccal_stepsize;
+
+ while (rccal_stepsize >= 0) {
+ write_radio_reg(pi,
+ (RADIO_2056_RX_RXLPF_RCCAL_LPC |
+ radio_addr_offset_rx), rccal_val);
+
+ if (rccal_stepsize == 16) {
+
+ wlc_phy_tx_tone_nphy(pi, ref_tone, NPHY_RXCAL_TONEAMP,
+ 0, 1, false);
+ udelay(2);
+
+ wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
+
+ if (core_idx == 0) {
+ ref_iq_vals =
+ max_t(u32, (est[0].i_pwr +
+ est[0].q_pwr) >> (log_num_samps + 1),
+ 1);
+ } else {
+ ref_iq_vals =
+ max_t(u32, (est[1].i_pwr +
+ est[1].q_pwr) >> (log_num_samps + 1),
+ 1);
+ }
+
+ wlc_phy_tx_tone_nphy(pi, target_bw, NPHY_RXCAL_TONEAMP,
+ 0, 1, false);
+ udelay(2);
+ }
+
+ wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
+
+ if (core_idx == 0) {
+ target_iq_vals =
+ (est[0].i_pwr + est[0].q_pwr) >> (log_num_samps +
+ 1);
+ } else {
+ target_iq_vals =
+ (est[1].i_pwr + est[1].q_pwr) >> (log_num_samps +
+ 1);
+ }
+ pwr_ratio = (uint) ((target_iq_vals << 16) / ref_iq_vals);
+
+ if (rccal_stepsize == 0) {
+ rccal_stepsize--;
+ } else if (rccal_stepsize == 1) {
+ last_rccal_val = rccal_val;
+ rccal_val += (pwr_ratio > target_pwr_ratio) ? 1 : -1;
+ last_pwr_ratio = pwr_ratio;
+ rccal_stepsize--;
+ } else {
+ rccal_stepsize = (rccal_stepsize >> 1);
+ rccal_val += ((pwr_ratio > target_pwr_ratio) ?
+ rccal_stepsize : (-rccal_stepsize));
+ }
+
+ if (rccal_stepsize == -1) {
+ best_rccal_val =
+ (ABS((int)last_pwr_ratio - (int)target_pwr_ratio) <
+ ABS((int)pwr_ratio -
+ (int)target_pwr_ratio)) ? last_rccal_val :
+ rccal_val;
+
+ if (CHSPEC_IS40(pi->radio_chanspec)) {
+ if ((best_rccal_val > 140)
+ || (best_rccal_val < 135)) {
+ best_rccal_val = 138;
+ }
+ } else {
+ if ((best_rccal_val > 142)
+ || (best_rccal_val < 137)) {
+ best_rccal_val = 140;
+ }
+ }
+
+ write_radio_reg(pi,
+ (RADIO_2056_RX_RXLPF_RCCAL_LPC |
+ radio_addr_offset_rx), best_rccal_val);
+ }
+ }
+
+ wlc_phy_stopplayback_nphy(pi);
+
+ write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx),
+ orig_txlpf_rccal_lpc_ovr_val);
+ write_radio_reg(pi,
+ (RADIO_2056_RX_RXLPF_RCCAL_HPC | radio_addr_offset_rx),
+ orig_rxlpf_rccal_hpc_ovr_val);
+
+ mod_phy_reg(pi, 0x48, (0x1 << 8), (orig_dcBypass << 8));
+
+ write_phy_reg(pi, 0x267, orig_RxStrnFilt40Num[0]);
+ write_phy_reg(pi, 0x268, orig_RxStrnFilt40Num[1]);
+ write_phy_reg(pi, 0x269, orig_RxStrnFilt40Num[2]);
+ write_phy_reg(pi, 0x26a, orig_RxStrnFilt40Den[0]);
+ write_phy_reg(pi, 0x26b, orig_RxStrnFilt40Den[1]);
+ write_phy_reg(pi, 0x26c, orig_RxStrnFilt40Num[3]);
+ write_phy_reg(pi, 0x26d, orig_RxStrnFilt40Num[4]);
+ write_phy_reg(pi, 0x26e, orig_RxStrnFilt40Num[5]);
+ write_phy_reg(pi, 0x26f, orig_RxStrnFilt40Den[2]);
+ write_phy_reg(pi, 0x270, orig_RxStrnFilt40Den[3]);
+
+ write_phy_reg(pi, 0xe7, orig_rfctrloverride[0]);
+ write_phy_reg(pi, 0xec, orig_rfctrloverride[1]);
+ write_phy_reg(pi, 0xf8, orig_rfctrlauxreg[0]);
+ write_phy_reg(pi, 0xfa, orig_rfctrlauxreg[1]);
+ write_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d, orig_rfctrlrssiothers);
+
+ pi->nphy_anarxlpf_adjusted = false;
+
+ return best_rccal_val - 0x80;
+}
+
+#define WAIT_FOR_SCOPE 4000
+static int
+wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t target_gain,
+ u8 cal_type, bool debug)
+{
+ u16 orig_BBConfig;
+ u8 core_no, rx_core;
+ u8 best_rccal[2];
+ u16 gain_save[2];
+ u16 cal_gain[2];
+ nphy_iqcal_params_t cal_params[2];
+ u8 rxcore_state;
+ s8 rxlpf_rccal_hpc, txlpf_rccal_lpc;
+ s8 txlpf_idac;
+ bool phyhang_avoid_state = false;
+ bool skip_rxiqcal = false;
+
+ orig_BBConfig = read_phy_reg(pi, 0x01);
+ mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
+
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 4)) {
+ phyhang_avoid_state = pi->phyhang_avoid;
+ pi->phyhang_avoid = false;
+ }
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
+
+ for (core_no = 0; core_no <= 1; core_no++) {
+ wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
+ &cal_params[core_no]);
+ cal_gain[core_no] = cal_params[core_no].cal_gain;
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
+
+ rxcore_state = wlc_phy_rxcore_getstate_nphy((wlc_phy_t *) pi);
+
+ for (rx_core = 0; rx_core < pi->pubpi.phy_corenum; rx_core++) {
+
+ skip_rxiqcal =
+ ((rxcore_state & (1 << rx_core)) == 0) ? true : false;
+
+ wlc_phy_rxcal_physetup_nphy(pi, rx_core);
+
+ wlc_phy_rxcal_radio_setup_nphy(pi, rx_core);
+
+ if ((!skip_rxiqcal) && ((cal_type == 0) || (cal_type == 2))) {
+
+ wlc_phy_rxcal_gainctrl_nphy(pi, rx_core, NULL, 0);
+
+ wlc_phy_tx_tone_nphy(pi,
+ (CHSPEC_IS40(pi->radio_chanspec)) ?
+ NPHY_RXCAL_TONEFREQ_40MHz :
+ NPHY_RXCAL_TONEFREQ_20MHz,
+ NPHY_RXCAL_TONEAMP, 0, cal_type,
+ false);
+
+ if (debug)
+ mdelay(WAIT_FOR_SCOPE);
+
+ wlc_phy_calc_rx_iq_comp_nphy(pi, rx_core + 1);
+ wlc_phy_stopplayback_nphy(pi);
+ }
+
+ if (((cal_type == 1) || (cal_type == 2))
+ && NREV_LT(pi->pubpi.phy_rev, 7)) {
+
+ if (rx_core == PHY_CORE_1) {
+
+ if (rxcore_state == 1) {
+ wlc_phy_rxcore_setstate_nphy((wlc_phy_t
+ *) pi, 3);
+ }
+
+ wlc_phy_rxcal_gainctrl_nphy(pi, rx_core, NULL,
+ 1);
+
+ best_rccal[rx_core] =
+ wlc_phy_rc_sweep_nphy(pi, rx_core, 1);
+ pi->nphy_rccal_value = best_rccal[rx_core];
+
+ if (rxcore_state == 1) {
+ wlc_phy_rxcore_setstate_nphy((wlc_phy_t
+ *) pi,
+ rxcore_state);
+ }
+ }
+ }
+
+ wlc_phy_rxcal_radio_cleanup_nphy(pi, rx_core);
+
+ wlc_phy_rxcal_phycleanup_nphy(pi, rx_core);
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
+ }
+
+ if ((cal_type == 1) || (cal_type == 2)) {
+
+ best_rccal[0] = best_rccal[1];
+ write_radio_reg(pi,
+ (RADIO_2056_RX_RXLPF_RCCAL_LPC |
+ RADIO_2056_RX0), (best_rccal[0] | 0x80));
+
+ for (rx_core = 0; rx_core < pi->pubpi.phy_corenum; rx_core++) {
+ rxlpf_rccal_hpc =
+ (((int)best_rccal[rx_core] - 12) >> 1) + 10;
+ txlpf_rccal_lpc = ((int)best_rccal[rx_core] - 12) + 10;
+
+ if (PHY_IPA(pi)) {
+ txlpf_rccal_lpc += IS40MHZ(pi) ? 24 : 12;
+ txlpf_idac = IS40MHZ(pi) ? 0x0e : 0x13;
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, rx_core,
+ TXLPF_IDAC_4, txlpf_idac);
+ }
+
+ rxlpf_rccal_hpc = max(min_t(u8, rxlpf_rccal_hpc, 31), 0);
+ txlpf_rccal_lpc = max(min_t(u8, txlpf_rccal_lpc, 31), 0);
+
+ write_radio_reg(pi, (RADIO_2056_RX_RXLPF_RCCAL_HPC |
+ ((rx_core ==
+ PHY_CORE_0) ? RADIO_2056_RX0 :
+ RADIO_2056_RX1)),
+ (rxlpf_rccal_hpc | 0x80));
+
+ write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL |
+ ((rx_core ==
+ PHY_CORE_0) ? RADIO_2056_TX0 :
+ RADIO_2056_TX1)),
+ (txlpf_rccal_lpc | 0x80));
+ }
+ }
+
+ write_phy_reg(pi, 0x01, orig_BBConfig);
+
+ wlc_phy_resetcca_nphy(pi);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_rxgain,
+ 0, 0x3, 1);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 1);
+ }
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
+ gain_save);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 4)) {
+ pi->phyhang_avoid = phyhang_avoid_state;
+ }
+
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+
+ return 0;
+}
+
+static int
+wlc_phy_cal_rxiq_nphy_rev2(phy_info_t *pi, nphy_txgains_t target_gain,
+ bool debug)
+{
+ phy_iq_est_t est[PHY_CORE_MAX];
+ u8 core_num, rx_core, tx_core;
+ u16 lna_vals[] = { 0x3, 0x3, 0x1 };
+ u16 hpf1_vals[] = { 0x7, 0x2, 0x0 };
+ u16 hpf2_vals[] = { 0x2, 0x0, 0x0 };
+ s16 curr_hpf1, curr_hpf2, curr_hpf, curr_lna;
+ s16 desired_log2_pwr, actual_log2_pwr, hpf_change;
+ u16 orig_RfseqCoreActv, orig_AfectrlCore, orig_AfectrlOverride;
+ u16 orig_RfctrlIntcRx, orig_RfctrlIntcTx;
+ u16 num_samps;
+ u32 i_pwr, q_pwr, tot_pwr[3];
+ u8 gain_pass, use_hpf_num;
+ u16 mask, val1, val2;
+ u16 core_no;
+ u16 gain_save[2];
+ u16 cal_gain[2];
+ nphy_iqcal_params_t cal_params[2];
+ u8 phy_bw;
+ int bcmerror = 0;
+ bool first_playtone = true;
+
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+
+ wlc_phy_reapply_txcal_coeffs_nphy(pi);
+ }
+
+ wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
+
+ for (core_no = 0; core_no <= 1; core_no++) {
+ wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
+ &cal_params[core_no]);
+ cal_gain[core_no] = cal_params[core_no].cal_gain;
+ }
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
+
+ num_samps = 1024;
+ desired_log2_pwr = 13;
+
+ for (core_num = 0; core_num < 2; core_num++) {
+
+ rx_core = core_num;
+ tx_core = 1 - core_num;
+
+ orig_RfseqCoreActv = read_phy_reg(pi, 0xa2);
+ orig_AfectrlCore = read_phy_reg(pi, (rx_core == PHY_CORE_0) ?
+ 0xa6 : 0xa7);
+ orig_AfectrlOverride = read_phy_reg(pi, 0xa5);
+ orig_RfctrlIntcRx = read_phy_reg(pi, (rx_core == PHY_CORE_0) ?
+ 0x91 : 0x92);
+ orig_RfctrlIntcTx = read_phy_reg(pi, (tx_core == PHY_CORE_0) ?
+ 0x91 : 0x92);
+
+ mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << tx_core) << 12);
+ mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
+
+ or_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7),
+ ((0x1 << 1) | (0x1 << 2)));
+ or_phy_reg(pi, 0xa5, ((0x1 << 1) | (0x1 << 2)));
+
+ if (((pi->nphy_rxcalparams) & 0xff000000)) {
+
+ write_phy_reg(pi,
+ (rx_core == PHY_CORE_0) ? 0x91 : 0x92,
+ (CHSPEC_IS5G(pi->radio_chanspec) ? 0x140 :
+ 0x110));
+ } else {
+
+ write_phy_reg(pi,
+ (rx_core == PHY_CORE_0) ? 0x91 : 0x92,
+ (CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 :
+ 0x120));
+ }
+
+ write_phy_reg(pi, (tx_core == PHY_CORE_0) ? 0x91 : 0x92,
+ (CHSPEC_IS5G(pi->radio_chanspec) ? 0x148 :
+ 0x114));
+
+ mask = RADIO_2055_COUPLE_RX_MASK | RADIO_2055_COUPLE_TX_MASK;
+ if (rx_core == PHY_CORE_0) {
+ val1 = RADIO_2055_COUPLE_RX_MASK;
+ val2 = RADIO_2055_COUPLE_TX_MASK;
+ } else {
+ val1 = RADIO_2055_COUPLE_TX_MASK;
+ val2 = RADIO_2055_COUPLE_RX_MASK;
+ }
+
+ if ((pi->nphy_rxcalparams & 0x10000)) {
+ mod_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, mask,
+ val1);
+ mod_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, mask,
+ val2);
+ }
+
+ for (gain_pass = 0; gain_pass < 4; gain_pass++) {
+
+ if (debug)
+ mdelay(WAIT_FOR_SCOPE);
+
+ if (gain_pass < 3) {
+ curr_lna = lna_vals[gain_pass];
+ curr_hpf1 = hpf1_vals[gain_pass];
+ curr_hpf2 = hpf2_vals[gain_pass];
+ } else {
+
+ if (tot_pwr[1] > 10000) {
+ curr_lna = lna_vals[2];
+ curr_hpf1 = hpf1_vals[2];
+ curr_hpf2 = hpf2_vals[2];
+ use_hpf_num = 1;
+ curr_hpf = curr_hpf1;
+ actual_log2_pwr =
+ wlc_phy_nbits(tot_pwr[2]);
+ } else {
+ if (tot_pwr[0] > 10000) {
+ curr_lna = lna_vals[1];
+ curr_hpf1 = hpf1_vals[1];
+ curr_hpf2 = hpf2_vals[1];
+ use_hpf_num = 1;
+ curr_hpf = curr_hpf1;
+ actual_log2_pwr =
+ wlc_phy_nbits(tot_pwr[1]);
+ } else {
+ curr_lna = lna_vals[0];
+ curr_hpf1 = hpf1_vals[0];
+ curr_hpf2 = hpf2_vals[0];
+ use_hpf_num = 2;
+ curr_hpf = curr_hpf2;
+ actual_log2_pwr =
+ wlc_phy_nbits(tot_pwr[0]);
+ }
+ }
+
+ hpf_change = desired_log2_pwr - actual_log2_pwr;
+ curr_hpf += hpf_change;
+ curr_hpf = max(min_t(u16, curr_hpf, 10), 0);
+ if (use_hpf_num == 1) {
+ curr_hpf1 = curr_hpf;
+ } else {
+ curr_hpf2 = curr_hpf;
+ }
+ }
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 10),
+ ((curr_hpf2 << 8) |
+ (curr_hpf1 << 4) |
+ (curr_lna << 2)), 0x3, 0);
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
+
+ wlc_phy_stopplayback_nphy(pi);
+
+ if (first_playtone) {
+ bcmerror = wlc_phy_tx_tone_nphy(pi, 4000,
+ (u16) (pi->
+ nphy_rxcalparams
+ &
+ 0xffff),
+ 0, 0, true);
+ first_playtone = false;
+ } else {
+ phy_bw =
+ (CHSPEC_IS40(pi->radio_chanspec)) ? 40 : 20;
+ wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff,
+ 0, 0, 0, true);
+ }
+
+ if (bcmerror == 0) {
+ if (gain_pass < 3) {
+
+ wlc_phy_rx_iq_est_nphy(pi, est,
+ num_samps, 32,
+ 0);
+ i_pwr =
+ (est[rx_core].i_pwr +
+ num_samps / 2) / num_samps;
+ q_pwr =
+ (est[rx_core].q_pwr +
+ num_samps / 2) / num_samps;
+ tot_pwr[gain_pass] = i_pwr + q_pwr;
+ } else {
+
+ wlc_phy_calc_rx_iq_comp_nphy(pi,
+ (1 <<
+ rx_core));
+ }
+
+ wlc_phy_stopplayback_nphy(pi);
+ }
+
+ if (bcmerror != 0)
+ break;
+ }
+
+ and_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, ~mask);
+ and_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, ~mask);
+
+ write_phy_reg(pi, (tx_core == PHY_CORE_0) ? 0x91 :
+ 0x92, orig_RfctrlIntcTx);
+ write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x91 :
+ 0x92, orig_RfctrlIntcRx);
+ write_phy_reg(pi, 0xa5, orig_AfectrlOverride);
+ write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 :
+ 0xa7, orig_AfectrlCore);
+ write_phy_reg(pi, 0xa2, orig_RfseqCoreActv);
+
+ if (bcmerror != 0)
+ break;
+ }
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 10), 0, 0x3, 1);
+ wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
+ gain_save);
+
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+
+ return bcmerror;
+}
+
+int
+wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
+ u8 cal_type, bool debug)
+{
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ cal_type = 0;
+ }
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ return wlc_phy_cal_rxiq_nphy_rev3(pi, target_gain, cal_type,
+ debug);
+ } else {
+ return wlc_phy_cal_rxiq_nphy_rev2(pi, target_gain, debug);
+ }
+}
+
+static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi)
+{
+ int j, type = 2;
+ u16 addr_offset = 0x2c5;
+
+ for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, addr_offset + j,
+ NPHY_IPA_REV4_txdigi_filtcoeffs[type][j]);
+ }
+}
+
+static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi)
+{
+ int j, type;
+ u16 addr_offset[] = { 0x186, 0x195,
+ 0x2c5
+ };
+
+ for (type = 0; type < 3; type++) {
+ for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, addr_offset[type] + j,
+ NPHY_IPA_REV4_txdigi_filtcoeffs[type][j]);
+ }
+ }
+
+ if (IS40MHZ(pi)) {
+ for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, 0x186 + j,
+ NPHY_IPA_REV4_txdigi_filtcoeffs[3][j]);
+ }
+ } else {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, 0x186 + j,
+ NPHY_IPA_REV4_txdigi_filtcoeffs[5]
+ [j]);
+ }
+ }
+
+ if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
+ for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, 0x2c5 + j,
+ NPHY_IPA_REV4_txdigi_filtcoeffs[6]
+ [j]);
+ }
+ }
+ }
+}
+
+static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi)
+{
+ int j;
+
+ if (IS40MHZ(pi)) {
+ for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, 0x195 + j,
+ NPHY_IPA_REV4_txdigi_filtcoeffs[4][j]);
+ }
+ } else {
+ for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
+ write_phy_reg(pi, 0x186 + j,
+ NPHY_IPA_REV4_txdigi_filtcoeffs[3][j]);
+ }
+ }
+}
+
+static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi)
+{
+ u16 m0m1;
+
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1);
+
+ return m0m1;
+}
+
+static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1)
+{
+ u16 m0m1 = (u16) ((m0 << 8) | m1);
+
+ wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m0m1);
+ wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1);
+}
+
+static u32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi)
+{
+ u32 *tx_pwrctrl_tbl = NULL;
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ if ((pi->pubpi.radiorev == 4)
+ || (pi->pubpi.radiorev == 6)) {
+
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_ipa_2g_2057rev4n6;
+ } else if (pi->pubpi.radiorev == 3) {
+
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_ipa_2g_2057rev3;
+ } else if (pi->pubpi.radiorev == 5) {
+
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_ipa_2g_2057rev5;
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_ipa_2g_2057rev7;
+ }
+
+ } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
+
+ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev6;
+ if (pi->sh->chip == BCM47162_CHIP_ID) {
+
+ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
+ }
+
+ } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
+
+ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
+ } else {
+
+ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa;
+ }
+
+ } else {
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if ((pi->pubpi.radiorev == 3) ||
+ (pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+
+ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_5g_2057;
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ tx_pwrctrl_tbl =
+ nphy_tpc_txgain_ipa_5g_2057rev7;
+ }
+
+ } else {
+ tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_5g;
+ }
+ }
+
+ return tx_pwrctrl_tbl;
+}
+
+static void
+wlc_phy_papd_cal_setup_nphy(phy_info_t *pi, nphy_papd_restore_state *state,
+ u8 core)
+{
+ s32 tone_freq;
+ u8 off_core;
+ u16 mixgain = 0;
+
+ off_core = core ^ 0x1;
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)
+ || NREV_GE(pi->pubpi.phy_rev, 8)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
+ wlc_phy_read_lpf_bw_ctl_nphy
+ (pi, 0), 0, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (pi->pubpi.radiorev == 5) {
+ mixgain = (core == 0) ? 0x20 : 0x00;
+
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ mixgain = 0x00;
+
+ } else if ((pi->pubpi.radiorev <= 4)
+ || (pi->pubpi.radiorev == 6)) {
+
+ mixgain = 0x00;
+ }
+
+ } else {
+ if ((pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+
+ mixgain = 0x50;
+ } else if ((pi->pubpi.radiorev == 3)
+ || (pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ mixgain = 0x0;
+ }
+ }
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11),
+ mixgain, (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_tx_pu,
+ 1, (1 << core), 0);
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_tx_pu,
+ 0, (1 << off_core), 0);
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
+ 0, 0x3, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1,
+ (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0,
+ (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1,
+ (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 8), 0,
+ (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 1,
+ (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 0,
+ (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 1,
+ (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5),
+ 0, (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 0,
+ (1 << core), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+
+ state->afectrl[core] = read_phy_reg(pi, (core == PHY_CORE_0) ?
+ 0xa6 : 0xa7);
+ state->afeoverride[core] =
+ read_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f : 0xa5);
+ state->afectrl[off_core] =
+ read_phy_reg(pi, (core == PHY_CORE_0) ? 0xa7 : 0xa6);
+ state->afeoverride[off_core] =
+ read_phy_reg(pi, (core == PHY_CORE_0) ? 0xa5 : 0x8f);
+
+ mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa6 : 0xa7),
+ (0x1 << 2), 0);
+ mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
+ 0xa5), (0x1 << 2), (0x1 << 2));
+
+ mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa7 : 0xa6),
+ (0x1 << 2), (0x1 << 2));
+ mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa5 :
+ 0x8f), (0x1 << 2), (0x1 << 2));
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ state->pwrup[core] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_2G_PWRUP);
+ state->atten[core] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_2G_ATTEN);
+ state->pwrup[off_core] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
+ TXRXCOUPLE_2G_PWRUP);
+ state->atten[off_core] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
+ TXRXCOUPLE_2G_ATTEN);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_2G_PWRUP, 0xc);
+
+ if ((pi->pubpi.radiorev == 3) ||
+ (pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_2G_ATTEN, 0xf0);
+
+ } else if (pi->pubpi.radiorev == 5) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_2G_ATTEN,
+ (core == 0) ? 0xf7 : 0xf2);
+
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_2G_ATTEN, 0xf0);
+
+ }
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
+ TXRXCOUPLE_2G_PWRUP, 0x0);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
+ TXRXCOUPLE_2G_ATTEN, 0xff);
+
+ } else {
+ state->pwrup[core] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_5G_PWRUP);
+ state->atten[core] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_5G_ATTEN);
+ state->pwrup[off_core] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
+ TXRXCOUPLE_5G_PWRUP);
+ state->atten[off_core] =
+ READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
+ TXRXCOUPLE_5G_ATTEN);
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_5G_PWRUP, 0xc);
+
+ if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_5G_ATTEN, 0xf4);
+
+ } else {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_5G_ATTEN, 0xf0);
+ }
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
+ TXRXCOUPLE_5G_PWRUP, 0x0);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
+ TXRXCOUPLE_5G_ATTEN, 0xff);
+ }
+
+ tone_freq = 4000;
+
+ wlc_phy_tx_tone_nphy(pi, tone_freq, 181, 0, 0, false);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 13), (1) << 13);
+
+ mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_OFF) << 0);
+
+ mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 13), (0) << 13);
+
+ } else {
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 0);
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 1, 0, 0);
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0x3, 0);
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 2), 1, 0x3, 0);
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 1, 0x3, 0);
+
+ state->afectrl[core] = read_phy_reg(pi, (core == PHY_CORE_0) ?
+ 0xa6 : 0xa7);
+ state->afeoverride[core] =
+ read_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f : 0xa5);
+
+ mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa6 : 0xa7),
+ (0x1 << 0) | (0x1 << 1) | (0x1 << 2), 0);
+ mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
+ 0xa5),
+ (0x1 << 0) |
+ (0x1 << 1) |
+ (0x1 << 2), (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
+
+ state->vga_master[core] =
+ READ_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER);
+ WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER, 0x2b);
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ state->fbmix[core] =
+ READ_RADIO_REG2(pi, RADIO_2056, RX, core,
+ TXFBMIX_G);
+ state->intpa_master[core] =
+ READ_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_MASTER);
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, TXFBMIX_G,
+ 0x03);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_MASTER, 0x04);
+ } else {
+ state->fbmix[core] =
+ READ_RADIO_REG2(pi, RADIO_2056, RX, core,
+ TXFBMIX_A);
+ state->intpa_master[core] =
+ READ_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAA_MASTER);
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, TXFBMIX_A,
+ 0x03);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAA_MASTER, 0x04);
+
+ }
+
+ tone_freq = 4000;
+
+ wlc_phy_tx_tone_nphy(pi, tone_freq, 181, 0, 0, false);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (1) << 0);
+
+ mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (0) << 0);
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 0);
+ }
+}
+
+static void
+wlc_phy_papd_cal_cleanup_nphy(phy_info_t *pi, nphy_papd_restore_state *state)
+{
+ u8 core;
+
+ wlc_phy_stopplayback_nphy(pi);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_2G_PWRUP, 0);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_2G_ATTEN,
+ state->atten[core]);
+ } else {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_5G_PWRUP, 0);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TXRXCOUPLE_5G_ATTEN,
+ state->atten[core]);
+ }
+ }
+
+ if ((pi->pubpi.radiorev == 4) || (pi->pubpi.radiorev == 6)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
+ 1, 0x3, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ } else {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
+ 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ }
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1),
+ 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 1, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID2);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 8), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 1, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 1, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+
+ write_phy_reg(pi, (core == PHY_CORE_0) ?
+ 0xa6 : 0xa7, state->afectrl[core]);
+ write_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f :
+ 0xa5, state->afeoverride[core]);
+ }
+
+ wlc_phy_ipa_set_bbmult_nphy(pi, (state->mm >> 8) & 0xff,
+ (state->mm & 0xff));
+
+ if (NREV_IS(pi->pubpi.phy_rev, 7)
+ || NREV_GE(pi->pubpi.phy_rev, 8)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7), 0, 0,
+ 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID1);
+ }
+ } else {
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 1);
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 0x3, 1);
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0x3, 1);
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 2), 0, 0x3, 1);
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 0, 0x3, 1);
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER,
+ state->vga_master[core]);
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ WRITE_RADIO_REG2(pi, RADIO_2056, RX, core,
+ TXFBMIX_G, state->fbmix[core]);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAG_MASTER,
+ state->intpa_master[core]);
+ } else {
+ WRITE_RADIO_REG2(pi, RADIO_2056, RX, core,
+ TXFBMIX_A, state->fbmix[core]);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ INTPAA_MASTER,
+ state->intpa_master[core]);
+ }
+
+ write_phy_reg(pi, (core == PHY_CORE_0) ?
+ 0xa6 : 0xa7, state->afectrl[core]);
+ write_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f :
+ 0xa5, state->afeoverride[core]);
+ }
+
+ wlc_phy_ipa_set_bbmult_nphy(pi, (state->mm >> 8) & 0xff,
+ (state->mm & 0xff));
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 1);
+ }
+}
+
+static void
+wlc_phy_a1_nphy(phy_info_t *pi, u8 core, u32 winsz, u32 start,
+ u32 end)
+{
+ u32 *buf, *src, *dst, sz;
+
+ sz = end - start + 1;
+
+ buf = kmalloc(2 * sizeof(u32) * NPHY_PAPD_EPS_TBL_SIZE, GFP_ATOMIC);
+ if (NULL == buf) {
+ return;
+ }
+
+ src = buf;
+ dst = buf + NPHY_PAPD_EPS_TBL_SIZE;
+
+ wlc_phy_table_read_nphy(pi,
+ (core ==
+ PHY_CORE_0 ? NPHY_TBL_ID_EPSILONTBL0 :
+ NPHY_TBL_ID_EPSILONTBL1),
+ NPHY_PAPD_EPS_TBL_SIZE, 0, 32, src);
+
+ do {
+ u32 phy_a1, phy_a2;
+ s32 phy_a3, phy_a4, phy_a5, phy_a6, phy_a7;
+
+ phy_a1 = end - min(end, (winsz >> 1));
+ phy_a2 = min_t(u32, NPHY_PAPD_EPS_TBL_SIZE - 1, end + (winsz >> 1));
+ phy_a3 = phy_a2 - phy_a1 + 1;
+ phy_a6 = 0;
+ phy_a7 = 0;
+
+ do {
+ wlc_phy_papd_decode_epsilon(src[phy_a2], &phy_a4,
+ &phy_a5);
+ phy_a6 += phy_a4;
+ phy_a7 += phy_a5;
+ } while (phy_a2-- != phy_a1);
+
+ phy_a6 /= phy_a3;
+ phy_a7 /= phy_a3;
+ dst[end] = ((u32) phy_a7 << 13) | ((u32) phy_a6 & 0x1fff);
+ } while (end-- != start);
+
+ wlc_phy_table_write_nphy(pi,
+ (core ==
+ PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0 :
+ NPHY_TBL_ID_EPSILONTBL1, sz, start, 32, dst);
+
+ kfree(buf);
+}
+
+static void
+wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *txgains,
+ phy_cal_mode_t cal_mode, u8 core)
+{
+ u16 phy_a1, phy_a2, phy_a3;
+ u16 phy_a4, phy_a5;
+ bool phy_a6;
+ u8 phy_a7, m[2];
+ u32 phy_a8 = 0;
+ nphy_txgains_t phy_a9;
+
+ if (NREV_LT(pi->pubpi.phy_rev, 3))
+ return;
+
+ phy_a7 = (core == PHY_CORE_0) ? 1 : 0;
+
+ phy_a6 = ((cal_mode == CAL_GCTRL)
+ || (cal_mode == CAL_SOFT)) ? true : false;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ phy_a9 = wlc_phy_get_tx_gain_nphy(pi);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ phy_a5 = ((phy_a9.txlpf[core] << 15) |
+ (phy_a9.txgm[core] << 12) |
+ (phy_a9.pga[core] << 8) |
+ (txgains->gains.pad[core] << 3) |
+ (phy_a9.ipa[core]));
+ } else {
+ phy_a5 = ((phy_a9.txlpf[core] << 15) |
+ (phy_a9.txgm[core] << 12) |
+ (txgains->gains.pga[core] << 8) |
+ (phy_a9.pad[core] << 3) | (phy_a9.ipa[core]));
+ }
+
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_txgain,
+ phy_a5, (1 << core), 0);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if ((pi->pubpi.radiorev <= 4)
+ || (pi->pubpi.radiorev == 6)) {
+
+ m[core] = IS40MHZ(pi) ? 60 : 79;
+ } else {
+
+ m[core] = IS40MHZ(pi) ? 45 : 64;
+ }
+
+ } else {
+ m[core] = IS40MHZ(pi) ? 75 : 107;
+ }
+
+ m[phy_a7] = 0;
+ wlc_phy_ipa_set_bbmult_nphy(pi, m[0], m[1]);
+
+ phy_a2 = 63;
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (pi->sh->chip == BCM6362_CHIP_ID) {
+ phy_a1 = 35;
+ phy_a3 = 35;
+ } else if ((pi->pubpi.radiorev == 4)
+ || (pi->pubpi.radiorev == 6)) {
+ phy_a1 = 30;
+ phy_a3 = 30;
+ } else {
+ phy_a1 = 25;
+ phy_a3 = 25;
+ }
+ } else {
+ if ((pi->pubpi.radiorev == 5)
+ || (pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+ phy_a1 = 25;
+ phy_a3 = 25;
+ } else {
+ phy_a1 = 35;
+ phy_a3 = 35;
+ }
+ }
+
+ if (cal_mode == CAL_GCTRL) {
+ if ((pi->pubpi.radiorev == 5)
+ && (CHSPEC_IS2G(pi->radio_chanspec))) {
+ phy_a1 = 55;
+ } else if (((pi->pubpi.radiorev == 7) &&
+ (CHSPEC_IS2G(pi->radio_chanspec))) ||
+ ((pi->pubpi.radiorev == 8) &&
+ (CHSPEC_IS2G(pi->radio_chanspec)))) {
+ phy_a1 = 60;
+ } else {
+ phy_a1 = 63;
+ }
+
+ } else if ((cal_mode != CAL_FULL) && (cal_mode != CAL_SOFT)) {
+
+ phy_a1 = 35;
+ phy_a3 = 35;
+ }
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (1) << 0);
+
+ mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (0) << 0);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 13), (1) << 13);
+
+ mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 13), (0) << 13);
+
+ write_phy_reg(pi, 0x2a1, 0x80);
+ write_phy_reg(pi, 0x2a2, 0x100);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x7 << 4), (11) << 4);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x7 << 8), (11) << 8);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x7 << 0), (0x3) << 0);
+
+ write_phy_reg(pi, 0x2e5, 0x20);
+
+ mod_phy_reg(pi, 0x2a0, (0x3f << 0), (phy_a3) << 0);
+
+ mod_phy_reg(pi, 0x29f, (0x3f << 0), (phy_a1) << 0);
+
+ mod_phy_reg(pi, 0x29f, (0x3f << 8), (phy_a2) << 8);
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
+ 1, ((core == 0) ? 1 : 2), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
+ 0, ((core == 0) ? 2 : 1), 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+
+ write_phy_reg(pi, 0x2be, 1);
+ SPINWAIT(read_phy_reg(pi, 0x2be), 10 * 1000 * 1000);
+
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
+ 0, 0x3, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+
+ wlc_phy_table_write_nphy(pi,
+ (core ==
+ PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0
+ : NPHY_TBL_ID_EPSILONTBL1, 1, phy_a3,
+ 32, &phy_a8);
+
+ if (cal_mode != CAL_GCTRL) {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ wlc_phy_a1_nphy(pi, core, 5, 0, 35);
+ }
+ }
+
+ wlc_phy_rfctrl_override_1tomany_nphy(pi,
+ NPHY_REV7_RfctrlOverride_cmd_txgain,
+ phy_a5, (1 << core), 1);
+
+ } else {
+
+ if (txgains) {
+ if (txgains->useindex) {
+ phy_a4 = 15 - ((txgains->index) >> 3);
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+ phy_a5 = 0x00f7 | (phy_a4 << 8);
+
+ if (pi->sh->chip ==
+ BCM47162_CHIP_ID) {
+ phy_a5 =
+ 0x10f7 | (phy_a4 <<
+ 8);
+ }
+ } else
+ if (NREV_IS(pi->pubpi.phy_rev, 5))
+ phy_a5 = 0x10f7 | (phy_a4 << 8);
+ else
+ phy_a5 = 0x50f7 | (phy_a4 << 8);
+ } else {
+ phy_a5 = 0x70f7 | (phy_a4 << 8);
+ }
+ wlc_phy_rfctrl_override_nphy(pi,
+ (0x1 << 13),
+ phy_a5,
+ (1 << core), 0);
+ } else {
+ wlc_phy_rfctrl_override_nphy(pi,
+ (0x1 << 13),
+ 0x5bf7,
+ (1 << core), 0);
+ }
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ m[core] = IS40MHZ(pi) ? 45 : 64;
+ } else {
+ m[core] = IS40MHZ(pi) ? 75 : 107;
+ }
+
+ m[phy_a7] = 0;
+ wlc_phy_ipa_set_bbmult_nphy(pi, m[0], m[1]);
+
+ phy_a2 = 63;
+
+ if (cal_mode == CAL_FULL) {
+ phy_a1 = 25;
+ phy_a3 = 25;
+ } else if (cal_mode == CAL_SOFT) {
+ phy_a1 = 25;
+ phy_a3 = 25;
+ } else if (cal_mode == CAL_GCTRL) {
+ phy_a1 = 63;
+ phy_a3 = 25;
+ } else {
+
+ phy_a1 = 25;
+ phy_a3 = 25;
+ }
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (1) << 0);
+
+ mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (0) << 0);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 13), (1) << 13);
+
+ mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 13), (0) << 13);
+
+ write_phy_reg(pi, 0x2a1, 0x20);
+ write_phy_reg(pi, 0x2a2, 0x60);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0xf << 4), (9) << 4);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0xf << 8), (9) << 8);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0xf << 0), (0x2) << 0);
+
+ write_phy_reg(pi, 0x2e5, 0x20);
+ } else {
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 11), (1) << 11);
+
+ mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 11), (0) << 11);
+
+ write_phy_reg(pi, 0x2a1, 0x80);
+ write_phy_reg(pi, 0x2a2, 0x600);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x7 << 4), (0) << 4);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x7 << 8), (0) << 8);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x7 << 0), (0x3) << 0);
+
+ mod_phy_reg(pi, 0x2a0, (0x3f << 8), (0x20) << 8);
+
+ }
+
+ mod_phy_reg(pi, 0x2a0, (0x3f << 0), (phy_a3) << 0);
+
+ mod_phy_reg(pi, 0x29f, (0x3f << 0), (phy_a1) << 0);
+
+ mod_phy_reg(pi, 0x29f, (0x3f << 8), (phy_a2) << 8);
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 1, 0x3, 0);
+
+ write_phy_reg(pi, 0x2be, 1);
+ SPINWAIT(read_phy_reg(pi, 0x2be), 10 * 1000 * 1000);
+
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 0);
+
+ wlc_phy_table_write_nphy(pi,
+ (core ==
+ PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0
+ : NPHY_TBL_ID_EPSILONTBL1, 1, phy_a3,
+ 32, &phy_a8);
+
+ if (cal_mode != CAL_GCTRL) {
+ wlc_phy_a1_nphy(pi, core, 5, 0, 40);
+ }
+ }
+}
+
+static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core)
+{
+ int phy_a1;
+ int phy_a2;
+ bool phy_a3;
+ nphy_ipa_txcalgains_t phy_a4;
+ bool phy_a5 = false;
+ bool phy_a6 = true;
+ s32 phy_a7, phy_a8;
+ u32 phy_a9;
+ int phy_a10;
+ bool phy_a11 = false;
+ int phy_a12;
+ u8 phy_a13 = 0;
+ u8 phy_a14;
+ u8 *phy_a15 = NULL;
+
+ phy_a4.useindex = true;
+ phy_a12 = start_gain;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+
+ phy_a2 = 20;
+ phy_a1 = 1;
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (pi->pubpi.radiorev == 5) {
+
+ phy_a15 = pad_gain_codes_used_2057rev5;
+ phy_a13 = sizeof(pad_gain_codes_used_2057rev5) /
+ sizeof(pad_gain_codes_used_2057rev5[0]) - 1;
+
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ phy_a15 = pad_gain_codes_used_2057rev7;
+ phy_a13 = sizeof(pad_gain_codes_used_2057rev7) /
+ sizeof(pad_gain_codes_used_2057rev7[0]) - 1;
+
+ } else {
+
+ phy_a15 = pad_all_gain_codes_2057;
+ phy_a13 = sizeof(pad_all_gain_codes_2057) /
+ sizeof(pad_all_gain_codes_2057[0]) - 1;
+ }
+
+ } else {
+
+ phy_a15 = pga_all_gain_codes_2057;
+ phy_a13 = sizeof(pga_all_gain_codes_2057) /
+ sizeof(pga_all_gain_codes_2057[0]) - 1;
+ }
+
+ phy_a14 = 0;
+
+ for (phy_a10 = 0; phy_a10 < phy_a2; phy_a10++) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ phy_a4.gains.pad[core] =
+ (u16) phy_a15[phy_a12];
+ } else {
+ phy_a4.gains.pga[core] =
+ (u16) phy_a15[phy_a12];
+ }
+
+ wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core);
+
+ wlc_phy_table_read_nphy(pi,
+ (core ==
+ PHY_CORE_0 ?
+ NPHY_TBL_ID_EPSILONTBL0 :
+ NPHY_TBL_ID_EPSILONTBL1), 1,
+ 63, 32, &phy_a9);
+
+ wlc_phy_papd_decode_epsilon(phy_a9, &phy_a7, &phy_a8);
+
+ phy_a3 = ((phy_a7 == 4095) || (phy_a7 == -4096) ||
+ (phy_a8 == 4095) || (phy_a8 == -4096));
+
+ if (!phy_a6 && (phy_a3 != phy_a5)) {
+ if (!phy_a3) {
+ phy_a12 -= (u8) phy_a1;
+ }
+ phy_a11 = true;
+ break;
+ }
+
+ if (phy_a3)
+ phy_a12 += (u8) phy_a1;
+ else
+ phy_a12 -= (u8) phy_a1;
+
+ if ((phy_a12 < phy_a14) || (phy_a12 > phy_a13)) {
+ if (phy_a12 < phy_a14) {
+ phy_a12 = phy_a14;
+ } else {
+ phy_a12 = phy_a13;
+ }
+ phy_a11 = true;
+ break;
+ }
+
+ phy_a6 = false;
+ phy_a5 = phy_a3;
+ }
+
+ } else {
+ phy_a2 = 10;
+ phy_a1 = 8;
+ for (phy_a10 = 0; phy_a10 < phy_a2; phy_a10++) {
+ phy_a4.index = (u8) phy_a12;
+ wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core);
+
+ wlc_phy_table_read_nphy(pi,
+ (core ==
+ PHY_CORE_0 ?
+ NPHY_TBL_ID_EPSILONTBL0 :
+ NPHY_TBL_ID_EPSILONTBL1), 1,
+ 63, 32, &phy_a9);
+
+ wlc_phy_papd_decode_epsilon(phy_a9, &phy_a7, &phy_a8);
+
+ phy_a3 = ((phy_a7 == 4095) || (phy_a7 == -4096) ||
+ (phy_a8 == 4095) || (phy_a8 == -4096));
+
+ if (!phy_a6 && (phy_a3 != phy_a5)) {
+ if (!phy_a3) {
+ phy_a12 -= (u8) phy_a1;
+ }
+ phy_a11 = true;
+ break;
+ }
+
+ if (phy_a3)
+ phy_a12 += (u8) phy_a1;
+ else
+ phy_a12 -= (u8) phy_a1;
+
+ if ((phy_a12 < 0) || (phy_a12 > 127)) {
+ if (phy_a12 < 0) {
+ phy_a12 = 0;
+ } else {
+ phy_a12 = 127;
+ }
+ phy_a11 = true;
+ break;
+ }
+
+ phy_a6 = false;
+ phy_a5 = phy_a3;
+ }
+
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ return (u8) phy_a15[phy_a12];
+ } else {
+ return (u8) phy_a12;
+ }
+
+}
+
+static void wlc_phy_a4(phy_info_t *pi, bool full_cal)
+{
+ nphy_ipa_txcalgains_t phy_b1[2];
+ nphy_papd_restore_state phy_b2;
+ bool phy_b3;
+ u8 phy_b4;
+ u8 phy_b5;
+ s16 phy_b6, phy_b7, phy_b8;
+ u16 phy_b9;
+ s16 phy_b10, phy_b11, phy_b12;
+
+ phy_b11 = 0;
+ phy_b12 = 0;
+ phy_b7 = 0;
+ phy_b8 = 0;
+ phy_b6 = 0;
+
+ if (pi->nphy_papd_skip == 1)
+ return;
+
+ phy_b3 =
+ (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
+ if (!phy_b3) {
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+ }
+
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ pi->nphy_force_papd_cal = false;
+
+ for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++)
+ pi->nphy_papd_tx_gain_at_last_cal[phy_b5] =
+ wlc_phy_txpwr_idx_cur_get_nphy(pi, phy_b5);
+
+ pi->nphy_papd_last_cal = pi->sh->now;
+ pi->nphy_papd_recal_counter++;
+
+ if (NORADIO_ENAB(pi->pubpi))
+ return;
+
+ phy_b4 = pi->nphy_txpwrctrl;
+ wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SCALARTBL0, 64, 0, 32,
+ nphy_papd_scaltbl);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SCALARTBL1, 64, 0, 32,
+ nphy_papd_scaltbl);
+
+ phy_b9 = read_phy_reg(pi, 0x01);
+ mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
+
+ for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
+ s32 i, val = 0;
+ for (i = 0; i < 64; i++) {
+ wlc_phy_table_write_nphy(pi,
+ ((phy_b5 ==
+ PHY_CORE_0) ?
+ NPHY_TBL_ID_EPSILONTBL0 :
+ NPHY_TBL_ID_EPSILONTBL1), 1,
+ i, 32, &val);
+ }
+ }
+
+ wlc_phy_ipa_restore_tx_digi_filts_nphy(pi);
+
+ phy_b2.mm = wlc_phy_ipa_get_bbmult_nphy(pi);
+ for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
+ wlc_phy_papd_cal_setup_nphy(pi, &phy_b2, phy_b5);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+
+ if ((pi->pubpi.radiorev == 3)
+ || (pi->pubpi.radiorev == 4)
+ || (pi->pubpi.radiorev == 6)) {
+
+ pi->nphy_papd_cal_gain_index[phy_b5] =
+ 23;
+
+ } else if (pi->pubpi.radiorev == 5) {
+
+ pi->nphy_papd_cal_gain_index[phy_b5] =
+ 0;
+ pi->nphy_papd_cal_gain_index[phy_b5] =
+ wlc_phy_a3_nphy(pi,
+ pi->
+ nphy_papd_cal_gain_index
+ [phy_b5], phy_b5);
+
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+
+ pi->nphy_papd_cal_gain_index[phy_b5] =
+ 0;
+ pi->nphy_papd_cal_gain_index[phy_b5] =
+ wlc_phy_a3_nphy(pi,
+ pi->
+ nphy_papd_cal_gain_index
+ [phy_b5], phy_b5);
+
+ }
+
+ phy_b1[phy_b5].gains.pad[phy_b5] =
+ pi->nphy_papd_cal_gain_index[phy_b5];
+
+ } else {
+ pi->nphy_papd_cal_gain_index[phy_b5] = 0;
+ pi->nphy_papd_cal_gain_index[phy_b5] =
+ wlc_phy_a3_nphy(pi,
+ pi->
+ nphy_papd_cal_gain_index
+ [phy_b5], phy_b5);
+ phy_b1[phy_b5].gains.pga[phy_b5] =
+ pi->nphy_papd_cal_gain_index[phy_b5];
+ }
+ } else {
+ phy_b1[phy_b5].useindex = true;
+ phy_b1[phy_b5].index = 16;
+ phy_b1[phy_b5].index =
+ wlc_phy_a3_nphy(pi, phy_b1[phy_b5].index, phy_b5);
+
+ pi->nphy_papd_cal_gain_index[phy_b5] =
+ 15 - ((phy_b1[phy_b5].index) >> 3);
+ }
+
+ switch (pi->nphy_papd_cal_type) {
+ case 0:
+ wlc_phy_a2_nphy(pi, &phy_b1[phy_b5], CAL_FULL, phy_b5);
+ break;
+ case 1:
+ wlc_phy_a2_nphy(pi, &phy_b1[phy_b5], CAL_SOFT, phy_b5);
+ break;
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_papd_cal_cleanup_nphy(pi, &phy_b2);
+ }
+ }
+
+ if (NREV_LT(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_papd_cal_cleanup_nphy(pi, &phy_b2);
+ }
+
+ for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
+ int eps_offset = 0;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (pi->pubpi.radiorev == 3) {
+ eps_offset = -2;
+ } else if (pi->pubpi.radiorev == 5) {
+ eps_offset = 3;
+ } else {
+ eps_offset = -1;
+ }
+ } else {
+ eps_offset = 2;
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ phy_b8 = phy_b1[phy_b5].gains.pad[phy_b5];
+ phy_b10 = 0;
+ if ((pi->pubpi.radiorev == 3) ||
+ (pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+ phy_b12 =
+ -
+ (nphy_papd_padgain_dlt_2g_2057rev3n4
+ [phy_b8]
+ + 1) / 2;
+ phy_b10 = -1;
+ } else if (pi->pubpi.radiorev == 5) {
+ phy_b12 =
+ -(nphy_papd_padgain_dlt_2g_2057rev5
+ [phy_b8]
+ + 1) / 2;
+ } else if ((pi->pubpi.radiorev == 7) ||
+ (pi->pubpi.radiorev == 8)) {
+ phy_b12 =
+ -(nphy_papd_padgain_dlt_2g_2057rev7
+ [phy_b8]
+ + 1) / 2;
+ }
+ } else {
+ phy_b7 = phy_b1[phy_b5].gains.pga[phy_b5];
+ if ((pi->pubpi.radiorev == 3) ||
+ (pi->pubpi.radiorev == 4) ||
+ (pi->pubpi.radiorev == 6)) {
+ phy_b11 =
+ -(nphy_papd_pgagain_dlt_5g_2057
+ [phy_b7]
+ + 1) / 2;
+ } else if ((pi->pubpi.radiorev == 7)
+ || (pi->pubpi.radiorev == 8)) {
+ phy_b11 =
+ -(nphy_papd_pgagain_dlt_5g_2057rev7
+ [phy_b7]
+ + 1) / 2;
+ }
+
+ phy_b10 = -9;
+ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ phy_b6 =
+ -60 + 27 + eps_offset + phy_b12 + phy_b10;
+ } else {
+ phy_b6 =
+ -60 + 27 + eps_offset + phy_b11 + phy_b10;
+ }
+
+ mod_phy_reg(pi, (phy_b5 == PHY_CORE_0) ? 0x298 :
+ 0x29c, (0x1ff << 7), (phy_b6) << 7);
+
+ pi->nphy_papd_epsilon_offset[phy_b5] = phy_b6;
+ } else {
+ if (NREV_LT(pi->pubpi.phy_rev, 5)) {
+ eps_offset = 4;
+ } else {
+ eps_offset = 2;
+ }
+
+ phy_b7 = 15 - ((phy_b1[phy_b5].index) >> 3);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ phy_b11 =
+ -(nphy_papd_pga_gain_delta_ipa_2g[phy_b7] +
+ 1) / 2;
+ phy_b10 = 0;
+ } else {
+ phy_b11 =
+ -(nphy_papd_pga_gain_delta_ipa_5g[phy_b7] +
+ 1) / 2;
+ phy_b10 = -9;
+ }
+
+ phy_b6 = -60 + 27 + eps_offset + phy_b11 + phy_b10;
+
+ mod_phy_reg(pi, (phy_b5 == PHY_CORE_0) ? 0x298 :
+ 0x29c, (0x1ff << 7), (phy_b6) << 7);
+
+ pi->nphy_papd_epsilon_offset[phy_b5] = phy_b6;
+ }
+ }
+
+ mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
+
+ mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 6)) {
+ mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 13), (0) << 13);
+
+ mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 13), (0) << 13);
+
+ } else {
+ mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 11), (0) << 11);
+
+ mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x2a3 :
+ 0x2a4, (0x1 << 11), (0) << 11);
+
+ }
+ pi->nphy_papdcomp = NPHY_PAPD_COMP_ON;
+
+ write_phy_reg(pi, 0x01, phy_b9);
+
+ wlc_phy_ipa_set_tx_digi_filts_nphy(pi);
+
+ wlc_phy_txpwrctrl_enable_nphy(pi, phy_b4);
+ if (phy_b4 == PHY_TPC_HW_OFF) {
+ wlc_phy_txpwr_index_nphy(pi, (1 << 0),
+ (s8) (pi->nphy_txpwrindex[0].
+ index_internal), false);
+ wlc_phy_txpwr_index_nphy(pi, (1 << 1),
+ (s8) (pi->nphy_txpwrindex[1].
+ index_internal), false);
+ }
+
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+
+ if (!phy_b3) {
+ wlapi_enable_mac(pi->sh->physhim);
+ }
+}
+
+void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi)
+{
+ uint core;
+ u32 txgain;
+ u16 rad_gain, dac_gain, bbmult, m1m2;
+ u8 txpi[2], chan_freq_range;
+ s32 rfpwr_offset;
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ if (pi->sh->sromrev < 4) {
+ txpi[0] = txpi[1] = 72;
+ } else {
+
+ chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
+ switch (chan_freq_range) {
+ case WL_CHAN_FREQ_RANGE_2G:
+ txpi[0] = pi->nphy_txpid2g[0];
+ txpi[1] = pi->nphy_txpid2g[1];
+ break;
+ case WL_CHAN_FREQ_RANGE_5GL:
+ txpi[0] = pi->nphy_txpid5gl[0];
+ txpi[1] = pi->nphy_txpid5gl[1];
+ break;
+ case WL_CHAN_FREQ_RANGE_5GM:
+ txpi[0] = pi->nphy_txpid5g[0];
+ txpi[1] = pi->nphy_txpid5g[1];
+ break;
+ case WL_CHAN_FREQ_RANGE_5GH:
+ txpi[0] = pi->nphy_txpid5gh[0];
+ txpi[1] = pi->nphy_txpid5gh[1];
+ break;
+ default:
+ txpi[0] = txpi[1] = 91;
+ break;
+ }
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ txpi[0] = txpi[1] = 30;
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ txpi[0] = txpi[1] = 40;
+ }
+
+ if (NREV_LT(pi->pubpi.phy_rev, 7)) {
+
+ if ((txpi[0] < 40) || (txpi[0] > 100) ||
+ (txpi[1] < 40) || (txpi[1] > 100))
+ txpi[0] = txpi[1] = 91;
+ }
+
+ pi->nphy_txpwrindex[PHY_CORE_0].index_internal = txpi[0];
+ pi->nphy_txpwrindex[PHY_CORE_1].index_internal = txpi[1];
+ pi->nphy_txpwrindex[PHY_CORE_0].index_internal_save = txpi[0];
+ pi->nphy_txpwrindex[PHY_CORE_1].index_internal_save = txpi[1];
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (PHY_IPA(pi)) {
+ u32 *tx_gaintbl =
+ wlc_phy_get_ipa_gaintbl_nphy(pi);
+ txgain = tx_gaintbl[txpi[core]];
+ } else {
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if NREV_IS
+ (pi->pubpi.phy_rev, 3) {
+ txgain =
+ nphy_tpc_5GHz_txgain_rev3
+ [txpi[core]];
+ } else if NREV_IS
+ (pi->pubpi.phy_rev, 4) {
+ txgain =
+ (pi->srom_fem5g.extpagain ==
+ 3) ?
+ nphy_tpc_5GHz_txgain_HiPwrEPA
+ [txpi[core]] :
+ nphy_tpc_5GHz_txgain_rev4
+ [txpi[core]];
+ } else {
+ txgain =
+ nphy_tpc_5GHz_txgain_rev5
+ [txpi[core]];
+ }
+ } else {
+ if (NREV_GE(pi->pubpi.phy_rev, 5) &&
+ (pi->srom_fem2g.extpagain == 3)) {
+ txgain =
+ nphy_tpc_txgain_HiPwrEPA
+ [txpi[core]];
+ } else {
+ txgain =
+ nphy_tpc_txgain_rev3[txpi
+ [core]];
+ }
+ }
+ }
+ } else {
+ txgain = nphy_tpc_txgain[txpi[core]];
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ rad_gain = (txgain >> 16) & ((1 << (32 - 16 + 1)) - 1);
+ } else {
+ rad_gain = (txgain >> 16) & ((1 << (28 - 16 + 1)) - 1);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ dac_gain = (txgain >> 8) & ((1 << (10 - 8 + 1)) - 1);
+ } else {
+ dac_gain = (txgain >> 8) & ((1 << (13 - 8 + 1)) - 1);
+ }
+ bbmult = (txgain >> 0) & ((1 << (7 - 0 + 1)) - 1);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
+ 0xa5), (0x1 << 8), (0x1 << 8));
+ } else {
+ mod_phy_reg(pi, 0xa5, (0x1 << 14), (0x1 << 14));
+ }
+ write_phy_reg(pi, (core == PHY_CORE_0) ? 0xaa : 0xab, dac_gain);
+
+ wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
+ &rad_gain);
+
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
+ m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
+ m1m2 |= ((core == PHY_CORE_0) ? (bbmult << 8) : (bbmult << 0));
+ wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
+
+ if (PHY_IPA(pi)) {
+ wlc_phy_table_read_nphy(pi,
+ (core ==
+ PHY_CORE_0 ?
+ NPHY_TBL_ID_CORE1TXPWRCTL :
+ NPHY_TBL_ID_CORE2TXPWRCTL), 1,
+ 576 + txpi[core], 32,
+ &rfpwr_offset);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1ff << 4),
+ ((s16) rfpwr_offset) << 4);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 2), (1) << 2);
+
+ }
+ }
+
+ and_phy_reg(pi, 0xbf, (u16) (~(0x1f << 0)));
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+static void
+wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max, u16 *pwr_offset,
+ u8 tmp_max_pwr, u8 rate_start,
+ u8 rate_end)
+{
+ u8 rate;
+ u8 word_num, nibble_num;
+ u8 tmp_nibble;
+
+ for (rate = rate_start; rate <= rate_end; rate++) {
+ word_num = (rate - rate_start) >> 2;
+ nibble_num = (rate - rate_start) & 0x3;
+ tmp_nibble = (pwr_offset[word_num] >> 4 * nibble_num) & 0xf;
+
+ srom_max[rate] = tmp_max_pwr - 2 * tmp_nibble;
+ }
+}
+
+static void
+wlc_phy_txpwr_nphy_po_apply(u8 *srom_max, u8 pwr_offset,
+ u8 rate_start, u8 rate_end)
+{
+ u8 rate;
+
+ for (rate = rate_start; rate <= rate_end; rate++) {
+ srom_max[rate] -= 2 * pwr_offset;
+ }
+}
+
+void
+wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
+ u8 rate_mcs_end, u8 rate_ofdm_start)
+{
+ u8 rate1, rate2;
+
+ rate2 = rate_ofdm_start;
+ for (rate1 = rate_mcs_start; rate1 <= rate_mcs_end - 1; rate1++) {
+ power[rate1] = power[rate2];
+ rate2 += (rate1 == rate_mcs_start) ? 2 : 1;
+ }
+ power[rate_mcs_end] = power[rate_mcs_end - 1];
+}
+
+void
+wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, u8 rate_ofdm_start,
+ u8 rate_ofdm_end, u8 rate_mcs_start)
+{
+ u8 rate1, rate2;
+
+ for (rate1 = rate_ofdm_start, rate2 = rate_mcs_start;
+ rate1 <= rate_ofdm_end; rate1++, rate2++) {
+ power[rate1] = power[rate2];
+ if (rate1 == rate_ofdm_start)
+ power[++rate1] = power[rate2];
+ }
+}
+
+void wlc_phy_txpwr_apply_nphy(phy_info_t *pi)
+{
+ uint rate1, rate2, band_num;
+ u8 tmp_bw40po = 0, tmp_cddpo = 0, tmp_stbcpo = 0;
+ u8 tmp_max_pwr = 0;
+ u16 pwr_offsets1[2], *pwr_offsets2 = NULL;
+ u8 *tx_srom_max_rate = NULL;
+
+ for (band_num = 0; band_num < (CH_2G_GROUP + CH_5G_GROUP); band_num++) {
+ switch (band_num) {
+ case 0:
+
+ tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_2g,
+ pi->nphy_pwrctrl_info[1].max_pwr_2g);
+
+ pwr_offsets1[0] = pi->cck2gpo;
+ wlc_phy_txpwr_nphy_srom_convert(pi->tx_srom_max_rate_2g,
+ pwr_offsets1,
+ tmp_max_pwr,
+ TXP_FIRST_CCK,
+ TXP_LAST_CCK);
+
+ pwr_offsets1[0] = (u16) (pi->ofdm2gpo & 0xffff);
+ pwr_offsets1[1] =
+ (u16) (pi->ofdm2gpo >> 16) & 0xffff;
+
+ pwr_offsets2 = pi->mcs2gpo;
+
+ tmp_cddpo = pi->cdd2gpo;
+ tmp_stbcpo = pi->stbc2gpo;
+ tmp_bw40po = pi->bw402gpo;
+
+ tx_srom_max_rate = pi->tx_srom_max_rate_2g;
+ break;
+ case 1:
+
+ tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gm,
+ pi->nphy_pwrctrl_info[1].max_pwr_5gm);
+
+ pwr_offsets1[0] = (u16) (pi->ofdm5gpo & 0xffff);
+ pwr_offsets1[1] =
+ (u16) (pi->ofdm5gpo >> 16) & 0xffff;
+
+ pwr_offsets2 = pi->mcs5gpo;
+
+ tmp_cddpo = pi->cdd5gpo;
+ tmp_stbcpo = pi->stbc5gpo;
+ tmp_bw40po = pi->bw405gpo;
+
+ tx_srom_max_rate = pi->tx_srom_max_rate_5g_mid;
+ break;
+ case 2:
+
+ tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gl,
+ pi->nphy_pwrctrl_info[1].max_pwr_5gl);
+
+ pwr_offsets1[0] = (u16) (pi->ofdm5glpo & 0xffff);
+ pwr_offsets1[1] =
+ (u16) (pi->ofdm5glpo >> 16) & 0xffff;
+
+ pwr_offsets2 = pi->mcs5glpo;
+
+ tmp_cddpo = pi->cdd5glpo;
+ tmp_stbcpo = pi->stbc5glpo;
+ tmp_bw40po = pi->bw405glpo;
+
+ tx_srom_max_rate = pi->tx_srom_max_rate_5g_low;
+ break;
+ case 3:
+
+ tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gh,
+ pi->nphy_pwrctrl_info[1].max_pwr_5gh);
+
+ pwr_offsets1[0] = (u16) (pi->ofdm5ghpo & 0xffff);
+ pwr_offsets1[1] =
+ (u16) (pi->ofdm5ghpo >> 16) & 0xffff;
+
+ pwr_offsets2 = pi->mcs5ghpo;
+
+ tmp_cddpo = pi->cdd5ghpo;
+ tmp_stbcpo = pi->stbc5ghpo;
+ tmp_bw40po = pi->bw405ghpo;
+
+ tx_srom_max_rate = pi->tx_srom_max_rate_5g_hi;
+ break;
+ }
+
+ wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets1,
+ tmp_max_pwr, TXP_FIRST_OFDM,
+ TXP_LAST_OFDM);
+
+ wlc_phy_ofdm_to_mcs_powers_nphy(tx_srom_max_rate,
+ TXP_FIRST_MCS_20_SISO,
+ TXP_LAST_MCS_20_SISO,
+ TXP_FIRST_OFDM);
+
+ wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2,
+ tmp_max_pwr,
+ TXP_FIRST_MCS_20_CDD,
+ TXP_LAST_MCS_20_CDD);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, tmp_cddpo,
+ TXP_FIRST_MCS_20_CDD,
+ TXP_LAST_MCS_20_CDD);
+ }
+
+ wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
+ TXP_FIRST_OFDM_20_CDD,
+ TXP_LAST_OFDM_20_CDD,
+ TXP_FIRST_MCS_20_CDD);
+
+ wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2,
+ tmp_max_pwr,
+ TXP_FIRST_MCS_20_STBC,
+ TXP_LAST_MCS_20_STBC);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
+ tmp_stbcpo,
+ TXP_FIRST_MCS_20_STBC,
+ TXP_LAST_MCS_20_STBC);
+ }
+
+ wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
+ &pwr_offsets2[2], tmp_max_pwr,
+ TXP_FIRST_MCS_20_SDM,
+ TXP_LAST_MCS_20_SDM);
+
+ if (NPHY_IS_SROM_REINTERPRET) {
+
+ wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
+ &pwr_offsets2[4],
+ tmp_max_pwr,
+ TXP_FIRST_MCS_40_SISO,
+ TXP_LAST_MCS_40_SISO);
+
+ wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
+ TXP_FIRST_OFDM_40_SISO,
+ TXP_LAST_OFDM_40_SISO,
+ TXP_FIRST_MCS_40_SISO);
+
+ wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
+ &pwr_offsets2[4],
+ tmp_max_pwr,
+ TXP_FIRST_MCS_40_CDD,
+ TXP_LAST_MCS_40_CDD);
+
+ wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, tmp_cddpo,
+ TXP_FIRST_MCS_40_CDD,
+ TXP_LAST_MCS_40_CDD);
+
+ wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
+ TXP_FIRST_OFDM_40_CDD,
+ TXP_LAST_OFDM_40_CDD,
+ TXP_FIRST_MCS_40_CDD);
+
+ wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
+ &pwr_offsets2[4],
+ tmp_max_pwr,
+ TXP_FIRST_MCS_40_STBC,
+ TXP_LAST_MCS_40_STBC);
+
+ wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
+ tmp_stbcpo,
+ TXP_FIRST_MCS_40_STBC,
+ TXP_LAST_MCS_40_STBC);
+
+ wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
+ &pwr_offsets2[6],
+ tmp_max_pwr,
+ TXP_FIRST_MCS_40_SDM,
+ TXP_LAST_MCS_40_SDM);
+ } else {
+
+ for (rate1 = TXP_FIRST_OFDM_40_SISO, rate2 =
+ TXP_FIRST_OFDM; rate1 <= TXP_LAST_MCS_40_SDM;
+ rate1++, rate2++)
+ tx_srom_max_rate[rate1] =
+ tx_srom_max_rate[rate2];
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
+ tmp_bw40po,
+ TXP_FIRST_OFDM_40_SISO,
+ TXP_LAST_MCS_40_SDM);
+ }
+
+ tx_srom_max_rate[TXP_MCS_32] =
+ tx_srom_max_rate[TXP_FIRST_MCS_40_CDD];
+ }
+
+ return;
+}
+
+static void wlc_phy_txpwr_srom_read_ppr_nphy(phy_info_t *pi)
+{
+ u16 bw40po, cddpo, stbcpo, bwduppo;
+ uint band_num;
+
+ if (pi->sh->sromrev >= 9) {
+
+ return;
+ }
+
+ bw40po = (u16) PHY_GETINTVAR(pi, "bw40po");
+ pi->bw402gpo = bw40po & 0xf;
+ pi->bw405gpo = (bw40po & 0xf0) >> 4;
+ pi->bw405glpo = (bw40po & 0xf00) >> 8;
+ pi->bw405ghpo = (bw40po & 0xf000) >> 12;
+
+ cddpo = (u16) PHY_GETINTVAR(pi, "cddpo");
+ pi->cdd2gpo = cddpo & 0xf;
+ pi->cdd5gpo = (cddpo & 0xf0) >> 4;
+ pi->cdd5glpo = (cddpo & 0xf00) >> 8;
+ pi->cdd5ghpo = (cddpo & 0xf000) >> 12;
+
+ stbcpo = (u16) PHY_GETINTVAR(pi, "stbcpo");
+ pi->stbc2gpo = stbcpo & 0xf;
+ pi->stbc5gpo = (stbcpo & 0xf0) >> 4;
+ pi->stbc5glpo = (stbcpo & 0xf00) >> 8;
+ pi->stbc5ghpo = (stbcpo & 0xf000) >> 12;
+
+ bwduppo = (u16) PHY_GETINTVAR(pi, "bwduppo");
+ pi->bwdup2gpo = bwduppo & 0xf;
+ pi->bwdup5gpo = (bwduppo & 0xf0) >> 4;
+ pi->bwdup5glpo = (bwduppo & 0xf00) >> 8;
+ pi->bwdup5ghpo = (bwduppo & 0xf000) >> 12;
+
+ for (band_num = 0; band_num < (CH_2G_GROUP + CH_5G_GROUP); band_num++) {
+ switch (band_num) {
+ case 0:
+
+ pi->nphy_txpid2g[PHY_CORE_0] =
+ (u8) PHY_GETINTVAR(pi, "txpid2ga0");
+ pi->nphy_txpid2g[PHY_CORE_1] =
+ (u8) PHY_GETINTVAR(pi, "txpid2ga1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g =
+ (s8) PHY_GETINTVAR(pi, "maxp2ga0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_2g =
+ (s8) PHY_GETINTVAR(pi, "maxp2ga1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_a1 =
+ (s16) PHY_GETINTVAR(pi, "pa2gw0a0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_a1 =
+ (s16) PHY_GETINTVAR(pi, "pa2gw0a1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b0 =
+ (s16) PHY_GETINTVAR(pi, "pa2gw1a0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b0 =
+ (s16) PHY_GETINTVAR(pi, "pa2gw1a1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b1 =
+ (s16) PHY_GETINTVAR(pi, "pa2gw2a0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b1 =
+ (s16) PHY_GETINTVAR(pi, "pa2gw2a1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_2g =
+ (s8) PHY_GETINTVAR(pi, "itt2ga0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g =
+ (s8) PHY_GETINTVAR(pi, "itt2ga1");
+
+ pi->cck2gpo = (u16) PHY_GETINTVAR(pi, "cck2gpo");
+
+ pi->ofdm2gpo = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
+
+ pi->mcs2gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs2gpo0");
+ pi->mcs2gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs2gpo1");
+ pi->mcs2gpo[2] = (u16) PHY_GETINTVAR(pi, "mcs2gpo2");
+ pi->mcs2gpo[3] = (u16) PHY_GETINTVAR(pi, "mcs2gpo3");
+ pi->mcs2gpo[4] = (u16) PHY_GETINTVAR(pi, "mcs2gpo4");
+ pi->mcs2gpo[5] = (u16) PHY_GETINTVAR(pi, "mcs2gpo5");
+ pi->mcs2gpo[6] = (u16) PHY_GETINTVAR(pi, "mcs2gpo6");
+ pi->mcs2gpo[7] = (u16) PHY_GETINTVAR(pi, "mcs2gpo7");
+ break;
+ case 1:
+
+ pi->nphy_txpid5g[PHY_CORE_0] =
+ (u8) PHY_GETINTVAR(pi, "txpid5ga0");
+ pi->nphy_txpid5g[PHY_CORE_1] =
+ (u8) PHY_GETINTVAR(pi, "txpid5ga1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm =
+ (s8) PHY_GETINTVAR(pi, "maxp5ga0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm =
+ (s8) PHY_GETINTVAR(pi, "maxp5ga1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_a1 =
+ (s16) PHY_GETINTVAR(pi, "pa5gw0a0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_a1 =
+ (s16) PHY_GETINTVAR(pi, "pa5gw0a1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b0 =
+ (s16) PHY_GETINTVAR(pi, "pa5gw1a0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b0 =
+ (s16) PHY_GETINTVAR(pi, "pa5gw1a1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b1 =
+ (s16) PHY_GETINTVAR(pi, "pa5gw2a0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b1 =
+ (s16) PHY_GETINTVAR(pi, "pa5gw2a1");
+ pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_5gm =
+ (s8) PHY_GETINTVAR(pi, "itt5ga0");
+ pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
+ (s8) PHY_GETINTVAR(pi, "itt5ga1");
+
+ pi->ofdm5gpo = (u32) PHY_GETINTVAR(pi, "ofdm5gpo");
+
+ pi->mcs5gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs5gpo0");
+ pi->mcs5gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs5gpo1");
+ pi->mcs5gpo[2] = (u16) PHY_GETINTVAR(pi, "mcs5gpo2");
+ pi->mcs5gpo[3] = (u16) PHY_GETINTVAR(pi, "mcs5gpo3");
+ pi->mcs5gpo[4] = (u16) PHY_GETINTVAR(pi, "mcs5gpo4");
+ pi->mcs5gpo[5] = (u16) PHY_GETINTVAR(pi, "mcs5gpo5");
+ pi->mcs5gpo[6] = (u16) PHY_GETINTVAR(pi, "mcs5gpo6");
+ pi->mcs5gpo[7] = (u16) PHY_GETINTVAR(pi, "mcs5gpo7");
+ break;
+ case 2:
+
+ pi->nphy_txpid5gl[0] =
+ (u8) PHY_GETINTVAR(pi, "txpid5gla0");
+ pi->nphy_txpid5gl[1] =
+ (u8) PHY_GETINTVAR(pi, "txpid5gla1");
+ pi->nphy_pwrctrl_info[0].max_pwr_5gl =
+ (s8) PHY_GETINTVAR(pi, "maxp5gla0");
+ pi->nphy_pwrctrl_info[1].max_pwr_5gl =
+ (s8) PHY_GETINTVAR(pi, "maxp5gla1");
+ pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 =
+ (s16) PHY_GETINTVAR(pi, "pa5glw0a0");
+ pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 =
+ (s16) PHY_GETINTVAR(pi, "pa5glw0a1");
+ pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 =
+ (s16) PHY_GETINTVAR(pi, "pa5glw1a0");
+ pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 =
+ (s16) PHY_GETINTVAR(pi, "pa5glw1a1");
+ pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 =
+ (s16) PHY_GETINTVAR(pi, "pa5glw2a0");
+ pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 =
+ (s16) PHY_GETINTVAR(pi, "pa5glw2a1");
+ pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
+ pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
+
+ pi->ofdm5glpo = (u32) PHY_GETINTVAR(pi, "ofdm5glpo");
+
+ pi->mcs5glpo[0] =
+ (u16) PHY_GETINTVAR(pi, "mcs5glpo0");
+ pi->mcs5glpo[1] =
+ (u16) PHY_GETINTVAR(pi, "mcs5glpo1");
+ pi->mcs5glpo[2] =
+ (u16) PHY_GETINTVAR(pi, "mcs5glpo2");
+ pi->mcs5glpo[3] =
+ (u16) PHY_GETINTVAR(pi, "mcs5glpo3");
+ pi->mcs5glpo[4] =
+ (u16) PHY_GETINTVAR(pi, "mcs5glpo4");
+ pi->mcs5glpo[5] =
+ (u16) PHY_GETINTVAR(pi, "mcs5glpo5");
+ pi->mcs5glpo[6] =
+ (u16) PHY_GETINTVAR(pi, "mcs5glpo6");
+ pi->mcs5glpo[7] =
+ (u16) PHY_GETINTVAR(pi, "mcs5glpo7");
+ break;
+ case 3:
+
+ pi->nphy_txpid5gh[0] =
+ (u8) PHY_GETINTVAR(pi, "txpid5gha0");
+ pi->nphy_txpid5gh[1] =
+ (u8) PHY_GETINTVAR(pi, "txpid5gha1");
+ pi->nphy_pwrctrl_info[0].max_pwr_5gh =
+ (s8) PHY_GETINTVAR(pi, "maxp5gha0");
+ pi->nphy_pwrctrl_info[1].max_pwr_5gh =
+ (s8) PHY_GETINTVAR(pi, "maxp5gha1");
+ pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 =
+ (s16) PHY_GETINTVAR(pi, "pa5ghw0a0");
+ pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 =
+ (s16) PHY_GETINTVAR(pi, "pa5ghw0a1");
+ pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 =
+ (s16) PHY_GETINTVAR(pi, "pa5ghw1a0");
+ pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 =
+ (s16) PHY_GETINTVAR(pi, "pa5ghw1a1");
+ pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 =
+ (s16) PHY_GETINTVAR(pi, "pa5ghw2a0");
+ pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 =
+ (s16) PHY_GETINTVAR(pi, "pa5ghw2a1");
+ pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
+ pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
+
+ pi->ofdm5ghpo = (u32) PHY_GETINTVAR(pi, "ofdm5ghpo");
+
+ pi->mcs5ghpo[0] =
+ (u16) PHY_GETINTVAR(pi, "mcs5ghpo0");
+ pi->mcs5ghpo[1] =
+ (u16) PHY_GETINTVAR(pi, "mcs5ghpo1");
+ pi->mcs5ghpo[2] =
+ (u16) PHY_GETINTVAR(pi, "mcs5ghpo2");
+ pi->mcs5ghpo[3] =
+ (u16) PHY_GETINTVAR(pi, "mcs5ghpo3");
+ pi->mcs5ghpo[4] =
+ (u16) PHY_GETINTVAR(pi, "mcs5ghpo4");
+ pi->mcs5ghpo[5] =
+ (u16) PHY_GETINTVAR(pi, "mcs5ghpo5");
+ pi->mcs5ghpo[6] =
+ (u16) PHY_GETINTVAR(pi, "mcs5ghpo6");
+ pi->mcs5ghpo[7] =
+ (u16) PHY_GETINTVAR(pi, "mcs5ghpo7");
+ break;
+ }
+ }
+
+ wlc_phy_txpwr_apply_nphy(pi);
+}
+
+static bool wlc_phy_txpwr_srom_read_nphy(phy_info_t *pi)
+{
+
+ pi->antswitch = (u8) PHY_GETINTVAR(pi, "antswitch");
+ pi->aa2g = (u8) PHY_GETINTVAR(pi, "aa2g");
+ pi->aa5g = (u8) PHY_GETINTVAR(pi, "aa5g");
+
+ pi->srom_fem2g.tssipos = (u8) PHY_GETINTVAR(pi, "tssipos2g");
+ pi->srom_fem2g.extpagain = (u8) PHY_GETINTVAR(pi, "extpagain2g");
+ pi->srom_fem2g.pdetrange = (u8) PHY_GETINTVAR(pi, "pdetrange2g");
+ pi->srom_fem2g.triso = (u8) PHY_GETINTVAR(pi, "triso2g");
+ pi->srom_fem2g.antswctrllut = (u8) PHY_GETINTVAR(pi, "antswctl2g");
+
+ pi->srom_fem5g.tssipos = (u8) PHY_GETINTVAR(pi, "tssipos5g");
+ pi->srom_fem5g.extpagain = (u8) PHY_GETINTVAR(pi, "extpagain5g");
+ pi->srom_fem5g.pdetrange = (u8) PHY_GETINTVAR(pi, "pdetrange5g");
+ pi->srom_fem5g.triso = (u8) PHY_GETINTVAR(pi, "triso5g");
+ if (PHY_GETVAR(pi, "antswctl5g")) {
+
+ pi->srom_fem5g.antswctrllut =
+ (u8) PHY_GETINTVAR(pi, "antswctl5g");
+ } else {
+
+ pi->srom_fem5g.antswctrllut =
+ (u8) PHY_GETINTVAR(pi, "antswctl2g");
+ }
+
+ wlc_phy_txpower_ipa_upd(pi);
+
+ pi->phy_txcore_disable_temp = (s16) PHY_GETINTVAR(pi, "tempthresh");
+ if (pi->phy_txcore_disable_temp == 0) {
+ pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
+ }
+
+ pi->phy_tempsense_offset = (s8) PHY_GETINTVAR(pi, "tempoffset");
+ if (pi->phy_tempsense_offset != 0) {
+ if (pi->phy_tempsense_offset >
+ (NPHY_SROM_TEMPSHIFT + NPHY_SROM_MAXTEMPOFFSET)) {
+ pi->phy_tempsense_offset = NPHY_SROM_MAXTEMPOFFSET;
+ } else if (pi->phy_tempsense_offset < (NPHY_SROM_TEMPSHIFT +
+ NPHY_SROM_MINTEMPOFFSET)) {
+ pi->phy_tempsense_offset = NPHY_SROM_MINTEMPOFFSET;
+ } else {
+ pi->phy_tempsense_offset -= NPHY_SROM_TEMPSHIFT;
+ }
+ }
+
+ pi->phy_txcore_enable_temp =
+ pi->phy_txcore_disable_temp - PHY_HYSTERESIS_DELTATEMP;
+
+ pi->phycal_tempdelta = (u8) PHY_GETINTVAR(pi, "phycal_tempdelta");
+ if (pi->phycal_tempdelta > NPHY_CAL_MAXTEMPDELTA) {
+ pi->phycal_tempdelta = 0;
+ }
+
+ wlc_phy_txpwr_srom_read_ppr_nphy(pi);
+
+ return true;
+}
+
+void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi)
+{
+ u8 tx_pwr_ctrl_state;
+ wlc_phy_txpwr_limit_to_tbl_nphy(pi);
+ wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
+
+ tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
+
+ if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
+ wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
+ (void)R_REG(&pi->regs->maccontrol);
+ udelay(1);
+ }
+
+ wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
+
+ if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
+ wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
+}
+
+static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
+{
+ u32 idx;
+ u16 iqloCalbuf[7];
+ u32 iqcomp, locomp, curr_locomp;
+ s8 locomp_i, locomp_q;
+ s8 curr_locomp_i, curr_locomp_q;
+ u32 tbl_id, tbl_len, tbl_offset;
+ u32 regval[128];
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ wlc_phy_table_read_nphy(pi, 15, 7, 80, 16, iqloCalbuf);
+
+ tbl_len = 128;
+ tbl_offset = 320;
+ for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
+ tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
+ iqcomp =
+ (tbl_id ==
+ 26) ? (((u32) (iqloCalbuf[0] & 0x3ff)) << 10) |
+ (iqloCalbuf[1] & 0x3ff)
+ : (((u32) (iqloCalbuf[2] & 0x3ff)) << 10) |
+ (iqloCalbuf[3] & 0x3ff);
+
+ for (idx = 0; idx < tbl_len; idx++) {
+ regval[idx] = iqcomp;
+ }
+ wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
+ regval);
+ }
+
+ tbl_offset = 448;
+ for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
+ tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
+
+ locomp =
+ (u32) ((tbl_id == 26) ? iqloCalbuf[5] : iqloCalbuf[6]);
+ locomp_i = (s8) ((locomp >> 8) & 0xff);
+ locomp_q = (s8) ((locomp) & 0xff);
+ for (idx = 0; idx < tbl_len; idx++) {
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ curr_locomp_i = locomp_i;
+ curr_locomp_q = locomp_q;
+ } else {
+ curr_locomp_i = (s8) ((locomp_i *
+ nphy_tpc_loscale[idx] +
+ 128) >> 8);
+ curr_locomp_q =
+ (s8) ((locomp_q * nphy_tpc_loscale[idx] +
+ 128) >> 8);
+ }
+ curr_locomp = (u32) ((curr_locomp_i & 0xff) << 8);
+ curr_locomp |= (u32) (curr_locomp_q & 0xff);
+ regval[idx] = curr_locomp;
+ }
+ wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
+ regval);
+ }
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2)) {
+
+ wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX1, 0xFFFF);
+ wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX2, 0xFFFF);
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+static void wlc_phy_ipa_internal_tssi_setup_nphy(phy_info_t *pi)
+{
+ u8 core;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MASTER, 0x5);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MUX, 0xe);
+
+ if (pi->pubpi.radiorev != 5)
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX,
+ core, TSSIA, 0);
+
+ if (!NREV_IS(pi->pubpi.phy_rev, 7)) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX,
+ core, TSSIG, 0x1);
+ } else {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX,
+ core, TSSIG, 0x31);
+ }
+ } else {
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MASTER, 0x9);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TX_SSI_MUX, 0xc);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
+ TSSIG, 0);
+
+ if (pi->pubpi.radiorev != 5) {
+ if (!NREV_IS(pi->pubpi.phy_rev, 7)) {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057,
+ TX, core,
+ TSSIA, 0x1);
+ } else {
+
+ WRITE_RADIO_REG3(pi, RADIO_2057,
+ TX, core,
+ TSSIA, 0x31);
+ }
+ }
+ }
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_VCM_HG,
+ 0);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_IDAC,
+ 0);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM,
+ 0x3);
+ WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_MISC1,
+ 0x0);
+ }
+ } else {
+ WRITE_RADIO_SYN(pi, RADIO_2056, RESERVED_ADDR31,
+ (CHSPEC_IS2G(pi->radio_chanspec)) ? 0x128 :
+ 0x80);
+ WRITE_RADIO_SYN(pi, RADIO_2056, RESERVED_ADDR30, 0x0);
+ WRITE_RADIO_SYN(pi, RADIO_2056, GPIO_MASTER1, 0x29);
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, IQCAL_VCM_HG,
+ 0x0);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, IQCAL_IDAC,
+ 0x0);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_VCM,
+ 0x3);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TX_AMP_DET,
+ 0x0);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC1,
+ 0x8);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC2,
+ 0x0);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC3,
+ 0x0);
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ TX_SSI_MASTER, 0x5);
+
+ if (pi->pubpi.radiorev != 5)
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX,
+ core, TSSIA, 0x0);
+ if (NREV_GE(pi->pubpi.phy_rev, 5)) {
+
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX,
+ core, TSSIG, 0x31);
+ } else {
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX,
+ core, TSSIG, 0x11);
+ }
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ TX_SSI_MUX, 0xe);
+ } else {
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ TX_SSI_MASTER, 0x9);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ TSSIA, 0x31);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ TSSIG, 0x0);
+ WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
+ TX_SSI_MUX, 0xc);
+ }
+ }
+ }
+}
+
+static void wlc_phy_txpwrctrl_idle_tssi_nphy(phy_info_t *pi)
+{
+ s32 rssi_buf[4];
+ s32 int_val;
+
+ if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi) || PHY_MUTED(pi))
+
+ return;
+
+ if (PHY_IPA(pi)) {
+ wlc_phy_ipa_internal_tssi_setup_nphy(pi);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
+ 0, 0x3, 0,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 3, 0);
+ }
+
+ wlc_phy_stopplayback_nphy(pi);
+
+ wlc_phy_tx_tone_nphy(pi, 4000, 0, 0, 0, false);
+
+ udelay(20);
+ int_val =
+ wlc_phy_poll_rssi_nphy(pi, (u8) NPHY_RSSI_SEL_TSSI_2G, rssi_buf,
+ 1);
+ wlc_phy_stopplayback_nphy(pi);
+ wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_OFF, 0);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
+ 0, 0x3, 1,
+ NPHY_REV7_RFCTRLOVERRIDE_ID0);
+ } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 3, 1);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_2g =
+ (u8) ((int_val >> 24) & 0xff);
+ pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_5g =
+ (u8) ((int_val >> 24) & 0xff);
+
+ pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_2g =
+ (u8) ((int_val >> 8) & 0xff);
+ pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_5g =
+ (u8) ((int_val >> 8) & 0xff);
+ } else {
+ pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_2g =
+ (u8) ((int_val >> 24) & 0xff);
+
+ pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_2g =
+ (u8) ((int_val >> 8) & 0xff);
+
+ pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_5g =
+ (u8) ((int_val >> 16) & 0xff);
+ pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_5g =
+ (u8) ((int_val) & 0xff);
+ }
+
+}
+
+static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
+{
+ u32 idx;
+ s16 a1[2], b0[2], b1[2];
+ s8 target_pwr_qtrdbm[2];
+ s32 num, den, pwr_est;
+ u8 chan_freq_range;
+ u8 idle_tssi[2];
+ u32 tbl_id, tbl_len, tbl_offset;
+ u32 regval[64];
+ u8 core;
+
+ if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
+ wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
+ (void)R_REG(&pi->regs->maccontrol);
+ udelay(1);
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ or_phy_reg(pi, 0x122, (0x1 << 0));
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ and_phy_reg(pi, 0x1e7, (u16) (~(0x1 << 15)));
+ } else {
+
+ or_phy_reg(pi, 0x1e7, (0x1 << 15));
+ }
+
+ if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
+ wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
+
+ if (pi->sh->sromrev < 4) {
+ idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
+ idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
+ target_pwr_qtrdbm[0] = 13 * 4;
+ target_pwr_qtrdbm[1] = 13 * 4;
+ a1[0] = -424;
+ a1[1] = -424;
+ b0[0] = 5612;
+ b0[1] = 5612;
+ b1[1] = -1393;
+ b1[0] = -1393;
+ } else {
+
+ chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
+ switch (chan_freq_range) {
+ case WL_CHAN_FREQ_RANGE_2G:
+ idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
+ idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
+ target_pwr_qtrdbm[0] =
+ pi->nphy_pwrctrl_info[0].max_pwr_2g;
+ target_pwr_qtrdbm[1] =
+ pi->nphy_pwrctrl_info[1].max_pwr_2g;
+ a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_a1;
+ a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_a1;
+ b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b0;
+ b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b0;
+ b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b1;
+ b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b1;
+ break;
+ case WL_CHAN_FREQ_RANGE_5GL:
+ idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
+ idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
+ target_pwr_qtrdbm[0] =
+ pi->nphy_pwrctrl_info[0].max_pwr_5gl;
+ target_pwr_qtrdbm[1] =
+ pi->nphy_pwrctrl_info[1].max_pwr_5gl;
+ a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1;
+ a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1;
+ b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0;
+ b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0;
+ b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1;
+ b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1;
+ break;
+ case WL_CHAN_FREQ_RANGE_5GM:
+ idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
+ idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
+ target_pwr_qtrdbm[0] =
+ pi->nphy_pwrctrl_info[0].max_pwr_5gm;
+ target_pwr_qtrdbm[1] =
+ pi->nphy_pwrctrl_info[1].max_pwr_5gm;
+ a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_a1;
+ a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_a1;
+ b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b0;
+ b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b0;
+ b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b1;
+ b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b1;
+ break;
+ case WL_CHAN_FREQ_RANGE_5GH:
+ idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
+ idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
+ target_pwr_qtrdbm[0] =
+ pi->nphy_pwrctrl_info[0].max_pwr_5gh;
+ target_pwr_qtrdbm[1] =
+ pi->nphy_pwrctrl_info[1].max_pwr_5gh;
+ a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1;
+ a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1;
+ b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0;
+ b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0;
+ b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1;
+ b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1;
+ break;
+ default:
+ idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
+ idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
+ target_pwr_qtrdbm[0] = 13 * 4;
+ target_pwr_qtrdbm[1] = 13 * 4;
+ a1[0] = -424;
+ a1[1] = -424;
+ b0[0] = 5612;
+ b0[1] = 5612;
+ b1[1] = -1393;
+ b1[0] = -1393;
+ break;
+ }
+ }
+
+ target_pwr_qtrdbm[0] = (s8) pi->tx_power_max;
+ target_pwr_qtrdbm[1] = (s8) pi->tx_power_max;
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if (pi->srom_fem2g.tssipos) {
+ or_phy_reg(pi, 0x1e9, (0x1 << 14));
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ for (core = 0; core <= 1; core++) {
+ if (PHY_IPA(pi)) {
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ WRITE_RADIO_REG3(pi, RADIO_2057,
+ TX, core,
+ TX_SSI_MUX,
+ 0xe);
+ } else {
+ WRITE_RADIO_REG3(pi, RADIO_2057,
+ TX, core,
+ TX_SSI_MUX,
+ 0xc);
+ }
+ } else {
+ }
+ }
+ } else {
+ if (PHY_IPA(pi)) {
+
+ write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
+ RADIO_2056_TX0,
+ (CHSPEC_IS5G
+ (pi->
+ radio_chanspec)) ? 0xc : 0xe);
+ write_radio_reg(pi,
+ RADIO_2056_TX_TX_SSI_MUX |
+ RADIO_2056_TX1,
+ (CHSPEC_IS5G
+ (pi->
+ radio_chanspec)) ? 0xc : 0xe);
+ } else {
+
+ write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
+ RADIO_2056_TX0, 0x11);
+ write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
+ RADIO_2056_TX1, 0x11);
+ }
+ }
+ }
+
+ if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
+ wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
+ (void)R_REG(&pi->regs->maccontrol);
+ udelay(1);
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ mod_phy_reg(pi, 0x1e7, (0x7f << 0),
+ (NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 << 0));
+ } else {
+ mod_phy_reg(pi, 0x1e7, (0x7f << 0),
+ (NPHY_TxPwrCtrlCmd_pwrIndex_init << 0));
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ mod_phy_reg(pi, 0x222, (0xff << 0),
+ (NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 << 0));
+ } else if (NREV_GT(pi->pubpi.phy_rev, 1)) {
+ mod_phy_reg(pi, 0x222, (0xff << 0),
+ (NPHY_TxPwrCtrlCmd_pwrIndex_init << 0));
+ }
+
+ if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
+ wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
+
+ write_phy_reg(pi, 0x1e8, (0x3 << 8) | (240 << 0));
+
+ write_phy_reg(pi, 0x1e9,
+ (1 << 15) | (idle_tssi[0] << 0) | (idle_tssi[1] << 8));
+
+ write_phy_reg(pi, 0x1ea,
+ (target_pwr_qtrdbm[0] << 0) |
+ (target_pwr_qtrdbm[1] << 8));
+
+ tbl_len = 64;
+ tbl_offset = 0;
+ for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
+ tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
+
+ for (idx = 0; idx < tbl_len; idx++) {
+ num =
+ 8 * (16 * b0[tbl_id - 26] + b1[tbl_id - 26] * idx);
+ den = 32768 + a1[tbl_id - 26] * idx;
+ pwr_est = max(((4 * num + den / 2) / den), -8);
+ if (NREV_LT(pi->pubpi.phy_rev, 3)) {
+ if (idx <=
+ (uint) (31 - idle_tssi[tbl_id - 26] + 1))
+ pwr_est =
+ max(pwr_est,
+ target_pwr_qtrdbm[tbl_id - 26] +
+ 1);
+ }
+ regval[idx] = (u32) pwr_est;
+ }
+ wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
+ regval);
+ }
+
+ wlc_phy_txpwr_limit_to_tbl_nphy(pi);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 84, 64, 8,
+ pi->adj_pwr_tbl_nphy);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 84, 64, 8,
+ pi->adj_pwr_tbl_nphy);
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+static bool wlc_phy_txpwr_ison_nphy(phy_info_t *pi)
+{
+ return read_phy_reg((pi), 0x1e7) & ((0x1 << 15) |
+ (0x1 << 14) | (0x1 << 13));
+}
+
+static u8 wlc_phy_txpwr_idx_cur_get_nphy(phy_info_t *pi, u8 core)
+{
+ u16 tmp;
+ tmp = read_phy_reg(pi, ((core == PHY_CORE_0) ? 0x1ed : 0x1ee));
+
+ tmp = (tmp & (0x7f << 8)) >> 8;
+ return (u8) tmp;
+}
+
+static void
+wlc_phy_txpwr_idx_cur_set_nphy(phy_info_t *pi, u8 idx0, u8 idx1)
+{
+ mod_phy_reg(pi, 0x1e7, (0x7f << 0), idx0);
+
+ if (NREV_GT(pi->pubpi.phy_rev, 1))
+ mod_phy_reg(pi, 0x222, (0xff << 0), idx1);
+}
+
+u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi)
+{
+ u16 tmp;
+ u16 pwr_idx[2];
+
+ if (wlc_phy_txpwr_ison_nphy(pi)) {
+ pwr_idx[0] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_0);
+ pwr_idx[1] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_1);
+
+ tmp = (pwr_idx[0] << 8) | pwr_idx[1];
+ } else {
+ tmp =
+ ((pi->nphy_txpwrindex[PHY_CORE_0].
+ index_internal & 0xff) << 8) | (pi->
+ nphy_txpwrindex
+ [PHY_CORE_1].
+ index_internal & 0xff);
+ }
+
+ return tmp;
+}
+
+void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi)
+{
+ if (PHY_IPA(pi)
+ && (pi->nphy_force_papd_cal
+ || (wlc_phy_txpwr_ison_nphy(pi)
+ &&
+ (((u32)
+ ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 0) -
+ pi->nphy_papd_tx_gain_at_last_cal[0]) >= 4)
+ || ((u32)
+ ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 1) -
+ pi->nphy_papd_tx_gain_at_last_cal[1]) >= 4))))) {
+ wlc_phy_a4(pi, true);
+ }
+}
+
+void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type)
+{
+ u16 mask = 0, val = 0, ishw = 0;
+ u8 ctr;
+ uint core;
+ u32 tbl_offset;
+ u32 tbl_len;
+ u16 regval[84];
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ switch (ctrl_type) {
+ case PHY_TPC_HW_OFF:
+ case PHY_TPC_HW_ON:
+ pi->nphy_txpwrctrl = ctrl_type;
+ break;
+ default:
+ break;
+ }
+
+ if (ctrl_type == PHY_TPC_HW_OFF) {
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ if (wlc_phy_txpwr_ison_nphy(pi)) {
+ for (core = 0; core < pi->pubpi.phy_corenum;
+ core++)
+ pi->nphy_txpwr_idx[core] =
+ wlc_phy_txpwr_idx_cur_get_nphy(pi,
+ (u8)
+ core);
+ }
+
+ }
+
+ tbl_len = 84;
+ tbl_offset = 64;
+ for (ctr = 0; ctr < tbl_len; ctr++) {
+ regval[ctr] = 0;
+ }
+ wlc_phy_table_write_nphy(pi, 26, tbl_len, tbl_offset, 16,
+ regval);
+ wlc_phy_table_write_nphy(pi, 27, tbl_len, tbl_offset, 16,
+ regval);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+
+ and_phy_reg(pi, 0x1e7,
+ (u16) (~((0x1 << 15) |
+ (0x1 << 14) | (0x1 << 13))));
+ } else {
+ and_phy_reg(pi, 0x1e7,
+ (u16) (~((0x1 << 14) | (0x1 << 13))));
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ or_phy_reg(pi, 0x8f, (0x1 << 8));
+ or_phy_reg(pi, 0xa5, (0x1 << 8));
+ } else {
+ or_phy_reg(pi, 0xa5, (0x1 << 14));
+ }
+
+ if (NREV_IS(pi->pubpi.phy_rev, 2))
+ mod_phy_reg(pi, 0xdc, 0x00ff, 0x53);
+ else if (NREV_LT(pi->pubpi.phy_rev, 2))
+ mod_phy_reg(pi, 0xdc, 0x00ff, 0x5a);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2) && IS40MHZ(pi))
+ wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_IQSWAP_WAR,
+ MHF1_IQSWAP_WAR, WLC_BAND_ALL);
+
+ } else {
+
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 84, 64,
+ 8, pi->adj_pwr_tbl_nphy);
+ wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 84, 64,
+ 8, pi->adj_pwr_tbl_nphy);
+
+ ishw = (ctrl_type == PHY_TPC_HW_ON) ? 0x1 : 0x0;
+ mask = (0x1 << 14) | (0x1 << 13);
+ val = (ishw << 14) | (ishw << 13);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ mask |= (0x1 << 15);
+ val |= (ishw << 15);
+ }
+
+ mod_phy_reg(pi, 0x1e7, mask, val);
+
+ if (CHSPEC_IS5G(pi->radio_chanspec)) {
+ if (NREV_GE(pi->pubpi.phy_rev, 7)) {
+ mod_phy_reg(pi, 0x1e7, (0x7f << 0), 0x32);
+ mod_phy_reg(pi, 0x222, (0xff << 0), 0x32);
+ } else {
+ mod_phy_reg(pi, 0x1e7, (0x7f << 0), 0x64);
+ if (NREV_GT(pi->pubpi.phy_rev, 1))
+ mod_phy_reg(pi, 0x222,
+ (0xff << 0), 0x64);
+ }
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ if ((pi->nphy_txpwr_idx[0] != 128)
+ && (pi->nphy_txpwr_idx[1] != 128)) {
+ wlc_phy_txpwr_idx_cur_set_nphy(pi,
+ pi->
+ nphy_txpwr_idx
+ [0],
+ pi->
+ nphy_txpwr_idx
+ [1]);
+ }
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ and_phy_reg(pi, 0x8f, ~(0x1 << 8));
+ and_phy_reg(pi, 0xa5, ~(0x1 << 8));
+ } else {
+ and_phy_reg(pi, 0xa5, ~(0x1 << 14));
+ }
+
+ if (NREV_IS(pi->pubpi.phy_rev, 2))
+ mod_phy_reg(pi, 0xdc, 0x00ff, 0x3b);
+ else if (NREV_LT(pi->pubpi.phy_rev, 2))
+ mod_phy_reg(pi, 0xdc, 0x00ff, 0x40);
+
+ if (NREV_LT(pi->pubpi.phy_rev, 2) && IS40MHZ(pi))
+ wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_IQSWAP_WAR,
+ 0x0, WLC_BAND_ALL);
+
+ if (PHY_IPA(pi)) {
+ mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 2), (0) << 2);
+
+ mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 2), (0) << 2);
+
+ }
+
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+void
+wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask, s8 txpwrindex,
+ bool restore_cals)
+{
+ u8 core, txpwrctl_tbl;
+ u16 tx_ind0, iq_ind0, lo_ind0;
+ u16 m1m2;
+ u32 txgain;
+ u16 rad_gain, dac_gain;
+ u8 bbmult;
+ u32 iqcomp;
+ u16 iqcomp_a, iqcomp_b;
+ u32 locomp;
+ u16 tmpval;
+ u8 tx_pwr_ctrl_state;
+ s32 rfpwr_offset;
+ u16 regval[2];
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+
+ tx_ind0 = 192;
+ iq_ind0 = 320;
+ lo_ind0 = 448;
+
+ for (core = 0; core < pi->pubpi.phy_corenum; core++) {
+
+ if ((core_mask & (1 << core)) == 0) {
+ continue;
+ }
+
+ txpwrctl_tbl = (core == PHY_CORE_0) ? 26 : 27;
+
+ if (txpwrindex < 0) {
+ if (pi->nphy_txpwrindex[core].index < 0) {
+
+ continue;
+ }
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ mod_phy_reg(pi, 0x8f,
+ (0x1 << 8),
+ pi->nphy_txpwrindex[core].
+ AfectrlOverride);
+ mod_phy_reg(pi, 0xa5, (0x1 << 8),
+ pi->nphy_txpwrindex[core].
+ AfectrlOverride);
+ } else {
+ mod_phy_reg(pi, 0xa5,
+ (0x1 << 14),
+ pi->nphy_txpwrindex[core].
+ AfectrlOverride);
+ }
+
+ write_phy_reg(pi, (core == PHY_CORE_0) ?
+ 0xaa : 0xab,
+ pi->nphy_txpwrindex[core].AfeCtrlDacGain);
+
+ wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
+ &pi->nphy_txpwrindex[core].
+ rad_gain);
+
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
+ m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
+ m1m2 |= ((core == PHY_CORE_0) ?
+ (pi->nphy_txpwrindex[core].bbmult << 8) :
+ (pi->nphy_txpwrindex[core].bbmult << 0));
+ wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
+
+ if (restore_cals) {
+
+ wlc_phy_table_write_nphy(pi, 15, 2,
+ (80 + 2 * core), 16,
+ (void *)&pi->
+ nphy_txpwrindex[core].
+ iqcomp_a);
+
+ wlc_phy_table_write_nphy(pi, 15, 1, (85 + core),
+ 16,
+ &pi->
+ nphy_txpwrindex[core].
+ locomp);
+ wlc_phy_table_write_nphy(pi, 15, 1, (93 + core),
+ 16,
+ (void *)&pi->
+ nphy_txpwrindex[core].
+ locomp);
+ }
+
+ wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
+
+ pi->nphy_txpwrindex[core].index_internal =
+ pi->nphy_txpwrindex[core].index_internal_save;
+ } else {
+
+ if (pi->nphy_txpwrindex[core].index < 0) {
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ mod_phy_reg(pi, 0x8f,
+ (0x1 << 8),
+ pi->nphy_txpwrindex[core].
+ AfectrlOverride);
+ mod_phy_reg(pi, 0xa5, (0x1 << 8),
+ pi->nphy_txpwrindex[core].
+ AfectrlOverride);
+ } else {
+ pi->nphy_txpwrindex[core].
+ AfectrlOverride =
+ read_phy_reg(pi, 0xa5);
+ }
+
+ pi->nphy_txpwrindex[core].AfeCtrlDacGain =
+ read_phy_reg(pi,
+ (core ==
+ PHY_CORE_0) ? 0xaa : 0xab);
+
+ wlc_phy_table_read_nphy(pi, 7, 1,
+ (0x110 + core), 16,
+ &pi->
+ nphy_txpwrindex[core].
+ rad_gain);
+
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16,
+ &tmpval);
+ tmpval >>= ((core == PHY_CORE_0) ? 8 : 0);
+ tmpval &= 0xff;
+ pi->nphy_txpwrindex[core].bbmult =
+ (u8) tmpval;
+
+ wlc_phy_table_read_nphy(pi, 15, 2,
+ (80 + 2 * core), 16,
+ (void *)&pi->
+ nphy_txpwrindex[core].
+ iqcomp_a);
+
+ wlc_phy_table_read_nphy(pi, 15, 1, (85 + core),
+ 16,
+ (void *)&pi->
+ nphy_txpwrindex[core].
+ locomp);
+
+ pi->nphy_txpwrindex[core].index_internal_save =
+ pi->nphy_txpwrindex[core].index_internal;
+ }
+
+ tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
+ wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
+
+ if (NREV_IS(pi->pubpi.phy_rev, 1))
+ wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
+
+ wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
+ (tx_ind0 + txpwrindex), 32,
+ &txgain);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ rad_gain =
+ (txgain >> 16) & ((1 << (32 - 16 + 1)) - 1);
+ } else {
+ rad_gain =
+ (txgain >> 16) & ((1 << (28 - 16 + 1)) - 1);
+ }
+ dac_gain = (txgain >> 8) & ((1 << (13 - 8 + 1)) - 1);
+ bbmult = (txgain >> 0) & ((1 << (7 - 0 + 1)) - 1);
+
+ if (NREV_GE(pi->pubpi.phy_rev, 3)) {
+ mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
+ 0xa5), (0x1 << 8), (0x1 << 8));
+ } else {
+ mod_phy_reg(pi, 0xa5, (0x1 << 14), (0x1 << 14));
+ }
+ write_phy_reg(pi, (core == PHY_CORE_0) ?
+ 0xaa : 0xab, dac_gain);
+
+ wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
+ &rad_gain);
+
+ wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
+ m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
+ m1m2 |=
+ ((core ==
+ PHY_CORE_0) ? (bbmult << 8) : (bbmult << 0));
+
+ wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
+
+ wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
+ (iq_ind0 + txpwrindex), 32,
+ &iqcomp);
+ iqcomp_a = (iqcomp >> 10) & ((1 << (19 - 10 + 1)) - 1);
+ iqcomp_b = (iqcomp >> 0) & ((1 << (9 - 0 + 1)) - 1);
+
+ if (restore_cals) {
+ regval[0] = (u16) iqcomp_a;
+ regval[1] = (u16) iqcomp_b;
+ wlc_phy_table_write_nphy(pi, 15, 2,
+ (80 + 2 * core), 16,
+ regval);
+ }
+
+ wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
+ (lo_ind0 + txpwrindex), 32,
+ &locomp);
+ if (restore_cals) {
+ wlc_phy_table_write_nphy(pi, 15, 1, (85 + core),
+ 16, &locomp);
+ }
+
+ if (NREV_IS(pi->pubpi.phy_rev, 1))
+ wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
+
+ if (PHY_IPA(pi)) {
+ wlc_phy_table_read_nphy(pi,
+ (core ==
+ PHY_CORE_0 ?
+ NPHY_TBL_ID_CORE1TXPWRCTL
+ :
+ NPHY_TBL_ID_CORE2TXPWRCTL),
+ 1, 576 + txpwrindex, 32,
+ &rfpwr_offset);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1ff << 4),
+ ((s16) rfpwr_offset) << 4);
+
+ mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
+ 0x29b, (0x1 << 2), (1) << 2);
+
+ }
+
+ wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
+ }
+
+ pi->nphy_txpwrindex[core].index = txpwrindex;
+ }
+
+ if (pi->phyhang_avoid)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+}
+
+void
+wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan, u8 *max_pwr,
+ u8 txp_rate_idx)
+{
+ u8 chan_freq_range;
+
+ chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, chan);
+ switch (chan_freq_range) {
+ case WL_CHAN_FREQ_RANGE_2G:
+ *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
+ break;
+ case WL_CHAN_FREQ_RANGE_5GM:
+ *max_pwr = pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
+ break;
+ case WL_CHAN_FREQ_RANGE_5GL:
+ *max_pwr = pi->tx_srom_max_rate_5g_low[txp_rate_idx];
+ break;
+ case WL_CHAN_FREQ_RANGE_5GH:
+ *max_pwr = pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
+ break;
+ default:
+ *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
+ break;
+ }
+
+ return;
+}
+
+void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable)
+{
+ u16 clip_off[] = { 0xffff, 0xffff };
+
+ if (enable) {
+ if (pi->nphy_deaf_count == 0) {
+ pi->classifier_state =
+ wlc_phy_classifier_nphy(pi, 0, 0);
+ wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
+ wlc_phy_clip_det_nphy(pi, 0, pi->clip_state);
+ wlc_phy_clip_det_nphy(pi, 1, clip_off);
+ }
+
+ pi->nphy_deaf_count++;
+
+ wlc_phy_resetcca_nphy(pi);
+
+ } else {
+ pi->nphy_deaf_count--;
+
+ if (pi->nphy_deaf_count == 0) {
+ wlc_phy_classifier_nphy(pi, (0x7 << 0),
+ pi->classifier_state);
+ wlc_phy_clip_det_nphy(pi, 1, pi->clip_state);
+ }
+ }
+}
+
+void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode)
+{
+ wlapi_suspend_mac_and_wait(pi->sh->physhim);
+
+ if (mode) {
+ if (pi->nphy_deaf_count == 0)
+ wlc_phy_stay_in_carriersearch_nphy(pi, true);
+ } else {
+ if (pi->nphy_deaf_count > 0)
+ wlc_phy_stay_in_carriersearch_nphy(pi, false);
+ }
+ wlapi_enable_mac(pi->sh->physhim);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/types.h>
+
+#include "phy_qmath.h"
+
+/*
+Description: This function make 16 bit unsigned multiplication. To fit the output into
+16 bits the 32 bit multiplication result is right shifted by 16 bits.
+*/
+u16 qm_mulu16(u16 op1, u16 op2)
+{
+ return (u16) (((u32) op1 * (u32) op2) >> 16);
+}
+
+/*
+Description: This function make 16 bit multiplication and return the result in 16 bits.
+To fit the multiplication result into 16 bits the multiplication result is right shifted by
+15 bits. Right shifting 15 bits instead of 16 bits is done to remove the extra sign bit formed
+due to the multiplication.
+When both the 16bit inputs are 0x8000 then the output is saturated to 0x7fffffff.
+*/
+s16 qm_muls16(s16 op1, s16 op2)
+{
+ s32 result;
+ if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000) {
+ result = 0x7fffffff;
+ } else {
+ result = ((s32) (op1) * (s32) (op2));
+ }
+ return (s16) (result >> 15);
+}
+
+/*
+Description: This function add two 32 bit numbers and return the 32bit result.
+If the result overflow 32 bits, the output will be saturated to 32bits.
+*/
+s32 qm_add32(s32 op1, s32 op2)
+{
+ s32 result;
+ result = op1 + op2;
+ if (op1 < 0 && op2 < 0 && result > 0) {
+ result = 0x80000000;
+ } else if (op1 > 0 && op2 > 0 && result < 0) {
+ result = 0x7fffffff;
+ }
+ return result;
+}
+
+/*
+Description: This function add two 16 bit numbers and return the 16bit result.
+If the result overflow 16 bits, the output will be saturated to 16bits.
+*/
+s16 qm_add16(s16 op1, s16 op2)
+{
+ s16 result;
+ s32 temp = (s32) op1 + (s32) op2;
+ if (temp > (s32) 0x7fff) {
+ result = (s16) 0x7fff;
+ } else if (temp < (s32) 0xffff8000) {
+ result = (s16) 0xffff8000;
+ } else {
+ result = (s16) temp;
+ }
+ return result;
+}
+
+/*
+Description: This function make 16 bit subtraction and return the 16bit result.
+If the result overflow 16 bits, the output will be saturated to 16bits.
+*/
+s16 qm_sub16(s16 op1, s16 op2)
+{
+ s16 result;
+ s32 temp = (s32) op1 - (s32) op2;
+ if (temp > (s32) 0x7fff) {
+ result = (s16) 0x7fff;
+ } else if (temp < (s32) 0xffff8000) {
+ result = (s16) 0xffff8000;
+ } else {
+ result = (s16) temp;
+ }
+ return result;
+}
+
+/*
+Description: This function make a 32 bit saturated left shift when the specified shift
+is +ve. This function will make a 32 bit right shift when the specified shift is -ve.
+This function return the result after shifting operation.
+*/
+s32 qm_shl32(s32 op, int shift)
+{
+ int i;
+ s32 result;
+ result = op;
+ if (shift > 31)
+ shift = 31;
+ else if (shift < -31)
+ shift = -31;
+ if (shift >= 0) {
+ for (i = 0; i < shift; i++) {
+ result = qm_add32(result, result);
+ }
+ } else {
+ result = result >> (-shift);
+ }
+ return result;
+}
+
+/*
+Description: This function make a 16 bit saturated left shift when the specified shift
+is +ve. This function will make a 16 bit right shift when the specified shift is -ve.
+This function return the result after shifting operation.
+*/
+s16 qm_shl16(s16 op, int shift)
+{
+ int i;
+ s16 result;
+ result = op;
+ if (shift > 15)
+ shift = 15;
+ else if (shift < -15)
+ shift = -15;
+ if (shift > 0) {
+ for (i = 0; i < shift; i++) {
+ result = qm_add16(result, result);
+ }
+ } else {
+ result = result >> (-shift);
+ }
+ return result;
+}
+
+/*
+Description: This function make a 16 bit right shift when shift is +ve.
+This function make a 16 bit saturated left shift when shift is -ve. This function
+return the result of the shift operation.
+*/
+s16 qm_shr16(s16 op, int shift)
+{
+ return qm_shl16(op, -shift);
+}
+
+/*
+Description: This function return the number of redundant sign bits in a 32 bit number.
+Example: qm_norm32(0x00000080) = 23
+*/
+s16 qm_norm32(s32 op)
+{
+ u16 u16extraSignBits;
+ if (op == 0) {
+ return 31;
+ } else {
+ u16extraSignBits = 0;
+ while ((op >> 31) == (op >> 30)) {
+ u16extraSignBits++;
+ op = op << 1;
+ }
+ }
+ return u16extraSignBits;
+}
+
+/* This table is log2(1+(i/32)) where i=[0:1:31], in q.15 format */
+static const s16 log_table[] = {
+ 0,
+ 1455,
+ 2866,
+ 4236,
+ 5568,
+ 6863,
+ 8124,
+ 9352,
+ 10549,
+ 11716,
+ 12855,
+ 13968,
+ 15055,
+ 16117,
+ 17156,
+ 18173,
+ 19168,
+ 20143,
+ 21098,
+ 22034,
+ 22952,
+ 23852,
+ 24736,
+ 25604,
+ 26455,
+ 27292,
+ 28114,
+ 28922,
+ 29717,
+ 30498,
+ 31267,
+ 32024
+};
+
+#define LOG_TABLE_SIZE 32 /* log_table size */
+#define LOG2_LOG_TABLE_SIZE 5 /* log2(log_table size) */
+#define Q_LOG_TABLE 15 /* qformat of log_table */
+#define LOG10_2 19728 /* log10(2) in q.16 */
+
+/*
+Description:
+This routine takes the input number N and its q format qN and compute
+the log10(N). This routine first normalizes the input no N. Then N is in mag*(2^x) format.
+mag is any number in the range 2^30-(2^31 - 1). Then log2(mag * 2^x) = log2(mag) + x is computed.
+From that log10(mag * 2^x) = log2(mag * 2^x) * log10(2) is computed.
+This routine looks the log2 value in the table considering LOG2_LOG_TABLE_SIZE+1 MSBs.
+As the MSB is always 1, only next LOG2_OF_LOG_TABLE_SIZE MSBs are used for table lookup.
+Next 16 MSBs are used for interpolation.
+Inputs:
+N - number to which log10 has to be found.
+qN - q format of N
+log10N - address where log10(N) will be written.
+qLog10N - address where log10N qformat will be written.
+Note/Problem:
+For accurate results input should be in normalized or near normalized form.
+*/
+void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N)
+{
+ s16 s16norm, s16tableIndex, s16errorApproximation;
+ u16 u16offset;
+ s32 s32log;
+
+ /* normalize the N. */
+ s16norm = qm_norm32(N);
+ N = N << s16norm;
+
+ /* The qformat of N after normalization.
+ * -30 is added to treat the no as between 1.0 to 2.0
+ * i.e. after adding the -30 to the qformat the decimal point will be
+ * just rigtht of the MSB. (i.e. after sign bit and 1st MSB). i.e.
+ * at the right side of 30th bit.
+ */
+ qN = qN + s16norm - 30;
+
+ /* take the table index as the LOG2_OF_LOG_TABLE_SIZE bits right of the MSB */
+ s16tableIndex = (s16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE)));
+
+ /* remove the MSB. the MSB is always 1 after normalization. */
+ s16tableIndex =
+ s16tableIndex & (s16) ((1 << LOG2_LOG_TABLE_SIZE) - 1);
+
+ /* remove the (1+LOG2_OF_LOG_TABLE_SIZE) MSBs in the N. */
+ N = N & ((1 << (32 - (2 + LOG2_LOG_TABLE_SIZE))) - 1);
+
+ /* take the offset as the 16 MSBS after table index.
+ */
+ u16offset = (u16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE + 16)));
+
+ /* look the log value in the table. */
+ s32log = log_table[s16tableIndex]; /* q.15 format */
+
+ /* interpolate using the offset. */
+ s16errorApproximation = (s16) qm_mulu16(u16offset, (u16) (log_table[s16tableIndex + 1] - log_table[s16tableIndex])); /* q.15 */
+
+ s32log = qm_add16((s16) s32log, s16errorApproximation); /* q.15 format */
+
+ /* adjust for the qformat of the N as
+ * log2(mag * 2^x) = log2(mag) + x
+ */
+ s32log = qm_add32(s32log, ((s32) -qN) << 15); /* q.15 format */
+
+ /* normalize the result. */
+ s16norm = qm_norm32(s32log);
+
+ /* bring all the important bits into lower 16 bits */
+ s32log = qm_shl32(s32log, s16norm - 16); /* q.15+s16norm-16 format */
+
+ /* compute the log10(N) by multiplying log2(N) with log10(2).
+ * as log10(mag * 2^x) = log2(mag * 2^x) * log10(2)
+ * log10N in q.15+s16norm-16+1 (LOG10_2 is in q.16)
+ */
+ *log10N = qm_muls16((s16) s32log, (s16) LOG10_2);
+
+ /* write the q format of the result. */
+ *qLog10N = 15 + s16norm - 16 + 1;
+
+ return;
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_QMATH_H_
+#define _BRCM_QMATH_H_
+
+u16 qm_mulu16(u16 op1, u16 op2);
+
+s16 qm_muls16(s16 op1, s16 op2);
+
+s32 qm_add32(s32 op1, s32 op2);
+
+s16 qm_add16(s16 op1, s16 op2);
+
+s16 qm_sub16(s16 op1, s16 op2);
+
+s32 qm_shl32(s32 op, int shift);
+
+s16 qm_shl16(s16 op, int shift);
+
+s16 qm_shr16(s16 op, int shift);
+
+s16 qm_norm32(s32 op);
+
+void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N);
+
+#endif /* #ifndef _BRCM_QMATH_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_PHY_RADIO_H_
+#define _BRCM_PHY_RADIO_H_
+
+#define RADIO_IDCODE 0x01
+
+#define RADIO_DEFAULT_CORE 0
+
+#define RXC0_RSSI_RST 0x80
+#define RXC0_MODE_RSSI 0x40
+#define RXC0_MODE_OFF 0x20
+#define RXC0_MODE_CM 0x10
+#define RXC0_LAN_LOAD 0x08
+#define RXC0_OFF_ADJ_MASK 0x07
+
+#define TXC0_MODE_TXLPF 0x04
+#define TXC0_PA_TSSI_EN 0x02
+#define TXC0_TSSI_EN 0x01
+
+#define TXC1_PA_GAIN_MASK 0x60
+#define TXC1_PA_GAIN_3DB 0x40
+#define TXC1_PA_GAIN_2DB 0x20
+#define TXC1_TX_MIX_GAIN 0x10
+#define TXC1_OFF_I_MASK 0x0c
+#define TXC1_OFF_Q_MASK 0x03
+
+#define RADIO_2055_READ_OFF 0x100
+#define RADIO_2057_READ_OFF 0x200
+
+#define RADIO_2055_GEN_SPARE 0x00
+#define RADIO_2055_SP_PIN_PD 0x02
+#define RADIO_2055_SP_RSSI_CORE1 0x03
+#define RADIO_2055_SP_PD_MISC_CORE1 0x04
+#define RADIO_2055_SP_RSSI_CORE2 0x05
+#define RADIO_2055_SP_PD_MISC_CORE2 0x06
+#define RADIO_2055_SP_RX_GC1_CORE1 0x07
+#define RADIO_2055_SP_RX_GC2_CORE1 0x08
+#define RADIO_2055_SP_RX_GC1_CORE2 0x09
+#define RADIO_2055_SP_RX_GC2_CORE2 0x0a
+#define RADIO_2055_SP_LPF_BW_SELECT_CORE1 0x0b
+#define RADIO_2055_SP_LPF_BW_SELECT_CORE2 0x0c
+#define RADIO_2055_SP_TX_GC1_CORE1 0x0d
+#define RADIO_2055_SP_TX_GC2_CORE1 0x0e
+#define RADIO_2055_SP_TX_GC1_CORE2 0x0f
+#define RADIO_2055_SP_TX_GC2_CORE2 0x10
+#define RADIO_2055_MASTER_CNTRL1 0x11
+#define RADIO_2055_MASTER_CNTRL2 0x12
+#define RADIO_2055_PD_LGEN 0x13
+#define RADIO_2055_PD_PLL_TS 0x14
+#define RADIO_2055_PD_CORE1_LGBUF 0x15
+#define RADIO_2055_PD_CORE1_TX 0x16
+#define RADIO_2055_PD_CORE1_RXTX 0x17
+#define RADIO_2055_PD_CORE1_RSSI_MISC 0x18
+#define RADIO_2055_PD_CORE2_LGBUF 0x19
+#define RADIO_2055_PD_CORE2_TX 0x1a
+#define RADIO_2055_PD_CORE2_RXTX 0x1b
+#define RADIO_2055_PD_CORE2_RSSI_MISC 0x1c
+#define RADIO_2055_PWRDET_LGEN 0x1d
+#define RADIO_2055_PWRDET_LGBUF_CORE1 0x1e
+#define RADIO_2055_PWRDET_RXTX_CORE1 0x1f
+#define RADIO_2055_PWRDET_LGBUF_CORE2 0x20
+#define RADIO_2055_PWRDET_RXTX_CORE2 0x21
+#define RADIO_2055_RRCCAL_CNTRL_SPARE 0x22
+#define RADIO_2055_RRCCAL_N_OPT_SEL 0x23
+#define RADIO_2055_CAL_MISC 0x24
+#define RADIO_2055_CAL_COUNTER_OUT 0x25
+#define RADIO_2055_CAL_COUNTER_OUT2 0x26
+#define RADIO_2055_CAL_CVAR_CNTRL 0x27
+#define RADIO_2055_CAL_RVAR_CNTRL 0x28
+#define RADIO_2055_CAL_LPO_CNTRL 0x29
+#define RADIO_2055_CAL_TS 0x2a
+#define RADIO_2055_CAL_RCCAL_READ_TS 0x2b
+#define RADIO_2055_CAL_RCAL_READ_TS 0x2c
+#define RADIO_2055_PAD_DRIVER 0x2d
+#define RADIO_2055_XO_CNTRL1 0x2e
+#define RADIO_2055_XO_CNTRL2 0x2f
+#define RADIO_2055_XO_REGULATOR 0x30
+#define RADIO_2055_XO_MISC 0x31
+#define RADIO_2055_PLL_LF_C1 0x32
+#define RADIO_2055_PLL_CAL_VTH 0x33
+#define RADIO_2055_PLL_LF_C2 0x34
+#define RADIO_2055_PLL_REF 0x35
+#define RADIO_2055_PLL_LF_R1 0x36
+#define RADIO_2055_PLL_PFD_CP 0x37
+#define RADIO_2055_PLL_IDAC_CPOPAMP 0x38
+#define RADIO_2055_PLL_CP_REGULATOR 0x39
+#define RADIO_2055_PLL_RCAL 0x3a
+#define RADIO_2055_RF_PLL_MOD0 0x3b
+#define RADIO_2055_RF_PLL_MOD1 0x3c
+#define RADIO_2055_RF_MMD_IDAC1 0x3d
+#define RADIO_2055_RF_MMD_IDAC0 0x3e
+#define RADIO_2055_RF_MMD_SPARE 0x3f
+#define RADIO_2055_VCO_CAL1 0x40
+#define RADIO_2055_VCO_CAL2 0x41
+#define RADIO_2055_VCO_CAL3 0x42
+#define RADIO_2055_VCO_CAL4 0x43
+#define RADIO_2055_VCO_CAL5 0x44
+#define RADIO_2055_VCO_CAL6 0x45
+#define RADIO_2055_VCO_CAL7 0x46
+#define RADIO_2055_VCO_CAL8 0x47
+#define RADIO_2055_VCO_CAL9 0x48
+#define RADIO_2055_VCO_CAL10 0x49
+#define RADIO_2055_VCO_CAL11 0x4a
+#define RADIO_2055_VCO_CAL12 0x4b
+#define RADIO_2055_VCO_CAL13 0x4c
+#define RADIO_2055_VCO_CAL14 0x4d
+#define RADIO_2055_VCO_CAL15 0x4e
+#define RADIO_2055_VCO_CAL16 0x4f
+#define RADIO_2055_VCO_KVCO 0x50
+#define RADIO_2055_VCO_CAP_TAIL 0x51
+#define RADIO_2055_VCO_IDAC_VCO 0x52
+#define RADIO_2055_VCO_REGULATOR 0x53
+#define RADIO_2055_PLL_RF_VTH 0x54
+#define RADIO_2055_LGBUF_CEN_BUF 0x55
+#define RADIO_2055_LGEN_TUNE1 0x56
+#define RADIO_2055_LGEN_TUNE2 0x57
+#define RADIO_2055_LGEN_IDAC1 0x58
+#define RADIO_2055_LGEN_IDAC2 0x59
+#define RADIO_2055_LGEN_BIAS_CNT 0x5a
+#define RADIO_2055_LGEN_BIAS_IDAC 0x5b
+#define RADIO_2055_LGEN_RCAL 0x5c
+#define RADIO_2055_LGEN_DIV 0x5d
+#define RADIO_2055_LGEN_SPARE2 0x5e
+#define RADIO_2055_CORE1_LGBUF_A_TUNE 0x5f
+#define RADIO_2055_CORE1_LGBUF_G_TUNE 0x60
+#define RADIO_2055_CORE1_LGBUF_DIV 0x61
+#define RADIO_2055_CORE1_LGBUF_A_IDAC 0x62
+#define RADIO_2055_CORE1_LGBUF_G_IDAC 0x63
+#define RADIO_2055_CORE1_LGBUF_IDACFIL_OVR 0x64
+#define RADIO_2055_CORE1_LGBUF_SPARE 0x65
+#define RADIO_2055_CORE1_RXRF_SPC1 0x66
+#define RADIO_2055_CORE1_RXRF_REG1 0x67
+#define RADIO_2055_CORE1_RXRF_REG2 0x68
+#define RADIO_2055_CORE1_RXRF_RCAL 0x69
+#define RADIO_2055_CORE1_RXBB_BUFI_LPFCMP 0x6a
+#define RADIO_2055_CORE1_RXBB_LPF 0x6b
+#define RADIO_2055_CORE1_RXBB_MIDAC_HIPAS 0x6c
+#define RADIO_2055_CORE1_RXBB_VGA1_IDAC 0x6d
+#define RADIO_2055_CORE1_RXBB_VGA2_IDAC 0x6e
+#define RADIO_2055_CORE1_RXBB_VGA3_IDAC 0x6f
+#define RADIO_2055_CORE1_RXBB_BUFO_CTRL 0x70
+#define RADIO_2055_CORE1_RXBB_RCCAL_CTRL 0x71
+#define RADIO_2055_CORE1_RXBB_RSSI_CTRL1 0x72
+#define RADIO_2055_CORE1_RXBB_RSSI_CTRL2 0x73
+#define RADIO_2055_CORE1_RXBB_RSSI_CTRL3 0x74
+#define RADIO_2055_CORE1_RXBB_RSSI_CTRL4 0x75
+#define RADIO_2055_CORE1_RXBB_RSSI_CTRL5 0x76
+#define RADIO_2055_CORE1_RXBB_REGULATOR 0x77
+#define RADIO_2055_CORE1_RXBB_SPARE1 0x78
+#define RADIO_2055_CORE1_RXTXBB_RCAL 0x79
+#define RADIO_2055_CORE1_TXRF_SGM_PGA 0x7a
+#define RADIO_2055_CORE1_TXRF_SGM_PAD 0x7b
+#define RADIO_2055_CORE1_TXRF_CNTR_PGA1 0x7c
+#define RADIO_2055_CORE1_TXRF_CNTR_PAD1 0x7d
+#define RADIO_2055_CORE1_TX_RFPGA_IDAC 0x7e
+#define RADIO_2055_CORE1_TX_PGA_PAD_TN 0x7f
+#define RADIO_2055_CORE1_TX_PAD_IDAC1 0x80
+#define RADIO_2055_CORE1_TX_PAD_IDAC2 0x81
+#define RADIO_2055_CORE1_TX_MX_BGTRIM 0x82
+#define RADIO_2055_CORE1_TXRF_RCAL 0x83
+#define RADIO_2055_CORE1_TXRF_PAD_TSSI1 0x84
+#define RADIO_2055_CORE1_TXRF_PAD_TSSI2 0x85
+#define RADIO_2055_CORE1_TX_RF_SPARE 0x86
+#define RADIO_2055_CORE1_TXRF_IQCAL1 0x87
+#define RADIO_2055_CORE1_TXRF_IQCAL2 0x88
+#define RADIO_2055_CORE1_TXBB_RCCAL_CTRL 0x89
+#define RADIO_2055_CORE1_TXBB_LPF1 0x8a
+#define RADIO_2055_CORE1_TX_VOS_CNCL 0x8b
+#define RADIO_2055_CORE1_TX_LPF_MXGM_IDAC 0x8c
+#define RADIO_2055_CORE1_TX_BB_MXGM 0x8d
+#define RADIO_2055_CORE2_LGBUF_A_TUNE 0x8e
+#define RADIO_2055_CORE2_LGBUF_G_TUNE 0x8f
+#define RADIO_2055_CORE2_LGBUF_DIV 0x90
+#define RADIO_2055_CORE2_LGBUF_A_IDAC 0x91
+#define RADIO_2055_CORE2_LGBUF_G_IDAC 0x92
+#define RADIO_2055_CORE2_LGBUF_IDACFIL_OVR 0x93
+#define RADIO_2055_CORE2_LGBUF_SPARE 0x94
+#define RADIO_2055_CORE2_RXRF_SPC1 0x95
+#define RADIO_2055_CORE2_RXRF_REG1 0x96
+#define RADIO_2055_CORE2_RXRF_REG2 0x97
+#define RADIO_2055_CORE2_RXRF_RCAL 0x98
+#define RADIO_2055_CORE2_RXBB_BUFI_LPFCMP 0x99
+#define RADIO_2055_CORE2_RXBB_LPF 0x9a
+#define RADIO_2055_CORE2_RXBB_MIDAC_HIPAS 0x9b
+#define RADIO_2055_CORE2_RXBB_VGA1_IDAC 0x9c
+#define RADIO_2055_CORE2_RXBB_VGA2_IDAC 0x9d
+#define RADIO_2055_CORE2_RXBB_VGA3_IDAC 0x9e
+#define RADIO_2055_CORE2_RXBB_BUFO_CTRL 0x9f
+#define RADIO_2055_CORE2_RXBB_RCCAL_CTRL 0xa0
+#define RADIO_2055_CORE2_RXBB_RSSI_CTRL1 0xa1
+#define RADIO_2055_CORE2_RXBB_RSSI_CTRL2 0xa2
+#define RADIO_2055_CORE2_RXBB_RSSI_CTRL3 0xa3
+#define RADIO_2055_CORE2_RXBB_RSSI_CTRL4 0xa4
+#define RADIO_2055_CORE2_RXBB_RSSI_CTRL5 0xa5
+#define RADIO_2055_CORE2_RXBB_REGULATOR 0xa6
+#define RADIO_2055_CORE2_RXBB_SPARE1 0xa7
+#define RADIO_2055_CORE2_RXTXBB_RCAL 0xa8
+#define RADIO_2055_CORE2_TXRF_SGM_PGA 0xa9
+#define RADIO_2055_CORE2_TXRF_SGM_PAD 0xaa
+#define RADIO_2055_CORE2_TXRF_CNTR_PGA1 0xab
+#define RADIO_2055_CORE2_TXRF_CNTR_PAD1 0xac
+#define RADIO_2055_CORE2_TX_RFPGA_IDAC 0xad
+#define RADIO_2055_CORE2_TX_PGA_PAD_TN 0xae
+#define RADIO_2055_CORE2_TX_PAD_IDAC1 0xaf
+#define RADIO_2055_CORE2_TX_PAD_IDAC2 0xb0
+#define RADIO_2055_CORE2_TX_MX_BGTRIM 0xb1
+#define RADIO_2055_CORE2_TXRF_RCAL 0xb2
+#define RADIO_2055_CORE2_TXRF_PAD_TSSI1 0xb3
+#define RADIO_2055_CORE2_TXRF_PAD_TSSI2 0xb4
+#define RADIO_2055_CORE2_TX_RF_SPARE 0xb5
+#define RADIO_2055_CORE2_TXRF_IQCAL1 0xb6
+#define RADIO_2055_CORE2_TXRF_IQCAL2 0xb7
+#define RADIO_2055_CORE2_TXBB_RCCAL_CTRL 0xb8
+#define RADIO_2055_CORE2_TXBB_LPF1 0xb9
+#define RADIO_2055_CORE2_TX_VOS_CNCL 0xba
+#define RADIO_2055_CORE2_TX_LPF_MXGM_IDAC 0xbb
+#define RADIO_2055_CORE2_TX_BB_MXGM 0xbc
+#define RADIO_2055_PRG_GC_HPVGA23_21 0xbd
+#define RADIO_2055_PRG_GC_HPVGA23_22 0xbe
+#define RADIO_2055_PRG_GC_HPVGA23_23 0xbf
+#define RADIO_2055_PRG_GC_HPVGA23_24 0xc0
+#define RADIO_2055_PRG_GC_HPVGA23_25 0xc1
+#define RADIO_2055_PRG_GC_HPVGA23_26 0xc2
+#define RADIO_2055_PRG_GC_HPVGA23_27 0xc3
+#define RADIO_2055_PRG_GC_HPVGA23_28 0xc4
+#define RADIO_2055_PRG_GC_HPVGA23_29 0xc5
+#define RADIO_2055_PRG_GC_HPVGA23_30 0xc6
+#define RADIO_2055_CORE1_LNA_GAINBST 0xcd
+#define RADIO_2055_CORE1_B0_NBRSSI_VCM 0xd2
+#define RADIO_2055_CORE1_GEN_SPARE2 0xd6
+#define RADIO_2055_CORE2_LNA_GAINBST 0xd9
+#define RADIO_2055_CORE2_B0_NBRSSI_VCM 0xde
+#define RADIO_2055_CORE2_GEN_SPARE2 0xe2
+
+#define RADIO_2055_GAINBST_GAIN_DB 6
+#define RADIO_2055_GAINBST_CODE 0x6
+
+#define RADIO_2055_JTAGCTRL_MASK 0x04
+#define RADIO_2055_JTAGSYNC_MASK 0x08
+#define RADIO_2055_RRCAL_START 0x40
+#define RADIO_2055_RRCAL_RST_N 0x01
+#define RADIO_2055_CAL_LPO_ENABLE 0x80
+#define RADIO_2055_RCAL_DONE 0x80
+#define RADIO_2055_NBRSSI_VCM_I_MASK 0x03
+#define RADIO_2055_NBRSSI_VCM_I_SHIFT 0x00
+#define RADIO_2055_NBRSSI_VCM_Q_MASK 0x03
+#define RADIO_2055_NBRSSI_VCM_Q_SHIFT 0x00
+#define RADIO_2055_WBRSSI_VCM_IQ_MASK 0x0c
+#define RADIO_2055_WBRSSI_VCM_IQ_SHIFT 0x02
+#define RADIO_2055_NBRSSI_PD 0x01
+#define RADIO_2055_WBRSSI_G1_PD 0x04
+#define RADIO_2055_WBRSSI_G2_PD 0x02
+#define RADIO_2055_NBRSSI_SEL 0x01
+#define RADIO_2055_WBRSSI_G1_SEL 0x04
+#define RADIO_2055_WBRSSI_G2_SEL 0x02
+#define RADIO_2055_COUPLE_RX_MASK 0x01
+#define RADIO_2055_COUPLE_TX_MASK 0x02
+#define RADIO_2055_GAINBST_DISABLE 0x02
+#define RADIO_2055_GAINBST_VAL_MASK 0x07
+#define RADIO_2055_RXMX_GC_MASK 0x0c
+
+#define RADIO_MIMO_CORESEL_OFF 0x0
+#define RADIO_MIMO_CORESEL_CORE1 0x1
+#define RADIO_MIMO_CORESEL_CORE2 0x2
+#define RADIO_MIMO_CORESEL_CORE3 0x3
+#define RADIO_MIMO_CORESEL_CORE4 0x4
+#define RADIO_MIMO_CORESEL_ALLRX 0x5
+#define RADIO_MIMO_CORESEL_ALLTX 0x6
+#define RADIO_MIMO_CORESEL_ALLRXTX 0x7
+
+#define RADIO_2064_READ_OFF 0x200
+
+#define RADIO_2064_REG000 0x0
+#define RADIO_2064_REG001 0x1
+#define RADIO_2064_REG002 0x2
+#define RADIO_2064_REG003 0x3
+#define RADIO_2064_REG004 0x4
+#define RADIO_2064_REG005 0x5
+#define RADIO_2064_REG006 0x6
+#define RADIO_2064_REG007 0x7
+#define RADIO_2064_REG008 0x8
+#define RADIO_2064_REG009 0x9
+#define RADIO_2064_REG00A 0xa
+#define RADIO_2064_REG00B 0xb
+#define RADIO_2064_REG00C 0xc
+#define RADIO_2064_REG00D 0xd
+#define RADIO_2064_REG00E 0xe
+#define RADIO_2064_REG00F 0xf
+#define RADIO_2064_REG010 0x10
+#define RADIO_2064_REG011 0x11
+#define RADIO_2064_REG012 0x12
+#define RADIO_2064_REG013 0x13
+#define RADIO_2064_REG014 0x14
+#define RADIO_2064_REG015 0x15
+#define RADIO_2064_REG016 0x16
+#define RADIO_2064_REG017 0x17
+#define RADIO_2064_REG018 0x18
+#define RADIO_2064_REG019 0x19
+#define RADIO_2064_REG01A 0x1a
+#define RADIO_2064_REG01B 0x1b
+#define RADIO_2064_REG01C 0x1c
+#define RADIO_2064_REG01D 0x1d
+#define RADIO_2064_REG01E 0x1e
+#define RADIO_2064_REG01F 0x1f
+#define RADIO_2064_REG020 0x20
+#define RADIO_2064_REG021 0x21
+#define RADIO_2064_REG022 0x22
+#define RADIO_2064_REG023 0x23
+#define RADIO_2064_REG024 0x24
+#define RADIO_2064_REG025 0x25
+#define RADIO_2064_REG026 0x26
+#define RADIO_2064_REG027 0x27
+#define RADIO_2064_REG028 0x28
+#define RADIO_2064_REG029 0x29
+#define RADIO_2064_REG02A 0x2a
+#define RADIO_2064_REG02B 0x2b
+#define RADIO_2064_REG02C 0x2c
+#define RADIO_2064_REG02D 0x2d
+#define RADIO_2064_REG02E 0x2e
+#define RADIO_2064_REG02F 0x2f
+#define RADIO_2064_REG030 0x30
+#define RADIO_2064_REG031 0x31
+#define RADIO_2064_REG032 0x32
+#define RADIO_2064_REG033 0x33
+#define RADIO_2064_REG034 0x34
+#define RADIO_2064_REG035 0x35
+#define RADIO_2064_REG036 0x36
+#define RADIO_2064_REG037 0x37
+#define RADIO_2064_REG038 0x38
+#define RADIO_2064_REG039 0x39
+#define RADIO_2064_REG03A 0x3a
+#define RADIO_2064_REG03B 0x3b
+#define RADIO_2064_REG03C 0x3c
+#define RADIO_2064_REG03D 0x3d
+#define RADIO_2064_REG03E 0x3e
+#define RADIO_2064_REG03F 0x3f
+#define RADIO_2064_REG040 0x40
+#define RADIO_2064_REG041 0x41
+#define RADIO_2064_REG042 0x42
+#define RADIO_2064_REG043 0x43
+#define RADIO_2064_REG044 0x44
+#define RADIO_2064_REG045 0x45
+#define RADIO_2064_REG046 0x46
+#define RADIO_2064_REG047 0x47
+#define RADIO_2064_REG048 0x48
+#define RADIO_2064_REG049 0x49
+#define RADIO_2064_REG04A 0x4a
+#define RADIO_2064_REG04B 0x4b
+#define RADIO_2064_REG04C 0x4c
+#define RADIO_2064_REG04D 0x4d
+#define RADIO_2064_REG04E 0x4e
+#define RADIO_2064_REG04F 0x4f
+#define RADIO_2064_REG050 0x50
+#define RADIO_2064_REG051 0x51
+#define RADIO_2064_REG052 0x52
+#define RADIO_2064_REG053 0x53
+#define RADIO_2064_REG054 0x54
+#define RADIO_2064_REG055 0x55
+#define RADIO_2064_REG056 0x56
+#define RADIO_2064_REG057 0x57
+#define RADIO_2064_REG058 0x58
+#define RADIO_2064_REG059 0x59
+#define RADIO_2064_REG05A 0x5a
+#define RADIO_2064_REG05B 0x5b
+#define RADIO_2064_REG05C 0x5c
+#define RADIO_2064_REG05D 0x5d
+#define RADIO_2064_REG05E 0x5e
+#define RADIO_2064_REG05F 0x5f
+#define RADIO_2064_REG060 0x60
+#define RADIO_2064_REG061 0x61
+#define RADIO_2064_REG062 0x62
+#define RADIO_2064_REG063 0x63
+#define RADIO_2064_REG064 0x64
+#define RADIO_2064_REG065 0x65
+#define RADIO_2064_REG066 0x66
+#define RADIO_2064_REG067 0x67
+#define RADIO_2064_REG068 0x68
+#define RADIO_2064_REG069 0x69
+#define RADIO_2064_REG06A 0x6a
+#define RADIO_2064_REG06B 0x6b
+#define RADIO_2064_REG06C 0x6c
+#define RADIO_2064_REG06D 0x6d
+#define RADIO_2064_REG06E 0x6e
+#define RADIO_2064_REG06F 0x6f
+#define RADIO_2064_REG070 0x70
+#define RADIO_2064_REG071 0x71
+#define RADIO_2064_REG072 0x72
+#define RADIO_2064_REG073 0x73
+#define RADIO_2064_REG074 0x74
+#define RADIO_2064_REG075 0x75
+#define RADIO_2064_REG076 0x76
+#define RADIO_2064_REG077 0x77
+#define RADIO_2064_REG078 0x78
+#define RADIO_2064_REG079 0x79
+#define RADIO_2064_REG07A 0x7a
+#define RADIO_2064_REG07B 0x7b
+#define RADIO_2064_REG07C 0x7c
+#define RADIO_2064_REG07D 0x7d
+#define RADIO_2064_REG07E 0x7e
+#define RADIO_2064_REG07F 0x7f
+#define RADIO_2064_REG080 0x80
+#define RADIO_2064_REG081 0x81
+#define RADIO_2064_REG082 0x82
+#define RADIO_2064_REG083 0x83
+#define RADIO_2064_REG084 0x84
+#define RADIO_2064_REG085 0x85
+#define RADIO_2064_REG086 0x86
+#define RADIO_2064_REG087 0x87
+#define RADIO_2064_REG088 0x88
+#define RADIO_2064_REG089 0x89
+#define RADIO_2064_REG08A 0x8a
+#define RADIO_2064_REG08B 0x8b
+#define RADIO_2064_REG08C 0x8c
+#define RADIO_2064_REG08D 0x8d
+#define RADIO_2064_REG08E 0x8e
+#define RADIO_2064_REG08F 0x8f
+#define RADIO_2064_REG090 0x90
+#define RADIO_2064_REG091 0x91
+#define RADIO_2064_REG092 0x92
+#define RADIO_2064_REG093 0x93
+#define RADIO_2064_REG094 0x94
+#define RADIO_2064_REG095 0x95
+#define RADIO_2064_REG096 0x96
+#define RADIO_2064_REG097 0x97
+#define RADIO_2064_REG098 0x98
+#define RADIO_2064_REG099 0x99
+#define RADIO_2064_REG09A 0x9a
+#define RADIO_2064_REG09B 0x9b
+#define RADIO_2064_REG09C 0x9c
+#define RADIO_2064_REG09D 0x9d
+#define RADIO_2064_REG09E 0x9e
+#define RADIO_2064_REG09F 0x9f
+#define RADIO_2064_REG0A0 0xa0
+#define RADIO_2064_REG0A1 0xa1
+#define RADIO_2064_REG0A2 0xa2
+#define RADIO_2064_REG0A3 0xa3
+#define RADIO_2064_REG0A4 0xa4
+#define RADIO_2064_REG0A5 0xa5
+#define RADIO_2064_REG0A6 0xa6
+#define RADIO_2064_REG0A7 0xa7
+#define RADIO_2064_REG0A8 0xa8
+#define RADIO_2064_REG0A9 0xa9
+#define RADIO_2064_REG0AA 0xaa
+#define RADIO_2064_REG0AB 0xab
+#define RADIO_2064_REG0AC 0xac
+#define RADIO_2064_REG0AD 0xad
+#define RADIO_2064_REG0AE 0xae
+#define RADIO_2064_REG0AF 0xaf
+#define RADIO_2064_REG0B0 0xb0
+#define RADIO_2064_REG0B1 0xb1
+#define RADIO_2064_REG0B2 0xb2
+#define RADIO_2064_REG0B3 0xb3
+#define RADIO_2064_REG0B4 0xb4
+#define RADIO_2064_REG0B5 0xb5
+#define RADIO_2064_REG0B6 0xb6
+#define RADIO_2064_REG0B7 0xb7
+#define RADIO_2064_REG0B8 0xb8
+#define RADIO_2064_REG0B9 0xb9
+#define RADIO_2064_REG0BA 0xba
+#define RADIO_2064_REG0BB 0xbb
+#define RADIO_2064_REG0BC 0xbc
+#define RADIO_2064_REG0BD 0xbd
+#define RADIO_2064_REG0BE 0xbe
+#define RADIO_2064_REG0BF 0xbf
+#define RADIO_2064_REG0C0 0xc0
+#define RADIO_2064_REG0C1 0xc1
+#define RADIO_2064_REG0C2 0xc2
+#define RADIO_2064_REG0C3 0xc3
+#define RADIO_2064_REG0C4 0xc4
+#define RADIO_2064_REG0C5 0xc5
+#define RADIO_2064_REG0C6 0xc6
+#define RADIO_2064_REG0C7 0xc7
+#define RADIO_2064_REG0C8 0xc8
+#define RADIO_2064_REG0C9 0xc9
+#define RADIO_2064_REG0CA 0xca
+#define RADIO_2064_REG0CB 0xcb
+#define RADIO_2064_REG0CC 0xcc
+#define RADIO_2064_REG0CD 0xcd
+#define RADIO_2064_REG0CE 0xce
+#define RADIO_2064_REG0CF 0xcf
+#define RADIO_2064_REG0D0 0xd0
+#define RADIO_2064_REG0D1 0xd1
+#define RADIO_2064_REG0D2 0xd2
+#define RADIO_2064_REG0D3 0xd3
+#define RADIO_2064_REG0D4 0xd4
+#define RADIO_2064_REG0D5 0xd5
+#define RADIO_2064_REG0D6 0xd6
+#define RADIO_2064_REG0D7 0xd7
+#define RADIO_2064_REG0D8 0xd8
+#define RADIO_2064_REG0D9 0xd9
+#define RADIO_2064_REG0DA 0xda
+#define RADIO_2064_REG0DB 0xdb
+#define RADIO_2064_REG0DC 0xdc
+#define RADIO_2064_REG0DD 0xdd
+#define RADIO_2064_REG0DE 0xde
+#define RADIO_2064_REG0DF 0xdf
+#define RADIO_2064_REG0E0 0xe0
+#define RADIO_2064_REG0E1 0xe1
+#define RADIO_2064_REG0E2 0xe2
+#define RADIO_2064_REG0E3 0xe3
+#define RADIO_2064_REG0E4 0xe4
+#define RADIO_2064_REG0E5 0xe5
+#define RADIO_2064_REG0E6 0xe6
+#define RADIO_2064_REG0E7 0xe7
+#define RADIO_2064_REG0E8 0xe8
+#define RADIO_2064_REG0E9 0xe9
+#define RADIO_2064_REG0EA 0xea
+#define RADIO_2064_REG0EB 0xeb
+#define RADIO_2064_REG0EC 0xec
+#define RADIO_2064_REG0ED 0xed
+#define RADIO_2064_REG0EE 0xee
+#define RADIO_2064_REG0EF 0xef
+#define RADIO_2064_REG0F0 0xf0
+#define RADIO_2064_REG0F1 0xf1
+#define RADIO_2064_REG0F2 0xf2
+#define RADIO_2064_REG0F3 0xf3
+#define RADIO_2064_REG0F4 0xf4
+#define RADIO_2064_REG0F5 0xf5
+#define RADIO_2064_REG0F6 0xf6
+#define RADIO_2064_REG0F7 0xf7
+#define RADIO_2064_REG0F8 0xf8
+#define RADIO_2064_REG0F9 0xf9
+#define RADIO_2064_REG0FA 0xfa
+#define RADIO_2064_REG0FB 0xfb
+#define RADIO_2064_REG0FC 0xfc
+#define RADIO_2064_REG0FD 0xfd
+#define RADIO_2064_REG0FE 0xfe
+#define RADIO_2064_REG0FF 0xff
+#define RADIO_2064_REG100 0x100
+#define RADIO_2064_REG101 0x101
+#define RADIO_2064_REG102 0x102
+#define RADIO_2064_REG103 0x103
+#define RADIO_2064_REG104 0x104
+#define RADIO_2064_REG105 0x105
+#define RADIO_2064_REG106 0x106
+#define RADIO_2064_REG107 0x107
+#define RADIO_2064_REG108 0x108
+#define RADIO_2064_REG109 0x109
+#define RADIO_2064_REG10A 0x10a
+#define RADIO_2064_REG10B 0x10b
+#define RADIO_2064_REG10C 0x10c
+#define RADIO_2064_REG10D 0x10d
+#define RADIO_2064_REG10E 0x10e
+#define RADIO_2064_REG10F 0x10f
+#define RADIO_2064_REG110 0x110
+#define RADIO_2064_REG111 0x111
+#define RADIO_2064_REG112 0x112
+#define RADIO_2064_REG113 0x113
+#define RADIO_2064_REG114 0x114
+#define RADIO_2064_REG115 0x115
+#define RADIO_2064_REG116 0x116
+#define RADIO_2064_REG117 0x117
+#define RADIO_2064_REG118 0x118
+#define RADIO_2064_REG119 0x119
+#define RADIO_2064_REG11A 0x11a
+#define RADIO_2064_REG11B 0x11b
+#define RADIO_2064_REG11C 0x11c
+#define RADIO_2064_REG11D 0x11d
+#define RADIO_2064_REG11E 0x11e
+#define RADIO_2064_REG11F 0x11f
+#define RADIO_2064_REG120 0x120
+#define RADIO_2064_REG121 0x121
+#define RADIO_2064_REG122 0x122
+#define RADIO_2064_REG123 0x123
+#define RADIO_2064_REG124 0x124
+#define RADIO_2064_REG125 0x125
+#define RADIO_2064_REG126 0x126
+#define RADIO_2064_REG127 0x127
+#define RADIO_2064_REG128 0x128
+#define RADIO_2064_REG129 0x129
+#define RADIO_2064_REG12A 0x12a
+#define RADIO_2064_REG12B 0x12b
+#define RADIO_2064_REG12C 0x12c
+#define RADIO_2064_REG12D 0x12d
+#define RADIO_2064_REG12E 0x12e
+#define RADIO_2064_REG12F 0x12f
+#define RADIO_2064_REG130 0x130
+
+#define RADIO_2056_SYN (0x0 << 12)
+#define RADIO_2056_TX0 (0x2 << 12)
+#define RADIO_2056_TX1 (0x3 << 12)
+#define RADIO_2056_RX0 (0x6 << 12)
+#define RADIO_2056_RX1 (0x7 << 12)
+#define RADIO_2056_ALLTX (0xe << 12)
+#define RADIO_2056_ALLRX (0xf << 12)
+
+#define RADIO_2056_SYN_RESERVED_ADDR0 0x0
+#define RADIO_2056_SYN_IDCODE 0x1
+#define RADIO_2056_SYN_RESERVED_ADDR2 0x2
+#define RADIO_2056_SYN_RESERVED_ADDR3 0x3
+#define RADIO_2056_SYN_RESERVED_ADDR4 0x4
+#define RADIO_2056_SYN_RESERVED_ADDR5 0x5
+#define RADIO_2056_SYN_RESERVED_ADDR6 0x6
+#define RADIO_2056_SYN_RESERVED_ADDR7 0x7
+#define RADIO_2056_SYN_COM_CTRL 0x8
+#define RADIO_2056_SYN_COM_PU 0x9
+#define RADIO_2056_SYN_COM_OVR 0xa
+#define RADIO_2056_SYN_COM_RESET 0xb
+#define RADIO_2056_SYN_COM_RCAL 0xc
+#define RADIO_2056_SYN_COM_RC_RXLPF 0xd
+#define RADIO_2056_SYN_COM_RC_TXLPF 0xe
+#define RADIO_2056_SYN_COM_RC_RXHPF 0xf
+#define RADIO_2056_SYN_RESERVED_ADDR16 0x10
+#define RADIO_2056_SYN_RESERVED_ADDR17 0x11
+#define RADIO_2056_SYN_RESERVED_ADDR18 0x12
+#define RADIO_2056_SYN_RESERVED_ADDR19 0x13
+#define RADIO_2056_SYN_RESERVED_ADDR20 0x14
+#define RADIO_2056_SYN_RESERVED_ADDR21 0x15
+#define RADIO_2056_SYN_RESERVED_ADDR22 0x16
+#define RADIO_2056_SYN_RESERVED_ADDR23 0x17
+#define RADIO_2056_SYN_RESERVED_ADDR24 0x18
+#define RADIO_2056_SYN_RESERVED_ADDR25 0x19
+#define RADIO_2056_SYN_RESERVED_ADDR26 0x1a
+#define RADIO_2056_SYN_RESERVED_ADDR27 0x1b
+#define RADIO_2056_SYN_RESERVED_ADDR28 0x1c
+#define RADIO_2056_SYN_RESERVED_ADDR29 0x1d
+#define RADIO_2056_SYN_RESERVED_ADDR30 0x1e
+#define RADIO_2056_SYN_RESERVED_ADDR31 0x1f
+#define RADIO_2056_SYN_GPIO_MASTER1 0x20
+#define RADIO_2056_SYN_GPIO_MASTER2 0x21
+#define RADIO_2056_SYN_TOPBIAS_MASTER 0x22
+#define RADIO_2056_SYN_TOPBIAS_RCAL 0x23
+#define RADIO_2056_SYN_AFEREG 0x24
+#define RADIO_2056_SYN_TEMPPROCSENSE 0x25
+#define RADIO_2056_SYN_TEMPPROCSENSEIDAC 0x26
+#define RADIO_2056_SYN_TEMPPROCSENSERCAL 0x27
+#define RADIO_2056_SYN_LPO 0x28
+#define RADIO_2056_SYN_VDDCAL_MASTER 0x29
+#define RADIO_2056_SYN_VDDCAL_IDAC 0x2a
+#define RADIO_2056_SYN_VDDCAL_STATUS 0x2b
+#define RADIO_2056_SYN_RCAL_MASTER 0x2c
+#define RADIO_2056_SYN_RCAL_CODE_OUT 0x2d
+#define RADIO_2056_SYN_RCCAL_CTRL0 0x2e
+#define RADIO_2056_SYN_RCCAL_CTRL1 0x2f
+#define RADIO_2056_SYN_RCCAL_CTRL2 0x30
+#define RADIO_2056_SYN_RCCAL_CTRL3 0x31
+#define RADIO_2056_SYN_RCCAL_CTRL4 0x32
+#define RADIO_2056_SYN_RCCAL_CTRL5 0x33
+#define RADIO_2056_SYN_RCCAL_CTRL6 0x34
+#define RADIO_2056_SYN_RCCAL_CTRL7 0x35
+#define RADIO_2056_SYN_RCCAL_CTRL8 0x36
+#define RADIO_2056_SYN_RCCAL_CTRL9 0x37
+#define RADIO_2056_SYN_RCCAL_CTRL10 0x38
+#define RADIO_2056_SYN_RCCAL_CTRL11 0x39
+#define RADIO_2056_SYN_ZCAL_SPARE1 0x3a
+#define RADIO_2056_SYN_ZCAL_SPARE2 0x3b
+#define RADIO_2056_SYN_PLL_MAST1 0x3c
+#define RADIO_2056_SYN_PLL_MAST2 0x3d
+#define RADIO_2056_SYN_PLL_MAST3 0x3e
+#define RADIO_2056_SYN_PLL_BIAS_RESET 0x3f
+#define RADIO_2056_SYN_PLL_XTAL0 0x40
+#define RADIO_2056_SYN_PLL_XTAL1 0x41
+#define RADIO_2056_SYN_PLL_XTAL3 0x42
+#define RADIO_2056_SYN_PLL_XTAL4 0x43
+#define RADIO_2056_SYN_PLL_XTAL5 0x44
+#define RADIO_2056_SYN_PLL_XTAL6 0x45
+#define RADIO_2056_SYN_PLL_REFDIV 0x46
+#define RADIO_2056_SYN_PLL_PFD 0x47
+#define RADIO_2056_SYN_PLL_CP1 0x48
+#define RADIO_2056_SYN_PLL_CP2 0x49
+#define RADIO_2056_SYN_PLL_CP3 0x4a
+#define RADIO_2056_SYN_PLL_LOOPFILTER1 0x4b
+#define RADIO_2056_SYN_PLL_LOOPFILTER2 0x4c
+#define RADIO_2056_SYN_PLL_LOOPFILTER3 0x4d
+#define RADIO_2056_SYN_PLL_LOOPFILTER4 0x4e
+#define RADIO_2056_SYN_PLL_LOOPFILTER5 0x4f
+#define RADIO_2056_SYN_PLL_MMD1 0x50
+#define RADIO_2056_SYN_PLL_MMD2 0x51
+#define RADIO_2056_SYN_PLL_VCO1 0x52
+#define RADIO_2056_SYN_PLL_VCO2 0x53
+#define RADIO_2056_SYN_PLL_MONITOR1 0x54
+#define RADIO_2056_SYN_PLL_MONITOR2 0x55
+#define RADIO_2056_SYN_PLL_VCOCAL1 0x56
+#define RADIO_2056_SYN_PLL_VCOCAL2 0x57
+#define RADIO_2056_SYN_PLL_VCOCAL4 0x58
+#define RADIO_2056_SYN_PLL_VCOCAL5 0x59
+#define RADIO_2056_SYN_PLL_VCOCAL6 0x5a
+#define RADIO_2056_SYN_PLL_VCOCAL7 0x5b
+#define RADIO_2056_SYN_PLL_VCOCAL8 0x5c
+#define RADIO_2056_SYN_PLL_VCOCAL9 0x5d
+#define RADIO_2056_SYN_PLL_VCOCAL10 0x5e
+#define RADIO_2056_SYN_PLL_VCOCAL11 0x5f
+#define RADIO_2056_SYN_PLL_VCOCAL12 0x60
+#define RADIO_2056_SYN_PLL_VCOCAL13 0x61
+#define RADIO_2056_SYN_PLL_VREG 0x62
+#define RADIO_2056_SYN_PLL_STATUS1 0x63
+#define RADIO_2056_SYN_PLL_STATUS2 0x64
+#define RADIO_2056_SYN_PLL_STATUS3 0x65
+#define RADIO_2056_SYN_LOGEN_PU0 0x66
+#define RADIO_2056_SYN_LOGEN_PU1 0x67
+#define RADIO_2056_SYN_LOGEN_PU2 0x68
+#define RADIO_2056_SYN_LOGEN_PU3 0x69
+#define RADIO_2056_SYN_LOGEN_PU5 0x6a
+#define RADIO_2056_SYN_LOGEN_PU6 0x6b
+#define RADIO_2056_SYN_LOGEN_PU7 0x6c
+#define RADIO_2056_SYN_LOGEN_PU8 0x6d
+#define RADIO_2056_SYN_LOGEN_BIAS_RESET 0x6e
+#define RADIO_2056_SYN_LOGEN_RCCR1 0x6f
+#define RADIO_2056_SYN_LOGEN_VCOBUF1 0x70
+#define RADIO_2056_SYN_LOGEN_MIXER1 0x71
+#define RADIO_2056_SYN_LOGEN_MIXER2 0x72
+#define RADIO_2056_SYN_LOGEN_BUF1 0x73
+#define RADIO_2056_SYN_LOGENBUF2 0x74
+#define RADIO_2056_SYN_LOGEN_BUF3 0x75
+#define RADIO_2056_SYN_LOGEN_BUF4 0x76
+#define RADIO_2056_SYN_LOGEN_DIV1 0x77
+#define RADIO_2056_SYN_LOGEN_DIV2 0x78
+#define RADIO_2056_SYN_LOGEN_DIV3 0x79
+#define RADIO_2056_SYN_LOGEN_ACL1 0x7a
+#define RADIO_2056_SYN_LOGEN_ACL2 0x7b
+#define RADIO_2056_SYN_LOGEN_ACL3 0x7c
+#define RADIO_2056_SYN_LOGEN_ACL4 0x7d
+#define RADIO_2056_SYN_LOGEN_ACL5 0x7e
+#define RADIO_2056_SYN_LOGEN_ACL6 0x7f
+#define RADIO_2056_SYN_LOGEN_ACLOUT 0x80
+#define RADIO_2056_SYN_LOGEN_ACLCAL1 0x81
+#define RADIO_2056_SYN_LOGEN_ACLCAL2 0x82
+#define RADIO_2056_SYN_LOGEN_ACLCAL3 0x83
+#define RADIO_2056_SYN_CALEN 0x84
+#define RADIO_2056_SYN_LOGEN_PEAKDET1 0x85
+#define RADIO_2056_SYN_LOGEN_CORE_ACL_OVR 0x86
+#define RADIO_2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87
+#define RADIO_2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88
+#define RADIO_2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89
+#define RADIO_2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8a
+#define RADIO_2056_SYN_LOGEN_VCOBUF2 0x8b
+#define RADIO_2056_SYN_LOGEN_MIXER3 0x8c
+#define RADIO_2056_SYN_LOGEN_BUF5 0x8d
+#define RADIO_2056_SYN_LOGEN_BUF6 0x8e
+#define RADIO_2056_SYN_LOGEN_CBUFRX1 0x8f
+#define RADIO_2056_SYN_LOGEN_CBUFRX2 0x90
+#define RADIO_2056_SYN_LOGEN_CBUFRX3 0x91
+#define RADIO_2056_SYN_LOGEN_CBUFRX4 0x92
+#define RADIO_2056_SYN_LOGEN_CBUFTX1 0x93
+#define RADIO_2056_SYN_LOGEN_CBUFTX2 0x94
+#define RADIO_2056_SYN_LOGEN_CBUFTX3 0x95
+#define RADIO_2056_SYN_LOGEN_CBUFTX4 0x96
+#define RADIO_2056_SYN_LOGEN_CMOSRX1 0x97
+#define RADIO_2056_SYN_LOGEN_CMOSRX2 0x98
+#define RADIO_2056_SYN_LOGEN_CMOSRX3 0x99
+#define RADIO_2056_SYN_LOGEN_CMOSRX4 0x9a
+#define RADIO_2056_SYN_LOGEN_CMOSTX1 0x9b
+#define RADIO_2056_SYN_LOGEN_CMOSTX2 0x9c
+#define RADIO_2056_SYN_LOGEN_CMOSTX3 0x9d
+#define RADIO_2056_SYN_LOGEN_CMOSTX4 0x9e
+#define RADIO_2056_SYN_LOGEN_VCOBUF2_OVRVAL 0x9f
+#define RADIO_2056_SYN_LOGEN_MIXER3_OVRVAL 0xa0
+#define RADIO_2056_SYN_LOGEN_BUF5_OVRVAL 0xa1
+#define RADIO_2056_SYN_LOGEN_BUF6_OVRVAL 0xa2
+#define RADIO_2056_SYN_LOGEN_CBUFRX1_OVRVAL 0xa3
+#define RADIO_2056_SYN_LOGEN_CBUFRX2_OVRVAL 0xa4
+#define RADIO_2056_SYN_LOGEN_CBUFRX3_OVRVAL 0xa5
+#define RADIO_2056_SYN_LOGEN_CBUFRX4_OVRVAL 0xa6
+#define RADIO_2056_SYN_LOGEN_CBUFTX1_OVRVAL 0xa7
+#define RADIO_2056_SYN_LOGEN_CBUFTX2_OVRVAL 0xa8
+#define RADIO_2056_SYN_LOGEN_CBUFTX3_OVRVAL 0xa9
+#define RADIO_2056_SYN_LOGEN_CBUFTX4_OVRVAL 0xaa
+#define RADIO_2056_SYN_LOGEN_CMOSRX1_OVRVAL 0xab
+#define RADIO_2056_SYN_LOGEN_CMOSRX2_OVRVAL 0xac
+#define RADIO_2056_SYN_LOGEN_CMOSRX3_OVRVAL 0xad
+#define RADIO_2056_SYN_LOGEN_CMOSRX4_OVRVAL 0xae
+#define RADIO_2056_SYN_LOGEN_CMOSTX1_OVRVAL 0xaf
+#define RADIO_2056_SYN_LOGEN_CMOSTX2_OVRVAL 0xb0
+#define RADIO_2056_SYN_LOGEN_CMOSTX3_OVRVAL 0xb1
+#define RADIO_2056_SYN_LOGEN_CMOSTX4_OVRVAL 0xb2
+#define RADIO_2056_SYN_LOGEN_ACL_WAITCNT 0xb3
+#define RADIO_2056_SYN_LOGEN_CORE_CALVALID 0xb4
+#define RADIO_2056_SYN_LOGEN_RX_CMOS_CALVALID 0xb5
+#define RADIO_2056_SYN_LOGEN_TX_CMOS_VALID 0xb6
+
+#define RADIO_2056_TX_RESERVED_ADDR0 0x0
+#define RADIO_2056_TX_IDCODE 0x1
+#define RADIO_2056_TX_RESERVED_ADDR2 0x2
+#define RADIO_2056_TX_RESERVED_ADDR3 0x3
+#define RADIO_2056_TX_RESERVED_ADDR4 0x4
+#define RADIO_2056_TX_RESERVED_ADDR5 0x5
+#define RADIO_2056_TX_RESERVED_ADDR6 0x6
+#define RADIO_2056_TX_RESERVED_ADDR7 0x7
+#define RADIO_2056_TX_COM_CTRL 0x8
+#define RADIO_2056_TX_COM_PU 0x9
+#define RADIO_2056_TX_COM_OVR 0xa
+#define RADIO_2056_TX_COM_RESET 0xb
+#define RADIO_2056_TX_COM_RCAL 0xc
+#define RADIO_2056_TX_COM_RC_RXLPF 0xd
+#define RADIO_2056_TX_COM_RC_TXLPF 0xe
+#define RADIO_2056_TX_COM_RC_RXHPF 0xf
+#define RADIO_2056_TX_RESERVED_ADDR16 0x10
+#define RADIO_2056_TX_RESERVED_ADDR17 0x11
+#define RADIO_2056_TX_RESERVED_ADDR18 0x12
+#define RADIO_2056_TX_RESERVED_ADDR19 0x13
+#define RADIO_2056_TX_RESERVED_ADDR20 0x14
+#define RADIO_2056_TX_RESERVED_ADDR21 0x15
+#define RADIO_2056_TX_RESERVED_ADDR22 0x16
+#define RADIO_2056_TX_RESERVED_ADDR23 0x17
+#define RADIO_2056_TX_RESERVED_ADDR24 0x18
+#define RADIO_2056_TX_RESERVED_ADDR25 0x19
+#define RADIO_2056_TX_RESERVED_ADDR26 0x1a
+#define RADIO_2056_TX_RESERVED_ADDR27 0x1b
+#define RADIO_2056_TX_RESERVED_ADDR28 0x1c
+#define RADIO_2056_TX_RESERVED_ADDR29 0x1d
+#define RADIO_2056_TX_RESERVED_ADDR30 0x1e
+#define RADIO_2056_TX_RESERVED_ADDR31 0x1f
+#define RADIO_2056_TX_IQCAL_GAIN_BW 0x20
+#define RADIO_2056_TX_LOFT_FINE_I 0x21
+#define RADIO_2056_TX_LOFT_FINE_Q 0x22
+#define RADIO_2056_TX_LOFT_COARSE_I 0x23
+#define RADIO_2056_TX_LOFT_COARSE_Q 0x24
+#define RADIO_2056_TX_TX_COM_MASTER1 0x25
+#define RADIO_2056_TX_TX_COM_MASTER2 0x26
+#define RADIO_2056_TX_RXIQCAL_TXMUX 0x27
+#define RADIO_2056_TX_TX_SSI_MASTER 0x28
+#define RADIO_2056_TX_IQCAL_VCM_HG 0x29
+#define RADIO_2056_TX_IQCAL_IDAC 0x2a
+#define RADIO_2056_TX_TSSI_VCM 0x2b
+#define RADIO_2056_TX_TX_AMP_DET 0x2c
+#define RADIO_2056_TX_TX_SSI_MUX 0x2d
+#define RADIO_2056_TX_TSSIA 0x2e
+#define RADIO_2056_TX_TSSIG 0x2f
+#define RADIO_2056_TX_TSSI_MISC1 0x30
+#define RADIO_2056_TX_TSSI_MISC2 0x31
+#define RADIO_2056_TX_TSSI_MISC3 0x32
+#define RADIO_2056_TX_PA_SPARE1 0x33
+#define RADIO_2056_TX_PA_SPARE2 0x34
+#define RADIO_2056_TX_INTPAA_MASTER 0x35
+#define RADIO_2056_TX_INTPAA_GAIN 0x36
+#define RADIO_2056_TX_INTPAA_BOOST_TUNE 0x37
+#define RADIO_2056_TX_INTPAA_IAUX_STAT 0x38
+#define RADIO_2056_TX_INTPAA_IAUX_DYN 0x39
+#define RADIO_2056_TX_INTPAA_IMAIN_STAT 0x3a
+#define RADIO_2056_TX_INTPAA_IMAIN_DYN 0x3b
+#define RADIO_2056_TX_INTPAA_CASCBIAS 0x3c
+#define RADIO_2056_TX_INTPAA_PASLOPE 0x3d
+#define RADIO_2056_TX_INTPAA_PA_MISC 0x3e
+#define RADIO_2056_TX_INTPAG_MASTER 0x3f
+#define RADIO_2056_TX_INTPAG_GAIN 0x40
+#define RADIO_2056_TX_INTPAG_BOOST_TUNE 0x41
+#define RADIO_2056_TX_INTPAG_IAUX_STAT 0x42
+#define RADIO_2056_TX_INTPAG_IAUX_DYN 0x43
+#define RADIO_2056_TX_INTPAG_IMAIN_STAT 0x44
+#define RADIO_2056_TX_INTPAG_IMAIN_DYN 0x45
+#define RADIO_2056_TX_INTPAG_CASCBIAS 0x46
+#define RADIO_2056_TX_INTPAG_PASLOPE 0x47
+#define RADIO_2056_TX_INTPAG_PA_MISC 0x48
+#define RADIO_2056_TX_PADA_MASTER 0x49
+#define RADIO_2056_TX_PADA_IDAC 0x4a
+#define RADIO_2056_TX_PADA_CASCBIAS 0x4b
+#define RADIO_2056_TX_PADA_GAIN 0x4c
+#define RADIO_2056_TX_PADA_BOOST_TUNE 0x4d
+#define RADIO_2056_TX_PADA_SLOPE 0x4e
+#define RADIO_2056_TX_PADG_MASTER 0x4f
+#define RADIO_2056_TX_PADG_IDAC 0x50
+#define RADIO_2056_TX_PADG_CASCBIAS 0x51
+#define RADIO_2056_TX_PADG_GAIN 0x52
+#define RADIO_2056_TX_PADG_BOOST_TUNE 0x53
+#define RADIO_2056_TX_PADG_SLOPE 0x54
+#define RADIO_2056_TX_PGAA_MASTER 0x55
+#define RADIO_2056_TX_PGAA_IDAC 0x56
+#define RADIO_2056_TX_PGAA_GAIN 0x57
+#define RADIO_2056_TX_PGAA_BOOST_TUNE 0x58
+#define RADIO_2056_TX_PGAA_SLOPE 0x59
+#define RADIO_2056_TX_PGAA_MISC 0x5a
+#define RADIO_2056_TX_PGAG_MASTER 0x5b
+#define RADIO_2056_TX_PGAG_IDAC 0x5c
+#define RADIO_2056_TX_PGAG_GAIN 0x5d
+#define RADIO_2056_TX_PGAG_BOOST_TUNE 0x5e
+#define RADIO_2056_TX_PGAG_SLOPE 0x5f
+#define RADIO_2056_TX_PGAG_MISC 0x60
+#define RADIO_2056_TX_MIXA_MASTER 0x61
+#define RADIO_2056_TX_MIXA_BOOST_TUNE 0x62
+#define RADIO_2056_TX_MIXG 0x63
+#define RADIO_2056_TX_MIXG_BOOST_TUNE 0x64
+#define RADIO_2056_TX_BB_GM_MASTER 0x65
+#define RADIO_2056_TX_GMBB_GM 0x66
+#define RADIO_2056_TX_GMBB_IDAC 0x67
+#define RADIO_2056_TX_TXLPF_MASTER 0x68
+#define RADIO_2056_TX_TXLPF_RCCAL 0x69
+#define RADIO_2056_TX_TXLPF_RCCAL_OFF0 0x6a
+#define RADIO_2056_TX_TXLPF_RCCAL_OFF1 0x6b
+#define RADIO_2056_TX_TXLPF_RCCAL_OFF2 0x6c
+#define RADIO_2056_TX_TXLPF_RCCAL_OFF3 0x6d
+#define RADIO_2056_TX_TXLPF_RCCAL_OFF4 0x6e
+#define RADIO_2056_TX_TXLPF_RCCAL_OFF5 0x6f
+#define RADIO_2056_TX_TXLPF_RCCAL_OFF6 0x70
+#define RADIO_2056_TX_TXLPF_BW 0x71
+#define RADIO_2056_TX_TXLPF_GAIN 0x72
+#define RADIO_2056_TX_TXLPF_IDAC 0x73
+#define RADIO_2056_TX_TXLPF_IDAC_0 0x74
+#define RADIO_2056_TX_TXLPF_IDAC_1 0x75
+#define RADIO_2056_TX_TXLPF_IDAC_2 0x76
+#define RADIO_2056_TX_TXLPF_IDAC_3 0x77
+#define RADIO_2056_TX_TXLPF_IDAC_4 0x78
+#define RADIO_2056_TX_TXLPF_IDAC_5 0x79
+#define RADIO_2056_TX_TXLPF_IDAC_6 0x7a
+#define RADIO_2056_TX_TXLPF_OPAMP_IDAC 0x7b
+#define RADIO_2056_TX_TXLPF_MISC 0x7c
+#define RADIO_2056_TX_TXSPARE1 0x7d
+#define RADIO_2056_TX_TXSPARE2 0x7e
+#define RADIO_2056_TX_TXSPARE3 0x7f
+#define RADIO_2056_TX_TXSPARE4 0x80
+#define RADIO_2056_TX_TXSPARE5 0x81
+#define RADIO_2056_TX_TXSPARE6 0x82
+#define RADIO_2056_TX_TXSPARE7 0x83
+#define RADIO_2056_TX_TXSPARE8 0x84
+#define RADIO_2056_TX_TXSPARE9 0x85
+#define RADIO_2056_TX_TXSPARE10 0x86
+#define RADIO_2056_TX_TXSPARE11 0x87
+#define RADIO_2056_TX_TXSPARE12 0x88
+#define RADIO_2056_TX_TXSPARE13 0x89
+#define RADIO_2056_TX_TXSPARE14 0x8a
+#define RADIO_2056_TX_TXSPARE15 0x8b
+#define RADIO_2056_TX_TXSPARE16 0x8c
+#define RADIO_2056_TX_STATUS_INTPA_GAIN 0x8d
+#define RADIO_2056_TX_STATUS_PAD_GAIN 0x8e
+#define RADIO_2056_TX_STATUS_PGA_GAIN 0x8f
+#define RADIO_2056_TX_STATUS_GM_TXLPF_GAIN 0x90
+#define RADIO_2056_TX_STATUS_TXLPF_BW 0x91
+#define RADIO_2056_TX_STATUS_TXLPF_RC 0x92
+#define RADIO_2056_TX_GMBB_IDAC0 0x93
+#define RADIO_2056_TX_GMBB_IDAC1 0x94
+#define RADIO_2056_TX_GMBB_IDAC2 0x95
+#define RADIO_2056_TX_GMBB_IDAC3 0x96
+#define RADIO_2056_TX_GMBB_IDAC4 0x97
+#define RADIO_2056_TX_GMBB_IDAC5 0x98
+#define RADIO_2056_TX_GMBB_IDAC6 0x99
+#define RADIO_2056_TX_GMBB_IDAC7 0x9a
+
+#define RADIO_2056_RX_RESERVED_ADDR0 0x0
+#define RADIO_2056_RX_IDCODE 0x1
+#define RADIO_2056_RX_RESERVED_ADDR2 0x2
+#define RADIO_2056_RX_RESERVED_ADDR3 0x3
+#define RADIO_2056_RX_RESERVED_ADDR4 0x4
+#define RADIO_2056_RX_RESERVED_ADDR5 0x5
+#define RADIO_2056_RX_RESERVED_ADDR6 0x6
+#define RADIO_2056_RX_RESERVED_ADDR7 0x7
+#define RADIO_2056_RX_COM_CTRL 0x8
+#define RADIO_2056_RX_COM_PU 0x9
+#define RADIO_2056_RX_COM_OVR 0xa
+#define RADIO_2056_RX_COM_RESET 0xb
+#define RADIO_2056_RX_COM_RCAL 0xc
+#define RADIO_2056_RX_COM_RC_RXLPF 0xd
+#define RADIO_2056_RX_COM_RC_TXLPF 0xe
+#define RADIO_2056_RX_COM_RC_RXHPF 0xf
+#define RADIO_2056_RX_RESERVED_ADDR16 0x10
+#define RADIO_2056_RX_RESERVED_ADDR17 0x11
+#define RADIO_2056_RX_RESERVED_ADDR18 0x12
+#define RADIO_2056_RX_RESERVED_ADDR19 0x13
+#define RADIO_2056_RX_RESERVED_ADDR20 0x14
+#define RADIO_2056_RX_RESERVED_ADDR21 0x15
+#define RADIO_2056_RX_RESERVED_ADDR22 0x16
+#define RADIO_2056_RX_RESERVED_ADDR23 0x17
+#define RADIO_2056_RX_RESERVED_ADDR24 0x18
+#define RADIO_2056_RX_RESERVED_ADDR25 0x19
+#define RADIO_2056_RX_RESERVED_ADDR26 0x1a
+#define RADIO_2056_RX_RESERVED_ADDR27 0x1b
+#define RADIO_2056_RX_RESERVED_ADDR28 0x1c
+#define RADIO_2056_RX_RESERVED_ADDR29 0x1d
+#define RADIO_2056_RX_RESERVED_ADDR30 0x1e
+#define RADIO_2056_RX_RESERVED_ADDR31 0x1f
+#define RADIO_2056_RX_RXIQCAL_RXMUX 0x20
+#define RADIO_2056_RX_RSSI_PU 0x21
+#define RADIO_2056_RX_RSSI_SEL 0x22
+#define RADIO_2056_RX_RSSI_GAIN 0x23
+#define RADIO_2056_RX_RSSI_NB_IDAC 0x24
+#define RADIO_2056_RX_RSSI_WB2I_IDAC_1 0x25
+#define RADIO_2056_RX_RSSI_WB2I_IDAC_2 0x26
+#define RADIO_2056_RX_RSSI_WB2Q_IDAC_1 0x27
+#define RADIO_2056_RX_RSSI_WB2Q_IDAC_2 0x28
+#define RADIO_2056_RX_RSSI_POLE 0x29
+#define RADIO_2056_RX_RSSI_WB1_IDAC 0x2a
+#define RADIO_2056_RX_RSSI_MISC 0x2b
+#define RADIO_2056_RX_LNAA_MASTER 0x2c
+#define RADIO_2056_RX_LNAA_TUNE 0x2d
+#define RADIO_2056_RX_LNAA_GAIN 0x2e
+#define RADIO_2056_RX_LNA_A_SLOPE 0x2f
+#define RADIO_2056_RX_BIASPOLE_LNAA1_IDAC 0x30
+#define RADIO_2056_RX_LNAA2_IDAC 0x31
+#define RADIO_2056_RX_LNA1A_MISC 0x32
+#define RADIO_2056_RX_LNAG_MASTER 0x33
+#define RADIO_2056_RX_LNAG_TUNE 0x34
+#define RADIO_2056_RX_LNAG_GAIN 0x35
+#define RADIO_2056_RX_LNA_G_SLOPE 0x36
+#define RADIO_2056_RX_BIASPOLE_LNAG1_IDAC 0x37
+#define RADIO_2056_RX_LNAG2_IDAC 0x38
+#define RADIO_2056_RX_LNA1G_MISC 0x39
+#define RADIO_2056_RX_MIXA_MASTER 0x3a
+#define RADIO_2056_RX_MIXA_VCM 0x3b
+#define RADIO_2056_RX_MIXA_CTRLPTAT 0x3c
+#define RADIO_2056_RX_MIXA_LOB_BIAS 0x3d
+#define RADIO_2056_RX_MIXA_CORE_IDAC 0x3e
+#define RADIO_2056_RX_MIXA_CMFB_IDAC 0x3f
+#define RADIO_2056_RX_MIXA_BIAS_AUX 0x40
+#define RADIO_2056_RX_MIXA_BIAS_MAIN 0x41
+#define RADIO_2056_RX_MIXA_BIAS_MISC 0x42
+#define RADIO_2056_RX_MIXA_MAST_BIAS 0x43
+#define RADIO_2056_RX_MIXG_MASTER 0x44
+#define RADIO_2056_RX_MIXG_VCM 0x45
+#define RADIO_2056_RX_MIXG_CTRLPTAT 0x46
+#define RADIO_2056_RX_MIXG_LOB_BIAS 0x47
+#define RADIO_2056_RX_MIXG_CORE_IDAC 0x48
+#define RADIO_2056_RX_MIXG_CMFB_IDAC 0x49
+#define RADIO_2056_RX_MIXG_BIAS_AUX 0x4a
+#define RADIO_2056_RX_MIXG_BIAS_MAIN 0x4b
+#define RADIO_2056_RX_MIXG_BIAS_MISC 0x4c
+#define RADIO_2056_RX_MIXG_MAST_BIAS 0x4d
+#define RADIO_2056_RX_TIA_MASTER 0x4e
+#define RADIO_2056_RX_TIA_IOPAMP 0x4f
+#define RADIO_2056_RX_TIA_QOPAMP 0x50
+#define RADIO_2056_RX_TIA_IMISC 0x51
+#define RADIO_2056_RX_TIA_QMISC 0x52
+#define RADIO_2056_RX_TIA_GAIN 0x53
+#define RADIO_2056_RX_TIA_SPARE1 0x54
+#define RADIO_2056_RX_TIA_SPARE2 0x55
+#define RADIO_2056_RX_BB_LPF_MASTER 0x56
+#define RADIO_2056_RX_AACI_MASTER 0x57
+#define RADIO_2056_RX_RXLPF_IDAC 0x58
+#define RADIO_2056_RX_RXLPF_OPAMPBIAS_LOWQ 0x59
+#define RADIO_2056_RX_RXLPF_OPAMPBIAS_HIGHQ 0x5a
+#define RADIO_2056_RX_RXLPF_BIAS_DCCANCEL 0x5b
+#define RADIO_2056_RX_RXLPF_OUTVCM 0x5c
+#define RADIO_2056_RX_RXLPF_INVCM_BODY 0x5d
+#define RADIO_2056_RX_RXLPF_CC_OP 0x5e
+#define RADIO_2056_RX_RXLPF_GAIN 0x5f
+#define RADIO_2056_RX_RXLPF_Q_BW 0x60
+#define RADIO_2056_RX_RXLPF_HP_CORNER_BW 0x61
+#define RADIO_2056_RX_RXLPF_RCCAL_HPC 0x62
+#define RADIO_2056_RX_RXHPF_OFF0 0x63
+#define RADIO_2056_RX_RXHPF_OFF1 0x64
+#define RADIO_2056_RX_RXHPF_OFF2 0x65
+#define RADIO_2056_RX_RXHPF_OFF3 0x66
+#define RADIO_2056_RX_RXHPF_OFF4 0x67
+#define RADIO_2056_RX_RXHPF_OFF5 0x68
+#define RADIO_2056_RX_RXHPF_OFF6 0x69
+#define RADIO_2056_RX_RXHPF_OFF7 0x6a
+#define RADIO_2056_RX_RXLPF_RCCAL_LPC 0x6b
+#define RADIO_2056_RX_RXLPF_OFF_0 0x6c
+#define RADIO_2056_RX_RXLPF_OFF_1 0x6d
+#define RADIO_2056_RX_RXLPF_OFF_2 0x6e
+#define RADIO_2056_RX_RXLPF_OFF_3 0x6f
+#define RADIO_2056_RX_RXLPF_OFF_4 0x70
+#define RADIO_2056_RX_UNUSED 0x71
+#define RADIO_2056_RX_VGA_MASTER 0x72
+#define RADIO_2056_RX_VGA_BIAS 0x73
+#define RADIO_2056_RX_VGA_BIAS_DCCANCEL 0x74
+#define RADIO_2056_RX_VGA_GAIN 0x75
+#define RADIO_2056_RX_VGA_HP_CORNER_BW 0x76
+#define RADIO_2056_RX_VGABUF_BIAS 0x77
+#define RADIO_2056_RX_VGABUF_GAIN_BW 0x78
+#define RADIO_2056_RX_TXFBMIX_A 0x79
+#define RADIO_2056_RX_TXFBMIX_G 0x7a
+#define RADIO_2056_RX_RXSPARE1 0x7b
+#define RADIO_2056_RX_RXSPARE2 0x7c
+#define RADIO_2056_RX_RXSPARE3 0x7d
+#define RADIO_2056_RX_RXSPARE4 0x7e
+#define RADIO_2056_RX_RXSPARE5 0x7f
+#define RADIO_2056_RX_RXSPARE6 0x80
+#define RADIO_2056_RX_RXSPARE7 0x81
+#define RADIO_2056_RX_RXSPARE8 0x82
+#define RADIO_2056_RX_RXSPARE9 0x83
+#define RADIO_2056_RX_RXSPARE10 0x84
+#define RADIO_2056_RX_RXSPARE11 0x85
+#define RADIO_2056_RX_RXSPARE12 0x86
+#define RADIO_2056_RX_RXSPARE13 0x87
+#define RADIO_2056_RX_RXSPARE14 0x88
+#define RADIO_2056_RX_RXSPARE15 0x89
+#define RADIO_2056_RX_RXSPARE16 0x8a
+#define RADIO_2056_RX_STATUS_LNAA_GAIN 0x8b
+#define RADIO_2056_RX_STATUS_LNAG_GAIN 0x8c
+#define RADIO_2056_RX_STATUS_MIXTIA_GAIN 0x8d
+#define RADIO_2056_RX_STATUS_RXLPF_GAIN 0x8e
+#define RADIO_2056_RX_STATUS_VGA_BUF_GAIN 0x8f
+#define RADIO_2056_RX_STATUS_RXLPF_Q 0x90
+#define RADIO_2056_RX_STATUS_RXLPF_BUF_BW 0x91
+#define RADIO_2056_RX_STATUS_RXLPF_VGA_HPC 0x92
+#define RADIO_2056_RX_STATUS_RXLPF_RC 0x93
+#define RADIO_2056_RX_STATUS_HPC_RC 0x94
+
+#define RADIO_2056_LNA1_A_PU 0x01
+#define RADIO_2056_LNA2_A_PU 0x02
+#define RADIO_2056_LNA1_G_PU 0x01
+#define RADIO_2056_LNA2_G_PU 0x02
+#define RADIO_2056_MIXA_PU_I 0x01
+#define RADIO_2056_MIXA_PU_Q 0x02
+#define RADIO_2056_MIXA_PU_GM 0x10
+#define RADIO_2056_MIXG_PU_I 0x01
+#define RADIO_2056_MIXG_PU_Q 0x02
+#define RADIO_2056_MIXG_PU_GM 0x10
+#define RADIO_2056_TIA_PU 0x01
+#define RADIO_2056_BB_LPF_PU 0x20
+#define RADIO_2056_W1_PU 0x02
+#define RADIO_2056_W2_PU 0x04
+#define RADIO_2056_NB_PU 0x08
+#define RADIO_2056_RSSI_W1_SEL 0x02
+#define RADIO_2056_RSSI_W2_SEL 0x04
+#define RADIO_2056_RSSI_NB_SEL 0x08
+#define RADIO_2056_VCM_MASK 0x1c
+#define RADIO_2056_RSSI_VCM_SHIFT 0x02
+
+#define RADIO_2057_DACBUF_VINCM_CORE0 0x0
+#define RADIO_2057_IDCODE 0x1
+#define RADIO_2057_RCCAL_MASTER 0x2
+#define RADIO_2057_RCCAL_CAP_SIZE 0x3
+#define RADIO_2057_RCAL_CONFIG 0x4
+#define RADIO_2057_GPAIO_CONFIG 0x5
+#define RADIO_2057_GPAIO_SEL1 0x6
+#define RADIO_2057_GPAIO_SEL0 0x7
+#define RADIO_2057_CLPO_CONFIG 0x8
+#define RADIO_2057_BANDGAP_CONFIG 0x9
+#define RADIO_2057_BANDGAP_RCAL_TRIM 0xa
+#define RADIO_2057_AFEREG_CONFIG 0xb
+#define RADIO_2057_TEMPSENSE_CONFIG 0xc
+#define RADIO_2057_XTAL_CONFIG1 0xd
+#define RADIO_2057_XTAL_ICORE_SIZE 0xe
+#define RADIO_2057_XTAL_BUF_SIZE 0xf
+#define RADIO_2057_XTAL_PULLCAP_SIZE 0x10
+#define RADIO_2057_RFPLL_MASTER 0x11
+#define RADIO_2057_VCOMONITOR_VTH_L 0x12
+#define RADIO_2057_VCOMONITOR_VTH_H 0x13
+#define RADIO_2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x14
+#define RADIO_2057_VCO_VARCSIZE_IDAC 0x15
+#define RADIO_2057_VCOCAL_COUNTVAL0 0x16
+#define RADIO_2057_VCOCAL_COUNTVAL1 0x17
+#define RADIO_2057_VCOCAL_INTCLK_COUNT 0x18
+#define RADIO_2057_VCOCAL_MASTER 0x19
+#define RADIO_2057_VCOCAL_NUMCAPCHANGE 0x1a
+#define RADIO_2057_VCOCAL_WINSIZE 0x1b
+#define RADIO_2057_VCOCAL_DELAY_AFTER_REFRESH 0x1c
+#define RADIO_2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x1d
+#define RADIO_2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x1e
+#define RADIO_2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x1f
+#define RADIO_2057_VCO_FORCECAPEN_FORCECAP1 0x20
+#define RADIO_2057_VCO_FORCECAP0 0x21
+#define RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x22
+#define RADIO_2057_RFPLL_PFD_RESET_PW 0x23
+#define RADIO_2057_RFPLL_LOOPFILTER_R2 0x24
+#define RADIO_2057_RFPLL_LOOPFILTER_R1 0x25
+#define RADIO_2057_RFPLL_LOOPFILTER_C3 0x26
+#define RADIO_2057_RFPLL_LOOPFILTER_C2 0x27
+#define RADIO_2057_RFPLL_LOOPFILTER_C1 0x28
+#define RADIO_2057_CP_KPD_IDAC 0x29
+#define RADIO_2057_RFPLL_IDACS 0x2a
+#define RADIO_2057_RFPLL_MISC_EN 0x2b
+#define RADIO_2057_RFPLL_MMD0 0x2c
+#define RADIO_2057_RFPLL_MMD1 0x2d
+#define RADIO_2057_RFPLL_MISC_CAL_RESETN 0x2e
+#define RADIO_2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x2f
+#define RADIO_2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x30
+#define RADIO_2057_VCOCAL_READCAP0 0x31
+#define RADIO_2057_VCOCAL_READCAP1 0x32
+#define RADIO_2057_VCOCAL_STATUS 0x33
+#define RADIO_2057_LOGEN_PUS 0x34
+#define RADIO_2057_LOGEN_PTAT_RESETS 0x35
+#define RADIO_2057_VCOBUF_IDACS 0x36
+#define RADIO_2057_VCOBUF_TUNE 0x37
+#define RADIO_2057_CMOSBUF_TX2GQ_IDACS 0x38
+#define RADIO_2057_CMOSBUF_TX2GI_IDACS 0x39
+#define RADIO_2057_CMOSBUF_TX5GQ_IDACS 0x3a
+#define RADIO_2057_CMOSBUF_TX5GI_IDACS 0x3b
+#define RADIO_2057_CMOSBUF_RX2GQ_IDACS 0x3c
+#define RADIO_2057_CMOSBUF_RX2GI_IDACS 0x3d
+#define RADIO_2057_CMOSBUF_RX5GQ_IDACS 0x3e
+#define RADIO_2057_CMOSBUF_RX5GI_IDACS 0x3f
+#define RADIO_2057_LOGEN_MX2G_IDACS 0x40
+#define RADIO_2057_LOGEN_MX2G_TUNE 0x41
+#define RADIO_2057_LOGEN_MX5G_IDACS 0x42
+#define RADIO_2057_LOGEN_MX5G_TUNE 0x43
+#define RADIO_2057_LOGEN_MX5G_RCCR 0x44
+#define RADIO_2057_LOGEN_INDBUF2G_IDAC 0x45
+#define RADIO_2057_LOGEN_INDBUF2G_IBOOST 0x46
+#define RADIO_2057_LOGEN_INDBUF2G_TUNE 0x47
+#define RADIO_2057_LOGEN_INDBUF5G_IDAC 0x48
+#define RADIO_2057_LOGEN_INDBUF5G_IBOOST 0x49
+#define RADIO_2057_LOGEN_INDBUF5G_TUNE 0x4a
+#define RADIO_2057_CMOSBUF_TX_RCCR 0x4b
+#define RADIO_2057_CMOSBUF_RX_RCCR 0x4c
+#define RADIO_2057_LOGEN_SEL_PKDET 0x4d
+#define RADIO_2057_CMOSBUF_SHAREIQ_PTAT 0x4e
+#define RADIO_2057_RXTXBIAS_CONFIG_CORE0 0x4f
+#define RADIO_2057_TXGM_TXRF_PUS_CORE0 0x50
+#define RADIO_2057_TXGM_IDAC_BLEED_CORE0 0x51
+#define RADIO_2057_TXGM_GAIN_CORE0 0x56
+#define RADIO_2057_TXGM2G_PKDET_PUS_CORE0 0x57
+#define RADIO_2057_PAD2G_PTATS_CORE0 0x58
+#define RADIO_2057_PAD2G_IDACS_CORE0 0x59
+#define RADIO_2057_PAD2G_BOOST_PU_CORE0 0x5a
+#define RADIO_2057_PAD2G_CASCV_GAIN_CORE0 0x5b
+#define RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x5c
+#define RADIO_2057_TXMIX2G_LODC_CORE0 0x5d
+#define RADIO_2057_PAD2G_TUNE_PUS_CORE0 0x5e
+#define RADIO_2057_IPA2G_GAIN_CORE0 0x5f
+#define RADIO_2057_TSSI2G_SPARE1_CORE0 0x60
+#define RADIO_2057_TSSI2G_SPARE2_CORE0 0x61
+#define RADIO_2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x62
+#define RADIO_2057_IPA2G_IMAIN_CORE0 0x63
+#define RADIO_2057_IPA2G_CASCONV_CORE0 0x64
+#define RADIO_2057_IPA2G_CASCOFFV_CORE0 0x65
+#define RADIO_2057_IPA2G_BIAS_FILTER_CORE0 0x66
+#define RADIO_2057_TX5G_PKDET_CORE0 0x69
+#define RADIO_2057_PGA_PTAT_TXGM5G_PU_CORE0 0x6a
+#define RADIO_2057_PAD5G_PTATS1_CORE0 0x6b
+#define RADIO_2057_PAD5G_CLASS_PTATS2_CORE0 0x6c
+#define RADIO_2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x6d
+#define RADIO_2057_PAD5G_CASCV_IMAIN_CORE0 0x6e
+#define RADIO_2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x6f
+#define RADIO_2057_PGA_BOOST_TUNE_CORE0 0x70
+#define RADIO_2057_PGA_GAIN_CORE0 0x71
+#define RADIO_2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x72
+#define RADIO_2057_TXMIX5G_BOOST_TUNE_CORE0 0x73
+#define RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE0 0x74
+#define RADIO_2057_IPA5G_IAUX_CORE0 0x75
+#define RADIO_2057_IPA5G_GAIN_CORE0 0x76
+#define RADIO_2057_TSSI5G_SPARE1_CORE0 0x77
+#define RADIO_2057_TSSI5G_SPARE2_CORE0 0x78
+#define RADIO_2057_IPA5G_CASCOFFV_PU_CORE0 0x79
+#define RADIO_2057_IPA5G_PTAT_CORE0 0x7a
+#define RADIO_2057_IPA5G_IMAIN_CORE0 0x7b
+#define RADIO_2057_IPA5G_CASCONV_CORE0 0x7c
+#define RADIO_2057_IPA5G_BIAS_FILTER_CORE0 0x7d
+#define RADIO_2057_PAD_BIAS_FILTER_BWS_CORE0 0x80
+#define RADIO_2057_TR2G_CONFIG1_CORE0_NU 0x81
+#define RADIO_2057_TR2G_CONFIG2_CORE0_NU 0x82
+#define RADIO_2057_LNA5G_RFEN_CORE0 0x83
+#define RADIO_2057_TR5G_CONFIG2_CORE0_NU 0x84
+#define RADIO_2057_RXRFBIAS_IBOOST_PU_CORE0 0x85
+#define RADIO_2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x86
+#define RADIO_2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x87
+#define RADIO_2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x88
+#define RADIO_2057_RXMIX_CMFBITAIL_PU_CORE0 0x89
+#define RADIO_2057_LNA2_IMAIN_PTAT_PU_CORE0 0x8a
+#define RADIO_2057_LNA2_IAUX_PTAT_CORE0 0x8b
+#define RADIO_2057_LNA1_IMAIN_PTAT_PU_CORE0 0x8c
+#define RADIO_2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x8d
+#define RADIO_2057_RXRFBIAS_BANDSEL_CORE0 0x8e
+#define RADIO_2057_TIA_CONFIG_CORE0 0x8f
+#define RADIO_2057_TIA_IQGAIN_CORE0 0x90
+#define RADIO_2057_TIA_IBIAS2_CORE0 0x91
+#define RADIO_2057_TIA_IBIAS1_CORE0 0x92
+#define RADIO_2057_TIA_SPARE_Q_CORE0 0x93
+#define RADIO_2057_TIA_SPARE_I_CORE0 0x94
+#define RADIO_2057_RXMIX2G_PUS_CORE0 0x95
+#define RADIO_2057_RXMIX2G_VCMREFS_CORE0 0x96
+#define RADIO_2057_RXMIX2G_LODC_QI_CORE0 0x97
+#define RADIO_2057_W12G_BW_LNA2G_PUS_CORE0 0x98
+#define RADIO_2057_LNA2G_GAIN_CORE0 0x99
+#define RADIO_2057_LNA2G_TUNE_CORE0 0x9a
+#define RADIO_2057_RXMIX5G_PUS_CORE0 0x9b
+#define RADIO_2057_RXMIX5G_VCMREFS_CORE0 0x9c
+#define RADIO_2057_RXMIX5G_LODC_QI_CORE0 0x9d
+#define RADIO_2057_W15G_BW_LNA5G_PUS_CORE0 0x9e
+#define RADIO_2057_LNA5G_GAIN_CORE0 0x9f
+#define RADIO_2057_LNA5G_TUNE_CORE0 0xa0
+#define RADIO_2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0xa1
+#define RADIO_2057_RXBB_BIAS_MASTER_CORE0 0xa2
+#define RADIO_2057_RXBB_VGABUF_IDACS_CORE0 0xa3
+#define RADIO_2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0xa4
+#define RADIO_2057_TXBUF_VINCM_CORE0 0xa5
+#define RADIO_2057_TXBUF_IDACS_CORE0 0xa6
+#define RADIO_2057_LPF_RESP_RXBUF_BW_CORE0 0xa7
+#define RADIO_2057_RXBB_CC_CORE0 0xa8
+#define RADIO_2057_RXBB_SPARE3_CORE0 0xa9
+#define RADIO_2057_RXBB_RCCAL_HPC_CORE0 0xaa
+#define RADIO_2057_LPF_IDACS_CORE0 0xab
+#define RADIO_2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0xac
+#define RADIO_2057_TXBUF_GAIN_CORE0 0xad
+#define RADIO_2057_AFELOOPBACK_AACI_RESP_CORE0 0xae
+#define RADIO_2057_RXBUF_DEGEN_CORE0 0xaf
+#define RADIO_2057_RXBB_SPARE2_CORE0 0xb0
+#define RADIO_2057_RXBB_SPARE1_CORE0 0xb1
+#define RADIO_2057_RSSI_MASTER_CORE0 0xb2
+#define RADIO_2057_W2_MASTER_CORE0 0xb3
+#define RADIO_2057_NB_MASTER_CORE0 0xb4
+#define RADIO_2057_W2_IDACS0_Q_CORE0 0xb5
+#define RADIO_2057_W2_IDACS1_Q_CORE0 0xb6
+#define RADIO_2057_W2_IDACS0_I_CORE0 0xb7
+#define RADIO_2057_W2_IDACS1_I_CORE0 0xb8
+#define RADIO_2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0xb9
+#define RADIO_2057_NB_IDACS_Q_CORE0 0xba
+#define RADIO_2057_NB_IDACS_I_CORE0 0xbb
+#define RADIO_2057_BACKUP4_CORE0 0xc1
+#define RADIO_2057_BACKUP3_CORE0 0xc2
+#define RADIO_2057_BACKUP2_CORE0 0xc3
+#define RADIO_2057_BACKUP1_CORE0 0xc4
+#define RADIO_2057_SPARE16_CORE0 0xc5
+#define RADIO_2057_SPARE15_CORE0 0xc6
+#define RADIO_2057_SPARE14_CORE0 0xc7
+#define RADIO_2057_SPARE13_CORE0 0xc8
+#define RADIO_2057_SPARE12_CORE0 0xc9
+#define RADIO_2057_SPARE11_CORE0 0xca
+#define RADIO_2057_TX2G_BIAS_RESETS_CORE0 0xcb
+#define RADIO_2057_TX5G_BIAS_RESETS_CORE0 0xcc
+#define RADIO_2057_IQTEST_SEL_PU 0xcd
+#define RADIO_2057_XTAL_CONFIG2 0xce
+#define RADIO_2057_BUFS_MISC_LPFBW_CORE0 0xcf
+#define RADIO_2057_TXLPF_RCCAL_CORE0 0xd0
+#define RADIO_2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0xd1
+#define RADIO_2057_LPF_GAIN_CORE0 0xd2
+#define RADIO_2057_DACBUF_IDACS_BW_CORE0 0xd3
+#define RADIO_2057_RXTXBIAS_CONFIG_CORE1 0xd4
+#define RADIO_2057_TXGM_TXRF_PUS_CORE1 0xd5
+#define RADIO_2057_TXGM_IDAC_BLEED_CORE1 0xd6
+#define RADIO_2057_TXGM_GAIN_CORE1 0xdb
+#define RADIO_2057_TXGM2G_PKDET_PUS_CORE1 0xdc
+#define RADIO_2057_PAD2G_PTATS_CORE1 0xdd
+#define RADIO_2057_PAD2G_IDACS_CORE1 0xde
+#define RADIO_2057_PAD2G_BOOST_PU_CORE1 0xdf
+#define RADIO_2057_PAD2G_CASCV_GAIN_CORE1 0xe0
+#define RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0xe1
+#define RADIO_2057_TXMIX2G_LODC_CORE1 0xe2
+#define RADIO_2057_PAD2G_TUNE_PUS_CORE1 0xe3
+#define RADIO_2057_IPA2G_GAIN_CORE1 0xe4
+#define RADIO_2057_TSSI2G_SPARE1_CORE1 0xe5
+#define RADIO_2057_TSSI2G_SPARE2_CORE1 0xe6
+#define RADIO_2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0xe7
+#define RADIO_2057_IPA2G_IMAIN_CORE1 0xe8
+#define RADIO_2057_IPA2G_CASCONV_CORE1 0xe9
+#define RADIO_2057_IPA2G_CASCOFFV_CORE1 0xea
+#define RADIO_2057_IPA2G_BIAS_FILTER_CORE1 0xeb
+#define RADIO_2057_TX5G_PKDET_CORE1 0xee
+#define RADIO_2057_PGA_PTAT_TXGM5G_PU_CORE1 0xef
+#define RADIO_2057_PAD5G_PTATS1_CORE1 0xf0
+#define RADIO_2057_PAD5G_CLASS_PTATS2_CORE1 0xf1
+#define RADIO_2057_PGA_BOOSTPTAT_IMAIN_CORE1 0xf2
+#define RADIO_2057_PAD5G_CASCV_IMAIN_CORE1 0xf3
+#define RADIO_2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0xf4
+#define RADIO_2057_PGA_BOOST_TUNE_CORE1 0xf5
+#define RADIO_2057_PGA_GAIN_CORE1 0xf6
+#define RADIO_2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0xf7
+#define RADIO_2057_TXMIX5G_BOOST_TUNE_CORE1 0xf8
+#define RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE1 0xf9
+#define RADIO_2057_IPA5G_IAUX_CORE1 0xfa
+#define RADIO_2057_IPA5G_GAIN_CORE1 0xfb
+#define RADIO_2057_TSSI5G_SPARE1_CORE1 0xfc
+#define RADIO_2057_TSSI5G_SPARE2_CORE1 0xfd
+#define RADIO_2057_IPA5G_CASCOFFV_PU_CORE1 0xfe
+#define RADIO_2057_IPA5G_PTAT_CORE1 0xff
+#define RADIO_2057_IPA5G_IMAIN_CORE1 0x100
+#define RADIO_2057_IPA5G_CASCONV_CORE1 0x101
+#define RADIO_2057_IPA5G_BIAS_FILTER_CORE1 0x102
+#define RADIO_2057_PAD_BIAS_FILTER_BWS_CORE1 0x105
+#define RADIO_2057_TR2G_CONFIG1_CORE1_NU 0x106
+#define RADIO_2057_TR2G_CONFIG2_CORE1_NU 0x107
+#define RADIO_2057_LNA5G_RFEN_CORE1 0x108
+#define RADIO_2057_TR5G_CONFIG2_CORE1_NU 0x109
+#define RADIO_2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a
+#define RADIO_2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b
+#define RADIO_2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c
+#define RADIO_2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d
+#define RADIO_2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e
+#define RADIO_2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f
+#define RADIO_2057_LNA2_IAUX_PTAT_CORE1 0x110
+#define RADIO_2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111
+#define RADIO_2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112
+#define RADIO_2057_RXRFBIAS_BANDSEL_CORE1 0x113
+#define RADIO_2057_TIA_CONFIG_CORE1 0x114
+#define RADIO_2057_TIA_IQGAIN_CORE1 0x115
+#define RADIO_2057_TIA_IBIAS2_CORE1 0x116
+#define RADIO_2057_TIA_IBIAS1_CORE1 0x117
+#define RADIO_2057_TIA_SPARE_Q_CORE1 0x118
+#define RADIO_2057_TIA_SPARE_I_CORE1 0x119
+#define RADIO_2057_RXMIX2G_PUS_CORE1 0x11a
+#define RADIO_2057_RXMIX2G_VCMREFS_CORE1 0x11b
+#define RADIO_2057_RXMIX2G_LODC_QI_CORE1 0x11c
+#define RADIO_2057_W12G_BW_LNA2G_PUS_CORE1 0x11d
+#define RADIO_2057_LNA2G_GAIN_CORE1 0x11e
+#define RADIO_2057_LNA2G_TUNE_CORE1 0x11f
+#define RADIO_2057_RXMIX5G_PUS_CORE1 0x120
+#define RADIO_2057_RXMIX5G_VCMREFS_CORE1 0x121
+#define RADIO_2057_RXMIX5G_LODC_QI_CORE1 0x122
+#define RADIO_2057_W15G_BW_LNA5G_PUS_CORE1 0x123
+#define RADIO_2057_LNA5G_GAIN_CORE1 0x124
+#define RADIO_2057_LNA5G_TUNE_CORE1 0x125
+#define RADIO_2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126
+#define RADIO_2057_RXBB_BIAS_MASTER_CORE1 0x127
+#define RADIO_2057_RXBB_VGABUF_IDACS_CORE1 0x128
+#define RADIO_2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129
+#define RADIO_2057_TXBUF_VINCM_CORE1 0x12a
+#define RADIO_2057_TXBUF_IDACS_CORE1 0x12b
+#define RADIO_2057_LPF_RESP_RXBUF_BW_CORE1 0x12c
+#define RADIO_2057_RXBB_CC_CORE1 0x12d
+#define RADIO_2057_RXBB_SPARE3_CORE1 0x12e
+#define RADIO_2057_RXBB_RCCAL_HPC_CORE1 0x12f
+#define RADIO_2057_LPF_IDACS_CORE1 0x130
+#define RADIO_2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131
+#define RADIO_2057_TXBUF_GAIN_CORE1 0x132
+#define RADIO_2057_AFELOOPBACK_AACI_RESP_CORE1 0x133
+#define RADIO_2057_RXBUF_DEGEN_CORE1 0x134
+#define RADIO_2057_RXBB_SPARE2_CORE1 0x135
+#define RADIO_2057_RXBB_SPARE1_CORE1 0x136
+#define RADIO_2057_RSSI_MASTER_CORE1 0x137
+#define RADIO_2057_W2_MASTER_CORE1 0x138
+#define RADIO_2057_NB_MASTER_CORE1 0x139
+#define RADIO_2057_W2_IDACS0_Q_CORE1 0x13a
+#define RADIO_2057_W2_IDACS1_Q_CORE1 0x13b
+#define RADIO_2057_W2_IDACS0_I_CORE1 0x13c
+#define RADIO_2057_W2_IDACS1_I_CORE1 0x13d
+#define RADIO_2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e
+#define RADIO_2057_NB_IDACS_Q_CORE1 0x13f
+#define RADIO_2057_NB_IDACS_I_CORE1 0x140
+#define RADIO_2057_BACKUP4_CORE1 0x146
+#define RADIO_2057_BACKUP3_CORE1 0x147
+#define RADIO_2057_BACKUP2_CORE1 0x148
+#define RADIO_2057_BACKUP1_CORE1 0x149
+#define RADIO_2057_SPARE16_CORE1 0x14a
+#define RADIO_2057_SPARE15_CORE1 0x14b
+#define RADIO_2057_SPARE14_CORE1 0x14c
+#define RADIO_2057_SPARE13_CORE1 0x14d
+#define RADIO_2057_SPARE12_CORE1 0x14e
+#define RADIO_2057_SPARE11_CORE1 0x14f
+#define RADIO_2057_TX2G_BIAS_RESETS_CORE1 0x150
+#define RADIO_2057_TX5G_BIAS_RESETS_CORE1 0x151
+#define RADIO_2057_SPARE8_CORE1 0x152
+#define RADIO_2057_SPARE7_CORE1 0x153
+#define RADIO_2057_BUFS_MISC_LPFBW_CORE1 0x154
+#define RADIO_2057_TXLPF_RCCAL_CORE1 0x155
+#define RADIO_2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156
+#define RADIO_2057_LPF_GAIN_CORE1 0x157
+#define RADIO_2057_DACBUF_IDACS_BW_CORE1 0x158
+#define RADIO_2057_DACBUF_VINCM_CORE1 0x159
+#define RADIO_2057_RCCAL_START_R1_Q1_P1 0x15a
+#define RADIO_2057_RCCAL_X1 0x15b
+#define RADIO_2057_RCCAL_TRC0 0x15c
+#define RADIO_2057_RCCAL_TRC1 0x15d
+#define RADIO_2057_RCCAL_DONE_OSCCAP 0x15e
+#define RADIO_2057_RCCAL_N0_0 0x15f
+#define RADIO_2057_RCCAL_N0_1 0x160
+#define RADIO_2057_RCCAL_N1_0 0x161
+#define RADIO_2057_RCCAL_N1_1 0x162
+#define RADIO_2057_RCAL_STATUS 0x163
+#define RADIO_2057_XTALPUOVR_PINCTRL 0x164
+#define RADIO_2057_OVR_REG0 0x165
+#define RADIO_2057_OVR_REG1 0x166
+#define RADIO_2057_OVR_REG2 0x167
+#define RADIO_2057_OVR_REG3 0x168
+#define RADIO_2057_OVR_REG4 0x169
+#define RADIO_2057_RCCAL_SCAP_VAL 0x16a
+#define RADIO_2057_RCCAL_BCAP_VAL 0x16b
+#define RADIO_2057_RCCAL_HPC_VAL 0x16c
+#define RADIO_2057_RCCAL_OVERRIDES 0x16d
+#define RADIO_2057_TX0_IQCAL_GAIN_BW 0x170
+#define RADIO_2057_TX0_LOFT_FINE_I 0x171
+#define RADIO_2057_TX0_LOFT_FINE_Q 0x172
+#define RADIO_2057_TX0_LOFT_COARSE_I 0x173
+#define RADIO_2057_TX0_LOFT_COARSE_Q 0x174
+#define RADIO_2057_TX0_TX_SSI_MASTER 0x175
+#define RADIO_2057_TX0_IQCAL_VCM_HG 0x176
+#define RADIO_2057_TX0_IQCAL_IDAC 0x177
+#define RADIO_2057_TX0_TSSI_VCM 0x178
+#define RADIO_2057_TX0_TX_SSI_MUX 0x179
+#define RADIO_2057_TX0_TSSIA 0x17a
+#define RADIO_2057_TX0_TSSIG 0x17b
+#define RADIO_2057_TX0_TSSI_MISC1 0x17c
+#define RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d
+#define RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e
+#define RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f
+#define RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180
+#define RADIO_2057_TX1_IQCAL_GAIN_BW 0x190
+#define RADIO_2057_TX1_LOFT_FINE_I 0x191
+#define RADIO_2057_TX1_LOFT_FINE_Q 0x192
+#define RADIO_2057_TX1_LOFT_COARSE_I 0x193
+#define RADIO_2057_TX1_LOFT_COARSE_Q 0x194
+#define RADIO_2057_TX1_TX_SSI_MASTER 0x195
+#define RADIO_2057_TX1_IQCAL_VCM_HG 0x196
+#define RADIO_2057_TX1_IQCAL_IDAC 0x197
+#define RADIO_2057_TX1_TSSI_VCM 0x198
+#define RADIO_2057_TX1_TX_SSI_MUX 0x199
+#define RADIO_2057_TX1_TSSIA 0x19a
+#define RADIO_2057_TX1_TSSIG 0x19b
+#define RADIO_2057_TX1_TSSI_MISC1 0x19c
+#define RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d
+#define RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e
+#define RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f
+#define RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0
+#define RADIO_2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1
+#define RADIO_2057_AFE_SET_VCM_I_CORE0 0x1a2
+#define RADIO_2057_AFE_SET_VCM_Q_CORE0 0x1a3
+#define RADIO_2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4
+#define RADIO_2057_AFE_STATUS_VCM_I_CORE0 0x1a5
+#define RADIO_2057_AFE_STATUS_VCM_Q_CORE0 0x1a6
+#define RADIO_2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7
+#define RADIO_2057_AFE_SET_VCM_I_CORE1 0x1a8
+#define RADIO_2057_AFE_SET_VCM_Q_CORE1 0x1a9
+#define RADIO_2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa
+#define RADIO_2057_AFE_STATUS_VCM_I_CORE1 0x1ab
+#define RADIO_2057_AFE_STATUS_VCM_Q_CORE1 0x1ac
+
+#define RADIO_2057v7_DACBUF_VINCM_CORE0 0x1ad
+#define RADIO_2057v7_RCCAL_MASTER 0x1ae
+#define RADIO_2057v7_TR2G_CONFIG3_CORE0_NU 0x1af
+#define RADIO_2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0
+#define RADIO_2057v7_LOGEN_PUS1 0x1b1
+#define RADIO_2057v7_OVR_REG5 0x1b2
+#define RADIO_2057v7_OVR_REG6 0x1b3
+#define RADIO_2057v7_OVR_REG7 0x1b4
+#define RADIO_2057v7_OVR_REG8 0x1b5
+#define RADIO_2057v7_OVR_REG9 0x1b6
+#define RADIO_2057v7_OVR_REG10 0x1b7
+#define RADIO_2057v7_OVR_REG11 0x1b8
+#define RADIO_2057v7_OVR_REG12 0x1b9
+#define RADIO_2057v7_OVR_REG13 0x1ba
+#define RADIO_2057v7_OVR_REG14 0x1bb
+#define RADIO_2057v7_OVR_REG15 0x1bc
+#define RADIO_2057v7_OVR_REG16 0x1bd
+#define RADIO_2057v7_OVR_REG1 0x1be
+#define RADIO_2057v7_OVR_REG18 0x1bf
+#define RADIO_2057v7_OVR_REG19 0x1c0
+#define RADIO_2057v7_OVR_REG20 0x1c1
+#define RADIO_2057v7_OVR_REG21 0x1c2
+#define RADIO_2057v7_OVR_REG2 0x1c3
+#define RADIO_2057v7_OVR_REG23 0x1c4
+#define RADIO_2057v7_OVR_REG24 0x1c5
+#define RADIO_2057v7_OVR_REG25 0x1c6
+#define RADIO_2057v7_OVR_REG26 0x1c7
+#define RADIO_2057v7_OVR_REG27 0x1c8
+#define RADIO_2057v7_OVR_REG28 0x1c9
+#define RADIO_2057v7_IQTEST_SEL_PU2 0x1ca
+
+#define RADIO_2057_VCM_MASK 0x7
+
+#endif /* _BRCM_PHY_RADIO_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define NPHY_TBL_ID_GAIN1 0
+#define NPHY_TBL_ID_GAIN2 1
+#define NPHY_TBL_ID_GAINBITS1 2
+#define NPHY_TBL_ID_GAINBITS2 3
+#define NPHY_TBL_ID_GAINLIMIT 4
+#define NPHY_TBL_ID_WRSSIGainLimit 5
+#define NPHY_TBL_ID_RFSEQ 7
+#define NPHY_TBL_ID_AFECTRL 8
+#define NPHY_TBL_ID_ANTSWCTRLLUT 9
+#define NPHY_TBL_ID_IQLOCAL 15
+#define NPHY_TBL_ID_NOISEVAR 16
+#define NPHY_TBL_ID_SAMPLEPLAY 17
+#define NPHY_TBL_ID_CORE1TXPWRCTL 26
+#define NPHY_TBL_ID_CORE2TXPWRCTL 27
+#define NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL 30
+
+#define NPHY_TBL_ID_EPSILONTBL0 31
+#define NPHY_TBL_ID_SCALARTBL0 32
+#define NPHY_TBL_ID_EPSILONTBL1 33
+#define NPHY_TBL_ID_SCALARTBL1 34
+
+#define NPHY_TO_BPHY_OFF 0xc00
+
+#define NPHY_BandControl_currentBand 0x0001
+#define RFCC_CHIP0_PU 0x0400
+#define RFCC_POR_FORCE 0x0040
+#define RFCC_OE_POR_FORCE 0x0080
+#define NPHY_RfctrlIntc_override_OFF 0
+#define NPHY_RfctrlIntc_override_TRSW 1
+#define NPHY_RfctrlIntc_override_PA 2
+#define NPHY_RfctrlIntc_override_EXT_LNA_PU 3
+#define NPHY_RfctrlIntc_override_EXT_LNA_GAIN 4
+#define RIFS_ENABLE 0x80
+#define BPHY_BAND_SEL_UP20 0x10
+#define NPHY_MLenable 0x02
+
+#define NPHY_RfseqMode_CoreActv_override 0x0001
+#define NPHY_RfseqMode_Trigger_override 0x0002
+#define NPHY_RfseqCoreActv_TxRxChain0 (0x11)
+#define NPHY_RfseqCoreActv_TxRxChain1 (0x22)
+
+#define NPHY_RfseqTrigger_rx2tx 0x0001
+#define NPHY_RfseqTrigger_tx2rx 0x0002
+#define NPHY_RfseqTrigger_updategainh 0x0004
+#define NPHY_RfseqTrigger_updategainl 0x0008
+#define NPHY_RfseqTrigger_updategainu 0x0010
+#define NPHY_RfseqTrigger_reset2rx 0x0020
+#define NPHY_RfseqStatus_rx2tx 0x0001
+#define NPHY_RfseqStatus_tx2rx 0x0002
+#define NPHY_RfseqStatus_updategainh 0x0004
+#define NPHY_RfseqStatus_updategainl 0x0008
+#define NPHY_RfseqStatus_updategainu 0x0010
+#define NPHY_RfseqStatus_reset2rx 0x0020
+#define NPHY_ClassifierCtrl_cck_en 0x1
+#define NPHY_ClassifierCtrl_ofdm_en 0x2
+#define NPHY_ClassifierCtrl_waited_en 0x4
+#define NPHY_IQFlip_ADC1 0x0001
+#define NPHY_IQFlip_ADC2 0x0010
+#define NPHY_sampleCmd_STOP 0x0002
+
+#define RX_GF_OR_MM 0x0004
+#define RX_GF_MM_AUTO 0x0100
+
+#define NPHY_iqloCalCmdGctl_IQLO_CAL_EN 0x8000
+
+#define NPHY_IqestCmd_iqstart 0x1
+#define NPHY_IqestCmd_iqMode 0x2
+
+#define NPHY_TxPwrCtrlCmd_pwrIndex_init 0x40
+#define NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 0x19
+
+#define PRIM_SEL_UP20 0x8000
+
+#define NPHY_RFSEQ_RX2TX 0x0
+#define NPHY_RFSEQ_TX2RX 0x1
+#define NPHY_RFSEQ_RESET2RX 0x2
+#define NPHY_RFSEQ_UPDATEGAINH 0x3
+#define NPHY_RFSEQ_UPDATEGAINL 0x4
+#define NPHY_RFSEQ_UPDATEGAINU 0x5
+
+#define NPHY_RFSEQ_CMD_NOP 0x0
+#define NPHY_RFSEQ_CMD_RXG_FBW 0x1
+#define NPHY_RFSEQ_CMD_TR_SWITCH 0x2
+#define NPHY_RFSEQ_CMD_EXT_PA 0x3
+#define NPHY_RFSEQ_CMD_RXPD_TXPD 0x4
+#define NPHY_RFSEQ_CMD_TX_GAIN 0x5
+#define NPHY_RFSEQ_CMD_RX_GAIN 0x6
+#define NPHY_RFSEQ_CMD_SET_HPF_BW 0x7
+#define NPHY_RFSEQ_CMD_CLR_HIQ_DIS 0x8
+#define NPHY_RFSEQ_CMD_END 0xf
+
+#define NPHY_REV3_RFSEQ_CMD_NOP 0x0
+#define NPHY_REV3_RFSEQ_CMD_RXG_FBW 0x1
+#define NPHY_REV3_RFSEQ_CMD_TR_SWITCH 0x2
+#define NPHY_REV3_RFSEQ_CMD_INT_PA_PU 0x3
+#define NPHY_REV3_RFSEQ_CMD_EXT_PA 0x4
+#define NPHY_REV3_RFSEQ_CMD_RXPD_TXPD 0x5
+#define NPHY_REV3_RFSEQ_CMD_TX_GAIN 0x6
+#define NPHY_REV3_RFSEQ_CMD_RX_GAIN 0x7
+#define NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS 0x8
+#define NPHY_REV3_RFSEQ_CMD_SET_HPF_H_HPC 0x9
+#define NPHY_REV3_RFSEQ_CMD_SET_LPF_H_HPC 0xa
+#define NPHY_REV3_RFSEQ_CMD_SET_HPF_M_HPC 0xb
+#define NPHY_REV3_RFSEQ_CMD_SET_LPF_M_HPC 0xc
+#define NPHY_REV3_RFSEQ_CMD_SET_HPF_L_HPC 0xd
+#define NPHY_REV3_RFSEQ_CMD_SET_LPF_L_HPC 0xe
+#define NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS 0xf
+#define NPHY_REV3_RFSEQ_CMD_END 0x1f
+
+#define NPHY_RSSI_SEL_W1 0x0
+#define NPHY_RSSI_SEL_W2 0x1
+#define NPHY_RSSI_SEL_NB 0x2
+#define NPHY_RSSI_SEL_IQ 0x3
+#define NPHY_RSSI_SEL_TSSI_2G 0x4
+#define NPHY_RSSI_SEL_TSSI_5G 0x5
+#define NPHY_RSSI_SEL_TBD 0x6
+
+#define NPHY_RAIL_I 0x0
+#define NPHY_RAIL_Q 0x1
+
+#define NPHY_FORCESIG_DECODEGATEDCLKS 0x8
+
+#define NPHY_REV7_RfctrlOverride_cmd_rxrf_pu 0x0
+#define NPHY_REV7_RfctrlOverride_cmd_rx_pu 0x1
+#define NPHY_REV7_RfctrlOverride_cmd_tx_pu 0x2
+#define NPHY_REV7_RfctrlOverride_cmd_rxgain 0x3
+#define NPHY_REV7_RfctrlOverride_cmd_txgain 0x4
+
+#define NPHY_REV7_RXGAINCODE_RFMXGAIN_MASK 0x000ff
+#define NPHY_REV7_RXGAINCODE_LPFGAIN_MASK 0x0ff00
+#define NPHY_REV7_RXGAINCODE_DVGAGAIN_MASK 0xf0000
+
+#define NPHY_REV7_TXGAINCODE_TGAIN_MASK 0x7fff
+#define NPHY_REV7_TXGAINCODE_LPFGAIN_MASK 0x8000
+#define NPHY_REV7_TXGAINCODE_BIQ0GAIN_SHIFT 14
+
+#define NPHY_REV7_RFCTRLOVERRIDE_ID0 0x0
+#define NPHY_REV7_RFCTRLOVERRIDE_ID1 0x1
+#define NPHY_REV7_RFCTRLOVERRIDE_ID2 0x2
+
+#define NPHY_IqestIqAccLo(core) ((core == 0) ? 0x12c : 0x134)
+
+#define NPHY_IqestIqAccHi(core) ((core == 0) ? 0x12d : 0x135)
+
+#define NPHY_IqestipwrAccLo(core) ((core == 0) ? 0x12e : 0x136)
+
+#define NPHY_IqestipwrAccHi(core) ((core == 0) ? 0x12f : 0x137)
+
+#define NPHY_IqestqpwrAccLo(core) ((core == 0) ? 0x130 : 0x138)
+
+#define NPHY_IqestqpwrAccHi(core) ((core == 0) ? 0x131 : 0x139)
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/types.h>
+#include <dma.h>
+#include <phy_int.h>
+#include <phytbl_lcn.h>
+
+const u32 dot11lcn_gain_tbl_rev0[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000004,
+ 0x00000008,
+ 0x00000001,
+ 0x00000005,
+ 0x00000009,
+ 0x0000000d,
+ 0x0000004d,
+ 0x0000008d,
+ 0x0000000d,
+ 0x0000004d,
+ 0x0000008d,
+ 0x000000cd,
+ 0x0000004f,
+ 0x0000008f,
+ 0x000000cf,
+ 0x000000d3,
+ 0x00000113,
+ 0x00000513,
+ 0x00000913,
+ 0x00000953,
+ 0x00000d53,
+ 0x00001153,
+ 0x00001193,
+ 0x00005193,
+ 0x00009193,
+ 0x0000d193,
+ 0x00011193,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000000,
+ 0x00000004,
+ 0x00000008,
+ 0x00000001,
+ 0x00000005,
+ 0x00000009,
+ 0x0000000d,
+ 0x0000004d,
+ 0x0000008d,
+ 0x0000000d,
+ 0x0000004d,
+ 0x0000008d,
+ 0x000000cd,
+ 0x0000004f,
+ 0x0000008f,
+ 0x000000cf,
+ 0x000000d3,
+ 0x00000113,
+ 0x00000513,
+ 0x00000913,
+ 0x00000953,
+ 0x00000d53,
+ 0x00001153,
+ 0x00005153,
+ 0x00009153,
+ 0x0000d153,
+ 0x00011153,
+ 0x00015153,
+ 0x00019153,
+ 0x0001d153,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 dot11lcn_gain_tbl_rev1[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000008,
+ 0x00000004,
+ 0x00000008,
+ 0x00000001,
+ 0x00000005,
+ 0x00000009,
+ 0x0000000D,
+ 0x00000011,
+ 0x00000051,
+ 0x00000091,
+ 0x00000011,
+ 0x00000051,
+ 0x00000091,
+ 0x000000d1,
+ 0x00000053,
+ 0x00000093,
+ 0x000000d3,
+ 0x000000d7,
+ 0x00000117,
+ 0x00000517,
+ 0x00000917,
+ 0x00000957,
+ 0x00000d57,
+ 0x00001157,
+ 0x00001197,
+ 0x00005197,
+ 0x00009197,
+ 0x0000d197,
+ 0x00011197,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000008,
+ 0x00000004,
+ 0x00000008,
+ 0x00000001,
+ 0x00000005,
+ 0x00000009,
+ 0x0000000D,
+ 0x00000011,
+ 0x00000051,
+ 0x00000091,
+ 0x00000011,
+ 0x00000051,
+ 0x00000091,
+ 0x000000d1,
+ 0x00000053,
+ 0x00000093,
+ 0x000000d3,
+ 0x000000d7,
+ 0x00000117,
+ 0x00000517,
+ 0x00000917,
+ 0x00000957,
+ 0x00000d57,
+ 0x00001157,
+ 0x00005157,
+ 0x00009157,
+ 0x0000d157,
+ 0x00011157,
+ 0x00015157,
+ 0x00019157,
+ 0x0001d157,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u16 dot11lcn_aux_gain_idx_tbl_rev0[] = {
+ 0x0401,
+ 0x0402,
+ 0x0403,
+ 0x0404,
+ 0x0405,
+ 0x0406,
+ 0x0407,
+ 0x0408,
+ 0x0409,
+ 0x040a,
+ 0x058b,
+ 0x058c,
+ 0x058d,
+ 0x058e,
+ 0x058f,
+ 0x0090,
+ 0x0091,
+ 0x0092,
+ 0x0193,
+ 0x0194,
+ 0x0195,
+ 0x0196,
+ 0x0197,
+ 0x0198,
+ 0x0199,
+ 0x019a,
+ 0x019b,
+ 0x019c,
+ 0x019d,
+ 0x019e,
+ 0x019f,
+ 0x01a0,
+ 0x01a1,
+ 0x01a2,
+ 0x01a3,
+ 0x01a4,
+ 0x01a5,
+ 0x0000,
+};
+
+const u32 dot11lcn_gain_idx_tbl_rev0[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x10000000,
+ 0x00000000,
+ 0x20000000,
+ 0x00000000,
+ 0x30000000,
+ 0x00000000,
+ 0x40000000,
+ 0x00000000,
+ 0x50000000,
+ 0x00000000,
+ 0x60000000,
+ 0x00000000,
+ 0x70000000,
+ 0x00000000,
+ 0x80000000,
+ 0x00000000,
+ 0x90000000,
+ 0x00000008,
+ 0xa0000000,
+ 0x00000008,
+ 0xb0000000,
+ 0x00000008,
+ 0xc0000000,
+ 0x00000008,
+ 0xd0000000,
+ 0x00000008,
+ 0xe0000000,
+ 0x00000008,
+ 0xf0000000,
+ 0x00000008,
+ 0x00000000,
+ 0x00000009,
+ 0x10000000,
+ 0x00000009,
+ 0x20000000,
+ 0x00000019,
+ 0x30000000,
+ 0x00000019,
+ 0x40000000,
+ 0x00000019,
+ 0x50000000,
+ 0x00000019,
+ 0x60000000,
+ 0x00000019,
+ 0x70000000,
+ 0x00000019,
+ 0x80000000,
+ 0x00000019,
+ 0x90000000,
+ 0x00000019,
+ 0xa0000000,
+ 0x00000019,
+ 0xb0000000,
+ 0x00000019,
+ 0xc0000000,
+ 0x00000019,
+ 0xd0000000,
+ 0x00000019,
+ 0xe0000000,
+ 0x00000019,
+ 0xf0000000,
+ 0x00000019,
+ 0x00000000,
+ 0x0000001a,
+ 0x10000000,
+ 0x0000001a,
+ 0x20000000,
+ 0x0000001a,
+ 0x30000000,
+ 0x0000001a,
+ 0x40000000,
+ 0x0000001a,
+ 0x50000000,
+ 0x00000002,
+ 0x60000000,
+ 0x00000002,
+ 0x70000000,
+ 0x00000002,
+ 0x80000000,
+ 0x00000002,
+ 0x90000000,
+ 0x00000002,
+ 0xa0000000,
+ 0x00000002,
+ 0xb0000000,
+ 0x00000002,
+ 0xc0000000,
+ 0x0000000a,
+ 0xd0000000,
+ 0x0000000a,
+ 0xe0000000,
+ 0x0000000a,
+ 0xf0000000,
+ 0x0000000a,
+ 0x00000000,
+ 0x0000000b,
+ 0x10000000,
+ 0x0000000b,
+ 0x20000000,
+ 0x0000000b,
+ 0x30000000,
+ 0x0000000b,
+ 0x40000000,
+ 0x0000000b,
+ 0x50000000,
+ 0x0000001b,
+ 0x60000000,
+ 0x0000001b,
+ 0x70000000,
+ 0x0000001b,
+ 0x80000000,
+ 0x0000001b,
+ 0x90000000,
+ 0x0000001b,
+ 0xa0000000,
+ 0x0000001b,
+ 0xb0000000,
+ 0x0000001b,
+ 0xc0000000,
+ 0x0000001b,
+ 0xd0000000,
+ 0x0000001b,
+ 0xe0000000,
+ 0x0000001b,
+ 0xf0000000,
+ 0x0000001b,
+ 0x00000000,
+ 0x0000001c,
+ 0x10000000,
+ 0x0000001c,
+ 0x20000000,
+ 0x0000001c,
+ 0x30000000,
+ 0x0000001c,
+ 0x40000000,
+ 0x0000001c,
+ 0x50000000,
+ 0x0000001c,
+ 0x60000000,
+ 0x0000001c,
+ 0x70000000,
+ 0x0000001c,
+ 0x80000000,
+ 0x0000001c,
+ 0x90000000,
+ 0x0000001c,
+};
+
+const u16 dot11lcn_aux_gain_idx_tbl_2G[] = {
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0001,
+ 0x0080,
+ 0x0081,
+ 0x0100,
+ 0x0101,
+ 0x0180,
+ 0x0181,
+ 0x0182,
+ 0x0183,
+ 0x0184,
+ 0x0185,
+ 0x0186,
+ 0x0187,
+ 0x0188,
+ 0x0285,
+ 0x0289,
+ 0x028a,
+ 0x028b,
+ 0x028c,
+ 0x028d,
+ 0x028e,
+ 0x028f,
+ 0x0290,
+ 0x0291,
+ 0x0292,
+ 0x0293,
+ 0x0294,
+ 0x0295,
+ 0x0296,
+ 0x0297,
+ 0x0298,
+ 0x0299,
+ 0x029a,
+ 0x0000
+};
+
+const u8 dot11lcn_gain_val_tbl_2G[] = {
+ 0xfc,
+ 0x02,
+ 0x08,
+ 0x0e,
+ 0x13,
+ 0x1b,
+ 0xfc,
+ 0x02,
+ 0x08,
+ 0x0e,
+ 0x13,
+ 0x1b,
+ 0xfc,
+ 0x00,
+ 0x0c,
+ 0x03,
+ 0xeb,
+ 0xfe,
+ 0x07,
+ 0x0b,
+ 0x0f,
+ 0xfb,
+ 0xfe,
+ 0x01,
+ 0x05,
+ 0x08,
+ 0x0b,
+ 0x0e,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x15,
+ 0x18,
+ 0x1b,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00
+};
+
+const u32 dot11lcn_gain_idx_tbl_2G[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000008,
+ 0x10000000,
+ 0x00000008,
+ 0x00000000,
+ 0x00000010,
+ 0x10000000,
+ 0x00000010,
+ 0x00000000,
+ 0x00000018,
+ 0x10000000,
+ 0x00000018,
+ 0x20000000,
+ 0x00000018,
+ 0x30000000,
+ 0x00000018,
+ 0x40000000,
+ 0x00000018,
+ 0x50000000,
+ 0x00000018,
+ 0x60000000,
+ 0x00000018,
+ 0x70000000,
+ 0x00000018,
+ 0x80000000,
+ 0x00000018,
+ 0x50000000,
+ 0x00000028,
+ 0x90000000,
+ 0x00000028,
+ 0xa0000000,
+ 0x00000028,
+ 0xb0000000,
+ 0x00000028,
+ 0xc0000000,
+ 0x00000028,
+ 0xd0000000,
+ 0x00000028,
+ 0xe0000000,
+ 0x00000028,
+ 0xf0000000,
+ 0x00000028,
+ 0x00000000,
+ 0x00000029,
+ 0x10000000,
+ 0x00000029,
+ 0x20000000,
+ 0x00000029,
+ 0x30000000,
+ 0x00000029,
+ 0x40000000,
+ 0x00000029,
+ 0x50000000,
+ 0x00000029,
+ 0x60000000,
+ 0x00000029,
+ 0x70000000,
+ 0x00000029,
+ 0x80000000,
+ 0x00000029,
+ 0x90000000,
+ 0x00000029,
+ 0xa0000000,
+ 0x00000029,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000008,
+ 0x10000000,
+ 0x00000008,
+ 0x00000000,
+ 0x00000010,
+ 0x10000000,
+ 0x00000010,
+ 0x00000000,
+ 0x00000018,
+ 0x10000000,
+ 0x00000018,
+ 0x20000000,
+ 0x00000018,
+ 0x30000000,
+ 0x00000018,
+ 0x40000000,
+ 0x00000018,
+ 0x50000000,
+ 0x00000018,
+ 0x60000000,
+ 0x00000018,
+ 0x70000000,
+ 0x00000018,
+ 0x80000000,
+ 0x00000018,
+ 0x50000000,
+ 0x00000028,
+ 0x90000000,
+ 0x00000028,
+ 0xa0000000,
+ 0x00000028,
+ 0xb0000000,
+ 0x00000028,
+ 0xc0000000,
+ 0x00000028,
+ 0xd0000000,
+ 0x00000028,
+ 0xe0000000,
+ 0x00000028,
+ 0xf0000000,
+ 0x00000028,
+ 0x00000000,
+ 0x00000029,
+ 0x10000000,
+ 0x00000029,
+ 0x20000000,
+ 0x00000029,
+ 0x30000000,
+ 0x00000029,
+ 0x40000000,
+ 0x00000029,
+ 0x50000000,
+ 0x00000029,
+ 0x60000000,
+ 0x00000029,
+ 0x70000000,
+ 0x00000029,
+ 0x80000000,
+ 0x00000029,
+ 0x90000000,
+ 0x00000029,
+ 0xa0000000,
+ 0x00000029,
+ 0xb0000000,
+ 0x00000029,
+ 0xc0000000,
+ 0x00000029,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+const u32 dot11lcn_gain_tbl_2G[] = {
+ 0x00000000,
+ 0x00000004,
+ 0x00000008,
+ 0x00000001,
+ 0x00000005,
+ 0x00000009,
+ 0x0000000d,
+ 0x0000004d,
+ 0x0000008d,
+ 0x00000049,
+ 0x00000089,
+ 0x000000c9,
+ 0x0000004b,
+ 0x0000008b,
+ 0x000000cb,
+ 0x000000cf,
+ 0x0000010f,
+ 0x0000050f,
+ 0x0000090f,
+ 0x0000094f,
+ 0x00000d4f,
+ 0x0000114f,
+ 0x0000118f,
+ 0x0000518f,
+ 0x0000918f,
+ 0x0000d18f,
+ 0x0001118f,
+ 0x0001518f,
+ 0x0001918f,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+const u32 dot11lcn_gain_tbl_extlna_2G[] = {
+ 0x00000000,
+ 0x00000004,
+ 0x00000008,
+ 0x00000001,
+ 0x00000005,
+ 0x00000009,
+ 0x0000000d,
+ 0x00000003,
+ 0x00000007,
+ 0x0000000b,
+ 0x0000000f,
+ 0x0000004f,
+ 0x0000008f,
+ 0x000000cf,
+ 0x0000010f,
+ 0x0000014f,
+ 0x0000018f,
+ 0x0000058f,
+ 0x0000098f,
+ 0x00000d8f,
+ 0x00008000,
+ 0x00008004,
+ 0x00008008,
+ 0x00008001,
+ 0x00008005,
+ 0x00008009,
+ 0x0000800d,
+ 0x00008003,
+ 0x00008007,
+ 0x0000800b,
+ 0x0000800f,
+ 0x0000804f,
+ 0x0000808f,
+ 0x000080cf,
+ 0x0000810f,
+ 0x0000814f,
+ 0x0000818f,
+ 0x0000858f,
+ 0x0000898f,
+ 0x00008d8f,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+const u16 dot11lcn_aux_gain_idx_tbl_extlna_2G[] = {
+ 0x0400,
+ 0x0400,
+ 0x0400,
+ 0x0400,
+ 0x0400,
+ 0x0400,
+ 0x0400,
+ 0x0400,
+ 0x0400,
+ 0x0401,
+ 0x0402,
+ 0x0403,
+ 0x0404,
+ 0x0483,
+ 0x0484,
+ 0x0485,
+ 0x0486,
+ 0x0583,
+ 0x0584,
+ 0x0585,
+ 0x0587,
+ 0x0588,
+ 0x0589,
+ 0x058a,
+ 0x0687,
+ 0x0688,
+ 0x0689,
+ 0x068a,
+ 0x068b,
+ 0x068c,
+ 0x068d,
+ 0x068e,
+ 0x068f,
+ 0x0690,
+ 0x0691,
+ 0x0692,
+ 0x0693,
+ 0x0000
+};
+
+const u8 dot11lcn_gain_val_tbl_extlna_2G[] = {
+ 0xfc,
+ 0x02,
+ 0x08,
+ 0x0e,
+ 0x13,
+ 0x1b,
+ 0xfc,
+ 0x02,
+ 0x08,
+ 0x0e,
+ 0x13,
+ 0x1b,
+ 0xfc,
+ 0x00,
+ 0x0f,
+ 0x03,
+ 0xeb,
+ 0xfe,
+ 0x07,
+ 0x0b,
+ 0x0f,
+ 0xfb,
+ 0xfe,
+ 0x01,
+ 0x05,
+ 0x08,
+ 0x0b,
+ 0x0e,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x15,
+ 0x18,
+ 0x1b,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00
+};
+
+const u32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
+ 0x00000000,
+ 0x00000040,
+ 0x00000000,
+ 0x00000040,
+ 0x00000000,
+ 0x00000040,
+ 0x00000000,
+ 0x00000040,
+ 0x00000000,
+ 0x00000040,
+ 0x00000000,
+ 0x00000040,
+ 0x00000000,
+ 0x00000040,
+ 0x00000000,
+ 0x00000040,
+ 0x00000000,
+ 0x00000040,
+ 0x10000000,
+ 0x00000040,
+ 0x20000000,
+ 0x00000040,
+ 0x30000000,
+ 0x00000040,
+ 0x40000000,
+ 0x00000040,
+ 0x30000000,
+ 0x00000048,
+ 0x40000000,
+ 0x00000048,
+ 0x50000000,
+ 0x00000048,
+ 0x60000000,
+ 0x00000048,
+ 0x30000000,
+ 0x00000058,
+ 0x40000000,
+ 0x00000058,
+ 0x50000000,
+ 0x00000058,
+ 0x70000000,
+ 0x00000058,
+ 0x80000000,
+ 0x00000058,
+ 0x90000000,
+ 0x00000058,
+ 0xa0000000,
+ 0x00000058,
+ 0x70000000,
+ 0x00000068,
+ 0x80000000,
+ 0x00000068,
+ 0x90000000,
+ 0x00000068,
+ 0xa0000000,
+ 0x00000068,
+ 0xb0000000,
+ 0x00000068,
+ 0xc0000000,
+ 0x00000068,
+ 0xd0000000,
+ 0x00000068,
+ 0xe0000000,
+ 0x00000068,
+ 0xf0000000,
+ 0x00000068,
+ 0x00000000,
+ 0x00000069,
+ 0x10000000,
+ 0x00000069,
+ 0x20000000,
+ 0x00000069,
+ 0x30000000,
+ 0x00000069,
+ 0x40000000,
+ 0x00000041,
+ 0x40000000,
+ 0x00000041,
+ 0x40000000,
+ 0x00000041,
+ 0x40000000,
+ 0x00000041,
+ 0x40000000,
+ 0x00000041,
+ 0x40000000,
+ 0x00000041,
+ 0x40000000,
+ 0x00000041,
+ 0x40000000,
+ 0x00000041,
+ 0x40000000,
+ 0x00000041,
+ 0x50000000,
+ 0x00000041,
+ 0x60000000,
+ 0x00000041,
+ 0x70000000,
+ 0x00000041,
+ 0x80000000,
+ 0x00000041,
+ 0x70000000,
+ 0x00000049,
+ 0x80000000,
+ 0x00000049,
+ 0x90000000,
+ 0x00000049,
+ 0xa0000000,
+ 0x00000049,
+ 0x70000000,
+ 0x00000059,
+ 0x80000000,
+ 0x00000059,
+ 0x90000000,
+ 0x00000059,
+ 0xb0000000,
+ 0x00000059,
+ 0xc0000000,
+ 0x00000059,
+ 0xd0000000,
+ 0x00000059,
+ 0xe0000000,
+ 0x00000059,
+ 0xb0000000,
+ 0x00000069,
+ 0xc0000000,
+ 0x00000069,
+ 0xd0000000,
+ 0x00000069,
+ 0xe0000000,
+ 0x00000069,
+ 0xf0000000,
+ 0x00000069,
+ 0x00000000,
+ 0x0000006a,
+ 0x10000000,
+ 0x0000006a,
+ 0x20000000,
+ 0x0000006a,
+ 0x30000000,
+ 0x0000006a,
+ 0x40000000,
+ 0x0000006a,
+ 0x50000000,
+ 0x0000006a,
+ 0x60000000,
+ 0x0000006a,
+ 0x70000000,
+ 0x0000006a,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+const u32 dot11lcn_aux_gain_idx_tbl_5G[] = {
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0001,
+ 0x0002,
+ 0x0003,
+ 0x0004,
+ 0x0083,
+ 0x0084,
+ 0x0085,
+ 0x0086,
+ 0x0087,
+ 0x0186,
+ 0x0187,
+ 0x0188,
+ 0x0189,
+ 0x018a,
+ 0x018b,
+ 0x018c,
+ 0x018d,
+ 0x018e,
+ 0x018f,
+ 0x0190,
+ 0x0191,
+ 0x0192,
+ 0x0193,
+ 0x0194,
+ 0x0195,
+ 0x0196,
+ 0x0197,
+ 0x0198,
+ 0x0199,
+ 0x019a,
+ 0x019b,
+ 0x019c,
+ 0x019d,
+ 0x0000
+};
+
+const u32 dot11lcn_gain_val_tbl_5G[] = {
+ 0xf7,
+ 0xfd,
+ 0x00,
+ 0x04,
+ 0x04,
+ 0x04,
+ 0xf7,
+ 0xfd,
+ 0x00,
+ 0x04,
+ 0x04,
+ 0x04,
+ 0xf6,
+ 0x00,
+ 0x0c,
+ 0x03,
+ 0xeb,
+ 0xfe,
+ 0x06,
+ 0x0a,
+ 0x10,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x15,
+ 0x18,
+ 0x1b,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x15,
+ 0x18,
+ 0x1b,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00
+};
+
+const u32 dot11lcn_gain_idx_tbl_5G[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x10000000,
+ 0x00000000,
+ 0x20000000,
+ 0x00000000,
+ 0x30000000,
+ 0x00000000,
+ 0x40000000,
+ 0x00000000,
+ 0x30000000,
+ 0x00000008,
+ 0x40000000,
+ 0x00000008,
+ 0x50000000,
+ 0x00000008,
+ 0x60000000,
+ 0x00000008,
+ 0x70000000,
+ 0x00000008,
+ 0x60000000,
+ 0x00000018,
+ 0x70000000,
+ 0x00000018,
+ 0x80000000,
+ 0x00000018,
+ 0x90000000,
+ 0x00000018,
+ 0xa0000000,
+ 0x00000018,
+ 0xb0000000,
+ 0x00000018,
+ 0xc0000000,
+ 0x00000018,
+ 0xd0000000,
+ 0x00000018,
+ 0xe0000000,
+ 0x00000018,
+ 0xf0000000,
+ 0x00000018,
+ 0x00000000,
+ 0x00000019,
+ 0x10000000,
+ 0x00000019,
+ 0x20000000,
+ 0x00000019,
+ 0x30000000,
+ 0x00000019,
+ 0x40000000,
+ 0x00000019,
+ 0x50000000,
+ 0x00000019,
+ 0x60000000,
+ 0x00000019,
+ 0x70000000,
+ 0x00000019,
+ 0x80000000,
+ 0x00000019,
+ 0x90000000,
+ 0x00000019,
+ 0xa0000000,
+ 0x00000019,
+ 0xb0000000,
+ 0x00000019,
+ 0xc0000000,
+ 0x00000019,
+ 0xd0000000,
+ 0x00000019,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+const u32 dot11lcn_gain_tbl_5G[] = {
+ 0x00000000,
+ 0x00000040,
+ 0x00000080,
+ 0x00000001,
+ 0x00000005,
+ 0x00000009,
+ 0x0000000d,
+ 0x00000011,
+ 0x00000015,
+ 0x00000055,
+ 0x00000095,
+ 0x00000017,
+ 0x0000001b,
+ 0x0000005b,
+ 0x0000009b,
+ 0x000000db,
+ 0x0000011b,
+ 0x0000015b,
+ 0x0000019b,
+ 0x0000059b,
+ 0x0000099b,
+ 0x00000d9b,
+ 0x0000119b,
+ 0x0000519b,
+ 0x0000919b,
+ 0x0000d19b,
+ 0x0001119b,
+ 0x0001519b,
+ 0x0001919b,
+ 0x0001d19b,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+};
+
+const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[] = {
+ {&dot11lcn_gain_tbl_rev0,
+ sizeof(dot11lcn_gain_tbl_rev0) / sizeof(dot11lcn_gain_tbl_rev0[0]), 18,
+ 0, 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_rev0,
+ sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
+ sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_rev0,
+ sizeof(dot11lcn_gain_idx_tbl_rev0) /
+ sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
+ ,
+};
+
+const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev1[] = {
+ {&dot11lcn_gain_tbl_rev1,
+ sizeof(dot11lcn_gain_tbl_rev1) / sizeof(dot11lcn_gain_tbl_rev1[0]), 18,
+ 0, 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_rev0,
+ sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
+ sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_rev0,
+ sizeof(dot11lcn_gain_idx_tbl_rev0) /
+ sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
+ ,
+};
+
+const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[] = {
+ {&dot11lcn_gain_tbl_2G,
+ sizeof(dot11lcn_gain_tbl_2G) / sizeof(dot11lcn_gain_tbl_2G[0]), 18, 0,
+ 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_2G,
+ sizeof(dot11lcn_aux_gain_idx_tbl_2G) /
+ sizeof(dot11lcn_aux_gain_idx_tbl_2G[0]), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_2G,
+ sizeof(dot11lcn_gain_idx_tbl_2G) / sizeof(dot11lcn_gain_idx_tbl_2G[0]),
+ 13, 0, 32}
+ ,
+ {&dot11lcn_gain_val_tbl_2G,
+ sizeof(dot11lcn_gain_val_tbl_2G) / sizeof(dot11lcn_gain_val_tbl_2G[0]),
+ 17, 0, 8}
+};
+
+const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[] = {
+ {&dot11lcn_gain_tbl_5G,
+ sizeof(dot11lcn_gain_tbl_5G) / sizeof(dot11lcn_gain_tbl_5G[0]), 18, 0,
+ 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_5G,
+ sizeof(dot11lcn_aux_gain_idx_tbl_5G) /
+ sizeof(dot11lcn_aux_gain_idx_tbl_5G[0]), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_5G,
+ sizeof(dot11lcn_gain_idx_tbl_5G) / sizeof(dot11lcn_gain_idx_tbl_5G[0]),
+ 13, 0, 32}
+ ,
+ {&dot11lcn_gain_val_tbl_5G,
+ sizeof(dot11lcn_gain_val_tbl_5G) / sizeof(dot11lcn_gain_val_tbl_5G[0]),
+ 17, 0, 8}
+};
+
+const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[] = {
+ {&dot11lcn_gain_tbl_extlna_2G,
+ sizeof(dot11lcn_gain_tbl_extlna_2G) /
+ sizeof(dot11lcn_gain_tbl_extlna_2G[0]), 18, 0, 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_extlna_2G,
+ sizeof(dot11lcn_aux_gain_idx_tbl_extlna_2G) /
+ sizeof(dot11lcn_aux_gain_idx_tbl_extlna_2G[0]), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_extlna_2G,
+ sizeof(dot11lcn_gain_idx_tbl_extlna_2G) /
+ sizeof(dot11lcn_gain_idx_tbl_extlna_2G[0]), 13, 0, 32}
+ ,
+ {&dot11lcn_gain_val_tbl_extlna_2G,
+ sizeof(dot11lcn_gain_val_tbl_extlna_2G) /
+ sizeof(dot11lcn_gain_val_tbl_extlna_2G[0]), 17, 0, 8}
+};
+
+const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[] = {
+ {&dot11lcn_gain_tbl_5G,
+ sizeof(dot11lcn_gain_tbl_5G) / sizeof(dot11lcn_gain_tbl_5G[0]), 18, 0,
+ 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_5G,
+ sizeof(dot11lcn_aux_gain_idx_tbl_5G) /
+ sizeof(dot11lcn_aux_gain_idx_tbl_5G[0]), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_5G,
+ sizeof(dot11lcn_gain_idx_tbl_5G) / sizeof(dot11lcn_gain_idx_tbl_5G[0]),
+ 13, 0, 32}
+ ,
+ {&dot11lcn_gain_val_tbl_5G,
+ sizeof(dot11lcn_gain_val_tbl_5G) / sizeof(dot11lcn_gain_val_tbl_5G[0]),
+ 17, 0, 8}
+};
+
+const u32 dot11lcnphytbl_rx_gain_info_sz_rev0 =
+ sizeof(dot11lcnphytbl_rx_gain_info_rev0) /
+ sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]);
+
+const u32 dot11lcnphytbl_rx_gain_info_sz_rev1 =
+ sizeof(dot11lcnphytbl_rx_gain_info_rev1) /
+ sizeof(dot11lcnphytbl_rx_gain_info_rev1[0]);
+
+const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz =
+ sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) /
+ sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]);
+
+const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz =
+ sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) /
+ sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]);
+
+const u16 dot11lcn_min_sig_sq_tbl_rev0[] = {
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+ 0x014d,
+};
+
+const u16 dot11lcn_noise_scale_tbl_rev0[] = {
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+};
+
+const u32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
+ 0x000141f8,
+ 0x000021f8,
+ 0x000021fb,
+ 0x000041fb,
+ 0x0001fe4b,
+ 0x0000217b,
+ 0x00002133,
+ 0x000040eb,
+ 0x0001fea3,
+ 0x0000024b,
+};
+
+const u32 dot11lcn_ps_ctrl_tbl_rev0[] = {
+ 0x00100001,
+ 0x00200010,
+ 0x00300001,
+ 0x00400010,
+ 0x00500022,
+ 0x00600122,
+ 0x00700222,
+ 0x00800322,
+ 0x00900422,
+ 0x00a00522,
+ 0x00b00622,
+ 0x00c00722,
+ 0x00d00822,
+ 0x00f00922,
+ 0x00100a22,
+ 0x00200b22,
+ 0x00300c22,
+ 0x00400d22,
+ 0x00500e22,
+ 0x00600f22,
+};
+
+const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[] = {
+ 0x0007,
+ 0x0005,
+ 0x0006,
+ 0x0004,
+ 0x0007,
+ 0x0005,
+ 0x0006,
+ 0x0004,
+ 0x0007,
+ 0x0005,
+ 0x0006,
+ 0x0004,
+ 0x0007,
+ 0x0005,
+ 0x0006,
+ 0x0004,
+ 0x000b,
+ 0x000b,
+ 0x000a,
+ 0x000a,
+ 0x000b,
+ 0x000b,
+ 0x000a,
+ 0x000a,
+ 0x000b,
+ 0x000b,
+ 0x000a,
+ 0x000a,
+ 0x000b,
+ 0x000b,
+ 0x000a,
+ 0x000a,
+ 0x0007,
+ 0x0005,
+ 0x0006,
+ 0x0004,
+ 0x0007,
+ 0x0005,
+ 0x0006,
+ 0x0004,
+ 0x0007,
+ 0x0005,
+ 0x0006,
+ 0x0004,
+ 0x0007,
+ 0x0005,
+ 0x0006,
+ 0x0004,
+ 0x000b,
+ 0x000b,
+ 0x000a,
+ 0x000a,
+ 0x000b,
+ 0x000b,
+ 0x000a,
+ 0x000a,
+ 0x000b,
+ 0x000b,
+ 0x000a,
+ 0x000a,
+ 0x000b,
+ 0x000b,
+ 0x000a,
+ 0x000a,
+
+};
+
+const u16 dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[] = {
+ 0x0007,
+ 0x0005,
+ 0x0002,
+ 0x0000,
+ 0x0007,
+ 0x0005,
+ 0x0002,
+ 0x0000,
+ 0x0007,
+ 0x0005,
+ 0x0002,
+ 0x0000,
+ 0x0007,
+ 0x0005,
+ 0x0002,
+ 0x0000,
+ 0x0007,
+ 0x0007,
+ 0x0002,
+ 0x0002,
+ 0x0007,
+ 0x0007,
+ 0x0002,
+ 0x0002,
+ 0x0007,
+ 0x0007,
+ 0x0002,
+ 0x0002,
+ 0x0007,
+ 0x0007,
+ 0x0002,
+ 0x0002,
+ 0x0007,
+ 0x0005,
+ 0x0002,
+ 0x0000,
+ 0x0007,
+ 0x0005,
+ 0x0002,
+ 0x0000,
+ 0x0007,
+ 0x0005,
+ 0x0002,
+ 0x0000,
+ 0x0007,
+ 0x0005,
+ 0x0002,
+ 0x0000,
+ 0x0007,
+ 0x0007,
+ 0x0002,
+ 0x0002,
+ 0x0007,
+ 0x0007,
+ 0x0002,
+ 0x0002,
+ 0x0007,
+ 0x0007,
+ 0x0002,
+ 0x0002,
+ 0x0007,
+ 0x0007,
+ 0x0002,
+ 0x0002,
+};
+
+const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = {
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+ 0x0002,
+ 0x0008,
+ 0x0004,
+ 0x0001,
+};
+
+const u16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = {
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+ 0x000a,
+ 0x0009,
+ 0x0006,
+ 0x0005,
+};
+
+const u16 dot11lcn_sw_ctrl_tbl_rev0[] = {
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+ 0x0004,
+ 0x0004,
+ 0x0002,
+ 0x0002,
+};
+
+const u8 dot11lcn_nf_table_rev0[] = {
+ 0x5f,
+ 0x36,
+ 0x29,
+ 0x1f,
+ 0x5f,
+ 0x36,
+ 0x29,
+ 0x1f,
+ 0x5f,
+ 0x36,
+ 0x29,
+ 0x1f,
+ 0x5f,
+ 0x36,
+ 0x29,
+ 0x1f,
+};
+
+const u8 dot11lcn_gain_val_tbl_rev0[] = {
+ 0x09,
+ 0x0f,
+ 0x14,
+ 0x18,
+ 0xfe,
+ 0x07,
+ 0x0b,
+ 0x0f,
+ 0xfb,
+ 0xfe,
+ 0x01,
+ 0x05,
+ 0x08,
+ 0x0b,
+ 0x0e,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0x06,
+ 0x09,
+ 0x0c,
+ 0x0f,
+ 0x12,
+ 0x15,
+ 0x18,
+ 0x1b,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x03,
+ 0xeb,
+ 0x00,
+ 0x00,
+};
+
+const u8 dot11lcn_spur_tbl_rev0[] = {
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x02,
+ 0x03,
+ 0x01,
+ 0x03,
+ 0x02,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x02,
+ 0x03,
+ 0x01,
+ 0x03,
+ 0x02,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+ 0x01,
+};
+
+const u16 dot11lcn_unsup_mcs_tbl_rev0[] = {
+ 0x001a,
+ 0x0034,
+ 0x004e,
+ 0x0068,
+ 0x009c,
+ 0x00d0,
+ 0x00ea,
+ 0x0104,
+ 0x0034,
+ 0x0068,
+ 0x009c,
+ 0x00d0,
+ 0x0138,
+ 0x01a0,
+ 0x01d4,
+ 0x0208,
+ 0x004e,
+ 0x009c,
+ 0x00ea,
+ 0x0138,
+ 0x01d4,
+ 0x0270,
+ 0x02be,
+ 0x030c,
+ 0x0068,
+ 0x00d0,
+ 0x0138,
+ 0x01a0,
+ 0x0270,
+ 0x0340,
+ 0x03a8,
+ 0x0410,
+ 0x0018,
+ 0x009c,
+ 0x00d0,
+ 0x0104,
+ 0x00ea,
+ 0x0138,
+ 0x0186,
+ 0x00d0,
+ 0x0104,
+ 0x0104,
+ 0x0138,
+ 0x016c,
+ 0x016c,
+ 0x01a0,
+ 0x0138,
+ 0x0186,
+ 0x0186,
+ 0x01d4,
+ 0x0222,
+ 0x0222,
+ 0x0270,
+ 0x0104,
+ 0x0138,
+ 0x016c,
+ 0x0138,
+ 0x016c,
+ 0x01a0,
+ 0x01d4,
+ 0x01a0,
+ 0x01d4,
+ 0x0208,
+ 0x0208,
+ 0x023c,
+ 0x0186,
+ 0x01d4,
+ 0x0222,
+ 0x01d4,
+ 0x0222,
+ 0x0270,
+ 0x02be,
+ 0x0270,
+ 0x02be,
+ 0x030c,
+ 0x030c,
+ 0x035a,
+ 0x0036,
+ 0x006c,
+ 0x00a2,
+ 0x00d8,
+ 0x0144,
+ 0x01b0,
+ 0x01e6,
+ 0x021c,
+ 0x006c,
+ 0x00d8,
+ 0x0144,
+ 0x01b0,
+ 0x0288,
+ 0x0360,
+ 0x03cc,
+ 0x0438,
+ 0x00a2,
+ 0x0144,
+ 0x01e6,
+ 0x0288,
+ 0x03cc,
+ 0x0510,
+ 0x05b2,
+ 0x0654,
+ 0x00d8,
+ 0x01b0,
+ 0x0288,
+ 0x0360,
+ 0x0510,
+ 0x06c0,
+ 0x0798,
+ 0x0870,
+ 0x0018,
+ 0x0144,
+ 0x01b0,
+ 0x021c,
+ 0x01e6,
+ 0x0288,
+ 0x032a,
+ 0x01b0,
+ 0x021c,
+ 0x021c,
+ 0x0288,
+ 0x02f4,
+ 0x02f4,
+ 0x0360,
+ 0x0288,
+ 0x032a,
+ 0x032a,
+ 0x03cc,
+ 0x046e,
+ 0x046e,
+ 0x0510,
+ 0x021c,
+ 0x0288,
+ 0x02f4,
+ 0x0288,
+ 0x02f4,
+ 0x0360,
+ 0x03cc,
+ 0x0360,
+ 0x03cc,
+ 0x0438,
+ 0x0438,
+ 0x04a4,
+ 0x032a,
+ 0x03cc,
+ 0x046e,
+ 0x03cc,
+ 0x046e,
+ 0x0510,
+ 0x05b2,
+ 0x0510,
+ 0x05b2,
+ 0x0654,
+ 0x0654,
+ 0x06f6,
+};
+
+const u16 dot11lcn_iq_local_tbl_rev0[] = {
+ 0x0200,
+ 0x0300,
+ 0x0400,
+ 0x0600,
+ 0x0800,
+ 0x0b00,
+ 0x1000,
+ 0x1001,
+ 0x1002,
+ 0x1003,
+ 0x1004,
+ 0x1005,
+ 0x1006,
+ 0x1007,
+ 0x1707,
+ 0x2007,
+ 0x2d07,
+ 0x4007,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0200,
+ 0x0300,
+ 0x0400,
+ 0x0600,
+ 0x0800,
+ 0x0b00,
+ 0x1000,
+ 0x1001,
+ 0x1002,
+ 0x1003,
+ 0x1004,
+ 0x1005,
+ 0x1006,
+ 0x1007,
+ 0x1707,
+ 0x2007,
+ 0x2d07,
+ 0x4007,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x4000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+};
+
+const u32 dot11lcn_papd_compdelta_tbl_rev0[] = {
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+ 0x00080000,
+};
+
+const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[] = {
+ {&dot11lcn_min_sig_sq_tbl_rev0,
+ sizeof(dot11lcn_min_sig_sq_tbl_rev0) /
+ sizeof(dot11lcn_min_sig_sq_tbl_rev0[0]), 2, 0, 16}
+ ,
+ {&dot11lcn_noise_scale_tbl_rev0,
+ sizeof(dot11lcn_noise_scale_tbl_rev0) /
+ sizeof(dot11lcn_noise_scale_tbl_rev0[0]), 1, 0, 16}
+ ,
+ {&dot11lcn_fltr_ctrl_tbl_rev0,
+ sizeof(dot11lcn_fltr_ctrl_tbl_rev0) /
+ sizeof(dot11lcn_fltr_ctrl_tbl_rev0[0]), 11, 0, 32}
+ ,
+ {&dot11lcn_ps_ctrl_tbl_rev0,
+ sizeof(dot11lcn_ps_ctrl_tbl_rev0) /
+ sizeof(dot11lcn_ps_ctrl_tbl_rev0[0]), 12, 0, 32}
+ ,
+ {&dot11lcn_gain_idx_tbl_rev0,
+ sizeof(dot11lcn_gain_idx_tbl_rev0) /
+ sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_rev0,
+ sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
+ sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
+ ,
+ {&dot11lcn_sw_ctrl_tbl_rev0,
+ sizeof(dot11lcn_sw_ctrl_tbl_rev0) /
+ sizeof(dot11lcn_sw_ctrl_tbl_rev0[0]), 15, 0, 16}
+ ,
+ {&dot11lcn_nf_table_rev0,
+ sizeof(dot11lcn_nf_table_rev0) / sizeof(dot11lcn_nf_table_rev0[0]), 16,
+ 0, 8}
+ ,
+ {&dot11lcn_gain_val_tbl_rev0,
+ sizeof(dot11lcn_gain_val_tbl_rev0) /
+ sizeof(dot11lcn_gain_val_tbl_rev0[0]), 17, 0, 8}
+ ,
+ {&dot11lcn_gain_tbl_rev0,
+ sizeof(dot11lcn_gain_tbl_rev0) / sizeof(dot11lcn_gain_tbl_rev0[0]), 18,
+ 0, 32}
+ ,
+ {&dot11lcn_spur_tbl_rev0,
+ sizeof(dot11lcn_spur_tbl_rev0) / sizeof(dot11lcn_spur_tbl_rev0[0]), 20,
+ 0, 8}
+ ,
+ {&dot11lcn_unsup_mcs_tbl_rev0,
+ sizeof(dot11lcn_unsup_mcs_tbl_rev0) /
+ sizeof(dot11lcn_unsup_mcs_tbl_rev0[0]), 23, 0, 16}
+ ,
+ {&dot11lcn_iq_local_tbl_rev0,
+ sizeof(dot11lcn_iq_local_tbl_rev0) /
+ sizeof(dot11lcn_iq_local_tbl_rev0[0]), 0, 0, 16}
+ ,
+ {&dot11lcn_papd_compdelta_tbl_rev0,
+ sizeof(dot11lcn_papd_compdelta_tbl_rev0) /
+ sizeof(dot11lcn_papd_compdelta_tbl_rev0[0]), 24, 0, 32}
+ ,
+};
+
+const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313 = {
+ &dot11lcn_sw_ctrl_tbl_4313_rev0,
+ sizeof(dot11lcn_sw_ctrl_tbl_4313_rev0) /
+ sizeof(dot11lcn_sw_ctrl_tbl_4313_rev0[0]), 15, 0, 16
+};
+
+const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa = {
+ &dot11lcn_sw_ctrl_tbl_4313_epa_rev0,
+ sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0) /
+ sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0[0]), 15, 0, 16
+};
+
+const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa = {
+ &dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo,
+ sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo) /
+ sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[0]), 15, 0, 16
+};
+
+const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = {
+ &dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0,
+ sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0) /
+ sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16
+};
+
+const u32 dot11lcnphytbl_info_sz_rev0 =
+ sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]);
+
+const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = {
+ {3, 0, 31, 0, 72,}
+ ,
+ {3, 0, 31, 0, 70,}
+ ,
+ {3, 0, 31, 0, 68,}
+ ,
+ {3, 0, 30, 0, 67,}
+ ,
+ {3, 0, 29, 0, 68,}
+ ,
+ {3, 0, 28, 0, 68,}
+ ,
+ {3, 0, 27, 0, 69,}
+ ,
+ {3, 0, 26, 0, 70,}
+ ,
+ {3, 0, 25, 0, 70,}
+ ,
+ {3, 0, 24, 0, 71,}
+ ,
+ {3, 0, 23, 0, 72,}
+ ,
+ {3, 0, 23, 0, 70,}
+ ,
+ {3, 0, 22, 0, 71,}
+ ,
+ {3, 0, 21, 0, 72,}
+ ,
+ {3, 0, 21, 0, 70,}
+ ,
+ {3, 0, 21, 0, 68,}
+ ,
+ {3, 0, 21, 0, 66,}
+ ,
+ {3, 0, 21, 0, 64,}
+ ,
+ {3, 0, 21, 0, 63,}
+ ,
+ {3, 0, 20, 0, 64,}
+ ,
+ {3, 0, 19, 0, 65,}
+ ,
+ {3, 0, 19, 0, 64,}
+ ,
+ {3, 0, 18, 0, 65,}
+ ,
+ {3, 0, 18, 0, 64,}
+ ,
+ {3, 0, 17, 0, 65,}
+ ,
+ {3, 0, 17, 0, 64,}
+ ,
+ {3, 0, 16, 0, 65,}
+ ,
+ {3, 0, 16, 0, 64,}
+ ,
+ {3, 0, 16, 0, 62,}
+ ,
+ {3, 0, 16, 0, 60,}
+ ,
+ {3, 0, 16, 0, 58,}
+ ,
+ {3, 0, 15, 0, 61,}
+ ,
+ {3, 0, 15, 0, 59,}
+ ,
+ {3, 0, 14, 0, 61,}
+ ,
+ {3, 0, 14, 0, 60,}
+ ,
+ {3, 0, 14, 0, 58,}
+ ,
+ {3, 0, 13, 0, 60,}
+ ,
+ {3, 0, 13, 0, 59,}
+ ,
+ {3, 0, 12, 0, 62,}
+ ,
+ {3, 0, 12, 0, 60,}
+ ,
+ {3, 0, 12, 0, 58,}
+ ,
+ {3, 0, 11, 0, 62,}
+ ,
+ {3, 0, 11, 0, 60,}
+ ,
+ {3, 0, 11, 0, 59,}
+ ,
+ {3, 0, 11, 0, 57,}
+ ,
+ {3, 0, 10, 0, 61,}
+ ,
+ {3, 0, 10, 0, 59,}
+ ,
+ {3, 0, 10, 0, 57,}
+ ,
+ {3, 0, 9, 0, 62,}
+ ,
+ {3, 0, 9, 0, 60,}
+ ,
+ {3, 0, 9, 0, 58,}
+ ,
+ {3, 0, 9, 0, 57,}
+ ,
+ {3, 0, 8, 0, 62,}
+ ,
+ {3, 0, 8, 0, 60,}
+ ,
+ {3, 0, 8, 0, 58,}
+ ,
+ {3, 0, 8, 0, 57,}
+ ,
+ {3, 0, 8, 0, 55,}
+ ,
+ {3, 0, 7, 0, 61,}
+ ,
+ {3, 0, 7, 0, 60,}
+ ,
+ {3, 0, 7, 0, 58,}
+ ,
+ {3, 0, 7, 0, 56,}
+ ,
+ {3, 0, 7, 0, 55,}
+ ,
+ {3, 0, 6, 0, 62,}
+ ,
+ {3, 0, 6, 0, 60,}
+ ,
+ {3, 0, 6, 0, 58,}
+ ,
+ {3, 0, 6, 0, 57,}
+ ,
+ {3, 0, 6, 0, 55,}
+ ,
+ {3, 0, 6, 0, 54,}
+ ,
+ {3, 0, 6, 0, 52,}
+ ,
+ {3, 0, 5, 0, 61,}
+ ,
+ {3, 0, 5, 0, 59,}
+ ,
+ {3, 0, 5, 0, 57,}
+ ,
+ {3, 0, 5, 0, 56,}
+ ,
+ {3, 0, 5, 0, 54,}
+ ,
+ {3, 0, 5, 0, 53,}
+ ,
+ {3, 0, 5, 0, 51,}
+ ,
+ {3, 0, 4, 0, 62,}
+ ,
+ {3, 0, 4, 0, 60,}
+ ,
+ {3, 0, 4, 0, 58,}
+ ,
+ {3, 0, 4, 0, 57,}
+ ,
+ {3, 0, 4, 0, 55,}
+ ,
+ {3, 0, 4, 0, 54,}
+ ,
+ {3, 0, 4, 0, 52,}
+ ,
+ {3, 0, 4, 0, 51,}
+ ,
+ {3, 0, 4, 0, 49,}
+ ,
+ {3, 0, 4, 0, 48,}
+ ,
+ {3, 0, 4, 0, 46,}
+ ,
+ {3, 0, 3, 0, 60,}
+ ,
+ {3, 0, 3, 0, 58,}
+ ,
+ {3, 0, 3, 0, 57,}
+ ,
+ {3, 0, 3, 0, 55,}
+ ,
+ {3, 0, 3, 0, 54,}
+ ,
+ {3, 0, 3, 0, 52,}
+ ,
+ {3, 0, 3, 0, 51,}
+ ,
+ {3, 0, 3, 0, 49,}
+ ,
+ {3, 0, 3, 0, 48,}
+ ,
+ {3, 0, 3, 0, 46,}
+ ,
+ {3, 0, 3, 0, 45,}
+ ,
+ {3, 0, 3, 0, 44,}
+ ,
+ {3, 0, 3, 0, 43,}
+ ,
+ {3, 0, 3, 0, 41,}
+ ,
+ {3, 0, 2, 0, 61,}
+ ,
+ {3, 0, 2, 0, 59,}
+ ,
+ {3, 0, 2, 0, 57,}
+ ,
+ {3, 0, 2, 0, 56,}
+ ,
+ {3, 0, 2, 0, 54,}
+ ,
+ {3, 0, 2, 0, 53,}
+ ,
+ {3, 0, 2, 0, 51,}
+ ,
+ {3, 0, 2, 0, 50,}
+ ,
+ {3, 0, 2, 0, 48,}
+ ,
+ {3, 0, 2, 0, 47,}
+ ,
+ {3, 0, 2, 0, 46,}
+ ,
+ {3, 0, 2, 0, 44,}
+ ,
+ {3, 0, 2, 0, 43,}
+ ,
+ {3, 0, 2, 0, 42,}
+ ,
+ {3, 0, 2, 0, 41,}
+ ,
+ {3, 0, 2, 0, 39,}
+ ,
+ {3, 0, 2, 0, 38,}
+ ,
+ {3, 0, 2, 0, 37,}
+ ,
+ {3, 0, 2, 0, 36,}
+ ,
+ {3, 0, 2, 0, 35,}
+ ,
+ {3, 0, 2, 0, 34,}
+ ,
+ {3, 0, 2, 0, 33,}
+ ,
+ {3, 0, 2, 0, 32,}
+ ,
+ {3, 0, 1, 0, 63,}
+ ,
+ {3, 0, 1, 0, 61,}
+ ,
+ {3, 0, 1, 0, 59,}
+ ,
+ {3, 0, 1, 0, 57,}
+ ,
+};
+
+const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_gaintable_rev0[128] = {
+ {7, 0, 31, 0, 72,}
+ ,
+ {7, 0, 31, 0, 70,}
+ ,
+ {7, 0, 31, 0, 68,}
+ ,
+ {7, 0, 30, 0, 67,}
+ ,
+ {7, 0, 29, 0, 68,}
+ ,
+ {7, 0, 28, 0, 68,}
+ ,
+ {7, 0, 27, 0, 69,}
+ ,
+ {7, 0, 26, 0, 70,}
+ ,
+ {7, 0, 25, 0, 70,}
+ ,
+ {7, 0, 24, 0, 71,}
+ ,
+ {7, 0, 23, 0, 72,}
+ ,
+ {7, 0, 23, 0, 70,}
+ ,
+ {7, 0, 22, 0, 71,}
+ ,
+ {7, 0, 21, 0, 72,}
+ ,
+ {7, 0, 21, 0, 70,}
+ ,
+ {7, 0, 21, 0, 68,}
+ ,
+ {7, 0, 21, 0, 66,}
+ ,
+ {7, 0, 21, 0, 64,}
+ ,
+ {7, 0, 21, 0, 63,}
+ ,
+ {7, 0, 20, 0, 64,}
+ ,
+ {7, 0, 19, 0, 65,}
+ ,
+ {7, 0, 19, 0, 64,}
+ ,
+ {7, 0, 18, 0, 65,}
+ ,
+ {7, 0, 18, 0, 64,}
+ ,
+ {7, 0, 17, 0, 65,}
+ ,
+ {7, 0, 17, 0, 64,}
+ ,
+ {7, 0, 16, 0, 65,}
+ ,
+ {7, 0, 16, 0, 64,}
+ ,
+ {7, 0, 16, 0, 62,}
+ ,
+ {7, 0, 16, 0, 60,}
+ ,
+ {7, 0, 16, 0, 58,}
+ ,
+ {7, 0, 15, 0, 61,}
+ ,
+ {7, 0, 15, 0, 59,}
+ ,
+ {7, 0, 14, 0, 61,}
+ ,
+ {7, 0, 14, 0, 60,}
+ ,
+ {7, 0, 14, 0, 58,}
+ ,
+ {7, 0, 13, 0, 60,}
+ ,
+ {7, 0, 13, 0, 59,}
+ ,
+ {7, 0, 12, 0, 62,}
+ ,
+ {7, 0, 12, 0, 60,}
+ ,
+ {7, 0, 12, 0, 58,}
+ ,
+ {7, 0, 11, 0, 62,}
+ ,
+ {7, 0, 11, 0, 60,}
+ ,
+ {7, 0, 11, 0, 59,}
+ ,
+ {7, 0, 11, 0, 57,}
+ ,
+ {7, 0, 10, 0, 61,}
+ ,
+ {7, 0, 10, 0, 59,}
+ ,
+ {7, 0, 10, 0, 57,}
+ ,
+ {7, 0, 9, 0, 62,}
+ ,
+ {7, 0, 9, 0, 60,}
+ ,
+ {7, 0, 9, 0, 58,}
+ ,
+ {7, 0, 9, 0, 57,}
+ ,
+ {7, 0, 8, 0, 62,}
+ ,
+ {7, 0, 8, 0, 60,}
+ ,
+ {7, 0, 8, 0, 58,}
+ ,
+ {7, 0, 8, 0, 57,}
+ ,
+ {7, 0, 8, 0, 55,}
+ ,
+ {7, 0, 7, 0, 61,}
+ ,
+ {7, 0, 7, 0, 60,}
+ ,
+ {7, 0, 7, 0, 58,}
+ ,
+ {7, 0, 7, 0, 56,}
+ ,
+ {7, 0, 7, 0, 55,}
+ ,
+ {7, 0, 6, 0, 62,}
+ ,
+ {7, 0, 6, 0, 60,}
+ ,
+ {7, 0, 6, 0, 58,}
+ ,
+ {7, 0, 6, 0, 57,}
+ ,
+ {7, 0, 6, 0, 55,}
+ ,
+ {7, 0, 6, 0, 54,}
+ ,
+ {7, 0, 6, 0, 52,}
+ ,
+ {7, 0, 5, 0, 61,}
+ ,
+ {7, 0, 5, 0, 59,}
+ ,
+ {7, 0, 5, 0, 57,}
+ ,
+ {7, 0, 5, 0, 56,}
+ ,
+ {7, 0, 5, 0, 54,}
+ ,
+ {7, 0, 5, 0, 53,}
+ ,
+ {7, 0, 5, 0, 51,}
+ ,
+ {7, 0, 4, 0, 62,}
+ ,
+ {7, 0, 4, 0, 60,}
+ ,
+ {7, 0, 4, 0, 58,}
+ ,
+ {7, 0, 4, 0, 57,}
+ ,
+ {7, 0, 4, 0, 55,}
+ ,
+ {7, 0, 4, 0, 54,}
+ ,
+ {7, 0, 4, 0, 52,}
+ ,
+ {7, 0, 4, 0, 51,}
+ ,
+ {7, 0, 4, 0, 49,}
+ ,
+ {7, 0, 4, 0, 48,}
+ ,
+ {7, 0, 4, 0, 46,}
+ ,
+ {7, 0, 3, 0, 60,}
+ ,
+ {7, 0, 3, 0, 58,}
+ ,
+ {7, 0, 3, 0, 57,}
+ ,
+ {7, 0, 3, 0, 55,}
+ ,
+ {7, 0, 3, 0, 54,}
+ ,
+ {7, 0, 3, 0, 52,}
+ ,
+ {7, 0, 3, 0, 51,}
+ ,
+ {7, 0, 3, 0, 49,}
+ ,
+ {7, 0, 3, 0, 48,}
+ ,
+ {7, 0, 3, 0, 46,}
+ ,
+ {7, 0, 3, 0, 45,}
+ ,
+ {7, 0, 3, 0, 44,}
+ ,
+ {7, 0, 3, 0, 43,}
+ ,
+ {7, 0, 3, 0, 41,}
+ ,
+ {7, 0, 2, 0, 61,}
+ ,
+ {7, 0, 2, 0, 59,}
+ ,
+ {7, 0, 2, 0, 57,}
+ ,
+ {7, 0, 2, 0, 56,}
+ ,
+ {7, 0, 2, 0, 54,}
+ ,
+ {7, 0, 2, 0, 53,}
+ ,
+ {7, 0, 2, 0, 51,}
+ ,
+ {7, 0, 2, 0, 50,}
+ ,
+ {7, 0, 2, 0, 48,}
+ ,
+ {7, 0, 2, 0, 47,}
+ ,
+ {7, 0, 2, 0, 46,}
+ ,
+ {7, 0, 2, 0, 44,}
+ ,
+ {7, 0, 2, 0, 43,}
+ ,
+ {7, 0, 2, 0, 42,}
+ ,
+ {7, 0, 2, 0, 41,}
+ ,
+ {7, 0, 2, 0, 39,}
+ ,
+ {7, 0, 2, 0, 38,}
+ ,
+ {7, 0, 2, 0, 37,}
+ ,
+ {7, 0, 2, 0, 36,}
+ ,
+ {7, 0, 2, 0, 35,}
+ ,
+ {7, 0, 2, 0, 34,}
+ ,
+ {7, 0, 2, 0, 33,}
+ ,
+ {7, 0, 2, 0, 32,}
+ ,
+ {7, 0, 1, 0, 63,}
+ ,
+ {7, 0, 1, 0, 61,}
+ ,
+ {7, 0, 1, 0, 59,}
+ ,
+ {7, 0, 1, 0, 57,}
+ ,
+};
+
+const lcnphy_tx_gain_tbl_entry dot11lcnphy_5GHz_gaintable_rev0[128] = {
+ {255, 255, 0xf0, 0, 152,}
+ ,
+ {255, 255, 0xf0, 0, 147,}
+ ,
+ {255, 255, 0xf0, 0, 143,}
+ ,
+ {255, 255, 0xf0, 0, 139,}
+ ,
+ {255, 255, 0xf0, 0, 135,}
+ ,
+ {255, 255, 0xf0, 0, 131,}
+ ,
+ {255, 255, 0xf0, 0, 128,}
+ ,
+ {255, 255, 0xf0, 0, 124,}
+ ,
+ {255, 255, 0xf0, 0, 121,}
+ ,
+ {255, 255, 0xf0, 0, 117,}
+ ,
+ {255, 255, 0xf0, 0, 114,}
+ ,
+ {255, 255, 0xf0, 0, 111,}
+ ,
+ {255, 255, 0xf0, 0, 107,}
+ ,
+ {255, 255, 0xf0, 0, 104,}
+ ,
+ {255, 255, 0xf0, 0, 101,}
+ ,
+ {255, 255, 0xf0, 0, 99,}
+ ,
+ {255, 255, 0xf0, 0, 96,}
+ ,
+ {255, 255, 0xf0, 0, 93,}
+ ,
+ {255, 255, 0xf0, 0, 90,}
+ ,
+ {255, 255, 0xf0, 0, 88,}
+ ,
+ {255, 255, 0xf0, 0, 85,}
+ ,
+ {255, 255, 0xf0, 0, 83,}
+ ,
+ {255, 255, 0xf0, 0, 81,}
+ ,
+ {255, 255, 0xf0, 0, 78,}
+ ,
+ {255, 255, 0xf0, 0, 76,}
+ ,
+ {255, 255, 0xf0, 0, 74,}
+ ,
+ {255, 255, 0xf0, 0, 72,}
+ ,
+ {255, 255, 0xf0, 0, 70,}
+ ,
+ {255, 255, 0xf0, 0, 68,}
+ ,
+ {255, 255, 0xf0, 0, 66,}
+ ,
+ {255, 255, 0xf0, 0, 64,}
+ ,
+ {255, 248, 0xf0, 0, 64,}
+ ,
+ {255, 241, 0xf0, 0, 64,}
+ ,
+ {255, 251, 0xe0, 0, 64,}
+ ,
+ {255, 244, 0xe0, 0, 64,}
+ ,
+ {255, 254, 0xd0, 0, 64,}
+ ,
+ {255, 246, 0xd0, 0, 64,}
+ ,
+ {255, 239, 0xd0, 0, 64,}
+ ,
+ {255, 249, 0xc0, 0, 64,}
+ ,
+ {255, 242, 0xc0, 0, 64,}
+ ,
+ {255, 255, 0xb0, 0, 64,}
+ ,
+ {255, 248, 0xb0, 0, 64,}
+ ,
+ {255, 241, 0xb0, 0, 64,}
+ ,
+ {255, 254, 0xa0, 0, 64,}
+ ,
+ {255, 246, 0xa0, 0, 64,}
+ ,
+ {255, 239, 0xa0, 0, 64,}
+ ,
+ {255, 255, 0x90, 0, 64,}
+ ,
+ {255, 248, 0x90, 0, 64,}
+ ,
+ {255, 241, 0x90, 0, 64,}
+ ,
+ {255, 234, 0x90, 0, 64,}
+ ,
+ {255, 255, 0x80, 0, 64,}
+ ,
+ {255, 248, 0x80, 0, 64,}
+ ,
+ {255, 241, 0x80, 0, 64,}
+ ,
+ {255, 234, 0x80, 0, 64,}
+ ,
+ {255, 255, 0x70, 0, 64,}
+ ,
+ {255, 248, 0x70, 0, 64,}
+ ,
+ {255, 241, 0x70, 0, 64,}
+ ,
+ {255, 234, 0x70, 0, 64,}
+ ,
+ {255, 227, 0x70, 0, 64,}
+ ,
+ {255, 221, 0x70, 0, 64,}
+ ,
+ {255, 215, 0x70, 0, 64,}
+ ,
+ {255, 208, 0x70, 0, 64,}
+ ,
+ {255, 203, 0x70, 0, 64,}
+ ,
+ {255, 197, 0x70, 0, 64,}
+ ,
+ {255, 255, 0x60, 0, 64,}
+ ,
+ {255, 248, 0x60, 0, 64,}
+ ,
+ {255, 241, 0x60, 0, 64,}
+ ,
+ {255, 234, 0x60, 0, 64,}
+ ,
+ {255, 227, 0x60, 0, 64,}
+ ,
+ {255, 221, 0x60, 0, 64,}
+ ,
+ {255, 255, 0x50, 0, 64,}
+ ,
+ {255, 248, 0x50, 0, 64,}
+ ,
+ {255, 241, 0x50, 0, 64,}
+ ,
+ {255, 234, 0x50, 0, 64,}
+ ,
+ {255, 227, 0x50, 0, 64,}
+ ,
+ {255, 221, 0x50, 0, 64,}
+ ,
+ {255, 215, 0x50, 0, 64,}
+ ,
+ {255, 208, 0x50, 0, 64,}
+ ,
+ {255, 255, 0x40, 0, 64,}
+ ,
+ {255, 248, 0x40, 0, 64,}
+ ,
+ {255, 241, 0x40, 0, 64,}
+ ,
+ {255, 234, 0x40, 0, 64,}
+ ,
+ {255, 227, 0x40, 0, 64,}
+ ,
+ {255, 221, 0x40, 0, 64,}
+ ,
+ {255, 215, 0x40, 0, 64,}
+ ,
+ {255, 208, 0x40, 0, 64,}
+ ,
+ {255, 203, 0x40, 0, 64,}
+ ,
+ {255, 197, 0x40, 0, 64,}
+ ,
+ {255, 255, 0x30, 0, 64,}
+ ,
+ {255, 248, 0x30, 0, 64,}
+ ,
+ {255, 241, 0x30, 0, 64,}
+ ,
+ {255, 234, 0x30, 0, 64,}
+ ,
+ {255, 227, 0x30, 0, 64,}
+ ,
+ {255, 221, 0x30, 0, 64,}
+ ,
+ {255, 215, 0x30, 0, 64,}
+ ,
+ {255, 208, 0x30, 0, 64,}
+ ,
+ {255, 203, 0x30, 0, 64,}
+ ,
+ {255, 197, 0x30, 0, 64,}
+ ,
+ {255, 191, 0x30, 0, 64,}
+ ,
+ {255, 186, 0x30, 0, 64,}
+ ,
+ {255, 181, 0x30, 0, 64,}
+ ,
+ {255, 175, 0x30, 0, 64,}
+ ,
+ {255, 255, 0x20, 0, 64,}
+ ,
+ {255, 248, 0x20, 0, 64,}
+ ,
+ {255, 241, 0x20, 0, 64,}
+ ,
+ {255, 234, 0x20, 0, 64,}
+ ,
+ {255, 227, 0x20, 0, 64,}
+ ,
+ {255, 221, 0x20, 0, 64,}
+ ,
+ {255, 215, 0x20, 0, 64,}
+ ,
+ {255, 208, 0x20, 0, 64,}
+ ,
+ {255, 203, 0x20, 0, 64,}
+ ,
+ {255, 197, 0x20, 0, 64,}
+ ,
+ {255, 191, 0x20, 0, 64,}
+ ,
+ {255, 186, 0x20, 0, 64,}
+ ,
+ {255, 181, 0x20, 0, 64,}
+ ,
+ {255, 175, 0x20, 0, 64,}
+ ,
+ {255, 170, 0x20, 0, 64,}
+ ,
+ {255, 166, 0x20, 0, 64,}
+ ,
+ {255, 161, 0x20, 0, 64,}
+ ,
+ {255, 156, 0x20, 0, 64,}
+ ,
+ {255, 152, 0x20, 0, 64,}
+ ,
+ {255, 148, 0x20, 0, 64,}
+ ,
+ {255, 143, 0x20, 0, 64,}
+ ,
+ {255, 139, 0x20, 0, 64,}
+ ,
+ {255, 135, 0x20, 0, 64,}
+ ,
+ {255, 132, 0x20, 0, 64,}
+ ,
+ {255, 255, 0x10, 0, 64,}
+ ,
+ {255, 248, 0x10, 0, 64,}
+ ,
+};
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+typedef phytbl_info_t dot11lcnphytbl_info_t;
+
+extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[];
+extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev0;
+extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313;
+extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa;
+extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa_combo;
+
+extern const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[];
+extern const u32 dot11lcnphytbl_info_sz_rev0;
+
+extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[];
+extern const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
+
+extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[];
+extern const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
+
+extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[];
+
+extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[];
+
+typedef struct {
+ unsigned char gm;
+ unsigned char pga;
+ unsigned char pad;
+ unsigned char dac;
+ unsigned char bb_mult;
+} lcnphy_tx_gain_tbl_entry;
+
+extern const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_gaintable_rev0[];
+extern const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[];
+
+extern const lcnphy_tx_gain_tbl_entry dot11lcnphy_5GHz_gaintable_rev0[];
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+
+#include <dma.h>
+#include <phy_int.h>
+#include <phytbl_n.h>
+
+const u32 frame_struct_rev0[] = {
+ 0x08004a04,
+ 0x00100000,
+ 0x01000a05,
+ 0x00100020,
+ 0x09804506,
+ 0x00100030,
+ 0x09804507,
+ 0x00100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08004a0c,
+ 0x00100004,
+ 0x01000a0d,
+ 0x00100024,
+ 0x0980450e,
+ 0x00100034,
+ 0x0980450f,
+ 0x00100034,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a04,
+ 0x00100000,
+ 0x11008a05,
+ 0x00100020,
+ 0x1980c506,
+ 0x00100030,
+ 0x21810506,
+ 0x00100030,
+ 0x21810506,
+ 0x00100030,
+ 0x01800504,
+ 0x00100030,
+ 0x11808505,
+ 0x00100030,
+ 0x29814507,
+ 0x01100030,
+ 0x00000a04,
+ 0x00100000,
+ 0x11008a05,
+ 0x00100020,
+ 0x21810506,
+ 0x00100030,
+ 0x21810506,
+ 0x00100030,
+ 0x29814507,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a0c,
+ 0x00100008,
+ 0x11008a0d,
+ 0x00100028,
+ 0x1980c50e,
+ 0x00100038,
+ 0x2181050e,
+ 0x00100038,
+ 0x2181050e,
+ 0x00100038,
+ 0x0180050c,
+ 0x00100038,
+ 0x1180850d,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000a0c,
+ 0x00100008,
+ 0x11008a0d,
+ 0x00100028,
+ 0x2181050e,
+ 0x00100038,
+ 0x2181050e,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08004a04,
+ 0x00100000,
+ 0x01000a05,
+ 0x00100020,
+ 0x1980c506,
+ 0x00100030,
+ 0x1980c506,
+ 0x00100030,
+ 0x11808504,
+ 0x00100030,
+ 0x3981ca05,
+ 0x00100030,
+ 0x29814507,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x10008a04,
+ 0x00100000,
+ 0x3981ca05,
+ 0x00100030,
+ 0x1980c506,
+ 0x00100030,
+ 0x29814507,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08004a0c,
+ 0x00100008,
+ 0x01000a0d,
+ 0x00100028,
+ 0x1980c50e,
+ 0x00100038,
+ 0x1980c50e,
+ 0x00100038,
+ 0x1180850c,
+ 0x00100038,
+ 0x3981ca0d,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x10008a0c,
+ 0x00100008,
+ 0x3981ca0d,
+ 0x00100038,
+ 0x1980c50e,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40021404,
+ 0x00100000,
+ 0x02001405,
+ 0x00100040,
+ 0x0b004a06,
+ 0x01900060,
+ 0x13008a06,
+ 0x01900060,
+ 0x13008a06,
+ 0x01900060,
+ 0x43020a04,
+ 0x00100060,
+ 0x1b00ca05,
+ 0x00100060,
+ 0x23010a07,
+ 0x01500060,
+ 0x40021404,
+ 0x00100000,
+ 0x1a00d405,
+ 0x00100040,
+ 0x13008a06,
+ 0x01900060,
+ 0x13008a06,
+ 0x01900060,
+ 0x23010a07,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100010,
+ 0x0200140d,
+ 0x00100050,
+ 0x0b004a0e,
+ 0x01900070,
+ 0x13008a0e,
+ 0x01900070,
+ 0x13008a0e,
+ 0x01900070,
+ 0x43020a0c,
+ 0x00100070,
+ 0x1b00ca0d,
+ 0x00100070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x4002140c,
+ 0x00100010,
+ 0x1a00d40d,
+ 0x00100050,
+ 0x13008a0e,
+ 0x01900070,
+ 0x13008a0e,
+ 0x01900070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x50029404,
+ 0x00100000,
+ 0x32019405,
+ 0x00100040,
+ 0x0b004a06,
+ 0x01900060,
+ 0x0b004a06,
+ 0x01900060,
+ 0x5b02ca04,
+ 0x00100060,
+ 0x3b01d405,
+ 0x00100060,
+ 0x23010a07,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x5802d404,
+ 0x00100000,
+ 0x3b01d405,
+ 0x00100060,
+ 0x0b004a06,
+ 0x01900060,
+ 0x23010a07,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x5002940c,
+ 0x00100010,
+ 0x3201940d,
+ 0x00100050,
+ 0x0b004a0e,
+ 0x01900070,
+ 0x0b004a0e,
+ 0x01900070,
+ 0x5b02ca0c,
+ 0x00100070,
+ 0x3b01d40d,
+ 0x00100070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x5802d40c,
+ 0x00100010,
+ 0x3b01d40d,
+ 0x00100070,
+ 0x0b004a0e,
+ 0x01900070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40021404,
+ 0x000f4800,
+ 0x62031405,
+ 0x00100040,
+ 0x53028a06,
+ 0x01900060,
+ 0x53028a07,
+ 0x01900060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x000f4808,
+ 0x6203140d,
+ 0x00100048,
+ 0x53028a0e,
+ 0x01900068,
+ 0x53028a0f,
+ 0x01900068,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a0c,
+ 0x00100004,
+ 0x11008a0d,
+ 0x00100024,
+ 0x1980c50e,
+ 0x00100034,
+ 0x2181050e,
+ 0x00100034,
+ 0x2181050e,
+ 0x00100034,
+ 0x0180050c,
+ 0x00100038,
+ 0x1180850d,
+ 0x00100038,
+ 0x1181850d,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a0c,
+ 0x00100008,
+ 0x11008a0d,
+ 0x00100028,
+ 0x2181050e,
+ 0x00100038,
+ 0x2181050e,
+ 0x00100038,
+ 0x1181850d,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08004a04,
+ 0x00100000,
+ 0x01000a05,
+ 0x00100020,
+ 0x0180c506,
+ 0x00100030,
+ 0x0180c506,
+ 0x00100030,
+ 0x2180c50c,
+ 0x00100030,
+ 0x49820a0d,
+ 0x0016a130,
+ 0x41824a0d,
+ 0x0016a130,
+ 0x2981450f,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x2000ca0c,
+ 0x00100000,
+ 0x49820a0d,
+ 0x0016a130,
+ 0x1980c50e,
+ 0x00100030,
+ 0x41824a0d,
+ 0x0016a130,
+ 0x2981450f,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100008,
+ 0x0200140d,
+ 0x00100048,
+ 0x0b004a0e,
+ 0x01900068,
+ 0x13008a0e,
+ 0x01900068,
+ 0x13008a0e,
+ 0x01900068,
+ 0x43020a0c,
+ 0x00100070,
+ 0x1b00ca0d,
+ 0x00100070,
+ 0x1b014a0d,
+ 0x00100070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100010,
+ 0x1a00d40d,
+ 0x00100050,
+ 0x13008a0e,
+ 0x01900070,
+ 0x13008a0e,
+ 0x01900070,
+ 0x1b014a0d,
+ 0x00100070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x50029404,
+ 0x00100000,
+ 0x32019405,
+ 0x00100040,
+ 0x03004a06,
+ 0x01900060,
+ 0x03004a06,
+ 0x01900060,
+ 0x6b030a0c,
+ 0x00100060,
+ 0x4b02140d,
+ 0x0016a160,
+ 0x4302540d,
+ 0x0016a160,
+ 0x23010a0f,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x6b03140c,
+ 0x00100060,
+ 0x4b02140d,
+ 0x0016a160,
+ 0x0b004a0e,
+ 0x01900060,
+ 0x4302540d,
+ 0x0016a160,
+ 0x23010a0f,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40021404,
+ 0x00100000,
+ 0x1a00d405,
+ 0x00100040,
+ 0x53028a06,
+ 0x01900060,
+ 0x5b02ca06,
+ 0x01900060,
+ 0x5b02ca06,
+ 0x01900060,
+ 0x43020a04,
+ 0x00100060,
+ 0x1b00ca05,
+ 0x00100060,
+ 0x53028a07,
+ 0x0190c060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100010,
+ 0x1a00d40d,
+ 0x00100050,
+ 0x53028a0e,
+ 0x01900070,
+ 0x5b02ca0e,
+ 0x01900070,
+ 0x5b02ca0e,
+ 0x01900070,
+ 0x43020a0c,
+ 0x00100070,
+ 0x1b00ca0d,
+ 0x00100070,
+ 0x53028a0f,
+ 0x0190c070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40021404,
+ 0x00100000,
+ 0x1a00d405,
+ 0x00100040,
+ 0x5b02ca06,
+ 0x01900060,
+ 0x5b02ca06,
+ 0x01900060,
+ 0x53028a07,
+ 0x0190c060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100010,
+ 0x1a00d40d,
+ 0x00100050,
+ 0x5b02ca0e,
+ 0x01900070,
+ 0x5b02ca0e,
+ 0x01900070,
+ 0x53028a0f,
+ 0x0190c070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u8 frame_lut_rev0[] = {
+ 0x02,
+ 0x04,
+ 0x14,
+ 0x14,
+ 0x03,
+ 0x05,
+ 0x16,
+ 0x16,
+ 0x0a,
+ 0x0c,
+ 0x1c,
+ 0x1c,
+ 0x0b,
+ 0x0d,
+ 0x1e,
+ 0x1e,
+ 0x06,
+ 0x08,
+ 0x18,
+ 0x18,
+ 0x07,
+ 0x09,
+ 0x1a,
+ 0x1a,
+ 0x0e,
+ 0x10,
+ 0x20,
+ 0x28,
+ 0x0f,
+ 0x11,
+ 0x22,
+ 0x2a,
+};
+
+const u32 tmap_tbl_rev0[] = {
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x000aa888,
+ 0x88880000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa2222220,
+ 0x22222222,
+ 0x22c22222,
+ 0x00000222,
+ 0x22000000,
+ 0x2222a222,
+ 0x22222222,
+ 0x222222a2,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00011111,
+ 0x11110000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0xa8aa88a0,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x00088aaa,
+ 0xaaaa0000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xaaa8aaa0,
+ 0x8aaa8aaa,
+ 0xaa8a8a8a,
+ 0x000aaa88,
+ 0x8aaa0000,
+ 0xaaa8a888,
+ 0x8aa88a8a,
+ 0x8a88a888,
+ 0x08080a00,
+ 0x0a08080a,
+ 0x080a0a08,
+ 0x00080808,
+ 0x080a0000,
+ 0x080a0808,
+ 0x080a0808,
+ 0x0a0a0a08,
+ 0xa0a0a0a0,
+ 0x80a0a080,
+ 0x8080a0a0,
+ 0x00008080,
+ 0x80a00000,
+ 0x80a080a0,
+ 0xa080a0a0,
+ 0x8080a0a0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x99999000,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb90,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00aaa888,
+ 0x22000000,
+ 0x2222b222,
+ 0x22222222,
+ 0x222222b2,
+ 0xb2222220,
+ 0x22222222,
+ 0x22d22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x33000000,
+ 0x3333b333,
+ 0x33333333,
+ 0x333333b3,
+ 0xb3333330,
+ 0x33333333,
+ 0x33d33333,
+ 0x00000333,
+ 0x22000000,
+ 0x2222a222,
+ 0x22222222,
+ 0x222222a2,
+ 0xa2222220,
+ 0x22222222,
+ 0x22c22222,
+ 0x00000222,
+ 0x99b99b00,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb99,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x08aaa888,
+ 0x22222200,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0x22222222,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x11111111,
+ 0xf1111111,
+ 0x11111111,
+ 0x11f11111,
+ 0x01111111,
+ 0xbb9bb900,
+ 0xb9b9bb99,
+ 0xb99bbbbb,
+ 0xbbbb9b9b,
+ 0xb9bb99bb,
+ 0xb99999b9,
+ 0xb9b9b99b,
+ 0x00000bbb,
+ 0xaa000000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xa8aa88aa,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x0a888aaa,
+ 0xaa000000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xa8aa88a0,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x00000aaa,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0xbbbbbb00,
+ 0x999bbbbb,
+ 0x9bb99b9b,
+ 0xb9b9b9bb,
+ 0xb9b99bbb,
+ 0xb9b9b9bb,
+ 0xb9bb9b99,
+ 0x00000999,
+ 0x8a000000,
+ 0xaa88a888,
+ 0xa88888aa,
+ 0xa88a8a88,
+ 0xa88aa88a,
+ 0x88a8aaaa,
+ 0xa8aa8aaa,
+ 0x0888a88a,
+ 0x0b0b0b00,
+ 0x090b0b0b,
+ 0x0b090b0b,
+ 0x0909090b,
+ 0x09090b0b,
+ 0x09090b0b,
+ 0x09090b09,
+ 0x00000909,
+ 0x0a000000,
+ 0x0a080808,
+ 0x080a080a,
+ 0x080a0a08,
+ 0x080a080a,
+ 0x0808080a,
+ 0x0a0a0a08,
+ 0x0808080a,
+ 0xb0b0b000,
+ 0x9090b0b0,
+ 0x90b09090,
+ 0xb0b0b090,
+ 0xb0b090b0,
+ 0x90b0b0b0,
+ 0xb0b09090,
+ 0x00000090,
+ 0x80000000,
+ 0xa080a080,
+ 0xa08080a0,
+ 0xa0808080,
+ 0xa080a080,
+ 0x80a0a0a0,
+ 0xa0a080a0,
+ 0x00a0a0a0,
+ 0x22000000,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0xf2222220,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00000111,
+ 0x33000000,
+ 0x3333f333,
+ 0x33333333,
+ 0x333333f3,
+ 0xf3333330,
+ 0x33333333,
+ 0x33f33333,
+ 0x00000333,
+ 0x22000000,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0xf2222220,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x99000000,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb90,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88888000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00aaa888,
+ 0x88a88a00,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x08aaa888,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 tdtrn_tbl_rev0[] = {
+ 0x061c061c,
+ 0x0050ee68,
+ 0xf592fe36,
+ 0xfe5212f6,
+ 0x00000c38,
+ 0xfe5212f6,
+ 0xf592fe36,
+ 0x0050ee68,
+ 0x061c061c,
+ 0xee680050,
+ 0xfe36f592,
+ 0x12f6fe52,
+ 0x0c380000,
+ 0x12f6fe52,
+ 0xfe36f592,
+ 0xee680050,
+ 0x061c061c,
+ 0x0050ee68,
+ 0xf592fe36,
+ 0xfe5212f6,
+ 0x00000c38,
+ 0xfe5212f6,
+ 0xf592fe36,
+ 0x0050ee68,
+ 0x061c061c,
+ 0xee680050,
+ 0xfe36f592,
+ 0x12f6fe52,
+ 0x0c380000,
+ 0x12f6fe52,
+ 0xfe36f592,
+ 0xee680050,
+ 0x05e305e3,
+ 0x004def0c,
+ 0xf5f3fe47,
+ 0xfe611246,
+ 0x00000bc7,
+ 0xfe611246,
+ 0xf5f3fe47,
+ 0x004def0c,
+ 0x05e305e3,
+ 0xef0c004d,
+ 0xfe47f5f3,
+ 0x1246fe61,
+ 0x0bc70000,
+ 0x1246fe61,
+ 0xfe47f5f3,
+ 0xef0c004d,
+ 0x05e305e3,
+ 0x004def0c,
+ 0xf5f3fe47,
+ 0xfe611246,
+ 0x00000bc7,
+ 0xfe611246,
+ 0xf5f3fe47,
+ 0x004def0c,
+ 0x05e305e3,
+ 0xef0c004d,
+ 0xfe47f5f3,
+ 0x1246fe61,
+ 0x0bc70000,
+ 0x1246fe61,
+ 0xfe47f5f3,
+ 0xef0c004d,
+ 0xfa58fa58,
+ 0xf895043b,
+ 0xff4c09c0,
+ 0xfbc6ffa8,
+ 0xfb84f384,
+ 0x0798f6f9,
+ 0x05760122,
+ 0x058409f6,
+ 0x0b500000,
+ 0x05b7f542,
+ 0x08860432,
+ 0x06ddfee7,
+ 0xfb84f384,
+ 0xf9d90664,
+ 0xf7e8025c,
+ 0x00fff7bd,
+ 0x05a805a8,
+ 0xf7bd00ff,
+ 0x025cf7e8,
+ 0x0664f9d9,
+ 0xf384fb84,
+ 0xfee706dd,
+ 0x04320886,
+ 0xf54205b7,
+ 0x00000b50,
+ 0x09f60584,
+ 0x01220576,
+ 0xf6f90798,
+ 0xf384fb84,
+ 0xffa8fbc6,
+ 0x09c0ff4c,
+ 0x043bf895,
+ 0x02d402d4,
+ 0x07de0270,
+ 0xfc96079c,
+ 0xf90afe94,
+ 0xfe00ff2c,
+ 0x02d4065d,
+ 0x092a0096,
+ 0x0014fbb8,
+ 0xfd2cfd2c,
+ 0x076afb3c,
+ 0x0096f752,
+ 0xf991fd87,
+ 0xfb2c0200,
+ 0xfeb8f960,
+ 0x08e0fc96,
+ 0x049802a8,
+ 0xfd2cfd2c,
+ 0x02a80498,
+ 0xfc9608e0,
+ 0xf960feb8,
+ 0x0200fb2c,
+ 0xfd87f991,
+ 0xf7520096,
+ 0xfb3c076a,
+ 0xfd2cfd2c,
+ 0xfbb80014,
+ 0x0096092a,
+ 0x065d02d4,
+ 0xff2cfe00,
+ 0xfe94f90a,
+ 0x079cfc96,
+ 0x027007de,
+ 0x02d402d4,
+ 0x027007de,
+ 0x079cfc96,
+ 0xfe94f90a,
+ 0xff2cfe00,
+ 0x065d02d4,
+ 0x0096092a,
+ 0xfbb80014,
+ 0xfd2cfd2c,
+ 0xfb3c076a,
+ 0xf7520096,
+ 0xfd87f991,
+ 0x0200fb2c,
+ 0xf960feb8,
+ 0xfc9608e0,
+ 0x02a80498,
+ 0xfd2cfd2c,
+ 0x049802a8,
+ 0x08e0fc96,
+ 0xfeb8f960,
+ 0xfb2c0200,
+ 0xf991fd87,
+ 0x0096f752,
+ 0x076afb3c,
+ 0xfd2cfd2c,
+ 0x0014fbb8,
+ 0x092a0096,
+ 0x02d4065d,
+ 0xfe00ff2c,
+ 0xf90afe94,
+ 0xfc96079c,
+ 0x07de0270,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x062a0000,
+ 0xfefa0759,
+ 0x08b80908,
+ 0xf396fc2d,
+ 0xf9d6045c,
+ 0xfc4ef608,
+ 0xf748f596,
+ 0x07b207bf,
+ 0x062a062a,
+ 0xf84ef841,
+ 0xf748f596,
+ 0x03b209f8,
+ 0xf9d6045c,
+ 0x0c6a03d3,
+ 0x08b80908,
+ 0x0106f8a7,
+ 0x062a0000,
+ 0xfefaf8a7,
+ 0x08b8f6f8,
+ 0xf39603d3,
+ 0xf9d6fba4,
+ 0xfc4e09f8,
+ 0xf7480a6a,
+ 0x07b2f841,
+ 0x062af9d6,
+ 0xf84e07bf,
+ 0xf7480a6a,
+ 0x03b2f608,
+ 0xf9d6fba4,
+ 0x0c6afc2d,
+ 0x08b8f6f8,
+ 0x01060759,
+ 0x062a0000,
+ 0xfefa0759,
+ 0x08b80908,
+ 0xf396fc2d,
+ 0xf9d6045c,
+ 0xfc4ef608,
+ 0xf748f596,
+ 0x07b207bf,
+ 0x062a062a,
+ 0xf84ef841,
+ 0xf748f596,
+ 0x03b209f8,
+ 0xf9d6045c,
+ 0x0c6a03d3,
+ 0x08b80908,
+ 0x0106f8a7,
+ 0x062a0000,
+ 0xfefaf8a7,
+ 0x08b8f6f8,
+ 0xf39603d3,
+ 0xf9d6fba4,
+ 0xfc4e09f8,
+ 0xf7480a6a,
+ 0x07b2f841,
+ 0x062af9d6,
+ 0xf84e07bf,
+ 0xf7480a6a,
+ 0x03b2f608,
+ 0xf9d6fba4,
+ 0x0c6afc2d,
+ 0x08b8f6f8,
+ 0x01060759,
+ 0x061c061c,
+ 0xff30009d,
+ 0xffb21141,
+ 0xfd87fb54,
+ 0xf65dfe59,
+ 0x02eef99e,
+ 0x0166f03c,
+ 0xfff809b6,
+ 0x000008a4,
+ 0x000af42b,
+ 0x00eff577,
+ 0xfa840bf2,
+ 0xfc02ff51,
+ 0x08260f67,
+ 0xfff0036f,
+ 0x0842f9c3,
+ 0x00000000,
+ 0x063df7be,
+ 0xfc910010,
+ 0xf099f7da,
+ 0x00af03fe,
+ 0xf40e057c,
+ 0x0a89ff11,
+ 0x0bd5fff6,
+ 0xf75c0000,
+ 0xf64a0008,
+ 0x0fc4fe9a,
+ 0x0662fd12,
+ 0x01a709a3,
+ 0x04ac0279,
+ 0xeebf004e,
+ 0xff6300d0,
+ 0xf9e4f9e4,
+ 0x00d0ff63,
+ 0x004eeebf,
+ 0x027904ac,
+ 0x09a301a7,
+ 0xfd120662,
+ 0xfe9a0fc4,
+ 0x0008f64a,
+ 0x0000f75c,
+ 0xfff60bd5,
+ 0xff110a89,
+ 0x057cf40e,
+ 0x03fe00af,
+ 0xf7daf099,
+ 0x0010fc91,
+ 0xf7be063d,
+ 0x00000000,
+ 0xf9c30842,
+ 0x036ffff0,
+ 0x0f670826,
+ 0xff51fc02,
+ 0x0bf2fa84,
+ 0xf57700ef,
+ 0xf42b000a,
+ 0x08a40000,
+ 0x09b6fff8,
+ 0xf03c0166,
+ 0xf99e02ee,
+ 0xfe59f65d,
+ 0xfb54fd87,
+ 0x1141ffb2,
+ 0x009dff30,
+ 0x05e30000,
+ 0xff060705,
+ 0x085408a0,
+ 0xf425fc59,
+ 0xfa1d042a,
+ 0xfc78f67a,
+ 0xf7acf60e,
+ 0x075a0766,
+ 0x05e305e3,
+ 0xf8a6f89a,
+ 0xf7acf60e,
+ 0x03880986,
+ 0xfa1d042a,
+ 0x0bdb03a7,
+ 0x085408a0,
+ 0x00faf8fb,
+ 0x05e30000,
+ 0xff06f8fb,
+ 0x0854f760,
+ 0xf42503a7,
+ 0xfa1dfbd6,
+ 0xfc780986,
+ 0xf7ac09f2,
+ 0x075af89a,
+ 0x05e3fa1d,
+ 0xf8a60766,
+ 0xf7ac09f2,
+ 0x0388f67a,
+ 0xfa1dfbd6,
+ 0x0bdbfc59,
+ 0x0854f760,
+ 0x00fa0705,
+ 0x05e30000,
+ 0xff060705,
+ 0x085408a0,
+ 0xf425fc59,
+ 0xfa1d042a,
+ 0xfc78f67a,
+ 0xf7acf60e,
+ 0x075a0766,
+ 0x05e305e3,
+ 0xf8a6f89a,
+ 0xf7acf60e,
+ 0x03880986,
+ 0xfa1d042a,
+ 0x0bdb03a7,
+ 0x085408a0,
+ 0x00faf8fb,
+ 0x05e30000,
+ 0xff06f8fb,
+ 0x0854f760,
+ 0xf42503a7,
+ 0xfa1dfbd6,
+ 0xfc780986,
+ 0xf7ac09f2,
+ 0x075af89a,
+ 0x05e3fa1d,
+ 0xf8a60766,
+ 0xf7ac09f2,
+ 0x0388f67a,
+ 0xfa1dfbd6,
+ 0x0bdbfc59,
+ 0x0854f760,
+ 0x00fa0705,
+ 0xfa58fa58,
+ 0xf8f0fe00,
+ 0x0448073d,
+ 0xfdc9fe46,
+ 0xf9910258,
+ 0x089d0407,
+ 0xfd5cf71a,
+ 0x02affde0,
+ 0x083e0496,
+ 0xff5a0740,
+ 0xff7afd97,
+ 0x00fe01f1,
+ 0x0009082e,
+ 0xfa94ff75,
+ 0xfecdf8ea,
+ 0xffb0f693,
+ 0xfd2cfa58,
+ 0x0433ff16,
+ 0xfba405dd,
+ 0xfa610341,
+ 0x06a606cb,
+ 0x0039fd2d,
+ 0x0677fa97,
+ 0x01fa05e0,
+ 0xf896003e,
+ 0x075a068b,
+ 0x012cfc3e,
+ 0xfa23f98d,
+ 0xfc7cfd43,
+ 0xff90fc0d,
+ 0x01c10982,
+ 0x00c601d6,
+ 0xfd2cfd2c,
+ 0x01d600c6,
+ 0x098201c1,
+ 0xfc0dff90,
+ 0xfd43fc7c,
+ 0xf98dfa23,
+ 0xfc3e012c,
+ 0x068b075a,
+ 0x003ef896,
+ 0x05e001fa,
+ 0xfa970677,
+ 0xfd2d0039,
+ 0x06cb06a6,
+ 0x0341fa61,
+ 0x05ddfba4,
+ 0xff160433,
+ 0xfa58fd2c,
+ 0xf693ffb0,
+ 0xf8eafecd,
+ 0xff75fa94,
+ 0x082e0009,
+ 0x01f100fe,
+ 0xfd97ff7a,
+ 0x0740ff5a,
+ 0x0496083e,
+ 0xfde002af,
+ 0xf71afd5c,
+ 0x0407089d,
+ 0x0258f991,
+ 0xfe46fdc9,
+ 0x073d0448,
+ 0xfe00f8f0,
+ 0xfd2cfd2c,
+ 0xfce00500,
+ 0xfc09fddc,
+ 0xfe680157,
+ 0x04c70571,
+ 0xfc3aff21,
+ 0xfcd70228,
+ 0x056d0277,
+ 0x0200fe00,
+ 0x0022f927,
+ 0xfe3c032b,
+ 0xfc44ff3c,
+ 0x03e9fbdb,
+ 0x04570313,
+ 0x04c9ff5c,
+ 0x000d03b8,
+ 0xfa580000,
+ 0xfbe900d2,
+ 0xf9d0fe0b,
+ 0x0125fdf9,
+ 0x042501bf,
+ 0x0328fa2b,
+ 0xffa902f0,
+ 0xfa250157,
+ 0x0200fe00,
+ 0x03740438,
+ 0xff0405fd,
+ 0x030cfe52,
+ 0x0037fb39,
+ 0xff6904c5,
+ 0x04f8fd23,
+ 0xfd31fc1b,
+ 0xfd2cfd2c,
+ 0xfc1bfd31,
+ 0xfd2304f8,
+ 0x04c5ff69,
+ 0xfb390037,
+ 0xfe52030c,
+ 0x05fdff04,
+ 0x04380374,
+ 0xfe000200,
+ 0x0157fa25,
+ 0x02f0ffa9,
+ 0xfa2b0328,
+ 0x01bf0425,
+ 0xfdf90125,
+ 0xfe0bf9d0,
+ 0x00d2fbe9,
+ 0x0000fa58,
+ 0x03b8000d,
+ 0xff5c04c9,
+ 0x03130457,
+ 0xfbdb03e9,
+ 0xff3cfc44,
+ 0x032bfe3c,
+ 0xf9270022,
+ 0xfe000200,
+ 0x0277056d,
+ 0x0228fcd7,
+ 0xff21fc3a,
+ 0x057104c7,
+ 0x0157fe68,
+ 0xfddcfc09,
+ 0x0500fce0,
+ 0xfd2cfd2c,
+ 0x0500fce0,
+ 0xfddcfc09,
+ 0x0157fe68,
+ 0x057104c7,
+ 0xff21fc3a,
+ 0x0228fcd7,
+ 0x0277056d,
+ 0xfe000200,
+ 0xf9270022,
+ 0x032bfe3c,
+ 0xff3cfc44,
+ 0xfbdb03e9,
+ 0x03130457,
+ 0xff5c04c9,
+ 0x03b8000d,
+ 0x0000fa58,
+ 0x00d2fbe9,
+ 0xfe0bf9d0,
+ 0xfdf90125,
+ 0x01bf0425,
+ 0xfa2b0328,
+ 0x02f0ffa9,
+ 0x0157fa25,
+ 0xfe000200,
+ 0x04380374,
+ 0x05fdff04,
+ 0xfe52030c,
+ 0xfb390037,
+ 0x04c5ff69,
+ 0xfd2304f8,
+ 0xfc1bfd31,
+ 0xfd2cfd2c,
+ 0xfd31fc1b,
+ 0x04f8fd23,
+ 0xff6904c5,
+ 0x0037fb39,
+ 0x030cfe52,
+ 0xff0405fd,
+ 0x03740438,
+ 0x0200fe00,
+ 0xfa250157,
+ 0xffa902f0,
+ 0x0328fa2b,
+ 0x042501bf,
+ 0x0125fdf9,
+ 0xf9d0fe0b,
+ 0xfbe900d2,
+ 0xfa580000,
+ 0x000d03b8,
+ 0x04c9ff5c,
+ 0x04570313,
+ 0x03e9fbdb,
+ 0xfc44ff3c,
+ 0xfe3c032b,
+ 0x0022f927,
+ 0x0200fe00,
+ 0x056d0277,
+ 0xfcd70228,
+ 0xfc3aff21,
+ 0x04c70571,
+ 0xfe680157,
+ 0xfc09fddc,
+ 0xfce00500,
+ 0x05a80000,
+ 0xff1006be,
+ 0x0800084a,
+ 0xf49cfc7e,
+ 0xfa580400,
+ 0xfc9cf6da,
+ 0xf800f672,
+ 0x0710071c,
+ 0x05a805a8,
+ 0xf8f0f8e4,
+ 0xf800f672,
+ 0x03640926,
+ 0xfa580400,
+ 0x0b640382,
+ 0x0800084a,
+ 0x00f0f942,
+ 0x05a80000,
+ 0xff10f942,
+ 0x0800f7b6,
+ 0xf49c0382,
+ 0xfa58fc00,
+ 0xfc9c0926,
+ 0xf800098e,
+ 0x0710f8e4,
+ 0x05a8fa58,
+ 0xf8f0071c,
+ 0xf800098e,
+ 0x0364f6da,
+ 0xfa58fc00,
+ 0x0b64fc7e,
+ 0x0800f7b6,
+ 0x00f006be,
+ 0x05a80000,
+ 0xff1006be,
+ 0x0800084a,
+ 0xf49cfc7e,
+ 0xfa580400,
+ 0xfc9cf6da,
+ 0xf800f672,
+ 0x0710071c,
+ 0x05a805a8,
+ 0xf8f0f8e4,
+ 0xf800f672,
+ 0x03640926,
+ 0xfa580400,
+ 0x0b640382,
+ 0x0800084a,
+ 0x00f0f942,
+ 0x05a80000,
+ 0xff10f942,
+ 0x0800f7b6,
+ 0xf49c0382,
+ 0xfa58fc00,
+ 0xfc9c0926,
+ 0xf800098e,
+ 0x0710f8e4,
+ 0x05a8fa58,
+ 0xf8f0071c,
+ 0xf800098e,
+ 0x0364f6da,
+ 0xfa58fc00,
+ 0x0b64fc7e,
+ 0x0800f7b6,
+ 0x00f006be,
+};
+
+const u32 intlv_tbl_rev0[] = {
+ 0x00802070,
+ 0x0671188d,
+ 0x0a60192c,
+ 0x0a300e46,
+ 0x00c1188d,
+ 0x080024d2,
+ 0x00000070,
+};
+
+const u16 pilot_tbl_rev0[] = {
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0xff0a,
+ 0xff82,
+ 0xffa0,
+ 0xff28,
+ 0xffff,
+ 0xffff,
+ 0xffff,
+ 0xffff,
+ 0xff82,
+ 0xffa0,
+ 0xff28,
+ 0xff0a,
+ 0xffff,
+ 0xffff,
+ 0xffff,
+ 0xffff,
+ 0xf83f,
+ 0xfa1f,
+ 0xfa97,
+ 0xfab5,
+ 0xf2bd,
+ 0xf0bf,
+ 0xffff,
+ 0xffff,
+ 0xf017,
+ 0xf815,
+ 0xf215,
+ 0xf095,
+ 0xf035,
+ 0xf01d,
+ 0xffff,
+ 0xffff,
+ 0xff08,
+ 0xff02,
+ 0xff80,
+ 0xff20,
+ 0xff08,
+ 0xff02,
+ 0xff80,
+ 0xff20,
+ 0xf01f,
+ 0xf817,
+ 0xfa15,
+ 0xf295,
+ 0xf0b5,
+ 0xf03d,
+ 0xffff,
+ 0xffff,
+ 0xf82a,
+ 0xfa0a,
+ 0xfa82,
+ 0xfaa0,
+ 0xf2a8,
+ 0xf0aa,
+ 0xffff,
+ 0xffff,
+ 0xf002,
+ 0xf800,
+ 0xf200,
+ 0xf080,
+ 0xf020,
+ 0xf008,
+ 0xffff,
+ 0xffff,
+ 0xf00a,
+ 0xf802,
+ 0xfa00,
+ 0xf280,
+ 0xf0a0,
+ 0xf028,
+ 0xffff,
+ 0xffff,
+};
+
+const u32 pltlut_tbl_rev0[] = {
+ 0x76540123,
+ 0x62407351,
+ 0x76543201,
+ 0x76540213,
+ 0x76540123,
+ 0x76430521,
+};
+
+const u32 tdi_tbl20_ant0_rev0[] = {
+ 0x00091226,
+ 0x000a1429,
+ 0x000b56ad,
+ 0x000c58b0,
+ 0x000d5ab3,
+ 0x000e9cb6,
+ 0x000f9eba,
+ 0x0000c13d,
+ 0x00020301,
+ 0x00030504,
+ 0x00040708,
+ 0x0005090b,
+ 0x00064b8e,
+ 0x00095291,
+ 0x000a5494,
+ 0x000b9718,
+ 0x000c9927,
+ 0x000d9b2a,
+ 0x000edd2e,
+ 0x000fdf31,
+ 0x000101b4,
+ 0x000243b7,
+ 0x000345bb,
+ 0x000447be,
+ 0x00058982,
+ 0x00068c05,
+ 0x00099309,
+ 0x000a950c,
+ 0x000bd78f,
+ 0x000cd992,
+ 0x000ddb96,
+ 0x000f1d99,
+ 0x00005fa8,
+ 0x0001422c,
+ 0x0002842f,
+ 0x00038632,
+ 0x00048835,
+ 0x0005ca38,
+ 0x0006ccbc,
+ 0x0009d3bf,
+ 0x000b1603,
+ 0x000c1806,
+ 0x000d1a0a,
+ 0x000e1c0d,
+ 0x000f5e10,
+ 0x00008093,
+ 0x00018297,
+ 0x0002c49a,
+ 0x0003c680,
+ 0x0004c880,
+ 0x00060b00,
+ 0x00070d00,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 tdi_tbl20_ant1_rev0[] = {
+ 0x00014b26,
+ 0x00028d29,
+ 0x000393ad,
+ 0x00049630,
+ 0x0005d833,
+ 0x0006da36,
+ 0x00099c3a,
+ 0x000a9e3d,
+ 0x000bc081,
+ 0x000cc284,
+ 0x000dc488,
+ 0x000f068b,
+ 0x0000488e,
+ 0x00018b91,
+ 0x0002d214,
+ 0x0003d418,
+ 0x0004d6a7,
+ 0x000618aa,
+ 0x00071aae,
+ 0x0009dcb1,
+ 0x000b1eb4,
+ 0x000c0137,
+ 0x000d033b,
+ 0x000e053e,
+ 0x000f4702,
+ 0x00008905,
+ 0x00020c09,
+ 0x0003128c,
+ 0x0004148f,
+ 0x00051712,
+ 0x00065916,
+ 0x00091b19,
+ 0x000a1d28,
+ 0x000b5f2c,
+ 0x000c41af,
+ 0x000d43b2,
+ 0x000e85b5,
+ 0x000f87b8,
+ 0x0000c9bc,
+ 0x00024cbf,
+ 0x00035303,
+ 0x00045506,
+ 0x0005978a,
+ 0x0006998d,
+ 0x00095b90,
+ 0x000a5d93,
+ 0x000b9f97,
+ 0x000c821a,
+ 0x000d8400,
+ 0x000ec600,
+ 0x000fc800,
+ 0x00010a00,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 tdi_tbl40_ant0_rev0[] = {
+ 0x0011a346,
+ 0x00136ccf,
+ 0x0014f5d9,
+ 0x001641e2,
+ 0x0017cb6b,
+ 0x00195475,
+ 0x001b2383,
+ 0x001cad0c,
+ 0x001e7616,
+ 0x0000821f,
+ 0x00020ba8,
+ 0x0003d4b2,
+ 0x00056447,
+ 0x00072dd0,
+ 0x0008b6da,
+ 0x000a02e3,
+ 0x000b8c6c,
+ 0x000d15f6,
+ 0x0011e484,
+ 0x0013ae0d,
+ 0x00153717,
+ 0x00168320,
+ 0x00180ca9,
+ 0x00199633,
+ 0x001b6548,
+ 0x001ceed1,
+ 0x001eb7db,
+ 0x0000c3e4,
+ 0x00024d6d,
+ 0x000416f7,
+ 0x0005a585,
+ 0x00076f0f,
+ 0x0008f818,
+ 0x000a4421,
+ 0x000bcdab,
+ 0x000d9734,
+ 0x00122649,
+ 0x0013efd2,
+ 0x001578dc,
+ 0x0016c4e5,
+ 0x00184e6e,
+ 0x001a17f8,
+ 0x001ba686,
+ 0x001d3010,
+ 0x001ef999,
+ 0x00010522,
+ 0x00028eac,
+ 0x00045835,
+ 0x0005e74a,
+ 0x0007b0d3,
+ 0x00093a5d,
+ 0x000a85e6,
+ 0x000c0f6f,
+ 0x000dd8f9,
+ 0x00126787,
+ 0x00143111,
+ 0x0015ba9a,
+ 0x00170623,
+ 0x00188fad,
+ 0x001a5936,
+ 0x001be84b,
+ 0x001db1d4,
+ 0x001f3b5e,
+ 0x000146e7,
+ 0x00031070,
+ 0x000499fa,
+ 0x00062888,
+ 0x0007f212,
+ 0x00097b9b,
+ 0x000ac7a4,
+ 0x000c50ae,
+ 0x000e1a37,
+ 0x0012a94c,
+ 0x001472d5,
+ 0x0015fc5f,
+ 0x00174868,
+ 0x0018d171,
+ 0x001a9afb,
+ 0x001c2989,
+ 0x001df313,
+ 0x001f7c9c,
+ 0x000188a5,
+ 0x000351af,
+ 0x0004db38,
+ 0x0006aa4d,
+ 0x000833d7,
+ 0x0009bd60,
+ 0x000b0969,
+ 0x000c9273,
+ 0x000e5bfc,
+ 0x00132a8a,
+ 0x0014b414,
+ 0x00163d9d,
+ 0x001789a6,
+ 0x001912b0,
+ 0x001adc39,
+ 0x001c6bce,
+ 0x001e34d8,
+ 0x001fbe61,
+ 0x0001ca6a,
+ 0x00039374,
+ 0x00051cfd,
+ 0x0006ec0b,
+ 0x00087515,
+ 0x0009fe9e,
+ 0x000b4aa7,
+ 0x000cd3b1,
+ 0x000e9d3a,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 tdi_tbl40_ant1_rev0[] = {
+ 0x001edb36,
+ 0x000129ca,
+ 0x0002b353,
+ 0x00047cdd,
+ 0x0005c8e6,
+ 0x000791ef,
+ 0x00091bf9,
+ 0x000aaa07,
+ 0x000c3391,
+ 0x000dfd1a,
+ 0x00120923,
+ 0x0013d22d,
+ 0x00155c37,
+ 0x0016eacb,
+ 0x00187454,
+ 0x001a3dde,
+ 0x001b89e7,
+ 0x001d12f0,
+ 0x001f1cfa,
+ 0x00016b88,
+ 0x00033492,
+ 0x0004be1b,
+ 0x00060a24,
+ 0x0007d32e,
+ 0x00095d38,
+ 0x000aec4c,
+ 0x000c7555,
+ 0x000e3edf,
+ 0x00124ae8,
+ 0x001413f1,
+ 0x0015a37b,
+ 0x00172c89,
+ 0x0018b593,
+ 0x001a419c,
+ 0x001bcb25,
+ 0x001d942f,
+ 0x001f63b9,
+ 0x0001ad4d,
+ 0x00037657,
+ 0x0004c260,
+ 0x00068be9,
+ 0x000814f3,
+ 0x0009a47c,
+ 0x000b2d8a,
+ 0x000cb694,
+ 0x000e429d,
+ 0x00128c26,
+ 0x001455b0,
+ 0x0015e4ba,
+ 0x00176e4e,
+ 0x0018f758,
+ 0x001a8361,
+ 0x001c0cea,
+ 0x001dd674,
+ 0x001fa57d,
+ 0x0001ee8b,
+ 0x0003b795,
+ 0x0005039e,
+ 0x0006cd27,
+ 0x000856b1,
+ 0x0009e5c6,
+ 0x000b6f4f,
+ 0x000cf859,
+ 0x000e8462,
+ 0x00130deb,
+ 0x00149775,
+ 0x00162603,
+ 0x0017af8c,
+ 0x00193896,
+ 0x001ac49f,
+ 0x001c4e28,
+ 0x001e17b2,
+ 0x0000a6c7,
+ 0x00023050,
+ 0x0003f9da,
+ 0x00054563,
+ 0x00070eec,
+ 0x00089876,
+ 0x000a2704,
+ 0x000bb08d,
+ 0x000d3a17,
+ 0x001185a0,
+ 0x00134f29,
+ 0x0014d8b3,
+ 0x001667c8,
+ 0x0017f151,
+ 0x00197adb,
+ 0x001b0664,
+ 0x001c8fed,
+ 0x001e5977,
+ 0x0000e805,
+ 0x0002718f,
+ 0x00043b18,
+ 0x000586a1,
+ 0x0007502b,
+ 0x0008d9b4,
+ 0x000a68c9,
+ 0x000bf252,
+ 0x000dbbdc,
+ 0x0011c7e5,
+ 0x001390ee,
+ 0x00151a78,
+ 0x0016a906,
+ 0x00183290,
+ 0x0019bc19,
+ 0x001b4822,
+ 0x001cd12c,
+ 0x001e9ab5,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u16 bdi_tbl_rev0[] = {
+ 0x0070,
+ 0x0126,
+ 0x012c,
+ 0x0246,
+ 0x048d,
+ 0x04d2,
+};
+
+const u32 chanest_tbl_rev0[] = {
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+};
+
+const u8 mcs_tbl_rev0[] = {
+ 0x00,
+ 0x08,
+ 0x0a,
+ 0x10,
+ 0x12,
+ 0x19,
+ 0x1a,
+ 0x1c,
+ 0x40,
+ 0x48,
+ 0x4a,
+ 0x50,
+ 0x52,
+ 0x59,
+ 0x5a,
+ 0x5c,
+ 0x80,
+ 0x88,
+ 0x8a,
+ 0x90,
+ 0x92,
+ 0x99,
+ 0x9a,
+ 0x9c,
+ 0xc0,
+ 0xc8,
+ 0xca,
+ 0xd0,
+ 0xd2,
+ 0xd9,
+ 0xda,
+ 0xdc,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x01,
+ 0x02,
+ 0x04,
+ 0x08,
+ 0x09,
+ 0x0a,
+ 0x0c,
+ 0x10,
+ 0x11,
+ 0x12,
+ 0x14,
+ 0x18,
+ 0x19,
+ 0x1a,
+ 0x1c,
+ 0x20,
+ 0x21,
+ 0x22,
+ 0x24,
+ 0x40,
+ 0x41,
+ 0x42,
+ 0x44,
+ 0x48,
+ 0x49,
+ 0x4a,
+ 0x4c,
+ 0x50,
+ 0x51,
+ 0x52,
+ 0x54,
+ 0x58,
+ 0x59,
+ 0x5a,
+ 0x5c,
+ 0x60,
+ 0x61,
+ 0x62,
+ 0x64,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+};
+
+const u32 noise_var_tbl0_rev0[] = {
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+};
+
+const u32 noise_var_tbl1_rev0[] = {
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+};
+
+const u8 est_pwr_lut_core0_rev0[] = {
+ 0x50,
+ 0x4f,
+ 0x4e,
+ 0x4d,
+ 0x4c,
+ 0x4b,
+ 0x4a,
+ 0x49,
+ 0x48,
+ 0x47,
+ 0x46,
+ 0x45,
+ 0x44,
+ 0x43,
+ 0x42,
+ 0x41,
+ 0x40,
+ 0x3f,
+ 0x3e,
+ 0x3d,
+ 0x3c,
+ 0x3b,
+ 0x3a,
+ 0x39,
+ 0x38,
+ 0x37,
+ 0x36,
+ 0x35,
+ 0x34,
+ 0x33,
+ 0x32,
+ 0x31,
+ 0x30,
+ 0x2f,
+ 0x2e,
+ 0x2d,
+ 0x2c,
+ 0x2b,
+ 0x2a,
+ 0x29,
+ 0x28,
+ 0x27,
+ 0x26,
+ 0x25,
+ 0x24,
+ 0x23,
+ 0x22,
+ 0x21,
+ 0x20,
+ 0x1f,
+ 0x1e,
+ 0x1d,
+ 0x1c,
+ 0x1b,
+ 0x1a,
+ 0x19,
+ 0x18,
+ 0x17,
+ 0x16,
+ 0x15,
+ 0x14,
+ 0x13,
+ 0x12,
+ 0x11,
+};
+
+const u8 est_pwr_lut_core1_rev0[] = {
+ 0x50,
+ 0x4f,
+ 0x4e,
+ 0x4d,
+ 0x4c,
+ 0x4b,
+ 0x4a,
+ 0x49,
+ 0x48,
+ 0x47,
+ 0x46,
+ 0x45,
+ 0x44,
+ 0x43,
+ 0x42,
+ 0x41,
+ 0x40,
+ 0x3f,
+ 0x3e,
+ 0x3d,
+ 0x3c,
+ 0x3b,
+ 0x3a,
+ 0x39,
+ 0x38,
+ 0x37,
+ 0x36,
+ 0x35,
+ 0x34,
+ 0x33,
+ 0x32,
+ 0x31,
+ 0x30,
+ 0x2f,
+ 0x2e,
+ 0x2d,
+ 0x2c,
+ 0x2b,
+ 0x2a,
+ 0x29,
+ 0x28,
+ 0x27,
+ 0x26,
+ 0x25,
+ 0x24,
+ 0x23,
+ 0x22,
+ 0x21,
+ 0x20,
+ 0x1f,
+ 0x1e,
+ 0x1d,
+ 0x1c,
+ 0x1b,
+ 0x1a,
+ 0x19,
+ 0x18,
+ 0x17,
+ 0x16,
+ 0x15,
+ 0x14,
+ 0x13,
+ 0x12,
+ 0x11,
+};
+
+const u8 adj_pwr_lut_core0_rev0[] = {
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+};
+
+const u8 adj_pwr_lut_core1_rev0[] = {
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+};
+
+const u32 gainctrl_lut_core0_rev0[] = {
+ 0x03cc2b44,
+ 0x03cc2b42,
+ 0x03cc2b40,
+ 0x03cc2b3e,
+ 0x03cc2b3d,
+ 0x03cc2b3b,
+ 0x03c82b44,
+ 0x03c82b42,
+ 0x03c82b40,
+ 0x03c82b3e,
+ 0x03c82b3d,
+ 0x03c82b3b,
+ 0x03c82b39,
+ 0x03c82b38,
+ 0x03c82b36,
+ 0x03c82b34,
+ 0x03c42b44,
+ 0x03c42b42,
+ 0x03c42b40,
+ 0x03c42b3e,
+ 0x03c42b3d,
+ 0x03c42b3b,
+ 0x03c42b39,
+ 0x03c42b38,
+ 0x03c42b36,
+ 0x03c42b34,
+ 0x03c42b33,
+ 0x03c42b32,
+ 0x03c42b30,
+ 0x03c42b2f,
+ 0x03c42b2d,
+ 0x03c02b44,
+ 0x03c02b42,
+ 0x03c02b40,
+ 0x03c02b3e,
+ 0x03c02b3d,
+ 0x03c02b3b,
+ 0x03c02b39,
+ 0x03c02b38,
+ 0x03c02b36,
+ 0x03c02b34,
+ 0x03b02b44,
+ 0x03b02b42,
+ 0x03b02b40,
+ 0x03b02b3e,
+ 0x03b02b3d,
+ 0x03b02b3b,
+ 0x03b02b39,
+ 0x03b02b38,
+ 0x03b02b36,
+ 0x03b02b34,
+ 0x03b02b33,
+ 0x03b02b32,
+ 0x03b02b30,
+ 0x03b02b2f,
+ 0x03b02b2d,
+ 0x03a02b44,
+ 0x03a02b42,
+ 0x03a02b40,
+ 0x03a02b3e,
+ 0x03a02b3d,
+ 0x03a02b3b,
+ 0x03a02b39,
+ 0x03a02b38,
+ 0x03a02b36,
+ 0x03a02b34,
+ 0x03902b44,
+ 0x03902b42,
+ 0x03902b40,
+ 0x03902b3e,
+ 0x03902b3d,
+ 0x03902b3b,
+ 0x03902b39,
+ 0x03902b38,
+ 0x03902b36,
+ 0x03902b34,
+ 0x03902b33,
+ 0x03902b32,
+ 0x03902b30,
+ 0x03802b44,
+ 0x03802b42,
+ 0x03802b40,
+ 0x03802b3e,
+ 0x03802b3d,
+ 0x03802b3b,
+ 0x03802b39,
+ 0x03802b38,
+ 0x03802b36,
+ 0x03802b34,
+ 0x03802b33,
+ 0x03802b32,
+ 0x03802b30,
+ 0x03802b2f,
+ 0x03802b2d,
+ 0x03802b2c,
+ 0x03802b2b,
+ 0x03802b2a,
+ 0x03802b29,
+ 0x03802b27,
+ 0x03802b26,
+ 0x03802b25,
+ 0x03802b24,
+ 0x03802b23,
+ 0x03802b22,
+ 0x03802b21,
+ 0x03802b20,
+ 0x03802b1f,
+ 0x03802b1e,
+ 0x03802b1e,
+ 0x03802b1d,
+ 0x03802b1c,
+ 0x03802b1b,
+ 0x03802b1a,
+ 0x03802b1a,
+ 0x03802b19,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x00002b00,
+};
+
+const u32 gainctrl_lut_core1_rev0[] = {
+ 0x03cc2b44,
+ 0x03cc2b42,
+ 0x03cc2b40,
+ 0x03cc2b3e,
+ 0x03cc2b3d,
+ 0x03cc2b3b,
+ 0x03c82b44,
+ 0x03c82b42,
+ 0x03c82b40,
+ 0x03c82b3e,
+ 0x03c82b3d,
+ 0x03c82b3b,
+ 0x03c82b39,
+ 0x03c82b38,
+ 0x03c82b36,
+ 0x03c82b34,
+ 0x03c42b44,
+ 0x03c42b42,
+ 0x03c42b40,
+ 0x03c42b3e,
+ 0x03c42b3d,
+ 0x03c42b3b,
+ 0x03c42b39,
+ 0x03c42b38,
+ 0x03c42b36,
+ 0x03c42b34,
+ 0x03c42b33,
+ 0x03c42b32,
+ 0x03c42b30,
+ 0x03c42b2f,
+ 0x03c42b2d,
+ 0x03c02b44,
+ 0x03c02b42,
+ 0x03c02b40,
+ 0x03c02b3e,
+ 0x03c02b3d,
+ 0x03c02b3b,
+ 0x03c02b39,
+ 0x03c02b38,
+ 0x03c02b36,
+ 0x03c02b34,
+ 0x03b02b44,
+ 0x03b02b42,
+ 0x03b02b40,
+ 0x03b02b3e,
+ 0x03b02b3d,
+ 0x03b02b3b,
+ 0x03b02b39,
+ 0x03b02b38,
+ 0x03b02b36,
+ 0x03b02b34,
+ 0x03b02b33,
+ 0x03b02b32,
+ 0x03b02b30,
+ 0x03b02b2f,
+ 0x03b02b2d,
+ 0x03a02b44,
+ 0x03a02b42,
+ 0x03a02b40,
+ 0x03a02b3e,
+ 0x03a02b3d,
+ 0x03a02b3b,
+ 0x03a02b39,
+ 0x03a02b38,
+ 0x03a02b36,
+ 0x03a02b34,
+ 0x03902b44,
+ 0x03902b42,
+ 0x03902b40,
+ 0x03902b3e,
+ 0x03902b3d,
+ 0x03902b3b,
+ 0x03902b39,
+ 0x03902b38,
+ 0x03902b36,
+ 0x03902b34,
+ 0x03902b33,
+ 0x03902b32,
+ 0x03902b30,
+ 0x03802b44,
+ 0x03802b42,
+ 0x03802b40,
+ 0x03802b3e,
+ 0x03802b3d,
+ 0x03802b3b,
+ 0x03802b39,
+ 0x03802b38,
+ 0x03802b36,
+ 0x03802b34,
+ 0x03802b33,
+ 0x03802b32,
+ 0x03802b30,
+ 0x03802b2f,
+ 0x03802b2d,
+ 0x03802b2c,
+ 0x03802b2b,
+ 0x03802b2a,
+ 0x03802b29,
+ 0x03802b27,
+ 0x03802b26,
+ 0x03802b25,
+ 0x03802b24,
+ 0x03802b23,
+ 0x03802b22,
+ 0x03802b21,
+ 0x03802b20,
+ 0x03802b1f,
+ 0x03802b1e,
+ 0x03802b1e,
+ 0x03802b1d,
+ 0x03802b1c,
+ 0x03802b1b,
+ 0x03802b1a,
+ 0x03802b1a,
+ 0x03802b19,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x03802b18,
+ 0x00002b00,
+};
+
+const u32 iq_lut_core0_rev0[] = {
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+};
+
+const u32 iq_lut_core1_rev0[] = {
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+ 0x0000007f,
+};
+
+const u16 loft_lut_core0_rev0[] = {
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+};
+
+const u16 loft_lut_core1_rev0[] = {
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+ 0x0000,
+ 0x0101,
+ 0x0002,
+ 0x0103,
+};
+
+const mimophytbl_info_t mimophytbl_info_rev0_volatile[] = {
+ {&bdi_tbl_rev0, sizeof(bdi_tbl_rev0) / sizeof(bdi_tbl_rev0[0]), 21, 0,
+ 16}
+ ,
+ {&pltlut_tbl_rev0, sizeof(pltlut_tbl_rev0) / sizeof(pltlut_tbl_rev0[0]),
+ 20, 0, 32}
+ ,
+ {&gainctrl_lut_core0_rev0,
+ sizeof(gainctrl_lut_core0_rev0) / sizeof(gainctrl_lut_core0_rev0[0]),
+ 26, 192, 32}
+ ,
+ {&gainctrl_lut_core1_rev0,
+ sizeof(gainctrl_lut_core1_rev0) / sizeof(gainctrl_lut_core1_rev0[0]),
+ 27, 192, 32}
+ ,
+
+ {&est_pwr_lut_core0_rev0,
+ sizeof(est_pwr_lut_core0_rev0) / sizeof(est_pwr_lut_core0_rev0[0]), 26,
+ 0, 8}
+ ,
+ {&est_pwr_lut_core1_rev0,
+ sizeof(est_pwr_lut_core1_rev0) / sizeof(est_pwr_lut_core1_rev0[0]), 27,
+ 0, 8}
+ ,
+ {&adj_pwr_lut_core0_rev0,
+ sizeof(adj_pwr_lut_core0_rev0) / sizeof(adj_pwr_lut_core0_rev0[0]), 26,
+ 64, 8}
+ ,
+ {&adj_pwr_lut_core1_rev0,
+ sizeof(adj_pwr_lut_core1_rev0) / sizeof(adj_pwr_lut_core1_rev0[0]), 27,
+ 64, 8}
+ ,
+ {&iq_lut_core0_rev0,
+ sizeof(iq_lut_core0_rev0) / sizeof(iq_lut_core0_rev0[0]), 26, 320, 32}
+ ,
+ {&iq_lut_core1_rev0,
+ sizeof(iq_lut_core1_rev0) / sizeof(iq_lut_core1_rev0[0]), 27, 320, 32}
+ ,
+ {&loft_lut_core0_rev0,
+ sizeof(loft_lut_core0_rev0) / sizeof(loft_lut_core0_rev0[0]), 26, 448,
+ 16}
+ ,
+ {&loft_lut_core1_rev0,
+ sizeof(loft_lut_core1_rev0) / sizeof(loft_lut_core1_rev0[0]), 27, 448,
+ 16}
+ ,
+};
+
+const mimophytbl_info_t mimophytbl_info_rev0[] = {
+ {&frame_struct_rev0,
+ sizeof(frame_struct_rev0) / sizeof(frame_struct_rev0[0]), 10, 0, 32}
+ ,
+ {&frame_lut_rev0, sizeof(frame_lut_rev0) / sizeof(frame_lut_rev0[0]),
+ 24, 0, 8}
+ ,
+ {&tmap_tbl_rev0, sizeof(tmap_tbl_rev0) / sizeof(tmap_tbl_rev0[0]), 12,
+ 0, 32}
+ ,
+ {&tdtrn_tbl_rev0, sizeof(tdtrn_tbl_rev0) / sizeof(tdtrn_tbl_rev0[0]),
+ 14, 0, 32}
+ ,
+ {&intlv_tbl_rev0, sizeof(intlv_tbl_rev0) / sizeof(intlv_tbl_rev0[0]),
+ 13, 0, 32}
+ ,
+ {&pilot_tbl_rev0, sizeof(pilot_tbl_rev0) / sizeof(pilot_tbl_rev0[0]),
+ 11, 0, 16}
+ ,
+ {&tdi_tbl20_ant0_rev0,
+ sizeof(tdi_tbl20_ant0_rev0) / sizeof(tdi_tbl20_ant0_rev0[0]), 19, 128,
+ 32}
+ ,
+ {&tdi_tbl20_ant1_rev0,
+ sizeof(tdi_tbl20_ant1_rev0) / sizeof(tdi_tbl20_ant1_rev0[0]), 19, 256,
+ 32}
+ ,
+ {&tdi_tbl40_ant0_rev0,
+ sizeof(tdi_tbl40_ant0_rev0) / sizeof(tdi_tbl40_ant0_rev0[0]), 19, 640,
+ 32}
+ ,
+ {&tdi_tbl40_ant1_rev0,
+ sizeof(tdi_tbl40_ant1_rev0) / sizeof(tdi_tbl40_ant1_rev0[0]), 19, 768,
+ 32}
+ ,
+ {&chanest_tbl_rev0,
+ sizeof(chanest_tbl_rev0) / sizeof(chanest_tbl_rev0[0]), 22, 0, 32}
+ ,
+ {&mcs_tbl_rev0, sizeof(mcs_tbl_rev0) / sizeof(mcs_tbl_rev0[0]), 18, 0, 8}
+ ,
+ {&noise_var_tbl0_rev0,
+ sizeof(noise_var_tbl0_rev0) / sizeof(noise_var_tbl0_rev0[0]), 16, 0,
+ 32}
+ ,
+ {&noise_var_tbl1_rev0,
+ sizeof(noise_var_tbl1_rev0) / sizeof(noise_var_tbl1_rev0[0]), 16, 128,
+ 32}
+ ,
+};
+
+const u32 mimophytbl_info_sz_rev0 =
+ sizeof(mimophytbl_info_rev0) / sizeof(mimophytbl_info_rev0[0]);
+const u32 mimophytbl_info_sz_rev0_volatile =
+ sizeof(mimophytbl_info_rev0_volatile) /
+ sizeof(mimophytbl_info_rev0_volatile[0]);
+
+const u16 ant_swctrl_tbl_rev3[] = {
+ 0x0082,
+ 0x0082,
+ 0x0211,
+ 0x0222,
+ 0x0328,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0144,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0188,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0082,
+ 0x0082,
+ 0x0211,
+ 0x0222,
+ 0x0328,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0144,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0188,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+};
+
+const u16 ant_swctrl_tbl_rev3_1[] = {
+ 0x0022,
+ 0x0022,
+ 0x0011,
+ 0x0022,
+ 0x0022,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0011,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0022,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0022,
+ 0x0022,
+ 0x0011,
+ 0x0022,
+ 0x0022,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0011,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0022,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+};
+
+const u16 ant_swctrl_tbl_rev3_2[] = {
+ 0x0088,
+ 0x0088,
+ 0x0044,
+ 0x0088,
+ 0x0088,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0044,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0088,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0088,
+ 0x0088,
+ 0x0044,
+ 0x0088,
+ 0x0088,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0044,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0088,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+};
+
+const u16 ant_swctrl_tbl_rev3_3[] = {
+ 0x022,
+ 0x022,
+ 0x011,
+ 0x022,
+ 0x000,
+ 0x000,
+ 0x000,
+ 0x000,
+ 0x011,
+ 0x000,
+ 0x000,
+ 0x000,
+ 0x022,
+ 0x000,
+ 0x000,
+ 0x3cc,
+ 0x022,
+ 0x022,
+ 0x011,
+ 0x022,
+ 0x000,
+ 0x000,
+ 0x000,
+ 0x000,
+ 0x011,
+ 0x000,
+ 0x000,
+ 0x000,
+ 0x022,
+ 0x000,
+ 0x000,
+ 0x3cc
+};
+
+const u32 frame_struct_rev3[] = {
+ 0x08004a04,
+ 0x00100000,
+ 0x01000a05,
+ 0x00100020,
+ 0x09804506,
+ 0x00100030,
+ 0x09804507,
+ 0x00100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08004a0c,
+ 0x00100004,
+ 0x01000a0d,
+ 0x00100024,
+ 0x0980450e,
+ 0x00100034,
+ 0x0980450f,
+ 0x00100034,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a04,
+ 0x00100000,
+ 0x11008a05,
+ 0x00100020,
+ 0x1980c506,
+ 0x00100030,
+ 0x21810506,
+ 0x00100030,
+ 0x21810506,
+ 0x00100030,
+ 0x01800504,
+ 0x00100030,
+ 0x11808505,
+ 0x00100030,
+ 0x29814507,
+ 0x01100030,
+ 0x00000a04,
+ 0x00100000,
+ 0x11008a05,
+ 0x00100020,
+ 0x21810506,
+ 0x00100030,
+ 0x21810506,
+ 0x00100030,
+ 0x29814507,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a0c,
+ 0x00100008,
+ 0x11008a0d,
+ 0x00100028,
+ 0x1980c50e,
+ 0x00100038,
+ 0x2181050e,
+ 0x00100038,
+ 0x2181050e,
+ 0x00100038,
+ 0x0180050c,
+ 0x00100038,
+ 0x1180850d,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000a0c,
+ 0x00100008,
+ 0x11008a0d,
+ 0x00100028,
+ 0x2181050e,
+ 0x00100038,
+ 0x2181050e,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08004a04,
+ 0x00100000,
+ 0x01000a05,
+ 0x00100020,
+ 0x1980c506,
+ 0x00100030,
+ 0x1980c506,
+ 0x00100030,
+ 0x11808504,
+ 0x00100030,
+ 0x3981ca05,
+ 0x00100030,
+ 0x29814507,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x10008a04,
+ 0x00100000,
+ 0x3981ca05,
+ 0x00100030,
+ 0x1980c506,
+ 0x00100030,
+ 0x29814507,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08004a0c,
+ 0x00100008,
+ 0x01000a0d,
+ 0x00100028,
+ 0x1980c50e,
+ 0x00100038,
+ 0x1980c50e,
+ 0x00100038,
+ 0x1180850c,
+ 0x00100038,
+ 0x3981ca0d,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x10008a0c,
+ 0x00100008,
+ 0x3981ca0d,
+ 0x00100038,
+ 0x1980c50e,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40021404,
+ 0x00100000,
+ 0x02001405,
+ 0x00100040,
+ 0x0b004a06,
+ 0x01900060,
+ 0x13008a06,
+ 0x01900060,
+ 0x13008a06,
+ 0x01900060,
+ 0x43020a04,
+ 0x00100060,
+ 0x1b00ca05,
+ 0x00100060,
+ 0x23010a07,
+ 0x01500060,
+ 0x40021404,
+ 0x00100000,
+ 0x1a00d405,
+ 0x00100040,
+ 0x13008a06,
+ 0x01900060,
+ 0x13008a06,
+ 0x01900060,
+ 0x23010a07,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100010,
+ 0x0200140d,
+ 0x00100050,
+ 0x0b004a0e,
+ 0x01900070,
+ 0x13008a0e,
+ 0x01900070,
+ 0x13008a0e,
+ 0x01900070,
+ 0x43020a0c,
+ 0x00100070,
+ 0x1b00ca0d,
+ 0x00100070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x4002140c,
+ 0x00100010,
+ 0x1a00d40d,
+ 0x00100050,
+ 0x13008a0e,
+ 0x01900070,
+ 0x13008a0e,
+ 0x01900070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x50029404,
+ 0x00100000,
+ 0x32019405,
+ 0x00100040,
+ 0x0b004a06,
+ 0x01900060,
+ 0x0b004a06,
+ 0x01900060,
+ 0x5b02ca04,
+ 0x00100060,
+ 0x3b01d405,
+ 0x00100060,
+ 0x23010a07,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x5802d404,
+ 0x00100000,
+ 0x3b01d405,
+ 0x00100060,
+ 0x0b004a06,
+ 0x01900060,
+ 0x23010a07,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x5002940c,
+ 0x00100010,
+ 0x3201940d,
+ 0x00100050,
+ 0x0b004a0e,
+ 0x01900070,
+ 0x0b004a0e,
+ 0x01900070,
+ 0x5b02ca0c,
+ 0x00100070,
+ 0x3b01d40d,
+ 0x00100070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x5802d40c,
+ 0x00100010,
+ 0x3b01d40d,
+ 0x00100070,
+ 0x0b004a0e,
+ 0x01900070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40021404,
+ 0x000f4800,
+ 0x62031405,
+ 0x00100040,
+ 0x53028a06,
+ 0x01900060,
+ 0x53028a07,
+ 0x01900060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x000f4808,
+ 0x6203140d,
+ 0x00100048,
+ 0x53028a0e,
+ 0x01900068,
+ 0x53028a0f,
+ 0x01900068,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a0c,
+ 0x00100004,
+ 0x11008a0d,
+ 0x00100024,
+ 0x1980c50e,
+ 0x00100034,
+ 0x2181050e,
+ 0x00100034,
+ 0x2181050e,
+ 0x00100034,
+ 0x0180050c,
+ 0x00100038,
+ 0x1180850d,
+ 0x00100038,
+ 0x1181850d,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000a0c,
+ 0x00100008,
+ 0x11008a0d,
+ 0x00100028,
+ 0x2181050e,
+ 0x00100038,
+ 0x2181050e,
+ 0x00100038,
+ 0x1181850d,
+ 0x00100038,
+ 0x2981450f,
+ 0x01100038,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x08004a04,
+ 0x00100000,
+ 0x01000a05,
+ 0x00100020,
+ 0x0180c506,
+ 0x00100030,
+ 0x0180c506,
+ 0x00100030,
+ 0x2180c50c,
+ 0x00100030,
+ 0x49820a0d,
+ 0x0016a130,
+ 0x41824a0d,
+ 0x0016a130,
+ 0x2981450f,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x2000ca0c,
+ 0x00100000,
+ 0x49820a0d,
+ 0x0016a130,
+ 0x1980c50e,
+ 0x00100030,
+ 0x41824a0d,
+ 0x0016a130,
+ 0x2981450f,
+ 0x01100030,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100008,
+ 0x0200140d,
+ 0x00100048,
+ 0x0b004a0e,
+ 0x01900068,
+ 0x13008a0e,
+ 0x01900068,
+ 0x13008a0e,
+ 0x01900068,
+ 0x43020a0c,
+ 0x00100070,
+ 0x1b00ca0d,
+ 0x00100070,
+ 0x1b014a0d,
+ 0x00100070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100010,
+ 0x1a00d40d,
+ 0x00100050,
+ 0x13008a0e,
+ 0x01900070,
+ 0x13008a0e,
+ 0x01900070,
+ 0x1b014a0d,
+ 0x00100070,
+ 0x23010a0f,
+ 0x01500070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x50029404,
+ 0x00100000,
+ 0x32019405,
+ 0x00100040,
+ 0x03004a06,
+ 0x01900060,
+ 0x03004a06,
+ 0x01900060,
+ 0x6b030a0c,
+ 0x00100060,
+ 0x4b02140d,
+ 0x0016a160,
+ 0x4302540d,
+ 0x0016a160,
+ 0x23010a0f,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x6b03140c,
+ 0x00100060,
+ 0x4b02140d,
+ 0x0016a160,
+ 0x0b004a0e,
+ 0x01900060,
+ 0x4302540d,
+ 0x0016a160,
+ 0x23010a0f,
+ 0x01500060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40021404,
+ 0x00100000,
+ 0x1a00d405,
+ 0x00100040,
+ 0x53028a06,
+ 0x01900060,
+ 0x5b02ca06,
+ 0x01900060,
+ 0x5b02ca06,
+ 0x01900060,
+ 0x43020a04,
+ 0x00100060,
+ 0x1b00ca05,
+ 0x00100060,
+ 0x53028a07,
+ 0x0190c060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100010,
+ 0x1a00d40d,
+ 0x00100050,
+ 0x53028a0e,
+ 0x01900070,
+ 0x5b02ca0e,
+ 0x01900070,
+ 0x5b02ca0e,
+ 0x01900070,
+ 0x43020a0c,
+ 0x00100070,
+ 0x1b00ca0d,
+ 0x00100070,
+ 0x53028a0f,
+ 0x0190c070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x40021404,
+ 0x00100000,
+ 0x1a00d405,
+ 0x00100040,
+ 0x5b02ca06,
+ 0x01900060,
+ 0x5b02ca06,
+ 0x01900060,
+ 0x53028a07,
+ 0x0190c060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x4002140c,
+ 0x00100010,
+ 0x1a00d40d,
+ 0x00100050,
+ 0x5b02ca0e,
+ 0x01900070,
+ 0x5b02ca0e,
+ 0x01900070,
+ 0x53028a0f,
+ 0x0190c070,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u16 pilot_tbl_rev3[] = {
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0xff08,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0x80d5,
+ 0xff0a,
+ 0xff82,
+ 0xffa0,
+ 0xff28,
+ 0xffff,
+ 0xffff,
+ 0xffff,
+ 0xffff,
+ 0xff82,
+ 0xffa0,
+ 0xff28,
+ 0xff0a,
+ 0xffff,
+ 0xffff,
+ 0xffff,
+ 0xffff,
+ 0xf83f,
+ 0xfa1f,
+ 0xfa97,
+ 0xfab5,
+ 0xf2bd,
+ 0xf0bf,
+ 0xffff,
+ 0xffff,
+ 0xf017,
+ 0xf815,
+ 0xf215,
+ 0xf095,
+ 0xf035,
+ 0xf01d,
+ 0xffff,
+ 0xffff,
+ 0xff08,
+ 0xff02,
+ 0xff80,
+ 0xff20,
+ 0xff08,
+ 0xff02,
+ 0xff80,
+ 0xff20,
+ 0xf01f,
+ 0xf817,
+ 0xfa15,
+ 0xf295,
+ 0xf0b5,
+ 0xf03d,
+ 0xffff,
+ 0xffff,
+ 0xf82a,
+ 0xfa0a,
+ 0xfa82,
+ 0xfaa0,
+ 0xf2a8,
+ 0xf0aa,
+ 0xffff,
+ 0xffff,
+ 0xf002,
+ 0xf800,
+ 0xf200,
+ 0xf080,
+ 0xf020,
+ 0xf008,
+ 0xffff,
+ 0xffff,
+ 0xf00a,
+ 0xf802,
+ 0xfa00,
+ 0xf280,
+ 0xf0a0,
+ 0xf028,
+ 0xffff,
+ 0xffff,
+};
+
+const u32 tmap_tbl_rev3[] = {
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x000aa888,
+ 0x88880000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa2222220,
+ 0x22222222,
+ 0x22c22222,
+ 0x00000222,
+ 0x22000000,
+ 0x2222a222,
+ 0x22222222,
+ 0x222222a2,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00011111,
+ 0x11110000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0xa8aa88a0,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x00088aaa,
+ 0xaaaa0000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xaaa8aaa0,
+ 0x8aaa8aaa,
+ 0xaa8a8a8a,
+ 0x000aaa88,
+ 0x8aaa0000,
+ 0xaaa8a888,
+ 0x8aa88a8a,
+ 0x8a88a888,
+ 0x08080a00,
+ 0x0a08080a,
+ 0x080a0a08,
+ 0x00080808,
+ 0x080a0000,
+ 0x080a0808,
+ 0x080a0808,
+ 0x0a0a0a08,
+ 0xa0a0a0a0,
+ 0x80a0a080,
+ 0x8080a0a0,
+ 0x00008080,
+ 0x80a00000,
+ 0x80a080a0,
+ 0xa080a0a0,
+ 0x8080a0a0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x99999000,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb90,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00aaa888,
+ 0x22000000,
+ 0x2222b222,
+ 0x22222222,
+ 0x222222b2,
+ 0xb2222220,
+ 0x22222222,
+ 0x22d22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x33000000,
+ 0x3333b333,
+ 0x33333333,
+ 0x333333b3,
+ 0xb3333330,
+ 0x33333333,
+ 0x33d33333,
+ 0x00000333,
+ 0x22000000,
+ 0x2222a222,
+ 0x22222222,
+ 0x222222a2,
+ 0xa2222220,
+ 0x22222222,
+ 0x22c22222,
+ 0x00000222,
+ 0x99b99b00,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb99,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x08aaa888,
+ 0x22222200,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0x22222222,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x11111111,
+ 0xf1111111,
+ 0x11111111,
+ 0x11f11111,
+ 0x01111111,
+ 0xbb9bb900,
+ 0xb9b9bb99,
+ 0xb99bbbbb,
+ 0xbbbb9b9b,
+ 0xb9bb99bb,
+ 0xb99999b9,
+ 0xb9b9b99b,
+ 0x00000bbb,
+ 0xaa000000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xa8aa88aa,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x0a888aaa,
+ 0xaa000000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xa8aa88a0,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x00000aaa,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0xbbbbbb00,
+ 0x999bbbbb,
+ 0x9bb99b9b,
+ 0xb9b9b9bb,
+ 0xb9b99bbb,
+ 0xb9b9b9bb,
+ 0xb9bb9b99,
+ 0x00000999,
+ 0x8a000000,
+ 0xaa88a888,
+ 0xa88888aa,
+ 0xa88a8a88,
+ 0xa88aa88a,
+ 0x88a8aaaa,
+ 0xa8aa8aaa,
+ 0x0888a88a,
+ 0x0b0b0b00,
+ 0x090b0b0b,
+ 0x0b090b0b,
+ 0x0909090b,
+ 0x09090b0b,
+ 0x09090b0b,
+ 0x09090b09,
+ 0x00000909,
+ 0x0a000000,
+ 0x0a080808,
+ 0x080a080a,
+ 0x080a0a08,
+ 0x080a080a,
+ 0x0808080a,
+ 0x0a0a0a08,
+ 0x0808080a,
+ 0xb0b0b000,
+ 0x9090b0b0,
+ 0x90b09090,
+ 0xb0b0b090,
+ 0xb0b090b0,
+ 0x90b0b0b0,
+ 0xb0b09090,
+ 0x00000090,
+ 0x80000000,
+ 0xa080a080,
+ 0xa08080a0,
+ 0xa0808080,
+ 0xa080a080,
+ 0x80a0a0a0,
+ 0xa0a080a0,
+ 0x00a0a0a0,
+ 0x22000000,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0xf2222220,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00000111,
+ 0x33000000,
+ 0x3333f333,
+ 0x33333333,
+ 0x333333f3,
+ 0xf3333330,
+ 0x33333333,
+ 0x33f33333,
+ 0x00000333,
+ 0x22000000,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0xf2222220,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x99000000,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb90,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88888000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00aaa888,
+ 0x88a88a00,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x08aaa888,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 intlv_tbl_rev3[] = {
+ 0x00802070,
+ 0x0671188d,
+ 0x0a60192c,
+ 0x0a300e46,
+ 0x00c1188d,
+ 0x080024d2,
+ 0x00000070,
+};
+
+const u32 tdtrn_tbl_rev3[] = {
+ 0x061c061c,
+ 0x0050ee68,
+ 0xf592fe36,
+ 0xfe5212f6,
+ 0x00000c38,
+ 0xfe5212f6,
+ 0xf592fe36,
+ 0x0050ee68,
+ 0x061c061c,
+ 0xee680050,
+ 0xfe36f592,
+ 0x12f6fe52,
+ 0x0c380000,
+ 0x12f6fe52,
+ 0xfe36f592,
+ 0xee680050,
+ 0x061c061c,
+ 0x0050ee68,
+ 0xf592fe36,
+ 0xfe5212f6,
+ 0x00000c38,
+ 0xfe5212f6,
+ 0xf592fe36,
+ 0x0050ee68,
+ 0x061c061c,
+ 0xee680050,
+ 0xfe36f592,
+ 0x12f6fe52,
+ 0x0c380000,
+ 0x12f6fe52,
+ 0xfe36f592,
+ 0xee680050,
+ 0x05e305e3,
+ 0x004def0c,
+ 0xf5f3fe47,
+ 0xfe611246,
+ 0x00000bc7,
+ 0xfe611246,
+ 0xf5f3fe47,
+ 0x004def0c,
+ 0x05e305e3,
+ 0xef0c004d,
+ 0xfe47f5f3,
+ 0x1246fe61,
+ 0x0bc70000,
+ 0x1246fe61,
+ 0xfe47f5f3,
+ 0xef0c004d,
+ 0x05e305e3,
+ 0x004def0c,
+ 0xf5f3fe47,
+ 0xfe611246,
+ 0x00000bc7,
+ 0xfe611246,
+ 0xf5f3fe47,
+ 0x004def0c,
+ 0x05e305e3,
+ 0xef0c004d,
+ 0xfe47f5f3,
+ 0x1246fe61,
+ 0x0bc70000,
+ 0x1246fe61,
+ 0xfe47f5f3,
+ 0xef0c004d,
+ 0xfa58fa58,
+ 0xf895043b,
+ 0xff4c09c0,
+ 0xfbc6ffa8,
+ 0xfb84f384,
+ 0x0798f6f9,
+ 0x05760122,
+ 0x058409f6,
+ 0x0b500000,
+ 0x05b7f542,
+ 0x08860432,
+ 0x06ddfee7,
+ 0xfb84f384,
+ 0xf9d90664,
+ 0xf7e8025c,
+ 0x00fff7bd,
+ 0x05a805a8,
+ 0xf7bd00ff,
+ 0x025cf7e8,
+ 0x0664f9d9,
+ 0xf384fb84,
+ 0xfee706dd,
+ 0x04320886,
+ 0xf54205b7,
+ 0x00000b50,
+ 0x09f60584,
+ 0x01220576,
+ 0xf6f90798,
+ 0xf384fb84,
+ 0xffa8fbc6,
+ 0x09c0ff4c,
+ 0x043bf895,
+ 0x02d402d4,
+ 0x07de0270,
+ 0xfc96079c,
+ 0xf90afe94,
+ 0xfe00ff2c,
+ 0x02d4065d,
+ 0x092a0096,
+ 0x0014fbb8,
+ 0xfd2cfd2c,
+ 0x076afb3c,
+ 0x0096f752,
+ 0xf991fd87,
+ 0xfb2c0200,
+ 0xfeb8f960,
+ 0x08e0fc96,
+ 0x049802a8,
+ 0xfd2cfd2c,
+ 0x02a80498,
+ 0xfc9608e0,
+ 0xf960feb8,
+ 0x0200fb2c,
+ 0xfd87f991,
+ 0xf7520096,
+ 0xfb3c076a,
+ 0xfd2cfd2c,
+ 0xfbb80014,
+ 0x0096092a,
+ 0x065d02d4,
+ 0xff2cfe00,
+ 0xfe94f90a,
+ 0x079cfc96,
+ 0x027007de,
+ 0x02d402d4,
+ 0x027007de,
+ 0x079cfc96,
+ 0xfe94f90a,
+ 0xff2cfe00,
+ 0x065d02d4,
+ 0x0096092a,
+ 0xfbb80014,
+ 0xfd2cfd2c,
+ 0xfb3c076a,
+ 0xf7520096,
+ 0xfd87f991,
+ 0x0200fb2c,
+ 0xf960feb8,
+ 0xfc9608e0,
+ 0x02a80498,
+ 0xfd2cfd2c,
+ 0x049802a8,
+ 0x08e0fc96,
+ 0xfeb8f960,
+ 0xfb2c0200,
+ 0xf991fd87,
+ 0x0096f752,
+ 0x076afb3c,
+ 0xfd2cfd2c,
+ 0x0014fbb8,
+ 0x092a0096,
+ 0x02d4065d,
+ 0xfe00ff2c,
+ 0xf90afe94,
+ 0xfc96079c,
+ 0x07de0270,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x062a0000,
+ 0xfefa0759,
+ 0x08b80908,
+ 0xf396fc2d,
+ 0xf9d6045c,
+ 0xfc4ef608,
+ 0xf748f596,
+ 0x07b207bf,
+ 0x062a062a,
+ 0xf84ef841,
+ 0xf748f596,
+ 0x03b209f8,
+ 0xf9d6045c,
+ 0x0c6a03d3,
+ 0x08b80908,
+ 0x0106f8a7,
+ 0x062a0000,
+ 0xfefaf8a7,
+ 0x08b8f6f8,
+ 0xf39603d3,
+ 0xf9d6fba4,
+ 0xfc4e09f8,
+ 0xf7480a6a,
+ 0x07b2f841,
+ 0x062af9d6,
+ 0xf84e07bf,
+ 0xf7480a6a,
+ 0x03b2f608,
+ 0xf9d6fba4,
+ 0x0c6afc2d,
+ 0x08b8f6f8,
+ 0x01060759,
+ 0x062a0000,
+ 0xfefa0759,
+ 0x08b80908,
+ 0xf396fc2d,
+ 0xf9d6045c,
+ 0xfc4ef608,
+ 0xf748f596,
+ 0x07b207bf,
+ 0x062a062a,
+ 0xf84ef841,
+ 0xf748f596,
+ 0x03b209f8,
+ 0xf9d6045c,
+ 0x0c6a03d3,
+ 0x08b80908,
+ 0x0106f8a7,
+ 0x062a0000,
+ 0xfefaf8a7,
+ 0x08b8f6f8,
+ 0xf39603d3,
+ 0xf9d6fba4,
+ 0xfc4e09f8,
+ 0xf7480a6a,
+ 0x07b2f841,
+ 0x062af9d6,
+ 0xf84e07bf,
+ 0xf7480a6a,
+ 0x03b2f608,
+ 0xf9d6fba4,
+ 0x0c6afc2d,
+ 0x08b8f6f8,
+ 0x01060759,
+ 0x061c061c,
+ 0xff30009d,
+ 0xffb21141,
+ 0xfd87fb54,
+ 0xf65dfe59,
+ 0x02eef99e,
+ 0x0166f03c,
+ 0xfff809b6,
+ 0x000008a4,
+ 0x000af42b,
+ 0x00eff577,
+ 0xfa840bf2,
+ 0xfc02ff51,
+ 0x08260f67,
+ 0xfff0036f,
+ 0x0842f9c3,
+ 0x00000000,
+ 0x063df7be,
+ 0xfc910010,
+ 0xf099f7da,
+ 0x00af03fe,
+ 0xf40e057c,
+ 0x0a89ff11,
+ 0x0bd5fff6,
+ 0xf75c0000,
+ 0xf64a0008,
+ 0x0fc4fe9a,
+ 0x0662fd12,
+ 0x01a709a3,
+ 0x04ac0279,
+ 0xeebf004e,
+ 0xff6300d0,
+ 0xf9e4f9e4,
+ 0x00d0ff63,
+ 0x004eeebf,
+ 0x027904ac,
+ 0x09a301a7,
+ 0xfd120662,
+ 0xfe9a0fc4,
+ 0x0008f64a,
+ 0x0000f75c,
+ 0xfff60bd5,
+ 0xff110a89,
+ 0x057cf40e,
+ 0x03fe00af,
+ 0xf7daf099,
+ 0x0010fc91,
+ 0xf7be063d,
+ 0x00000000,
+ 0xf9c30842,
+ 0x036ffff0,
+ 0x0f670826,
+ 0xff51fc02,
+ 0x0bf2fa84,
+ 0xf57700ef,
+ 0xf42b000a,
+ 0x08a40000,
+ 0x09b6fff8,
+ 0xf03c0166,
+ 0xf99e02ee,
+ 0xfe59f65d,
+ 0xfb54fd87,
+ 0x1141ffb2,
+ 0x009dff30,
+ 0x05e30000,
+ 0xff060705,
+ 0x085408a0,
+ 0xf425fc59,
+ 0xfa1d042a,
+ 0xfc78f67a,
+ 0xf7acf60e,
+ 0x075a0766,
+ 0x05e305e3,
+ 0xf8a6f89a,
+ 0xf7acf60e,
+ 0x03880986,
+ 0xfa1d042a,
+ 0x0bdb03a7,
+ 0x085408a0,
+ 0x00faf8fb,
+ 0x05e30000,
+ 0xff06f8fb,
+ 0x0854f760,
+ 0xf42503a7,
+ 0xfa1dfbd6,
+ 0xfc780986,
+ 0xf7ac09f2,
+ 0x075af89a,
+ 0x05e3fa1d,
+ 0xf8a60766,
+ 0xf7ac09f2,
+ 0x0388f67a,
+ 0xfa1dfbd6,
+ 0x0bdbfc59,
+ 0x0854f760,
+ 0x00fa0705,
+ 0x05e30000,
+ 0xff060705,
+ 0x085408a0,
+ 0xf425fc59,
+ 0xfa1d042a,
+ 0xfc78f67a,
+ 0xf7acf60e,
+ 0x075a0766,
+ 0x05e305e3,
+ 0xf8a6f89a,
+ 0xf7acf60e,
+ 0x03880986,
+ 0xfa1d042a,
+ 0x0bdb03a7,
+ 0x085408a0,
+ 0x00faf8fb,
+ 0x05e30000,
+ 0xff06f8fb,
+ 0x0854f760,
+ 0xf42503a7,
+ 0xfa1dfbd6,
+ 0xfc780986,
+ 0xf7ac09f2,
+ 0x075af89a,
+ 0x05e3fa1d,
+ 0xf8a60766,
+ 0xf7ac09f2,
+ 0x0388f67a,
+ 0xfa1dfbd6,
+ 0x0bdbfc59,
+ 0x0854f760,
+ 0x00fa0705,
+ 0xfa58fa58,
+ 0xf8f0fe00,
+ 0x0448073d,
+ 0xfdc9fe46,
+ 0xf9910258,
+ 0x089d0407,
+ 0xfd5cf71a,
+ 0x02affde0,
+ 0x083e0496,
+ 0xff5a0740,
+ 0xff7afd97,
+ 0x00fe01f1,
+ 0x0009082e,
+ 0xfa94ff75,
+ 0xfecdf8ea,
+ 0xffb0f693,
+ 0xfd2cfa58,
+ 0x0433ff16,
+ 0xfba405dd,
+ 0xfa610341,
+ 0x06a606cb,
+ 0x0039fd2d,
+ 0x0677fa97,
+ 0x01fa05e0,
+ 0xf896003e,
+ 0x075a068b,
+ 0x012cfc3e,
+ 0xfa23f98d,
+ 0xfc7cfd43,
+ 0xff90fc0d,
+ 0x01c10982,
+ 0x00c601d6,
+ 0xfd2cfd2c,
+ 0x01d600c6,
+ 0x098201c1,
+ 0xfc0dff90,
+ 0xfd43fc7c,
+ 0xf98dfa23,
+ 0xfc3e012c,
+ 0x068b075a,
+ 0x003ef896,
+ 0x05e001fa,
+ 0xfa970677,
+ 0xfd2d0039,
+ 0x06cb06a6,
+ 0x0341fa61,
+ 0x05ddfba4,
+ 0xff160433,
+ 0xfa58fd2c,
+ 0xf693ffb0,
+ 0xf8eafecd,
+ 0xff75fa94,
+ 0x082e0009,
+ 0x01f100fe,
+ 0xfd97ff7a,
+ 0x0740ff5a,
+ 0x0496083e,
+ 0xfde002af,
+ 0xf71afd5c,
+ 0x0407089d,
+ 0x0258f991,
+ 0xfe46fdc9,
+ 0x073d0448,
+ 0xfe00f8f0,
+ 0xfd2cfd2c,
+ 0xfce00500,
+ 0xfc09fddc,
+ 0xfe680157,
+ 0x04c70571,
+ 0xfc3aff21,
+ 0xfcd70228,
+ 0x056d0277,
+ 0x0200fe00,
+ 0x0022f927,
+ 0xfe3c032b,
+ 0xfc44ff3c,
+ 0x03e9fbdb,
+ 0x04570313,
+ 0x04c9ff5c,
+ 0x000d03b8,
+ 0xfa580000,
+ 0xfbe900d2,
+ 0xf9d0fe0b,
+ 0x0125fdf9,
+ 0x042501bf,
+ 0x0328fa2b,
+ 0xffa902f0,
+ 0xfa250157,
+ 0x0200fe00,
+ 0x03740438,
+ 0xff0405fd,
+ 0x030cfe52,
+ 0x0037fb39,
+ 0xff6904c5,
+ 0x04f8fd23,
+ 0xfd31fc1b,
+ 0xfd2cfd2c,
+ 0xfc1bfd31,
+ 0xfd2304f8,
+ 0x04c5ff69,
+ 0xfb390037,
+ 0xfe52030c,
+ 0x05fdff04,
+ 0x04380374,
+ 0xfe000200,
+ 0x0157fa25,
+ 0x02f0ffa9,
+ 0xfa2b0328,
+ 0x01bf0425,
+ 0xfdf90125,
+ 0xfe0bf9d0,
+ 0x00d2fbe9,
+ 0x0000fa58,
+ 0x03b8000d,
+ 0xff5c04c9,
+ 0x03130457,
+ 0xfbdb03e9,
+ 0xff3cfc44,
+ 0x032bfe3c,
+ 0xf9270022,
+ 0xfe000200,
+ 0x0277056d,
+ 0x0228fcd7,
+ 0xff21fc3a,
+ 0x057104c7,
+ 0x0157fe68,
+ 0xfddcfc09,
+ 0x0500fce0,
+ 0xfd2cfd2c,
+ 0x0500fce0,
+ 0xfddcfc09,
+ 0x0157fe68,
+ 0x057104c7,
+ 0xff21fc3a,
+ 0x0228fcd7,
+ 0x0277056d,
+ 0xfe000200,
+ 0xf9270022,
+ 0x032bfe3c,
+ 0xff3cfc44,
+ 0xfbdb03e9,
+ 0x03130457,
+ 0xff5c04c9,
+ 0x03b8000d,
+ 0x0000fa58,
+ 0x00d2fbe9,
+ 0xfe0bf9d0,
+ 0xfdf90125,
+ 0x01bf0425,
+ 0xfa2b0328,
+ 0x02f0ffa9,
+ 0x0157fa25,
+ 0xfe000200,
+ 0x04380374,
+ 0x05fdff04,
+ 0xfe52030c,
+ 0xfb390037,
+ 0x04c5ff69,
+ 0xfd2304f8,
+ 0xfc1bfd31,
+ 0xfd2cfd2c,
+ 0xfd31fc1b,
+ 0x04f8fd23,
+ 0xff6904c5,
+ 0x0037fb39,
+ 0x030cfe52,
+ 0xff0405fd,
+ 0x03740438,
+ 0x0200fe00,
+ 0xfa250157,
+ 0xffa902f0,
+ 0x0328fa2b,
+ 0x042501bf,
+ 0x0125fdf9,
+ 0xf9d0fe0b,
+ 0xfbe900d2,
+ 0xfa580000,
+ 0x000d03b8,
+ 0x04c9ff5c,
+ 0x04570313,
+ 0x03e9fbdb,
+ 0xfc44ff3c,
+ 0xfe3c032b,
+ 0x0022f927,
+ 0x0200fe00,
+ 0x056d0277,
+ 0xfcd70228,
+ 0xfc3aff21,
+ 0x04c70571,
+ 0xfe680157,
+ 0xfc09fddc,
+ 0xfce00500,
+ 0x05a80000,
+ 0xff1006be,
+ 0x0800084a,
+ 0xf49cfc7e,
+ 0xfa580400,
+ 0xfc9cf6da,
+ 0xf800f672,
+ 0x0710071c,
+ 0x05a805a8,
+ 0xf8f0f8e4,
+ 0xf800f672,
+ 0x03640926,
+ 0xfa580400,
+ 0x0b640382,
+ 0x0800084a,
+ 0x00f0f942,
+ 0x05a80000,
+ 0xff10f942,
+ 0x0800f7b6,
+ 0xf49c0382,
+ 0xfa58fc00,
+ 0xfc9c0926,
+ 0xf800098e,
+ 0x0710f8e4,
+ 0x05a8fa58,
+ 0xf8f0071c,
+ 0xf800098e,
+ 0x0364f6da,
+ 0xfa58fc00,
+ 0x0b64fc7e,
+ 0x0800f7b6,
+ 0x00f006be,
+ 0x05a80000,
+ 0xff1006be,
+ 0x0800084a,
+ 0xf49cfc7e,
+ 0xfa580400,
+ 0xfc9cf6da,
+ 0xf800f672,
+ 0x0710071c,
+ 0x05a805a8,
+ 0xf8f0f8e4,
+ 0xf800f672,
+ 0x03640926,
+ 0xfa580400,
+ 0x0b640382,
+ 0x0800084a,
+ 0x00f0f942,
+ 0x05a80000,
+ 0xff10f942,
+ 0x0800f7b6,
+ 0xf49c0382,
+ 0xfa58fc00,
+ 0xfc9c0926,
+ 0xf800098e,
+ 0x0710f8e4,
+ 0x05a8fa58,
+ 0xf8f0071c,
+ 0xf800098e,
+ 0x0364f6da,
+ 0xfa58fc00,
+ 0x0b64fc7e,
+ 0x0800f7b6,
+ 0x00f006be,
+};
+
+const u32 noise_var_tbl_rev3[] = {
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+ 0x02110211,
+ 0x0000014d,
+};
+
+const u16 mcs_tbl_rev3[] = {
+ 0x0000,
+ 0x0008,
+ 0x000a,
+ 0x0010,
+ 0x0012,
+ 0x0019,
+ 0x001a,
+ 0x001c,
+ 0x0080,
+ 0x0088,
+ 0x008a,
+ 0x0090,
+ 0x0092,
+ 0x0099,
+ 0x009a,
+ 0x009c,
+ 0x0100,
+ 0x0108,
+ 0x010a,
+ 0x0110,
+ 0x0112,
+ 0x0119,
+ 0x011a,
+ 0x011c,
+ 0x0180,
+ 0x0188,
+ 0x018a,
+ 0x0190,
+ 0x0192,
+ 0x0199,
+ 0x019a,
+ 0x019c,
+ 0x0000,
+ 0x0098,
+ 0x00a0,
+ 0x00a8,
+ 0x009a,
+ 0x00a2,
+ 0x00aa,
+ 0x0120,
+ 0x0128,
+ 0x0128,
+ 0x0130,
+ 0x0138,
+ 0x0138,
+ 0x0140,
+ 0x0122,
+ 0x012a,
+ 0x012a,
+ 0x0132,
+ 0x013a,
+ 0x013a,
+ 0x0142,
+ 0x01a8,
+ 0x01b0,
+ 0x01b8,
+ 0x01b0,
+ 0x01b8,
+ 0x01c0,
+ 0x01c8,
+ 0x01c0,
+ 0x01c8,
+ 0x01d0,
+ 0x01d0,
+ 0x01d8,
+ 0x01aa,
+ 0x01b2,
+ 0x01ba,
+ 0x01b2,
+ 0x01ba,
+ 0x01c2,
+ 0x01ca,
+ 0x01c2,
+ 0x01ca,
+ 0x01d2,
+ 0x01d2,
+ 0x01da,
+ 0x0001,
+ 0x0002,
+ 0x0004,
+ 0x0009,
+ 0x000c,
+ 0x0011,
+ 0x0014,
+ 0x0018,
+ 0x0020,
+ 0x0021,
+ 0x0022,
+ 0x0024,
+ 0x0081,
+ 0x0082,
+ 0x0084,
+ 0x0089,
+ 0x008c,
+ 0x0091,
+ 0x0094,
+ 0x0098,
+ 0x00a0,
+ 0x00a1,
+ 0x00a2,
+ 0x00a4,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+ 0x0007,
+};
+
+const u32 tdi_tbl20_ant0_rev3[] = {
+ 0x00091226,
+ 0x000a1429,
+ 0x000b56ad,
+ 0x000c58b0,
+ 0x000d5ab3,
+ 0x000e9cb6,
+ 0x000f9eba,
+ 0x0000c13d,
+ 0x00020301,
+ 0x00030504,
+ 0x00040708,
+ 0x0005090b,
+ 0x00064b8e,
+ 0x00095291,
+ 0x000a5494,
+ 0x000b9718,
+ 0x000c9927,
+ 0x000d9b2a,
+ 0x000edd2e,
+ 0x000fdf31,
+ 0x000101b4,
+ 0x000243b7,
+ 0x000345bb,
+ 0x000447be,
+ 0x00058982,
+ 0x00068c05,
+ 0x00099309,
+ 0x000a950c,
+ 0x000bd78f,
+ 0x000cd992,
+ 0x000ddb96,
+ 0x000f1d99,
+ 0x00005fa8,
+ 0x0001422c,
+ 0x0002842f,
+ 0x00038632,
+ 0x00048835,
+ 0x0005ca38,
+ 0x0006ccbc,
+ 0x0009d3bf,
+ 0x000b1603,
+ 0x000c1806,
+ 0x000d1a0a,
+ 0x000e1c0d,
+ 0x000f5e10,
+ 0x00008093,
+ 0x00018297,
+ 0x0002c49a,
+ 0x0003c680,
+ 0x0004c880,
+ 0x00060b00,
+ 0x00070d00,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 tdi_tbl20_ant1_rev3[] = {
+ 0x00014b26,
+ 0x00028d29,
+ 0x000393ad,
+ 0x00049630,
+ 0x0005d833,
+ 0x0006da36,
+ 0x00099c3a,
+ 0x000a9e3d,
+ 0x000bc081,
+ 0x000cc284,
+ 0x000dc488,
+ 0x000f068b,
+ 0x0000488e,
+ 0x00018b91,
+ 0x0002d214,
+ 0x0003d418,
+ 0x0004d6a7,
+ 0x000618aa,
+ 0x00071aae,
+ 0x0009dcb1,
+ 0x000b1eb4,
+ 0x000c0137,
+ 0x000d033b,
+ 0x000e053e,
+ 0x000f4702,
+ 0x00008905,
+ 0x00020c09,
+ 0x0003128c,
+ 0x0004148f,
+ 0x00051712,
+ 0x00065916,
+ 0x00091b19,
+ 0x000a1d28,
+ 0x000b5f2c,
+ 0x000c41af,
+ 0x000d43b2,
+ 0x000e85b5,
+ 0x000f87b8,
+ 0x0000c9bc,
+ 0x00024cbf,
+ 0x00035303,
+ 0x00045506,
+ 0x0005978a,
+ 0x0006998d,
+ 0x00095b90,
+ 0x000a5d93,
+ 0x000b9f97,
+ 0x000c821a,
+ 0x000d8400,
+ 0x000ec600,
+ 0x000fc800,
+ 0x00010a00,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 tdi_tbl40_ant0_rev3[] = {
+ 0x0011a346,
+ 0x00136ccf,
+ 0x0014f5d9,
+ 0x001641e2,
+ 0x0017cb6b,
+ 0x00195475,
+ 0x001b2383,
+ 0x001cad0c,
+ 0x001e7616,
+ 0x0000821f,
+ 0x00020ba8,
+ 0x0003d4b2,
+ 0x00056447,
+ 0x00072dd0,
+ 0x0008b6da,
+ 0x000a02e3,
+ 0x000b8c6c,
+ 0x000d15f6,
+ 0x0011e484,
+ 0x0013ae0d,
+ 0x00153717,
+ 0x00168320,
+ 0x00180ca9,
+ 0x00199633,
+ 0x001b6548,
+ 0x001ceed1,
+ 0x001eb7db,
+ 0x0000c3e4,
+ 0x00024d6d,
+ 0x000416f7,
+ 0x0005a585,
+ 0x00076f0f,
+ 0x0008f818,
+ 0x000a4421,
+ 0x000bcdab,
+ 0x000d9734,
+ 0x00122649,
+ 0x0013efd2,
+ 0x001578dc,
+ 0x0016c4e5,
+ 0x00184e6e,
+ 0x001a17f8,
+ 0x001ba686,
+ 0x001d3010,
+ 0x001ef999,
+ 0x00010522,
+ 0x00028eac,
+ 0x00045835,
+ 0x0005e74a,
+ 0x0007b0d3,
+ 0x00093a5d,
+ 0x000a85e6,
+ 0x000c0f6f,
+ 0x000dd8f9,
+ 0x00126787,
+ 0x00143111,
+ 0x0015ba9a,
+ 0x00170623,
+ 0x00188fad,
+ 0x001a5936,
+ 0x001be84b,
+ 0x001db1d4,
+ 0x001f3b5e,
+ 0x000146e7,
+ 0x00031070,
+ 0x000499fa,
+ 0x00062888,
+ 0x0007f212,
+ 0x00097b9b,
+ 0x000ac7a4,
+ 0x000c50ae,
+ 0x000e1a37,
+ 0x0012a94c,
+ 0x001472d5,
+ 0x0015fc5f,
+ 0x00174868,
+ 0x0018d171,
+ 0x001a9afb,
+ 0x001c2989,
+ 0x001df313,
+ 0x001f7c9c,
+ 0x000188a5,
+ 0x000351af,
+ 0x0004db38,
+ 0x0006aa4d,
+ 0x000833d7,
+ 0x0009bd60,
+ 0x000b0969,
+ 0x000c9273,
+ 0x000e5bfc,
+ 0x00132a8a,
+ 0x0014b414,
+ 0x00163d9d,
+ 0x001789a6,
+ 0x001912b0,
+ 0x001adc39,
+ 0x001c6bce,
+ 0x001e34d8,
+ 0x001fbe61,
+ 0x0001ca6a,
+ 0x00039374,
+ 0x00051cfd,
+ 0x0006ec0b,
+ 0x00087515,
+ 0x0009fe9e,
+ 0x000b4aa7,
+ 0x000cd3b1,
+ 0x000e9d3a,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 tdi_tbl40_ant1_rev3[] = {
+ 0x001edb36,
+ 0x000129ca,
+ 0x0002b353,
+ 0x00047cdd,
+ 0x0005c8e6,
+ 0x000791ef,
+ 0x00091bf9,
+ 0x000aaa07,
+ 0x000c3391,
+ 0x000dfd1a,
+ 0x00120923,
+ 0x0013d22d,
+ 0x00155c37,
+ 0x0016eacb,
+ 0x00187454,
+ 0x001a3dde,
+ 0x001b89e7,
+ 0x001d12f0,
+ 0x001f1cfa,
+ 0x00016b88,
+ 0x00033492,
+ 0x0004be1b,
+ 0x00060a24,
+ 0x0007d32e,
+ 0x00095d38,
+ 0x000aec4c,
+ 0x000c7555,
+ 0x000e3edf,
+ 0x00124ae8,
+ 0x001413f1,
+ 0x0015a37b,
+ 0x00172c89,
+ 0x0018b593,
+ 0x001a419c,
+ 0x001bcb25,
+ 0x001d942f,
+ 0x001f63b9,
+ 0x0001ad4d,
+ 0x00037657,
+ 0x0004c260,
+ 0x00068be9,
+ 0x000814f3,
+ 0x0009a47c,
+ 0x000b2d8a,
+ 0x000cb694,
+ 0x000e429d,
+ 0x00128c26,
+ 0x001455b0,
+ 0x0015e4ba,
+ 0x00176e4e,
+ 0x0018f758,
+ 0x001a8361,
+ 0x001c0cea,
+ 0x001dd674,
+ 0x001fa57d,
+ 0x0001ee8b,
+ 0x0003b795,
+ 0x0005039e,
+ 0x0006cd27,
+ 0x000856b1,
+ 0x0009e5c6,
+ 0x000b6f4f,
+ 0x000cf859,
+ 0x000e8462,
+ 0x00130deb,
+ 0x00149775,
+ 0x00162603,
+ 0x0017af8c,
+ 0x00193896,
+ 0x001ac49f,
+ 0x001c4e28,
+ 0x001e17b2,
+ 0x0000a6c7,
+ 0x00023050,
+ 0x0003f9da,
+ 0x00054563,
+ 0x00070eec,
+ 0x00089876,
+ 0x000a2704,
+ 0x000bb08d,
+ 0x000d3a17,
+ 0x001185a0,
+ 0x00134f29,
+ 0x0014d8b3,
+ 0x001667c8,
+ 0x0017f151,
+ 0x00197adb,
+ 0x001b0664,
+ 0x001c8fed,
+ 0x001e5977,
+ 0x0000e805,
+ 0x0002718f,
+ 0x00043b18,
+ 0x000586a1,
+ 0x0007502b,
+ 0x0008d9b4,
+ 0x000a68c9,
+ 0x000bf252,
+ 0x000dbbdc,
+ 0x0011c7e5,
+ 0x001390ee,
+ 0x00151a78,
+ 0x0016a906,
+ 0x00183290,
+ 0x0019bc19,
+ 0x001b4822,
+ 0x001cd12c,
+ 0x001e9ab5,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 pltlut_tbl_rev3[] = {
+ 0x76540213,
+ 0x62407351,
+ 0x76543210,
+ 0x76540213,
+ 0x76540213,
+ 0x76430521,
+};
+
+const u32 chanest_tbl_rev3[] = {
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x44444444,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+ 0x10101010,
+};
+
+const u8 frame_lut_rev3[] = {
+ 0x02,
+ 0x04,
+ 0x14,
+ 0x14,
+ 0x03,
+ 0x05,
+ 0x16,
+ 0x16,
+ 0x0a,
+ 0x0c,
+ 0x1c,
+ 0x1c,
+ 0x0b,
+ 0x0d,
+ 0x1e,
+ 0x1e,
+ 0x06,
+ 0x08,
+ 0x18,
+ 0x18,
+ 0x07,
+ 0x09,
+ 0x1a,
+ 0x1a,
+ 0x0e,
+ 0x10,
+ 0x20,
+ 0x28,
+ 0x0f,
+ 0x11,
+ 0x22,
+ 0x2a,
+};
+
+const u8 est_pwr_lut_core0_rev3[] = {
+ 0x55,
+ 0x54,
+ 0x54,
+ 0x53,
+ 0x52,
+ 0x52,
+ 0x51,
+ 0x51,
+ 0x50,
+ 0x4f,
+ 0x4f,
+ 0x4e,
+ 0x4e,
+ 0x4d,
+ 0x4c,
+ 0x4c,
+ 0x4b,
+ 0x4a,
+ 0x49,
+ 0x49,
+ 0x48,
+ 0x47,
+ 0x46,
+ 0x46,
+ 0x45,
+ 0x44,
+ 0x43,
+ 0x42,
+ 0x41,
+ 0x40,
+ 0x40,
+ 0x3f,
+ 0x3e,
+ 0x3d,
+ 0x3c,
+ 0x3a,
+ 0x39,
+ 0x38,
+ 0x37,
+ 0x36,
+ 0x35,
+ 0x33,
+ 0x32,
+ 0x31,
+ 0x2f,
+ 0x2e,
+ 0x2c,
+ 0x2b,
+ 0x29,
+ 0x27,
+ 0x25,
+ 0x23,
+ 0x21,
+ 0x1f,
+ 0x1d,
+ 0x1a,
+ 0x18,
+ 0x15,
+ 0x12,
+ 0x0e,
+ 0x0b,
+ 0x07,
+ 0x02,
+ 0xfd,
+};
+
+const u8 est_pwr_lut_core1_rev3[] = {
+ 0x55,
+ 0x54,
+ 0x54,
+ 0x53,
+ 0x52,
+ 0x52,
+ 0x51,
+ 0x51,
+ 0x50,
+ 0x4f,
+ 0x4f,
+ 0x4e,
+ 0x4e,
+ 0x4d,
+ 0x4c,
+ 0x4c,
+ 0x4b,
+ 0x4a,
+ 0x49,
+ 0x49,
+ 0x48,
+ 0x47,
+ 0x46,
+ 0x46,
+ 0x45,
+ 0x44,
+ 0x43,
+ 0x42,
+ 0x41,
+ 0x40,
+ 0x40,
+ 0x3f,
+ 0x3e,
+ 0x3d,
+ 0x3c,
+ 0x3a,
+ 0x39,
+ 0x38,
+ 0x37,
+ 0x36,
+ 0x35,
+ 0x33,
+ 0x32,
+ 0x31,
+ 0x2f,
+ 0x2e,
+ 0x2c,
+ 0x2b,
+ 0x29,
+ 0x27,
+ 0x25,
+ 0x23,
+ 0x21,
+ 0x1f,
+ 0x1d,
+ 0x1a,
+ 0x18,
+ 0x15,
+ 0x12,
+ 0x0e,
+ 0x0b,
+ 0x07,
+ 0x02,
+ 0xfd,
+};
+
+const u8 adj_pwr_lut_core0_rev3[] = {
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+};
+
+const u8 adj_pwr_lut_core1_rev3[] = {
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+};
+
+const u32 gainctrl_lut_core0_rev3[] = {
+ 0x5bf70044,
+ 0x5bf70042,
+ 0x5bf70040,
+ 0x5bf7003e,
+ 0x5bf7003c,
+ 0x5bf7003b,
+ 0x5bf70039,
+ 0x5bf70037,
+ 0x5bf70036,
+ 0x5bf70034,
+ 0x5bf70033,
+ 0x5bf70031,
+ 0x5bf70030,
+ 0x5ba70044,
+ 0x5ba70042,
+ 0x5ba70040,
+ 0x5ba7003e,
+ 0x5ba7003c,
+ 0x5ba7003b,
+ 0x5ba70039,
+ 0x5ba70037,
+ 0x5ba70036,
+ 0x5ba70034,
+ 0x5ba70033,
+ 0x5b770044,
+ 0x5b770042,
+ 0x5b770040,
+ 0x5b77003e,
+ 0x5b77003c,
+ 0x5b77003b,
+ 0x5b770039,
+ 0x5b770037,
+ 0x5b770036,
+ 0x5b770034,
+ 0x5b770033,
+ 0x5b770031,
+ 0x5b770030,
+ 0x5b77002f,
+ 0x5b77002d,
+ 0x5b77002c,
+ 0x5b470044,
+ 0x5b470042,
+ 0x5b470040,
+ 0x5b47003e,
+ 0x5b47003c,
+ 0x5b47003b,
+ 0x5b470039,
+ 0x5b470037,
+ 0x5b470036,
+ 0x5b470034,
+ 0x5b470033,
+ 0x5b470031,
+ 0x5b470030,
+ 0x5b47002f,
+ 0x5b47002d,
+ 0x5b47002c,
+ 0x5b47002b,
+ 0x5b47002a,
+ 0x5b270044,
+ 0x5b270042,
+ 0x5b270040,
+ 0x5b27003e,
+ 0x5b27003c,
+ 0x5b27003b,
+ 0x5b270039,
+ 0x5b270037,
+ 0x5b270036,
+ 0x5b270034,
+ 0x5b270033,
+ 0x5b270031,
+ 0x5b270030,
+ 0x5b27002f,
+ 0x5b170044,
+ 0x5b170042,
+ 0x5b170040,
+ 0x5b17003e,
+ 0x5b17003c,
+ 0x5b17003b,
+ 0x5b170039,
+ 0x5b170037,
+ 0x5b170036,
+ 0x5b170034,
+ 0x5b170033,
+ 0x5b170031,
+ 0x5b170030,
+ 0x5b17002f,
+ 0x5b17002d,
+ 0x5b17002c,
+ 0x5b17002b,
+ 0x5b17002a,
+ 0x5b170028,
+ 0x5b170027,
+ 0x5b170026,
+ 0x5b170025,
+ 0x5b170024,
+ 0x5b170023,
+ 0x5b070044,
+ 0x5b070042,
+ 0x5b070040,
+ 0x5b07003e,
+ 0x5b07003c,
+ 0x5b07003b,
+ 0x5b070039,
+ 0x5b070037,
+ 0x5b070036,
+ 0x5b070034,
+ 0x5b070033,
+ 0x5b070031,
+ 0x5b070030,
+ 0x5b07002f,
+ 0x5b07002d,
+ 0x5b07002c,
+ 0x5b07002b,
+ 0x5b07002a,
+ 0x5b070028,
+ 0x5b070027,
+ 0x5b070026,
+ 0x5b070025,
+ 0x5b070024,
+ 0x5b070023,
+ 0x5b070022,
+ 0x5b070021,
+ 0x5b070020,
+ 0x5b07001f,
+ 0x5b07001e,
+ 0x5b07001d,
+ 0x5b07001d,
+ 0x5b07001c,
+};
+
+const u32 gainctrl_lut_core1_rev3[] = {
+ 0x5bf70044,
+ 0x5bf70042,
+ 0x5bf70040,
+ 0x5bf7003e,
+ 0x5bf7003c,
+ 0x5bf7003b,
+ 0x5bf70039,
+ 0x5bf70037,
+ 0x5bf70036,
+ 0x5bf70034,
+ 0x5bf70033,
+ 0x5bf70031,
+ 0x5bf70030,
+ 0x5ba70044,
+ 0x5ba70042,
+ 0x5ba70040,
+ 0x5ba7003e,
+ 0x5ba7003c,
+ 0x5ba7003b,
+ 0x5ba70039,
+ 0x5ba70037,
+ 0x5ba70036,
+ 0x5ba70034,
+ 0x5ba70033,
+ 0x5b770044,
+ 0x5b770042,
+ 0x5b770040,
+ 0x5b77003e,
+ 0x5b77003c,
+ 0x5b77003b,
+ 0x5b770039,
+ 0x5b770037,
+ 0x5b770036,
+ 0x5b770034,
+ 0x5b770033,
+ 0x5b770031,
+ 0x5b770030,
+ 0x5b77002f,
+ 0x5b77002d,
+ 0x5b77002c,
+ 0x5b470044,
+ 0x5b470042,
+ 0x5b470040,
+ 0x5b47003e,
+ 0x5b47003c,
+ 0x5b47003b,
+ 0x5b470039,
+ 0x5b470037,
+ 0x5b470036,
+ 0x5b470034,
+ 0x5b470033,
+ 0x5b470031,
+ 0x5b470030,
+ 0x5b47002f,
+ 0x5b47002d,
+ 0x5b47002c,
+ 0x5b47002b,
+ 0x5b47002a,
+ 0x5b270044,
+ 0x5b270042,
+ 0x5b270040,
+ 0x5b27003e,
+ 0x5b27003c,
+ 0x5b27003b,
+ 0x5b270039,
+ 0x5b270037,
+ 0x5b270036,
+ 0x5b270034,
+ 0x5b270033,
+ 0x5b270031,
+ 0x5b270030,
+ 0x5b27002f,
+ 0x5b170044,
+ 0x5b170042,
+ 0x5b170040,
+ 0x5b17003e,
+ 0x5b17003c,
+ 0x5b17003b,
+ 0x5b170039,
+ 0x5b170037,
+ 0x5b170036,
+ 0x5b170034,
+ 0x5b170033,
+ 0x5b170031,
+ 0x5b170030,
+ 0x5b17002f,
+ 0x5b17002d,
+ 0x5b17002c,
+ 0x5b17002b,
+ 0x5b17002a,
+ 0x5b170028,
+ 0x5b170027,
+ 0x5b170026,
+ 0x5b170025,
+ 0x5b170024,
+ 0x5b170023,
+ 0x5b070044,
+ 0x5b070042,
+ 0x5b070040,
+ 0x5b07003e,
+ 0x5b07003c,
+ 0x5b07003b,
+ 0x5b070039,
+ 0x5b070037,
+ 0x5b070036,
+ 0x5b070034,
+ 0x5b070033,
+ 0x5b070031,
+ 0x5b070030,
+ 0x5b07002f,
+ 0x5b07002d,
+ 0x5b07002c,
+ 0x5b07002b,
+ 0x5b07002a,
+ 0x5b070028,
+ 0x5b070027,
+ 0x5b070026,
+ 0x5b070025,
+ 0x5b070024,
+ 0x5b070023,
+ 0x5b070022,
+ 0x5b070021,
+ 0x5b070020,
+ 0x5b07001f,
+ 0x5b07001e,
+ 0x5b07001d,
+ 0x5b07001d,
+ 0x5b07001c,
+};
+
+const u32 iq_lut_core0_rev3[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 iq_lut_core1_rev3[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u16 loft_lut_core0_rev3[] = {
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+};
+
+const u16 loft_lut_core1_rev3[] = {
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+ 0x0000,
+};
+
+const u16 papd_comp_rfpwr_tbl_core0_rev3[] = {
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+};
+
+const u16 papd_comp_rfpwr_tbl_core1_rev3[] = {
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x0036,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x002a,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x001e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x000e,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01fc,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01ee,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+ 0x01d6,
+};
+
+const u32 papd_comp_epsilon_tbl_core0_rev3[] = {
+ 0x00000000,
+ 0x00001fa0,
+ 0x00019f78,
+ 0x0001df7e,
+ 0x03fa9f86,
+ 0x03fd1f90,
+ 0x03fe5f8a,
+ 0x03fb1f94,
+ 0x03fd9fa0,
+ 0x00009f98,
+ 0x03fd1fac,
+ 0x03ff9fa2,
+ 0x03fe9fae,
+ 0x00001fae,
+ 0x03fddfb4,
+ 0x03ff1fb8,
+ 0x03ff9fbc,
+ 0x03ffdfbe,
+ 0x03fe9fc2,
+ 0x03fedfc6,
+ 0x03fedfc6,
+ 0x03ff9fc8,
+ 0x03ff5fc6,
+ 0x03fedfc2,
+ 0x03ff9fc0,
+ 0x03ff5fac,
+ 0x03ff5fac,
+ 0x03ff9fa2,
+ 0x03ff9fa6,
+ 0x03ff9faa,
+ 0x03ff5fb0,
+ 0x03ff5fb4,
+ 0x03ff1fca,
+ 0x03ff5fce,
+ 0x03fcdfdc,
+ 0x03fb4006,
+ 0x00000030,
+ 0x03ff808a,
+ 0x03ff80da,
+ 0x0000016c,
+ 0x03ff8318,
+ 0x03ff063a,
+ 0x03fd8bd6,
+ 0x00014ffe,
+ 0x00034ffe,
+ 0x00034ffe,
+ 0x0003cffe,
+ 0x00040ffe,
+ 0x00040ffe,
+ 0x0003cffe,
+ 0x0003cffe,
+ 0x00020ffe,
+ 0x03fe0ffe,
+ 0x03fdcffe,
+ 0x03f94ffe,
+ 0x03f54ffe,
+ 0x03f44ffe,
+ 0x03ef8ffe,
+ 0x03ee0ffe,
+ 0x03ebcffe,
+ 0x03e8cffe,
+ 0x03e74ffe,
+ 0x03e4cffe,
+ 0x03e38ffe,
+};
+
+const u32 papd_cal_scalars_tbl_core0_rev3[] = {
+ 0x05af005a,
+ 0x0571005e,
+ 0x05040066,
+ 0x04bd006c,
+ 0x047d0072,
+ 0x04430078,
+ 0x03f70081,
+ 0x03cb0087,
+ 0x03870091,
+ 0x035e0098,
+ 0x032e00a1,
+ 0x030300aa,
+ 0x02d800b4,
+ 0x02ae00bf,
+ 0x028900ca,
+ 0x026400d6,
+ 0x024100e3,
+ 0x022200f0,
+ 0x020200ff,
+ 0x01e5010e,
+ 0x01ca011e,
+ 0x01b0012f,
+ 0x01990140,
+ 0x01830153,
+ 0x016c0168,
+ 0x0158017d,
+ 0x01450193,
+ 0x013301ab,
+ 0x012101c5,
+ 0x011101e0,
+ 0x010201fc,
+ 0x00f4021a,
+ 0x00e6011d,
+ 0x00d9012e,
+ 0x00cd0140,
+ 0x00c20153,
+ 0x00b70167,
+ 0x00ac017c,
+ 0x00a30193,
+ 0x009a01ab,
+ 0x009101c4,
+ 0x008901df,
+ 0x008101fb,
+ 0x007a0219,
+ 0x00730239,
+ 0x006d025b,
+ 0x0067027e,
+ 0x006102a4,
+ 0x005c02cc,
+ 0x005602f6,
+ 0x00520323,
+ 0x004d0353,
+ 0x00490385,
+ 0x004503bb,
+ 0x004103f3,
+ 0x003d042f,
+ 0x003a046f,
+ 0x003704b2,
+ 0x003404f9,
+ 0x00310545,
+ 0x002e0596,
+ 0x002b05f5,
+ 0x00290640,
+ 0x002606a4,
+};
+
+const u32 papd_comp_epsilon_tbl_core1_rev3[] = {
+ 0x00000000,
+ 0x00001fa0,
+ 0x00019f78,
+ 0x0001df7e,
+ 0x03fa9f86,
+ 0x03fd1f90,
+ 0x03fe5f8a,
+ 0x03fb1f94,
+ 0x03fd9fa0,
+ 0x00009f98,
+ 0x03fd1fac,
+ 0x03ff9fa2,
+ 0x03fe9fae,
+ 0x00001fae,
+ 0x03fddfb4,
+ 0x03ff1fb8,
+ 0x03ff9fbc,
+ 0x03ffdfbe,
+ 0x03fe9fc2,
+ 0x03fedfc6,
+ 0x03fedfc6,
+ 0x03ff9fc8,
+ 0x03ff5fc6,
+ 0x03fedfc2,
+ 0x03ff9fc0,
+ 0x03ff5fac,
+ 0x03ff5fac,
+ 0x03ff9fa2,
+ 0x03ff9fa6,
+ 0x03ff9faa,
+ 0x03ff5fb0,
+ 0x03ff5fb4,
+ 0x03ff1fca,
+ 0x03ff5fce,
+ 0x03fcdfdc,
+ 0x03fb4006,
+ 0x00000030,
+ 0x03ff808a,
+ 0x03ff80da,
+ 0x0000016c,
+ 0x03ff8318,
+ 0x03ff063a,
+ 0x03fd8bd6,
+ 0x00014ffe,
+ 0x00034ffe,
+ 0x00034ffe,
+ 0x0003cffe,
+ 0x00040ffe,
+ 0x00040ffe,
+ 0x0003cffe,
+ 0x0003cffe,
+ 0x00020ffe,
+ 0x03fe0ffe,
+ 0x03fdcffe,
+ 0x03f94ffe,
+ 0x03f54ffe,
+ 0x03f44ffe,
+ 0x03ef8ffe,
+ 0x03ee0ffe,
+ 0x03ebcffe,
+ 0x03e8cffe,
+ 0x03e74ffe,
+ 0x03e4cffe,
+ 0x03e38ffe,
+};
+
+const u32 papd_cal_scalars_tbl_core1_rev3[] = {
+ 0x05af005a,
+ 0x0571005e,
+ 0x05040066,
+ 0x04bd006c,
+ 0x047d0072,
+ 0x04430078,
+ 0x03f70081,
+ 0x03cb0087,
+ 0x03870091,
+ 0x035e0098,
+ 0x032e00a1,
+ 0x030300aa,
+ 0x02d800b4,
+ 0x02ae00bf,
+ 0x028900ca,
+ 0x026400d6,
+ 0x024100e3,
+ 0x022200f0,
+ 0x020200ff,
+ 0x01e5010e,
+ 0x01ca011e,
+ 0x01b0012f,
+ 0x01990140,
+ 0x01830153,
+ 0x016c0168,
+ 0x0158017d,
+ 0x01450193,
+ 0x013301ab,
+ 0x012101c5,
+ 0x011101e0,
+ 0x010201fc,
+ 0x00f4021a,
+ 0x00e6011d,
+ 0x00d9012e,
+ 0x00cd0140,
+ 0x00c20153,
+ 0x00b70167,
+ 0x00ac017c,
+ 0x00a30193,
+ 0x009a01ab,
+ 0x009101c4,
+ 0x008901df,
+ 0x008101fb,
+ 0x007a0219,
+ 0x00730239,
+ 0x006d025b,
+ 0x0067027e,
+ 0x006102a4,
+ 0x005c02cc,
+ 0x005602f6,
+ 0x00520323,
+ 0x004d0353,
+ 0x00490385,
+ 0x004503bb,
+ 0x004103f3,
+ 0x003d042f,
+ 0x003a046f,
+ 0x003704b2,
+ 0x003404f9,
+ 0x00310545,
+ 0x002e0596,
+ 0x002b05f5,
+ 0x00290640,
+ 0x002606a4,
+};
+
+const mimophytbl_info_t mimophytbl_info_rev3_volatile[] = {
+ {&ant_swctrl_tbl_rev3,
+ sizeof(ant_swctrl_tbl_rev3) / sizeof(ant_swctrl_tbl_rev3[0]), 9, 0, 16}
+ ,
+};
+
+const mimophytbl_info_t mimophytbl_info_rev3_volatile1[] = {
+ {&ant_swctrl_tbl_rev3_1,
+ sizeof(ant_swctrl_tbl_rev3_1) / sizeof(ant_swctrl_tbl_rev3_1[0]), 9, 0,
+ 16}
+ ,
+};
+
+const mimophytbl_info_t mimophytbl_info_rev3_volatile2[] = {
+ {&ant_swctrl_tbl_rev3_2,
+ sizeof(ant_swctrl_tbl_rev3_2) / sizeof(ant_swctrl_tbl_rev3_2[0]), 9, 0,
+ 16}
+ ,
+};
+
+const mimophytbl_info_t mimophytbl_info_rev3_volatile3[] = {
+ {&ant_swctrl_tbl_rev3_3,
+ sizeof(ant_swctrl_tbl_rev3_3) / sizeof(ant_swctrl_tbl_rev3_3[0]), 9, 0,
+ 16}
+ ,
+};
+
+const mimophytbl_info_t mimophytbl_info_rev3[] = {
+ {&frame_struct_rev3,
+ sizeof(frame_struct_rev3) / sizeof(frame_struct_rev3[0]), 10, 0, 32}
+ ,
+ {&pilot_tbl_rev3, sizeof(pilot_tbl_rev3) / sizeof(pilot_tbl_rev3[0]),
+ 11, 0, 16}
+ ,
+ {&tmap_tbl_rev3, sizeof(tmap_tbl_rev3) / sizeof(tmap_tbl_rev3[0]), 12,
+ 0, 32}
+ ,
+ {&intlv_tbl_rev3, sizeof(intlv_tbl_rev3) / sizeof(intlv_tbl_rev3[0]),
+ 13, 0, 32}
+ ,
+ {&tdtrn_tbl_rev3, sizeof(tdtrn_tbl_rev3) / sizeof(tdtrn_tbl_rev3[0]),
+ 14, 0, 32}
+ ,
+ {&noise_var_tbl_rev3,
+ sizeof(noise_var_tbl_rev3) / sizeof(noise_var_tbl_rev3[0]), 16, 0, 32}
+ ,
+ {&mcs_tbl_rev3, sizeof(mcs_tbl_rev3) / sizeof(mcs_tbl_rev3[0]), 18, 0,
+ 16}
+ ,
+ {&tdi_tbl20_ant0_rev3,
+ sizeof(tdi_tbl20_ant0_rev3) / sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
+ 32}
+ ,
+ {&tdi_tbl20_ant1_rev3,
+ sizeof(tdi_tbl20_ant1_rev3) / sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
+ 32}
+ ,
+ {&tdi_tbl40_ant0_rev3,
+ sizeof(tdi_tbl40_ant0_rev3) / sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
+ 32}
+ ,
+ {&tdi_tbl40_ant1_rev3,
+ sizeof(tdi_tbl40_ant1_rev3) / sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
+ 32}
+ ,
+ {&pltlut_tbl_rev3, sizeof(pltlut_tbl_rev3) / sizeof(pltlut_tbl_rev3[0]),
+ 20, 0, 32}
+ ,
+ {&chanest_tbl_rev3,
+ sizeof(chanest_tbl_rev3) / sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
+ ,
+ {&frame_lut_rev3, sizeof(frame_lut_rev3) / sizeof(frame_lut_rev3[0]),
+ 24, 0, 8}
+ ,
+ {&est_pwr_lut_core0_rev3,
+ sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
+ 0, 8}
+ ,
+ {&est_pwr_lut_core1_rev3,
+ sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
+ 0, 8}
+ ,
+ {&adj_pwr_lut_core0_rev3,
+ sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
+ 64, 8}
+ ,
+ {&adj_pwr_lut_core1_rev3,
+ sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
+ 64, 8}
+ ,
+ {&gainctrl_lut_core0_rev3,
+ sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
+ 26, 192, 32}
+ ,
+ {&gainctrl_lut_core1_rev3,
+ sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
+ 27, 192, 32}
+ ,
+ {&iq_lut_core0_rev3,
+ sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
+ ,
+ {&iq_lut_core1_rev3,
+ sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
+ ,
+ {&loft_lut_core0_rev3,
+ sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
+ 16}
+ ,
+ {&loft_lut_core1_rev3,
+ sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
+ 16}
+};
+
+const u32 mimophytbl_info_sz_rev3 =
+ sizeof(mimophytbl_info_rev3) / sizeof(mimophytbl_info_rev3[0]);
+const u32 mimophytbl_info_sz_rev3_volatile =
+ sizeof(mimophytbl_info_rev3_volatile) /
+ sizeof(mimophytbl_info_rev3_volatile[0]);
+const u32 mimophytbl_info_sz_rev3_volatile1 =
+ sizeof(mimophytbl_info_rev3_volatile1) /
+ sizeof(mimophytbl_info_rev3_volatile1[0]);
+const u32 mimophytbl_info_sz_rev3_volatile2 =
+ sizeof(mimophytbl_info_rev3_volatile2) /
+ sizeof(mimophytbl_info_rev3_volatile2[0]);
+const u32 mimophytbl_info_sz_rev3_volatile3 =
+ sizeof(mimophytbl_info_rev3_volatile3) /
+ sizeof(mimophytbl_info_rev3_volatile3[0]);
+
+const u32 tmap_tbl_rev7[] = {
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x000aa888,
+ 0x88880000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa2222220,
+ 0x22222222,
+ 0x22c22222,
+ 0x00000222,
+ 0x22000000,
+ 0x2222a222,
+ 0x22222222,
+ 0x222222a2,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00011111,
+ 0x11110000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0xa8aa88a0,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x00088aaa,
+ 0xaaaa0000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xaaa8aaa0,
+ 0x8aaa8aaa,
+ 0xaa8a8a8a,
+ 0x000aaa88,
+ 0x8aaa0000,
+ 0xaaa8a888,
+ 0x8aa88a8a,
+ 0x8a88a888,
+ 0x08080a00,
+ 0x0a08080a,
+ 0x080a0a08,
+ 0x00080808,
+ 0x080a0000,
+ 0x080a0808,
+ 0x080a0808,
+ 0x0a0a0a08,
+ 0xa0a0a0a0,
+ 0x80a0a080,
+ 0x8080a0a0,
+ 0x00008080,
+ 0x80a00000,
+ 0x80a080a0,
+ 0xa080a0a0,
+ 0x8080a0a0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x99999000,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb90,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00aaa888,
+ 0x22000000,
+ 0x2222b222,
+ 0x22222222,
+ 0x222222b2,
+ 0xb2222220,
+ 0x22222222,
+ 0x22d22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x33000000,
+ 0x3333b333,
+ 0x33333333,
+ 0x333333b3,
+ 0xb3333330,
+ 0x33333333,
+ 0x33d33333,
+ 0x00000333,
+ 0x22000000,
+ 0x2222a222,
+ 0x22222222,
+ 0x222222a2,
+ 0xa2222220,
+ 0x22222222,
+ 0x22c22222,
+ 0x00000222,
+ 0x99b99b00,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb99,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x08aaa888,
+ 0x22222200,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0x22222222,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x11111111,
+ 0xf1111111,
+ 0x11111111,
+ 0x11f11111,
+ 0x01111111,
+ 0xbb9bb900,
+ 0xb9b9bb99,
+ 0xb99bbbbb,
+ 0xbbbb9b9b,
+ 0xb9bb99bb,
+ 0xb99999b9,
+ 0xb9b9b99b,
+ 0x00000bbb,
+ 0xaa000000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xa8aa88aa,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x0a888aaa,
+ 0xaa000000,
+ 0xa8a8aa88,
+ 0xa88aaaaa,
+ 0xaaaa8a8a,
+ 0xa8aa88a0,
+ 0xa88888a8,
+ 0xa8a8a88a,
+ 0x00000aaa,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0xbbbbbb00,
+ 0x999bbbbb,
+ 0x9bb99b9b,
+ 0xb9b9b9bb,
+ 0xb9b99bbb,
+ 0xb9b9b9bb,
+ 0xb9bb9b99,
+ 0x00000999,
+ 0x8a000000,
+ 0xaa88a888,
+ 0xa88888aa,
+ 0xa88a8a88,
+ 0xa88aa88a,
+ 0x88a8aaaa,
+ 0xa8aa8aaa,
+ 0x0888a88a,
+ 0x0b0b0b00,
+ 0x090b0b0b,
+ 0x0b090b0b,
+ 0x0909090b,
+ 0x09090b0b,
+ 0x09090b0b,
+ 0x09090b09,
+ 0x00000909,
+ 0x0a000000,
+ 0x0a080808,
+ 0x080a080a,
+ 0x080a0a08,
+ 0x080a080a,
+ 0x0808080a,
+ 0x0a0a0a08,
+ 0x0808080a,
+ 0xb0b0b000,
+ 0x9090b0b0,
+ 0x90b09090,
+ 0xb0b0b090,
+ 0xb0b090b0,
+ 0x90b0b0b0,
+ 0xb0b09090,
+ 0x00000090,
+ 0x80000000,
+ 0xa080a080,
+ 0xa08080a0,
+ 0xa0808080,
+ 0xa080a080,
+ 0x80a0a0a0,
+ 0xa0a080a0,
+ 0x00a0a0a0,
+ 0x22000000,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0xf2222220,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x11000000,
+ 0x1111f111,
+ 0x11111111,
+ 0x111111f1,
+ 0xf1111110,
+ 0x11111111,
+ 0x11f11111,
+ 0x00000111,
+ 0x33000000,
+ 0x3333f333,
+ 0x33333333,
+ 0x333333f3,
+ 0xf3333330,
+ 0x33333333,
+ 0x33f33333,
+ 0x00000333,
+ 0x22000000,
+ 0x2222f222,
+ 0x22222222,
+ 0x222222f2,
+ 0xf2222220,
+ 0x22222222,
+ 0x22f22222,
+ 0x00000222,
+ 0x99000000,
+ 0x9b9b99bb,
+ 0x9bb99999,
+ 0x9999b9b9,
+ 0x9b99bb90,
+ 0x9bbbbb9b,
+ 0x9b9b9bb9,
+ 0x00000999,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88888000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00aaa888,
+ 0x88a88a00,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x000aa888,
+ 0x88880000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa88,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x08aaa888,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x11000000,
+ 0x1111a111,
+ 0x11111111,
+ 0x111111a1,
+ 0xa1111110,
+ 0x11111111,
+ 0x11c11111,
+ 0x00000111,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x88000000,
+ 0x8a8a88aa,
+ 0x8aa88888,
+ 0x8888a8a8,
+ 0x8a88aa80,
+ 0x8aaaaa8a,
+ 0x8a8a8aa8,
+ 0x00000888,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+
+const u32 noise_var_tbl_rev7[] = {
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+ 0x020c020c,
+ 0x0000014d,
+};
+
+const u32 papd_comp_epsilon_tbl_core0_rev7[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00016023,
+ 0x00006028,
+ 0x00034036,
+ 0x0003402e,
+ 0x0007203c,
+ 0x0006e037,
+ 0x00070030,
+ 0x0009401f,
+ 0x0009a00f,
+ 0x000b600d,
+ 0x000c8007,
+ 0x000ce007,
+ 0x00101fff,
+ 0x00121ff9,
+ 0x0012e004,
+ 0x0014dffc,
+ 0x0016dff6,
+ 0x0018dfe9,
+ 0x001b3fe5,
+ 0x001c5fd0,
+ 0x001ddfc2,
+ 0x001f1fb6,
+ 0x00207fa4,
+ 0x00219f8f,
+ 0x0022ff7d,
+ 0x00247f6c,
+ 0x0024df5b,
+ 0x00267f4b,
+ 0x0027df3b,
+ 0x0029bf3b,
+ 0x002b5f2f,
+ 0x002d3f2e,
+ 0x002f5f2a,
+ 0x002fff15,
+ 0x00315f0b,
+ 0x0032defa,
+ 0x0033beeb,
+ 0x0034fed9,
+ 0x00353ec5,
+ 0x00361eb0,
+ 0x00363e9b,
+ 0x0036be87,
+ 0x0036be70,
+ 0x0038fe67,
+ 0x0044beb2,
+ 0x00513ef3,
+ 0x00595f11,
+ 0x00669f3d,
+ 0x0078dfdf,
+ 0x00a143aa,
+ 0x01642fff,
+ 0x0162afff,
+ 0x01620fff,
+ 0x0160cfff,
+ 0x015f0fff,
+ 0x015dafff,
+ 0x015bcfff,
+ 0x015bcfff,
+ 0x015b4fff,
+ 0x015acfff,
+ 0x01590fff,
+ 0x0156cfff,
+};
+
+const u32 papd_cal_scalars_tbl_core0_rev7[] = {
+ 0x0b5e002d,
+ 0x0ae2002f,
+ 0x0a3b0032,
+ 0x09a70035,
+ 0x09220038,
+ 0x08ab003b,
+ 0x081f003f,
+ 0x07a20043,
+ 0x07340047,
+ 0x06d2004b,
+ 0x067a004f,
+ 0x06170054,
+ 0x05bf0059,
+ 0x0571005e,
+ 0x051e0064,
+ 0x04d3006a,
+ 0x04910070,
+ 0x044c0077,
+ 0x040f007e,
+ 0x03d90085,
+ 0x03a1008d,
+ 0x036f0095,
+ 0x033d009e,
+ 0x030b00a8,
+ 0x02e000b2,
+ 0x02b900bc,
+ 0x029200c7,
+ 0x026d00d3,
+ 0x024900e0,
+ 0x022900ed,
+ 0x020a00fb,
+ 0x01ec010a,
+ 0x01d20119,
+ 0x01b7012a,
+ 0x019e013c,
+ 0x0188014e,
+ 0x01720162,
+ 0x015d0177,
+ 0x0149018e,
+ 0x013701a5,
+ 0x012601be,
+ 0x011501d8,
+ 0x010601f4,
+ 0x00f70212,
+ 0x00e90231,
+ 0x00dc0253,
+ 0x00d00276,
+ 0x00c4029b,
+ 0x00b902c3,
+ 0x00af02ed,
+ 0x00a50319,
+ 0x009c0348,
+ 0x0093037a,
+ 0x008b03af,
+ 0x008303e6,
+ 0x007c0422,
+ 0x00750460,
+ 0x006e04a3,
+ 0x006804e9,
+ 0x00620533,
+ 0x005d0582,
+ 0x005805d6,
+ 0x0053062e,
+ 0x004e068c,
+};
+
+const u32 papd_comp_epsilon_tbl_core1_rev7[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00016023,
+ 0x00006028,
+ 0x00034036,
+ 0x0003402e,
+ 0x0007203c,
+ 0x0006e037,
+ 0x00070030,
+ 0x0009401f,
+ 0x0009a00f,
+ 0x000b600d,
+ 0x000c8007,
+ 0x000ce007,
+ 0x00101fff,
+ 0x00121ff9,
+ 0x0012e004,
+ 0x0014dffc,
+ 0x0016dff6,
+ 0x0018dfe9,
+ 0x001b3fe5,
+ 0x001c5fd0,
+ 0x001ddfc2,
+ 0x001f1fb6,
+ 0x00207fa4,
+ 0x00219f8f,
+ 0x0022ff7d,
+ 0x00247f6c,
+ 0x0024df5b,
+ 0x00267f4b,
+ 0x0027df3b,
+ 0x0029bf3b,
+ 0x002b5f2f,
+ 0x002d3f2e,
+ 0x002f5f2a,
+ 0x002fff15,
+ 0x00315f0b,
+ 0x0032defa,
+ 0x0033beeb,
+ 0x0034fed9,
+ 0x00353ec5,
+ 0x00361eb0,
+ 0x00363e9b,
+ 0x0036be87,
+ 0x0036be70,
+ 0x0038fe67,
+ 0x0044beb2,
+ 0x00513ef3,
+ 0x00595f11,
+ 0x00669f3d,
+ 0x0078dfdf,
+ 0x00a143aa,
+ 0x01642fff,
+ 0x0162afff,
+ 0x01620fff,
+ 0x0160cfff,
+ 0x015f0fff,
+ 0x015dafff,
+ 0x015bcfff,
+ 0x015bcfff,
+ 0x015b4fff,
+ 0x015acfff,
+ 0x01590fff,
+ 0x0156cfff,
+};
+
+const u32 papd_cal_scalars_tbl_core1_rev7[] = {
+ 0x0b5e002d,
+ 0x0ae2002f,
+ 0x0a3b0032,
+ 0x09a70035,
+ 0x09220038,
+ 0x08ab003b,
+ 0x081f003f,
+ 0x07a20043,
+ 0x07340047,
+ 0x06d2004b,
+ 0x067a004f,
+ 0x06170054,
+ 0x05bf0059,
+ 0x0571005e,
+ 0x051e0064,
+ 0x04d3006a,
+ 0x04910070,
+ 0x044c0077,
+ 0x040f007e,
+ 0x03d90085,
+ 0x03a1008d,
+ 0x036f0095,
+ 0x033d009e,
+ 0x030b00a8,
+ 0x02e000b2,
+ 0x02b900bc,
+ 0x029200c7,
+ 0x026d00d3,
+ 0x024900e0,
+ 0x022900ed,
+ 0x020a00fb,
+ 0x01ec010a,
+ 0x01d20119,
+ 0x01b7012a,
+ 0x019e013c,
+ 0x0188014e,
+ 0x01720162,
+ 0x015d0177,
+ 0x0149018e,
+ 0x013701a5,
+ 0x012601be,
+ 0x011501d8,
+ 0x010601f4,
+ 0x00f70212,
+ 0x00e90231,
+ 0x00dc0253,
+ 0x00d00276,
+ 0x00c4029b,
+ 0x00b902c3,
+ 0x00af02ed,
+ 0x00a50319,
+ 0x009c0348,
+ 0x0093037a,
+ 0x008b03af,
+ 0x008303e6,
+ 0x007c0422,
+ 0x00750460,
+ 0x006e04a3,
+ 0x006804e9,
+ 0x00620533,
+ 0x005d0582,
+ 0x005805d6,
+ 0x0053062e,
+ 0x004e068c,
+};
+
+const mimophytbl_info_t mimophytbl_info_rev7[] = {
+ {&frame_struct_rev3,
+ sizeof(frame_struct_rev3) / sizeof(frame_struct_rev3[0]), 10, 0, 32}
+ ,
+ {&pilot_tbl_rev3, sizeof(pilot_tbl_rev3) / sizeof(pilot_tbl_rev3[0]),
+ 11, 0, 16}
+ ,
+ {&tmap_tbl_rev7, sizeof(tmap_tbl_rev7) / sizeof(tmap_tbl_rev7[0]), 12,
+ 0, 32}
+ ,
+ {&intlv_tbl_rev3, sizeof(intlv_tbl_rev3) / sizeof(intlv_tbl_rev3[0]),
+ 13, 0, 32}
+ ,
+ {&tdtrn_tbl_rev3, sizeof(tdtrn_tbl_rev3) / sizeof(tdtrn_tbl_rev3[0]),
+ 14, 0, 32}
+ ,
+ {&noise_var_tbl_rev7,
+ sizeof(noise_var_tbl_rev7) / sizeof(noise_var_tbl_rev7[0]), 16, 0, 32}
+ ,
+ {&mcs_tbl_rev3, sizeof(mcs_tbl_rev3) / sizeof(mcs_tbl_rev3[0]), 18, 0,
+ 16}
+ ,
+ {&tdi_tbl20_ant0_rev3,
+ sizeof(tdi_tbl20_ant0_rev3) / sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
+ 32}
+ ,
+ {&tdi_tbl20_ant1_rev3,
+ sizeof(tdi_tbl20_ant1_rev3) / sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
+ 32}
+ ,
+ {&tdi_tbl40_ant0_rev3,
+ sizeof(tdi_tbl40_ant0_rev3) / sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
+ 32}
+ ,
+ {&tdi_tbl40_ant1_rev3,
+ sizeof(tdi_tbl40_ant1_rev3) / sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
+ 32}
+ ,
+ {&pltlut_tbl_rev3, sizeof(pltlut_tbl_rev3) / sizeof(pltlut_tbl_rev3[0]),
+ 20, 0, 32}
+ ,
+ {&chanest_tbl_rev3,
+ sizeof(chanest_tbl_rev3) / sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
+ ,
+ {&frame_lut_rev3, sizeof(frame_lut_rev3) / sizeof(frame_lut_rev3[0]),
+ 24, 0, 8}
+ ,
+ {&est_pwr_lut_core0_rev3,
+ sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
+ 0, 8}
+ ,
+ {&est_pwr_lut_core1_rev3,
+ sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
+ 0, 8}
+ ,
+ {&adj_pwr_lut_core0_rev3,
+ sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
+ 64, 8}
+ ,
+ {&adj_pwr_lut_core1_rev3,
+ sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
+ 64, 8}
+ ,
+ {&gainctrl_lut_core0_rev3,
+ sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
+ 26, 192, 32}
+ ,
+ {&gainctrl_lut_core1_rev3,
+ sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
+ 27, 192, 32}
+ ,
+ {&iq_lut_core0_rev3,
+ sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
+ ,
+ {&iq_lut_core1_rev3,
+ sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
+ ,
+ {&loft_lut_core0_rev3,
+ sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
+ 16}
+ ,
+ {&loft_lut_core1_rev3,
+ sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
+ 16}
+ ,
+ {&papd_comp_rfpwr_tbl_core0_rev3,
+ sizeof(papd_comp_rfpwr_tbl_core0_rev3) /
+ sizeof(papd_comp_rfpwr_tbl_core0_rev3[0]), 26, 576, 16}
+ ,
+ {&papd_comp_rfpwr_tbl_core1_rev3,
+ sizeof(papd_comp_rfpwr_tbl_core1_rev3) /
+ sizeof(papd_comp_rfpwr_tbl_core1_rev3[0]), 27, 576, 16}
+ ,
+ {&papd_comp_epsilon_tbl_core0_rev7,
+ sizeof(papd_comp_epsilon_tbl_core0_rev7) /
+ sizeof(papd_comp_epsilon_tbl_core0_rev7[0]), 31, 0, 32}
+ ,
+ {&papd_cal_scalars_tbl_core0_rev7,
+ sizeof(papd_cal_scalars_tbl_core0_rev7) /
+ sizeof(papd_cal_scalars_tbl_core0_rev7[0]), 32, 0, 32}
+ ,
+ {&papd_comp_epsilon_tbl_core1_rev7,
+ sizeof(papd_comp_epsilon_tbl_core1_rev7) /
+ sizeof(papd_comp_epsilon_tbl_core1_rev7[0]), 33, 0, 32}
+ ,
+ {&papd_cal_scalars_tbl_core1_rev7,
+ sizeof(papd_cal_scalars_tbl_core1_rev7) /
+ sizeof(papd_cal_scalars_tbl_core1_rev7[0]), 34, 0, 32}
+ ,
+};
+
+const u32 mimophytbl_info_sz_rev7 =
+ sizeof(mimophytbl_info_rev7) / sizeof(mimophytbl_info_rev7[0]);
+
+const mimophytbl_info_t mimophytbl_info_rev16[] = {
+ {&noise_var_tbl_rev7,
+ sizeof(noise_var_tbl_rev7) / sizeof(noise_var_tbl_rev7[0]), 16, 0, 32}
+ ,
+ {&est_pwr_lut_core0_rev3,
+ sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
+ 0, 8}
+ ,
+ {&est_pwr_lut_core1_rev3,
+ sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
+ 0, 8}
+ ,
+ {&adj_pwr_lut_core0_rev3,
+ sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
+ 64, 8}
+ ,
+ {&adj_pwr_lut_core1_rev3,
+ sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
+ 64, 8}
+ ,
+ {&gainctrl_lut_core0_rev3,
+ sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
+ 26, 192, 32}
+ ,
+ {&gainctrl_lut_core1_rev3,
+ sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
+ 27, 192, 32}
+ ,
+ {&iq_lut_core0_rev3,
+ sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
+ ,
+ {&iq_lut_core1_rev3,
+ sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
+ ,
+ {&loft_lut_core0_rev3,
+ sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
+ 16}
+ ,
+ {&loft_lut_core1_rev3,
+ sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
+ 16}
+ ,
+};
+
+const u32 mimophytbl_info_sz_rev16 =
+ sizeof(mimophytbl_info_rev16) / sizeof(mimophytbl_info_rev16[0]);
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define ANT_SWCTRL_TBL_REV3_IDX (0)
+
+typedef phytbl_info_t mimophytbl_info_t;
+
+extern const mimophytbl_info_t mimophytbl_info_rev0[],
+ mimophytbl_info_rev0_volatile[];
+extern const u32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile;
+
+extern const mimophytbl_info_t mimophytbl_info_rev3[],
+ mimophytbl_info_rev3_volatile[], mimophytbl_info_rev3_volatile1[],
+ mimophytbl_info_rev3_volatile2[], mimophytbl_info_rev3_volatile3[];
+extern const u32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile,
+ mimophytbl_info_sz_rev3_volatile1, mimophytbl_info_sz_rev3_volatile2,
+ mimophytbl_info_sz_rev3_volatile3;
+
+extern const u32 noise_var_tbl_rev3[];
+
+extern const mimophytbl_info_t mimophytbl_info_rev7[];
+extern const u32 mimophytbl_info_sz_rev7;
+extern const u32 noise_var_tbl_rev7[];
+
+extern const mimophytbl_info_t mimophytbl_info_rev16[];
+extern const u32 mimophytbl_info_sz_rev16;
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <wlc_cfg.h>
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-
-#include <bcmdefs.h>
-#include <chipcommon.h>
-#include <bcmdevs.h>
-#include "bcmdma.h"
-
-#include <wlc_types.h>
-#include <wlc_phy_int.h>
-#include <wlc_phyreg_n.h>
-#include <wlc_phy_radio.h>
-#include <wlc_phy_lcn.h>
-
-u32 phyhal_msg_level = PHYHAL_ERROR;
-
-typedef struct _chan_info_basic {
- u16 chan;
- u16 freq;
-} chan_info_basic_t;
-
-static chan_info_basic_t chan_info_all[] = {
-
- {1, 2412},
- {2, 2417},
- {3, 2422},
- {4, 2427},
- {5, 2432},
- {6, 2437},
- {7, 2442},
- {8, 2447},
- {9, 2452},
- {10, 2457},
- {11, 2462},
- {12, 2467},
- {13, 2472},
- {14, 2484},
-
- {34, 5170},
- {38, 5190},
- {42, 5210},
- {46, 5230},
-
- {36, 5180},
- {40, 5200},
- {44, 5220},
- {48, 5240},
- {52, 5260},
- {56, 5280},
- {60, 5300},
- {64, 5320},
-
- {100, 5500},
- {104, 5520},
- {108, 5540},
- {112, 5560},
- {116, 5580},
- {120, 5600},
- {124, 5620},
- {128, 5640},
- {132, 5660},
- {136, 5680},
- {140, 5700},
-
- {149, 5745},
- {153, 5765},
- {157, 5785},
- {161, 5805},
- {165, 5825},
-
- {184, 4920},
- {188, 4940},
- {192, 4960},
- {196, 4980},
- {200, 5000},
- {204, 5020},
- {208, 5040},
- {212, 5060},
- {216, 50800}
-};
-
-u16 ltrn_list[PHY_LTRN_LIST_LEN] = {
- 0x18f9, 0x0d01, 0x00e4, 0xdef4, 0x06f1, 0x0ffc,
- 0xfa27, 0x1dff, 0x10f0, 0x0918, 0xf20a, 0xe010,
- 0x1417, 0x1104, 0xf114, 0xf2fa, 0xf7db, 0xe2fc,
- 0xe1fb, 0x13ee, 0xff0d, 0xe91c, 0x171a, 0x0318,
- 0xda00, 0x03e8, 0x17e6, 0xe9e4, 0xfff3, 0x1312,
- 0xe105, 0xe204, 0xf725, 0xf206, 0xf1ec, 0x11fc,
- 0x14e9, 0xe0f0, 0xf2f6, 0x09e8, 0x1010, 0x1d01,
- 0xfad9, 0x0f04, 0x060f, 0xde0c, 0x001c, 0x0dff,
- 0x1807, 0xf61a, 0xe40e, 0x0f16, 0x05f9, 0x18ec,
- 0x0a1b, 0xff1e, 0x2600, 0xffe2, 0x0ae5, 0x1814,
- 0x0507, 0x0fea, 0xe4f2, 0xf6e6
-};
-
-const u8 ofdm_rate_lookup[] = {
-
- WLC_RATE_48M,
- WLC_RATE_24M,
- WLC_RATE_12M,
- WLC_RATE_6M,
- WLC_RATE_54M,
- WLC_RATE_36M,
- WLC_RATE_18M,
- WLC_RATE_9M
-};
-
-#define PHY_WREG_LIMIT 24
-
-static void wlc_set_phy_uninitted(phy_info_t *pi);
-static u32 wlc_phy_get_radio_ver(phy_info_t *pi);
-static void wlc_phy_timercb_phycal(void *arg);
-
-static bool wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr,
- s8 *pwr_ant);
-
-static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay);
-static void wlc_phy_noise_cb(phy_info_t *pi, u8 channel, s8 noise_dbm);
-static void wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason,
- u8 ch);
-
-static void wlc_phy_txpower_reg_limit_calc(phy_info_t *pi,
- struct txpwr_limits *tp, chanspec_t);
-static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi);
-
-static s8 wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan,
- u32 band, u8 rate);
-static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band);
-static s8 wlc_phy_env_measure_vbat(phy_info_t *pi);
-static s8 wlc_phy_env_measure_temperature(phy_info_t *pi);
-
-char *phy_getvar(phy_info_t *pi, const char *name)
-{
- char *vars = pi->vars;
- char *s;
- int len;
-
- if (!name)
- return NULL;
-
- len = strlen(name);
- if (len == 0)
- return NULL;
-
- for (s = vars; s && *s;) {
- if ((memcmp(s, name, len) == 0) && (s[len] == '='))
- return &s[len + 1];
-
- while (*s++)
- ;
- }
-
- return NULL;
-}
-
-int phy_getintvar(phy_info_t *pi, const char *name)
-{
- char *val;
-
- val = PHY_GETVAR(pi, name);
- if (val == NULL)
- return 0;
-
- return simple_strtoul(val, NULL, 0);
-}
-
-void wlc_phyreg_enter(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- wlapi_bmac_ucode_wake_override_phyreg_set(pi->sh->physhim);
-}
-
-void wlc_phyreg_exit(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- wlapi_bmac_ucode_wake_override_phyreg_clear(pi->sh->physhim);
-}
-
-void wlc_radioreg_enter(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO);
-
- udelay(10);
-}
-
-void wlc_radioreg_exit(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- volatile u16 dummy;
-
- dummy = R_REG(&pi->regs->phyversion);
- pi->phy_wreg = 0;
- wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);
-}
-
-u16 read_radio_reg(phy_info_t *pi, u16 addr)
-{
- u16 data;
-
- if ((addr == RADIO_IDCODE))
- return 0xffff;
-
- if (NORADIO_ENAB(pi->pubpi))
- return NORADIO_IDCODE & 0xffff;
-
- switch (pi->pubpi.phy_type) {
- case PHY_TYPE_N:
- CASECHECK(PHYTYPE, PHY_TYPE_N);
- if (NREV_GE(pi->pubpi.phy_rev, 7))
- addr |= RADIO_2057_READ_OFF;
- else
- addr |= RADIO_2055_READ_OFF;
- break;
-
- case PHY_TYPE_LCN:
- CASECHECK(PHYTYPE, PHY_TYPE_LCN);
- addr |= RADIO_2064_READ_OFF;
- break;
-
- default:
- break;
- }
-
- if ((D11REV_GE(pi->sh->corerev, 24)) ||
- (D11REV_IS(pi->sh->corerev, 22)
- && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
- W_REG_FLUSH(&pi->regs->radioregaddr, addr);
- data = R_REG(&pi->regs->radioregdata);
- } else {
- W_REG_FLUSH(&pi->regs->phy4waddr, addr);
-
-#ifdef __ARM_ARCH_4T__
- __asm__(" .align 4 ");
- __asm__(" nop ");
- data = R_REG(&pi->regs->phy4wdatalo);
-#else
- data = R_REG(&pi->regs->phy4wdatalo);
-#endif
-
- }
- pi->phy_wreg = 0;
-
- return data;
-}
-
-void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
-{
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- if ((D11REV_GE(pi->sh->corerev, 24)) ||
- (D11REV_IS(pi->sh->corerev, 22)
- && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
-
- W_REG_FLUSH(&pi->regs->radioregaddr, addr);
- W_REG(&pi->regs->radioregdata, val);
- } else {
- W_REG_FLUSH(&pi->regs->phy4waddr, addr);
- W_REG(&pi->regs->phy4wdatalo, val);
- }
-
- if (pi->sh->bustype == PCI_BUS) {
- if (++pi->phy_wreg >= pi->phy_wreg_limit) {
- (void)R_REG(&pi->regs->maccontrol);
- pi->phy_wreg = 0;
- }
- }
-}
-
-static u32 read_radio_id(phy_info_t *pi)
-{
- u32 id;
-
- if (NORADIO_ENAB(pi->pubpi))
- return NORADIO_IDCODE;
-
- if (D11REV_GE(pi->sh->corerev, 24)) {
- u32 b0, b1, b2;
-
- W_REG_FLUSH(&pi->regs->radioregaddr, 0);
- b0 = (u32) R_REG(&pi->regs->radioregdata);
- W_REG_FLUSH(&pi->regs->radioregaddr, 1);
- b1 = (u32) R_REG(&pi->regs->radioregdata);
- W_REG_FLUSH(&pi->regs->radioregaddr, 2);
- b2 = (u32) R_REG(&pi->regs->radioregdata);
-
- id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
- & 0xf);
- } else {
- W_REG_FLUSH(&pi->regs->phy4waddr, RADIO_IDCODE);
- id = (u32) R_REG(&pi->regs->phy4wdatalo);
- id |= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
- }
- pi->phy_wreg = 0;
- return id;
-}
-
-void and_radio_reg(phy_info_t *pi, u16 addr, u16 val)
-{
- u16 rval;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- rval = read_radio_reg(pi, addr);
- write_radio_reg(pi, addr, (rval & val));
-}
-
-void or_radio_reg(phy_info_t *pi, u16 addr, u16 val)
-{
- u16 rval;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- rval = read_radio_reg(pi, addr);
- write_radio_reg(pi, addr, (rval | val));
-}
-
-void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask)
-{
- u16 rval;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- rval = read_radio_reg(pi, addr);
- write_radio_reg(pi, addr, (rval ^ mask));
-}
-
-void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
-{
- u16 rval;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- rval = read_radio_reg(pi, addr);
- write_radio_reg(pi, addr, (rval & ~mask) | (val & mask));
-}
-
-void write_phy_channel_reg(phy_info_t *pi, uint val)
-{
- W_REG(&pi->regs->phychannel, val);
-}
-
-u16 read_phy_reg(phy_info_t *pi, u16 addr)
-{
- d11regs_t *regs;
-
- regs = pi->regs;
-
- W_REG_FLUSH(®s->phyregaddr, addr);
-
- pi->phy_wreg = 0;
- return R_REG(®s->phyregdata);
-}
-
-void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
-{
- d11regs_t *regs;
-
- regs = pi->regs;
-
-#ifdef __mips__
- W_REG_FLUSH(®s->phyregaddr, addr);
- W_REG(®s->phyregdata, val);
- if (addr == 0x72)
- (void)R_REG(®s->phyregdata);
-#else
- W_REG((u32 *)(®s->phyregaddr),
- addr | (val << 16));
- if (pi->sh->bustype == PCI_BUS) {
- if (++pi->phy_wreg >= pi->phy_wreg_limit) {
- pi->phy_wreg = 0;
- (void)R_REG(®s->phyversion);
- }
- }
-#endif
-}
-
-void and_phy_reg(phy_info_t *pi, u16 addr, u16 val)
-{
- d11regs_t *regs;
-
- regs = pi->regs;
-
- W_REG_FLUSH(®s->phyregaddr, addr);
-
- W_REG(®s->phyregdata, (R_REG(®s->phyregdata) & val));
- pi->phy_wreg = 0;
-}
-
-void or_phy_reg(phy_info_t *pi, u16 addr, u16 val)
-{
- d11regs_t *regs;
-
- regs = pi->regs;
-
- W_REG_FLUSH(®s->phyregaddr, addr);
-
- W_REG(®s->phyregdata, (R_REG(®s->phyregdata) | val));
- pi->phy_wreg = 0;
-}
-
-void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
-{
- d11regs_t *regs;
-
- regs = pi->regs;
-
- W_REG_FLUSH(®s->phyregaddr, addr);
-
- W_REG(®s->phyregdata,
- ((R_REG(®s->phyregdata) & ~mask) | (val & mask)));
- pi->phy_wreg = 0;
-}
-
-static void WLBANDINITFN(wlc_set_phy_uninitted) (phy_info_t *pi)
-{
- int i, j;
-
- pi->initialized = false;
-
- pi->tx_vos = 0xffff;
- pi->nrssi_table_delta = 0x7fffffff;
- pi->rc_cal = 0xffff;
- pi->mintxbias = 0xffff;
- pi->txpwridx = -1;
- if (ISNPHY(pi)) {
- pi->phy_spuravoid = SPURAVOID_DISABLE;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)
- && NREV_LT(pi->pubpi.phy_rev, 7))
- pi->phy_spuravoid = SPURAVOID_AUTO;
-
- pi->nphy_papd_skip = 0;
- pi->nphy_papd_epsilon_offset[0] = 0xf588;
- pi->nphy_papd_epsilon_offset[1] = 0xf588;
- pi->nphy_txpwr_idx[0] = 128;
- pi->nphy_txpwr_idx[1] = 128;
- pi->nphy_txpwrindex[0].index_internal = 40;
- pi->nphy_txpwrindex[1].index_internal = 40;
- pi->phy_pabias = 0;
- } else {
- pi->phy_spuravoid = SPURAVOID_AUTO;
- }
- pi->radiopwr = 0xffff;
- for (i = 0; i < STATIC_NUM_RF; i++) {
- for (j = 0; j < STATIC_NUM_BB; j++) {
- pi->stats_11b_txpower[i][j] = -1;
- }
- }
-}
-
-shared_phy_t *wlc_phy_shared_attach(shared_phy_params_t *shp)
-{
- shared_phy_t *sh;
-
- sh = kzalloc(sizeof(shared_phy_t), GFP_ATOMIC);
- if (sh == NULL) {
- return NULL;
- }
-
- sh->sih = shp->sih;
- sh->physhim = shp->physhim;
- sh->unit = shp->unit;
- sh->corerev = shp->corerev;
-
- sh->vid = shp->vid;
- sh->did = shp->did;
- sh->chip = shp->chip;
- sh->chiprev = shp->chiprev;
- sh->chippkg = shp->chippkg;
- sh->sromrev = shp->sromrev;
- sh->boardtype = shp->boardtype;
- sh->boardrev = shp->boardrev;
- sh->boardvendor = shp->boardvendor;
- sh->boardflags = shp->boardflags;
- sh->boardflags2 = shp->boardflags2;
- sh->bustype = shp->bustype;
- sh->buscorerev = shp->buscorerev;
-
- sh->fast_timer = PHY_SW_TIMER_FAST;
- sh->slow_timer = PHY_SW_TIMER_SLOW;
- sh->glacial_timer = PHY_SW_TIMER_GLACIAL;
-
- sh->rssi_mode = RSSI_ANT_MERGE_MAX;
-
- return sh;
-}
-
-void wlc_phy_shared_detach(shared_phy_t *phy_sh)
-{
- if (phy_sh) {
- kfree(phy_sh);
- }
-}
-
-wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype,
- char *vars, struct wiphy *wiphy)
-{
- phy_info_t *pi;
- u32 sflags = 0;
- uint phyversion;
- int i;
-
- if (D11REV_IS(sh->corerev, 4))
- sflags = SISF_2G_PHY | SISF_5G_PHY;
- else
- sflags = ai_core_sflags(sh->sih, 0, 0);
-
- if (BAND_5G(bandtype)) {
- if ((sflags & (SISF_5G_PHY | SISF_DB_PHY)) == 0) {
- return NULL;
- }
- }
-
- pi = sh->phy_head;
- if ((sflags & SISF_DB_PHY) && pi) {
-
- wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
- pi->refcnt++;
- return &pi->pubpi_ro;
- }
-
- pi = kzalloc(sizeof(phy_info_t), GFP_ATOMIC);
- if (pi == NULL) {
- return NULL;
- }
- pi->wiphy = wiphy;
- pi->regs = (d11regs_t *) regs;
- pi->sh = sh;
- pi->phy_init_por = true;
- pi->phy_wreg_limit = PHY_WREG_LIMIT;
-
- pi->vars = vars;
-
- pi->txpwr_percent = 100;
-
- pi->do_initcal = true;
-
- pi->phycal_tempdelta = 0;
-
- if (BAND_2G(bandtype) && (sflags & SISF_2G_PHY)) {
-
- pi->pubpi.coreflags = SICF_GMODE;
- }
-
- wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
- phyversion = R_REG(&pi->regs->phyversion);
-
- pi->pubpi.phy_type = PHY_TYPE(phyversion);
- pi->pubpi.phy_rev = phyversion & PV_PV_MASK;
-
- if (pi->pubpi.phy_type == PHY_TYPE_LCNXN) {
- pi->pubpi.phy_type = PHY_TYPE_N;
- pi->pubpi.phy_rev += LCNXN_BASEREV;
- }
- pi->pubpi.phy_corenum = PHY_CORE_NUM_2;
- pi->pubpi.ana_rev = (phyversion & PV_AV_MASK) >> PV_AV_SHIFT;
-
- if (!VALID_PHYTYPE(pi->pubpi.phy_type)) {
- goto err;
- }
- if (BAND_5G(bandtype)) {
- if (!ISNPHY(pi)) {
- goto err;
- }
- } else {
- if (!ISNPHY(pi) && !ISLCNPHY(pi)) {
- goto err;
- }
- }
-
- if (ISSIM_ENAB(pi->sh->sih)) {
- pi->pubpi.radioid = NORADIO_ID;
- pi->pubpi.radiorev = 5;
- } else {
- u32 idcode;
-
- wlc_phy_anacore((wlc_phy_t *) pi, ON);
-
- idcode = wlc_phy_get_radio_ver(pi);
- pi->pubpi.radioid =
- (idcode & IDCODE_ID_MASK) >> IDCODE_ID_SHIFT;
- pi->pubpi.radiorev =
- (idcode & IDCODE_REV_MASK) >> IDCODE_REV_SHIFT;
- pi->pubpi.radiover =
- (idcode & IDCODE_VER_MASK) >> IDCODE_VER_SHIFT;
- if (!VALID_RADIO(pi, pi->pubpi.radioid)) {
- goto err;
- }
-
- wlc_phy_switch_radio((wlc_phy_t *) pi, OFF);
- }
-
- wlc_set_phy_uninitted(pi);
-
- pi->bw = WL_CHANSPEC_BW_20;
- pi->radio_chanspec =
- BAND_2G(bandtype) ? CH20MHZ_CHSPEC(1) : CH20MHZ_CHSPEC(36);
-
- pi->rxiq_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
- pi->rxiq_antsel = ANT_RX_DIV_DEF;
-
- pi->watchdog_override = true;
-
- pi->cal_type_override = PHY_PERICAL_AUTO;
-
- pi->nphy_saved_noisevars.bufcount = 0;
-
- if (ISNPHY(pi))
- pi->min_txpower = PHY_TXPWR_MIN_NPHY;
- else
- pi->min_txpower = PHY_TXPWR_MIN;
-
- pi->sh->phyrxchain = 0x3;
-
- pi->rx2tx_biasentry = -1;
-
- pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
- pi->phy_txcore_enable_temp =
- PHY_CHAIN_TX_DISABLE_TEMP - PHY_HYSTERESIS_DELTATEMP;
- pi->phy_tempsense_offset = 0;
- pi->phy_txcore_heatedup = false;
-
- pi->nphy_lastcal_temp = -50;
-
- pi->phynoise_polling = true;
- if (ISNPHY(pi) || ISLCNPHY(pi))
- pi->phynoise_polling = false;
-
- for (i = 0; i < TXP_NUM_RATES; i++) {
- pi->txpwr_limit[i] = WLC_TXPWR_MAX;
- pi->txpwr_env_limit[i] = WLC_TXPWR_MAX;
- pi->tx_user_target[i] = WLC_TXPWR_MAX;
- }
-
- pi->radiopwr_override = RADIOPWR_OVERRIDE_DEF;
-
- pi->user_txpwr_at_rfport = false;
-
- if (ISNPHY(pi)) {
-
- pi->phycal_timer = wlapi_init_timer(pi->sh->physhim,
- wlc_phy_timercb_phycal,
- pi, "phycal");
- if (!pi->phycal_timer) {
- goto err;
- }
-
- if (!wlc_phy_attach_nphy(pi))
- goto err;
-
- } else if (ISLCNPHY(pi)) {
- if (!wlc_phy_attach_lcnphy(pi))
- goto err;
-
- } else {
-
- }
-
- pi->refcnt++;
- pi->next = pi->sh->phy_head;
- sh->phy_head = pi;
-
- pi->vars = (char *)&pi->vars;
-
- memcpy(&pi->pubpi_ro, &pi->pubpi, sizeof(wlc_phy_t));
-
- return &pi->pubpi_ro;
-
- err:
- kfree(pi);
- return NULL;
-}
-
-void wlc_phy_detach(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (pih) {
- if (--pi->refcnt) {
- return;
- }
-
- if (pi->phycal_timer) {
- wlapi_free_timer(pi->sh->physhim, pi->phycal_timer);
- pi->phycal_timer = NULL;
- }
-
- if (pi->sh->phy_head == pi)
- pi->sh->phy_head = pi->next;
- else if (pi->sh->phy_head->next == pi)
- pi->sh->phy_head->next = NULL;
-
- if (pi->pi_fptr.detach)
- (pi->pi_fptr.detach) (pi);
-
- kfree(pi);
- }
-}
-
-bool
-wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype, u16 *phyrev,
- u16 *radioid, u16 *radiover)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- *phytype = (u16) pi->pubpi.phy_type;
- *phyrev = (u16) pi->pubpi.phy_rev;
- *radioid = pi->pubpi.radioid;
- *radiover = pi->pubpi.radiorev;
-
- return true;
-}
-
-bool wlc_phy_get_encore(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- return pi->pubpi.abgphy_encore;
-}
-
-u32 wlc_phy_get_coreflags(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- return pi->pubpi.coreflags;
-}
-
-static void wlc_phy_timercb_phycal(void *arg)
-{
- phy_info_t *pi = (phy_info_t *) arg;
- uint delay = 5;
-
- if (PHY_PERICAL_MPHASE_PENDING(pi)) {
- if (!pi->sh->up) {
- wlc_phy_cal_perical_mphase_reset(pi);
- return;
- }
-
- if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)) {
-
- delay = 1000;
- wlc_phy_cal_perical_mphase_restart(pi);
- } else
- wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_AUTO);
- wlapi_add_timer(pi->sh->physhim, pi->phycal_timer, delay, 0);
- return;
- }
-
-}
-
-void wlc_phy_anacore(wlc_phy_t *pih, bool on)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (ISNPHY(pi)) {
- if (on) {
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- write_phy_reg(pi, 0xa6, 0x0d);
- write_phy_reg(pi, 0x8f, 0x0);
- write_phy_reg(pi, 0xa7, 0x0d);
- write_phy_reg(pi, 0xa5, 0x0);
- } else {
- write_phy_reg(pi, 0xa5, 0x0);
- }
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- write_phy_reg(pi, 0x8f, 0x07ff);
- write_phy_reg(pi, 0xa6, 0x0fd);
- write_phy_reg(pi, 0xa5, 0x07ff);
- write_phy_reg(pi, 0xa7, 0x0fd);
- } else {
- write_phy_reg(pi, 0xa5, 0x7fff);
- }
- }
- } else if (ISLCNPHY(pi)) {
- if (on) {
- and_phy_reg(pi, 0x43b,
- ~((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
- } else {
- or_phy_reg(pi, 0x43c,
- (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
- or_phy_reg(pi, 0x43b,
- (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
- }
- }
-}
-
-u32 wlc_phy_clk_bwbits(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- u32 phy_bw_clkbits = 0;
-
- if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
- switch (pi->bw) {
- case WL_CHANSPEC_BW_10:
- phy_bw_clkbits = SICF_BW10;
- break;
- case WL_CHANSPEC_BW_20:
- phy_bw_clkbits = SICF_BW20;
- break;
- case WL_CHANSPEC_BW_40:
- phy_bw_clkbits = SICF_BW40;
- break;
- default:
- break;
- }
- }
-
- return phy_bw_clkbits;
-}
-
-void WLBANDINITFN(wlc_phy_por_inform) (wlc_phy_t *ppi)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- pi->phy_init_por = true;
-}
-
-void wlc_phy_edcrs_lock(wlc_phy_t *pih, bool lock)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- pi->edcrs_threshold_lock = lock;
-
- write_phy_reg(pi, 0x22c, 0x46b);
- write_phy_reg(pi, 0x22d, 0x46b);
- write_phy_reg(pi, 0x22e, 0x3c0);
- write_phy_reg(pi, 0x22f, 0x3c0);
-}
-
-void wlc_phy_initcal_enable(wlc_phy_t *pih, bool initcal)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- pi->do_initcal = initcal;
-}
-
-void wlc_phy_hw_clk_state_upd(wlc_phy_t *pih, bool newstate)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (!pi || !pi->sh)
- return;
-
- pi->sh->clk = newstate;
-}
-
-void wlc_phy_hw_state_upd(wlc_phy_t *pih, bool newstate)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (!pi || !pi->sh)
- return;
-
- pi->sh->up = newstate;
-}
-
-void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec)
-{
- u32 mc;
- initfn_t phy_init = NULL;
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (pi->init_in_progress)
- return;
-
- pi->init_in_progress = true;
-
- pi->radio_chanspec = chanspec;
-
- mc = R_REG(&pi->regs->maccontrol);
- if (WARN(mc & MCTL_EN_MAC, "HW error MAC running on init"))
- return;
-
- if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN)) {
- pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
- }
-
- if (WARN(!(ai_core_sflags(pi->sh->sih, 0, 0) & SISF_FCLKA),
- "HW error SISF_FCLKA\n"))
- return;
-
- phy_init = pi->pi_fptr.init;
-
- if (phy_init == NULL) {
- return;
- }
-
- wlc_phy_anacore(pih, ON);
-
- if (CHSPEC_BW(pi->radio_chanspec) != pi->bw)
- wlapi_bmac_bw_set(pi->sh->physhim,
- CHSPEC_BW(pi->radio_chanspec));
-
- pi->nphy_gain_boost = true;
-
- wlc_phy_switch_radio((wlc_phy_t *) pi, ON);
-
- (*phy_init) (pi);
-
- pi->phy_init_por = false;
-
- if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
- wlc_phy_do_dummy_tx(pi, true, OFF);
-
- if (!(ISNPHY(pi)))
- wlc_phy_txpower_update_shm(pi);
-
- wlc_phy_ant_rxdiv_set((wlc_phy_t *) pi, pi->sh->rx_antdiv);
-
- pi->init_in_progress = false;
-}
-
-void wlc_phy_cal_init(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- initfn_t cal_init = NULL;
-
- if (WARN((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) != 0,
- "HW error: MAC enabled during phy cal\n"))
- return;
-
- if (!pi->initialized) {
- cal_init = pi->pi_fptr.calinit;
- if (cal_init)
- (*cal_init) (pi);
-
- pi->initialized = true;
- }
-}
-
-int wlc_phy_down(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- int callbacks = 0;
-
- if (pi->phycal_timer
- && !wlapi_del_timer(pi->sh->physhim, pi->phycal_timer))
- callbacks++;
-
- pi->nphy_iqcal_chanspec_2G = 0;
- pi->nphy_iqcal_chanspec_5G = 0;
-
- return callbacks;
-}
-
-static u32 wlc_phy_get_radio_ver(phy_info_t *pi)
-{
- u32 ver;
-
- ver = read_radio_id(pi);
-
- return ver;
-}
-
-void
-wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
- u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
-{
- write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
-
- pi->tbl_data_hi = tblDataHi;
- pi->tbl_data_lo = tblDataLo;
-
- if ((pi->sh->chip == BCM43224_CHIP_ID ||
- pi->sh->chip == BCM43421_CHIP_ID) &&
- (pi->sh->chiprev == 1)) {
- pi->tbl_addr = tblAddr;
- pi->tbl_save_id = tbl_id;
- pi->tbl_save_offset = tbl_offset;
- }
-}
-
-void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val)
-{
- if ((pi->sh->chip == BCM43224_CHIP_ID ||
- pi->sh->chip == BCM43421_CHIP_ID) &&
- (pi->sh->chiprev == 1) &&
- (pi->tbl_save_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
- read_phy_reg(pi, pi->tbl_data_lo);
-
- write_phy_reg(pi, pi->tbl_addr,
- (pi->tbl_save_id << 10) | pi->tbl_save_offset);
- pi->tbl_save_offset++;
- }
-
- if (width == 32) {
-
- write_phy_reg(pi, pi->tbl_data_hi, (u16) (val >> 16));
- write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
- } else {
-
- write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
- }
-}
-
-void
-wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
- u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
-{
- uint idx;
- uint tbl_id = ptbl_info->tbl_id;
- uint tbl_offset = ptbl_info->tbl_offset;
- uint tbl_width = ptbl_info->tbl_width;
- const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr;
- const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
- const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
-
- write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
-
- for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
-
- if ((pi->sh->chip == BCM43224_CHIP_ID ||
- pi->sh->chip == BCM43421_CHIP_ID) &&
- (pi->sh->chiprev == 1) &&
- (tbl_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
- read_phy_reg(pi, tblDataLo);
-
- write_phy_reg(pi, tblAddr,
- (tbl_id << 10) | (tbl_offset + idx));
- }
-
- if (tbl_width == 32) {
-
- write_phy_reg(pi, tblDataHi,
- (u16) (ptbl_32b[idx] >> 16));
- write_phy_reg(pi, tblDataLo, (u16) ptbl_32b[idx]);
- } else if (tbl_width == 16) {
-
- write_phy_reg(pi, tblDataLo, ptbl_16b[idx]);
- } else {
-
- write_phy_reg(pi, tblDataLo, ptbl_8b[idx]);
- }
- }
-}
-
-void
-wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
- u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
-{
- uint idx;
- uint tbl_id = ptbl_info->tbl_id;
- uint tbl_offset = ptbl_info->tbl_offset;
- uint tbl_width = ptbl_info->tbl_width;
- u8 *ptbl_8b = (u8 *)ptbl_info->tbl_ptr;
- u16 *ptbl_16b = (u16 *)ptbl_info->tbl_ptr;
- u32 *ptbl_32b = (u32 *)ptbl_info->tbl_ptr;
-
- write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
-
- for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
-
- if ((pi->sh->chip == BCM43224_CHIP_ID ||
- pi->sh->chip == BCM43421_CHIP_ID) &&
- (pi->sh->chiprev == 1)) {
- (void)read_phy_reg(pi, tblDataLo);
-
- write_phy_reg(pi, tblAddr,
- (tbl_id << 10) | (tbl_offset + idx));
- }
-
- if (tbl_width == 32) {
-
- ptbl_32b[idx] = read_phy_reg(pi, tblDataLo);
- ptbl_32b[idx] |= (read_phy_reg(pi, tblDataHi) << 16);
- } else if (tbl_width == 16) {
-
- ptbl_16b[idx] = read_phy_reg(pi, tblDataLo);
- } else {
-
- ptbl_8b[idx] = (u8) read_phy_reg(pi, tblDataLo);
- }
- }
-}
-
-uint
-wlc_phy_init_radio_regs_allbands(phy_info_t *pi, radio_20xx_regs_t *radioregs)
-{
- uint i = 0;
-
- do {
- if (radioregs[i].do_init) {
- write_radio_reg(pi, radioregs[i].address,
- (u16) radioregs[i].init);
- }
-
- i++;
- } while (radioregs[i].address != 0xffff);
-
- return i;
-}
-
-uint
-wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
- u16 core_offset)
-{
- uint i = 0;
- uint count = 0;
-
- do {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if (radioregs[i].do_init_a) {
- write_radio_reg(pi,
- radioregs[i].
- address | core_offset,
- (u16) radioregs[i].init_a);
- if (ISNPHY(pi) && (++count % 4 == 0))
- WLC_PHY_WAR_PR51571(pi);
- }
- } else {
- if (radioregs[i].do_init_g) {
- write_radio_reg(pi,
- radioregs[i].
- address | core_offset,
- (u16) radioregs[i].init_g);
- if (ISNPHY(pi) && (++count % 4 == 0))
- WLC_PHY_WAR_PR51571(pi);
- }
- }
-
- i++;
- } while (radioregs[i].address != 0xffff);
-
- return i;
-}
-
-void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
-{
-#define DUMMY_PKT_LEN 20
- d11regs_t *regs = pi->regs;
- int i, count;
- u8 ofdmpkt[DUMMY_PKT_LEN] = {
- 0xcc, 0x01, 0x02, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
- };
- u8 cckpkt[DUMMY_PKT_LEN] = {
- 0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
- };
- u32 *dummypkt;
-
- dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
- wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
- dummypkt);
-
- W_REG(®s->xmtsel, 0);
-
- if (D11REV_GE(pi->sh->corerev, 11))
- W_REG(®s->wepctl, 0x100);
- else
- W_REG(®s->wepctl, 0);
-
- W_REG(®s->txe_phyctl, (ofdm ? 1 : 0) | PHY_TXC_ANT_0);
- if (ISNPHY(pi) || ISLCNPHY(pi)) {
- W_REG(®s->txe_phyctl1, 0x1A02);
- }
-
- W_REG(®s->txe_wm_0, 0);
- W_REG(®s->txe_wm_1, 0);
-
- W_REG(®s->xmttplatetxptr, 0);
- W_REG(®s->xmttxcnt, DUMMY_PKT_LEN);
-
- W_REG(®s->xmtsel, ((8 << 8) | (1 << 5) | (1 << 2) | 2));
-
- W_REG(®s->txe_ctl, 0);
-
- if (!pa_on) {
- if (ISNPHY(pi))
- wlc_phy_pa_override_nphy(pi, OFF);
- }
-
- if (ISNPHY(pi) || ISLCNPHY(pi))
- W_REG(®s->txe_aux, 0xD0);
- else
- W_REG(®s->txe_aux, ((1 << 5) | (1 << 4)));
-
- (void)R_REG(®s->txe_aux);
-
- i = 0;
- count = ofdm ? 30 : 250;
-
- if (ISSIM_ENAB(pi->sh->sih)) {
- count *= 100;
- }
-
- while ((i++ < count)
- && (R_REG(®s->txe_status) & (1 << 7))) {
- udelay(10);
- }
-
- i = 0;
-
- while ((i++ < 10)
- && ((R_REG(®s->txe_status) & (1 << 10)) == 0)) {
- udelay(10);
- }
-
- i = 0;
-
- while ((i++ < 10) && ((R_REG(®s->ifsstat) & (1 << 8))))
- udelay(10);
-
- if (!pa_on) {
- if (ISNPHY(pi))
- wlc_phy_pa_override_nphy(pi, ON);
- }
-}
-
-void wlc_phy_hold_upd(wlc_phy_t *pih, mbool id, bool set)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (set) {
- mboolset(pi->measure_hold, id);
- } else {
- mboolclr(pi->measure_hold, id);
- }
-
- return;
-}
-
-void wlc_phy_mute_upd(wlc_phy_t *pih, bool mute, mbool flags)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (mute) {
- mboolset(pi->measure_hold, PHY_HOLD_FOR_MUTE);
- } else {
- mboolclr(pi->measure_hold, PHY_HOLD_FOR_MUTE);
- }
-
- if (!mute && (flags & PHY_MUTE_FOR_PREISM))
- pi->nphy_perical_last = pi->sh->now - pi->sh->glacial_timer;
- return;
-}
-
-void wlc_phy_clear_tssi(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (ISNPHY(pi)) {
- return;
- } else {
- wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_0, NULL_TSSI_W);
- wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_1, NULL_TSSI_W);
- wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_0, NULL_TSSI_W);
- wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_1, NULL_TSSI_W);
- }
-}
-
-static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi)
-{
- return false;
-}
-
-void wlc_phy_switch_radio(wlc_phy_t *pih, bool on)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- {
- uint mc;
-
- mc = R_REG(&pi->regs->maccontrol);
- }
-
- if (ISNPHY(pi)) {
- wlc_phy_switch_radio_nphy(pi, on);
-
- } else if (ISLCNPHY(pi)) {
- if (on) {
- and_phy_reg(pi, 0x44c,
- ~((0x1 << 8) |
- (0x1 << 9) |
- (0x1 << 10) | (0x1 << 11) | (0x1 << 12)));
- and_phy_reg(pi, 0x4b0, ~((0x1 << 3) | (0x1 << 11)));
- and_phy_reg(pi, 0x4f9, ~(0x1 << 3));
- } else {
- and_phy_reg(pi, 0x44d,
- ~((0x1 << 10) |
- (0x1 << 11) |
- (0x1 << 12) | (0x1 << 13) | (0x1 << 14)));
- or_phy_reg(pi, 0x44c,
- (0x1 << 8) |
- (0x1 << 9) |
- (0x1 << 10) | (0x1 << 11) | (0x1 << 12));
-
- and_phy_reg(pi, 0x4b7, ~((0x7f << 8)));
- and_phy_reg(pi, 0x4b1, ~((0x1 << 13)));
- or_phy_reg(pi, 0x4b0, (0x1 << 3) | (0x1 << 11));
- and_phy_reg(pi, 0x4fa, ~((0x1 << 3)));
- or_phy_reg(pi, 0x4f9, (0x1 << 3));
- }
- }
-}
-
-u16 wlc_phy_bw_state_get(wlc_phy_t *ppi)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- return pi->bw;
-}
-
-void wlc_phy_bw_state_set(wlc_phy_t *ppi, u16 bw)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- pi->bw = bw;
-}
-
-void wlc_phy_chanspec_radio_set(wlc_phy_t *ppi, chanspec_t newch)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- pi->radio_chanspec = newch;
-
-}
-
-chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- return pi->radio_chanspec;
-}
-
-void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- u16 m_cur_channel;
- chansetfn_t chanspec_set = NULL;
-
- m_cur_channel = CHSPEC_CHANNEL(chanspec);
- if (CHSPEC_IS5G(chanspec))
- m_cur_channel |= D11_CURCHANNEL_5G;
- if (CHSPEC_IS40(chanspec))
- m_cur_channel |= D11_CURCHANNEL_40;
- wlapi_bmac_write_shm(pi->sh->physhim, M_CURCHANNEL, m_cur_channel);
-
- chanspec_set = pi->pi_fptr.chanset;
- if (chanspec_set)
- (*chanspec_set) (pi, chanspec);
-
-}
-
-int wlc_phy_chanspec_freq2bandrange_lpssn(uint freq)
-{
- int range = -1;
-
- if (freq < 2500)
- range = WL_CHAN_FREQ_RANGE_2G;
- else if (freq <= 5320)
- range = WL_CHAN_FREQ_RANGE_5GL;
- else if (freq <= 5700)
- range = WL_CHAN_FREQ_RANGE_5GM;
- else
- range = WL_CHAN_FREQ_RANGE_5GH;
-
- return range;
-}
-
-int wlc_phy_chanspec_bandrange_get(phy_info_t *pi, chanspec_t chanspec)
-{
- int range = -1;
- uint channel = CHSPEC_CHANNEL(chanspec);
- uint freq = wlc_phy_channel2freq(channel);
-
- if (ISNPHY(pi)) {
- range = wlc_phy_get_chan_freq_range_nphy(pi, channel);
- } else if (ISLCNPHY(pi)) {
- range = wlc_phy_chanspec_freq2bandrange_lpssn(freq);
- }
-
- return range;
-}
-
-void wlc_phy_chanspec_ch14_widefilter_set(wlc_phy_t *ppi, bool wide_filter)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- pi->channel_14_wide_filter = wide_filter;
-
-}
-
-int wlc_phy_channel2freq(uint channel)
-{
- uint i;
-
- for (i = 0; i < ARRAY_SIZE(chan_info_all); i++)
- if (chan_info_all[i].chan == channel)
- return chan_info_all[i].freq;
- return 0;
-}
-
-void
-wlc_phy_chanspec_band_validch(wlc_phy_t *ppi, uint band, chanvec_t *channels)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- uint i;
- uint channel;
-
- memset(channels, 0, sizeof(chanvec_t));
-
- for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
- channel = chan_info_all[i].chan;
-
- if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
- && (channel <= LAST_REF5_CHANNUM))
- continue;
-
- if (((band == WLC_BAND_2G) && (channel <= CH_MAX_2G_CHANNEL)) ||
- ((band == WLC_BAND_5G) && (channel > CH_MAX_2G_CHANNEL)))
- setbit(channels->vec, channel);
- }
-}
-
-chanspec_t wlc_phy_chanspec_band_firstch(wlc_phy_t *ppi, uint band)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- uint i;
- uint channel;
- chanspec_t chspec;
-
- for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
- channel = chan_info_all[i].chan;
-
- if (ISNPHY(pi) && IS40MHZ(pi)) {
- uint j;
-
- for (j = 0; j < ARRAY_SIZE(chan_info_all); j++) {
- if (chan_info_all[j].chan ==
- channel + CH_10MHZ_APART)
- break;
- }
-
- if (j == ARRAY_SIZE(chan_info_all))
- continue;
-
- channel = UPPER_20_SB(channel);
- chspec =
- channel | WL_CHANSPEC_BW_40 |
- WL_CHANSPEC_CTL_SB_LOWER;
- if (band == WLC_BAND_2G)
- chspec |= WL_CHANSPEC_BAND_2G;
- else
- chspec |= WL_CHANSPEC_BAND_5G;
- } else
- chspec = CH20MHZ_CHSPEC(channel);
-
- if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
- && (channel <= LAST_REF5_CHANNUM))
- continue;
-
- if (((band == WLC_BAND_2G) && (channel <= CH_MAX_2G_CHANNEL)) ||
- ((band == WLC_BAND_5G) && (channel > CH_MAX_2G_CHANNEL)))
- return chspec;
- }
-
- return (chanspec_t) INVCHANSPEC;
-}
-
-int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- *qdbm = pi->tx_user_target[0];
- if (override != NULL)
- *override = pi->txpwroverride;
- return 0;
-}
-
-void wlc_phy_txpower_target_set(wlc_phy_t *ppi, struct txpwr_limits *txpwr)
-{
- bool mac_enabled = false;
- phy_info_t *pi = (phy_info_t *) ppi;
-
- memcpy(&pi->tx_user_target[TXP_FIRST_CCK],
- &txpwr->cck[0], WLC_NUM_RATES_CCK);
-
- memcpy(&pi->tx_user_target[TXP_FIRST_OFDM],
- &txpwr->ofdm[0], WLC_NUM_RATES_OFDM);
- memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_20_CDD],
- &txpwr->ofdm_cdd[0], WLC_NUM_RATES_OFDM);
-
- memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_SISO],
- &txpwr->ofdm_40_siso[0], WLC_NUM_RATES_OFDM);
- memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_CDD],
- &txpwr->ofdm_40_cdd[0], WLC_NUM_RATES_OFDM);
-
- memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SISO],
- &txpwr->mcs_20_siso[0], WLC_NUM_RATES_MCS_1_STREAM);
- memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_CDD],
- &txpwr->mcs_20_cdd[0], WLC_NUM_RATES_MCS_1_STREAM);
- memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_STBC],
- &txpwr->mcs_20_stbc[0], WLC_NUM_RATES_MCS_1_STREAM);
- memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SDM],
- &txpwr->mcs_20_mimo[0], WLC_NUM_RATES_MCS_2_STREAM);
-
- memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SISO],
- &txpwr->mcs_40_siso[0], WLC_NUM_RATES_MCS_1_STREAM);
- memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_CDD],
- &txpwr->mcs_40_cdd[0], WLC_NUM_RATES_MCS_1_STREAM);
- memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_STBC],
- &txpwr->mcs_40_stbc[0], WLC_NUM_RATES_MCS_1_STREAM);
- memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],
- &txpwr->mcs_40_mimo[0], WLC_NUM_RATES_MCS_2_STREAM);
-
- if (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC)
- mac_enabled = true;
-
- if (mac_enabled)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- wlc_phy_txpower_recalc_target(pi);
- wlc_phy_cal_txpower_recalc_sw(pi);
-
- if (mac_enabled)
- wlapi_enable_mac(pi->sh->physhim);
-}
-
-int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- int i;
-
- if (qdbm > 127)
- return 5;
-
- for (i = 0; i < TXP_NUM_RATES; i++)
- pi->tx_user_target[i] = (u8) qdbm;
-
- pi->txpwroverride = false;
-
- if (pi->sh->up) {
- if (!SCAN_INPROG_PHY(pi)) {
- bool suspend;
-
- suspend =
- (0 ==
- (R_REG(&pi->regs->maccontrol) &
- MCTL_EN_MAC));
-
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- wlc_phy_txpower_recalc_target(pi);
- wlc_phy_cal_txpower_recalc_sw(pi);
-
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
- }
- }
- return 0;
-}
-
-void
-wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint channel, u8 *min_pwr,
- u8 *max_pwr, int txp_rate_idx)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- uint i;
-
- *min_pwr = pi->min_txpower * WLC_TXPWR_DB_FACTOR;
-
- if (ISNPHY(pi)) {
- if (txp_rate_idx < 0)
- txp_rate_idx = TXP_FIRST_CCK;
- wlc_phy_txpower_sromlimit_get_nphy(pi, channel, max_pwr,
- (u8) txp_rate_idx);
-
- } else if ((channel <= CH_MAX_2G_CHANNEL)) {
- if (txp_rate_idx < 0)
- txp_rate_idx = TXP_FIRST_CCK;
- *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
- } else {
-
- *max_pwr = WLC_TXPWR_MAX;
-
- if (txp_rate_idx < 0)
- txp_rate_idx = TXP_FIRST_OFDM;
-
- for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
- if (channel == chan_info_all[i].chan) {
- break;
- }
- }
-
- if (pi->hwtxpwr) {
- *max_pwr = pi->hwtxpwr[i];
- } else {
-
- if ((i >= FIRST_MID_5G_CHAN) && (i <= LAST_MID_5G_CHAN))
- *max_pwr =
- pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
- if ((i >= FIRST_HIGH_5G_CHAN)
- && (i <= LAST_HIGH_5G_CHAN))
- *max_pwr =
- pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
- if ((i >= FIRST_LOW_5G_CHAN) && (i <= LAST_LOW_5G_CHAN))
- *max_pwr =
- pi->tx_srom_max_rate_5g_low[txp_rate_idx];
- }
- }
-}
-
-void
-wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan, u8 *max_txpwr,
- u8 *min_txpwr)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- u8 tx_pwr_max = 0;
- u8 tx_pwr_min = 255;
- u8 max_num_rate;
- u8 maxtxpwr, mintxpwr, rate, pactrl;
-
- pactrl = 0;
-
- max_num_rate = ISNPHY(pi) ? TXP_NUM_RATES :
- ISLCNPHY(pi) ? (TXP_LAST_SISO_MCS_20 + 1) : (TXP_LAST_OFDM + 1);
-
- for (rate = 0; rate < max_num_rate; rate++) {
-
- wlc_phy_txpower_sromlimit(ppi, chan, &mintxpwr, &maxtxpwr,
- rate);
-
- maxtxpwr = (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
-
- maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
-
- tx_pwr_max = max(tx_pwr_max, maxtxpwr);
- tx_pwr_min = min(tx_pwr_min, maxtxpwr);
- }
- *max_txpwr = tx_pwr_max;
- *min_txpwr = tx_pwr_min;
-}
-
-void
-wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint bandunit, s32 *max_pwr,
- s32 *min_pwr, u32 *step_pwr)
-{
- return;
-}
-
-u8 wlc_phy_txpower_get_target_min(wlc_phy_t *ppi)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- return pi->tx_power_min;
-}
-
-u8 wlc_phy_txpower_get_target_max(wlc_phy_t *ppi)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- return pi->tx_power_max;
-}
-
-void wlc_phy_txpower_recalc_target(phy_info_t *pi)
-{
- u8 maxtxpwr, mintxpwr, rate, pactrl;
- uint target_chan;
- u8 tx_pwr_target[TXP_NUM_RATES];
- u8 tx_pwr_max = 0;
- u8 tx_pwr_min = 255;
- u8 tx_pwr_max_rate_ind = 0;
- u8 max_num_rate;
- u8 start_rate = 0;
- chanspec_t chspec;
- u32 band = CHSPEC2WLC_BAND(pi->radio_chanspec);
- initfn_t txpwr_recalc_fn = NULL;
-
- chspec = pi->radio_chanspec;
- if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_NONE)
- target_chan = CHSPEC_CHANNEL(chspec);
- else if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER)
- target_chan = UPPER_20_SB(CHSPEC_CHANNEL(chspec));
- else
- target_chan = LOWER_20_SB(CHSPEC_CHANNEL(chspec));
-
- pactrl = 0;
- if (ISLCNPHY(pi)) {
- u32 offset_mcs, i;
-
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- offset_mcs = pi->mcs40_po;
- for (i = TXP_FIRST_SISO_MCS_20;
- i <= TXP_LAST_SISO_MCS_20; i++) {
- pi->tx_srom_max_rate_2g[i - 8] =
- pi->tx_srom_max_2g -
- ((offset_mcs & 0xf) * 2);
- offset_mcs >>= 4;
- }
- } else {
- offset_mcs = pi->mcs20_po;
- for (i = TXP_FIRST_SISO_MCS_20;
- i <= TXP_LAST_SISO_MCS_20; i++) {
- pi->tx_srom_max_rate_2g[i - 8] =
- pi->tx_srom_max_2g -
- ((offset_mcs & 0xf) * 2);
- offset_mcs >>= 4;
- }
- }
- }
-#if WL11N
- max_num_rate = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
- ((ISLCNPHY(pi)) ?
- (TXP_LAST_SISO_MCS_20 + 1) : (TXP_LAST_OFDM + 1)));
-#else
- max_num_rate = ((ISNPHY(pi)) ? (TXP_NUM_RATES) : (TXP_LAST_OFDM + 1));
-#endif
-
- wlc_phy_upd_env_txpwr_rate_limits(pi, band);
-
- for (rate = start_rate; rate < max_num_rate; rate++) {
-
- tx_pwr_target[rate] = pi->tx_user_target[rate];
-
- if (pi->user_txpwr_at_rfport) {
- tx_pwr_target[rate] +=
- wlc_user_txpwr_antport_to_rfport(pi, target_chan,
- band, rate);
- }
-
- {
-
- wlc_phy_txpower_sromlimit((wlc_phy_t *) pi, target_chan,
- &mintxpwr, &maxtxpwr, rate);
-
- maxtxpwr = min(maxtxpwr, pi->txpwr_limit[rate]);
-
- maxtxpwr =
- (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
-
- maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
-
- maxtxpwr = min(maxtxpwr, tx_pwr_target[rate]);
-
- if (pi->txpwr_percent <= 100)
- maxtxpwr = (maxtxpwr * pi->txpwr_percent) / 100;
-
- tx_pwr_target[rate] = max(maxtxpwr, mintxpwr);
- }
-
- tx_pwr_target[rate] =
- min(tx_pwr_target[rate], pi->txpwr_env_limit[rate]);
-
- if (tx_pwr_target[rate] > tx_pwr_max)
- tx_pwr_max_rate_ind = rate;
-
- tx_pwr_max = max(tx_pwr_max, tx_pwr_target[rate]);
- tx_pwr_min = min(tx_pwr_min, tx_pwr_target[rate]);
- }
-
- memset(pi->tx_power_offset, 0, sizeof(pi->tx_power_offset));
- pi->tx_power_max = tx_pwr_max;
- pi->tx_power_min = tx_pwr_min;
- pi->tx_power_max_rate_ind = tx_pwr_max_rate_ind;
- for (rate = 0; rate < max_num_rate; rate++) {
-
- pi->tx_power_target[rate] = tx_pwr_target[rate];
-
- if (!pi->hwpwrctrl || ISNPHY(pi)) {
- pi->tx_power_offset[rate] =
- pi->tx_power_max - pi->tx_power_target[rate];
- } else {
- pi->tx_power_offset[rate] =
- pi->tx_power_target[rate] - pi->tx_power_min;
- }
- }
-
- txpwr_recalc_fn = pi->pi_fptr.txpwrrecalc;
- if (txpwr_recalc_fn)
- (*txpwr_recalc_fn) (pi);
-}
-
-void
-wlc_phy_txpower_reg_limit_calc(phy_info_t *pi, struct txpwr_limits *txpwr,
- chanspec_t chanspec)
-{
- u8 tmp_txpwr_limit[2 * WLC_NUM_RATES_OFDM];
- u8 *txpwr_ptr1 = NULL, *txpwr_ptr2 = NULL;
- int rate_start_index = 0, rate1, rate2, k;
-
- for (rate1 = WL_TX_POWER_CCK_FIRST, rate2 = 0;
- rate2 < WL_TX_POWER_CCK_NUM; rate1++, rate2++)
- pi->txpwr_limit[rate1] = txpwr->cck[rate2];
-
- for (rate1 = WL_TX_POWER_OFDM_FIRST, rate2 = 0;
- rate2 < WL_TX_POWER_OFDM_NUM; rate1++, rate2++)
- pi->txpwr_limit[rate1] = txpwr->ofdm[rate2];
-
- if (ISNPHY(pi)) {
-
- for (k = 0; k < 4; k++) {
- switch (k) {
- case 0:
-
- txpwr_ptr1 = txpwr->mcs_20_siso;
- txpwr_ptr2 = txpwr->ofdm;
- rate_start_index = WL_TX_POWER_OFDM_FIRST;
- break;
- case 1:
-
- txpwr_ptr1 = txpwr->mcs_20_cdd;
- txpwr_ptr2 = txpwr->ofdm_cdd;
- rate_start_index = WL_TX_POWER_OFDM20_CDD_FIRST;
- break;
- case 2:
-
- txpwr_ptr1 = txpwr->mcs_40_siso;
- txpwr_ptr2 = txpwr->ofdm_40_siso;
- rate_start_index =
- WL_TX_POWER_OFDM40_SISO_FIRST;
- break;
- case 3:
-
- txpwr_ptr1 = txpwr->mcs_40_cdd;
- txpwr_ptr2 = txpwr->ofdm_40_cdd;
- rate_start_index = WL_TX_POWER_OFDM40_CDD_FIRST;
- break;
- }
-
- for (rate2 = 0; rate2 < WLC_NUM_RATES_OFDM; rate2++) {
- tmp_txpwr_limit[rate2] = 0;
- tmp_txpwr_limit[WLC_NUM_RATES_OFDM + rate2] =
- txpwr_ptr1[rate2];
- }
- wlc_phy_mcs_to_ofdm_powers_nphy(tmp_txpwr_limit, 0,
- WLC_NUM_RATES_OFDM - 1,
- WLC_NUM_RATES_OFDM);
- for (rate1 = rate_start_index, rate2 = 0;
- rate2 < WLC_NUM_RATES_OFDM; rate1++, rate2++)
- pi->txpwr_limit[rate1] =
- min(txpwr_ptr2[rate2],
- tmp_txpwr_limit[rate2]);
- }
-
- for (k = 0; k < 4; k++) {
- switch (k) {
- case 0:
-
- txpwr_ptr1 = txpwr->ofdm;
- txpwr_ptr2 = txpwr->mcs_20_siso;
- rate_start_index = WL_TX_POWER_MCS20_SISO_FIRST;
- break;
- case 1:
-
- txpwr_ptr1 = txpwr->ofdm_cdd;
- txpwr_ptr2 = txpwr->mcs_20_cdd;
- rate_start_index = WL_TX_POWER_MCS20_CDD_FIRST;
- break;
- case 2:
-
- txpwr_ptr1 = txpwr->ofdm_40_siso;
- txpwr_ptr2 = txpwr->mcs_40_siso;
- rate_start_index = WL_TX_POWER_MCS40_SISO_FIRST;
- break;
- case 3:
-
- txpwr_ptr1 = txpwr->ofdm_40_cdd;
- txpwr_ptr2 = txpwr->mcs_40_cdd;
- rate_start_index = WL_TX_POWER_MCS40_CDD_FIRST;
- break;
- }
- for (rate2 = 0; rate2 < WLC_NUM_RATES_OFDM; rate2++) {
- tmp_txpwr_limit[rate2] = 0;
- tmp_txpwr_limit[WLC_NUM_RATES_OFDM + rate2] =
- txpwr_ptr1[rate2];
- }
- wlc_phy_ofdm_to_mcs_powers_nphy(tmp_txpwr_limit, 0,
- WLC_NUM_RATES_OFDM - 1,
- WLC_NUM_RATES_OFDM);
- for (rate1 = rate_start_index, rate2 = 0;
- rate2 < WLC_NUM_RATES_MCS_1_STREAM;
- rate1++, rate2++)
- pi->txpwr_limit[rate1] =
- min(txpwr_ptr2[rate2],
- tmp_txpwr_limit[rate2]);
- }
-
- for (k = 0; k < 2; k++) {
- switch (k) {
- case 0:
-
- rate_start_index = WL_TX_POWER_MCS20_STBC_FIRST;
- txpwr_ptr1 = txpwr->mcs_20_stbc;
- break;
- case 1:
-
- rate_start_index = WL_TX_POWER_MCS40_STBC_FIRST;
- txpwr_ptr1 = txpwr->mcs_40_stbc;
- break;
- }
- for (rate1 = rate_start_index, rate2 = 0;
- rate2 < WLC_NUM_RATES_MCS_1_STREAM;
- rate1++, rate2++)
- pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
- }
-
- for (k = 0; k < 2; k++) {
- switch (k) {
- case 0:
-
- rate_start_index = WL_TX_POWER_MCS20_SDM_FIRST;
- txpwr_ptr1 = txpwr->mcs_20_mimo;
- break;
- case 1:
-
- rate_start_index = WL_TX_POWER_MCS40_SDM_FIRST;
- txpwr_ptr1 = txpwr->mcs_40_mimo;
- break;
- }
- for (rate1 = rate_start_index, rate2 = 0;
- rate2 < WLC_NUM_RATES_MCS_2_STREAM;
- rate1++, rate2++)
- pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
- }
-
- pi->txpwr_limit[WL_TX_POWER_MCS_32] = txpwr->mcs32;
-
- pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST] =
- min(pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST],
- pi->txpwr_limit[WL_TX_POWER_MCS_32]);
- pi->txpwr_limit[WL_TX_POWER_MCS_32] =
- pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST];
- }
-}
-
-void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- pi->txpwr_percent = txpwr_percent;
-}
-
-void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- pi->sh->machwcap = machwcap;
-}
-
-void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- u16 rxc;
- rxc = 0;
-
- if (start_end == ON) {
- if (!ISNPHY(pi))
- return;
-
- if (NREV_IS(pi->pubpi.phy_rev, 3)
- || NREV_IS(pi->pubpi.phy_rev, 4)) {
- W_REG(&pi->regs->phyregaddr, 0xa0);
- (void)R_REG(&pi->regs->phyregaddr);
- rxc = R_REG(&pi->regs->phyregdata);
- W_REG(&pi->regs->phyregdata,
- (0x1 << 15) | rxc);
- }
- } else {
- if (NREV_IS(pi->pubpi.phy_rev, 3)
- || NREV_IS(pi->pubpi.phy_rev, 4)) {
- W_REG(&pi->regs->phyregaddr, 0xa0);
- (void)R_REG(&pi->regs->phyregaddr);
- W_REG(&pi->regs->phyregdata, rxc);
- }
-
- wlc_phy_por_inform(ppi);
- }
-}
-
-void
-wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *txpwr,
- chanspec_t chanspec)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- wlc_phy_txpower_reg_limit_calc(pi, txpwr, chanspec);
-
- if (ISLCNPHY(pi)) {
- int i, j;
- for (i = TXP_FIRST_OFDM_20_CDD, j = 0;
- j < WLC_NUM_RATES_MCS_1_STREAM; i++, j++) {
- if (txpwr->mcs_20_siso[j])
- pi->txpwr_limit[i] = txpwr->mcs_20_siso[j];
- else
- pi->txpwr_limit[i] = txpwr->ofdm[j];
- }
- }
-
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- wlc_phy_txpower_recalc_target(pi);
- wlc_phy_cal_txpower_recalc_sw(pi);
- wlapi_enable_mac(pi->sh->physhim);
-}
-
-void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- pi->ofdm_rateset_war = war;
-}
-
-void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- pi->bf_preempt_4306 = bf_preempt;
-}
-
-void wlc_phy_txpower_update_shm(phy_info_t *pi)
-{
- int j;
- if (ISNPHY(pi)) {
- return;
- }
-
- if (!pi->sh->clk)
- return;
-
- if (pi->hwpwrctrl) {
- u16 offset;
-
- wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63);
- wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N,
- 1 << NUM_TSSI_FRAMES);
-
- wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_TARGET,
- pi->tx_power_min << NUM_TSSI_FRAMES);
-
- wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_CUR,
- pi->hwpwr_txcur);
-
- for (j = TXP_FIRST_OFDM; j <= TXP_LAST_OFDM; j++) {
- const u8 ucode_ofdm_rates[] = {
- 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c
- };
- offset = wlapi_bmac_rate_shm_offset(pi->sh->physhim,
- ucode_ofdm_rates[j -
- TXP_FIRST_OFDM]);
- wlapi_bmac_write_shm(pi->sh->physhim, offset + 6,
- pi->tx_power_offset[j]);
- wlapi_bmac_write_shm(pi->sh->physhim, offset + 14,
- -(pi->tx_power_offset[j] / 2));
- }
-
- wlapi_bmac_mhf(pi->sh->physhim, MHF2, MHF2_HWPWRCTL,
- MHF2_HWPWRCTL, WLC_BAND_ALL);
- } else {
- int i;
-
- for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++)
- pi->tx_power_offset[i] =
- (u8) roundup(pi->tx_power_offset[i], 8);
- wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET,
- (u16) ((pi->
- tx_power_offset[TXP_FIRST_OFDM]
- + 7) >> 3));
- }
-}
-
-bool wlc_phy_txpower_hw_ctrl_get(wlc_phy_t *ppi)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- if (ISNPHY(pi)) {
- return pi->nphy_txpwrctrl;
- } else {
- return pi->hwpwrctrl;
- }
-}
-
-void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- bool cur_hwpwrctrl = pi->hwpwrctrl;
- bool suspend;
-
- if (!pi->hwpwrctrl_capable) {
- return;
- }
-
- pi->hwpwrctrl = hwpwrctrl;
- pi->nphy_txpwrctrl = hwpwrctrl;
- pi->txpwrctrl = hwpwrctrl;
-
- if (ISNPHY(pi)) {
- suspend =
- (0 ==
- (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
- if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
- wlc_phy_txpwr_fixpower_nphy(pi);
- } else {
-
- mod_phy_reg(pi, 0x1e7, (0x7f << 0),
- pi->saved_txpwr_idx);
- }
-
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
- } else if (hwpwrctrl != cur_hwpwrctrl) {
-
- return;
- }
-}
-
-void wlc_phy_txpower_ipa_upd(phy_info_t *pi)
-{
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- pi->ipa2g_on = (pi->srom_fem2g.extpagain == 2);
- pi->ipa5g_on = (pi->srom_fem5g.extpagain == 2);
- } else {
- pi->ipa2g_on = false;
- pi->ipa5g_on = false;
- }
-}
-
-static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi);
-
-static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
-{
- s16 tx0_status, tx1_status;
- u16 estPower1, estPower2;
- u8 pwr0, pwr1, adj_pwr0, adj_pwr1;
- u32 est_pwr;
-
- estPower1 = read_phy_reg(pi, 0x118);
- estPower2 = read_phy_reg(pi, 0x119);
-
- if ((estPower1 & (0x1 << 8))
- == (0x1 << 8)) {
- pwr0 = (u8) (estPower1 & (0xff << 0))
- >> 0;
- } else {
- pwr0 = 0x80;
- }
-
- if ((estPower2 & (0x1 << 8))
- == (0x1 << 8)) {
- pwr1 = (u8) (estPower2 & (0xff << 0))
- >> 0;
- } else {
- pwr1 = 0x80;
- }
-
- tx0_status = read_phy_reg(pi, 0x1ed);
- tx1_status = read_phy_reg(pi, 0x1ee);
-
- if ((tx0_status & (0x1 << 15))
- == (0x1 << 15)) {
- adj_pwr0 = (u8) (tx0_status & (0xff << 0))
- >> 0;
- } else {
- adj_pwr0 = 0x80;
- }
- if ((tx1_status & (0x1 << 15))
- == (0x1 << 15)) {
- adj_pwr1 = (u8) (tx1_status & (0xff << 0))
- >> 0;
- } else {
- adj_pwr1 = 0x80;
- }
-
- est_pwr =
- (u32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) | adj_pwr1);
- return est_pwr;
-}
-
-void
-wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power, uint channel)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- uint rate, num_rates;
- u8 min_pwr, max_pwr;
-
-#if WL_TX_POWER_RATES != TXP_NUM_RATES
-#error "tx_power_t struct out of sync with this fn"
-#endif
-
- if (ISNPHY(pi)) {
- power->rf_cores = 2;
- power->flags |= (WL_TX_POWER_F_MIMO);
- if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
- power->flags |=
- (WL_TX_POWER_F_ENABLED | WL_TX_POWER_F_HW);
- } else if (ISLCNPHY(pi)) {
- power->rf_cores = 1;
- power->flags |= (WL_TX_POWER_F_SISO);
- if (pi->radiopwr_override == RADIOPWR_OVERRIDE_DEF)
- power->flags |= WL_TX_POWER_F_ENABLED;
- if (pi->hwpwrctrl)
- power->flags |= WL_TX_POWER_F_HW;
- }
-
- num_rates = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
- ((ISLCNPHY(pi)) ?
- (TXP_LAST_OFDM_20_CDD + 1) : (TXP_LAST_OFDM + 1)));
-
- for (rate = 0; rate < num_rates; rate++) {
- power->user_limit[rate] = pi->tx_user_target[rate];
- wlc_phy_txpower_sromlimit(ppi, channel, &min_pwr, &max_pwr,
- rate);
- power->board_limit[rate] = (u8) max_pwr;
- power->target[rate] = pi->tx_power_target[rate];
- }
-
- if (ISNPHY(pi)) {
- u32 est_pout;
-
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- wlc_phyreg_enter((wlc_phy_t *) pi);
- est_pout = wlc_phy_txpower_est_power_nphy(pi);
- wlc_phyreg_exit((wlc_phy_t *) pi);
- wlapi_enable_mac(pi->sh->physhim);
-
- power->est_Pout[0] = (est_pout >> 8) & 0xff;
- power->est_Pout[1] = est_pout & 0xff;
-
- power->est_Pout_act[0] = est_pout >> 24;
- power->est_Pout_act[1] = (est_pout >> 16) & 0xff;
-
- if (power->est_Pout[0] == 0x80)
- power->est_Pout[0] = 0;
- if (power->est_Pout[1] == 0x80)
- power->est_Pout[1] = 0;
-
- if (power->est_Pout_act[0] == 0x80)
- power->est_Pout_act[0] = 0;
- if (power->est_Pout_act[1] == 0x80)
- power->est_Pout_act[1] = 0;
-
- power->est_Pout_cck = 0;
-
- power->tx_power_max[0] = pi->tx_power_max;
- power->tx_power_max[1] = pi->tx_power_max;
-
- power->tx_power_max_rate_ind[0] = pi->tx_power_max_rate_ind;
- power->tx_power_max_rate_ind[1] = pi->tx_power_max_rate_ind;
- } else if (!pi->hwpwrctrl) {
- } else if (pi->sh->up) {
-
- wlc_phyreg_enter(ppi);
- if (ISLCNPHY(pi)) {
-
- power->tx_power_max[0] = pi->tx_power_max;
- power->tx_power_max[1] = pi->tx_power_max;
-
- power->tx_power_max_rate_ind[0] =
- pi->tx_power_max_rate_ind;
- power->tx_power_max_rate_ind[1] =
- pi->tx_power_max_rate_ind;
-
- if (wlc_phy_tpc_isenabled_lcnphy(pi))
- power->flags |=
- (WL_TX_POWER_F_HW | WL_TX_POWER_F_ENABLED);
- else
- power->flags &=
- ~(WL_TX_POWER_F_HW | WL_TX_POWER_F_ENABLED);
-
- wlc_lcnphy_get_tssi(pi, (s8 *) &power->est_Pout[0],
- (s8 *) &power->est_Pout_cck);
- }
- wlc_phyreg_exit(ppi);
- }
-}
-
-void wlc_phy_antsel_type_set(wlc_phy_t *ppi, u8 antsel_type)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- pi->antsel_type = antsel_type;
-}
-
-bool wlc_phy_test_ison(wlc_phy_t *ppi)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- return pi->phytest_on;
-}
-
-void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- bool suspend;
-
- pi->sh->rx_antdiv = val;
-
- if (!(ISNPHY(pi) && D11REV_IS(pi->sh->corerev, 16))) {
- if (val > ANT_RX_DIV_FORCE_1)
- wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV,
- MHF1_ANTDIV, WLC_BAND_ALL);
- else
- wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV, 0,
- WLC_BAND_ALL);
- }
-
- if (ISNPHY(pi)) {
-
- return;
- }
-
- if (!pi->sh->clk)
- return;
-
- suspend =
- (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- if (ISLCNPHY(pi)) {
- if (val > ANT_RX_DIV_FORCE_1) {
- mod_phy_reg(pi, 0x410, (0x1 << 1), 0x01 << 1);
- mod_phy_reg(pi, 0x410,
- (0x1 << 0),
- ((ANT_RX_DIV_START_1 == val) ? 1 : 0) << 0);
- } else {
- mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1);
- mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0);
- }
- }
-
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
-
- return;
-}
-
-static bool
-wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr, s8 *pwr_ant)
-{
- s8 cmplx_pwr_dbm[PHY_CORE_MAX];
- u8 i;
-
- memset((u8 *) cmplx_pwr_dbm, 0, sizeof(cmplx_pwr_dbm));
- wlc_phy_compute_dB(cmplx_pwr, cmplx_pwr_dbm, pi->pubpi.phy_corenum);
-
- for (i = 0; i < pi->pubpi.phy_corenum; i++) {
- if (NREV_GE(pi->pubpi.phy_rev, 3))
- cmplx_pwr_dbm[i] += (s8) PHY_NOISE_OFFSETFACT_4322;
- else
-
- cmplx_pwr_dbm[i] += (s8) (16 - (15) * 3 - 70);
- }
-
- for (i = 0; i < pi->pubpi.phy_corenum; i++) {
- pi->nphy_noise_win[i][pi->nphy_noise_index] = cmplx_pwr_dbm[i];
- pwr_ant[i] = cmplx_pwr_dbm[i];
- }
- pi->nphy_noise_index =
- MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
- return true;
-}
-
-static void
-wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
- bool sampling_in_progress = (pi->phynoise_state != 0);
- bool wait_for_intr = true;
-
- if (NORADIO_ENAB(pi->pubpi)) {
- return;
- }
-
- switch (reason) {
- case PHY_NOISE_SAMPLE_MON:
-
- pi->phynoise_chan_watchdog = ch;
- pi->phynoise_state |= PHY_NOISE_STATE_MON;
-
- break;
-
- case PHY_NOISE_SAMPLE_EXTERNAL:
-
- pi->phynoise_state |= PHY_NOISE_STATE_EXTERNAL;
- break;
-
- default:
- break;
- }
-
- if (sampling_in_progress)
- return;
-
- pi->phynoise_now = pi->sh->now;
-
- if (pi->phy_fixed_noise) {
- if (ISNPHY(pi)) {
- pi->nphy_noise_win[WL_ANT_IDX_1][pi->nphy_noise_index] =
- PHY_NOISE_FIXED_VAL_NPHY;
- pi->nphy_noise_win[WL_ANT_IDX_2][pi->nphy_noise_index] =
- PHY_NOISE_FIXED_VAL_NPHY;
- pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
- PHY_NOISE_WINDOW_SZ);
-
- noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
- } else {
-
- noise_dbm = PHY_NOISE_FIXED_VAL;
- }
-
- wait_for_intr = false;
- goto done;
- }
-
- if (ISLCNPHY(pi)) {
- if (!pi->phynoise_polling
- || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
- wlapi_bmac_write_shm(pi->sh->physhim, M_JSSI_0, 0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
-
- OR_REG(&pi->regs->maccommand,
- MCMD_BG_NOISE);
- } else {
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- wlc_lcnphy_deaf_mode(pi, (bool) 0);
- noise_dbm = (s8) wlc_lcnphy_rx_signal_power(pi, 20);
- wlc_lcnphy_deaf_mode(pi, (bool) 1);
- wlapi_enable_mac(pi->sh->physhim);
- wait_for_intr = false;
- }
- } else if (ISNPHY(pi)) {
- if (!pi->phynoise_polling
- || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
-
- wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
-
- OR_REG(&pi->regs->maccommand,
- MCMD_BG_NOISE);
- } else {
- phy_iq_est_t est[PHY_CORE_MAX];
- u32 cmplx_pwr[PHY_CORE_MAX];
- s8 noise_dbm_ant[PHY_CORE_MAX];
- u16 log_num_samps, num_samps, classif_state = 0;
- u8 wait_time = 32;
- u8 wait_crs = 0;
- u8 i;
-
- memset((u8 *) est, 0, sizeof(est));
- memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
- memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
-
- log_num_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
- num_samps = 1 << log_num_samps;
-
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
- wlc_phy_classifier_nphy(pi, 3, 0);
- wlc_phy_rx_iq_est_nphy(pi, est, num_samps, wait_time,
- wait_crs);
- wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
- wlapi_enable_mac(pi->sh->physhim);
-
- for (i = 0; i < pi->pubpi.phy_corenum; i++)
- cmplx_pwr[i] =
- (est[i].i_pwr +
- est[i].q_pwr) >> log_num_samps;
-
- wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
-
- for (i = 0; i < pi->pubpi.phy_corenum; i++) {
- pi->nphy_noise_win[i][pi->nphy_noise_index] =
- noise_dbm_ant[i];
-
- if (noise_dbm_ant[i] > noise_dbm)
- noise_dbm = noise_dbm_ant[i];
- }
- pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
- PHY_NOISE_WINDOW_SZ);
-
- wait_for_intr = false;
- }
- }
-
- done:
-
- if (!wait_for_intr)
- wlc_phy_noise_cb(pi, ch, noise_dbm);
-
-}
-
-void wlc_phy_noise_sample_request_external(wlc_phy_t *pih)
-{
- u8 channel;
-
- channel = CHSPEC_CHANNEL(wlc_phy_chanspec_get(pih));
-
- wlc_phy_noise_sample_request(pih, PHY_NOISE_SAMPLE_EXTERNAL, channel);
-}
-
-static void wlc_phy_noise_cb(phy_info_t *pi, u8 channel, s8 noise_dbm)
-{
- if (!pi->phynoise_state)
- return;
-
- if (pi->phynoise_state & PHY_NOISE_STATE_MON) {
- if (pi->phynoise_chan_watchdog == channel) {
- pi->sh->phy_noise_window[pi->sh->phy_noise_index] =
- noise_dbm;
- pi->sh->phy_noise_index =
- MODINC(pi->sh->phy_noise_index, MA_WINDOW_SZ);
- }
- pi->phynoise_state &= ~PHY_NOISE_STATE_MON;
- }
-
- if (pi->phynoise_state & PHY_NOISE_STATE_EXTERNAL) {
- pi->phynoise_state &= ~PHY_NOISE_STATE_EXTERNAL;
- }
-
-}
-
-static s8 wlc_phy_noise_read_shmem(phy_info_t *pi)
-{
- u32 cmplx_pwr[PHY_CORE_MAX];
- s8 noise_dbm_ant[PHY_CORE_MAX];
- u16 lo, hi;
- u32 cmplx_pwr_tot = 0;
- s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
- u8 idx, core;
-
- memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
- memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
-
- for (idx = 0, core = 0; core < pi->pubpi.phy_corenum; idx += 2, core++) {
- lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP(idx));
- hi = wlapi_bmac_read_shm(pi->sh->physhim,
- M_PWRIND_MAP(idx + 1));
- cmplx_pwr[core] = (hi << 16) + lo;
- cmplx_pwr_tot += cmplx_pwr[core];
- if (cmplx_pwr[core] == 0) {
- noise_dbm_ant[core] = PHY_NOISE_FIXED_VAL_NPHY;
- } else
- cmplx_pwr[core] >>= PHY_NOISE_SAMPLE_LOG_NUM_UCODE;
- }
-
- if (cmplx_pwr_tot != 0)
- wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- pi->nphy_noise_win[core][pi->nphy_noise_index] =
- noise_dbm_ant[core];
-
- if (noise_dbm_ant[core] > noise_dbm)
- noise_dbm = noise_dbm_ant[core];
- }
- pi->nphy_noise_index =
- MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
-
- return noise_dbm;
-
-}
-
-void wlc_phy_noise_sample_intr(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- u16 jssi_aux;
- u8 channel = 0;
- s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
-
- if (ISLCNPHY(pi)) {
- u32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
- u16 lo, hi;
- s32 pwr_offset_dB, gain_dB;
- u16 status_0, status_1;
-
- jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
- channel = jssi_aux & D11_CURCHANNEL_MAX;
-
- lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP0);
- hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP1);
- cmplx_pwr0 = (hi << 16) + lo;
-
- lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP2);
- hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP3);
- cmplx_pwr1 = (hi << 16) + lo;
- cmplx_pwr = (cmplx_pwr0 + cmplx_pwr1) >> 6;
-
- status_0 = 0x44;
- status_1 = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_0);
- if ((cmplx_pwr > 0 && cmplx_pwr < 500)
- && ((status_1 & 0xc000) == 0x4000)) {
-
- wlc_phy_compute_dB(&cmplx_pwr, &noise_dbm,
- pi->pubpi.phy_corenum);
- pwr_offset_dB = (read_phy_reg(pi, 0x434) & 0xFF);
- if (pwr_offset_dB > 127)
- pwr_offset_dB -= 256;
-
- noise_dbm += (s8) (pwr_offset_dB - 30);
-
- gain_dB = (status_0 & 0x1ff);
- noise_dbm -= (s8) (gain_dB);
- } else {
- noise_dbm = PHY_NOISE_FIXED_VAL_LCNPHY;
- }
- } else if (ISNPHY(pi)) {
-
- jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
- channel = jssi_aux & D11_CURCHANNEL_MAX;
-
- noise_dbm = wlc_phy_noise_read_shmem(pi);
- }
-
- wlc_phy_noise_cb(pi, channel, noise_dbm);
-
-}
-
-s8 lcnphy_gain_index_offset_for_pkt_rssi[] = {
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 8,
- 9,
- 10,
- 8,
- 8,
- 7,
- 7,
- 1,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 1,
- 1,
- 0,
- 0,
- 0,
- 0
-};
-
-void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
-{
- u8 msb, secondmsb, i;
- u32 tmp;
-
- for (i = 0; i < core; i++) {
- secondmsb = 0;
- tmp = cmplx_pwr[i];
- msb = fls(tmp);
- if (msb)
- secondmsb = (u8) ((tmp >> (--msb - 1)) & 1);
- p_cmplx_pwr_dB[i] = (s8) (3 * msb + 2 * secondmsb);
- }
-}
-
-void wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx)
-{
- wlc_d11rxhdr_t *wlc_rxhdr = (wlc_d11rxhdr_t *) ctx;
- d11rxhdr_t *rxh = &wlc_rxhdr->rxhdr;
- int rssi = le16_to_cpu(rxh->PhyRxStatus_1) & PRXS1_JSSI_MASK;
- uint radioid = pih->radioid;
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (NORADIO_ENAB(pi->pubpi)) {
- rssi = WLC_RSSI_INVALID;
- goto end;
- }
-
- if ((pi->sh->corerev >= 11)
- && !(le16_to_cpu(rxh->RxStatus2) & RXS_PHYRXST_VALID)) {
- rssi = WLC_RSSI_INVALID;
- goto end;
- }
-
- if (ISLCNPHY(pi)) {
- u8 gidx = (le16_to_cpu(rxh->PhyRxStatus_2) & 0xFC00) >> 10;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (rssi > 127)
- rssi -= 256;
-
- rssi = rssi + lcnphy_gain_index_offset_for_pkt_rssi[gidx];
- if ((rssi > -46) && (gidx > 18))
- rssi = rssi + 7;
-
- rssi = rssi + pi_lcn->lcnphy_pkteng_rssi_slope;
-
- rssi = rssi + 2;
-
- }
-
- if (ISLCNPHY(pi)) {
-
- if (rssi > 127)
- rssi -= 256;
- } else if (radioid == BCM2055_ID || radioid == BCM2056_ID
- || radioid == BCM2057_ID) {
- rssi = wlc_phy_rssi_compute_nphy(pi, wlc_rxhdr);
- }
-
- end:
- wlc_rxhdr->rssi = (s8) rssi;
-}
-
-void wlc_phy_freqtrack_start(wlc_phy_t *pih)
-{
- return;
-}
-
-void wlc_phy_freqtrack_end(wlc_phy_t *pih)
-{
- return;
-}
-
-void wlc_phy_set_deaf(wlc_phy_t *ppi, bool user_flag)
-{
- phy_info_t *pi;
- pi = (phy_info_t *) ppi;
-
- if (ISLCNPHY(pi))
- wlc_lcnphy_deaf_mode(pi, true);
- else if (ISNPHY(pi))
- wlc_nphy_deaf_mode(pi, true);
-}
-
-void wlc_phy_watchdog(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- bool delay_phy_cal = false;
- pi->sh->now++;
-
- if (!pi->watchdog_override)
- return;
-
- if (!(SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi))) {
- wlc_phy_noise_sample_request((wlc_phy_t *) pi,
- PHY_NOISE_SAMPLE_MON,
- CHSPEC_CHANNEL(pi->
- radio_chanspec));
- }
-
- if (pi->phynoise_state && (pi->sh->now - pi->phynoise_now) > 5) {
- pi->phynoise_state = 0;
- }
-
- if ((!pi->phycal_txpower) ||
- ((pi->sh->now - pi->phycal_txpower) >= pi->sh->fast_timer)) {
-
- if (!SCAN_INPROG_PHY(pi) && wlc_phy_cal_txpower_recalc_sw(pi)) {
- pi->phycal_txpower = pi->sh->now;
- }
- }
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- if ((SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
- || ASSOC_INPROG_PHY(pi)))
- return;
-
- if (ISNPHY(pi) && !pi->disable_percal && !delay_phy_cal) {
-
- if ((pi->nphy_perical != PHY_PERICAL_DISABLE) &&
- (pi->nphy_perical != PHY_PERICAL_MANUAL) &&
- ((pi->sh->now - pi->nphy_perical_last) >=
- pi->sh->glacial_timer))
- wlc_phy_cal_perical((wlc_phy_t *) pi,
- PHY_PERICAL_WATCHDOG);
-
- wlc_phy_txpwr_papd_cal_nphy(pi);
- }
-
- if (ISLCNPHY(pi)) {
- if (pi->phy_forcecal ||
- ((pi->sh->now - pi->phy_lastcal) >=
- pi->sh->glacial_timer)) {
- if (!(SCAN_RM_IN_PROGRESS(pi) || ASSOC_INPROG_PHY(pi)))
- wlc_lcnphy_calib_modes(pi,
- LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
- if (!
- (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
- || ASSOC_INPROG_PHY(pi)
- || pi->carrier_suppr_disable
- || pi->disable_percal))
- wlc_lcnphy_calib_modes(pi,
- PHY_PERICAL_WATCHDOG);
- }
- }
-}
-
-void wlc_phy_BSSinit(wlc_phy_t *pih, bool bonlyap, int rssi)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- uint i;
- uint k;
-
- for (i = 0; i < MA_WINDOW_SZ; i++) {
- pi->sh->phy_noise_window[i] = (s8) (rssi & 0xff);
- }
- if (ISLCNPHY(pi)) {
- for (i = 0; i < MA_WINDOW_SZ; i++)
- pi->sh->phy_noise_window[i] =
- PHY_NOISE_FIXED_VAL_LCNPHY;
- }
- pi->sh->phy_noise_index = 0;
-
- for (i = 0; i < PHY_NOISE_WINDOW_SZ; i++) {
- for (k = WL_ANT_IDX_1; k < WL_ANT_RX_MAX; k++)
- pi->nphy_noise_win[k][i] = PHY_NOISE_FIXED_VAL_NPHY;
- }
- pi->nphy_noise_index = 0;
-}
-
-void
-wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag)
-{
- *eps_imag = (epsilon >> 13);
- if (*eps_imag > 0xfff)
- *eps_imag -= 0x2000;
-
- *eps_real = (epsilon & 0x1fff);
- if (*eps_real > 0xfff)
- *eps_real -= 0x2000;
-}
-
-static const fixed AtanTbl[] = {
- 2949120,
- 1740967,
- 919879,
- 466945,
- 234379,
- 117304,
- 58666,
- 29335,
- 14668,
- 7334,
- 3667,
- 1833,
- 917,
- 458,
- 229,
- 115,
- 57,
- 29
-};
-
-void wlc_phy_cordic(fixed theta, cs32 *val)
-{
- fixed angle, valtmp;
- unsigned iter;
- int signx = 1;
- int signtheta;
-
- val[0].i = CORDIC_AG;
- val[0].q = 0;
- angle = 0;
-
- signtheta = (theta < 0) ? -1 : 1;
- theta =
- ((theta + FIXED(180) * signtheta) % FIXED(360)) -
- FIXED(180) * signtheta;
-
- if (FLOAT(theta) > 90) {
- theta -= FIXED(180);
- signx = -1;
- } else if (FLOAT(theta) < -90) {
- theta += FIXED(180);
- signx = -1;
- }
-
- for (iter = 0; iter < CORDIC_NI; iter++) {
- if (theta > angle) {
- valtmp = val[0].i - (val[0].q >> iter);
- val[0].q = (val[0].i >> iter) + val[0].q;
- val[0].i = valtmp;
- angle += AtanTbl[iter];
- } else {
- valtmp = val[0].i + (val[0].q >> iter);
- val[0].q = -(val[0].i >> iter) + val[0].q;
- val[0].i = valtmp;
- angle -= AtanTbl[iter];
- }
- }
-
- val[0].i = val[0].i * signx;
- val[0].q = val[0].q * signx;
-}
-
-void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi)
-{
- wlapi_del_timer(pi->sh->physhim, pi->phycal_timer);
-
- pi->cal_type_override = PHY_PERICAL_AUTO;
- pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
- pi->mphase_txcal_cmdidx = 0;
-}
-
-static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay)
-{
-
- if ((pi->nphy_perical != PHY_PERICAL_MPHASE) &&
- (pi->nphy_perical != PHY_PERICAL_MANUAL))
- return;
-
- wlapi_del_timer(pi->sh->physhim, pi->phycal_timer);
-
- pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
- wlapi_add_timer(pi->sh->physhim, pi->phycal_timer, delay, 0);
-}
-
-void wlc_phy_cal_perical(wlc_phy_t *pih, u8 reason)
-{
- s16 nphy_currtemp = 0;
- s16 delta_temp = 0;
- bool do_periodic_cal = true;
- phy_info_t *pi = (phy_info_t *) pih;
-
- if (!ISNPHY(pi))
- return;
-
- if ((pi->nphy_perical == PHY_PERICAL_DISABLE) ||
- (pi->nphy_perical == PHY_PERICAL_MANUAL))
- return;
-
- switch (reason) {
- case PHY_PERICAL_DRIVERUP:
- break;
-
- case PHY_PERICAL_PHYINIT:
- if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
- if (PHY_PERICAL_MPHASE_PENDING(pi)) {
- wlc_phy_cal_perical_mphase_reset(pi);
- }
- wlc_phy_cal_perical_mphase_schedule(pi,
- PHY_PERICAL_INIT_DELAY);
- }
- break;
-
- case PHY_PERICAL_JOIN_BSS:
- case PHY_PERICAL_START_IBSS:
- case PHY_PERICAL_UP_BSS:
- if ((pi->nphy_perical == PHY_PERICAL_MPHASE) &&
- PHY_PERICAL_MPHASE_PENDING(pi)) {
- wlc_phy_cal_perical_mphase_reset(pi);
- }
-
- pi->first_cal_after_assoc = true;
-
- pi->cal_type_override = PHY_PERICAL_FULL;
-
- if (pi->phycal_tempdelta) {
- pi->nphy_lastcal_temp = wlc_phy_tempsense_nphy(pi);
- }
- wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_FULL);
- break;
-
- case PHY_PERICAL_WATCHDOG:
- if (pi->phycal_tempdelta) {
- nphy_currtemp = wlc_phy_tempsense_nphy(pi);
- delta_temp =
- (nphy_currtemp > pi->nphy_lastcal_temp) ?
- nphy_currtemp - pi->nphy_lastcal_temp :
- pi->nphy_lastcal_temp - nphy_currtemp;
-
- if ((delta_temp < (s16) pi->phycal_tempdelta) &&
- (pi->nphy_txiqlocal_chanspec ==
- pi->radio_chanspec)) {
- do_periodic_cal = false;
- } else {
- pi->nphy_lastcal_temp = nphy_currtemp;
- }
- }
-
- if (do_periodic_cal) {
-
- if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
-
- if (!PHY_PERICAL_MPHASE_PENDING(pi))
- wlc_phy_cal_perical_mphase_schedule(pi,
- PHY_PERICAL_WDOG_DELAY);
- } else if (pi->nphy_perical == PHY_PERICAL_SPHASE)
- wlc_phy_cal_perical_nphy_run(pi,
- PHY_PERICAL_AUTO);
- }
- break;
- default:
- break;
- }
-}
-
-void wlc_phy_cal_perical_mphase_restart(phy_info_t *pi)
-{
- pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
- pi->mphase_txcal_cmdidx = 0;
-}
-
-u8 wlc_phy_nbits(s32 value)
-{
- s32 abs_val;
- u8 nbits = 0;
-
- abs_val = ABS(value);
- while ((abs_val >> nbits) > 0)
- nbits++;
-
- return nbits;
-}
-
-void wlc_phy_stf_chain_init(wlc_phy_t *pih, u8 txchain, u8 rxchain)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- pi->sh->hw_phytxchain = txchain;
- pi->sh->hw_phyrxchain = rxchain;
- pi->sh->phytxchain = txchain;
- pi->sh->phyrxchain = rxchain;
- pi->pubpi.phy_corenum = (u8) PHY_BITSCNT(pi->sh->phyrxchain);
-}
-
-void wlc_phy_stf_chain_set(wlc_phy_t *pih, u8 txchain, u8 rxchain)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- pi->sh->phytxchain = txchain;
-
- if (ISNPHY(pi)) {
- wlc_phy_rxcore_setstate_nphy(pih, rxchain);
- }
- pi->pubpi.phy_corenum = (u8) PHY_BITSCNT(pi->sh->phyrxchain);
-}
-
-void wlc_phy_stf_chain_get(wlc_phy_t *pih, u8 *txchain, u8 *rxchain)
-{
- phy_info_t *pi = (phy_info_t *) pih;
-
- *txchain = pi->sh->phytxchain;
- *rxchain = pi->sh->phyrxchain;
-}
-
-u8 wlc_phy_stf_chain_active_get(wlc_phy_t *pih)
-{
- s16 nphy_currtemp;
- u8 active_bitmap;
- phy_info_t *pi = (phy_info_t *) pih;
-
- active_bitmap = (pi->phy_txcore_heatedup) ? 0x31 : 0x33;
-
- if (!pi->watchdog_override)
- return active_bitmap;
-
- if (NREV_GE(pi->pubpi.phy_rev, 6)) {
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- nphy_currtemp = wlc_phy_tempsense_nphy(pi);
- wlapi_enable_mac(pi->sh->physhim);
-
- if (!pi->phy_txcore_heatedup) {
- if (nphy_currtemp >= pi->phy_txcore_disable_temp) {
- active_bitmap &= 0xFD;
- pi->phy_txcore_heatedup = true;
- }
- } else {
- if (nphy_currtemp <= pi->phy_txcore_enable_temp) {
- active_bitmap |= 0x2;
- pi->phy_txcore_heatedup = false;
- }
- }
- }
-
- return active_bitmap;
-}
-
-s8 wlc_phy_stf_ssmode_get(wlc_phy_t *pih, chanspec_t chanspec)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- u8 siso_mcs_id, cdd_mcs_id;
-
- siso_mcs_id =
- (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_SISO :
- TXP_FIRST_MCS_20_SISO;
- cdd_mcs_id =
- (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_CDD :
- TXP_FIRST_MCS_20_CDD;
-
- if (pi->tx_power_target[siso_mcs_id] >
- (pi->tx_power_target[cdd_mcs_id] + 12))
- return PHY_TXC1_MODE_SISO;
- else
- return PHY_TXC1_MODE_CDD;
-}
-
-const u8 *wlc_phy_get_ofdm_rate_lookup(void)
-{
- return ofdm_rate_lookup;
-}
-
-void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode)
-{
- if ((pi->sh->chip == BCM4313_CHIP_ID) &&
- (pi->sh->boardflags & BFL_FEM)) {
- if (mode) {
- u16 txant = 0;
- txant = wlapi_bmac_get_txant(pi->sh->physhim);
- if (txant == 1) {
- mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
-
- mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
-
- }
- ai_corereg(pi->sh->sih, SI_CC_IDX,
- offsetof(chipcregs_t, gpiocontrol), ~0x0,
- 0x0);
- ai_corereg(pi->sh->sih, SI_CC_IDX,
- offsetof(chipcregs_t, gpioout), 0x40, 0x40);
- ai_corereg(pi->sh->sih, SI_CC_IDX,
- offsetof(chipcregs_t, gpioouten), 0x40,
- 0x40);
- } else {
- mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
-
- mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
-
- ai_corereg(pi->sh->sih, SI_CC_IDX,
- offsetof(chipcregs_t, gpioout), 0x40, 0x00);
- ai_corereg(pi->sh->sih, SI_CC_IDX,
- offsetof(chipcregs_t, gpioouten), 0x40, 0x0);
- ai_corereg(pi->sh->sih, SI_CC_IDX,
- offsetof(chipcregs_t, gpiocontrol), ~0x0,
- 0x40);
- }
- }
-}
-
-static s8
-wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, u32 band,
- u8 rate)
-{
- s8 offset = 0;
-
- if (!pi->user_txpwr_at_rfport)
- return offset;
- return offset;
-}
-
-static s8 wlc_phy_env_measure_vbat(phy_info_t *pi)
-{
- if (ISLCNPHY(pi))
- return wlc_lcnphy_vbatsense(pi, 0);
- else
- return 0;
-}
-
-static s8 wlc_phy_env_measure_temperature(phy_info_t *pi)
-{
- if (ISLCNPHY(pi))
- return wlc_lcnphy_tempsense_degree(pi, 0);
- else
- return 0;
-}
-
-static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band)
-{
- u8 i;
- s8 temp, vbat;
-
- for (i = 0; i < TXP_NUM_RATES; i++)
- pi->txpwr_env_limit[i] = WLC_TXPWR_MAX;
-
- vbat = wlc_phy_env_measure_vbat(pi);
- temp = wlc_phy_env_measure_temperature(pi);
-
-}
-
-void wlc_phy_ldpc_override_set(wlc_phy_t *ppi, bool ldpc)
-{
- return;
-}
-
-void
-wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset, s8 *ofdmoffset)
-{
- *cckoffset = 0;
- *ofdmoffset = 0;
-}
-
-s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi, chanspec_t chanspec)
-{
-
- return rssi;
-}
-
-bool wlc_phy_txpower_ipa_ison(wlc_phy_t *ppi)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
-
- if (ISNPHY(pi))
- return wlc_phy_n_txpower_ipa_ison(pi);
- else
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * phy_hal.h: functionality exported from the phy to higher layers
- */
-
-#ifndef _BRCM_PHY_HAL_H_
-#define _BRCM_PHY_HAL_H_
-
-#include <aiutils.h>
-#include <d11.h>
-#include <wlc_phy_shim.h>
-#include <net/mac80211.h> /* struct wiphy */
-#include "brcmu_wifi.h" /* chanspec_t */
-
-#define IDCODE_VER_MASK 0x0000000f
-#define IDCODE_VER_SHIFT 0
-#define IDCODE_MFG_MASK 0x00000fff
-#define IDCODE_MFG_SHIFT 0
-#define IDCODE_ID_MASK 0x0ffff000
-#define IDCODE_ID_SHIFT 12
-#define IDCODE_REV_MASK 0xf0000000
-#define IDCODE_REV_SHIFT 28
-
-#define NORADIO_ID 0xe4f5
-#define NORADIO_IDCODE 0x4e4f5246
-
-#define BCM2055_ID 0x2055
-#define BCM2055_IDCODE 0x02055000
-#define BCM2055A0_IDCODE 0x1205517f
-
-#define BCM2056_ID 0x2056
-#define BCM2056_IDCODE 0x02056000
-#define BCM2056A0_IDCODE 0x1205617f
-
-#define BCM2057_ID 0x2057
-#define BCM2057_IDCODE 0x02057000
-#define BCM2057A0_IDCODE 0x1205717f
-
-#define BCM2064_ID 0x2064
-#define BCM2064_IDCODE 0x02064000
-#define BCM2064A0_IDCODE 0x0206417f
-
-#define PHY_TPC_HW_OFF false
-#define PHY_TPC_HW_ON true
-
-#define PHY_PERICAL_DRIVERUP 1
-#define PHY_PERICAL_WATCHDOG 2
-#define PHY_PERICAL_PHYINIT 3
-#define PHY_PERICAL_JOIN_BSS 4
-#define PHY_PERICAL_START_IBSS 5
-#define PHY_PERICAL_UP_BSS 6
-#define PHY_PERICAL_CHAN 7
-#define PHY_FULLCAL 8
-
-#define PHY_PERICAL_DISABLE 0
-#define PHY_PERICAL_SPHASE 1
-#define PHY_PERICAL_MPHASE 2
-#define PHY_PERICAL_MANUAL 3
-
-#define PHY_HOLD_FOR_ASSOC 1
-#define PHY_HOLD_FOR_SCAN 2
-#define PHY_HOLD_FOR_RM 4
-#define PHY_HOLD_FOR_PLT 8
-#define PHY_HOLD_FOR_MUTE 16
-#define PHY_HOLD_FOR_NOT_ASSOC 0x20
-
-#define PHY_MUTE_FOR_PREISM 1
-#define PHY_MUTE_ALL 0xffffffff
-
-#define PHY_NOISE_FIXED_VAL (-95)
-#define PHY_NOISE_FIXED_VAL_NPHY (-92)
-#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)
-
-#define PHY_MODE_CAL 0x0002
-#define PHY_MODE_NOISEM 0x0004
-
-#define WLC_TXPWR_DB_FACTOR 4
-
-/* a large TX Power as an init value to factor out of min() calculations,
- * keep low enough to fit in an s8, units are .25 dBm
- */
-#define WLC_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
-
-#define WLC_NUM_RATES_CCK 4
-#define WLC_NUM_RATES_OFDM 8
-#define WLC_NUM_RATES_MCS_1_STREAM 8
-#define WLC_NUM_RATES_MCS_2_STREAM 8
-#define WLC_NUM_RATES_MCS_3_STREAM 8
-#define WLC_NUM_RATES_MCS_4_STREAM 8
-
-#define WLC_RSSI_INVALID 0 /* invalid RSSI value */
-
-typedef struct txpwr_limits {
- u8 cck[WLC_NUM_RATES_CCK];
- u8 ofdm[WLC_NUM_RATES_OFDM];
-
- u8 ofdm_cdd[WLC_NUM_RATES_OFDM];
-
- u8 ofdm_40_siso[WLC_NUM_RATES_OFDM];
- u8 ofdm_40_cdd[WLC_NUM_RATES_OFDM];
-
- u8 mcs_20_siso[WLC_NUM_RATES_MCS_1_STREAM];
- u8 mcs_20_cdd[WLC_NUM_RATES_MCS_1_STREAM];
- u8 mcs_20_stbc[WLC_NUM_RATES_MCS_1_STREAM];
- u8 mcs_20_mimo[WLC_NUM_RATES_MCS_2_STREAM];
-
- u8 mcs_40_siso[WLC_NUM_RATES_MCS_1_STREAM];
- u8 mcs_40_cdd[WLC_NUM_RATES_MCS_1_STREAM];
- u8 mcs_40_stbc[WLC_NUM_RATES_MCS_1_STREAM];
- u8 mcs_40_mimo[WLC_NUM_RATES_MCS_2_STREAM];
- u8 mcs32;
-} txpwr_limits_t;
-
-typedef struct {
- u32 flags;
- chanspec_t chanspec; /* txpwr report for this channel */
- chanspec_t local_chanspec; /* channel on which we are associated */
- u8 local_max; /* local max according to the AP */
- u8 local_constraint; /* local constraint according to the AP */
- s8 antgain[2]; /* Ant gain for each band - from SROM */
- u8 rf_cores; /* count of RF Cores being reported */
- u8 est_Pout[4]; /* Latest tx power out estimate per RF chain */
- u8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain
- * without adjustment
- */
- u8 est_Pout_cck; /* Latest CCK tx power out estimate */
- u8 tx_power_max[4]; /* Maximum target power among all rates */
- u8 tx_power_max_rate_ind[4]; /* Index of the rate with the max target power */
- u8 user_limit[WL_TX_POWER_RATES]; /* User limit */
- u8 reg_limit[WL_TX_POWER_RATES]; /* Regulatory power limit */
- u8 board_limit[WL_TX_POWER_RATES]; /* Max power board can support (SROM) */
- u8 target[WL_TX_POWER_RATES]; /* Latest target power */
-} tx_power_t;
-
-typedef struct tx_inst_power {
- u8 txpwr_est_Pout[2]; /* Latest estimate for 2.4 and 5 Ghz */
- u8 txpwr_est_Pout_gofdm; /* Pwr estimate for 2.4 OFDM */
-} tx_inst_power_t;
-
-typedef struct {
- u8 vec[MAXCHANNEL / NBBY];
-} chanvec_t;
-
-struct rpc_info;
-typedef struct shared_phy shared_phy_t;
-
-struct phy_pub;
-
-typedef struct phy_pub wlc_phy_t;
-
-typedef struct shared_phy_params {
- struct si_pub *sih;
- void *physhim;
- uint unit;
- uint corerev;
- uint bustype;
- uint buscorerev;
- char *vars;
- u16 vid;
- u16 did;
- uint chip;
- uint chiprev;
- uint chippkg;
- uint sromrev;
- uint boardtype;
- uint boardrev;
- uint boardvendor;
- u32 boardflags;
- u32 boardflags2;
-} shared_phy_params_t;
-
-
-extern shared_phy_t *wlc_phy_shared_attach(shared_phy_params_t *shp);
-extern void wlc_phy_shared_detach(shared_phy_t *phy_sh);
-extern wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype,
- char *vars, struct wiphy *wiphy);
-extern void wlc_phy_detach(wlc_phy_t *ppi);
-
-extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype,
- u16 *phyrev, u16 *radioid,
- u16 *radiover);
-extern bool wlc_phy_get_encore(wlc_phy_t *pih);
-extern u32 wlc_phy_get_coreflags(wlc_phy_t *pih);
-
-extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate);
-extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate);
-extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec);
-extern void wlc_phy_watchdog(wlc_phy_t *ppi);
-extern int wlc_phy_down(wlc_phy_t *ppi);
-extern u32 wlc_phy_clk_bwbits(wlc_phy_t *pih);
-extern void wlc_phy_cal_init(wlc_phy_t *ppi);
-extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init);
-
-extern void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec);
-extern chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi);
-extern void wlc_phy_chanspec_radio_set(wlc_phy_t *ppi, chanspec_t newch);
-extern u16 wlc_phy_bw_state_get(wlc_phy_t *ppi);
-extern void wlc_phy_bw_state_set(wlc_phy_t *ppi, u16 bw);
-
-extern void wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx);
-extern void wlc_phy_por_inform(wlc_phy_t *ppi);
-extern void wlc_phy_noise_sample_intr(wlc_phy_t *ppi);
-extern bool wlc_phy_bist_check_phy(wlc_phy_t *ppi);
-
-extern void wlc_phy_set_deaf(wlc_phy_t *ppi, bool user_flag);
-
-extern void wlc_phy_switch_radio(wlc_phy_t *ppi, bool on);
-extern void wlc_phy_anacore(wlc_phy_t *ppi, bool on);
-
-
-extern void wlc_phy_BSSinit(wlc_phy_t *ppi, bool bonlyap, int rssi);
-
-extern void wlc_phy_chanspec_ch14_widefilter_set(wlc_phy_t *ppi,
- bool wide_filter);
-extern void wlc_phy_chanspec_band_validch(wlc_phy_t *ppi, uint band,
- chanvec_t *channels);
-extern chanspec_t wlc_phy_chanspec_band_firstch(wlc_phy_t *ppi, uint band);
-
-extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan,
- u8 *_min_, u8 *_max_, int rate);
-extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan,
- u8 *_max_, u8 *_min_);
-extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, s32 *,
- s32 *, u32 *);
-extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *,
- chanspec_t chanspec);
-extern int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override);
-extern int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override);
-extern void wlc_phy_txpower_target_set(wlc_phy_t *ppi, struct txpwr_limits *);
-extern bool wlc_phy_txpower_hw_ctrl_get(wlc_phy_t *ppi);
-extern void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl);
-extern u8 wlc_phy_txpower_get_target_min(wlc_phy_t *ppi);
-extern u8 wlc_phy_txpower_get_target_max(wlc_phy_t *ppi);
-extern bool wlc_phy_txpower_ipa_ison(wlc_phy_t *pih);
-
-extern void wlc_phy_stf_chain_init(wlc_phy_t *pih, u8 txchain,
- u8 rxchain);
-extern void wlc_phy_stf_chain_set(wlc_phy_t *pih, u8 txchain,
- u8 rxchain);
-extern void wlc_phy_stf_chain_get(wlc_phy_t *pih, u8 *txchain,
- u8 *rxchain);
-extern u8 wlc_phy_stf_chain_active_get(wlc_phy_t *pih);
-extern s8 wlc_phy_stf_ssmode_get(wlc_phy_t *pih, chanspec_t chanspec);
-extern void wlc_phy_ldpc_override_set(wlc_phy_t *ppi, bool val);
-
-extern void wlc_phy_cal_perical(wlc_phy_t *ppi, u8 reason);
-extern void wlc_phy_noise_sample_request_external(wlc_phy_t *ppi);
-extern void wlc_phy_edcrs_lock(wlc_phy_t *pih, bool lock);
-extern void wlc_phy_cal_papd_recal(wlc_phy_t *ppi);
-
-extern void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val);
-extern void wlc_phy_clear_tssi(wlc_phy_t *ppi);
-extern void wlc_phy_hold_upd(wlc_phy_t *ppi, mbool id, bool val);
-extern void wlc_phy_mute_upd(wlc_phy_t *ppi, bool val, mbool flags);
-
-extern void wlc_phy_antsel_type_set(wlc_phy_t *ppi, u8 antsel_type);
-
-extern void wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power,
- uint channel);
-
-extern void wlc_phy_initcal_enable(wlc_phy_t *pih, bool initcal);
-extern bool wlc_phy_test_ison(wlc_phy_t *ppi);
-extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent);
-extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war);
-extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt);
-extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap);
-
-extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end);
-
-extern void wlc_phy_freqtrack_start(wlc_phy_t *ppi);
-extern void wlc_phy_freqtrack_end(wlc_phy_t *ppi);
-
-extern const u8 *wlc_phy_get_ofdm_rate_lookup(void);
-
-extern s8 wlc_phy_get_tx_power_offset_by_mcs(wlc_phy_t *ppi,
- u8 mcs_offset);
-extern s8 wlc_phy_get_tx_power_offset(wlc_phy_t *ppi, u8 tbl_offset);
-#endif /* _BRCM_PHY_HAL_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_PHY_INT_H_
-#define _BRCM_PHY_INT_H_
-
-#include <linux/kernel.h>
-#include <bcmdefs.h>
-#include <brcmu_utils.h>
-
-#include <wlc_phy_hal.h>
-
-#define PHY_VERSION { 1, 82, 8, 0 }
-
-#define PHYHAL_ERROR 0x0001
-#define PHYHAL_TRACE 0x0002
-#define PHYHAL_INFORM 0x0004
-
-extern u32 phyhal_msg_level;
-
-#define PHY_INFORM_ON() (phyhal_msg_level & PHYHAL_INFORM)
-#define PHY_THERMAL_ON() (phyhal_msg_level & PHYHAL_THERMAL)
-#define PHY_CAL_ON() (phyhal_msg_level & PHYHAL_CAL)
-
-#ifdef BOARD_TYPE
-#define BOARDTYPE(_type) BOARD_TYPE
-#else
-#define BOARDTYPE(_type) _type
-#endif
-
-#define LCNXN_BASEREV 16
-
-typedef struct {
- u8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */
- u8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
- u8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */
- u8 triso; /* TR switch isolation */
- u8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */
-} wlc_phy_srom_fem_t;
-
-struct wlc_hw_info;
-typedef struct phy_info phy_info_t;
-typedef void (*initfn_t) (phy_info_t *);
-typedef void (*chansetfn_t) (phy_info_t *, chanspec_t);
-typedef int (*longtrnfn_t) (phy_info_t *, int);
-typedef void (*txiqccgetfn_t) (phy_info_t *, u16 *, u16 *);
-typedef void (*txiqccsetfn_t) (phy_info_t *, u16, u16);
-typedef u16(*txloccgetfn_t) (phy_info_t *);
-typedef void (*radioloftgetfn_t) (phy_info_t *, u8 *, u8 *, u8 *,
- u8 *);
-typedef s32(*rxsigpwrfn_t) (phy_info_t *, s32);
-typedef void (*detachfn_t) (phy_info_t *);
-
-#undef ISNPHY
-#undef ISLCNPHY
-#define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
-#define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
-
-#define ISPHY_11N_CAP(pi) (ISNPHY(pi) || ISLCNPHY(pi))
-
-#define IS20MHZ(pi) ((pi)->bw == WL_CHANSPEC_BW_20)
-#define IS40MHZ(pi) ((pi)->bw == WL_CHANSPEC_BW_40)
-
-#define PHY_GET_RFATTN(rfgain) ((rfgain) & 0x0f)
-#define PHY_GET_PADMIX(rfgain) (((rfgain) & 0x10) >> 4)
-#define PHY_GET_RFGAINID(rfattn, padmix, width) ((rfattn) + ((padmix)*(width)))
-#define PHY_SAT(x, n) ((x) > ((1<<((n)-1))-1) ? ((1<<((n)-1))-1) : \
- ((x) < -(1<<((n)-1)) ? -(1<<((n)-1)) : (x)))
-#define PHY_SHIFT_ROUND(x, n) ((x) >= 0 ? ((x)+(1<<((n)-1)))>>(n) : (x)>>(n))
-#define PHY_HW_ROUND(x, s) ((x >> s) + ((x >> (s-1)) & (s != 0)))
-
-#define CH_5G_GROUP 3
-#define A_LOW_CHANS 0
-#define A_MID_CHANS 1
-#define A_HIGH_CHANS 2
-#define CH_2G_GROUP 1
-#define G_ALL_CHANS 0
-
-#define FIRST_REF5_CHANNUM 149
-#define LAST_REF5_CHANNUM 165
-#define FIRST_5G_CHAN 14
-#define LAST_5G_CHAN 50
-#define FIRST_MID_5G_CHAN 14
-#define LAST_MID_5G_CHAN 35
-#define FIRST_HIGH_5G_CHAN 36
-#define LAST_HIGH_5G_CHAN 41
-#define FIRST_LOW_5G_CHAN 42
-#define LAST_LOW_5G_CHAN 50
-
-#define BASE_LOW_5G_CHAN 4900
-#define BASE_MID_5G_CHAN 5100
-#define BASE_HIGH_5G_CHAN 5500
-
-#define CHAN5G_FREQ(chan) (5000 + chan*5)
-#define CHAN2G_FREQ(chan) (2407 + chan*5)
-
-#define TXP_FIRST_CCK 0
-#define TXP_LAST_CCK 3
-#define TXP_FIRST_OFDM 4
-#define TXP_LAST_OFDM 11
-#define TXP_FIRST_OFDM_20_CDD 12
-#define TXP_LAST_OFDM_20_CDD 19
-#define TXP_FIRST_MCS_20_SISO 20
-#define TXP_LAST_MCS_20_SISO 27
-#define TXP_FIRST_MCS_20_CDD 28
-#define TXP_LAST_MCS_20_CDD 35
-#define TXP_FIRST_MCS_20_STBC 36
-#define TXP_LAST_MCS_20_STBC 43
-#define TXP_FIRST_MCS_20_SDM 44
-#define TXP_LAST_MCS_20_SDM 51
-#define TXP_FIRST_OFDM_40_SISO 52
-#define TXP_LAST_OFDM_40_SISO 59
-#define TXP_FIRST_OFDM_40_CDD 60
-#define TXP_LAST_OFDM_40_CDD 67
-#define TXP_FIRST_MCS_40_SISO 68
-#define TXP_LAST_MCS_40_SISO 75
-#define TXP_FIRST_MCS_40_CDD 76
-#define TXP_LAST_MCS_40_CDD 83
-#define TXP_FIRST_MCS_40_STBC 84
-#define TXP_LAST_MCS_40_STBC 91
-#define TXP_FIRST_MCS_40_SDM 92
-#define TXP_LAST_MCS_40_SDM 99
-#define TXP_MCS_32 100
-#define TXP_NUM_RATES 101
-#define ADJ_PWR_TBL_LEN 84
-
-#define TXP_FIRST_SISO_MCS_20 20
-#define TXP_LAST_SISO_MCS_20 27
-
-#define PHY_CORE_NUM_1 1
-#define PHY_CORE_NUM_2 2
-#define PHY_CORE_NUM_3 3
-#define PHY_CORE_NUM_4 4
-#define PHY_CORE_MAX PHY_CORE_NUM_4
-#define PHY_CORE_0 0
-#define PHY_CORE_1 1
-#define PHY_CORE_2 2
-#define PHY_CORE_3 3
-
-#define MA_WINDOW_SZ 8
-
-#define PHY_NOISE_SAMPLE_MON 1
-#define PHY_NOISE_SAMPLE_EXTERNAL 2
-#define PHY_NOISE_WINDOW_SZ 16
-#define PHY_NOISE_GLITCH_INIT_MA 10
-#define PHY_NOISE_GLITCH_INIT_MA_BADPlCP 10
-#define PHY_NOISE_STATE_MON 0x1
-#define PHY_NOISE_STATE_EXTERNAL 0x2
-#define PHY_NOISE_SAMPLE_LOG_NUM_NPHY 10
-#define PHY_NOISE_SAMPLE_LOG_NUM_UCODE 9
-
-#define PHY_NOISE_OFFSETFACT_4322 (-103)
-#define PHY_NOISE_MA_WINDOW_SZ 2
-
-#define PHY_RSSI_TABLE_SIZE 64
-#define RSSI_ANT_MERGE_MAX 0
-#define RSSI_ANT_MERGE_MIN 1
-#define RSSI_ANT_MERGE_AVG 2
-
-#define PHY_TSSI_TABLE_SIZE 64
-#define APHY_TSSI_TABLE_SIZE 256
-#define TX_GAIN_TABLE_LENGTH 64
-#define DEFAULT_11A_TXP_IDX 24
-#define NUM_TSSI_FRAMES 4
-#define NULL_TSSI 0x7f
-#define NULL_TSSI_W 0x7f7f
-
-#define PHY_PAPD_EPS_TBL_SIZE_LCNPHY 64
-
-#define LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL 9
-
-#define PHY_TXPWR_MIN 10
-#define PHY_TXPWR_MIN_NPHY 8
-#define RADIOPWR_OVERRIDE_DEF (-1)
-
-#define PWRTBL_NUM_COEFF 3
-
-#define SPURAVOID_DISABLE 0
-#define SPURAVOID_AUTO 1
-#define SPURAVOID_FORCEON 2
-#define SPURAVOID_FORCEON2 3
-
-#define PHY_SW_TIMER_FAST 15
-#define PHY_SW_TIMER_SLOW 60
-#define PHY_SW_TIMER_GLACIAL 120
-
-#define PHY_PERICAL_AUTO 0
-#define PHY_PERICAL_FULL 1
-#define PHY_PERICAL_PARTIAL 2
-
-#define PHY_PERICAL_NODELAY 0
-#define PHY_PERICAL_INIT_DELAY 5
-#define PHY_PERICAL_ASSOC_DELAY 5
-#define PHY_PERICAL_WDOG_DELAY 5
-
-#define MPHASE_TXCAL_NUMCMDS 2
-#define PHY_PERICAL_MPHASE_PENDING(pi) (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_IDLE)
-
-enum {
- MPHASE_CAL_STATE_IDLE = 0,
- MPHASE_CAL_STATE_INIT = 1,
- MPHASE_CAL_STATE_TXPHASE0,
- MPHASE_CAL_STATE_TXPHASE1,
- MPHASE_CAL_STATE_TXPHASE2,
- MPHASE_CAL_STATE_TXPHASE3,
- MPHASE_CAL_STATE_TXPHASE4,
- MPHASE_CAL_STATE_TXPHASE5,
- MPHASE_CAL_STATE_PAPDCAL,
- MPHASE_CAL_STATE_RXCAL,
- MPHASE_CAL_STATE_RSSICAL,
- MPHASE_CAL_STATE_IDLETSSI
-};
-
-typedef enum {
- CAL_FULL,
- CAL_RECAL,
- CAL_CURRECAL,
- CAL_DIGCAL,
- CAL_GCTRL,
- CAL_SOFT,
- CAL_DIGLO
-} phy_cal_mode_t;
-
-#define RDR_NTIERS 1
-#define RDR_TIER_SIZE 64
-#define RDR_LIST_SIZE (512/3)
-#define RDR_EPOCH_SIZE 40
-#define RDR_NANTENNAS 2
-#define RDR_NTIER_SIZE RDR_LIST_SIZE
-#define RDR_LP_BUFFER_SIZE 64
-#define LP_LEN_HIS_SIZE 10
-
-#define STATIC_NUM_RF 32
-#define STATIC_NUM_BB 9
-
-#define BB_MULT_MASK 0x0000ffff
-#define BB_MULT_VALID_MASK 0x80000000
-
-#define CORDIC_AG 39797
-#define CORDIC_NI 18
-#define FIXED(X) ((s32)((X) << 16))
-#define FLOAT(X) (((X) >= 0) ? ((((X) >> 15) + 1) >> 1) : -((((-(X)) >> 15) + 1) >> 1))
-
-#define PHY_CHAIN_TX_DISABLE_TEMP 115
-#define PHY_HYSTERESIS_DELTATEMP 5
-
-#define PHY_BITSCNT(x) brcmu_bitcount((u8 *)&(x), sizeof(u8))
-
-#define MOD_PHY_REG(pi, phy_type, reg_name, field, value) \
- mod_phy_reg(pi, phy_type##_##reg_name, phy_type##_##reg_name##_##field##_MASK, \
- (value) << phy_type##_##reg_name##_##field##_##SHIFT);
-#define READ_PHY_REG(pi, phy_type, reg_name, field) \
- ((read_phy_reg(pi, phy_type##_##reg_name) & phy_type##_##reg_name##_##field##_##MASK)\
- >> phy_type##_##reg_name##_##field##_##SHIFT)
-
-#define VALID_PHYTYPE(phytype) (((uint)phytype == PHY_TYPE_N) || \
- ((uint)phytype == PHY_TYPE_LCN))
-
-#define VALID_N_RADIO(radioid) ((radioid == BCM2055_ID) || (radioid == BCM2056_ID) || \
- (radioid == BCM2057_ID))
-#define VALID_LCN_RADIO(radioid) (radioid == BCM2064_ID)
-
-#define VALID_RADIO(pi, radioid) (\
- (ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
- (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
-
-#define SCAN_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN))
-#define RM_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_RM))
-#define PLT_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_PLT))
-#define ASSOC_INPROG_PHY(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_ASSOC))
-#define SCAN_RM_IN_PROGRESS(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_SCAN | PHY_HOLD_FOR_RM))
-#define PHY_MUTED(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_MUTE))
-#define PUB_NOT_ASSOC(pi) (mboolisset(pi->measure_hold, PHY_HOLD_FOR_NOT_ASSOC))
-
-#if defined(EXT_CBALL)
-#define NORADIO_ENAB(pub) ((pub).radioid == NORADIO_ID)
-#else
-#define NORADIO_ENAB(pub) 0
-#endif
-
-#define PHY_LTRN_LIST_LEN 64
-extern u16 ltrn_list[PHY_LTRN_LIST_LEN];
-
-typedef struct _phy_table_info {
- uint table;
- int q;
- uint max;
-} phy_table_info_t;
-
-typedef struct phytbl_info {
- const void *tbl_ptr;
- u32 tbl_len;
- u32 tbl_id;
- u32 tbl_offset;
- u32 tbl_width;
-} phytbl_info_t;
-
-typedef struct {
- u8 curr_home_channel;
- u16 crsminpwrthld_40_stored;
- u16 crsminpwrthld_20L_stored;
- u16 crsminpwrthld_20U_stored;
- u16 init_gain_code_core1_stored;
- u16 init_gain_code_core2_stored;
- u16 init_gain_codeb_core1_stored;
- u16 init_gain_codeb_core2_stored;
- u16 init_gain_table_stored[4];
-
- u16 clip1_hi_gain_code_core1_stored;
- u16 clip1_hi_gain_code_core2_stored;
- u16 clip1_hi_gain_codeb_core1_stored;
- u16 clip1_hi_gain_codeb_core2_stored;
- u16 nb_clip_thresh_core1_stored;
- u16 nb_clip_thresh_core2_stored;
- u16 init_ofdmlna2gainchange_stored[4];
- u16 init_ccklna2gainchange_stored[4];
- u16 clip1_lo_gain_code_core1_stored;
- u16 clip1_lo_gain_code_core2_stored;
- u16 clip1_lo_gain_codeb_core1_stored;
- u16 clip1_lo_gain_codeb_core2_stored;
- u16 w1_clip_thresh_core1_stored;
- u16 w1_clip_thresh_core2_stored;
- u16 radio_2056_core1_rssi_gain_stored;
- u16 radio_2056_core2_rssi_gain_stored;
- u16 energy_drop_timeout_len_stored;
-
- u16 ed_crs40_assertthld0_stored;
- u16 ed_crs40_assertthld1_stored;
- u16 ed_crs40_deassertthld0_stored;
- u16 ed_crs40_deassertthld1_stored;
- u16 ed_crs20L_assertthld0_stored;
- u16 ed_crs20L_assertthld1_stored;
- u16 ed_crs20L_deassertthld0_stored;
- u16 ed_crs20L_deassertthld1_stored;
- u16 ed_crs20U_assertthld0_stored;
- u16 ed_crs20U_assertthld1_stored;
- u16 ed_crs20U_deassertthld0_stored;
- u16 ed_crs20U_deassertthld1_stored;
-
- u16 badplcp_ma;
- u16 badplcp_ma_previous;
- u16 badplcp_ma_total;
- u16 badplcp_ma_list[MA_WINDOW_SZ];
- int badplcp_ma_index;
- s16 pre_badplcp_cnt;
- s16 bphy_pre_badplcp_cnt;
-
- u16 init_gain_core1;
- u16 init_gain_core2;
- u16 init_gainb_core1;
- u16 init_gainb_core2;
- u16 init_gain_rfseq[4];
-
- u16 crsminpwr0;
- u16 crsminpwrl0;
- u16 crsminpwru0;
-
- s16 crsminpwr_index;
-
- u16 radio_2057_core1_rssi_wb1a_gc_stored;
- u16 radio_2057_core2_rssi_wb1a_gc_stored;
- u16 radio_2057_core1_rssi_wb1g_gc_stored;
- u16 radio_2057_core2_rssi_wb1g_gc_stored;
- u16 radio_2057_core1_rssi_wb2_gc_stored;
- u16 radio_2057_core2_rssi_wb2_gc_stored;
- u16 radio_2057_core1_rssi_nb_gc_stored;
- u16 radio_2057_core2_rssi_nb_gc_stored;
-
-} interference_info_t;
-
-typedef struct {
- u16 rc_cal_ovr;
- u16 phycrsth1;
- u16 phycrsth2;
- u16 init_n1p1_gain;
- u16 p1_p2_gain;
- u16 n1_n2_gain;
- u16 n1_p1_gain;
- u16 div_search_gain;
- u16 div_p1_p2_gain;
- u16 div_search_gn_change;
- u16 table_7_2;
- u16 table_7_3;
- u16 cckshbits_gnref;
- u16 clip_thresh;
- u16 clip2_thresh;
- u16 clip3_thresh;
- u16 clip_p2_thresh;
- u16 clip_pwdn_thresh;
- u16 clip_n1p1_thresh;
- u16 clip_n1_pwdn_thresh;
- u16 bbconfig;
- u16 cthr_sthr_shdin;
- u16 energy;
- u16 clip_p1_p2_thresh;
- u16 threshold;
- u16 reg15;
- u16 reg16;
- u16 reg17;
- u16 div_srch_idx;
- u16 div_srch_p1_p2;
- u16 div_srch_gn_back;
- u16 ant_dwell;
- u16 ant_wr_settle;
-} aci_save_gphy_t;
-
-typedef struct _lo_complex_t {
- s8 i;
- s8 q;
-} lo_complex_abgphy_info_t;
-
-typedef struct _nphy_iq_comp {
- s16 a0;
- s16 b0;
- s16 a1;
- s16 b1;
-} nphy_iq_comp_t;
-
-typedef struct _nphy_txpwrindex {
- s8 index;
- s8 index_internal;
- s8 index_internal_save;
- u16 AfectrlOverride;
- u16 AfeCtrlDacGain;
- u16 rad_gain;
- u8 bbmult;
- u16 iqcomp_a;
- u16 iqcomp_b;
- u16 locomp;
-} phy_txpwrindex_t;
-
-typedef struct {
-
- u16 txcal_coeffs_2G[8];
- u16 txcal_radio_regs_2G[8];
- nphy_iq_comp_t rxcal_coeffs_2G;
-
- u16 txcal_coeffs_5G[8];
- u16 txcal_radio_regs_5G[8];
- nphy_iq_comp_t rxcal_coeffs_5G;
-} txiqcal_cache_t;
-
-typedef struct _nphy_pwrctrl {
- s8 max_pwr_2g;
- s8 idle_targ_2g;
- s16 pwrdet_2g_a1;
- s16 pwrdet_2g_b0;
- s16 pwrdet_2g_b1;
- s8 max_pwr_5gm;
- s8 idle_targ_5gm;
- s8 max_pwr_5gh;
- s8 max_pwr_5gl;
- s16 pwrdet_5gm_a1;
- s16 pwrdet_5gm_b0;
- s16 pwrdet_5gm_b1;
- s16 pwrdet_5gl_a1;
- s16 pwrdet_5gl_b0;
- s16 pwrdet_5gl_b1;
- s16 pwrdet_5gh_a1;
- s16 pwrdet_5gh_b0;
- s16 pwrdet_5gh_b1;
- s8 idle_targ_5gl;
- s8 idle_targ_5gh;
- s8 idle_tssi_2g;
- s8 idle_tssi_5g;
- s8 idle_tssi;
- s16 a1;
- s16 b0;
- s16 b1;
-} phy_pwrctrl_t;
-
-typedef struct _nphy_txgains {
- u16 txlpf[2];
- u16 txgm[2];
- u16 pga[2];
- u16 pad[2];
- u16 ipa[2];
-} nphy_txgains_t;
-
-#define PHY_NOISEVAR_BUFSIZE 10
-
-typedef struct _nphy_noisevar_buf {
- int bufcount;
- int tone_id[PHY_NOISEVAR_BUFSIZE];
- u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
- u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
-} phy_noisevar_buf_t;
-
-typedef struct {
- u16 rssical_radio_regs_2G[2];
- u16 rssical_phyregs_2G[12];
-
- u16 rssical_radio_regs_5G[2];
- u16 rssical_phyregs_5G[12];
-} rssical_cache_t;
-
-typedef struct {
-
- u16 txiqlocal_a;
- u16 txiqlocal_b;
- u16 txiqlocal_didq;
- u8 txiqlocal_ei0;
- u8 txiqlocal_eq0;
- u8 txiqlocal_fi0;
- u8 txiqlocal_fq0;
-
- u16 txiqlocal_bestcoeffs[11];
- u16 txiqlocal_bestcoeffs_valid;
-
- u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
- u16 analog_gain_ref;
- u16 lut_begin;
- u16 lut_end;
- u16 lut_step;
- u16 rxcompdbm;
- u16 papdctrl;
- u16 sslpnCalibClkEnCtrl;
-
- u16 rxiqcal_coeff_a0;
- u16 rxiqcal_coeff_b0;
-} lcnphy_cal_results_t;
-
-struct shared_phy {
- struct phy_info *phy_head;
- uint unit;
- struct si_pub *sih;
- void *physhim;
- uint corerev;
- u32 machwcap;
- bool up;
- bool clk;
- uint now;
- u16 vid;
- u16 did;
- uint chip;
- uint chiprev;
- uint chippkg;
- uint sromrev;
- uint boardtype;
- uint boardrev;
- uint boardvendor;
- u32 boardflags;
- u32 boardflags2;
- uint bustype;
- uint buscorerev;
- uint fast_timer;
- uint slow_timer;
- uint glacial_timer;
- u8 rx_antdiv;
- s8 phy_noise_window[MA_WINDOW_SZ];
- uint phy_noise_index;
- u8 hw_phytxchain;
- u8 hw_phyrxchain;
- u8 phytxchain;
- u8 phyrxchain;
- u8 rssi_mode;
- bool _rifs_phy;
-};
-
-struct phy_pub {
- uint phy_type;
- uint phy_rev;
- u8 phy_corenum;
- u16 radioid;
- u8 radiorev;
- u8 radiover;
-
- uint coreflags;
- uint ana_rev;
- bool abgphy_encore;
-};
-
-struct phy_info_nphy;
-typedef struct phy_info_nphy phy_info_nphy_t;
-
-struct phy_info_lcnphy;
-typedef struct phy_info_lcnphy phy_info_lcnphy_t;
-
-struct phy_func_ptr {
- initfn_t init;
- initfn_t calinit;
- chansetfn_t chanset;
- initfn_t txpwrrecalc;
- longtrnfn_t longtrn;
- txiqccgetfn_t txiqccget;
- txiqccsetfn_t txiqccset;
- txloccgetfn_t txloccget;
- radioloftgetfn_t radioloftget;
- initfn_t carrsuppr;
- rxsigpwrfn_t rxsigpwr;
- detachfn_t detach;
-};
-typedef struct phy_func_ptr phy_func_ptr_t;
-
-struct phy_info {
- wlc_phy_t pubpi_ro;
- shared_phy_t *sh;
- phy_func_ptr_t pi_fptr;
- void *pi_ptr;
-
- union {
- phy_info_lcnphy_t *pi_lcnphy;
- } u;
- bool user_txpwr_at_rfport;
-
- d11regs_t *regs;
- struct phy_info *next;
- char *vars;
- wlc_phy_t pubpi;
-
- bool do_initcal;
- bool phytest_on;
- bool ofdm_rateset_war;
- bool bf_preempt_4306;
- chanspec_t radio_chanspec;
- u8 antsel_type;
- u16 bw;
- u8 txpwr_percent;
- bool phy_init_por;
-
- bool init_in_progress;
- bool initialized;
- bool sbtml_gm;
- uint refcnt;
- bool watchdog_override;
- u8 phynoise_state;
- uint phynoise_now;
- int phynoise_chan_watchdog;
- bool phynoise_polling;
- bool disable_percal;
- mbool measure_hold;
-
- s16 txpa_2g[PWRTBL_NUM_COEFF];
- s16 txpa_2g_low_temp[PWRTBL_NUM_COEFF];
- s16 txpa_2g_high_temp[PWRTBL_NUM_COEFF];
- s16 txpa_5g_low[PWRTBL_NUM_COEFF];
- s16 txpa_5g_mid[PWRTBL_NUM_COEFF];
- s16 txpa_5g_hi[PWRTBL_NUM_COEFF];
-
- u8 tx_srom_max_2g;
- u8 tx_srom_max_5g_low;
- u8 tx_srom_max_5g_mid;
- u8 tx_srom_max_5g_hi;
- u8 tx_srom_max_rate_2g[TXP_NUM_RATES];
- u8 tx_srom_max_rate_5g_low[TXP_NUM_RATES];
- u8 tx_srom_max_rate_5g_mid[TXP_NUM_RATES];
- u8 tx_srom_max_rate_5g_hi[TXP_NUM_RATES];
- u8 tx_user_target[TXP_NUM_RATES];
- s8 tx_power_offset[TXP_NUM_RATES];
- u8 tx_power_target[TXP_NUM_RATES];
-
- wlc_phy_srom_fem_t srom_fem2g;
- wlc_phy_srom_fem_t srom_fem5g;
-
- u8 tx_power_max;
- u8 tx_power_max_rate_ind;
- bool hwpwrctrl;
- u8 nphy_txpwrctrl;
- s8 nphy_txrx_chain;
- bool phy_5g_pwrgain;
-
- u16 phy_wreg;
- u16 phy_wreg_limit;
-
- s8 n_preamble_override;
- u8 antswitch;
- u8 aa2g, aa5g;
-
- s8 idle_tssi[CH_5G_GROUP];
- s8 target_idle_tssi;
- s8 txpwr_est_Pout;
- u8 tx_power_min;
- u8 txpwr_limit[TXP_NUM_RATES];
- u8 txpwr_env_limit[TXP_NUM_RATES];
- u8 adj_pwr_tbl_nphy[ADJ_PWR_TBL_LEN];
-
- bool channel_14_wide_filter;
-
- bool txpwroverride;
- bool txpwridx_override_aphy;
- s16 radiopwr_override;
- u16 hwpwr_txcur;
- u8 saved_txpwr_idx;
-
- bool edcrs_threshold_lock;
-
- u32 tr_R_gain_val;
- u32 tr_T_gain_val;
-
- s16 ofdm_analog_filt_bw_override;
- s16 cck_analog_filt_bw_override;
- s16 ofdm_rccal_override;
- s16 cck_rccal_override;
- u16 extlna_type;
-
- uint interference_mode_crs_time;
- u16 crsglitch_prev;
- bool interference_mode_crs;
-
- u32 phy_tx_tone_freq;
- uint phy_lastcal;
- bool phy_forcecal;
- bool phy_fixed_noise;
- u32 xtalfreq;
- u8 pdiv;
- s8 carrier_suppr_disable;
-
- bool phy_bphy_evm;
- bool phy_bphy_rfcs;
- s8 phy_scraminit;
- u8 phy_gpiosel;
-
- s16 phy_txcore_disable_temp;
- s16 phy_txcore_enable_temp;
- s8 phy_tempsense_offset;
- bool phy_txcore_heatedup;
-
- u16 radiopwr;
- u16 bb_atten;
- u16 txctl1;
-
- u16 mintxbias;
- u16 mintxmag;
- lo_complex_abgphy_info_t gphy_locomp_iq[STATIC_NUM_RF][STATIC_NUM_BB];
- s8 stats_11b_txpower[STATIC_NUM_RF][STATIC_NUM_BB];
- u16 gain_table[TX_GAIN_TABLE_LENGTH];
- bool loopback_gain;
- s16 max_lpback_gain_hdB;
- s16 trsw_rx_gain_hdB;
- u8 power_vec[8];
-
- u16 rc_cal;
- int nrssi_table_delta;
- int nrssi_slope_scale;
- int nrssi_slope_offset;
- int min_rssi;
- int max_rssi;
-
- s8 txpwridx;
- u8 min_txpower;
-
- u8 a_band_high_disable;
-
- u16 tx_vos;
- u16 global_tx_bb_dc_bias_loft;
-
- int rf_max;
- int bb_max;
- int rf_list_size;
- int bb_list_size;
- u16 *rf_attn_list;
- u16 *bb_attn_list;
- u16 padmix_mask;
- u16 padmix_reg;
- u16 *txmag_list;
- uint txmag_len;
- bool txmag_enable;
-
- s8 *a_tssi_to_dbm;
- s8 *m_tssi_to_dbm;
- s8 *l_tssi_to_dbm;
- s8 *h_tssi_to_dbm;
- u8 *hwtxpwr;
-
- u16 freqtrack_saved_regs[2];
- int cur_interference_mode;
- bool hwpwrctrl_capable;
- bool temppwrctrl_capable;
-
- uint phycal_nslope;
- uint phycal_noffset;
- uint phycal_mlo;
- uint phycal_txpower;
-
- u8 phy_aa2g;
-
- bool nphy_tableloaded;
- s8 nphy_rssisel;
- u32 nphy_bb_mult_save;
- u16 nphy_txiqlocal_bestc[11];
- bool nphy_txiqlocal_coeffsvalid;
- phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
- phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
- u16 cck2gpo;
- u32 ofdm2gpo;
- u32 ofdm5gpo;
- u32 ofdm5glpo;
- u32 ofdm5ghpo;
- u8 bw402gpo;
- u8 bw405gpo;
- u8 bw405glpo;
- u8 bw405ghpo;
- u8 cdd2gpo;
- u8 cdd5gpo;
- u8 cdd5glpo;
- u8 cdd5ghpo;
- u8 stbc2gpo;
- u8 stbc5gpo;
- u8 stbc5glpo;
- u8 stbc5ghpo;
- u8 bwdup2gpo;
- u8 bwdup5gpo;
- u8 bwdup5glpo;
- u8 bwdup5ghpo;
- u16 mcs2gpo[8];
- u16 mcs5gpo[8];
- u16 mcs5glpo[8];
- u16 mcs5ghpo[8];
- u32 nphy_rxcalparams;
-
- u8 phy_spuravoid;
- bool phy_isspuravoid;
-
- u8 phy_pabias;
- u8 nphy_papd_skip;
- u8 nphy_tssi_slope;
-
- s16 nphy_noise_win[PHY_CORE_MAX][PHY_NOISE_WINDOW_SZ];
- u8 nphy_noise_index;
-
- u8 nphy_txpid2g[PHY_CORE_NUM_2];
- u8 nphy_txpid5g[PHY_CORE_NUM_2];
- u8 nphy_txpid5gl[PHY_CORE_NUM_2];
- u8 nphy_txpid5gh[PHY_CORE_NUM_2];
-
- bool nphy_gain_boost;
- bool nphy_elna_gain_config;
- u16 old_bphy_test;
- u16 old_bphy_testcontrol;
-
- bool phyhang_avoid;
-
- bool rssical_nphy;
- u8 nphy_perical;
- uint nphy_perical_last;
- u8 cal_type_override;
- u8 mphase_cal_phase_id;
- u8 mphase_txcal_cmdidx;
- u8 mphase_txcal_numcmds;
- u16 mphase_txcal_bestcoeffs[11];
- chanspec_t nphy_txiqlocal_chanspec;
- chanspec_t nphy_iqcal_chanspec_2G;
- chanspec_t nphy_iqcal_chanspec_5G;
- chanspec_t nphy_rssical_chanspec_2G;
- chanspec_t nphy_rssical_chanspec_5G;
- struct wlapi_timer *phycal_timer;
- bool use_int_tx_iqlo_cal_nphy;
- bool internal_tx_iqlo_cal_tapoff_intpa_nphy;
- s16 nphy_lastcal_temp;
-
- txiqcal_cache_t calibration_cache;
- rssical_cache_t rssical_cache;
-
- u8 nphy_txpwr_idx[2];
- u8 nphy_papd_cal_type;
- uint nphy_papd_last_cal;
- u16 nphy_papd_tx_gain_at_last_cal[2];
- u8 nphy_papd_cal_gain_index[2];
- s16 nphy_papd_epsilon_offset[2];
- bool nphy_papd_recal_enable;
- u32 nphy_papd_recal_counter;
- bool nphy_force_papd_cal;
- bool nphy_papdcomp;
- bool ipa2g_on;
- bool ipa5g_on;
-
- u16 classifier_state;
- u16 clip_state[2];
- uint nphy_deaf_count;
- u8 rxiq_samps;
- u8 rxiq_antsel;
-
- u16 rfctrlIntc1_save;
- u16 rfctrlIntc2_save;
- bool first_cal_after_assoc;
- u16 tx_rx_cal_radio_saveregs[22];
- u16 tx_rx_cal_phy_saveregs[15];
-
- u8 nphy_cal_orig_pwr_idx[2];
- u8 nphy_txcal_pwr_idx[2];
- u8 nphy_rxcal_pwr_idx[2];
- u16 nphy_cal_orig_tx_gain[2];
- nphy_txgains_t nphy_cal_target_gain;
- u16 nphy_txcal_bbmult;
- u16 nphy_gmval;
-
- u16 nphy_saved_bbconf;
-
- bool nphy_gband_spurwar_en;
- bool nphy_gband_spurwar2_en;
- bool nphy_aband_spurwar_en;
- u16 nphy_rccal_value;
- u16 nphy_crsminpwr[3];
- phy_noisevar_buf_t nphy_saved_noisevars;
- bool nphy_anarxlpf_adjusted;
- bool nphy_crsminpwr_adjusted;
- bool nphy_noisevars_adjusted;
-
- bool nphy_rxcal_active;
- u16 radar_percal_mask;
- bool dfs_lp_buffer_nphy;
-
- u16 nphy_fineclockgatecontrol;
-
- s8 rx2tx_biasentry;
-
- u16 crsminpwr0;
- u16 crsminpwrl0;
- u16 crsminpwru0;
- s16 noise_crsminpwr_index;
- u16 init_gain_core1;
- u16 init_gain_core2;
- u16 init_gainb_core1;
- u16 init_gainb_core2;
- u8 aci_noise_curr_channel;
- u16 init_gain_rfseq[4];
-
- bool radio_is_on;
-
- bool nphy_sample_play_lpf_bw_ctl_ovr;
-
- u16 tbl_data_hi;
- u16 tbl_data_lo;
- u16 tbl_addr;
-
- uint tbl_save_id;
- uint tbl_save_offset;
-
- u8 txpwrctrl;
- s8 txpwrindex[PHY_CORE_MAX];
-
- u8 phycal_tempdelta;
- u32 mcs20_po;
- u32 mcs40_po;
- struct wiphy *wiphy;
-};
-
-typedef s32 fixed;
-
-typedef struct _cs32 {
- fixed q;
- fixed i;
-} cs32;
-
-typedef struct radio_regs {
- u16 address;
- u32 init_a;
- u32 init_g;
- u8 do_init_a;
- u8 do_init_g;
-} radio_regs_t;
-
-typedef struct radio_20xx_regs {
- u16 address;
- u8 init;
- u8 do_init;
-} radio_20xx_regs_t;
-
-typedef struct lcnphy_radio_regs {
- u16 address;
- u8 init_a;
- u8 init_g;
- u8 do_init_a;
- u8 do_init_g;
-} lcnphy_radio_regs_t;
-
-extern lcnphy_radio_regs_t lcnphy_radio_regs_2064[];
-extern lcnphy_radio_regs_t lcnphy_radio_regs_2066[];
-extern radio_regs_t regs_2055[], regs_SYN_2056[], regs_TX_2056[],
- regs_RX_2056[];
-extern radio_regs_t regs_SYN_2056_A1[], regs_TX_2056_A1[], regs_RX_2056_A1[];
-extern radio_regs_t regs_SYN_2056_rev5[], regs_TX_2056_rev5[],
- regs_RX_2056_rev5[];
-extern radio_regs_t regs_SYN_2056_rev6[], regs_TX_2056_rev6[],
- regs_RX_2056_rev6[];
-extern radio_regs_t regs_SYN_2056_rev7[], regs_TX_2056_rev7[],
- regs_RX_2056_rev7[];
-extern radio_regs_t regs_SYN_2056_rev8[], regs_TX_2056_rev8[],
- regs_RX_2056_rev8[];
-extern radio_20xx_regs_t regs_2057_rev4[], regs_2057_rev5[], regs_2057_rev5v1[];
-extern radio_20xx_regs_t regs_2057_rev7[], regs_2057_rev8[];
-
-extern char *phy_getvar(phy_info_t *pi, const char *name);
-extern int phy_getintvar(phy_info_t *pi, const char *name);
-#define PHY_GETVAR(pi, name) phy_getvar(pi, name)
-#define PHY_GETINTVAR(pi, name) phy_getintvar(pi, name)
-
-extern u16 read_phy_reg(phy_info_t *pi, u16 addr);
-extern void write_phy_reg(phy_info_t *pi, u16 addr, u16 val);
-extern void and_phy_reg(phy_info_t *pi, u16 addr, u16 val);
-extern void or_phy_reg(phy_info_t *pi, u16 addr, u16 val);
-extern void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val);
-
-extern u16 read_radio_reg(phy_info_t *pi, u16 addr);
-extern void or_radio_reg(phy_info_t *pi, u16 addr, u16 val);
-extern void and_radio_reg(phy_info_t *pi, u16 addr, u16 val);
-extern void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask,
- u16 val);
-extern void xor_radio_reg(phy_info_t *pi, u16 addr, u16 mask);
-
-extern void write_radio_reg(phy_info_t *pi, u16 addr, u16 val);
-
-extern void wlc_phyreg_enter(wlc_phy_t *pih);
-extern void wlc_phyreg_exit(wlc_phy_t *pih);
-extern void wlc_radioreg_enter(wlc_phy_t *pih);
-extern void wlc_radioreg_exit(wlc_phy_t *pih);
-
-extern void wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
- u16 tblAddr, u16 tblDataHi,
- u16 tblDatalo);
-extern void wlc_phy_write_table(phy_info_t *pi,
- const phytbl_info_t *ptbl_info, u16 tblAddr,
- u16 tblDataHi, u16 tblDatalo);
-extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
- u16 tblAddr, u16 tblDataHi,
- u16 tblDataLo);
-extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val);
-
-extern void write_phy_channel_reg(phy_info_t *pi, uint val);
-extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
-
-extern void wlc_phy_cordic(fixed theta, cs32 *val);
-extern u8 wlc_phy_nbits(s32 value);
-extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
-
-extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
- radio_20xx_regs_t *radioregs);
-extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
- u16 core_offset);
-
-extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
-
-extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
-extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
- s32 *eps_imag);
-
-extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
-extern void wlc_phy_cal_perical_mphase_restart(phy_info_t *pi);
-
-extern bool wlc_phy_attach_nphy(phy_info_t *pi);
-extern bool wlc_phy_attach_lcnphy(phy_info_t *pi);
-
-extern void wlc_phy_detach_lcnphy(phy_info_t *pi);
-
-extern void wlc_phy_init_nphy(phy_info_t *pi);
-extern void wlc_phy_init_lcnphy(phy_info_t *pi);
-
-extern void wlc_phy_cal_init_nphy(phy_info_t *pi);
-extern void wlc_phy_cal_init_lcnphy(phy_info_t *pi);
-
-extern void wlc_phy_chanspec_set_nphy(phy_info_t *pi, chanspec_t chanspec);
-extern void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec);
-extern void wlc_phy_chanspec_set_fixup_lcnphy(phy_info_t *pi,
- chanspec_t chanspec);
-extern int wlc_phy_channel2freq(uint channel);
-extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
-extern int wlc_phy_chanspec_bandrange_get(phy_info_t *, chanspec_t);
-
-extern void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode);
-extern s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi);
-
-extern void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi);
-extern void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi);
-extern void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi);
-
-extern void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index);
-extern void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable);
-extern void wlc_lcnphy_stop_tx_tone(phy_info_t *pi);
-extern void wlc_lcnphy_start_tx_tone(phy_info_t *pi, s32 f_kHz,
- u16 max_val, bool iqcalmode);
-
-extern void wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan,
- u8 *max_pwr, u8 rate_id);
-extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
- u8 rate_mcs_end,
- u8 rate_ofdm_start);
-extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
- u8 rate_ofdm_start,
- u8 rate_ofdm_end,
- u8 rate_mcs_start);
-
-extern u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode);
-extern s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode);
-extern s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode);
-extern s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode);
-extern void wlc_phy_carrier_suppress_lcnphy(phy_info_t *pi);
-extern void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel);
-extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
-extern void wlc_2064_vco_cal(phy_info_t *pi);
-
-extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
-
-#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
-#define LCNPHY_TX_POWER_TABLE_SIZE 128
-#define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1)
-#define LCNPHY_TBL_ID_TXPWRCTL 0x07
-#define LCNPHY_TX_PWR_CTRL_OFF 0
-#define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15)
-#define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \
- (0x1 << 14) | \
- (0x1 << 13))
-
-#define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001
-
-extern void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti);
-extern void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti);
-extern void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b);
-extern void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq);
-extern void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b);
-extern u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi);
-extern void wlc_lcnphy_get_radio_loft(phy_info_t *pi, u8 *ei0,
- u8 *eq0, u8 *fi0, u8 *fq0);
-extern void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode);
-extern void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode);
-extern bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi);
-extern void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi);
-extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
-extern void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr,
- s8 *cck_pwr);
-extern void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi);
-
-extern s32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, s32 gain_index);
-
-#define NPHY_MAX_HPVGA1_INDEX 10
-#define NPHY_DEF_HPVGA1_INDEXLIMIT 7
-
-typedef struct _phy_iq_est {
- s32 iq_prod;
- u32 i_pwr;
- u32 q_pwr;
-} phy_iq_est_t;
-
-extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
-extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
-
-#define wlc_phy_write_table_nphy(pi, pti) wlc_phy_write_table(pi, pti, 0x72, \
- 0x74, 0x73)
-#define wlc_phy_read_table_nphy(pi, pti) wlc_phy_read_table(pi, pti, 0x72, \
- 0x74, 0x73)
-#define wlc_nphy_table_addr(pi, id, off) wlc_phy_table_addr((pi), (id), (off), \
- 0x72, 0x74, 0x73)
-#define wlc_nphy_table_data_write(pi, w, v) wlc_phy_table_data_write((pi), (w), (v))
-
-extern void wlc_phy_table_read_nphy(phy_info_t *pi, u32, u32 l, u32 o,
- u32 w, void *d);
-extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,
- u32, const void *);
-
-#define PHY_IPA(pi) \
- ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
- (pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
-
-#define WLC_PHY_WAR_PR51571(pi) \
- if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
- (void)R_REG(&(pi)->regs->maccontrol)
-
-extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype);
-extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);
-extern void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en);
-
-extern u8 wlc_phy_get_chan_freq_range_nphy(phy_info_t *pi, uint chan);
-extern void wlc_phy_switch_radio_nphy(phy_info_t *pi, bool on);
-
-extern void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi);
-
-extern void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd);
-extern s16 wlc_phy_tempsense_nphy(phy_info_t *pi);
-
-extern u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val);
-
-extern void wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est,
- u16 num_samps, u8 wait_time,
- u8 wait_for_crs);
-
-extern void wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write,
- nphy_iq_comp_t *comp);
-extern void wlc_phy_aci_and_noise_reduction_nphy(phy_info_t *pi);
-
-extern void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask);
-extern u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih);
-
-extern void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type);
-extern void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi);
-extern void wlc_phy_txpwr_apply_nphy(phy_info_t *pi);
-extern void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi);
-extern u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi);
-
-extern nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi);
-extern int wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
- bool full, bool m);
-extern int wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
- u8 type, bool d);
-extern void wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask,
- s8 txpwrindex, bool res);
-extern void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core, u8 rssi_type);
-extern int wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type,
- s32 *rssi_buf, u8 nsamps);
-extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
-extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
-extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower,
- bool debug);
-extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
- u8 mode, u8, bool);
-extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
-extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, s32 *qdBm_pwrbuf,
- u8 num_samps);
-extern void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi);
-
-extern int wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh);
-
-#define NPHY_TESTPATTERN_BPHY_EVM 0
-#define NPHY_TESTPATTERN_BPHY_RFCS 1
-
-extern void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs);
-
-void wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset,
- s8 *ofdmoffset);
-extern s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi,
- chanspec_t chanspec);
-
-extern bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pih);
-#endif /* _BRCM_PHY_INT_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <wlc_cfg.h>
-#include <linux/pci.h>
-#include <brcmu_utils.h>
-#include <aiutils.h>
-#include <wlc_pmu.h>
-#include <wlc_scb.h>
-#include <wlc_pub.h>
-
-#include <bcmdevs.h>
-#include "bcmdma.h"
-
-#include "wlc_phy_radio.h"
-#include "wlc_phy_int.h"
-#include "wlc_phy_qmath.h"
-#include "wlc_phy_lcn.h"
-#include "wlc_phytbl_lcn.h"
-
-#define PLL_2064_NDIV 90
-#define PLL_2064_LOW_END_VCO 3000
-#define PLL_2064_LOW_END_KVCO 27
-#define PLL_2064_HIGH_END_VCO 4200
-#define PLL_2064_HIGH_END_KVCO 68
-#define PLL_2064_LOOP_BW_DOUBLER 200
-#define PLL_2064_D30_DOUBLER 10500
-#define PLL_2064_LOOP_BW 260
-#define PLL_2064_D30 8000
-#define PLL_2064_CAL_REF_TO 8
-#define PLL_2064_MHZ 1000000
-#define PLL_2064_OPEN_LOOP_DELAY 5
-
-#define TEMPSENSE 1
-#define VBATSENSE 2
-
-#define NOISE_IF_UPD_CHK_INTERVAL 1
-#define NOISE_IF_UPD_RST_INTERVAL 60
-#define NOISE_IF_UPD_THRESHOLD_CNT 1
-#define NOISE_IF_UPD_TRHRESHOLD 50
-#define NOISE_IF_UPD_TIMEOUT 1000
-#define NOISE_IF_OFF 0
-#define NOISE_IF_CHK 1
-#define NOISE_IF_ON 2
-
-#define PAPD_BLANKING_PROFILE 3
-#define PAPD2LUT 0
-#define PAPD_CORR_NORM 0
-#define PAPD_BLANKING_THRESHOLD 0
-#define PAPD_STOP_AFTER_LAST_UPDATE 0
-
-#define LCN_TARGET_PWR 60
-
-#define LCN_VBAT_OFFSET_433X 34649679
-#define LCN_VBAT_SLOPE_433X 8258032
-
-#define LCN_VBAT_SCALE_NOM 53
-#define LCN_VBAT_SCALE_DEN 432
-
-#define LCN_TEMPSENSE_OFFSET 80812
-#define LCN_TEMPSENSE_DEN 2647
-
-#define LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT \
- (0 + 8)
-#define LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK \
- (0x7f << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT)
-
-#define LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT \
- (0 + 8)
-#define LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_MASK \
- (0x7f << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT)
-
-#define wlc_lcnphy_enable_tx_gain_override(pi) \
- wlc_lcnphy_set_tx_gain_override(pi, true)
-#define wlc_lcnphy_disable_tx_gain_override(pi) \
- wlc_lcnphy_set_tx_gain_override(pi, false)
-
-#define wlc_lcnphy_iqcal_active(pi) \
- (read_phy_reg((pi), 0x451) & \
- ((0x1 << 15) | (0x1 << 14)))
-
-#define txpwrctrl_off(pi) (0x7 != ((read_phy_reg(pi, 0x4a4) & 0xE000) >> 13))
-#define wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) \
- (pi->temppwrctrl_capable)
-#define wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) \
- (pi->hwpwrctrl_capable)
-
-#define SWCTRL_BT_TX 0x18
-#define SWCTRL_OVR_DISABLE 0x40
-
-#define AFE_CLK_INIT_MODE_TXRX2X 1
-#define AFE_CLK_INIT_MODE_PAPD 0
-
-#define LCNPHY_TBL_ID_IQLOCAL 0x00
-
-#define LCNPHY_TBL_ID_RFSEQ 0x08
-#define LCNPHY_TBL_ID_GAIN_IDX 0x0d
-#define LCNPHY_TBL_ID_SW_CTRL 0x0f
-#define LCNPHY_TBL_ID_GAIN_TBL 0x12
-#define LCNPHY_TBL_ID_SPUR 0x14
-#define LCNPHY_TBL_ID_SAMPLEPLAY 0x15
-#define LCNPHY_TBL_ID_SAMPLEPLAY1 0x16
-
-#define LCNPHY_TX_PWR_CTRL_RATE_OFFSET 832
-#define LCNPHY_TX_PWR_CTRL_MAC_OFFSET 128
-#define LCNPHY_TX_PWR_CTRL_GAIN_OFFSET 192
-#define LCNPHY_TX_PWR_CTRL_IQ_OFFSET 320
-#define LCNPHY_TX_PWR_CTRL_LO_OFFSET 448
-#define LCNPHY_TX_PWR_CTRL_PWR_OFFSET 576
-
-#define LCNPHY_TX_PWR_CTRL_START_INDEX_2G_4313 140
-
-#define LCNPHY_TX_PWR_CTRL_START_NPT 1
-#define LCNPHY_TX_PWR_CTRL_MAX_NPT 7
-
-#define LCNPHY_NOISE_SAMPLES_DEFAULT 5000
-
-#define LCNPHY_ACI_DETECT_START 1
-#define LCNPHY_ACI_DETECT_PROGRESS 2
-#define LCNPHY_ACI_DETECT_STOP 3
-
-#define LCNPHY_ACI_CRSHIFRMLO_TRSH 100
-#define LCNPHY_ACI_GLITCH_TRSH 2000
-#define LCNPHY_ACI_TMOUT 250
-#define LCNPHY_ACI_DETECT_TIMEOUT 2
-#define LCNPHY_ACI_START_DELAY 0
-
-#define wlc_lcnphy_tx_gain_override_enabled(pi) \
- (0 != (read_phy_reg((pi), 0x43b) & (0x1 << 6)))
-
-#define wlc_lcnphy_total_tx_frames(pi) \
- wlapi_bmac_read_shm((pi)->sh->physhim, M_UCODE_MACSTAT + offsetof(macstat_t, txallfrm))
-
-typedef struct {
- u16 gm_gain;
- u16 pga_gain;
- u16 pad_gain;
- u16 dac_gain;
-} lcnphy_txgains_t;
-
-typedef enum {
- LCNPHY_CAL_FULL,
- LCNPHY_CAL_RECAL,
- LCNPHY_CAL_CURRECAL,
- LCNPHY_CAL_DIGCAL,
- LCNPHY_CAL_GCTRL
-} lcnphy_cal_mode_t;
-
-typedef struct {
- lcnphy_txgains_t gains;
- bool useindex;
- u8 index;
-} lcnphy_txcalgains_t;
-
-typedef struct {
- u8 chan;
- s16 a;
- s16 b;
-} lcnphy_rx_iqcomp_t;
-
-typedef struct {
- s16 re;
- s16 im;
-} lcnphy_spb_tone_t;
-
-typedef struct {
- u16 re;
- u16 im;
-} lcnphy_unsign16_struct;
-
-typedef struct {
- u32 iq_prod;
- u32 i_pwr;
- u32 q_pwr;
-} lcnphy_iq_est_t;
-
-typedef struct {
- u16 ptcentreTs20;
- u16 ptcentreFactor;
-} lcnphy_sfo_cfg_t;
-
-typedef enum {
- LCNPHY_PAPD_CAL_CW,
- LCNPHY_PAPD_CAL_OFDM
-} lcnphy_papd_cal_type_t;
-
-typedef u16 iqcal_gain_params_lcnphy[9];
-
-static const iqcal_gain_params_lcnphy tbl_iqcal_gainparams_lcnphy_2G[] = {
- {0, 0, 0, 0, 0, 0, 0, 0, 0},
-};
-
-static const iqcal_gain_params_lcnphy *tbl_iqcal_gainparams_lcnphy[1] = {
- tbl_iqcal_gainparams_lcnphy_2G,
-};
-
-static const u16 iqcal_gainparams_numgains_lcnphy[1] = {
- sizeof(tbl_iqcal_gainparams_lcnphy_2G) /
- sizeof(*tbl_iqcal_gainparams_lcnphy_2G),
-};
-
-static const lcnphy_sfo_cfg_t lcnphy_sfo_cfg[] = {
- {965, 1087},
- {967, 1085},
- {969, 1082},
- {971, 1080},
- {973, 1078},
- {975, 1076},
- {977, 1073},
- {979, 1071},
- {981, 1069},
- {983, 1067},
- {985, 1065},
- {987, 1063},
- {989, 1060},
- {994, 1055}
-};
-
-static const
-u16 lcnphy_iqcal_loft_gainladder[] = {
- ((2 << 8) | 0),
- ((3 << 8) | 0),
- ((4 << 8) | 0),
- ((6 << 8) | 0),
- ((8 << 8) | 0),
- ((11 << 8) | 0),
- ((16 << 8) | 0),
- ((16 << 8) | 1),
- ((16 << 8) | 2),
- ((16 << 8) | 3),
- ((16 << 8) | 4),
- ((16 << 8) | 5),
- ((16 << 8) | 6),
- ((16 << 8) | 7),
- ((23 << 8) | 7),
- ((32 << 8) | 7),
- ((45 << 8) | 7),
- ((64 << 8) | 7),
- ((91 << 8) | 7),
- ((128 << 8) | 7)
-};
-
-static const
-u16 lcnphy_iqcal_ir_gainladder[] = {
- ((1 << 8) | 0),
- ((2 << 8) | 0),
- ((4 << 8) | 0),
- ((6 << 8) | 0),
- ((8 << 8) | 0),
- ((11 << 8) | 0),
- ((16 << 8) | 0),
- ((23 << 8) | 0),
- ((32 << 8) | 0),
- ((45 << 8) | 0),
- ((64 << 8) | 0),
- ((64 << 8) | 1),
- ((64 << 8) | 2),
- ((64 << 8) | 3),
- ((64 << 8) | 4),
- ((64 << 8) | 5),
- ((64 << 8) | 6),
- ((64 << 8) | 7),
- ((91 << 8) | 7),
- ((128 << 8) | 7)
-};
-
-static const
-lcnphy_spb_tone_t lcnphy_spb_tone_3750[] = {
- {88, 0},
- {73, 49},
- {34, 81},
- {-17, 86},
- {-62, 62},
- {-86, 17},
- {-81, -34},
- {-49, -73},
- {0, -88},
- {49, -73},
- {81, -34},
- {86, 17},
- {62, 62},
- {17, 86},
- {-34, 81},
- {-73, 49},
- {-88, 0},
- {-73, -49},
- {-34, -81},
- {17, -86},
- {62, -62},
- {86, -17},
- {81, 34},
- {49, 73},
- {0, 88},
- {-49, 73},
- {-81, 34},
- {-86, -17},
- {-62, -62},
- {-17, -86},
- {34, -81},
- {73, -49},
-};
-
-static const
-u16 iqlo_loopback_rf_regs[20] = {
- RADIO_2064_REG036,
- RADIO_2064_REG11A,
- RADIO_2064_REG03A,
- RADIO_2064_REG025,
- RADIO_2064_REG028,
- RADIO_2064_REG005,
- RADIO_2064_REG112,
- RADIO_2064_REG0FF,
- RADIO_2064_REG11F,
- RADIO_2064_REG00B,
- RADIO_2064_REG113,
- RADIO_2064_REG007,
- RADIO_2064_REG0FC,
- RADIO_2064_REG0FD,
- RADIO_2064_REG012,
- RADIO_2064_REG057,
- RADIO_2064_REG059,
- RADIO_2064_REG05C,
- RADIO_2064_REG078,
- RADIO_2064_REG092,
-};
-
-static const
-u16 tempsense_phy_regs[14] = {
- 0x503,
- 0x4a4,
- 0x4d0,
- 0x4d9,
- 0x4da,
- 0x4a6,
- 0x938,
- 0x939,
- 0x4d8,
- 0x4d0,
- 0x4d7,
- 0x4a5,
- 0x40d,
- 0x4a2,
-};
-
-static const
-u16 rxiq_cal_rf_reg[11] = {
- RADIO_2064_REG098,
- RADIO_2064_REG116,
- RADIO_2064_REG12C,
- RADIO_2064_REG06A,
- RADIO_2064_REG00B,
- RADIO_2064_REG01B,
- RADIO_2064_REG113,
- RADIO_2064_REG01D,
- RADIO_2064_REG114,
- RADIO_2064_REG02E,
- RADIO_2064_REG12A,
-};
-
-static const
-lcnphy_rx_iqcomp_t lcnphy_rx_iqcomp_table_rev0[] = {
- {1, 0, 0},
- {2, 0, 0},
- {3, 0, 0},
- {4, 0, 0},
- {5, 0, 0},
- {6, 0, 0},
- {7, 0, 0},
- {8, 0, 0},
- {9, 0, 0},
- {10, 0, 0},
- {11, 0, 0},
- {12, 0, 0},
- {13, 0, 0},
- {14, 0, 0},
- {34, 0, 0},
- {38, 0, 0},
- {42, 0, 0},
- {46, 0, 0},
- {36, 0, 0},
- {40, 0, 0},
- {44, 0, 0},
- {48, 0, 0},
- {52, 0, 0},
- {56, 0, 0},
- {60, 0, 0},
- {64, 0, 0},
- {100, 0, 0},
- {104, 0, 0},
- {108, 0, 0},
- {112, 0, 0},
- {116, 0, 0},
- {120, 0, 0},
- {124, 0, 0},
- {128, 0, 0},
- {132, 0, 0},
- {136, 0, 0},
- {140, 0, 0},
- {149, 0, 0},
- {153, 0, 0},
- {157, 0, 0},
- {161, 0, 0},
- {165, 0, 0},
- {184, 0, 0},
- {188, 0, 0},
- {192, 0, 0},
- {196, 0, 0},
- {200, 0, 0},
- {204, 0, 0},
- {208, 0, 0},
- {212, 0, 0},
- {216, 0, 0},
-};
-
-static const u32 lcnphy_23bitgaincode_table[] = {
- 0x200100,
- 0x200200,
- 0x200004,
- 0x200014,
- 0x200024,
- 0x200034,
- 0x200134,
- 0x200234,
- 0x200334,
- 0x200434,
- 0x200037,
- 0x200137,
- 0x200237,
- 0x200337,
- 0x200437,
- 0x000035,
- 0x000135,
- 0x000235,
- 0x000037,
- 0x000137,
- 0x000237,
- 0x000337,
- 0x00013f,
- 0x00023f,
- 0x00033f,
- 0x00034f,
- 0x00044f,
- 0x00144f,
- 0x00244f,
- 0x00254f,
- 0x00354f,
- 0x00454f,
- 0x00464f,
- 0x01464f,
- 0x02464f,
- 0x03464f,
- 0x04464f,
-};
-
-static const s8 lcnphy_gain_table[] = {
- -16,
- -13,
- 10,
- 7,
- 4,
- 0,
- 3,
- 6,
- 9,
- 12,
- 15,
- 18,
- 21,
- 24,
- 27,
- 30,
- 33,
- 36,
- 39,
- 42,
- 45,
- 48,
- 50,
- 53,
- 56,
- 59,
- 62,
- 65,
- 68,
- 71,
- 74,
- 77,
- 80,
- 83,
- 86,
- 89,
- 92,
-};
-
-static const s8 lcnphy_gain_index_offset_for_rssi[] = {
- 7,
- 7,
- 7,
- 7,
- 7,
- 7,
- 7,
- 8,
- 7,
- 7,
- 6,
- 7,
- 7,
- 4,
- 4,
- 4,
- 4,
- 4,
- 4,
- 4,
- 4,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 4,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- -1,
- -2,
- -2,
- -2
-};
-
-extern const u8 spur_tbl_rev0[];
-extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev1;
-extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev1[];
-extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa;
-extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250;
-
-typedef struct _chan_info_2064_lcnphy {
- uint chan;
- uint freq;
- u8 logen_buftune;
- u8 logen_rccr_tx;
- u8 txrf_mix_tune_ctrl;
- u8 pa_input_tune_g;
- u8 logen_rccr_rx;
- u8 pa_rxrf_lna1_freq_tune;
- u8 pa_rxrf_lna2_freq_tune;
- u8 rxrf_rxrf_spare1;
-} chan_info_2064_lcnphy_t;
-
-static chan_info_2064_lcnphy_t chan_info_2064_lcnphy[] = {
- {1, 2412, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {2, 2417, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {3, 2422, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {4, 2427, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {5, 2432, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {6, 2437, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {7, 2442, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {8, 2447, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {9, 2452, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {10, 2457, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {11, 2462, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {12, 2467, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {13, 2472, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
- {14, 2484, 0x0B, 0x0A, 0x00, 0x07, 0x0A, 0x88, 0x88, 0x80},
-};
-
-lcnphy_radio_regs_t lcnphy_radio_regs_2064[] = {
- {0x00, 0, 0, 0, 0},
- {0x01, 0x64, 0x64, 0, 0},
- {0x02, 0x20, 0x20, 0, 0},
- {0x03, 0x66, 0x66, 0, 0},
- {0x04, 0xf8, 0xf8, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0x10, 0x10, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0x37, 0x37, 0, 0},
- {0x0B, 0x6, 0x6, 0, 0},
- {0x0C, 0x55, 0x55, 0, 0},
- {0x0D, 0x8b, 0x8b, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0x5, 0x5, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0xe, 0xe, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0xb, 0xb, 0, 0},
- {0x14, 0x2, 0x2, 0, 0},
- {0x15, 0x12, 0x12, 0, 0},
- {0x16, 0x12, 0x12, 0, 0},
- {0x17, 0xc, 0xc, 0, 0},
- {0x18, 0xc, 0xc, 0, 0},
- {0x19, 0xc, 0xc, 0, 0},
- {0x1A, 0x8, 0x8, 0, 0},
- {0x1B, 0x2, 0x2, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0x1, 0x1, 0, 0},
- {0x1E, 0x12, 0x12, 0, 0},
- {0x1F, 0x6e, 0x6e, 0, 0},
- {0x20, 0x2, 0x2, 0, 0},
- {0x21, 0x23, 0x23, 0, 0},
- {0x22, 0x8, 0x8, 0, 0},
- {0x23, 0, 0, 0, 0},
- {0x24, 0, 0, 0, 0},
- {0x25, 0xc, 0xc, 0, 0},
- {0x26, 0x33, 0x33, 0, 0},
- {0x27, 0x55, 0x55, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0x30, 0x30, 0, 0},
- {0x2A, 0xb, 0xb, 0, 0},
- {0x2B, 0x1b, 0x1b, 0, 0},
- {0x2C, 0x3, 0x3, 0, 0},
- {0x2D, 0x1b, 0x1b, 0, 0},
- {0x2E, 0, 0, 0, 0},
- {0x2F, 0x20, 0x20, 0, 0},
- {0x30, 0xa, 0xa, 0, 0},
- {0x31, 0, 0, 0, 0},
- {0x32, 0x62, 0x62, 0, 0},
- {0x33, 0x19, 0x19, 0, 0},
- {0x34, 0x33, 0x33, 0, 0},
- {0x35, 0x77, 0x77, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0x70, 0x70, 0, 0},
- {0x38, 0x3, 0x3, 0, 0},
- {0x39, 0xf, 0xf, 0, 0},
- {0x3A, 0x6, 0x6, 0, 0},
- {0x3B, 0xcf, 0xcf, 0, 0},
- {0x3C, 0x1a, 0x1a, 0, 0},
- {0x3D, 0x6, 0x6, 0, 0},
- {0x3E, 0x42, 0x42, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0xfb, 0xfb, 0, 0},
- {0x41, 0x9a, 0x9a, 0, 0},
- {0x42, 0x7a, 0x7a, 0, 0},
- {0x43, 0x29, 0x29, 0, 0},
- {0x44, 0, 0, 0, 0},
- {0x45, 0x8, 0x8, 0, 0},
- {0x46, 0xce, 0xce, 0, 0},
- {0x47, 0x27, 0x27, 0, 0},
- {0x48, 0x62, 0x62, 0, 0},
- {0x49, 0x6, 0x6, 0, 0},
- {0x4A, 0x58, 0x58, 0, 0},
- {0x4B, 0xf7, 0xf7, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0xb3, 0xb3, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0x2, 0x2, 0, 0},
- {0x50, 0, 0, 0, 0},
- {0x51, 0x9, 0x9, 0, 0},
- {0x52, 0x5, 0x5, 0, 0},
- {0x53, 0x17, 0x17, 0, 0},
- {0x54, 0x38, 0x38, 0, 0},
- {0x55, 0, 0, 0, 0},
- {0x56, 0, 0, 0, 0},
- {0x57, 0xb, 0xb, 0, 0},
- {0x58, 0, 0, 0, 0},
- {0x59, 0, 0, 0, 0},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0, 0, 0, 0},
- {0x5C, 0, 0, 0, 0},
- {0x5D, 0, 0, 0, 0},
- {0x5E, 0x88, 0x88, 0, 0},
- {0x5F, 0xcc, 0xcc, 0, 0},
- {0x60, 0x74, 0x74, 0, 0},
- {0x61, 0x74, 0x74, 0, 0},
- {0x62, 0x74, 0x74, 0, 0},
- {0x63, 0x44, 0x44, 0, 0},
- {0x64, 0x77, 0x77, 0, 0},
- {0x65, 0x44, 0x44, 0, 0},
- {0x66, 0x77, 0x77, 0, 0},
- {0x67, 0x55, 0x55, 0, 0},
- {0x68, 0x77, 0x77, 0, 0},
- {0x69, 0x77, 0x77, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0x7f, 0x7f, 0, 0},
- {0x6C, 0x8, 0x8, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0x88, 0x88, 0, 0},
- {0x6F, 0x66, 0x66, 0, 0},
- {0x70, 0x66, 0x66, 0, 0},
- {0x71, 0x28, 0x28, 0, 0},
- {0x72, 0x55, 0x55, 0, 0},
- {0x73, 0x4, 0x4, 0, 0},
- {0x74, 0, 0, 0, 0},
- {0x75, 0, 0, 0, 0},
- {0x76, 0, 0, 0, 0},
- {0x77, 0x1, 0x1, 0, 0},
- {0x78, 0xd6, 0xd6, 0, 0},
- {0x79, 0, 0, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0xb4, 0xb4, 0, 0},
- {0x84, 0x1, 0x1, 0, 0},
- {0x85, 0x20, 0x20, 0, 0},
- {0x86, 0x5, 0x5, 0, 0},
- {0x87, 0xff, 0xff, 0, 0},
- {0x88, 0x7, 0x7, 0, 0},
- {0x89, 0x77, 0x77, 0, 0},
- {0x8A, 0x77, 0x77, 0, 0},
- {0x8B, 0x77, 0x77, 0, 0},
- {0x8C, 0x77, 0x77, 0, 0},
- {0x8D, 0x8, 0x8, 0, 0},
- {0x8E, 0xa, 0xa, 0, 0},
- {0x8F, 0x8, 0x8, 0, 0},
- {0x90, 0x18, 0x18, 0, 0},
- {0x91, 0x5, 0x5, 0, 0},
- {0x92, 0x1f, 0x1f, 0, 0},
- {0x93, 0x10, 0x10, 0, 0},
- {0x94, 0x3, 0x3, 0, 0},
- {0x95, 0, 0, 0, 0},
- {0x96, 0, 0, 0, 0},
- {0x97, 0xaa, 0xaa, 0, 0},
- {0x98, 0, 0, 0, 0},
- {0x99, 0x23, 0x23, 0, 0},
- {0x9A, 0x7, 0x7, 0, 0},
- {0x9B, 0xf, 0xf, 0, 0},
- {0x9C, 0x10, 0x10, 0, 0},
- {0x9D, 0x3, 0x3, 0, 0},
- {0x9E, 0x4, 0x4, 0, 0},
- {0x9F, 0x20, 0x20, 0, 0},
- {0xA0, 0, 0, 0, 0},
- {0xA1, 0, 0, 0, 0},
- {0xA2, 0, 0, 0, 0},
- {0xA3, 0, 0, 0, 0},
- {0xA4, 0x1, 0x1, 0, 0},
- {0xA5, 0x77, 0x77, 0, 0},
- {0xA6, 0x77, 0x77, 0, 0},
- {0xA7, 0x77, 0x77, 0, 0},
- {0xA8, 0x77, 0x77, 0, 0},
- {0xA9, 0x8c, 0x8c, 0, 0},
- {0xAA, 0x88, 0x88, 0, 0},
- {0xAB, 0x78, 0x78, 0, 0},
- {0xAC, 0x57, 0x57, 0, 0},
- {0xAD, 0x88, 0x88, 0, 0},
- {0xAE, 0, 0, 0, 0},
- {0xAF, 0x8, 0x8, 0, 0},
- {0xB0, 0x88, 0x88, 0, 0},
- {0xB1, 0, 0, 0, 0},
- {0xB2, 0x1b, 0x1b, 0, 0},
- {0xB3, 0x3, 0x3, 0, 0},
- {0xB4, 0x24, 0x24, 0, 0},
- {0xB5, 0x3, 0x3, 0, 0},
- {0xB6, 0x1b, 0x1b, 0, 0},
- {0xB7, 0x24, 0x24, 0, 0},
- {0xB8, 0x3, 0x3, 0, 0},
- {0xB9, 0, 0, 0, 0},
- {0xBA, 0xaa, 0xaa, 0, 0},
- {0xBB, 0, 0, 0, 0},
- {0xBC, 0x4, 0x4, 0, 0},
- {0xBD, 0, 0, 0, 0},
- {0xBE, 0x8, 0x8, 0, 0},
- {0xBF, 0x11, 0x11, 0, 0},
- {0xC0, 0, 0, 0, 0},
- {0xC1, 0, 0, 0, 0},
- {0xC2, 0x62, 0x62, 0, 0},
- {0xC3, 0x1e, 0x1e, 0, 0},
- {0xC4, 0x33, 0x33, 0, 0},
- {0xC5, 0x37, 0x37, 0, 0},
- {0xC6, 0, 0, 0, 0},
- {0xC7, 0x70, 0x70, 0, 0},
- {0xC8, 0x1e, 0x1e, 0, 0},
- {0xC9, 0x6, 0x6, 0, 0},
- {0xCA, 0x4, 0x4, 0, 0},
- {0xCB, 0x2f, 0x2f, 0, 0},
- {0xCC, 0xf, 0xf, 0, 0},
- {0xCD, 0, 0, 0, 0},
- {0xCE, 0xff, 0xff, 0, 0},
- {0xCF, 0x8, 0x8, 0, 0},
- {0xD0, 0x3f, 0x3f, 0, 0},
- {0xD1, 0x3f, 0x3f, 0, 0},
- {0xD2, 0x3f, 0x3f, 0, 0},
- {0xD3, 0, 0, 0, 0},
- {0xD4, 0, 0, 0, 0},
- {0xD5, 0, 0, 0, 0},
- {0xD6, 0xcc, 0xcc, 0, 0},
- {0xD7, 0, 0, 0, 0},
- {0xD8, 0x8, 0x8, 0, 0},
- {0xD9, 0x8, 0x8, 0, 0},
- {0xDA, 0x8, 0x8, 0, 0},
- {0xDB, 0x11, 0x11, 0, 0},
- {0xDC, 0, 0, 0, 0},
- {0xDD, 0x87, 0x87, 0, 0},
- {0xDE, 0x88, 0x88, 0, 0},
- {0xDF, 0x8, 0x8, 0, 0},
- {0xE0, 0x8, 0x8, 0, 0},
- {0xE1, 0x8, 0x8, 0, 0},
- {0xE2, 0, 0, 0, 0},
- {0xE3, 0, 0, 0, 0},
- {0xE4, 0, 0, 0, 0},
- {0xE5, 0xf5, 0xf5, 0, 0},
- {0xE6, 0x30, 0x30, 0, 0},
- {0xE7, 0x1, 0x1, 0, 0},
- {0xE8, 0, 0, 0, 0},
- {0xE9, 0xff, 0xff, 0, 0},
- {0xEA, 0, 0, 0, 0},
- {0xEB, 0, 0, 0, 0},
- {0xEC, 0x22, 0x22, 0, 0},
- {0xED, 0, 0, 0, 0},
- {0xEE, 0, 0, 0, 0},
- {0xEF, 0, 0, 0, 0},
- {0xF0, 0x3, 0x3, 0, 0},
- {0xF1, 0x1, 0x1, 0, 0},
- {0xF2, 0, 0, 0, 0},
- {0xF3, 0, 0, 0, 0},
- {0xF4, 0, 0, 0, 0},
- {0xF5, 0, 0, 0, 0},
- {0xF6, 0, 0, 0, 0},
- {0xF7, 0x6, 0x6, 0, 0},
- {0xF8, 0, 0, 0, 0},
- {0xF9, 0, 0, 0, 0},
- {0xFA, 0x40, 0x40, 0, 0},
- {0xFB, 0, 0, 0, 0},
- {0xFC, 0x1, 0x1, 0, 0},
- {0xFD, 0x80, 0x80, 0, 0},
- {0xFE, 0x2, 0x2, 0, 0},
- {0xFF, 0x10, 0x10, 0, 0},
- {0x100, 0x2, 0x2, 0, 0},
- {0x101, 0x1e, 0x1e, 0, 0},
- {0x102, 0x1e, 0x1e, 0, 0},
- {0x103, 0, 0, 0, 0},
- {0x104, 0x1f, 0x1f, 0, 0},
- {0x105, 0, 0x8, 0, 1},
- {0x106, 0x2a, 0x2a, 0, 0},
- {0x107, 0xf, 0xf, 0, 0},
- {0x108, 0, 0, 0, 0},
- {0x109, 0, 0, 0, 0},
- {0x10A, 0, 0, 0, 0},
- {0x10B, 0, 0, 0, 0},
- {0x10C, 0, 0, 0, 0},
- {0x10D, 0, 0, 0, 0},
- {0x10E, 0, 0, 0, 0},
- {0x10F, 0, 0, 0, 0},
- {0x110, 0, 0, 0, 0},
- {0x111, 0, 0, 0, 0},
- {0x112, 0, 0, 0, 0},
- {0x113, 0, 0, 0, 0},
- {0x114, 0, 0, 0, 0},
- {0x115, 0, 0, 0, 0},
- {0x116, 0, 0, 0, 0},
- {0x117, 0, 0, 0, 0},
- {0x118, 0, 0, 0, 0},
- {0x119, 0, 0, 0, 0},
- {0x11A, 0, 0, 0, 0},
- {0x11B, 0, 0, 0, 0},
- {0x11C, 0x1, 0x1, 0, 0},
- {0x11D, 0, 0, 0, 0},
- {0x11E, 0, 0, 0, 0},
- {0x11F, 0, 0, 0, 0},
- {0x120, 0, 0, 0, 0},
- {0x121, 0, 0, 0, 0},
- {0x122, 0x80, 0x80, 0, 0},
- {0x123, 0, 0, 0, 0},
- {0x124, 0xf8, 0xf8, 0, 0},
- {0x125, 0, 0, 0, 0},
- {0x126, 0, 0, 0, 0},
- {0x127, 0, 0, 0, 0},
- {0x128, 0, 0, 0, 0},
- {0x129, 0, 0, 0, 0},
- {0x12A, 0, 0, 0, 0},
- {0x12B, 0, 0, 0, 0},
- {0x12C, 0, 0, 0, 0},
- {0x12D, 0, 0, 0, 0},
- {0x12E, 0, 0, 0, 0},
- {0x12F, 0, 0, 0, 0},
- {0x130, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-#define LCNPHY_NUM_DIG_FILT_COEFFS 16
-#define LCNPHY_NUM_TX_DIG_FILTERS_CCK 13
-
-u16
- LCNPHY_txdigfiltcoeffs_cck[LCNPHY_NUM_TX_DIG_FILTERS_CCK]
- [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = {
- {0, 1, 415, 1874, 64, 128, 64, 792, 1656, 64, 128, 64, 778, 1582, 64,
- 128, 64,},
- {1, 1, 402, 1847, 259, 59, 259, 671, 1794, 68, 54, 68, 608, 1863, 93,
- 167, 93,},
- {2, 1, 415, 1874, 64, 128, 64, 792, 1656, 192, 384, 192, 778, 1582, 64,
- 128, 64,},
- {3, 1, 302, 1841, 129, 258, 129, 658, 1720, 205, 410, 205, 754, 1760,
- 170, 340, 170,},
- {20, 1, 360, 1884, 242, 1734, 242, 752, 1720, 205, 1845, 205, 767, 1760,
- 256, 185, 256,},
- {21, 1, 360, 1884, 149, 1874, 149, 752, 1720, 205, 1883, 205, 767, 1760,
- 256, 273, 256,},
- {22, 1, 360, 1884, 98, 1948, 98, 752, 1720, 205, 1924, 205, 767, 1760,
- 256, 352, 256,},
- {23, 1, 350, 1884, 116, 1966, 116, 752, 1720, 205, 2008, 205, 767, 1760,
- 128, 233, 128,},
- {24, 1, 325, 1884, 32, 40, 32, 756, 1720, 256, 471, 256, 766, 1760, 256,
- 1881, 256,},
- {25, 1, 299, 1884, 51, 64, 51, 736, 1720, 256, 471, 256, 765, 1760, 256,
- 1881, 256,},
- {26, 1, 277, 1943, 39, 117, 88, 637, 1838, 64, 192, 144, 614, 1864, 128,
- 384, 288,},
- {27, 1, 245, 1943, 49, 147, 110, 626, 1838, 256, 768, 576, 613, 1864,
- 128, 384, 288,},
- {30, 1, 302, 1841, 61, 122, 61, 658, 1720, 205, 410, 205, 754, 1760,
- 170, 340, 170,},
-};
-
-#define LCNPHY_NUM_TX_DIG_FILTERS_OFDM 3
-u16
- LCNPHY_txdigfiltcoeffs_ofdm[LCNPHY_NUM_TX_DIG_FILTERS_OFDM]
- [LCNPHY_NUM_DIG_FILT_COEFFS + 1] = {
- {0, 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0, 0x0,
- 0x278, 0xfea0, 0x80, 0x100, 0x80,},
- {1, 0, 374, 0xFF79, 16, 32, 16, 799, 0xFE74, 50, 32, 50,
- 750, 0xFE2B, 212, 0xFFCE, 212,},
- {2, 0, 375, 0xFF16, 37, 76, 37, 799, 0xFE74, 32, 20, 32, 748,
- 0xFEF2, 128, 0xFFE2, 128}
-};
-
-#define wlc_lcnphy_set_start_tx_pwr_idx(pi, idx) \
- mod_phy_reg(pi, 0x4a4, \
- (0x1ff << 0), \
- (u16)(idx) << 0)
-
-#define wlc_lcnphy_set_tx_pwr_npt(pi, npt) \
- mod_phy_reg(pi, 0x4a5, \
- (0x7 << 8), \
- (u16)(npt) << 8)
-
-#define wlc_lcnphy_get_tx_pwr_ctrl(pi) \
- (read_phy_reg((pi), 0x4a4) & \
- ((0x1 << 15) | \
- (0x1 << 14) | \
- (0x1 << 13)))
-
-#define wlc_lcnphy_get_tx_pwr_npt(pi) \
- ((read_phy_reg(pi, 0x4a5) & \
- (0x7 << 8)) >> \
- 8)
-
-#define wlc_lcnphy_get_current_tx_pwr_idx_if_pwrctrl_on(pi) \
- (read_phy_reg(pi, 0x473) & 0x1ff)
-
-#define wlc_lcnphy_get_target_tx_pwr(pi) \
- ((read_phy_reg(pi, 0x4a7) & \
- (0xff << 0)) >> \
- 0)
-
-#define wlc_lcnphy_set_target_tx_pwr(pi, target) \
- mod_phy_reg(pi, 0x4a7, \
- (0xff << 0), \
- (u16)(target) << 0)
-
-#define wlc_radio_2064_rcal_done(pi) (0 != (read_radio_reg(pi, RADIO_2064_REG05C) & 0x20))
-#define tempsense_done(pi) (0x8000 == (read_phy_reg(pi, 0x476) & 0x8000))
-
-#define LCNPHY_IQLOCC_READ(val) ((u8)(-(s8)(((val) & 0xf0) >> 4) + (s8)((val) & 0x0f)))
-#define FIXED_TXPWR 78
-#define LCNPHY_TEMPSENSE(val) ((s16)((val > 255) ? (val - 512) : val))
-
-static u32 wlc_lcnphy_qdiv_roundup(u32 divident, u32 divisor,
- u8 precision);
-static void wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi,
- u16 ext_lna, u16 trsw,
- u16 biq2, u16 biq1,
- u16 tia, u16 lna2,
- u16 lna1);
-static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi);
-static void wlc_lcnphy_set_pa_gain(phy_info_t *pi, u16 gain);
-static void wlc_lcnphy_set_trsw_override(phy_info_t *pi, bool tx, bool rx);
-static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0);
-static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi);
-static void wlc_lcnphy_get_tx_gain(phy_info_t *pi, lcnphy_txgains_t *gains);
-static void wlc_lcnphy_set_tx_gain_override(phy_info_t *pi, bool bEnable);
-static void wlc_lcnphy_toggle_afe_pwdn(phy_info_t *pi);
-static void wlc_lcnphy_rx_gain_override_enable(phy_info_t *pi, bool enable);
-static void wlc_lcnphy_set_tx_gain(phy_info_t *pi,
- lcnphy_txgains_t *target_gains);
-static bool wlc_lcnphy_rx_iq_est(phy_info_t *pi, u16 num_samps,
- u8 wait_time, lcnphy_iq_est_t *iq_est);
-static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps);
-static u16 wlc_lcnphy_get_pa_gain(phy_info_t *pi);
-static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode);
-extern void wlc_lcnphy_tx_pwr_ctrl_init(wlc_phy_t *ppi);
-static void wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi,
- u8 channel);
-
-static void wlc_lcnphy_load_tx_gain_table(phy_info_t *pi,
- const lcnphy_tx_gain_tbl_entry *g);
-
-static void wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo,
- u16 thresh, s16 *ptr, int mode);
-static int wlc_lcnphy_calc_floor(s16 coeff, int type);
-static void wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi,
- u16 *values_to_save);
-static void wlc_lcnphy_tx_iqlo_loopback_cleanup(phy_info_t *pi,
- u16 *values_to_save);
-static void wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, s16 coeff_x,
- s16 coeff_y);
-static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type);
-static void wlc_lcnphy_a1(phy_info_t *pi, int cal_type,
- int num_levels, int step_size_lg2);
-static void wlc_lcnphy_tx_iqlo_soft_cal_full(phy_info_t *pi);
-
-static void wlc_lcnphy_set_chanspec_tweaks(phy_info_t *pi,
- chanspec_t chanspec);
-static void wlc_lcnphy_agc_temp_init(phy_info_t *pi);
-static void wlc_lcnphy_temp_adj(phy_info_t *pi);
-static void wlc_lcnphy_clear_papd_comptable(phy_info_t *pi);
-static void wlc_lcnphy_baseband_init(phy_info_t *pi);
-static void wlc_lcnphy_radio_init(phy_info_t *pi);
-static void wlc_lcnphy_rc_cal(phy_info_t *pi);
-static void wlc_lcnphy_rcal(phy_info_t *pi);
-static void wlc_lcnphy_txrx_spur_avoidance_mode(phy_info_t *pi, bool enable);
-static int wlc_lcnphy_load_tx_iir_filter(phy_info_t *pi, bool is_ofdm,
- s16 filt_type);
-static void wlc_lcnphy_set_rx_iq_comp(phy_info_t *pi, u16 a, u16 b);
-
-void wlc_lcnphy_write_table(phy_info_t *pi, const phytbl_info_t *pti)
-{
- wlc_phy_write_table(pi, pti, 0x455, 0x457, 0x456);
-}
-
-void wlc_lcnphy_read_table(phy_info_t *pi, phytbl_info_t *pti)
-{
- wlc_phy_read_table(pi, pti, 0x455, 0x457, 0x456);
-}
-
-static void
-wlc_lcnphy_common_read_table(phy_info_t *pi, u32 tbl_id,
- const void *tbl_ptr, u32 tbl_len,
- u32 tbl_width, u32 tbl_offset)
-{
- phytbl_info_t tab;
- tab.tbl_id = tbl_id;
- tab.tbl_ptr = tbl_ptr;
- tab.tbl_len = tbl_len;
- tab.tbl_width = tbl_width;
- tab.tbl_offset = tbl_offset;
- wlc_lcnphy_read_table(pi, &tab);
-}
-
-static void
-wlc_lcnphy_common_write_table(phy_info_t *pi, u32 tbl_id,
- const void *tbl_ptr, u32 tbl_len,
- u32 tbl_width, u32 tbl_offset)
-{
-
- phytbl_info_t tab;
- tab.tbl_id = tbl_id;
- tab.tbl_ptr = tbl_ptr;
- tab.tbl_len = tbl_len;
- tab.tbl_width = tbl_width;
- tab.tbl_offset = tbl_offset;
- wlc_lcnphy_write_table(pi, &tab);
-}
-
-static u32
-wlc_lcnphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
-{
- u32 quotient, remainder, roundup, rbit;
-
- quotient = dividend / divisor;
- remainder = dividend % divisor;
- rbit = divisor & 1;
- roundup = (divisor >> 1) + rbit;
-
- while (precision--) {
- quotient <<= 1;
- if (remainder >= roundup) {
- quotient++;
- remainder = ((remainder - roundup) << 1) + rbit;
- } else {
- remainder <<= 1;
- }
- }
-
- if (remainder >= roundup)
- quotient++;
-
- return quotient;
-}
-
-static int wlc_lcnphy_calc_floor(s16 coeff_x, int type)
-{
- int k;
- k = 0;
- if (type == 0) {
- if (coeff_x < 0) {
- k = (coeff_x - 1) / 2;
- } else {
- k = coeff_x / 2;
- }
- }
- if (type == 1) {
- if ((coeff_x + 1) < 0)
- k = (coeff_x) / 2;
- else
- k = (coeff_x + 1) / 2;
- }
- return k;
-}
-
-s8 wlc_lcnphy_get_current_tx_pwr_idx(phy_info_t *pi)
-{
- s8 index;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (txpwrctrl_off(pi))
- index = pi_lcn->lcnphy_current_index;
- else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
- index =
- (s8) (wlc_lcnphy_get_current_tx_pwr_idx_if_pwrctrl_on(pi)
- / 2);
- else
- index = pi_lcn->lcnphy_current_index;
- return index;
-}
-
-static u32 wlc_lcnphy_measure_digital_power(phy_info_t *pi, u16 nsamples)
-{
- lcnphy_iq_est_t iq_est = { 0, 0, 0 };
-
- if (!wlc_lcnphy_rx_iq_est(pi, nsamples, 32, &iq_est))
- return 0;
- return (iq_est.i_pwr + iq_est.q_pwr) / nsamples;
-}
-
-void wlc_lcnphy_crsuprs(phy_info_t *pi, int channel)
-{
- u16 afectrlovr, afectrlovrval;
- afectrlovr = read_phy_reg(pi, 0x43b);
- afectrlovrval = read_phy_reg(pi, 0x43c);
- if (channel != 0) {
- mod_phy_reg(pi, 0x43b, (0x1 << 1), (1) << 1);
-
- mod_phy_reg(pi, 0x43c, (0x1 << 1), (0) << 1);
-
- mod_phy_reg(pi, 0x43b, (0x1 << 4), (1) << 4);
-
- mod_phy_reg(pi, 0x43c, (0x1 << 6), (0) << 6);
-
- write_phy_reg(pi, 0x44b, 0xffff);
- wlc_lcnphy_tx_pu(pi, 1);
-
- mod_phy_reg(pi, 0x634, (0xff << 8), (0) << 8);
-
- or_phy_reg(pi, 0x6da, 0x0080);
-
- or_phy_reg(pi, 0x00a, 0x228);
- } else {
- and_phy_reg(pi, 0x00a, ~(0x228));
-
- and_phy_reg(pi, 0x6da, 0xFF7F);
- write_phy_reg(pi, 0x43b, afectrlovr);
- write_phy_reg(pi, 0x43c, afectrlovrval);
- }
-}
-
-static void wlc_lcnphy_toggle_afe_pwdn(phy_info_t *pi)
-{
- u16 save_AfeCtrlOvrVal, save_AfeCtrlOvr;
-
- save_AfeCtrlOvrVal = read_phy_reg(pi, 0x43c);
- save_AfeCtrlOvr = read_phy_reg(pi, 0x43b);
-
- write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal | 0x1);
- write_phy_reg(pi, 0x43b, save_AfeCtrlOvr | 0x1);
-
- write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal & 0xfffe);
- write_phy_reg(pi, 0x43b, save_AfeCtrlOvr & 0xfffe);
-
- write_phy_reg(pi, 0x43c, save_AfeCtrlOvrVal);
- write_phy_reg(pi, 0x43b, save_AfeCtrlOvr);
-}
-
-static void wlc_lcnphy_txrx_spur_avoidance_mode(phy_info_t *pi, bool enable)
-{
- if (enable) {
- write_phy_reg(pi, 0x942, 0x7);
- write_phy_reg(pi, 0x93b, ((1 << 13) + 23));
- write_phy_reg(pi, 0x93c, ((1 << 13) + 1989));
-
- write_phy_reg(pi, 0x44a, 0x084);
- write_phy_reg(pi, 0x44a, 0x080);
- write_phy_reg(pi, 0x6d3, 0x2222);
- write_phy_reg(pi, 0x6d3, 0x2220);
- } else {
- write_phy_reg(pi, 0x942, 0x0);
- write_phy_reg(pi, 0x93b, ((0 << 13) + 23));
- write_phy_reg(pi, 0x93c, ((0 << 13) + 1989));
- }
- wlapi_switch_macfreq(pi->sh->physhim, enable);
-}
-
-void wlc_phy_chanspec_set_lcnphy(phy_info_t *pi, chanspec_t chanspec)
-{
- u8 channel = CHSPEC_CHANNEL(chanspec);
-
- wlc_phy_chanspec_radio_set((wlc_phy_t *) pi, chanspec);
-
- wlc_lcnphy_set_chanspec_tweaks(pi, pi->radio_chanspec);
-
- or_phy_reg(pi, 0x44a, 0x44);
- write_phy_reg(pi, 0x44a, 0x80);
-
- if (!NORADIO_ENAB(pi->pubpi)) {
- wlc_lcnphy_radio_2064_channel_tune_4313(pi, channel);
- udelay(1000);
- }
-
- wlc_lcnphy_toggle_afe_pwdn(pi);
-
- write_phy_reg(pi, 0x657, lcnphy_sfo_cfg[channel - 1].ptcentreTs20);
- write_phy_reg(pi, 0x658, lcnphy_sfo_cfg[channel - 1].ptcentreFactor);
-
- if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
- mod_phy_reg(pi, 0x448, (0x3 << 8), (2) << 8);
-
- wlc_lcnphy_load_tx_iir_filter(pi, false, 3);
- } else {
- mod_phy_reg(pi, 0x448, (0x3 << 8), (1) << 8);
-
- wlc_lcnphy_load_tx_iir_filter(pi, false, 2);
- }
-
- wlc_lcnphy_load_tx_iir_filter(pi, true, 0);
-
- mod_phy_reg(pi, 0x4eb, (0x7 << 3), (1) << 3);
-
-}
-
-static void wlc_lcnphy_set_dac_gain(phy_info_t *pi, u16 dac_gain)
-{
- u16 dac_ctrl;
-
- dac_ctrl = (read_phy_reg(pi, 0x439) >> 0);
- dac_ctrl = dac_ctrl & 0xc7f;
- dac_ctrl = dac_ctrl | (dac_gain << 7);
- mod_phy_reg(pi, 0x439, (0xfff << 0), (dac_ctrl) << 0);
-
-}
-
-static void wlc_lcnphy_set_tx_gain_override(phy_info_t *pi, bool bEnable)
-{
- u16 bit = bEnable ? 1 : 0;
-
- mod_phy_reg(pi, 0x4b0, (0x1 << 7), bit << 7);
-
- mod_phy_reg(pi, 0x4b0, (0x1 << 14), bit << 14);
-
- mod_phy_reg(pi, 0x43b, (0x1 << 6), bit << 6);
-}
-
-static u16 wlc_lcnphy_get_pa_gain(phy_info_t *pi)
-{
- u16 pa_gain;
-
- pa_gain = (read_phy_reg(pi, 0x4fb) &
- LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK) >>
- LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT;
-
- return pa_gain;
-}
-
-static void
-wlc_lcnphy_set_tx_gain(phy_info_t *pi, lcnphy_txgains_t *target_gains)
-{
- u16 pa_gain = wlc_lcnphy_get_pa_gain(pi);
-
- mod_phy_reg(pi, 0x4b5,
- (0xffff << 0),
- ((target_gains->gm_gain) | (target_gains->pga_gain << 8)) <<
- 0);
- mod_phy_reg(pi, 0x4fb,
- (0x7fff << 0),
- ((target_gains->pad_gain) | (pa_gain << 8)) << 0);
-
- mod_phy_reg(pi, 0x4fc,
- (0xffff << 0),
- ((target_gains->gm_gain) | (target_gains->pga_gain << 8)) <<
- 0);
- mod_phy_reg(pi, 0x4fd,
- (0x7fff << 0),
- ((target_gains->pad_gain) | (pa_gain << 8)) << 0);
-
- wlc_lcnphy_set_dac_gain(pi, target_gains->dac_gain);
-
- wlc_lcnphy_enable_tx_gain_override(pi);
-}
-
-static void wlc_lcnphy_set_bbmult(phy_info_t *pi, u8 m0)
-{
- u16 m0m1 = (u16) m0 << 8;
- phytbl_info_t tab;
-
- tab.tbl_ptr = &m0m1;
- tab.tbl_len = 1;
- tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
- tab.tbl_offset = 87;
- tab.tbl_width = 16;
- wlc_lcnphy_write_table(pi, &tab);
-}
-
-static void wlc_lcnphy_clear_tx_power_offsets(phy_info_t *pi)
-{
- u32 data_buf[64];
- phytbl_info_t tab;
-
- memset(data_buf, 0, sizeof(data_buf));
-
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_ptr = data_buf;
-
- if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
-
- tab.tbl_len = 30;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
- wlc_lcnphy_write_table(pi, &tab);
- }
-
- tab.tbl_len = 64;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_MAC_OFFSET;
- wlc_lcnphy_write_table(pi, &tab);
-}
-
-typedef enum {
- LCNPHY_TSSI_PRE_PA,
- LCNPHY_TSSI_POST_PA,
- LCNPHY_TSSI_EXT
-} lcnphy_tssi_mode_t;
-
-static void wlc_lcnphy_set_tssi_mux(phy_info_t *pi, lcnphy_tssi_mode_t pos)
-{
- mod_phy_reg(pi, 0x4d7, (0x1 << 0), (0x1) << 0);
-
- mod_phy_reg(pi, 0x4d7, (0x1 << 6), (1) << 6);
-
- if (LCNPHY_TSSI_POST_PA == pos) {
- mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0) << 2);
-
- mod_phy_reg(pi, 0x4d9, (0x1 << 3), (1) << 3);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
- mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
- } else {
- mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1);
- mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
- }
- } else {
- mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2);
-
- mod_phy_reg(pi, 0x4d9, (0x1 << 3), (0) << 3);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
- mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
- } else {
- mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0);
- mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
- }
- }
- mod_phy_reg(pi, 0x637, (0x3 << 14), (0) << 14);
-
- if (LCNPHY_TSSI_EXT == pos) {
- write_radio_reg(pi, RADIO_2064_REG07F, 1);
- mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 0x2);
- mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 0x1 << 7);
- mod_radio_reg(pi, RADIO_2064_REG028, 0x1f, 0x3);
- }
-}
-
-static u16 wlc_lcnphy_rfseq_tbl_adc_pwrup(phy_info_t *pi)
-{
- u16 N1, N2, N3, N4, N5, N6, N;
- N1 = ((read_phy_reg(pi, 0x4a5) & (0xff << 0))
- >> 0);
- N2 = 1 << ((read_phy_reg(pi, 0x4a5) & (0x7 << 12))
- >> 12);
- N3 = ((read_phy_reg(pi, 0x40d) & (0xff << 0))
- >> 0);
- N4 = 1 << ((read_phy_reg(pi, 0x40d) & (0x7 << 8))
- >> 8);
- N5 = ((read_phy_reg(pi, 0x4a2) & (0xff << 0))
- >> 0);
- N6 = 1 << ((read_phy_reg(pi, 0x4a2) & (0x7 << 8))
- >> 8);
- N = 2 * (N1 + N2 + N3 + N4 + 2 * (N5 + N6)) + 80;
- if (N < 1600)
- N = 1600;
- return N;
-}
-
-static void wlc_lcnphy_pwrctrl_rssiparams(phy_info_t *pi)
-{
- u16 auxpga_vmid, auxpga_vmid_temp, auxpga_gain_temp;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- auxpga_vmid =
- (2 << 8) | (pi_lcn->lcnphy_rssi_vc << 4) | pi_lcn->lcnphy_rssi_vf;
- auxpga_vmid_temp = (2 << 8) | (8 << 4) | 4;
- auxpga_gain_temp = 2;
-
- mod_phy_reg(pi, 0x4d8, (0x1 << 0), (0) << 0);
-
- mod_phy_reg(pi, 0x4d8, (0x1 << 1), (0) << 1);
-
- mod_phy_reg(pi, 0x4d7, (0x1 << 3), (0) << 3);
-
- mod_phy_reg(pi, 0x4db,
- (0x3ff << 0) |
- (0x7 << 12),
- (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
-
- mod_phy_reg(pi, 0x4dc,
- (0x3ff << 0) |
- (0x7 << 12),
- (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
-
- mod_phy_reg(pi, 0x40a,
- (0x3ff << 0) |
- (0x7 << 12),
- (auxpga_vmid << 0) | (pi_lcn->lcnphy_rssi_gs << 12));
-
- mod_phy_reg(pi, 0x40b,
- (0x3ff << 0) |
- (0x7 << 12),
- (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
-
- mod_phy_reg(pi, 0x40c,
- (0x3ff << 0) |
- (0x7 << 12),
- (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
-
- mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5));
-}
-
-static void wlc_lcnphy_tssi_setup(phy_info_t *pi)
-{
- phytbl_info_t tab;
- u32 rfseq, ind;
-
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_ptr = &ind;
- tab.tbl_len = 1;
- tab.tbl_offset = 0;
- for (ind = 0; ind < 128; ind++) {
- wlc_lcnphy_write_table(pi, &tab);
- tab.tbl_offset++;
- }
- tab.tbl_offset = 704;
- for (ind = 0; ind < 128; ind++) {
- wlc_lcnphy_write_table(pi, &tab);
- tab.tbl_offset++;
- }
- mod_phy_reg(pi, 0x503, (0x1 << 0), (0) << 0);
-
- mod_phy_reg(pi, 0x503, (0x1 << 2), (0) << 2);
-
- mod_phy_reg(pi, 0x503, (0x1 << 4), (1) << 4);
-
- wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
- mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 15), (1) << 15);
-
- mod_phy_reg(pi, 0x4d0, (0x1 << 5), (0) << 5);
-
- mod_phy_reg(pi, 0x4a4, (0x1ff << 0), (0) << 0);
-
- mod_phy_reg(pi, 0x4a5, (0xff << 0), (255) << 0);
-
- mod_phy_reg(pi, 0x4a5, (0x7 << 12), (5) << 12);
-
- mod_phy_reg(pi, 0x4a5, (0x7 << 8), (0) << 8);
-
- mod_phy_reg(pi, 0x40d, (0xff << 0), (64) << 0);
-
- mod_phy_reg(pi, 0x40d, (0x7 << 8), (4) << 8);
-
- mod_phy_reg(pi, 0x4a2, (0xff << 0), (64) << 0);
-
- mod_phy_reg(pi, 0x4a2, (0x7 << 8), (4) << 8);
-
- mod_phy_reg(pi, 0x4d0, (0x1ff << 6), (0) << 6);
-
- mod_phy_reg(pi, 0x4a8, (0xff << 0), (0x1) << 0);
-
- wlc_lcnphy_clear_tx_power_offsets(pi);
-
- mod_phy_reg(pi, 0x4a6, (0x1 << 15), (1) << 15);
-
- mod_phy_reg(pi, 0x4a6, (0x1ff << 0), (0xff) << 0);
-
- mod_phy_reg(pi, 0x49a, (0x1ff << 0), (0xff) << 0);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
- mod_radio_reg(pi, RADIO_2064_REG028, 0xf, 0xe);
- mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
- } else {
- mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
- mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 1 << 3);
- }
-
- write_radio_reg(pi, RADIO_2064_REG025, 0xc);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
- mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
- } else {
- if (CHSPEC_IS2G(pi->radio_chanspec))
- mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 1 << 1);
- else
- mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 0 << 1);
- }
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 2))
- mod_radio_reg(pi, RADIO_2064_REG03A, 0x2, 1 << 1);
- else
- mod_radio_reg(pi, RADIO_2064_REG03A, 0x4, 1 << 2);
-
- mod_radio_reg(pi, RADIO_2064_REG11A, 0x1, 1 << 0);
-
- mod_radio_reg(pi, RADIO_2064_REG005, 0x8, 1 << 3);
-
- if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
- mod_phy_reg(pi, 0x4d7,
- (0x1 << 3) | (0x7 << 12), 0 << 3 | 2 << 12);
- }
-
- rfseq = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi);
- tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
- tab.tbl_width = 16;
- tab.tbl_ptr = &rfseq;
- tab.tbl_len = 1;
- tab.tbl_offset = 6;
- wlc_lcnphy_write_table(pi, &tab);
-
- mod_phy_reg(pi, 0x938, (0x1 << 2), (1) << 2);
-
- mod_phy_reg(pi, 0x939, (0x1 << 2), (1) << 2);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
-
- mod_phy_reg(pi, 0x4d7, (0x1 << 2), (1) << 2);
-
- mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8);
-
- wlc_lcnphy_pwrctrl_rssiparams(pi);
-}
-
-void wlc_lcnphy_tx_pwr_update_npt(phy_info_t *pi)
-{
- u16 tx_cnt, tx_total, npt;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- tx_total = wlc_lcnphy_total_tx_frames(pi);
- tx_cnt = tx_total - pi_lcn->lcnphy_tssi_tx_cnt;
- npt = wlc_lcnphy_get_tx_pwr_npt(pi);
-
- if (tx_cnt > (1 << npt)) {
-
- pi_lcn->lcnphy_tssi_tx_cnt = tx_total;
-
- pi_lcn->lcnphy_tssi_idx = wlc_lcnphy_get_current_tx_pwr_idx(pi);
- pi_lcn->lcnphy_tssi_npt = npt;
-
- }
-}
-
-s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1)
-{
- s32 a, b, p;
-
- a = 32768 + (a1 * tssi);
- b = (1024 * b0) + (64 * b1 * tssi);
- p = ((2 * b) + a) / (2 * a);
-
- return p;
-}
-
-static void wlc_lcnphy_txpower_reset_npt(phy_info_t *pi)
-{
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
- if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
- return;
-
- pi_lcn->lcnphy_tssi_idx = LCNPHY_TX_PWR_CTRL_START_INDEX_2G_4313;
- pi_lcn->lcnphy_tssi_npt = LCNPHY_TX_PWR_CTRL_START_NPT;
-}
-
-void wlc_lcnphy_txpower_recalc_target(phy_info_t *pi)
-{
- phytbl_info_t tab;
- u32 rate_table[WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM +
- WLC_NUM_RATES_MCS_1_STREAM];
- uint i, j;
- if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
- return;
-
- for (i = 0, j = 0; i < ARRAY_SIZE(rate_table); i++, j++) {
-
- if (i == WLC_NUM_RATES_CCK + WLC_NUM_RATES_OFDM)
- j = TXP_FIRST_MCS_20_SISO;
-
- rate_table[i] = (u32) ((s32) (-pi->tx_power_offset[j]));
- }
-
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_len = ARRAY_SIZE(rate_table);
- tab.tbl_ptr = rate_table;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
- wlc_lcnphy_write_table(pi, &tab);
-
- if (wlc_lcnphy_get_target_tx_pwr(pi) != pi->tx_power_min) {
- wlc_lcnphy_set_target_tx_pwr(pi, pi->tx_power_min);
-
- wlc_lcnphy_txpower_reset_npt(pi);
- }
-}
-
-static void wlc_lcnphy_set_tx_pwr_soft_ctrl(phy_info_t *pi, s8 index)
-{
- u32 cck_offset[4] = { 22, 22, 22, 22 };
- u32 ofdm_offset, reg_offset_cck;
- int i;
- u16 index2;
- phytbl_info_t tab;
-
- if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
- return;
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x1) << 14);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x0) << 14);
-
- or_phy_reg(pi, 0x6da, 0x0040);
-
- reg_offset_cck = 0;
- for (i = 0; i < 4; i++)
- cck_offset[i] -= reg_offset_cck;
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_len = 4;
- tab.tbl_ptr = cck_offset;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
- wlc_lcnphy_write_table(pi, &tab);
- ofdm_offset = 0;
- tab.tbl_len = 1;
- tab.tbl_ptr = &ofdm_offset;
- for (i = 836; i < 862; i++) {
- tab.tbl_offset = i;
- wlc_lcnphy_write_table(pi, &tab);
- }
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 15), (0x1) << 15);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0x1) << 14);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 13), (0x1) << 13);
-
- mod_phy_reg(pi, 0x4b0, (0x1 << 7), (0) << 7);
-
- mod_phy_reg(pi, 0x43b, (0x1 << 6), (0) << 6);
-
- mod_phy_reg(pi, 0x4a9, (0x1 << 15), (1) << 15);
-
- index2 = (u16) (index * 2);
- mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0);
-
- mod_phy_reg(pi, 0x6a3, (0x1 << 4), (0) << 4);
-
-}
-
-static s8 wlc_lcnphy_tempcompensated_txpwrctrl(phy_info_t *pi)
-{
- s8 index, delta_brd, delta_temp, new_index, tempcorrx;
- s16 manp, meas_temp, temp_diff;
- bool neg = 0;
- u16 temp;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
- return pi_lcn->lcnphy_current_index;
-
- index = FIXED_TXPWR;
-
- if (NORADIO_ENAB(pi->pubpi))
- return index;
-
- if (pi_lcn->lcnphy_tempsense_slope == 0) {
- return index;
- }
- temp = (u16) wlc_lcnphy_tempsense(pi, 0);
- meas_temp = LCNPHY_TEMPSENSE(temp);
-
- if (pi->tx_power_min != 0) {
- delta_brd = (pi_lcn->lcnphy_measPower - pi->tx_power_min);
- } else {
- delta_brd = 0;
- }
-
- manp = LCNPHY_TEMPSENSE(pi_lcn->lcnphy_rawtempsense);
- temp_diff = manp - meas_temp;
- if (temp_diff < 0) {
-
- neg = 1;
-
- temp_diff = -temp_diff;
- }
-
- delta_temp = (s8) wlc_lcnphy_qdiv_roundup((u32) (temp_diff * 192),
- (u32) (pi_lcn->
- lcnphy_tempsense_slope
- * 10), 0);
- if (neg)
- delta_temp = -delta_temp;
-
- if (pi_lcn->lcnphy_tempsense_option == 3
- && LCNREV_IS(pi->pubpi.phy_rev, 0))
- delta_temp = 0;
- if (pi_lcn->lcnphy_tempcorrx > 31)
- tempcorrx = (s8) (pi_lcn->lcnphy_tempcorrx - 64);
- else
- tempcorrx = (s8) pi_lcn->lcnphy_tempcorrx;
- if (LCNREV_IS(pi->pubpi.phy_rev, 1))
- tempcorrx = 4;
- new_index =
- index + delta_brd + delta_temp - pi_lcn->lcnphy_bandedge_corr;
- new_index += tempcorrx;
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 1))
- index = 127;
- if (new_index < 0 || new_index > 126) {
- return index;
- }
- return new_index;
-}
-
-static u16 wlc_lcnphy_set_tx_pwr_ctrl_mode(phy_info_t *pi, u16 mode)
-{
-
- u16 current_mode = mode;
- if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) &&
- mode == LCNPHY_TX_PWR_CTRL_HW)
- current_mode = LCNPHY_TX_PWR_CTRL_TEMPBASED;
- if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) &&
- mode == LCNPHY_TX_PWR_CTRL_TEMPBASED)
- current_mode = LCNPHY_TX_PWR_CTRL_HW;
- return current_mode;
-}
-
-void wlc_lcnphy_set_tx_pwr_ctrl(phy_info_t *pi, u16 mode)
-{
- u16 old_mode = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- s8 index;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, mode);
- old_mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, old_mode);
-
- mod_phy_reg(pi, 0x6da, (0x1 << 6),
- ((LCNPHY_TX_PWR_CTRL_HW == mode) ? 1 : 0) << 6);
-
- mod_phy_reg(pi, 0x6a3, (0x1 << 4),
- ((LCNPHY_TX_PWR_CTRL_HW == mode) ? 0 : 1) << 4);
-
- if (old_mode != mode) {
- if (LCNPHY_TX_PWR_CTRL_HW == old_mode) {
-
- wlc_lcnphy_tx_pwr_update_npt(pi);
-
- wlc_lcnphy_clear_tx_power_offsets(pi);
- }
- if (LCNPHY_TX_PWR_CTRL_HW == mode) {
-
- wlc_lcnphy_txpower_recalc_target(pi);
-
- wlc_lcnphy_set_start_tx_pwr_idx(pi,
- pi_lcn->
- lcnphy_tssi_idx);
- wlc_lcnphy_set_tx_pwr_npt(pi, pi_lcn->lcnphy_tssi_npt);
- mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 0);
-
- pi_lcn->lcnphy_tssi_tx_cnt =
- wlc_lcnphy_total_tx_frames(pi);
-
- wlc_lcnphy_disable_tx_gain_override(pi);
- pi_lcn->lcnphy_tx_power_idx_override = -1;
- } else
- wlc_lcnphy_enable_tx_gain_override(pi);
-
- mod_phy_reg(pi, 0x4a4,
- ((0x1 << 15) | (0x1 << 14) | (0x1 << 13)), mode);
- if (mode == LCNPHY_TX_PWR_CTRL_TEMPBASED) {
- index = wlc_lcnphy_tempcompensated_txpwrctrl(pi);
- wlc_lcnphy_set_tx_pwr_soft_ctrl(pi, index);
- pi_lcn->lcnphy_current_index = (s8)
- ((read_phy_reg(pi, 0x4a9) & 0xFF) / 2);
- }
- }
-}
-
-static bool wlc_lcnphy_iqcal_wait(phy_info_t *pi)
-{
- uint delay_count = 0;
-
- while (wlc_lcnphy_iqcal_active(pi)) {
- udelay(100);
- delay_count++;
-
- if (delay_count > (10 * 500))
- break;
- }
-
- return (0 == wlc_lcnphy_iqcal_active(pi));
-}
-
-static void
-wlc_lcnphy_tx_iqlo_cal(phy_info_t *pi,
- lcnphy_txgains_t *target_gains,
- lcnphy_cal_mode_t cal_mode, bool keep_tone)
-{
-
- lcnphy_txgains_t cal_gains, temp_gains;
- u16 hash;
- u8 band_idx;
- int j;
- u16 ncorr_override[5];
- u16 syst_coeffs[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
- };
-
- u16 commands_fullcal[] = {
- 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 };
-
- u16 commands_recal[] = {
- 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234 };
-
- u16 command_nums_fullcal[] = {
- 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 };
-
- u16 command_nums_recal[] = {
- 0x7a97, 0x7a97, 0x7a97, 0x7a87, 0x7a87, 0x7b97 };
- u16 *command_nums = command_nums_fullcal;
-
- u16 *start_coeffs = NULL, *cal_cmds = NULL, cal_type, diq_start;
- u16 tx_pwr_ctrl_old, save_txpwrctrlrfctrl2;
- u16 save_sslpnCalibClkEnCtrl, save_sslpnRxFeClkEnCtrl;
- bool tx_gain_override_old;
- lcnphy_txgains_t old_gains;
- uint i, n_cal_cmds = 0, n_cal_start = 0;
- u16 *values_to_save;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- values_to_save = kmalloc(sizeof(u16) * 20, GFP_ATOMIC);
- if (NULL == values_to_save) {
- return;
- }
-
- save_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
- save_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
-
- or_phy_reg(pi, 0x6da, 0x40);
- or_phy_reg(pi, 0x6db, 0x3);
-
- switch (cal_mode) {
- case LCNPHY_CAL_FULL:
- start_coeffs = syst_coeffs;
- cal_cmds = commands_fullcal;
- n_cal_cmds = ARRAY_SIZE(commands_fullcal);
- break;
-
- case LCNPHY_CAL_RECAL:
- start_coeffs = syst_coeffs;
- cal_cmds = commands_recal;
- n_cal_cmds = ARRAY_SIZE(commands_recal);
- command_nums = command_nums_recal;
- break;
-
- default:
- break;
- }
-
- wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- start_coeffs, 11, 16, 64);
-
- write_phy_reg(pi, 0x6da, 0xffff);
- mod_phy_reg(pi, 0x503, (0x1 << 3), (1) << 3);
-
- tx_pwr_ctrl_old = wlc_lcnphy_get_tx_pwr_ctrl(pi);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
-
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
-
- save_txpwrctrlrfctrl2 = read_phy_reg(pi, 0x4db);
-
- mod_phy_reg(pi, 0x4db, (0x3ff << 0), (0x2a6) << 0);
-
- mod_phy_reg(pi, 0x4db, (0x7 << 12), (2) << 12);
-
- wlc_lcnphy_tx_iqlo_loopback(pi, values_to_save);
-
- tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
- if (tx_gain_override_old)
- wlc_lcnphy_get_tx_gain(pi, &old_gains);
-
- if (!target_gains) {
- if (!tx_gain_override_old)
- wlc_lcnphy_set_tx_pwr_by_index(pi,
- pi_lcn->lcnphy_tssi_idx);
- wlc_lcnphy_get_tx_gain(pi, &temp_gains);
- target_gains = &temp_gains;
- }
-
- hash = (target_gains->gm_gain << 8) |
- (target_gains->pga_gain << 4) | (target_gains->pad_gain);
-
- band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0);
-
- cal_gains = *target_gains;
- memset(ncorr_override, 0, sizeof(ncorr_override));
- for (j = 0; j < iqcal_gainparams_numgains_lcnphy[band_idx]; j++) {
- if (hash == tbl_iqcal_gainparams_lcnphy[band_idx][j][0]) {
- cal_gains.gm_gain =
- tbl_iqcal_gainparams_lcnphy[band_idx][j][1];
- cal_gains.pga_gain =
- tbl_iqcal_gainparams_lcnphy[band_idx][j][2];
- cal_gains.pad_gain =
- tbl_iqcal_gainparams_lcnphy[band_idx][j][3];
- memcpy(ncorr_override,
- &tbl_iqcal_gainparams_lcnphy[band_idx][j][3],
- sizeof(ncorr_override));
- break;
- }
- }
-
- wlc_lcnphy_set_tx_gain(pi, &cal_gains);
-
- write_phy_reg(pi, 0x453, 0xaa9);
- write_phy_reg(pi, 0x93d, 0xc0);
-
- wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- (const void *)
- lcnphy_iqcal_loft_gainladder,
- ARRAY_SIZE(lcnphy_iqcal_loft_gainladder),
- 16, 0);
-
- wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- (const void *)lcnphy_iqcal_ir_gainladder,
- ARRAY_SIZE(lcnphy_iqcal_ir_gainladder), 16,
- 32);
-
- if (pi->phy_tx_tone_freq) {
-
- wlc_lcnphy_stop_tx_tone(pi);
- udelay(5);
- wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
- } else {
- wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1);
- }
-
- write_phy_reg(pi, 0x6da, 0xffff);
-
- for (i = n_cal_start; i < n_cal_cmds; i++) {
- u16 zero_diq = 0;
- u16 best_coeffs[11];
- u16 command_num;
-
- cal_type = (cal_cmds[i] & 0x0f00) >> 8;
-
- command_num = command_nums[i];
- if (ncorr_override[cal_type])
- command_num =
- ncorr_override[cal_type] << 8 | (command_num &
- 0xff);
-
- write_phy_reg(pi, 0x452, command_num);
-
- if ((cal_type == 3) || (cal_type == 4)) {
-
- wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- &diq_start, 1, 16, 69);
-
- wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- &zero_diq, 1, 16, 69);
- }
-
- write_phy_reg(pi, 0x451, cal_cmds[i]);
-
- if (!wlc_lcnphy_iqcal_wait(pi)) {
-
- goto cleanup;
- }
-
- wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- best_coeffs,
- ARRAY_SIZE(best_coeffs), 16, 96);
- wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- best_coeffs,
- ARRAY_SIZE(best_coeffs), 16, 64);
-
- if ((cal_type == 3) || (cal_type == 4)) {
- wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- &diq_start, 1, 16, 69);
- }
- wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- pi_lcn->lcnphy_cal_results.
- txiqlocal_bestcoeffs,
- ARRAY_SIZE(pi_lcn->
- lcnphy_cal_results.
- txiqlocal_bestcoeffs),
- 16, 96);
- }
-
- wlc_lcnphy_common_read_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- pi_lcn->lcnphy_cal_results.
- txiqlocal_bestcoeffs,
- ARRAY_SIZE(pi_lcn->lcnphy_cal_results.
- txiqlocal_bestcoeffs), 16, 96);
- pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs_valid = true;
-
- wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- &pi_lcn->lcnphy_cal_results.
- txiqlocal_bestcoeffs[0], 4, 16, 80);
-
- wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
- &pi_lcn->lcnphy_cal_results.
- txiqlocal_bestcoeffs[5], 2, 16, 85);
-
- cleanup:
- wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, values_to_save);
- kfree(values_to_save);
-
- if (!keep_tone)
- wlc_lcnphy_stop_tx_tone(pi);
-
- write_phy_reg(pi, 0x4db, save_txpwrctrlrfctrl2);
-
- write_phy_reg(pi, 0x453, 0);
-
- if (tx_gain_override_old)
- wlc_lcnphy_set_tx_gain(pi, &old_gains);
- wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl_old);
-
- write_phy_reg(pi, 0x6da, save_sslpnCalibClkEnCtrl);
- write_phy_reg(pi, 0x6db, save_sslpnRxFeClkEnCtrl);
-
-}
-
-static void wlc_lcnphy_idle_tssi_est(wlc_phy_t *ppi)
-{
- bool suspend, tx_gain_override_old;
- lcnphy_txgains_t old_gains;
- phy_info_t *pi = (phy_info_t *) ppi;
- u16 idleTssi, idleTssi0_2C, idleTssi0_OB, idleTssi0_regvalue_OB,
- idleTssi0_regvalue_2C;
- u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- u16 SAVE_lpfgain = read_radio_reg(pi, RADIO_2064_REG112);
- u16 SAVE_jtag_bb_afe_switch =
- read_radio_reg(pi, RADIO_2064_REG007) & 1;
- u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10;
- u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4;
- idleTssi = read_phy_reg(pi, 0x4ab);
- suspend =
- (0 ==
- (R_REG(&((phy_info_t *) pi)->regs->maccontrol) &
- MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
-
- tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
- wlc_lcnphy_get_tx_gain(pi, &old_gains);
-
- wlc_lcnphy_enable_tx_gain_override(pi);
- wlc_lcnphy_set_tx_pwr_by_index(pi, 127);
- write_radio_reg(pi, RADIO_2064_REG112, 0x6);
- mod_radio_reg(pi, RADIO_2064_REG007, 0x1, 1);
- mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 1 << 4);
- mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 1 << 2);
- wlc_lcnphy_tssi_setup(pi);
- wlc_phy_do_dummy_tx(pi, true, OFF);
- idleTssi = ((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
- >> 0);
-
- idleTssi0_2C = ((read_phy_reg(pi, 0x63e) & (0x1ff << 0))
- >> 0);
-
- if (idleTssi0_2C >= 256)
- idleTssi0_OB = idleTssi0_2C - 256;
- else
- idleTssi0_OB = idleTssi0_2C + 256;
-
- idleTssi0_regvalue_OB = idleTssi0_OB;
- if (idleTssi0_regvalue_OB >= 256)
- idleTssi0_regvalue_2C = idleTssi0_regvalue_OB - 256;
- else
- idleTssi0_regvalue_2C = idleTssi0_regvalue_OB + 256;
- mod_phy_reg(pi, 0x4a6, (0x1ff << 0), (idleTssi0_regvalue_2C) << 0);
-
- mod_phy_reg(pi, 0x44c, (0x1 << 12), (0) << 12);
-
- wlc_lcnphy_set_tx_gain_override(pi, tx_gain_override_old);
- wlc_lcnphy_set_tx_gain(pi, &old_gains);
- wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
-
- write_radio_reg(pi, RADIO_2064_REG112, SAVE_lpfgain);
- mod_radio_reg(pi, RADIO_2064_REG007, 0x1, SAVE_jtag_bb_afe_switch);
- mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, SAVE_jtag_auxpga);
- mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, SAVE_iqadc_aux_en);
- mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1 << 7);
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
-}
-
-static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
-{
- bool suspend;
- u16 save_txpwrCtrlEn;
- u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain;
- u16 auxpga_vmid;
- phytbl_info_t tab;
- u32 val;
- u8 save_reg007, save_reg0FF, save_reg11F, save_reg005, save_reg025,
- save_reg112;
- u16 values_to_save[14];
- s8 index;
- int i;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
- udelay(999);
-
- save_reg007 = (u8) read_radio_reg(pi, RADIO_2064_REG007);
- save_reg0FF = (u8) read_radio_reg(pi, RADIO_2064_REG0FF);
- save_reg11F = (u8) read_radio_reg(pi, RADIO_2064_REG11F);
- save_reg005 = (u8) read_radio_reg(pi, RADIO_2064_REG005);
- save_reg025 = (u8) read_radio_reg(pi, RADIO_2064_REG025);
- save_reg112 = (u8) read_radio_reg(pi, RADIO_2064_REG112);
-
- for (i = 0; i < 14; i++)
- values_to_save[i] = read_phy_reg(pi, tempsense_phy_regs[i]);
- suspend =
- (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- save_txpwrCtrlEn = read_radio_reg(pi, 0x4a4);
-
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
- index = pi_lcn->lcnphy_current_index;
- wlc_lcnphy_set_tx_pwr_by_index(pi, 127);
- mod_radio_reg(pi, RADIO_2064_REG007, 0x1, 0x1);
- mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 0x1 << 4);
- mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 0x1 << 2);
- mod_phy_reg(pi, 0x503, (0x1 << 0), (0) << 0);
-
- mod_phy_reg(pi, 0x503, (0x1 << 2), (0) << 2);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 15), (0) << 15);
-
- mod_phy_reg(pi, 0x4d0, (0x1 << 5), (0) << 5);
-
- mod_phy_reg(pi, 0x4a5, (0xff << 0), (255) << 0);
-
- mod_phy_reg(pi, 0x4a5, (0x7 << 12), (5) << 12);
-
- mod_phy_reg(pi, 0x4a5, (0x7 << 8), (0) << 8);
-
- mod_phy_reg(pi, 0x40d, (0xff << 0), (64) << 0);
-
- mod_phy_reg(pi, 0x40d, (0x7 << 8), (6) << 8);
-
- mod_phy_reg(pi, 0x4a2, (0xff << 0), (64) << 0);
-
- mod_phy_reg(pi, 0x4a2, (0x7 << 8), (6) << 8);
-
- mod_phy_reg(pi, 0x4d9, (0x7 << 4), (2) << 4);
-
- mod_phy_reg(pi, 0x4d9, (0x7 << 8), (3) << 8);
-
- mod_phy_reg(pi, 0x4d9, (0x7 << 12), (1) << 12);
-
- mod_phy_reg(pi, 0x4da, (0x1 << 12), (0) << 12);
-
- mod_phy_reg(pi, 0x4da, (0x1 << 13), (1) << 13);
-
- mod_phy_reg(pi, 0x4a6, (0x1 << 15), (1) << 15);
-
- write_radio_reg(pi, RADIO_2064_REG025, 0xC);
-
- mod_radio_reg(pi, RADIO_2064_REG005, 0x8, 0x1 << 3);
-
- mod_phy_reg(pi, 0x938, (0x1 << 2), (1) << 2);
-
- mod_phy_reg(pi, 0x939, (0x1 << 2), (1) << 2);
-
- mod_phy_reg(pi, 0x4a4, (0x1 << 12), (1) << 12);
-
- val = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi);
- tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
- tab.tbl_width = 16;
- tab.tbl_len = 1;
- tab.tbl_ptr = &val;
- tab.tbl_offset = 6;
- wlc_lcnphy_write_table(pi, &tab);
- if (mode == TEMPSENSE) {
- mod_phy_reg(pi, 0x4d7, (0x1 << 3), (1) << 3);
-
- mod_phy_reg(pi, 0x4d7, (0x7 << 12), (1) << 12);
-
- auxpga_vmidcourse = 8;
- auxpga_vmidfine = 0x4;
- auxpga_gain = 2;
- mod_radio_reg(pi, RADIO_2064_REG082, 0x20, 1 << 5);
- } else {
- mod_phy_reg(pi, 0x4d7, (0x1 << 3), (1) << 3);
-
- mod_phy_reg(pi, 0x4d7, (0x7 << 12), (3) << 12);
-
- auxpga_vmidcourse = 7;
- auxpga_vmidfine = 0xa;
- auxpga_gain = 2;
- }
- auxpga_vmid =
- (u16) ((2 << 8) | (auxpga_vmidcourse << 4) | auxpga_vmidfine);
- mod_phy_reg(pi, 0x4d8, (0x1 << 0), (1) << 0);
-
- mod_phy_reg(pi, 0x4d8, (0x3ff << 2), (auxpga_vmid) << 2);
-
- mod_phy_reg(pi, 0x4d8, (0x1 << 1), (1) << 1);
-
- mod_phy_reg(pi, 0x4d8, (0x7 << 12), (auxpga_gain) << 12);
-
- mod_phy_reg(pi, 0x4d0, (0x1 << 5), (1) << 5);
-
- write_radio_reg(pi, RADIO_2064_REG112, 0x6);
-
- wlc_phy_do_dummy_tx(pi, true, OFF);
- if (!tempsense_done(pi))
- udelay(10);
-
- write_radio_reg(pi, RADIO_2064_REG007, (u16) save_reg007);
- write_radio_reg(pi, RADIO_2064_REG0FF, (u16) save_reg0FF);
- write_radio_reg(pi, RADIO_2064_REG11F, (u16) save_reg11F);
- write_radio_reg(pi, RADIO_2064_REG005, (u16) save_reg005);
- write_radio_reg(pi, RADIO_2064_REG025, (u16) save_reg025);
- write_radio_reg(pi, RADIO_2064_REG112, (u16) save_reg112);
- for (i = 0; i < 14; i++)
- write_phy_reg(pi, tempsense_phy_regs[i], values_to_save[i]);
- wlc_lcnphy_set_tx_pwr_by_index(pi, (int)index);
-
- write_radio_reg(pi, 0x4a4, save_txpwrCtrlEn);
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
- udelay(999);
-}
-
-void WLBANDINITFN(wlc_lcnphy_tx_pwr_ctrl_init) (wlc_phy_t *ppi)
-{
- lcnphy_txgains_t tx_gains;
- u8 bbmult;
- phytbl_info_t tab;
- s32 a1, b0, b1;
- s32 tssi, pwr, maxtargetpwr, mintargetpwr;
- bool suspend;
- phy_info_t *pi = (phy_info_t *) ppi;
-
- suspend =
- (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- if (NORADIO_ENAB(pi->pubpi)) {
- wlc_lcnphy_set_bbmult(pi, 0x30);
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
- return;
- }
-
- if (!pi->hwpwrctrl_capable) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- tx_gains.gm_gain = 4;
- tx_gains.pga_gain = 12;
- tx_gains.pad_gain = 12;
- tx_gains.dac_gain = 0;
-
- bbmult = 150;
- } else {
- tx_gains.gm_gain = 7;
- tx_gains.pga_gain = 15;
- tx_gains.pad_gain = 14;
- tx_gains.dac_gain = 0;
-
- bbmult = 150;
- }
- wlc_lcnphy_set_tx_gain(pi, &tx_gains);
- wlc_lcnphy_set_bbmult(pi, bbmult);
- wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
- } else {
-
- wlc_lcnphy_idle_tssi_est(ppi);
-
- wlc_lcnphy_clear_tx_power_offsets(pi);
-
- b0 = pi->txpa_2g[0];
- b1 = pi->txpa_2g[1];
- a1 = pi->txpa_2g[2];
- maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1);
- mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1);
-
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_ptr = &pwr;
- tab.tbl_len = 1;
- tab.tbl_offset = 0;
- for (tssi = 0; tssi < 128; tssi++) {
- pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1);
-
- pwr = (pwr < mintargetpwr) ? mintargetpwr : pwr;
- wlc_lcnphy_write_table(pi, &tab);
- tab.tbl_offset++;
- }
-
- mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7);
-
- write_phy_reg(pi, 0x4a8, 10);
-
- wlc_lcnphy_set_target_tx_pwr(pi, LCN_TARGET_PWR);
-
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
- }
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
-}
-
-static u8 wlc_lcnphy_get_bbmult(phy_info_t *pi)
-{
- u16 m0m1;
- phytbl_info_t tab;
-
- tab.tbl_ptr = &m0m1;
- tab.tbl_len = 1;
- tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
- tab.tbl_offset = 87;
- tab.tbl_width = 16;
- wlc_lcnphy_read_table(pi, &tab);
-
- return (u8) ((m0m1 & 0xff00) >> 8);
-}
-
-static void wlc_lcnphy_set_pa_gain(phy_info_t *pi, u16 gain)
-{
- mod_phy_reg(pi, 0x4fb,
- LCNPHY_txgainctrlovrval1_pagain_ovr_val1_MASK,
- gain << LCNPHY_txgainctrlovrval1_pagain_ovr_val1_SHIFT);
- mod_phy_reg(pi, 0x4fd,
- LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_MASK,
- gain << LCNPHY_stxtxgainctrlovrval1_pagain_ovr_val1_SHIFT);
-}
-
-void
-wlc_lcnphy_get_radio_loft(phy_info_t *pi,
- u8 *ei0, u8 *eq0, u8 *fi0, u8 *fq0)
-{
- *ei0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG089));
- *eq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08A));
- *fi0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08B));
- *fq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08C));
-}
-
-static void wlc_lcnphy_get_tx_gain(phy_info_t *pi, lcnphy_txgains_t *gains)
-{
- u16 dac_gain;
-
- dac_gain = read_phy_reg(pi, 0x439) >> 0;
- gains->dac_gain = (dac_gain & 0x380) >> 7;
-
- {
- u16 rfgain0, rfgain1;
-
- rfgain0 = (read_phy_reg(pi, 0x4b5) & (0xffff << 0)) >> 0;
- rfgain1 = (read_phy_reg(pi, 0x4fb) & (0x7fff << 0)) >> 0;
-
- gains->gm_gain = rfgain0 & 0xff;
- gains->pga_gain = (rfgain0 >> 8) & 0xff;
- gains->pad_gain = rfgain1 & 0xff;
- }
-}
-
-void wlc_lcnphy_set_tx_iqcc(phy_info_t *pi, u16 a, u16 b)
-{
- phytbl_info_t tab;
- u16 iqcc[2];
-
- iqcc[0] = a;
- iqcc[1] = b;
-
- tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
- tab.tbl_width = 16;
- tab.tbl_ptr = iqcc;
- tab.tbl_len = 2;
- tab.tbl_offset = 80;
- wlc_lcnphy_write_table(pi, &tab);
-}
-
-void wlc_lcnphy_set_tx_locc(phy_info_t *pi, u16 didq)
-{
- phytbl_info_t tab;
-
- tab.tbl_id = LCNPHY_TBL_ID_IQLOCAL;
- tab.tbl_width = 16;
- tab.tbl_ptr = &didq;
- tab.tbl_len = 1;
- tab.tbl_offset = 85;
- wlc_lcnphy_write_table(pi, &tab);
-}
-
-void wlc_lcnphy_set_tx_pwr_by_index(phy_info_t *pi, int index)
-{
- phytbl_info_t tab;
- u16 a, b;
- u8 bb_mult;
- u32 bbmultiqcomp, txgain, locoeffs, rfpower;
- lcnphy_txgains_t gains;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- pi_lcn->lcnphy_tx_power_idx_override = (s8) index;
- pi_lcn->lcnphy_current_index = (u8) index;
-
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_len = 1;
-
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
-
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + index;
- tab.tbl_ptr = &bbmultiqcomp;
- wlc_lcnphy_read_table(pi, &tab);
-
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + index;
- tab.tbl_width = 32;
- tab.tbl_ptr = &txgain;
- wlc_lcnphy_read_table(pi, &tab);
-
- gains.gm_gain = (u16) (txgain & 0xff);
- gains.pga_gain = (u16) (txgain >> 8) & 0xff;
- gains.pad_gain = (u16) (txgain >> 16) & 0xff;
- gains.dac_gain = (u16) (bbmultiqcomp >> 28) & 0x07;
- wlc_lcnphy_set_tx_gain(pi, &gains);
- wlc_lcnphy_set_pa_gain(pi, (u16) (txgain >> 24) & 0x7f);
-
- bb_mult = (u8) ((bbmultiqcomp >> 20) & 0xff);
- wlc_lcnphy_set_bbmult(pi, bb_mult);
-
- wlc_lcnphy_enable_tx_gain_override(pi);
-
- if (!wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
-
- a = (u16) ((bbmultiqcomp >> 10) & 0x3ff);
- b = (u16) (bbmultiqcomp & 0x3ff);
- wlc_lcnphy_set_tx_iqcc(pi, a, b);
-
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + index;
- tab.tbl_ptr = &locoeffs;
- wlc_lcnphy_read_table(pi, &tab);
-
- wlc_lcnphy_set_tx_locc(pi, (u16) locoeffs);
-
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index;
- tab.tbl_ptr = &rfpower;
- wlc_lcnphy_read_table(pi, &tab);
- mod_phy_reg(pi, 0x6a6, (0x1fff << 0), (rfpower * 8) << 0);
-
- }
-}
-
-static void wlc_lcnphy_set_trsw_override(phy_info_t *pi, bool tx, bool rx)
-{
-
- mod_phy_reg(pi, 0x44d,
- (0x1 << 1) |
- (0x1 << 0), (tx ? (0x1 << 1) : 0) | (rx ? (0x1 << 0) : 0));
-
- or_phy_reg(pi, 0x44c, (0x1 << 1) | (0x1 << 0));
-}
-
-static void wlc_lcnphy_clear_papd_comptable(phy_info_t *pi)
-{
- u32 j;
- phytbl_info_t tab;
- u32 temp_offset[128];
- tab.tbl_ptr = temp_offset;
- tab.tbl_len = 128;
- tab.tbl_id = LCNPHY_TBL_ID_PAPDCOMPDELTATBL;
- tab.tbl_width = 32;
- tab.tbl_offset = 0;
-
- memset(temp_offset, 0, sizeof(temp_offset));
- for (j = 1; j < 128; j += 2)
- temp_offset[j] = 0x80000;
-
- wlc_lcnphy_write_table(pi, &tab);
- return;
-}
-
-static void
-wlc_lcnphy_set_rx_gain_by_distribution(phy_info_t *pi,
- u16 trsw,
- u16 ext_lna,
- u16 biq2,
- u16 biq1,
- u16 tia, u16 lna2, u16 lna1)
-{
- u16 gain0_15, gain16_19;
-
- gain16_19 = biq2 & 0xf;
- gain0_15 = ((biq1 & 0xf) << 12) |
- ((tia & 0xf) << 8) |
- ((lna2 & 0x3) << 6) |
- ((lna2 & 0x3) << 4) | ((lna1 & 0x3) << 2) | ((lna1 & 0x3) << 0);
-
- mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
- mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
- mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
-
- if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
- mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
- mod_phy_reg(pi, 0x4b1, (0x1 << 10), ext_lna << 10);
- } else {
- mod_phy_reg(pi, 0x4b1, (0x1 << 10), 0 << 10);
-
- mod_phy_reg(pi, 0x4b1, (0x1 << 15), 0 << 15);
-
- mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
- }
-
- mod_phy_reg(pi, 0x44d, (0x1 << 0), (!trsw) << 0);
-
-}
-
-static void wlc_lcnphy_rx_gain_override_enable(phy_info_t *pi, bool enable)
-{
- u16 ebit = enable ? 1 : 0;
-
- mod_phy_reg(pi, 0x4b0, (0x1 << 8), ebit << 8);
-
- mod_phy_reg(pi, 0x44c, (0x1 << 0), ebit << 0);
-
- if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
- mod_phy_reg(pi, 0x44c, (0x1 << 4), ebit << 4);
- mod_phy_reg(pi, 0x44c, (0x1 << 6), ebit << 6);
- mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5);
- mod_phy_reg(pi, 0x4b0, (0x1 << 6), ebit << 6);
- } else {
- mod_phy_reg(pi, 0x4b0, (0x1 << 12), ebit << 12);
- mod_phy_reg(pi, 0x4b0, (0x1 << 13), ebit << 13);
- mod_phy_reg(pi, 0x4b0, (0x1 << 5), ebit << 5);
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- mod_phy_reg(pi, 0x4b0, (0x1 << 10), ebit << 10);
- mod_phy_reg(pi, 0x4e5, (0x1 << 3), ebit << 3);
- }
-}
-
-void wlc_lcnphy_tx_pu(phy_info_t *pi, bool bEnable)
-{
- if (!bEnable) {
-
- and_phy_reg(pi, 0x43b, ~(u16) ((0x1 << 1) | (0x1 << 4)));
-
- mod_phy_reg(pi, 0x43c, (0x1 << 1), 1 << 1);
-
- and_phy_reg(pi, 0x44c,
- ~(u16) ((0x1 << 3) |
- (0x1 << 5) |
- (0x1 << 12) |
- (0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
-
- and_phy_reg(pi, 0x44d,
- ~(u16) ((0x1 << 3) | (0x1 << 5) | (0x1 << 14)));
- mod_phy_reg(pi, 0x44d, (0x1 << 2), 1 << 2);
-
- mod_phy_reg(pi, 0x44d, (0x1 << 1) | (0x1 << 0), (0x1 << 0));
-
- and_phy_reg(pi, 0x4f9,
- ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
-
- and_phy_reg(pi, 0x4fa,
- ~(u16) ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
- } else {
-
- mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
- mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
-
- mod_phy_reg(pi, 0x43b, (0x1 << 4), 1 << 4);
- mod_phy_reg(pi, 0x43c, (0x1 << 6), 0 << 6);
-
- mod_phy_reg(pi, 0x44c, (0x1 << 12), 1 << 12);
- mod_phy_reg(pi, 0x44d, (0x1 << 14), 1 << 14);
-
- wlc_lcnphy_set_trsw_override(pi, true, false);
-
- mod_phy_reg(pi, 0x44d, (0x1 << 2), 0 << 2);
- mod_phy_reg(pi, 0x44c, (0x1 << 2), 1 << 2);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
-
- mod_phy_reg(pi, 0x44c, (0x1 << 3), 1 << 3);
- mod_phy_reg(pi, 0x44d, (0x1 << 3), 1 << 3);
-
- mod_phy_reg(pi, 0x44c, (0x1 << 5), 1 << 5);
- mod_phy_reg(pi, 0x44d, (0x1 << 5), 0 << 5);
-
- mod_phy_reg(pi, 0x4f9, (0x1 << 1), 1 << 1);
- mod_phy_reg(pi, 0x4fa, (0x1 << 1), 1 << 1);
-
- mod_phy_reg(pi, 0x4f9, (0x1 << 2), 1 << 2);
- mod_phy_reg(pi, 0x4fa, (0x1 << 2), 1 << 2);
-
- mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0x4fa, (0x1 << 0), 1 << 0);
- } else {
-
- mod_phy_reg(pi, 0x44c, (0x1 << 3), 1 << 3);
- mod_phy_reg(pi, 0x44d, (0x1 << 3), 0 << 3);
-
- mod_phy_reg(pi, 0x44c, (0x1 << 5), 1 << 5);
- mod_phy_reg(pi, 0x44d, (0x1 << 5), 1 << 5);
-
- mod_phy_reg(pi, 0x4f9, (0x1 << 1), 1 << 1);
- mod_phy_reg(pi, 0x4fa, (0x1 << 1), 0 << 1);
-
- mod_phy_reg(pi, 0x4f9, (0x1 << 2), 1 << 2);
- mod_phy_reg(pi, 0x4fa, (0x1 << 2), 0 << 2);
-
- mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
- }
- }
-}
-
-static void
-wlc_lcnphy_run_samples(phy_info_t *pi,
- u16 num_samps,
- u16 num_loops, u16 wait, bool iqcalmode)
-{
-
- or_phy_reg(pi, 0x6da, 0x8080);
-
- mod_phy_reg(pi, 0x642, (0x7f << 0), (num_samps - 1) << 0);
- if (num_loops != 0xffff)
- num_loops--;
- mod_phy_reg(pi, 0x640, (0xffff << 0), num_loops << 0);
-
- mod_phy_reg(pi, 0x641, (0xffff << 0), wait << 0);
-
- if (iqcalmode) {
-
- and_phy_reg(pi, 0x453, (u16) ~(0x1 << 15));
- or_phy_reg(pi, 0x453, (0x1 << 15));
- } else {
- write_phy_reg(pi, 0x63f, 1);
- wlc_lcnphy_tx_pu(pi, 1);
- }
-
- or_radio_reg(pi, RADIO_2064_REG112, 0x6);
-}
-
-void wlc_lcnphy_deaf_mode(phy_info_t *pi, bool mode)
-{
-
- u8 phybw40;
- phybw40 = CHSPEC_IS40(pi->radio_chanspec);
-
- if (LCNREV_LT(pi->pubpi.phy_rev, 2)) {
- mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
- mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
- } else {
- mod_phy_reg(pi, 0x4b0, (0x1 << 5), (mode) << 5);
- mod_phy_reg(pi, 0x4b1, (0x1 << 9), 0 << 9);
- }
-
- if (phybw40 == 0) {
- mod_phy_reg((pi), 0x410,
- (0x1 << 6) |
- (0x1 << 5),
- ((CHSPEC_IS2G(pi->radio_chanspec)) ? (!mode) : 0) <<
- 6 | (!mode) << 5);
- mod_phy_reg(pi, 0x410, (0x1 << 7), (mode) << 7);
- }
-}
-
-void
-wlc_lcnphy_start_tx_tone(phy_info_t *pi, s32 f_kHz, u16 max_val,
- bool iqcalmode)
-{
- u8 phy_bw;
- u16 num_samps, t, k;
- u32 bw;
- fixed theta = 0, rot = 0;
- cs32 tone_samp;
- u32 data_buf[64];
- u16 i_samp, q_samp;
- phytbl_info_t tab;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- pi->phy_tx_tone_freq = f_kHz;
-
- wlc_lcnphy_deaf_mode(pi, true);
-
- phy_bw = 40;
- if (pi_lcn->lcnphy_spurmod) {
- write_phy_reg(pi, 0x942, 0x2);
- write_phy_reg(pi, 0x93b, 0x0);
- write_phy_reg(pi, 0x93c, 0x0);
- wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
- }
-
- if (f_kHz) {
- k = 1;
- do {
- bw = phy_bw * 1000 * k;
- num_samps = bw / ABS(f_kHz);
- k++;
- } while ((num_samps * (u32) (ABS(f_kHz))) != bw);
- } else
- num_samps = 2;
-
- rot = FIXED((f_kHz * 36) / phy_bw) / 100;
- theta = 0;
-
- for (t = 0; t < num_samps; t++) {
-
- wlc_phy_cordic(theta, &tone_samp);
-
- theta += rot;
-
- i_samp = (u16) (FLOAT(tone_samp.i * max_val) & 0x3ff);
- q_samp = (u16) (FLOAT(tone_samp.q * max_val) & 0x3ff);
- data_buf[t] = (i_samp << 10) | q_samp;
- }
-
- mod_phy_reg(pi, 0x6d6, (0x3 << 0), 0 << 0);
-
- mod_phy_reg(pi, 0x6da, (0x1 << 3), 1 << 3);
-
- tab.tbl_ptr = data_buf;
- tab.tbl_len = num_samps;
- tab.tbl_id = LCNPHY_TBL_ID_SAMPLEPLAY;
- tab.tbl_offset = 0;
- tab.tbl_width = 32;
- wlc_lcnphy_write_table(pi, &tab);
-
- wlc_lcnphy_run_samples(pi, num_samps, 0xffff, 0, iqcalmode);
-}
-
-void wlc_lcnphy_stop_tx_tone(phy_info_t *pi)
-{
- s16 playback_status;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- pi->phy_tx_tone_freq = 0;
- if (pi_lcn->lcnphy_spurmod) {
- write_phy_reg(pi, 0x942, 0x7);
- write_phy_reg(pi, 0x93b, 0x2017);
- write_phy_reg(pi, 0x93c, 0x27c5);
- wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
- }
-
- playback_status = read_phy_reg(pi, 0x644);
- if (playback_status & (0x1 << 0)) {
- wlc_lcnphy_tx_pu(pi, 0);
- mod_phy_reg(pi, 0x63f, (0x1 << 1), 1 << 1);
- } else if (playback_status & (0x1 << 1))
- mod_phy_reg(pi, 0x453, (0x1 << 15), 0 << 15);
-
- mod_phy_reg(pi, 0x6d6, (0x3 << 0), 1 << 0);
-
- mod_phy_reg(pi, 0x6da, (0x1 << 3), 0 << 3);
-
- mod_phy_reg(pi, 0x6da, (0x1 << 7), 0 << 7);
-
- and_radio_reg(pi, RADIO_2064_REG112, 0xFFF9);
-
- wlc_lcnphy_deaf_mode(pi, false);
-}
-
-static void wlc_lcnphy_clear_trsw_override(phy_info_t *pi)
-{
-
- and_phy_reg(pi, 0x44c, (u16) ~((0x1 << 1) | (0x1 << 0)));
-}
-
-void wlc_lcnphy_get_tx_iqcc(phy_info_t *pi, u16 *a, u16 *b)
-{
- u16 iqcc[2];
- phytbl_info_t tab;
-
- tab.tbl_ptr = iqcc;
- tab.tbl_len = 2;
- tab.tbl_id = 0;
- tab.tbl_offset = 80;
- tab.tbl_width = 16;
- wlc_lcnphy_read_table(pi, &tab);
-
- *a = iqcc[0];
- *b = iqcc[1];
-}
-
-u16 wlc_lcnphy_get_tx_locc(phy_info_t *pi)
-{
- phytbl_info_t tab;
- u16 didq;
-
- tab.tbl_id = 0;
- tab.tbl_width = 16;
- tab.tbl_ptr = &didq;
- tab.tbl_len = 1;
- tab.tbl_offset = 85;
- wlc_lcnphy_read_table(pi, &tab);
-
- return didq;
-}
-
-static void wlc_lcnphy_txpwrtbl_iqlo_cal(phy_info_t *pi)
-{
-
- lcnphy_txgains_t target_gains, old_gains;
- u8 save_bb_mult;
- u16 a, b, didq, save_pa_gain = 0;
- uint idx, SAVE_txpwrindex = 0xFF;
- u32 val;
- u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- phytbl_info_t tab;
- u8 ei0, eq0, fi0, fq0;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- wlc_lcnphy_get_tx_gain(pi, &old_gains);
- save_pa_gain = wlc_lcnphy_get_pa_gain(pi);
-
- save_bb_mult = wlc_lcnphy_get_bbmult(pi);
-
- if (SAVE_txpwrctrl == LCNPHY_TX_PWR_CTRL_OFF)
- SAVE_txpwrindex = wlc_lcnphy_get_current_tx_pwr_idx(pi);
-
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
-
- target_gains.gm_gain = 7;
- target_gains.pga_gain = 0;
- target_gains.pad_gain = 21;
- target_gains.dac_gain = 0;
- wlc_lcnphy_set_tx_gain(pi, &target_gains);
- wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 1) || pi_lcn->lcnphy_hw_iqcal_en) {
-
- wlc_lcnphy_set_tx_pwr_by_index(pi, 30);
-
- wlc_lcnphy_tx_iqlo_cal(pi, &target_gains,
- (pi_lcn->
- lcnphy_recal ? LCNPHY_CAL_RECAL :
- LCNPHY_CAL_FULL), false);
- } else {
-
- wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
- }
-
- wlc_lcnphy_get_radio_loft(pi, &ei0, &eq0, &fi0, &fq0);
- if ((ABS((s8) fi0) == 15) && (ABS((s8) fq0) == 15)) {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- target_gains.gm_gain = 255;
- target_gains.pga_gain = 255;
- target_gains.pad_gain = 0xf0;
- target_gains.dac_gain = 0;
- } else {
- target_gains.gm_gain = 7;
- target_gains.pga_gain = 45;
- target_gains.pad_gain = 186;
- target_gains.dac_gain = 0;
- }
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 1)
- || pi_lcn->lcnphy_hw_iqcal_en) {
-
- target_gains.pga_gain = 0;
- target_gains.pad_gain = 30;
- wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
- wlc_lcnphy_tx_iqlo_cal(pi, &target_gains,
- LCNPHY_CAL_FULL, false);
- } else {
-
- wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
- }
-
- }
-
- wlc_lcnphy_get_tx_iqcc(pi, &a, &b);
-
- didq = wlc_lcnphy_get_tx_locc(pi);
-
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_ptr = &val;
-
- tab.tbl_len = 1;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_RATE_OFFSET;
-
- for (idx = 0; idx < 128; idx++) {
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + idx;
-
- wlc_lcnphy_read_table(pi, &tab);
- val = (val & 0xfff00000) |
- ((u32) (a & 0x3FF) << 10) | (b & 0x3ff);
- wlc_lcnphy_write_table(pi, &tab);
-
- val = didq;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_LO_OFFSET + idx;
- wlc_lcnphy_write_table(pi, &tab);
- }
-
- pi_lcn->lcnphy_cal_results.txiqlocal_a = a;
- pi_lcn->lcnphy_cal_results.txiqlocal_b = b;
- pi_lcn->lcnphy_cal_results.txiqlocal_didq = didq;
- pi_lcn->lcnphy_cal_results.txiqlocal_ei0 = ei0;
- pi_lcn->lcnphy_cal_results.txiqlocal_eq0 = eq0;
- pi_lcn->lcnphy_cal_results.txiqlocal_fi0 = fi0;
- pi_lcn->lcnphy_cal_results.txiqlocal_fq0 = fq0;
-
- wlc_lcnphy_set_bbmult(pi, save_bb_mult);
- wlc_lcnphy_set_pa_gain(pi, save_pa_gain);
- wlc_lcnphy_set_tx_gain(pi, &old_gains);
-
- if (SAVE_txpwrctrl != LCNPHY_TX_PWR_CTRL_OFF)
- wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
- else
- wlc_lcnphy_set_tx_pwr_by_index(pi, SAVE_txpwrindex);
-}
-
-s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode)
-{
- u16 tempsenseval1, tempsenseval2;
- s16 avg = 0;
- bool suspend = 0;
-
- if (NORADIO_ENAB(pi->pubpi))
- return -1;
-
- if (mode == 1) {
- suspend =
- (0 ==
- (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
- }
- tempsenseval1 = read_phy_reg(pi, 0x476) & 0x1FF;
- tempsenseval2 = read_phy_reg(pi, 0x477) & 0x1FF;
-
- if (tempsenseval1 > 255)
- avg = (s16) (tempsenseval1 - 512);
- else
- avg = (s16) tempsenseval1;
-
- if (tempsenseval2 > 255)
- avg += (s16) (tempsenseval2 - 512);
- else
- avg += (s16) tempsenseval2;
-
- avg /= 2;
-
- if (mode == 1) {
-
- mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
-
- udelay(100);
- mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
-
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
- }
- return avg;
-}
-
-u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode)
-{
- u16 tempsenseval1, tempsenseval2;
- s32 avg = 0;
- bool suspend = 0;
- u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (NORADIO_ENAB(pi->pubpi))
- return -1;
-
- if (mode == 1) {
- suspend =
- (0 ==
- (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
- }
- tempsenseval1 = read_phy_reg(pi, 0x476) & 0x1FF;
- tempsenseval2 = read_phy_reg(pi, 0x477) & 0x1FF;
-
- if (tempsenseval1 > 255)
- avg = (int)(tempsenseval1 - 512);
- else
- avg = (int)tempsenseval1;
-
- if (pi_lcn->lcnphy_tempsense_option == 1 || pi->hwpwrctrl_capable) {
- if (tempsenseval2 > 255)
- avg = (int)(avg - tempsenseval2 + 512);
- else
- avg = (int)(avg - tempsenseval2);
- } else {
- if (tempsenseval2 > 255)
- avg = (int)(avg + tempsenseval2 - 512);
- else
- avg = (int)(avg + tempsenseval2);
- avg = avg / 2;
- }
- if (avg < 0)
- avg = avg + 512;
-
- if (pi_lcn->lcnphy_tempsense_option == 2)
- avg = tempsenseval1;
-
- if (mode)
- wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
-
- if (mode == 1) {
-
- mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
-
- udelay(100);
- mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
-
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
- }
- return (u16) avg;
-}
-
-s8 wlc_lcnphy_tempsense_degree(phy_info_t *pi, bool mode)
-{
- s32 degree = wlc_lcnphy_tempsense_new(pi, mode);
- degree =
- ((degree << 10) + LCN_TEMPSENSE_OFFSET + (LCN_TEMPSENSE_DEN >> 1))
- / LCN_TEMPSENSE_DEN;
- return (s8) degree;
-}
-
-s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode)
-{
- u16 vbatsenseval;
- s32 avg = 0;
- bool suspend = 0;
-
- if (NORADIO_ENAB(pi->pubpi))
- return -1;
-
- if (mode == 1) {
- suspend =
- (0 ==
- (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- wlc_lcnphy_vbat_temp_sense_setup(pi, VBATSENSE);
- }
-
- vbatsenseval = read_phy_reg(pi, 0x475) & 0x1FF;
-
- if (vbatsenseval > 255)
- avg = (s32) (vbatsenseval - 512);
- else
- avg = (s32) vbatsenseval;
-
- avg =
- (avg * LCN_VBAT_SCALE_NOM +
- (LCN_VBAT_SCALE_DEN >> 1)) / LCN_VBAT_SCALE_DEN;
-
- if (mode == 1) {
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
- }
- return (s8) avg;
-}
-
-static void wlc_lcnphy_afe_clk_init(phy_info_t *pi, u8 mode)
-{
- u8 phybw40;
- phybw40 = CHSPEC_IS40(pi->radio_chanspec);
-
- mod_phy_reg(pi, 0x6d1, (0x1 << 7), (1) << 7);
-
- if (((mode == AFE_CLK_INIT_MODE_PAPD) && (phybw40 == 0)) ||
- (mode == AFE_CLK_INIT_MODE_TXRX2X))
- write_phy_reg(pi, 0x6d0, 0x7);
-
- wlc_lcnphy_toggle_afe_pwdn(pi);
-}
-
-static bool
-wlc_lcnphy_rx_iq_est(phy_info_t *pi,
- u16 num_samps,
- u8 wait_time, lcnphy_iq_est_t *iq_est)
-{
- int wait_count = 0;
- bool result = true;
- u8 phybw40;
- phybw40 = CHSPEC_IS40(pi->radio_chanspec);
-
- mod_phy_reg(pi, 0x6da, (0x1 << 5), (1) << 5);
-
- mod_phy_reg(pi, 0x410, (0x1 << 3), (0) << 3);
-
- mod_phy_reg(pi, 0x482, (0xffff << 0), (num_samps) << 0);
-
- mod_phy_reg(pi, 0x481, (0xff << 0), ((u16) wait_time) << 0);
-
- mod_phy_reg(pi, 0x481, (0x1 << 8), (0) << 8);
-
- mod_phy_reg(pi, 0x481, (0x1 << 9), (1) << 9);
-
- while (read_phy_reg(pi, 0x481) & (0x1 << 9)) {
-
- if (wait_count > (10 * 500)) {
- result = false;
- goto cleanup;
- }
- udelay(100);
- wait_count++;
- }
-
- iq_est->iq_prod = ((u32) read_phy_reg(pi, 0x483) << 16) |
- (u32) read_phy_reg(pi, 0x484);
- iq_est->i_pwr = ((u32) read_phy_reg(pi, 0x485) << 16) |
- (u32) read_phy_reg(pi, 0x486);
- iq_est->q_pwr = ((u32) read_phy_reg(pi, 0x487) << 16) |
- (u32) read_phy_reg(pi, 0x488);
-
- cleanup:
- mod_phy_reg(pi, 0x410, (0x1 << 3), (1) << 3);
-
- mod_phy_reg(pi, 0x6da, (0x1 << 5), (0) << 5);
-
- return result;
-}
-
-static bool wlc_lcnphy_calc_rx_iq_comp(phy_info_t *pi, u16 num_samps)
-{
-#define LCNPHY_MIN_RXIQ_PWR 2
- bool result;
- u16 a0_new, b0_new;
- lcnphy_iq_est_t iq_est = { 0, 0, 0 };
- s32 a, b, temp;
- s16 iq_nbits, qq_nbits, arsh, brsh;
- s32 iq;
- u32 ii, qq;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- a0_new = ((read_phy_reg(pi, 0x645) & (0x3ff << 0)) >> 0);
- b0_new = ((read_phy_reg(pi, 0x646) & (0x3ff << 0)) >> 0);
- mod_phy_reg(pi, 0x6d1, (0x1 << 2), (0) << 2);
-
- mod_phy_reg(pi, 0x64b, (0x1 << 6), (1) << 6);
-
- wlc_lcnphy_set_rx_iq_comp(pi, 0, 0);
-
- result = wlc_lcnphy_rx_iq_est(pi, num_samps, 32, &iq_est);
- if (!result)
- goto cleanup;
-
- iq = (s32) iq_est.iq_prod;
- ii = iq_est.i_pwr;
- qq = iq_est.q_pwr;
-
- if ((ii + qq) < LCNPHY_MIN_RXIQ_PWR) {
- result = false;
- goto cleanup;
- }
-
- iq_nbits = wlc_phy_nbits(iq);
- qq_nbits = wlc_phy_nbits(qq);
-
- arsh = 10 - (30 - iq_nbits);
- if (arsh >= 0) {
- a = (-(iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
- temp = (s32) (ii >> arsh);
- if (temp == 0) {
- return false;
- }
- } else {
- a = (-(iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
- temp = (s32) (ii << -arsh);
- if (temp == 0) {
- return false;
- }
- }
- a /= temp;
- brsh = qq_nbits - 31 + 20;
- if (brsh >= 0) {
- b = (qq << (31 - qq_nbits));
- temp = (s32) (ii >> brsh);
- if (temp == 0) {
- return false;
- }
- } else {
- b = (qq << (31 - qq_nbits));
- temp = (s32) (ii << -brsh);
- if (temp == 0) {
- return false;
- }
- }
- b /= temp;
- b -= a * a;
- b = (s32) int_sqrt((unsigned long) b);
- b -= (1 << 10);
- a0_new = (u16) (a & 0x3ff);
- b0_new = (u16) (b & 0x3ff);
- cleanup:
-
- wlc_lcnphy_set_rx_iq_comp(pi, a0_new, b0_new);
-
- mod_phy_reg(pi, 0x64b, (0x1 << 0), (1) << 0);
-
- mod_phy_reg(pi, 0x64b, (0x1 << 3), (1) << 3);
-
- pi_lcn->lcnphy_cal_results.rxiqcal_coeff_a0 = a0_new;
- pi_lcn->lcnphy_cal_results.rxiqcal_coeff_b0 = b0_new;
-
- return result;
-}
-
-static bool
-wlc_lcnphy_rx_iq_cal(phy_info_t *pi, const lcnphy_rx_iqcomp_t *iqcomp,
- int iqcomp_sz, bool tx_switch, bool rx_switch, int module,
- int tx_gain_idx)
-{
- lcnphy_txgains_t old_gains;
- u16 tx_pwr_ctrl;
- u8 tx_gain_index_old = 0;
- bool result = false, tx_gain_override_old = false;
- u16 i, Core1TxControl_old, RFOverride0_old,
- RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old,
- rfoverride3_old, rfoverride3val_old, rfoverride4_old,
- rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
- int tia_gain;
- u32 received_power, rx_pwr_threshold;
- u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
- u16 values_to_save[11];
- s16 *ptr;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- ptr = kmalloc(sizeof(s16) * 131, GFP_ATOMIC);
- if (NULL == ptr) {
- return false;
- }
- if (module == 2) {
- while (iqcomp_sz--) {
- if (iqcomp[iqcomp_sz].chan ==
- CHSPEC_CHANNEL(pi->radio_chanspec)) {
-
- wlc_lcnphy_set_rx_iq_comp(pi,
- (u16)
- iqcomp[iqcomp_sz].a,
- (u16)
- iqcomp[iqcomp_sz].b);
- result = true;
- break;
- }
- }
- goto cal_done;
- }
-
- if (module == 1) {
-
- tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
-
- for (i = 0; i < 11; i++) {
- values_to_save[i] =
- read_radio_reg(pi, rxiq_cal_rf_reg[i]);
- }
- Core1TxControl_old = read_phy_reg(pi, 0x631);
-
- or_phy_reg(pi, 0x631, 0x0015);
-
- RFOverride0_old = read_phy_reg(pi, 0x44c);
- RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
- rfoverride2_old = read_phy_reg(pi, 0x4b0);
- rfoverride2val_old = read_phy_reg(pi, 0x4b1);
- rfoverride3_old = read_phy_reg(pi, 0x4f9);
- rfoverride3val_old = read_phy_reg(pi, 0x4fa);
- rfoverride4_old = read_phy_reg(pi, 0x938);
- rfoverride4val_old = read_phy_reg(pi, 0x939);
- afectrlovr_old = read_phy_reg(pi, 0x43b);
- afectrlovrval_old = read_phy_reg(pi, 0x43c);
- old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
- old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
-
- tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
- if (tx_gain_override_old) {
- wlc_lcnphy_get_tx_gain(pi, &old_gains);
- tx_gain_index_old = pi_lcn->lcnphy_current_index;
- }
-
- wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
-
- mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
-
- mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
- mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
-
- write_radio_reg(pi, RADIO_2064_REG116, 0x06);
- write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
- write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
- write_radio_reg(pi, RADIO_2064_REG098, 0x03);
- write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
- mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
- write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
- write_radio_reg(pi, RADIO_2064_REG114, 0x01);
- write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
- write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
-
- mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
- mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
- mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
- mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
- mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
- mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
- mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
- mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
- mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
-
- mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
-
- wlc_lcnphy_start_tx_tone(pi, 2000, 120, 0);
- write_phy_reg(pi, 0x6da, 0xffff);
- or_phy_reg(pi, 0x6db, 0x3);
- wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
- wlc_lcnphy_rx_gain_override_enable(pi, true);
-
- tia_gain = 8;
- rx_pwr_threshold = 950;
- while (tia_gain > 0) {
- tia_gain -= 1;
- wlc_lcnphy_set_rx_gain_by_distribution(pi,
- 0, 0, 2, 2,
- (u16)
- tia_gain, 1, 0);
- udelay(500);
-
- received_power =
- wlc_lcnphy_measure_digital_power(pi, 2000);
- if (received_power < rx_pwr_threshold)
- break;
- }
- result = wlc_lcnphy_calc_rx_iq_comp(pi, 0xffff);
-
- wlc_lcnphy_stop_tx_tone(pi);
-
- write_phy_reg(pi, 0x631, Core1TxControl_old);
-
- write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
- write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
- write_phy_reg(pi, 0x4b0, rfoverride2_old);
- write_phy_reg(pi, 0x4b1, rfoverride2val_old);
- write_phy_reg(pi, 0x4f9, rfoverride3_old);
- write_phy_reg(pi, 0x4fa, rfoverride3val_old);
- write_phy_reg(pi, 0x938, rfoverride4_old);
- write_phy_reg(pi, 0x939, rfoverride4val_old);
- write_phy_reg(pi, 0x43b, afectrlovr_old);
- write_phy_reg(pi, 0x43c, afectrlovrval_old);
- write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
- write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
-
- wlc_lcnphy_clear_trsw_override(pi);
-
- mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
-
- for (i = 0; i < 11; i++) {
- write_radio_reg(pi, rxiq_cal_rf_reg[i],
- values_to_save[i]);
- }
-
- if (tx_gain_override_old) {
- wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
- } else
- wlc_lcnphy_disable_tx_gain_override(pi);
- wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
-
- wlc_lcnphy_rx_gain_override_enable(pi, false);
- }
-
- cal_done:
- kfree(ptr);
- return result;
-}
-
-static void wlc_lcnphy_temp_adj(phy_info_t *pi)
-{
- if (NORADIO_ENAB(pi->pubpi))
- return;
-}
-
-static void wlc_lcnphy_glacial_timer_based_cal(phy_info_t *pi)
-{
- bool suspend;
- s8 index;
- u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
- suspend =
- (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- wlc_lcnphy_deaf_mode(pi, true);
- pi->phy_lastcal = pi->sh->now;
- pi->phy_forcecal = false;
- index = pi_lcn->lcnphy_current_index;
-
- wlc_lcnphy_txpwrtbl_iqlo_cal(pi);
-
- wlc_lcnphy_set_tx_pwr_by_index(pi, index);
- wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_pwrctrl);
- wlc_lcnphy_deaf_mode(pi, false);
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
-
-}
-
-static void wlc_lcnphy_periodic_cal(phy_info_t *pi)
-{
- bool suspend, full_cal;
- const lcnphy_rx_iqcomp_t *rx_iqcomp;
- int rx_iqcomp_sz;
- u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- s8 index;
- phytbl_info_t tab;
- s32 a1, b0, b1;
- s32 tssi, pwr, maxtargetpwr, mintargetpwr;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- pi->phy_lastcal = pi->sh->now;
- pi->phy_forcecal = false;
- full_cal =
- (pi_lcn->lcnphy_full_cal_channel !=
- CHSPEC_CHANNEL(pi->radio_chanspec));
- pi_lcn->lcnphy_full_cal_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
- index = pi_lcn->lcnphy_current_index;
-
- suspend =
- (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend) {
-
- wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- }
- wlc_lcnphy_deaf_mode(pi, true);
-
- wlc_lcnphy_txpwrtbl_iqlo_cal(pi);
-
- rx_iqcomp = lcnphy_rx_iqcomp_table_rev0;
- rx_iqcomp_sz = ARRAY_SIZE(lcnphy_rx_iqcomp_table_rev0);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 1))
- wlc_lcnphy_rx_iq_cal(pi, NULL, 0, true, false, 1, 40);
- else
- wlc_lcnphy_rx_iq_cal(pi, NULL, 0, true, false, 1, 127);
-
- if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) {
-
- wlc_lcnphy_idle_tssi_est((wlc_phy_t *) pi);
-
- b0 = pi->txpa_2g[0];
- b1 = pi->txpa_2g[1];
- a1 = pi->txpa_2g[2];
- maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1);
- mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1);
-
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_ptr = &pwr;
- tab.tbl_len = 1;
- tab.tbl_offset = 0;
- for (tssi = 0; tssi < 128; tssi++) {
- pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1);
- pwr = (pwr < mintargetpwr) ? mintargetpwr : pwr;
- wlc_lcnphy_write_table(pi, &tab);
- tab.tbl_offset++;
- }
- }
-
- wlc_lcnphy_set_tx_pwr_by_index(pi, index);
- wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_pwrctrl);
- wlc_lcnphy_deaf_mode(pi, false);
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
-}
-
-void wlc_lcnphy_calib_modes(phy_info_t *pi, uint mode)
-{
- u16 temp_new;
- int temp1, temp2, temp_diff;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- switch (mode) {
- case PHY_PERICAL_CHAN:
-
- break;
- case PHY_FULLCAL:
- wlc_lcnphy_periodic_cal(pi);
- break;
- case PHY_PERICAL_PHYINIT:
- wlc_lcnphy_periodic_cal(pi);
- break;
- case PHY_PERICAL_WATCHDOG:
- if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
- temp_new = wlc_lcnphy_tempsense(pi, 0);
- temp1 = LCNPHY_TEMPSENSE(temp_new);
- temp2 = LCNPHY_TEMPSENSE(pi_lcn->lcnphy_cal_temper);
- temp_diff = temp1 - temp2;
- if ((pi_lcn->lcnphy_cal_counter > 90) ||
- (temp_diff > 60) || (temp_diff < -60)) {
- wlc_lcnphy_glacial_timer_based_cal(pi);
- wlc_2064_vco_cal(pi);
- pi_lcn->lcnphy_cal_temper = temp_new;
- pi_lcn->lcnphy_cal_counter = 0;
- } else
- pi_lcn->lcnphy_cal_counter++;
- }
- break;
- case LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL:
- if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
- wlc_lcnphy_tx_power_adjustment((wlc_phy_t *) pi);
- break;
- }
-}
-
-void wlc_lcnphy_get_tssi(phy_info_t *pi, s8 *ofdm_pwr, s8 *cck_pwr)
-{
- s8 cck_offset;
- u16 status;
- status = (read_phy_reg(pi, 0x4ab));
- if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi) &&
- (status & (0x1 << 15))) {
- *ofdm_pwr = (s8) (((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
- >> 0) >> 1);
-
- if (wlc_phy_tpc_isenabled_lcnphy(pi))
- cck_offset = pi->tx_power_offset[TXP_FIRST_CCK];
- else
- cck_offset = 0;
-
- *cck_pwr = *ofdm_pwr + cck_offset;
- } else {
- *cck_pwr = 0;
- *ofdm_pwr = 0;
- }
-}
-
-void WLBANDINITFN(wlc_phy_cal_init_lcnphy) (phy_info_t *pi)
-{
- return;
-
-}
-
-static void wlc_lcnphy_set_chanspec_tweaks(phy_info_t *pi, chanspec_t chanspec)
-{
- u8 channel = CHSPEC_CHANNEL(chanspec);
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- if (channel == 14) {
- mod_phy_reg(pi, 0x448, (0x3 << 8), (2) << 8);
-
- } else {
- mod_phy_reg(pi, 0x448, (0x3 << 8), (1) << 8);
-
- }
- pi_lcn->lcnphy_bandedge_corr = 2;
- if (channel == 1)
- pi_lcn->lcnphy_bandedge_corr = 4;
-
- if (channel == 1 || channel == 2 || channel == 3 ||
- channel == 4 || channel == 9 ||
- channel == 10 || channel == 11 || channel == 12) {
- si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03000c04);
- si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x0);
- si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x200005c0);
-
- si_pmu_pllupd(pi->sh->sih);
- write_phy_reg(pi, 0x942, 0);
- wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
- pi_lcn->lcnphy_spurmod = 0;
- mod_phy_reg(pi, 0x424, (0xff << 8), (0x1b) << 8);
-
- write_phy_reg(pi, 0x425, 0x5907);
- } else {
- si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03140c04);
- si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x333333);
- si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x202c2820);
-
- si_pmu_pllupd(pi->sh->sih);
- write_phy_reg(pi, 0x942, 0);
- wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
-
- pi_lcn->lcnphy_spurmod = 0;
- mod_phy_reg(pi, 0x424, (0xff << 8), (0x1f) << 8);
-
- write_phy_reg(pi, 0x425, 0x590a);
- }
-
- or_phy_reg(pi, 0x44a, 0x44);
- write_phy_reg(pi, 0x44a, 0x80);
-}
-
-void wlc_lcnphy_tx_power_adjustment(wlc_phy_t *ppi)
-{
- s8 index;
- u16 index2;
- phy_info_t *pi = (phy_info_t *) ppi;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
- u16 SAVE_txpwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi) && SAVE_txpwrctrl) {
- index = wlc_lcnphy_tempcompensated_txpwrctrl(pi);
- index2 = (u16) (index * 2);
- mod_phy_reg(pi, 0x4a9, (0x1ff << 0), (index2) << 0);
-
- pi_lcn->lcnphy_current_index = (s8)
- ((read_phy_reg(pi, 0x4a9) & 0xFF) / 2);
- }
-}
-
-static void wlc_lcnphy_set_rx_iq_comp(phy_info_t *pi, u16 a, u16 b)
-{
- mod_phy_reg(pi, 0x645, (0x3ff << 0), (a) << 0);
-
- mod_phy_reg(pi, 0x646, (0x3ff << 0), (b) << 0);
-
- mod_phy_reg(pi, 0x647, (0x3ff << 0), (a) << 0);
-
- mod_phy_reg(pi, 0x648, (0x3ff << 0), (b) << 0);
-
- mod_phy_reg(pi, 0x649, (0x3ff << 0), (a) << 0);
-
- mod_phy_reg(pi, 0x64a, (0x3ff << 0), (b) << 0);
-
-}
-
-void WLBANDINITFN(wlc_phy_init_lcnphy) (phy_info_t *pi)
-{
- u8 phybw40;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
- phybw40 = CHSPEC_IS40(pi->radio_chanspec);
-
- pi_lcn->lcnphy_cal_counter = 0;
- pi_lcn->lcnphy_cal_temper = pi_lcn->lcnphy_rawtempsense;
-
- or_phy_reg(pi, 0x44a, 0x80);
- and_phy_reg(pi, 0x44a, 0x7f);
-
- wlc_lcnphy_afe_clk_init(pi, AFE_CLK_INIT_MODE_TXRX2X);
-
- write_phy_reg(pi, 0x60a, 160);
-
- write_phy_reg(pi, 0x46a, 25);
-
- wlc_lcnphy_baseband_init(pi);
-
- wlc_lcnphy_radio_init(pi);
-
- if (CHSPEC_IS2G(pi->radio_chanspec))
- wlc_lcnphy_tx_pwr_ctrl_init((wlc_phy_t *) pi);
-
- wlc_phy_chanspec_set((wlc_phy_t *) pi, pi->radio_chanspec);
-
- si_pmu_regcontrol(pi->sh->sih, 0, 0xf, 0x9);
-
- si_pmu_chipcontrol(pi->sh->sih, 0, 0xffffffff, 0x03CDDDDD);
-
- if ((pi->sh->boardflags & BFL_FEM)
- && wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
- wlc_lcnphy_set_tx_pwr_by_index(pi, FIXED_TXPWR);
-
- wlc_lcnphy_agc_temp_init(pi);
-
- wlc_lcnphy_temp_adj(pi);
-
- mod_phy_reg(pi, 0x448, (0x1 << 14), (1) << 14);
-
- udelay(100);
- mod_phy_reg(pi, 0x448, (0x1 << 14), (0) << 14);
-
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_HW);
- pi_lcn->lcnphy_noise_samples = LCNPHY_NOISE_SAMPLES_DEFAULT;
- wlc_lcnphy_calib_modes(pi, PHY_PERICAL_PHYINIT);
-}
-
-static void
-wlc_lcnphy_tx_iqlo_loopback(phy_info_t *pi, u16 *values_to_save)
-{
- u16 vmid;
- int i;
- for (i = 0; i < 20; i++) {
- values_to_save[i] =
- read_radio_reg(pi, iqlo_loopback_rf_regs[i]);
- }
-
- mod_phy_reg(pi, 0x44c, (0x1 << 12), 1 << 12);
- mod_phy_reg(pi, 0x44d, (0x1 << 14), 1 << 14);
-
- mod_phy_reg(pi, 0x44c, (0x1 << 11), 1 << 11);
- mod_phy_reg(pi, 0x44d, (0x1 << 13), 0 << 13);
-
- mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
- mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
-
- mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 2))
- and_radio_reg(pi, RADIO_2064_REG03A, 0xFD);
- else
- and_radio_reg(pi, RADIO_2064_REG03A, 0xF9);
- or_radio_reg(pi, RADIO_2064_REG11A, 0x1);
-
- or_radio_reg(pi, RADIO_2064_REG036, 0x01);
- or_radio_reg(pi, RADIO_2064_REG11A, 0x18);
- udelay(20);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
- if (CHSPEC_IS5G(pi->radio_chanspec))
- mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0);
- else
- or_radio_reg(pi, RADIO_2064_REG03A, 1);
- } else {
- if (CHSPEC_IS5G(pi->radio_chanspec))
- mod_radio_reg(pi, RADIO_2064_REG03A, 3, 1);
- else
- or_radio_reg(pi, RADIO_2064_REG03A, 0x3);
- }
-
- udelay(20);
-
- write_radio_reg(pi, RADIO_2064_REG025, 0xF);
- if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
- if (CHSPEC_IS5G(pi->radio_chanspec))
- mod_radio_reg(pi, RADIO_2064_REG028, 0xF, 0x4);
- else
- mod_radio_reg(pi, RADIO_2064_REG028, 0xF, 0x6);
- } else {
- if (CHSPEC_IS5G(pi->radio_chanspec))
- mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x4 << 1);
- else
- mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0x6 << 1);
- }
-
- udelay(20);
-
- write_radio_reg(pi, RADIO_2064_REG005, 0x8);
- or_radio_reg(pi, RADIO_2064_REG112, 0x80);
- udelay(20);
-
- or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
- or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
- udelay(20);
-
- or_radio_reg(pi, RADIO_2064_REG00B, 0x7);
- or_radio_reg(pi, RADIO_2064_REG113, 0x10);
- udelay(20);
-
- write_radio_reg(pi, RADIO_2064_REG007, 0x1);
- udelay(20);
-
- vmid = 0x2A6;
- mod_radio_reg(pi, RADIO_2064_REG0FC, 0x3 << 0, (vmid >> 8) & 0x3);
- write_radio_reg(pi, RADIO_2064_REG0FD, (vmid & 0xff));
- or_radio_reg(pi, RADIO_2064_REG11F, 0x44);
- udelay(20);
-
- or_radio_reg(pi, RADIO_2064_REG0FF, 0x10);
- udelay(20);
- write_radio_reg(pi, RADIO_2064_REG012, 0x02);
- or_radio_reg(pi, RADIO_2064_REG112, 0x06);
- write_radio_reg(pi, RADIO_2064_REG036, 0x11);
- write_radio_reg(pi, RADIO_2064_REG059, 0xcc);
- write_radio_reg(pi, RADIO_2064_REG05C, 0x2e);
- write_radio_reg(pi, RADIO_2064_REG078, 0xd7);
- write_radio_reg(pi, RADIO_2064_REG092, 0x15);
-}
-
-static void
-wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
- s16 *ptr, int mode)
-{
- u32 curval1, curval2, stpptr, curptr, strptr, val;
- u16 sslpnCalibClkEnCtrl, timer;
- u16 old_sslpnCalibClkEnCtrl;
- s16 imag, real;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- timer = 0;
- old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
-
- curval1 = R_REG(&pi->regs->psm_corectlsts);
- ptr[130] = 0;
- W_REG(&pi->regs->psm_corectlsts, ((1 << 6) | curval1));
-
- W_REG(&pi->regs->smpl_clct_strptr, 0x7E00);
- W_REG(&pi->regs->smpl_clct_stpptr, 0x8000);
- udelay(20);
- curval2 = R_REG(&pi->regs->psm_phy_hdr_param);
- W_REG(&pi->regs->psm_phy_hdr_param, curval2 | 0x30);
-
- write_phy_reg(pi, 0x555, 0x0);
- write_phy_reg(pi, 0x5a6, 0x5);
-
- write_phy_reg(pi, 0x5a2, (u16) (mode | mode << 6));
- write_phy_reg(pi, 0x5cf, 3);
- write_phy_reg(pi, 0x5a5, 0x3);
- write_phy_reg(pi, 0x583, 0x0);
- write_phy_reg(pi, 0x584, 0x0);
- write_phy_reg(pi, 0x585, 0x0fff);
- write_phy_reg(pi, 0x586, 0x0000);
-
- write_phy_reg(pi, 0x580, 0x4501);
-
- sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
- write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl | 0x2008));
- stpptr = R_REG(&pi->regs->smpl_clct_stpptr);
- curptr = R_REG(&pi->regs->smpl_clct_curptr);
- do {
- udelay(10);
- curptr = R_REG(&pi->regs->smpl_clct_curptr);
- timer++;
- } while ((curptr != stpptr) && (timer < 500));
-
- W_REG(&pi->regs->psm_phy_hdr_param, 0x2);
- strptr = 0x7E00;
- W_REG(&pi->regs->tplatewrptr, strptr);
- while (strptr < 0x8000) {
- val = R_REG(&pi->regs->tplatewrdata);
- imag = ((val >> 16) & 0x3ff);
- real = ((val) & 0x3ff);
- if (imag > 511) {
- imag -= 1024;
- }
- if (real > 511) {
- real -= 1024;
- }
- if (pi_lcn->lcnphy_iqcal_swp_dis)
- ptr[(strptr - 0x7E00) / 4] = real;
- else
- ptr[(strptr - 0x7E00) / 4] = imag;
- if (clip_detect_algo) {
- if (imag > thresh || imag < -thresh) {
- strptr = 0x8000;
- ptr[130] = 1;
- }
- }
- strptr += 4;
- }
-
- write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
- W_REG(&pi->regs->psm_phy_hdr_param, curval2);
- W_REG(&pi->regs->psm_corectlsts, curval1);
-}
-
-static void wlc_lcnphy_tx_iqlo_soft_cal_full(phy_info_t *pi)
-{
- lcnphy_unsign16_struct iqcc0, locc2, locc3, locc4;
-
- wlc_lcnphy_set_cc(pi, 0, 0, 0);
- wlc_lcnphy_set_cc(pi, 2, 0, 0);
- wlc_lcnphy_set_cc(pi, 3, 0, 0);
- wlc_lcnphy_set_cc(pi, 4, 0, 0);
-
- wlc_lcnphy_a1(pi, 4, 0, 0);
- wlc_lcnphy_a1(pi, 3, 0, 0);
- wlc_lcnphy_a1(pi, 2, 3, 2);
- wlc_lcnphy_a1(pi, 0, 5, 8);
- wlc_lcnphy_a1(pi, 2, 2, 1);
- wlc_lcnphy_a1(pi, 0, 4, 3);
-
- iqcc0 = wlc_lcnphy_get_cc(pi, 0);
- locc2 = wlc_lcnphy_get_cc(pi, 2);
- locc3 = wlc_lcnphy_get_cc(pi, 3);
- locc4 = wlc_lcnphy_get_cc(pi, 4);
-}
-
-static void
-wlc_lcnphy_set_cc(phy_info_t *pi, int cal_type, s16 coeff_x, s16 coeff_y)
-{
- u16 di0dq0;
- u16 x, y, data_rf;
- int k;
- switch (cal_type) {
- case 0:
- wlc_lcnphy_set_tx_iqcc(pi, coeff_x, coeff_y);
- break;
- case 2:
- di0dq0 = (coeff_x & 0xff) << 8 | (coeff_y & 0xff);
- wlc_lcnphy_set_tx_locc(pi, di0dq0);
- break;
- case 3:
- k = wlc_lcnphy_calc_floor(coeff_x, 0);
- y = 8 + k;
- k = wlc_lcnphy_calc_floor(coeff_x, 1);
- x = 8 - k;
- data_rf = (x * 16 + y);
- write_radio_reg(pi, RADIO_2064_REG089, data_rf);
- k = wlc_lcnphy_calc_floor(coeff_y, 0);
- y = 8 + k;
- k = wlc_lcnphy_calc_floor(coeff_y, 1);
- x = 8 - k;
- data_rf = (x * 16 + y);
- write_radio_reg(pi, RADIO_2064_REG08A, data_rf);
- break;
- case 4:
- k = wlc_lcnphy_calc_floor(coeff_x, 0);
- y = 8 + k;
- k = wlc_lcnphy_calc_floor(coeff_x, 1);
- x = 8 - k;
- data_rf = (x * 16 + y);
- write_radio_reg(pi, RADIO_2064_REG08B, data_rf);
- k = wlc_lcnphy_calc_floor(coeff_y, 0);
- y = 8 + k;
- k = wlc_lcnphy_calc_floor(coeff_y, 1);
- x = 8 - k;
- data_rf = (x * 16 + y);
- write_radio_reg(pi, RADIO_2064_REG08C, data_rf);
- break;
- }
-}
-
-static lcnphy_unsign16_struct wlc_lcnphy_get_cc(phy_info_t *pi, int cal_type)
-{
- u16 a, b, didq;
- u8 di0, dq0, ei, eq, fi, fq;
- lcnphy_unsign16_struct cc;
- cc.re = 0;
- cc.im = 0;
- switch (cal_type) {
- case 0:
- wlc_lcnphy_get_tx_iqcc(pi, &a, &b);
- cc.re = a;
- cc.im = b;
- break;
- case 2:
- didq = wlc_lcnphy_get_tx_locc(pi);
- di0 = (((didq & 0xff00) << 16) >> 24);
- dq0 = (((didq & 0x00ff) << 24) >> 24);
- cc.re = (u16) di0;
- cc.im = (u16) dq0;
- break;
- case 3:
- wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq);
- cc.re = (u16) ei;
- cc.im = (u16) eq;
- break;
- case 4:
- wlc_lcnphy_get_radio_loft(pi, &ei, &eq, &fi, &fq);
- cc.re = (u16) fi;
- cc.im = (u16) fq;
- break;
- }
- return cc;
-}
-
-static void
-wlc_lcnphy_a1(phy_info_t *pi, int cal_type, int num_levels, int step_size_lg2)
-{
- const lcnphy_spb_tone_t *phy_c1;
- lcnphy_spb_tone_t phy_c2;
- lcnphy_unsign16_struct phy_c3;
- int phy_c4, phy_c5, k, l, j, phy_c6;
- u16 phy_c7, phy_c8, phy_c9;
- s16 phy_c10, phy_c11, phy_c12, phy_c13, phy_c14, phy_c15, phy_c16;
- s16 *ptr, phy_c17;
- s32 phy_c18, phy_c19;
- u32 phy_c20, phy_c21;
- bool phy_c22, phy_c23, phy_c24, phy_c25;
- u16 phy_c26, phy_c27;
- u16 phy_c28, phy_c29, phy_c30;
- u16 phy_c31;
- u16 *phy_c32;
- phy_c21 = 0;
- phy_c10 = phy_c13 = phy_c14 = phy_c8 = 0;
- ptr = kmalloc(sizeof(s16) * 131, GFP_ATOMIC);
- if (NULL == ptr) {
- return;
- }
-
- phy_c32 = kmalloc(sizeof(u16) * 20, GFP_ATOMIC);
- if (NULL == phy_c32) {
- kfree(ptr);
- return;
- }
- phy_c26 = read_phy_reg(pi, 0x6da);
- phy_c27 = read_phy_reg(pi, 0x6db);
- phy_c31 = read_radio_reg(pi, RADIO_2064_REG026);
- write_phy_reg(pi, 0x93d, 0xC0);
-
- wlc_lcnphy_start_tx_tone(pi, 3750, 88, 0);
- write_phy_reg(pi, 0x6da, 0xffff);
- or_phy_reg(pi, 0x6db, 0x3);
-
- wlc_lcnphy_tx_iqlo_loopback(pi, phy_c32);
- udelay(500);
- phy_c28 = read_phy_reg(pi, 0x938);
- phy_c29 = read_phy_reg(pi, 0x4d7);
- phy_c30 = read_phy_reg(pi, 0x4d8);
- or_phy_reg(pi, 0x938, 0x1 << 2);
- or_phy_reg(pi, 0x4d7, 0x1 << 2);
- or_phy_reg(pi, 0x4d7, 0x1 << 3);
- mod_phy_reg(pi, 0x4d7, (0x7 << 12), 0x2 << 12);
- or_phy_reg(pi, 0x4d8, 1 << 0);
- or_phy_reg(pi, 0x4d8, 1 << 1);
- mod_phy_reg(pi, 0x4d8, (0x3ff << 2), 0x23A << 2);
- mod_phy_reg(pi, 0x4d8, (0x7 << 12), 0x7 << 12);
- phy_c1 = &lcnphy_spb_tone_3750[0];
- phy_c4 = 32;
-
- if (num_levels == 0) {
- if (cal_type != 0) {
- num_levels = 4;
- } else {
- num_levels = 9;
- }
- }
- if (step_size_lg2 == 0) {
- if (cal_type != 0) {
- step_size_lg2 = 3;
- } else {
- step_size_lg2 = 8;
- }
- }
-
- phy_c7 = (1 << step_size_lg2);
- phy_c3 = wlc_lcnphy_get_cc(pi, cal_type);
- phy_c15 = (s16) phy_c3.re;
- phy_c16 = (s16) phy_c3.im;
- if (cal_type == 2) {
- if (phy_c3.re > 127)
- phy_c15 = phy_c3.re - 256;
- if (phy_c3.im > 127)
- phy_c16 = phy_c3.im - 256;
- }
- wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
- udelay(20);
- for (phy_c8 = 0; phy_c7 != 0 && phy_c8 < num_levels; phy_c8++) {
- phy_c23 = 1;
- phy_c22 = 0;
- switch (cal_type) {
- case 0:
- phy_c10 = 511;
- break;
- case 2:
- phy_c10 = 127;
- break;
- case 3:
- phy_c10 = 15;
- break;
- case 4:
- phy_c10 = 15;
- break;
- }
-
- phy_c9 = read_phy_reg(pi, 0x93d);
- phy_c9 = 2 * phy_c9;
- phy_c24 = 0;
- phy_c5 = 7;
- phy_c25 = 1;
- while (1) {
- write_radio_reg(pi, RADIO_2064_REG026,
- (phy_c5 & 0x7) | ((phy_c5 & 0x7) << 4));
- udelay(50);
- phy_c22 = 0;
- ptr[130] = 0;
- wlc_lcnphy_samp_cap(pi, 1, phy_c9, &ptr[0], 2);
- if (ptr[130] == 1)
- phy_c22 = 1;
- if (phy_c22)
- phy_c5 -= 1;
- if ((phy_c22 != phy_c24) && (!phy_c25))
- break;
- if (!phy_c22)
- phy_c5 += 1;
- if (phy_c5 <= 0 || phy_c5 >= 7)
- break;
- phy_c24 = phy_c22;
- phy_c25 = 0;
- }
-
- if (phy_c5 < 0)
- phy_c5 = 0;
- else if (phy_c5 > 7)
- phy_c5 = 7;
-
- for (k = -phy_c7; k <= phy_c7; k += phy_c7) {
- for (l = -phy_c7; l <= phy_c7; l += phy_c7) {
- phy_c11 = phy_c15 + k;
- phy_c12 = phy_c16 + l;
-
- if (phy_c11 < -phy_c10)
- phy_c11 = -phy_c10;
- else if (phy_c11 > phy_c10)
- phy_c11 = phy_c10;
- if (phy_c12 < -phy_c10)
- phy_c12 = -phy_c10;
- else if (phy_c12 > phy_c10)
- phy_c12 = phy_c10;
- wlc_lcnphy_set_cc(pi, cal_type, phy_c11,
- phy_c12);
- udelay(20);
- wlc_lcnphy_samp_cap(pi, 0, 0, ptr, 2);
-
- phy_c18 = 0;
- phy_c19 = 0;
- for (j = 0; j < 128; j++) {
- if (cal_type != 0) {
- phy_c6 = j % phy_c4;
- } else {
- phy_c6 = (2 * j) % phy_c4;
- }
- phy_c2.re = phy_c1[phy_c6].re;
- phy_c2.im = phy_c1[phy_c6].im;
- phy_c17 = ptr[j];
- phy_c18 = phy_c18 + phy_c17 * phy_c2.re;
- phy_c19 = phy_c19 + phy_c17 * phy_c2.im;
- }
-
- phy_c18 = phy_c18 >> 10;
- phy_c19 = phy_c19 >> 10;
- phy_c20 =
- ((phy_c18 * phy_c18) + (phy_c19 * phy_c19));
-
- if (phy_c23 || phy_c20 < phy_c21) {
- phy_c21 = phy_c20;
- phy_c13 = phy_c11;
- phy_c14 = phy_c12;
- }
- phy_c23 = 0;
- }
- }
- phy_c23 = 1;
- phy_c15 = phy_c13;
- phy_c16 = phy_c14;
- phy_c7 = phy_c7 >> 1;
- wlc_lcnphy_set_cc(pi, cal_type, phy_c15, phy_c16);
- udelay(20);
- }
- goto cleanup;
- cleanup:
- wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, phy_c32);
- wlc_lcnphy_stop_tx_tone(pi);
- write_phy_reg(pi, 0x6da, phy_c26);
- write_phy_reg(pi, 0x6db, phy_c27);
- write_phy_reg(pi, 0x938, phy_c28);
- write_phy_reg(pi, 0x4d7, phy_c29);
- write_phy_reg(pi, 0x4d8, phy_c30);
- write_radio_reg(pi, RADIO_2064_REG026, phy_c31);
-
- kfree(phy_c32);
- kfree(ptr);
-}
-
-static void
-wlc_lcnphy_tx_iqlo_loopback_cleanup(phy_info_t *pi, u16 *values_to_save)
-{
- int i;
-
- and_phy_reg(pi, 0x44c, 0x0 >> 11);
-
- and_phy_reg(pi, 0x43b, 0xC);
-
- for (i = 0; i < 20; i++) {
- write_radio_reg(pi, iqlo_loopback_rf_regs[i],
- values_to_save[i]);
- }
-}
-
-static void
-WLBANDINITFN(wlc_lcnphy_load_tx_gain_table) (phy_info_t *pi,
- const lcnphy_tx_gain_tbl_entry *
- gain_table) {
- u32 j;
- phytbl_info_t tab;
- u32 val;
- u16 pa_gain;
- u16 gm_gain;
-
- if (CHSPEC_IS5G(pi->radio_chanspec))
- pa_gain = 0x70;
- else
- pa_gain = 0x70;
-
- if (pi->sh->boardflags & BFL_FEM)
- pa_gain = 0x10;
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_len = 1;
- tab.tbl_ptr = &val;
-
- for (j = 0; j < 128; j++) {
- gm_gain = gain_table[j].gm;
- val = (((u32) pa_gain << 24) |
- (gain_table[j].pad << 16) |
- (gain_table[j].pga << 8) | gm_gain);
-
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + j;
- wlc_lcnphy_write_table(pi, &tab);
-
- val = (gain_table[j].dac << 28) | (gain_table[j].bb_mult << 20);
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + j;
- wlc_lcnphy_write_table(pi, &tab);
- }
-}
-
-static void wlc_lcnphy_load_rfpower(phy_info_t *pi)
-{
- phytbl_info_t tab;
- u32 val, bbmult, rfgain;
- u8 index;
- u8 scale_factor = 1;
- s16 temp, temp1, temp2, qQ, qQ1, qQ2, shift;
-
- tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
- tab.tbl_width = 32;
- tab.tbl_len = 1;
-
- for (index = 0; index < 128; index++) {
- tab.tbl_ptr = &bbmult;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_IQ_OFFSET + index;
- wlc_lcnphy_read_table(pi, &tab);
- bbmult = bbmult >> 20;
-
- tab.tbl_ptr = &rfgain;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_GAIN_OFFSET + index;
- wlc_lcnphy_read_table(pi, &tab);
-
- qm_log10((s32) (bbmult), 0, &temp1, &qQ1);
- qm_log10((s32) (1 << 6), 0, &temp2, &qQ2);
-
- if (qQ1 < qQ2) {
- temp2 = qm_shr16(temp2, qQ2 - qQ1);
- qQ = qQ1;
- } else {
- temp1 = qm_shr16(temp1, qQ1 - qQ2);
- qQ = qQ2;
- }
- temp = qm_sub16(temp1, temp2);
-
- if (qQ >= 4)
- shift = qQ - 4;
- else
- shift = 4 - qQ;
-
- val = (((index << shift) + (5 * temp) +
- (1 << (scale_factor + shift - 3))) >> (scale_factor +
- shift - 2));
-
- tab.tbl_ptr = &val;
- tab.tbl_offset = LCNPHY_TX_PWR_CTRL_PWR_OFFSET + index;
- wlc_lcnphy_write_table(pi, &tab);
- }
-}
-
-static void WLBANDINITFN(wlc_lcnphy_tbl_init) (phy_info_t *pi)
-{
- uint idx;
- u8 phybw40;
- phytbl_info_t tab;
- u32 val;
-
- phybw40 = CHSPEC_IS40(pi->radio_chanspec);
-
- for (idx = 0; idx < dot11lcnphytbl_info_sz_rev0; idx++) {
- wlc_lcnphy_write_table(pi, &dot11lcnphytbl_info_rev0[idx]);
- }
-
- if (pi->sh->boardflags & BFL_FEM_BT) {
- tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
- tab.tbl_width = 16;
- tab.tbl_ptr = &val;
- tab.tbl_len = 1;
- val = 100;
- tab.tbl_offset = 4;
- wlc_lcnphy_write_table(pi, &tab);
- }
-
- tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
- tab.tbl_width = 16;
- tab.tbl_ptr = &val;
- tab.tbl_len = 1;
-
- val = 114;
- tab.tbl_offset = 0;
- wlc_lcnphy_write_table(pi, &tab);
-
- val = 130;
- tab.tbl_offset = 1;
- wlc_lcnphy_write_table(pi, &tab);
-
- val = 6;
- tab.tbl_offset = 8;
- wlc_lcnphy_write_table(pi, &tab);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (pi->sh->boardflags & BFL_FEM)
- wlc_lcnphy_load_tx_gain_table(pi,
- dot11lcnphy_2GHz_extPA_gaintable_rev0);
- else
- wlc_lcnphy_load_tx_gain_table(pi,
- dot11lcnphy_2GHz_gaintable_rev0);
- }
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- for (idx = 0;
- idx < dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
- idx++)
- if (pi->sh->boardflags & BFL_EXTLNA)
- wlc_lcnphy_write_table(pi,
- &dot11lcnphytbl_rx_gain_info_extlna_2G_rev2
- [idx]);
- else
- wlc_lcnphy_write_table(pi,
- &dot11lcnphytbl_rx_gain_info_2G_rev2
- [idx]);
- } else {
- for (idx = 0;
- idx < dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
- idx++)
- if (pi->sh->boardflags & BFL_EXTLNA_5GHz)
- wlc_lcnphy_write_table(pi,
- &dot11lcnphytbl_rx_gain_info_extlna_5G_rev2
- [idx]);
- else
- wlc_lcnphy_write_table(pi,
- &dot11lcnphytbl_rx_gain_info_5G_rev2
- [idx]);
- }
- }
-
- if ((pi->sh->boardflags & BFL_FEM)
- && !(pi->sh->boardflags & BFL_FEM_BT))
- wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313_epa);
- else if (pi->sh->boardflags & BFL_FEM_BT) {
- if (pi->sh->boardrev < 0x1250)
- wlc_lcnphy_write_table(pi,
- &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa);
- else
- wlc_lcnphy_write_table(pi,
- &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250);
- } else
- wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313);
-
- wlc_lcnphy_load_rfpower(pi);
-
- wlc_lcnphy_clear_papd_comptable(pi);
-}
-
-static void WLBANDINITFN(wlc_lcnphy_rev0_baseband_init) (phy_info_t *pi)
-{
- u16 afectrl1;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- write_radio_reg(pi, RADIO_2064_REG11C, 0x0);
-
- write_phy_reg(pi, 0x43b, 0x0);
- write_phy_reg(pi, 0x43c, 0x0);
- write_phy_reg(pi, 0x44c, 0x0);
- write_phy_reg(pi, 0x4e6, 0x0);
- write_phy_reg(pi, 0x4f9, 0x0);
- write_phy_reg(pi, 0x4b0, 0x0);
- write_phy_reg(pi, 0x938, 0x0);
- write_phy_reg(pi, 0x4b0, 0x0);
- write_phy_reg(pi, 0x44e, 0);
-
- or_phy_reg(pi, 0x567, 0x03);
-
- or_phy_reg(pi, 0x44a, 0x44);
- write_phy_reg(pi, 0x44a, 0x80);
-
- if (!(pi->sh->boardflags & BFL_FEM))
- wlc_lcnphy_set_tx_pwr_by_index(pi, 52);
-
- if (0) {
- afectrl1 = 0;
- afectrl1 = (u16) ((pi_lcn->lcnphy_rssi_vf) |
- (pi_lcn->lcnphy_rssi_vc << 4) | (pi_lcn->
- lcnphy_rssi_gs
- << 10));
- write_phy_reg(pi, 0x43e, afectrl1);
- }
-
- mod_phy_reg(pi, 0x634, (0xff << 0), 0xC << 0);
- if (pi->sh->boardflags & BFL_FEM) {
- mod_phy_reg(pi, 0x634, (0xff << 0), 0xA << 0);
-
- write_phy_reg(pi, 0x910, 0x1);
- }
-
- mod_phy_reg(pi, 0x448, (0x3 << 8), 1 << 8);
- mod_phy_reg(pi, 0x608, (0xff << 0), 0x17 << 0);
- mod_phy_reg(pi, 0x604, (0x7ff << 0), 0x3EA << 0);
-
-}
-
-static void WLBANDINITFN(wlc_lcnphy_rev2_baseband_init) (phy_info_t *pi)
-{
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- mod_phy_reg(pi, 0x416, (0xff << 0), 80 << 0);
-
- mod_phy_reg(pi, 0x416, (0xff << 8), 80 << 8);
- }
-}
-
-static void wlc_lcnphy_agc_temp_init(phy_info_t *pi)
-{
- s16 temp;
- phytbl_info_t tab;
- u32 tableBuffer[2];
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- temp = (s16) read_phy_reg(pi, 0x4df);
- pi_lcn->lcnphy_ofdmgainidxtableoffset = (temp & (0xff << 0)) >> 0;
-
- if (pi_lcn->lcnphy_ofdmgainidxtableoffset > 127)
- pi_lcn->lcnphy_ofdmgainidxtableoffset -= 256;
-
- pi_lcn->lcnphy_dsssgainidxtableoffset = (temp & (0xff << 8)) >> 8;
-
- if (pi_lcn->lcnphy_dsssgainidxtableoffset > 127)
- pi_lcn->lcnphy_dsssgainidxtableoffset -= 256;
-
- tab.tbl_ptr = tableBuffer;
- tab.tbl_len = 2;
- tab.tbl_id = 17;
- tab.tbl_offset = 59;
- tab.tbl_width = 32;
- wlc_lcnphy_read_table(pi, &tab);
-
- if (tableBuffer[0] > 63)
- tableBuffer[0] -= 128;
- pi_lcn->lcnphy_tr_R_gain_val = tableBuffer[0];
-
- if (tableBuffer[1] > 63)
- tableBuffer[1] -= 128;
- pi_lcn->lcnphy_tr_T_gain_val = tableBuffer[1];
-
- temp = (s16) (read_phy_reg(pi, 0x434)
- & (0xff << 0));
- if (temp > 127)
- temp -= 256;
- pi_lcn->lcnphy_input_pwr_offset_db = (s8) temp;
-
- pi_lcn->lcnphy_Med_Low_Gain_db = (read_phy_reg(pi, 0x424)
- & (0xff << 8))
- >> 8;
- pi_lcn->lcnphy_Very_Low_Gain_db = (read_phy_reg(pi, 0x425)
- & (0xff << 0))
- >> 0;
-
- tab.tbl_ptr = tableBuffer;
- tab.tbl_len = 2;
- tab.tbl_id = LCNPHY_TBL_ID_GAIN_IDX;
- tab.tbl_offset = 28;
- tab.tbl_width = 32;
- wlc_lcnphy_read_table(pi, &tab);
-
- pi_lcn->lcnphy_gain_idx_14_lowword = tableBuffer[0];
- pi_lcn->lcnphy_gain_idx_14_hiword = tableBuffer[1];
-
-}
-
-static void WLBANDINITFN(wlc_lcnphy_bu_tweaks) (phy_info_t *pi)
-{
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- or_phy_reg(pi, 0x805, 0x1);
-
- mod_phy_reg(pi, 0x42f, (0x7 << 0), (0x3) << 0);
-
- mod_phy_reg(pi, 0x030, (0x7 << 0), (0x3) << 0);
-
- write_phy_reg(pi, 0x414, 0x1e10);
- write_phy_reg(pi, 0x415, 0x0640);
-
- mod_phy_reg(pi, 0x4df, (0xff << 8), -9 << 8);
-
- or_phy_reg(pi, 0x44a, 0x44);
- write_phy_reg(pi, 0x44a, 0x80);
- mod_phy_reg(pi, 0x434, (0xff << 0), (0xFD) << 0);
-
- mod_phy_reg(pi, 0x420, (0xff << 0), (16) << 0);
-
- if (!(pi->sh->boardrev < 0x1204))
- mod_radio_reg(pi, RADIO_2064_REG09B, 0xF0, 0xF0);
-
- write_phy_reg(pi, 0x7d6, 0x0902);
- mod_phy_reg(pi, 0x429, (0xf << 0), (0x9) << 0);
-
- mod_phy_reg(pi, 0x429, (0x3f << 4), (0xe) << 4);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
- mod_phy_reg(pi, 0x423, (0xff << 0), (0x46) << 0);
-
- mod_phy_reg(pi, 0x411, (0xff << 0), (1) << 0);
-
- mod_phy_reg(pi, 0x434, (0xff << 0), (0xFF) << 0);
-
- mod_phy_reg(pi, 0x656, (0xf << 0), (2) << 0);
-
- mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
-
- mod_radio_reg(pi, RADIO_2064_REG0F7, 0x4, 0x4);
- mod_radio_reg(pi, RADIO_2064_REG0F1, 0x3, 0);
- mod_radio_reg(pi, RADIO_2064_REG0F2, 0xF8, 0x90);
- mod_radio_reg(pi, RADIO_2064_REG0F3, 0x3, 0x2);
- mod_radio_reg(pi, RADIO_2064_REG0F3, 0xf0, 0xa0);
-
- mod_radio_reg(pi, RADIO_2064_REG11F, 0x2, 0x2);
-
- wlc_lcnphy_clear_tx_power_offsets(pi);
- mod_phy_reg(pi, 0x4d0, (0x1ff << 6), (10) << 6);
-
- }
-}
-
-static void WLBANDINITFN(wlc_lcnphy_baseband_init) (phy_info_t *pi)
-{
-
- wlc_lcnphy_tbl_init(pi);
- wlc_lcnphy_rev0_baseband_init(pi);
- if (LCNREV_IS(pi->pubpi.phy_rev, 2))
- wlc_lcnphy_rev2_baseband_init(pi);
- wlc_lcnphy_bu_tweaks(pi);
-}
-
-static void WLBANDINITFN(wlc_radio_2064_init) (phy_info_t *pi)
-{
- u32 i;
- lcnphy_radio_regs_t *lcnphyregs = NULL;
-
- lcnphyregs = lcnphy_radio_regs_2064;
-
- for (i = 0; lcnphyregs[i].address != 0xffff; i++)
- if (CHSPEC_IS5G(pi->radio_chanspec) && lcnphyregs[i].do_init_a)
- write_radio_reg(pi,
- ((lcnphyregs[i].address & 0x3fff) |
- RADIO_DEFAULT_CORE),
- (u16) lcnphyregs[i].init_a);
- else if (lcnphyregs[i].do_init_g)
- write_radio_reg(pi,
- ((lcnphyregs[i].address & 0x3fff) |
- RADIO_DEFAULT_CORE),
- (u16) lcnphyregs[i].init_g);
-
- write_radio_reg(pi, RADIO_2064_REG032, 0x62);
- write_radio_reg(pi, RADIO_2064_REG033, 0x19);
-
- write_radio_reg(pi, RADIO_2064_REG090, 0x10);
-
- write_radio_reg(pi, RADIO_2064_REG010, 0x00);
-
- if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
-
- write_radio_reg(pi, RADIO_2064_REG060, 0x7f);
- write_radio_reg(pi, RADIO_2064_REG061, 0x72);
- write_radio_reg(pi, RADIO_2064_REG062, 0x7f);
- }
-
- write_radio_reg(pi, RADIO_2064_REG01D, 0x02);
- write_radio_reg(pi, RADIO_2064_REG01E, 0x06);
-
- mod_phy_reg(pi, 0x4ea, (0x7 << 0), 0 << 0);
-
- mod_phy_reg(pi, 0x4ea, (0x7 << 3), 1 << 3);
-
- mod_phy_reg(pi, 0x4ea, (0x7 << 6), 2 << 6);
-
- mod_phy_reg(pi, 0x4ea, (0x7 << 9), 3 << 9);
-
- mod_phy_reg(pi, 0x4ea, (0x7 << 12), 4 << 12);
-
- write_phy_reg(pi, 0x4ea, 0x4688);
-
- mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
-
- mod_phy_reg(pi, 0x4eb, (0x7 << 6), 0 << 6);
-
- mod_phy_reg(pi, 0x46a, (0xffff << 0), 25 << 0);
-
- wlc_lcnphy_set_tx_locc(pi, 0);
-
- wlc_lcnphy_rcal(pi);
-
- wlc_lcnphy_rc_cal(pi);
-}
-
-static void WLBANDINITFN(wlc_lcnphy_radio_init) (phy_info_t *pi)
-{
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- wlc_radio_2064_init(pi);
-}
-
-static void wlc_lcnphy_rcal(phy_info_t *pi)
-{
- u8 rcal_value;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- and_radio_reg(pi, RADIO_2064_REG05B, 0xfD);
-
- or_radio_reg(pi, RADIO_2064_REG004, 0x40);
- or_radio_reg(pi, RADIO_2064_REG120, 0x10);
-
- or_radio_reg(pi, RADIO_2064_REG078, 0x80);
- or_radio_reg(pi, RADIO_2064_REG129, 0x02);
-
- or_radio_reg(pi, RADIO_2064_REG057, 0x01);
-
- or_radio_reg(pi, RADIO_2064_REG05B, 0x02);
- mdelay(5);
- SPINWAIT(!wlc_radio_2064_rcal_done(pi), 10 * 1000 * 1000);
-
- if (wlc_radio_2064_rcal_done(pi)) {
- rcal_value = (u8) read_radio_reg(pi, RADIO_2064_REG05C);
- rcal_value = rcal_value & 0x1f;
- }
-
- and_radio_reg(pi, RADIO_2064_REG05B, 0xfD);
-
- and_radio_reg(pi, RADIO_2064_REG057, 0xFE);
-}
-
-static void wlc_lcnphy_rc_cal(phy_info_t *pi)
-{
- u8 dflt_rc_cal_val;
- u16 flt_val;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- dflt_rc_cal_val = 7;
- if (LCNREV_IS(pi->pubpi.phy_rev, 1))
- dflt_rc_cal_val = 11;
- flt_val =
- (dflt_rc_cal_val << 10) | (dflt_rc_cal_val << 5) |
- (dflt_rc_cal_val);
- write_phy_reg(pi, 0x933, flt_val);
- write_phy_reg(pi, 0x934, flt_val);
- write_phy_reg(pi, 0x935, flt_val);
- write_phy_reg(pi, 0x936, flt_val);
- write_phy_reg(pi, 0x937, (flt_val & 0x1FF));
-
- return;
-}
-
-static bool wlc_phy_txpwr_srom_read_lcnphy(phy_info_t *pi)
-{
- s8 txpwr = 0;
- int i;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- u16 cckpo = 0;
- u32 offset_ofdm, offset_mcs;
-
- pi_lcn->lcnphy_tr_isolation_mid =
- (u8) PHY_GETINTVAR(pi, "triso2g");
-
- pi_lcn->lcnphy_rx_power_offset =
- (u8) PHY_GETINTVAR(pi, "rxpo2g");
-
- pi->txpa_2g[0] = (s16) PHY_GETINTVAR(pi, "pa0b0");
- pi->txpa_2g[1] = (s16) PHY_GETINTVAR(pi, "pa0b1");
- pi->txpa_2g[2] = (s16) PHY_GETINTVAR(pi, "pa0b2");
-
- pi_lcn->lcnphy_rssi_vf = (u8) PHY_GETINTVAR(pi, "rssismf2g");
- pi_lcn->lcnphy_rssi_vc = (u8) PHY_GETINTVAR(pi, "rssismc2g");
- pi_lcn->lcnphy_rssi_gs = (u8) PHY_GETINTVAR(pi, "rssisav2g");
-
- {
- pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf;
- pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc;
- pi_lcn->lcnphy_rssi_gs_lowtemp = pi_lcn->lcnphy_rssi_gs;
-
- pi_lcn->lcnphy_rssi_vf_hightemp =
- pi_lcn->lcnphy_rssi_vf;
- pi_lcn->lcnphy_rssi_vc_hightemp =
- pi_lcn->lcnphy_rssi_vc;
- pi_lcn->lcnphy_rssi_gs_hightemp =
- pi_lcn->lcnphy_rssi_gs;
- }
-
- txpwr = (s8) PHY_GETINTVAR(pi, "maxp2ga0");
- pi->tx_srom_max_2g = txpwr;
-
- for (i = 0; i < PWRTBL_NUM_COEFF; i++) {
- pi->txpa_2g_low_temp[i] = pi->txpa_2g[i];
- pi->txpa_2g_high_temp[i] = pi->txpa_2g[i];
- }
-
- cckpo = (u16) PHY_GETINTVAR(pi, "cck2gpo");
- if (cckpo) {
- uint max_pwr_chan = txpwr;
-
- for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++) {
- pi->tx_srom_max_rate_2g[i] = max_pwr_chan -
- ((cckpo & 0xf) * 2);
- cckpo >>= 4;
- }
-
- offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
- for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
- pi->tx_srom_max_rate_2g[i] = max_pwr_chan -
- ((offset_ofdm & 0xf) * 2);
- offset_ofdm >>= 4;
- }
- } else {
- u8 opo = 0;
-
- opo = (u8) PHY_GETINTVAR(pi, "opo");
-
- for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++) {
- pi->tx_srom_max_rate_2g[i] = txpwr;
- }
-
- offset_ofdm = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
-
- for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++) {
- pi->tx_srom_max_rate_2g[i] = txpwr -
- ((offset_ofdm & 0xf) * 2);
- offset_ofdm >>= 4;
- }
- offset_mcs =
- ((u16) PHY_GETINTVAR(pi, "mcs2gpo1") << 16) |
- (u16) PHY_GETINTVAR(pi, "mcs2gpo0");
- pi_lcn->lcnphy_mcs20_po = offset_mcs;
- for (i = TXP_FIRST_SISO_MCS_20;
- i <= TXP_LAST_SISO_MCS_20; i++) {
- pi->tx_srom_max_rate_2g[i] =
- txpwr - ((offset_mcs & 0xf) * 2);
- offset_mcs >>= 4;
- }
- }
-
- pi_lcn->lcnphy_rawtempsense =
- (u16) PHY_GETINTVAR(pi, "rawtempsense");
- pi_lcn->lcnphy_measPower =
- (u8) PHY_GETINTVAR(pi, "measpower");
- pi_lcn->lcnphy_tempsense_slope =
- (u8) PHY_GETINTVAR(pi, "tempsense_slope");
- pi_lcn->lcnphy_hw_iqcal_en =
- (bool) PHY_GETINTVAR(pi, "hw_iqcal_en");
- pi_lcn->lcnphy_iqcal_swp_dis =
- (bool) PHY_GETINTVAR(pi, "iqcal_swp_dis");
- pi_lcn->lcnphy_tempcorrx =
- (u8) PHY_GETINTVAR(pi, "tempcorrx");
- pi_lcn->lcnphy_tempsense_option =
- (u8) PHY_GETINTVAR(pi, "tempsense_option");
- pi_lcn->lcnphy_freqoffset_corr =
- (u8) PHY_GETINTVAR(pi, "freqoffset_corr");
- if ((u8) getintvar(pi->vars, "aa2g") > 1)
- wlc_phy_ant_rxdiv_set((wlc_phy_t *) pi,
- (u8) getintvar(pi->vars,
- "aa2g"));
- }
- pi_lcn->lcnphy_cck_dig_filt_type = -1;
- if (PHY_GETVAR(pi, "cckdigfilttype")) {
- s16 temp;
- temp = (s16) PHY_GETINTVAR(pi, "cckdigfilttype");
- if (temp >= 0) {
- pi_lcn->lcnphy_cck_dig_filt_type = temp;
- }
- }
-
- return true;
-}
-
-void wlc_2064_vco_cal(phy_info_t *pi)
-{
- u8 calnrst;
-
- mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 1 << 3);
- calnrst = (u8) read_radio_reg(pi, RADIO_2064_REG056) & 0xf8;
- write_radio_reg(pi, RADIO_2064_REG056, calnrst);
- udelay(1);
- write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x03);
- udelay(1);
- write_radio_reg(pi, RADIO_2064_REG056, calnrst | 0x07);
- udelay(300);
- mod_radio_reg(pi, RADIO_2064_REG057, 1 << 3, 0);
-}
-
-static void
-wlc_lcnphy_radio_2064_channel_tune_4313(phy_info_t *pi, u8 channel)
-{
- uint i;
- const chan_info_2064_lcnphy_t *ci;
- u8 rfpll_doubler = 0;
- u8 pll_pwrup, pll_pwrup_ovr;
- fixed qFxtal, qFref, qFvco, qFcal;
- u8 d15, d16, f16, e44, e45;
- u32 div_int, div_frac, fvco3, fpfd, fref3, fcal_div;
- u16 loop_bw, d30, setCount;
- if (NORADIO_ENAB(pi->pubpi))
- return;
- ci = &chan_info_2064_lcnphy[0];
- rfpll_doubler = 1;
-
- mod_radio_reg(pi, RADIO_2064_REG09D, 0x4, 0x1 << 2);
-
- write_radio_reg(pi, RADIO_2064_REG09E, 0xf);
- if (!rfpll_doubler) {
- loop_bw = PLL_2064_LOOP_BW;
- d30 = PLL_2064_D30;
- } else {
- loop_bw = PLL_2064_LOOP_BW_DOUBLER;
- d30 = PLL_2064_D30_DOUBLER;
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- for (i = 0; i < ARRAY_SIZE(chan_info_2064_lcnphy); i++)
- if (chan_info_2064_lcnphy[i].chan == channel)
- break;
-
- if (i >= ARRAY_SIZE(chan_info_2064_lcnphy)) {
- return;
- }
-
- ci = &chan_info_2064_lcnphy[i];
- }
-
- write_radio_reg(pi, RADIO_2064_REG02A, ci->logen_buftune);
-
- mod_radio_reg(pi, RADIO_2064_REG030, 0x3, ci->logen_rccr_tx);
-
- mod_radio_reg(pi, RADIO_2064_REG091, 0x3, ci->txrf_mix_tune_ctrl);
-
- mod_radio_reg(pi, RADIO_2064_REG038, 0xf, ci->pa_input_tune_g);
-
- mod_radio_reg(pi, RADIO_2064_REG030, 0x3 << 2,
- (ci->logen_rccr_rx) << 2);
-
- mod_radio_reg(pi, RADIO_2064_REG05E, 0xf, ci->pa_rxrf_lna1_freq_tune);
-
- mod_radio_reg(pi, RADIO_2064_REG05E, (0xf) << 4,
- (ci->pa_rxrf_lna2_freq_tune) << 4);
-
- write_radio_reg(pi, RADIO_2064_REG06C, ci->rxrf_rxrf_spare1);
-
- pll_pwrup = (u8) read_radio_reg(pi, RADIO_2064_REG044);
- pll_pwrup_ovr = (u8) read_radio_reg(pi, RADIO_2064_REG12B);
-
- or_radio_reg(pi, RADIO_2064_REG044, 0x07);
-
- or_radio_reg(pi, RADIO_2064_REG12B, (0x07) << 1);
- e44 = 0;
- e45 = 0;
-
- fpfd = rfpll_doubler ? (pi->xtalfreq << 1) : (pi->xtalfreq);
- if (pi->xtalfreq > 26000000)
- e44 = 1;
- if (pi->xtalfreq > 52000000)
- e45 = 1;
- if (e44 == 0)
- fcal_div = 1;
- else if (e45 == 0)
- fcal_div = 2;
- else
- fcal_div = 4;
- fvco3 = (ci->freq * 3);
- fref3 = 2 * fpfd;
-
- qFxtal = wlc_lcnphy_qdiv_roundup(pi->xtalfreq, PLL_2064_MHZ, 16);
- qFref = wlc_lcnphy_qdiv_roundup(fpfd, PLL_2064_MHZ, 16);
- qFcal = pi->xtalfreq * fcal_div / PLL_2064_MHZ;
- qFvco = wlc_lcnphy_qdiv_roundup(fvco3, 2, 16);
-
- write_radio_reg(pi, RADIO_2064_REG04F, 0x02);
-
- d15 = (pi->xtalfreq * fcal_div * 4 / 5) / PLL_2064_MHZ - 1;
- write_radio_reg(pi, RADIO_2064_REG052, (0x07 & (d15 >> 2)));
- write_radio_reg(pi, RADIO_2064_REG053, (d15 & 0x3) << 5);
-
- d16 = (qFcal * 8 / (d15 + 1)) - 1;
- write_radio_reg(pi, RADIO_2064_REG051, d16);
-
- f16 = ((d16 + 1) * (d15 + 1)) / qFcal;
- setCount = f16 * 3 * (ci->freq) / 32 - 1;
- mod_radio_reg(pi, RADIO_2064_REG053, (0x0f << 0),
- (u8) (setCount >> 8));
-
- or_radio_reg(pi, RADIO_2064_REG053, 0x10);
- write_radio_reg(pi, RADIO_2064_REG054, (u8) (setCount & 0xff));
-
- div_int = ((fvco3 * (PLL_2064_MHZ >> 4)) / fref3) << 4;
-
- div_frac = ((fvco3 * (PLL_2064_MHZ >> 4)) % fref3) << 4;
- while (div_frac >= fref3) {
- div_int++;
- div_frac -= fref3;
- }
- div_frac = wlc_lcnphy_qdiv_roundup(div_frac, fref3, 20);
-
- mod_radio_reg(pi, RADIO_2064_REG045, (0x1f << 0),
- (u8) (div_int >> 4));
- mod_radio_reg(pi, RADIO_2064_REG046, (0x1f << 4),
- (u8) (div_int << 4));
- mod_radio_reg(pi, RADIO_2064_REG046, (0x0f << 0),
- (u8) (div_frac >> 16));
- write_radio_reg(pi, RADIO_2064_REG047, (u8) (div_frac >> 8) & 0xff);
- write_radio_reg(pi, RADIO_2064_REG048, (u8) div_frac & 0xff);
-
- write_radio_reg(pi, RADIO_2064_REG040, 0xfb);
-
- write_radio_reg(pi, RADIO_2064_REG041, 0x9A);
- write_radio_reg(pi, RADIO_2064_REG042, 0xA3);
- write_radio_reg(pi, RADIO_2064_REG043, 0x0C);
-
- {
- u8 h29, h23, c28, d29, h28_ten, e30, h30_ten, cp_current;
- u16 c29, c38, c30, g30, d28;
- c29 = loop_bw;
- d29 = 200;
- c38 = 1250;
- h29 = d29 / c29;
- h23 = 1;
- c28 = 30;
- d28 = (((PLL_2064_HIGH_END_KVCO - PLL_2064_LOW_END_KVCO) *
- (fvco3 / 2 - PLL_2064_LOW_END_VCO)) /
- (PLL_2064_HIGH_END_VCO - PLL_2064_LOW_END_VCO))
- + PLL_2064_LOW_END_KVCO;
- h28_ten = (d28 * 10) / c28;
- c30 = 2640;
- e30 = (d30 - 680) / 490;
- g30 = 680 + (e30 * 490);
- h30_ten = (g30 * 10) / c30;
- cp_current = ((c38 * h29 * h23 * 100) / h28_ten) / h30_ten;
- mod_radio_reg(pi, RADIO_2064_REG03C, 0x3f, cp_current);
- }
- if (channel >= 1 && channel <= 5)
- write_radio_reg(pi, RADIO_2064_REG03C, 0x8);
- else
- write_radio_reg(pi, RADIO_2064_REG03C, 0x7);
- write_radio_reg(pi, RADIO_2064_REG03D, 0x3);
-
- mod_radio_reg(pi, RADIO_2064_REG044, 0x0c, 0x0c);
- udelay(1);
-
- wlc_2064_vco_cal(pi);
-
- write_radio_reg(pi, RADIO_2064_REG044, pll_pwrup);
- write_radio_reg(pi, RADIO_2064_REG12B, pll_pwrup_ovr);
- if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
- write_radio_reg(pi, RADIO_2064_REG038, 3);
- write_radio_reg(pi, RADIO_2064_REG091, 7);
- }
-}
-
-bool wlc_phy_tpc_isenabled_lcnphy(phy_info_t *pi)
-{
- if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
- return 0;
- else
- return (LCNPHY_TX_PWR_CTRL_HW ==
- wlc_lcnphy_get_tx_pwr_ctrl((pi)));
-}
-
-void wlc_phy_txpower_recalc_target_lcnphy(phy_info_t *pi)
-{
- u16 pwr_ctrl;
- if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi)) {
- wlc_lcnphy_calib_modes(pi, LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
- } else if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi)) {
-
- pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
- wlc_lcnphy_txpower_recalc_target(pi);
-
- wlc_lcnphy_set_tx_pwr_ctrl(pi, pwr_ctrl);
- } else
- return;
-}
-
-void wlc_phy_detach_lcnphy(phy_info_t *pi)
-{
- kfree(pi->u.pi_lcnphy);
-}
-
-bool wlc_phy_attach_lcnphy(phy_info_t *pi)
-{
- phy_info_lcnphy_t *pi_lcn;
-
- pi->u.pi_lcnphy = kzalloc(sizeof(phy_info_lcnphy_t), GFP_ATOMIC);
- if (pi->u.pi_lcnphy == NULL) {
- return false;
- }
-
- pi_lcn = pi->u.pi_lcnphy;
-
- if ((0 == (pi->sh->boardflags & BFL_NOPA)) && !NORADIO_ENAB(pi->pubpi)) {
- pi->hwpwrctrl = true;
- pi->hwpwrctrl_capable = true;
- }
-
- pi->xtalfreq = si_pmu_alp_clock(pi->sh->sih);
- pi_lcn->lcnphy_papd_rxGnCtrl_init = 0;
-
- pi->pi_fptr.init = wlc_phy_init_lcnphy;
- pi->pi_fptr.calinit = wlc_phy_cal_init_lcnphy;
- pi->pi_fptr.chanset = wlc_phy_chanspec_set_lcnphy;
- pi->pi_fptr.txpwrrecalc = wlc_phy_txpower_recalc_target_lcnphy;
- pi->pi_fptr.txiqccget = wlc_lcnphy_get_tx_iqcc;
- pi->pi_fptr.txiqccset = wlc_lcnphy_set_tx_iqcc;
- pi->pi_fptr.txloccget = wlc_lcnphy_get_tx_locc;
- pi->pi_fptr.radioloftget = wlc_lcnphy_get_radio_loft;
- pi->pi_fptr.detach = wlc_phy_detach_lcnphy;
-
- if (!wlc_phy_txpwr_srom_read_lcnphy(pi))
- return false;
-
- if ((pi->sh->boardflags & BFL_FEM) && (LCNREV_IS(pi->pubpi.phy_rev, 1))) {
- if (pi_lcn->lcnphy_tempsense_option == 3) {
- pi->hwpwrctrl = true;
- pi->hwpwrctrl_capable = true;
- pi->temppwrctrl_capable = false;
- } else {
- pi->hwpwrctrl = false;
- pi->hwpwrctrl_capable = false;
- pi->temppwrctrl_capable = true;
- }
- }
-
- return true;
-}
-
-static void wlc_lcnphy_set_rx_gain(phy_info_t *pi, u32 gain)
-{
- u16 trsw, ext_lna, lna1, lna2, tia, biq0, biq1, gain0_15, gain16_19;
-
- trsw = (gain & ((u32) 1 << 28)) ? 0 : 1;
- ext_lna = (u16) (gain >> 29) & 0x01;
- lna1 = (u16) (gain >> 0) & 0x0f;
- lna2 = (u16) (gain >> 4) & 0x0f;
- tia = (u16) (gain >> 8) & 0xf;
- biq0 = (u16) (gain >> 12) & 0xf;
- biq1 = (u16) (gain >> 16) & 0xf;
-
- gain0_15 = (u16) ((lna1 & 0x3) | ((lna1 & 0x3) << 2) |
- ((lna2 & 0x3) << 4) | ((lna2 & 0x3) << 6) |
- ((tia & 0xf) << 8) | ((biq0 & 0xf) << 12));
- gain16_19 = biq1;
-
- mod_phy_reg(pi, 0x44d, (0x1 << 0), trsw << 0);
- mod_phy_reg(pi, 0x4b1, (0x1 << 9), ext_lna << 9);
- mod_phy_reg(pi, 0x4b1, (0x1 << 10), ext_lna << 10);
- mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
- mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- mod_phy_reg(pi, 0x4b1, (0x3 << 11), lna1 << 11);
- mod_phy_reg(pi, 0x4e6, (0x3 << 3), lna1 << 3);
- }
- wlc_lcnphy_rx_gain_override_enable(pi, true);
-}
-
-static u32 wlc_lcnphy_get_receive_power(phy_info_t *pi, s32 *gain_index)
-{
- u32 received_power = 0;
- s32 max_index = 0;
- u32 gain_code = 0;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- max_index = 36;
- if (*gain_index >= 0)
- gain_code = lcnphy_23bitgaincode_table[*gain_index];
-
- if (-1 == *gain_index) {
- *gain_index = 0;
- while ((*gain_index <= (s32) max_index)
- && (received_power < 700)) {
- wlc_lcnphy_set_rx_gain(pi,
- lcnphy_23bitgaincode_table
- [*gain_index]);
- received_power =
- wlc_lcnphy_measure_digital_power(pi,
- pi_lcn->
- lcnphy_noise_samples);
- (*gain_index)++;
- }
- (*gain_index)--;
- } else {
- wlc_lcnphy_set_rx_gain(pi, gain_code);
- received_power =
- wlc_lcnphy_measure_digital_power(pi,
- pi_lcn->
- lcnphy_noise_samples);
- }
-
- return received_power;
-}
-
-s32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, s32 gain_index)
-{
- s32 gain = 0;
- s32 nominal_power_db;
- s32 log_val, gain_mismatch, desired_gain, input_power_offset_db,
- input_power_db;
- s32 received_power, temperature;
- uint freq;
- phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
-
- received_power = wlc_lcnphy_get_receive_power(pi, &gain_index);
-
- gain = lcnphy_gain_table[gain_index];
-
- nominal_power_db = read_phy_reg(pi, 0x425) >> 8;
-
- {
- u32 power = (received_power * 16);
- u32 msb1, msb2, val1, val2, diff1, diff2;
- msb1 = ffs(power) - 1;
- msb2 = msb1 + 1;
- val1 = 1 << msb1;
- val2 = 1 << msb2;
- diff1 = (power - val1);
- diff2 = (val2 - power);
- if (diff1 < diff2)
- log_val = msb1;
- else
- log_val = msb2;
- }
-
- log_val = log_val * 3;
-
- gain_mismatch = (nominal_power_db / 2) - (log_val);
-
- desired_gain = gain + gain_mismatch;
-
- input_power_offset_db = read_phy_reg(pi, 0x434) & 0xFF;
-
- if (input_power_offset_db > 127)
- input_power_offset_db -= 256;
-
- input_power_db = input_power_offset_db - desired_gain;
-
- input_power_db =
- input_power_db + lcnphy_gain_index_offset_for_rssi[gain_index];
-
- freq = wlc_phy_channel2freq(CHSPEC_CHANNEL(pi->radio_chanspec));
- if ((freq > 2427) && (freq <= 2467))
- input_power_db = input_power_db - 1;
-
- temperature = pi_lcn->lcnphy_lastsensed_temperature;
-
- if ((temperature - 15) < -30) {
- input_power_db =
- input_power_db + (((temperature - 10 - 25) * 286) >> 12) -
- 7;
- } else if ((temperature - 15) < 4) {
- input_power_db =
- input_power_db + (((temperature - 10 - 25) * 286) >> 12) -
- 3;
- } else {
- input_power_db =
- input_power_db + (((temperature - 10 - 25) * 286) >> 12);
- }
-
- wlc_lcnphy_rx_gain_override_enable(pi, 0);
-
- return input_power_db;
-}
-
-static int
-wlc_lcnphy_load_tx_iir_filter(phy_info_t *pi, bool is_ofdm, s16 filt_type)
-{
- s16 filt_index = -1;
- int j;
-
- u16 addr[] = {
- 0x910,
- 0x91e,
- 0x91f,
- 0x924,
- 0x925,
- 0x926,
- 0x920,
- 0x921,
- 0x927,
- 0x928,
- 0x929,
- 0x922,
- 0x923,
- 0x930,
- 0x931,
- 0x932
- };
-
- u16 addr_ofdm[] = {
- 0x90f,
- 0x900,
- 0x901,
- 0x906,
- 0x907,
- 0x908,
- 0x902,
- 0x903,
- 0x909,
- 0x90a,
- 0x90b,
- 0x904,
- 0x905,
- 0x90c,
- 0x90d,
- 0x90e
- };
-
- if (!is_ofdm) {
- for (j = 0; j < LCNPHY_NUM_TX_DIG_FILTERS_CCK; j++) {
- if (filt_type == LCNPHY_txdigfiltcoeffs_cck[j][0]) {
- filt_index = (s16) j;
- break;
- }
- }
-
- if (filt_index != -1) {
- for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, addr[j],
- LCNPHY_txdigfiltcoeffs_cck
- [filt_index][j + 1]);
- }
- }
- } else {
- for (j = 0; j < LCNPHY_NUM_TX_DIG_FILTERS_OFDM; j++) {
- if (filt_type == LCNPHY_txdigfiltcoeffs_ofdm[j][0]) {
- filt_index = (s16) j;
- break;
- }
- }
-
- if (filt_index != -1) {
- for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, addr_ofdm[j],
- LCNPHY_txdigfiltcoeffs_ofdm
- [filt_index][j + 1]);
- }
- }
- }
-
- return (filt_index != -1) ? 0 : -1;
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_PHY_LCN_H_
-#define _BRCM_PHY_LCN_H_
-
-struct phy_info_lcnphy {
- int lcnphy_txrf_sp_9_override;
- u8 lcnphy_full_cal_channel;
- u8 lcnphy_cal_counter;
- u16 lcnphy_cal_temper;
- bool lcnphy_recal;
-
- u8 lcnphy_rc_cap;
- u32 lcnphy_mcs20_po;
-
- u8 lcnphy_tr_isolation_mid;
- u8 lcnphy_tr_isolation_low;
- u8 lcnphy_tr_isolation_hi;
-
- u8 lcnphy_bx_arch;
- u8 lcnphy_rx_power_offset;
- u8 lcnphy_rssi_vf;
- u8 lcnphy_rssi_vc;
- u8 lcnphy_rssi_gs;
- u8 lcnphy_tssi_val;
- u8 lcnphy_rssi_vf_lowtemp;
- u8 lcnphy_rssi_vc_lowtemp;
- u8 lcnphy_rssi_gs_lowtemp;
-
- u8 lcnphy_rssi_vf_hightemp;
- u8 lcnphy_rssi_vc_hightemp;
- u8 lcnphy_rssi_gs_hightemp;
-
- s16 lcnphy_pa0b0;
- s16 lcnphy_pa0b1;
- s16 lcnphy_pa0b2;
-
- u16 lcnphy_rawtempsense;
- u8 lcnphy_measPower;
- u8 lcnphy_tempsense_slope;
- u8 lcnphy_freqoffset_corr;
- u8 lcnphy_tempsense_option;
- u8 lcnphy_tempcorrx;
- bool lcnphy_iqcal_swp_dis;
- bool lcnphy_hw_iqcal_en;
- uint lcnphy_bandedge_corr;
- bool lcnphy_spurmod;
- u16 lcnphy_tssi_tx_cnt;
- u16 lcnphy_tssi_idx;
- u16 lcnphy_tssi_npt;
-
- u16 lcnphy_target_tx_freq;
- s8 lcnphy_tx_power_idx_override;
- u16 lcnphy_noise_samples;
-
- u32 lcnphy_papdRxGnIdx;
- u32 lcnphy_papd_rxGnCtrl_init;
-
- u32 lcnphy_gain_idx_14_lowword;
- u32 lcnphy_gain_idx_14_hiword;
- u32 lcnphy_gain_idx_27_lowword;
- u32 lcnphy_gain_idx_27_hiword;
- s16 lcnphy_ofdmgainidxtableoffset;
- s16 lcnphy_dsssgainidxtableoffset;
- u32 lcnphy_tr_R_gain_val;
- u32 lcnphy_tr_T_gain_val;
- s8 lcnphy_input_pwr_offset_db;
- u16 lcnphy_Med_Low_Gain_db;
- u16 lcnphy_Very_Low_Gain_db;
- s8 lcnphy_lastsensed_temperature;
- s8 lcnphy_pkteng_rssi_slope;
- u8 lcnphy_saved_tx_user_target[TXP_NUM_RATES];
- u8 lcnphy_volt_winner;
- u8 lcnphy_volt_low;
- u8 lcnphy_54_48_36_24mbps_backoff;
- u8 lcnphy_11n_backoff;
- u8 lcnphy_lowerofdm;
- u8 lcnphy_cck;
- u8 lcnphy_psat_2pt3_detected;
- s32 lcnphy_lowest_Re_div_Im;
- s8 lcnphy_final_papd_cal_idx;
- u16 lcnphy_extstxctrl4;
- u16 lcnphy_extstxctrl0;
- u16 lcnphy_extstxctrl1;
- s16 lcnphy_cck_dig_filt_type;
- s16 lcnphy_ofdm_dig_filt_type;
- lcnphy_cal_results_t lcnphy_cal_results;
-
- u8 lcnphy_psat_pwr;
- u8 lcnphy_psat_indx;
- s32 lcnphy_min_phase;
- u8 lcnphy_final_idx;
- u8 lcnphy_start_idx;
- u8 lcnphy_current_index;
- u16 lcnphy_logen_buf_1;
- u16 lcnphy_local_ovr_2;
- u16 lcnphy_local_oval_6;
- u16 lcnphy_local_oval_5;
- u16 lcnphy_logen_mixer_1;
-
- u8 lcnphy_aci_stat;
- uint lcnphy_aci_start_time;
- s8 lcnphy_tx_power_offset[TXP_NUM_RATES];
-};
-#endif /* _BRCM_PHY_LCN_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <bcmdefs.h>
-#include <wlc_cfg.h>
-#include <linux/delay.h>
-#include <linux/pci.h>
-#include <aiutils.h>
-#include <chipcommon.h>
-#include <wlc_pmu.h>
-
-#include <bcmdevs.h>
-#include "bcmdma.h"
-
-#include <wlc_types.h>
-#include <wlc_phy_radio.h>
-#include <wlc_phy_int.h>
-#include <wlc_phyreg_n.h>
-#include <wlc_phytbl_n.h>
-
-#define READ_RADIO_REG2(pi, radio_type, jspace, core, reg_name) \
- read_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
- ((core == PHY_CORE_0) ? radio_type##_##jspace##0 : radio_type##_##jspace##1))
-#define WRITE_RADIO_REG2(pi, radio_type, jspace, core, reg_name, value) \
- write_radio_reg(pi, radio_type##_##jspace##_##reg_name | \
- ((core == PHY_CORE_0) ? radio_type##_##jspace##0 : radio_type##_##jspace##1), value);
-#define WRITE_RADIO_SYN(pi, radio_type, reg_name, value) \
- write_radio_reg(pi, radio_type##_##SYN##_##reg_name, value);
-
-#define READ_RADIO_REG3(pi, radio_type, jspace, core, reg_name) \
- read_radio_reg(pi, ((core == PHY_CORE_0) ? radio_type##_##jspace##0##_##reg_name : \
- radio_type##_##jspace##1##_##reg_name));
-#define WRITE_RADIO_REG3(pi, radio_type, jspace, core, reg_name, value) \
- write_radio_reg(pi, ((core == PHY_CORE_0) ? radio_type##_##jspace##0##_##reg_name : \
- radio_type##_##jspace##1##_##reg_name), value);
-#define READ_RADIO_REG4(pi, radio_type, jspace, core, reg_name) \
- read_radio_reg(pi, ((core == PHY_CORE_0) ? radio_type##_##reg_name##_##jspace##0 : \
- radio_type##_##reg_name##_##jspace##1));
-#define WRITE_RADIO_REG4(pi, radio_type, jspace, core, reg_name, value) \
- write_radio_reg(pi, ((core == PHY_CORE_0) ? radio_type##_##reg_name##_##jspace##0 : \
- radio_type##_##reg_name##_##jspace##1), value);
-
-#define NPHY_ACI_MAX_UNDETECT_WINDOW_SZ 40
-#define NPHY_ACI_CHANNEL_DELTA 5
-#define NPHY_ACI_CHANNEL_SKIP 4
-#define NPHY_ACI_40MHZ_CHANNEL_DELTA 6
-#define NPHY_ACI_40MHZ_CHANNEL_SKIP 5
-#define NPHY_ACI_40MHZ_CHANNEL_DELTA_GE_REV3 6
-#define NPHY_ACI_40MHZ_CHANNEL_SKIP_GE_REV3 5
-#define NPHY_ACI_CHANNEL_DELTA_GE_REV3 4
-#define NPHY_ACI_CHANNEL_SKIP_GE_REV3 3
-
-#define NPHY_NOISE_NOASSOC_GLITCH_TH_UP 2
-
-#define NPHY_NOISE_NOASSOC_GLITCH_TH_DN 8
-
-#define NPHY_NOISE_ASSOC_GLITCH_TH_UP 2
-
-#define NPHY_NOISE_ASSOC_GLITCH_TH_DN 8
-
-#define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_UP 2
-
-#define NPHY_NOISE_ASSOC_ACI_GLITCH_TH_DN 8
-
-#define NPHY_NOISE_NOASSOC_ENTER_TH 400
-
-#define NPHY_NOISE_ASSOC_ENTER_TH 400
-
-#define NPHY_NOISE_ASSOC_RX_GLITCH_BADPLCP_ENTER_TH 400
-
-#define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX 44
-#define NPHY_NOISE_CRSMINPWR_ARRAY_MAX_INDEX_REV_7 56
-
-#define NPHY_NOISE_NOASSOC_CRSIDX_INCR 16
-
-#define NPHY_NOISE_ASSOC_CRSIDX_INCR 8
-
-#define NPHY_IS_SROM_REINTERPRET NREV_GE(pi->pubpi.phy_rev, 5)
-
-#define NPHY_RSSICAL_MAXREAD 31
-
-#define NPHY_RSSICAL_NPOLL 8
-#define NPHY_RSSICAL_MAXD (1<<20)
-#define NPHY_MIN_RXIQ_PWR 2
-
-#define NPHY_RSSICAL_W1_TARGET 25
-#define NPHY_RSSICAL_W2_TARGET NPHY_RSSICAL_W1_TARGET
-#define NPHY_RSSICAL_NB_TARGET 0
-
-#define NPHY_RSSICAL_W1_TARGET_REV3 29
-#define NPHY_RSSICAL_W2_TARGET_REV3 NPHY_RSSICAL_W1_TARGET_REV3
-
-#define NPHY_CALSANITY_RSSI_NB_MAX_POS 9
-#define NPHY_CALSANITY_RSSI_NB_MAX_NEG -9
-#define NPHY_CALSANITY_RSSI_W1_MAX_POS 12
-#define NPHY_CALSANITY_RSSI_W1_MAX_NEG (NPHY_RSSICAL_W1_TARGET - NPHY_RSSICAL_MAXREAD)
-#define NPHY_CALSANITY_RSSI_W2_MAX_POS NPHY_CALSANITY_RSSI_W1_MAX_POS
-#define NPHY_CALSANITY_RSSI_W2_MAX_NEG (NPHY_RSSICAL_W2_TARGET - NPHY_RSSICAL_MAXREAD)
-#define NPHY_RSSI_SXT(x) ((s8) (-((x) & 0x20) + ((x) & 0x1f)))
-#define NPHY_RSSI_NB_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_NB_MAX_POS) || \
- ((x) < NPHY_CALSANITY_RSSI_NB_MAX_NEG))
-#define NPHY_RSSI_W1_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W1_MAX_POS) || \
- ((x) < NPHY_CALSANITY_RSSI_W1_MAX_NEG))
-#define NPHY_RSSI_W2_VIOL(x) (((x) > NPHY_CALSANITY_RSSI_W2_MAX_POS) || \
- ((x) < NPHY_CALSANITY_RSSI_W2_MAX_NEG))
-
-#define NPHY_IQCAL_NUMGAINS 9
-#define NPHY_N_GCTL 0x66
-
-#define NPHY_PAPD_EPS_TBL_SIZE 64
-#define NPHY_PAPD_SCL_TBL_SIZE 64
-#define NPHY_NUM_DIG_FILT_COEFFS 15
-
-#define NPHY_PAPD_COMP_OFF 0
-#define NPHY_PAPD_COMP_ON 1
-
-#define NPHY_SROM_TEMPSHIFT 32
-#define NPHY_SROM_MAXTEMPOFFSET 16
-#define NPHY_SROM_MINTEMPOFFSET -16
-
-#define NPHY_CAL_MAXTEMPDELTA 64
-
-#define NPHY_NOISEVAR_TBLLEN40 256
-#define NPHY_NOISEVAR_TBLLEN20 128
-
-#define NPHY_ANARXLPFBW_REDUCTIONFACT 7
-
-#define NPHY_ADJUSTED_MINCRSPOWER 0x1e
-
-/* 5357 Chip specific ChipControl register bits */
-#define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */
-#define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */
-
-typedef struct _nphy_iqcal_params {
- u16 txlpf;
- u16 txgm;
- u16 pga;
- u16 pad;
- u16 ipa;
- u16 cal_gain;
- u16 ncorr[5];
-} nphy_iqcal_params_t;
-
-typedef struct _nphy_txiqcal_ladder {
- u8 percent;
- u8 g_env;
-} nphy_txiqcal_ladder_t;
-
-typedef struct {
- nphy_txgains_t gains;
- bool useindex;
- u8 index;
-} nphy_ipa_txcalgains_t;
-
-typedef struct nphy_papd_restore_state_t {
- u16 fbmix[2];
- u16 vga_master[2];
- u16 intpa_master[2];
- u16 afectrl[2];
- u16 afeoverride[2];
- u16 pwrup[2];
- u16 atten[2];
- u16 mm;
-} nphy_papd_restore_state;
-
-typedef struct _nphy_ipa_txrxgain {
- u16 hpvga;
- u16 lpf_biq1;
- u16 lpf_biq0;
- u16 lna2;
- u16 lna1;
- s8 txpwrindex;
-} nphy_ipa_txrxgain_t;
-
-#define NPHY_IPA_RXCAL_MAXGAININDEX (6 - 1)
-
-nphy_ipa_txrxgain_t nphy_ipa_rxcal_gaintbl_5GHz[] = { {0, 0, 0, 0, 0, 100},
-{0, 0, 0, 0, 0, 50},
-{0, 0, 0, 0, 0, -1},
-{0, 0, 0, 3, 0, -1},
-{0, 0, 3, 3, 0, -1},
-{0, 2, 3, 3, 0, -1}
-};
-
-nphy_ipa_txrxgain_t nphy_ipa_rxcal_gaintbl_2GHz[] = { {0, 0, 0, 0, 0, 128},
-{0, 0, 0, 0, 0, 70},
-{0, 0, 0, 0, 0, 20},
-{0, 0, 0, 3, 0, 20},
-{0, 0, 3, 3, 0, 20},
-{0, 2, 3, 3, 0, 20}
-};
-
-nphy_ipa_txrxgain_t nphy_ipa_rxcal_gaintbl_5GHz_rev7[] = { {0, 0, 0, 0, 0, 100},
-{0, 0, 0, 0, 0, 50},
-{0, 0, 0, 0, 0, -1},
-{0, 0, 0, 3, 0, -1},
-{0, 0, 3, 3, 0, -1},
-{0, 0, 5, 3, 0, -1}
-};
-
-nphy_ipa_txrxgain_t nphy_ipa_rxcal_gaintbl_2GHz_rev7[] = { {0, 0, 0, 0, 0, 10},
-{0, 0, 0, 1, 0, 10},
-{0, 0, 1, 2, 0, 10},
-{0, 0, 1, 3, 0, 10},
-{0, 0, 4, 3, 0, 10},
-{0, 0, 6, 3, 0, 10}
-};
-
-#define NPHY_RXCAL_TONEAMP 181
-#define NPHY_RXCAL_TONEFREQ_40MHz 4000
-#define NPHY_RXCAL_TONEFREQ_20MHz 2000
-
-enum {
- NPHY_RXCAL_GAIN_INIT = 0,
- NPHY_RXCAL_GAIN_UP,
- NPHY_RXCAL_GAIN_DOWN
-};
-
-#define wlc_phy_get_papd_nphy(pi) \
- (read_phy_reg((pi), 0x1e7) & \
- ((0x1 << 15) | \
- (0x1 << 14) | \
- (0x1 << 13)))
-
-#define TXFILT_SHAPING_OFDM20 0
-#define TXFILT_SHAPING_OFDM40 1
-#define TXFILT_SHAPING_CCK 2
-#define TXFILT_DEFAULT_OFDM20 3
-#define TXFILT_DEFAULT_OFDM40 4
-
-u16 NPHY_IPA_REV4_txdigi_filtcoeffs[][NPHY_NUM_DIG_FILT_COEFFS] = {
- {-377, 137, -407, 208, -1527, 956, 93, 186, 93,
- 230, -44, 230, 201, -191, 201},
- {-77, 20, -98, 49, -93, 60, 56, 111, 56, 26, -5,
- 26, 34, -32, 34},
- {-360, 164, -376, 164, -1533, 576, 308, -314, 308,
- 121, -73, 121, 91, 124, 91},
- {-295, 200, -363, 142, -1391, 826, 151, 301, 151,
- 151, 301, 151, 602, -752, 602},
- {-92, 58, -96, 49, -104, 44, 17, 35, 17,
- 12, 25, 12, 13, 27, 13},
- {-375, 136, -399, 209, -1479, 949, 130, 260, 130,
- 230, -44, 230, 201, -191, 201},
- {0xed9, 0xc8, 0xe95, 0x8e, 0xa91, 0x33a, 0x97, 0x12d, 0x97,
- 0x97, 0x12d, 0x97, 0x25a, 0xd10, 0x25a}
-};
-
-typedef struct _chan_info_nphy_2055 {
- u16 chan;
- u16 freq;
- uint unknown;
- u8 RF_pll_ref;
- u8 RF_rf_pll_mod1;
- u8 RF_rf_pll_mod0;
- u8 RF_vco_cap_tail;
- u8 RF_vco_cal1;
- u8 RF_vco_cal2;
- u8 RF_pll_lf_c1;
- u8 RF_pll_lf_r1;
- u8 RF_pll_lf_c2;
- u8 RF_lgbuf_cen_buf;
- u8 RF_lgen_tune1;
- u8 RF_lgen_tune2;
- u8 RF_core1_lgbuf_a_tune;
- u8 RF_core1_lgbuf_g_tune;
- u8 RF_core1_rxrf_reg1;
- u8 RF_core1_tx_pga_pad_tn;
- u8 RF_core1_tx_mx_bgtrim;
- u8 RF_core2_lgbuf_a_tune;
- u8 RF_core2_lgbuf_g_tune;
- u8 RF_core2_rxrf_reg1;
- u8 RF_core2_tx_pga_pad_tn;
- u8 RF_core2_tx_mx_bgtrim;
- u16 PHY_BW1a;
- u16 PHY_BW2;
- u16 PHY_BW3;
- u16 PHY_BW4;
- u16 PHY_BW5;
- u16 PHY_BW6;
-} chan_info_nphy_2055_t;
-
-typedef struct _chan_info_nphy_radio205x {
- u16 chan;
- u16 freq;
- u8 RF_SYN_pll_vcocal1;
- u8 RF_SYN_pll_vcocal2;
- u8 RF_SYN_pll_refdiv;
- u8 RF_SYN_pll_mmd2;
- u8 RF_SYN_pll_mmd1;
- u8 RF_SYN_pll_loopfilter1;
- u8 RF_SYN_pll_loopfilter2;
- u8 RF_SYN_pll_loopfilter3;
- u8 RF_SYN_pll_loopfilter4;
- u8 RF_SYN_pll_loopfilter5;
- u8 RF_SYN_reserved_addr27;
- u8 RF_SYN_reserved_addr28;
- u8 RF_SYN_reserved_addr29;
- u8 RF_SYN_logen_VCOBUF1;
- u8 RF_SYN_logen_MIXER2;
- u8 RF_SYN_logen_BUF3;
- u8 RF_SYN_logen_BUF4;
- u8 RF_RX0_lnaa_tune;
- u8 RF_RX0_lnag_tune;
- u8 RF_TX0_intpaa_boost_tune;
- u8 RF_TX0_intpag_boost_tune;
- u8 RF_TX0_pada_boost_tune;
- u8 RF_TX0_padg_boost_tune;
- u8 RF_TX0_pgaa_boost_tune;
- u8 RF_TX0_pgag_boost_tune;
- u8 RF_TX0_mixa_boost_tune;
- u8 RF_TX0_mixg_boost_tune;
- u8 RF_RX1_lnaa_tune;
- u8 RF_RX1_lnag_tune;
- u8 RF_TX1_intpaa_boost_tune;
- u8 RF_TX1_intpag_boost_tune;
- u8 RF_TX1_pada_boost_tune;
- u8 RF_TX1_padg_boost_tune;
- u8 RF_TX1_pgaa_boost_tune;
- u8 RF_TX1_pgag_boost_tune;
- u8 RF_TX1_mixa_boost_tune;
- u8 RF_TX1_mixg_boost_tune;
- u16 PHY_BW1a;
- u16 PHY_BW2;
- u16 PHY_BW3;
- u16 PHY_BW4;
- u16 PHY_BW5;
- u16 PHY_BW6;
-} chan_info_nphy_radio205x_t;
-
-typedef struct _chan_info_nphy_radio2057 {
- u16 chan;
- u16 freq;
- u8 RF_vcocal_countval0;
- u8 RF_vcocal_countval1;
- u8 RF_rfpll_refmaster_sparextalsize;
- u8 RF_rfpll_loopfilter_r1;
- u8 RF_rfpll_loopfilter_c2;
- u8 RF_rfpll_loopfilter_c1;
- u8 RF_cp_kpd_idac;
- u8 RF_rfpll_mmd0;
- u8 RF_rfpll_mmd1;
- u8 RF_vcobuf_tune;
- u8 RF_logen_mx2g_tune;
- u8 RF_logen_mx5g_tune;
- u8 RF_logen_indbuf2g_tune;
- u8 RF_logen_indbuf5g_tune;
- u8 RF_txmix2g_tune_boost_pu_core0;
- u8 RF_pad2g_tune_pus_core0;
- u8 RF_pga_boost_tune_core0;
- u8 RF_txmix5g_boost_tune_core0;
- u8 RF_pad5g_tune_misc_pus_core0;
- u8 RF_lna2g_tune_core0;
- u8 RF_lna5g_tune_core0;
- u8 RF_txmix2g_tune_boost_pu_core1;
- u8 RF_pad2g_tune_pus_core1;
- u8 RF_pga_boost_tune_core1;
- u8 RF_txmix5g_boost_tune_core1;
- u8 RF_pad5g_tune_misc_pus_core1;
- u8 RF_lna2g_tune_core1;
- u8 RF_lna5g_tune_core1;
- u16 PHY_BW1a;
- u16 PHY_BW2;
- u16 PHY_BW3;
- u16 PHY_BW4;
- u16 PHY_BW5;
- u16 PHY_BW6;
-} chan_info_nphy_radio2057_t;
-
-typedef struct _chan_info_nphy_radio2057_rev5 {
- u16 chan;
- u16 freq;
- u8 RF_vcocal_countval0;
- u8 RF_vcocal_countval1;
- u8 RF_rfpll_refmaster_sparextalsize;
- u8 RF_rfpll_loopfilter_r1;
- u8 RF_rfpll_loopfilter_c2;
- u8 RF_rfpll_loopfilter_c1;
- u8 RF_cp_kpd_idac;
- u8 RF_rfpll_mmd0;
- u8 RF_rfpll_mmd1;
- u8 RF_vcobuf_tune;
- u8 RF_logen_mx2g_tune;
- u8 RF_logen_indbuf2g_tune;
- u8 RF_txmix2g_tune_boost_pu_core0;
- u8 RF_pad2g_tune_pus_core0;
- u8 RF_lna2g_tune_core0;
- u8 RF_txmix2g_tune_boost_pu_core1;
- u8 RF_pad2g_tune_pus_core1;
- u8 RF_lna2g_tune_core1;
- u16 PHY_BW1a;
- u16 PHY_BW2;
- u16 PHY_BW3;
- u16 PHY_BW4;
- u16 PHY_BW5;
- u16 PHY_BW6;
-} chan_info_nphy_radio2057_rev5_t;
-
-typedef struct nphy_sfo_cfg {
- u16 PHY_BW1a;
- u16 PHY_BW2;
- u16 PHY_BW3;
- u16 PHY_BW4;
- u16 PHY_BW5;
- u16 PHY_BW6;
-} nphy_sfo_cfg_t;
-
-static chan_info_nphy_2055_t chan_info_nphy_2055[] = {
- {
- 184, 4920, 3280, 0x71, 0x01, 0xEC, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7B4, 0x7B0, 0x7AC, 0x214, 0x215, 0x216},
- {
- 186, 4930, 3287, 0x71, 0x01, 0xED, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7B8, 0x7B4, 0x7B0, 0x213, 0x214, 0x215},
- {
- 188, 4940, 3293, 0x71, 0x01, 0xEE, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7BC, 0x7B8, 0x7B4, 0x212, 0x213, 0x214},
- {
- 190, 4950, 3300, 0x71, 0x01, 0xEF, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7C0, 0x7BC, 0x7B8, 0x211, 0x212, 0x213},
- {
- 192, 4960, 3307, 0x71, 0x01, 0xF0, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7C4, 0x7C0, 0x7BC, 0x20F, 0x211, 0x212},
- {
- 194, 4970, 3313, 0x71, 0x01, 0xF1, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7C8, 0x7C4, 0x7C0, 0x20E, 0x20F, 0x211},
- {
- 196, 4980, 3320, 0x71, 0x01, 0xF2, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7CC, 0x7C8, 0x7C4, 0x20D, 0x20E, 0x20F},
- {
- 198, 4990, 3327, 0x71, 0x01, 0xF3, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7D0, 0x7CC, 0x7C8, 0x20C, 0x20D, 0x20E},
- {
- 200, 5000, 3333, 0x71, 0x01, 0xF4, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7D4, 0x7D0, 0x7CC, 0x20B, 0x20C, 0x20D},
- {
- 202, 5010, 3340, 0x71, 0x01, 0xF5, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7D8, 0x7D4, 0x7D0, 0x20A, 0x20B, 0x20C},
- {
- 204, 5020, 3347, 0x71, 0x01, 0xF6, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7DC, 0x7D8, 0x7D4, 0x209, 0x20A, 0x20B},
- {
- 206, 5030, 3353, 0x71, 0x01, 0xF7, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7E0, 0x7DC, 0x7D8, 0x208, 0x209, 0x20A},
- {
- 208, 5040, 3360, 0x71, 0x01, 0xF8, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7E4, 0x7E0, 0x7DC, 0x207, 0x208, 0x209},
- {
- 210, 5050, 3367, 0x71, 0x01, 0xF9, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, 0x8F, 0xFF, 0x00, 0x0F,
- 0x0F, 0x8F, 0x7E8, 0x7E4, 0x7E0, 0x206, 0x207, 0x208},
- {
- 212, 5060, 3373, 0x71, 0x01, 0xFA, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, 0x8E, 0xFF, 0x00, 0x0E,
- 0x0F, 0x8E, 0x7EC, 0x7E8, 0x7E4, 0x205, 0x206, 0x207},
- {
- 214, 5070, 3380, 0x71, 0x01, 0xFB, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
- 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, 0x8E, 0xFF, 0x00, 0x0E,
- 0x0F, 0x8E, 0x7F0, 0x7EC, 0x7E8, 0x204, 0x205, 0x206},
- {
- 216, 5080, 3387, 0x71, 0x01, 0xFC, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
- 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, 0x8D, 0xEE, 0x00, 0x0E,
- 0x0F, 0x8D, 0x7F4, 0x7F0, 0x7EC, 0x203, 0x204, 0x205},
- {
- 218, 5090, 3393, 0x71, 0x01, 0xFD, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
- 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, 0x8D, 0xEE, 0x00, 0x0E,
- 0x0F, 0x8D, 0x7F8, 0x7F4, 0x7F0, 0x202, 0x203, 0x204},
- {
- 220, 5100, 3400, 0x71, 0x01, 0xFE, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
- 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, 0x8D, 0xEE, 0x00, 0x0D,
- 0x0F, 0x8D, 0x7FC, 0x7F8, 0x7F4, 0x201, 0x202, 0x203},
- {
- 222, 5110, 3407, 0x71, 0x01, 0xFF, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
- 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, 0x8D, 0xEE, 0x00, 0x0D,
- 0x0F, 0x8D, 0x800, 0x7FC, 0x7F8, 0x200, 0x201, 0x202},
- {
- 224, 5120, 3413, 0x71, 0x02, 0x00, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
- 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, 0x8C, 0xDD, 0x00, 0x0D,
- 0x0F, 0x8C, 0x804, 0x800, 0x7FC, 0x1FF, 0x200, 0x201},
- {
- 226, 5130, 3420, 0x71, 0x02, 0x01, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
- 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, 0x8C, 0xDD, 0x00, 0x0D,
- 0x0F, 0x8C, 0x808, 0x804, 0x800, 0x1FE, 0x1FF, 0x200},
- {
- 228, 5140, 3427, 0x71, 0x02, 0x02, 0x0C, 0xC6, 0x01, 0x04, 0x0A,
- 0x00, 0x8D, 0x99, 0x99, 0xDD, 0x00, 0x0C, 0x0E, 0x8B, 0xDD, 0x00, 0x0C,
- 0x0E, 0x8B, 0x80C, 0x808, 0x804, 0x1FD, 0x1FE, 0x1FF},
- {
- 32, 5160, 3440, 0x71, 0x02, 0x04, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
- 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, 0x8A, 0xCC, 0x00, 0x0B,
- 0x0D, 0x8A, 0x814, 0x810, 0x80C, 0x1FB, 0x1FC, 0x1FD},
- {
- 34, 5170, 3447, 0x71, 0x02, 0x05, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
- 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, 0x8A, 0xCC, 0x00, 0x0B,
- 0x0D, 0x8A, 0x818, 0x814, 0x810, 0x1FA, 0x1FB, 0x1FC},
- {
- 36, 5180, 3453, 0x71, 0x02, 0x06, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
- 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, 0x89, 0xCC, 0x00, 0x0B,
- 0x0C, 0x89, 0x81C, 0x818, 0x814, 0x1F9, 0x1FA, 0x1FB},
- {
- 38, 5190, 3460, 0x71, 0x02, 0x07, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
- 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, 0x89, 0xCC, 0x00, 0x0B,
- 0x0C, 0x89, 0x820, 0x81C, 0x818, 0x1F8, 0x1F9, 0x1FA},
- {
- 40, 5200, 3467, 0x71, 0x02, 0x08, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
- 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, 0x89, 0xBB, 0x00, 0x0A,
- 0x0B, 0x89, 0x824, 0x820, 0x81C, 0x1F7, 0x1F8, 0x1F9},
- {
- 42, 5210, 3473, 0x71, 0x02, 0x09, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
- 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, 0x89, 0xBB, 0x00, 0x0A,
- 0x0B, 0x89, 0x828, 0x824, 0x820, 0x1F6, 0x1F7, 0x1F8},
- {
- 44, 5220, 3480, 0x71, 0x02, 0x0A, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
- 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, 0x88, 0xBB, 0x00, 0x09,
- 0x0A, 0x88, 0x82C, 0x828, 0x824, 0x1F5, 0x1F6, 0x1F7},
- {
- 46, 5230, 3487, 0x71, 0x02, 0x0B, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
- 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, 0x88, 0xBB, 0x00, 0x09,
- 0x0A, 0x88, 0x830, 0x82C, 0x828, 0x1F4, 0x1F5, 0x1F6},
- {
- 48, 5240, 3493, 0x71, 0x02, 0x0C, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
- 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A, 0x87, 0xAA, 0x00, 0x09,
- 0x0A, 0x87, 0x834, 0x830, 0x82C, 0x1F3, 0x1F4, 0x1F5},
- {
- 50, 5250, 3500, 0x71, 0x02, 0x0D, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
- 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A, 0x87, 0xAA, 0x00, 0x09,
- 0x0A, 0x87, 0x838, 0x834, 0x830, 0x1F2, 0x1F3, 0x1F4},
- {
- 52, 5260, 3507, 0x71, 0x02, 0x0E, 0x0A, 0x98, 0x01, 0x04, 0x0A,
- 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09, 0x87, 0xAA, 0x00, 0x08,
- 0x09, 0x87, 0x83C, 0x838, 0x834, 0x1F1, 0x1F2, 0x1F3},
- {
- 54, 5270, 3513, 0x71, 0x02, 0x0F, 0x0A, 0x98, 0x01, 0x04, 0x0A,
- 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09, 0x87, 0xAA, 0x00, 0x08,
- 0x09, 0x87, 0x840, 0x83C, 0x838, 0x1F0, 0x1F1, 0x1F2},
- {
- 56, 5280, 3520, 0x71, 0x02, 0x10, 0x09, 0x91, 0x01, 0x04, 0x0A,
- 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08, 0x86, 0x99, 0x00, 0x08,
- 0x08, 0x86, 0x844, 0x840, 0x83C, 0x1F0, 0x1F0, 0x1F1},
- {
- 58, 5290, 3527, 0x71, 0x02, 0x11, 0x09, 0x91, 0x01, 0x04, 0x0A,
- 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08, 0x86, 0x99, 0x00, 0x08,
- 0x08, 0x86, 0x848, 0x844, 0x840, 0x1EF, 0x1F0, 0x1F0},
- {
- 60, 5300, 3533, 0x71, 0x02, 0x12, 0x09, 0x8A, 0x01, 0x04, 0x0A,
- 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07, 0x85, 0x99, 0x00, 0x08,
- 0x07, 0x85, 0x84C, 0x848, 0x844, 0x1EE, 0x1EF, 0x1F0},
- {
- 62, 5310, 3540, 0x71, 0x02, 0x13, 0x09, 0x8A, 0x01, 0x04, 0x0A,
- 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07, 0x85, 0x99, 0x00, 0x08,
- 0x07, 0x85, 0x850, 0x84C, 0x848, 0x1ED, 0x1EE, 0x1EF},
- {
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- {
- 161, 5805, 3870, 0x72, 0x04, 0x89, 0x01, 0xED, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x916, 0x912, 0x90E, 0x1C3, 0x1C4, 0x1C4},
- {
- 162, 5810, 3873, 0x71, 0x02, 0x45, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x918, 0x914, 0x910, 0x1C2, 0x1C3, 0x1C4},
- {
- 163, 5815, 3877, 0x72, 0x04, 0x8B, 0x01, 0xED, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x91A, 0x916, 0x912, 0x1C2, 0x1C3, 0x1C4},
- {
- 164, 5820, 3880, 0x71, 0x02, 0x46, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x91C, 0x918, 0x914, 0x1C2, 0x1C2, 0x1C3},
- {
- 165, 5825, 3883, 0x72, 0x04, 0x8D, 0x01, 0xED, 0x00, 0x03, 0x14,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x91E, 0x91A, 0x916, 0x1C1, 0x1C2, 0x1C3},
- {
- 166, 5830, 3887, 0x71, 0x02, 0x47, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x920, 0x91C, 0x918, 0x1C1, 0x1C2, 0x1C2},
- {
- 168, 5840, 3893, 0x71, 0x02, 0x48, 0x01, 0x0A, 0x01, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x924, 0x920, 0x91C, 0x1C0, 0x1C1, 0x1C2},
- {
- 170, 5850, 3900, 0x71, 0x02, 0x49, 0x01, 0xE0, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x928, 0x924, 0x920, 0x1BF, 0x1C0, 0x1C1},
- {
- 172, 5860, 3907, 0x71, 0x02, 0x4A, 0x01, 0xDE, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x92C, 0x928, 0x924, 0x1BF, 0x1BF, 0x1C0},
- {
- 174, 5870, 3913, 0x71, 0x02, 0x4B, 0x00, 0xDB, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x930, 0x92C, 0x928, 0x1BE, 0x1BF, 0x1BF},
- {
- 176, 5880, 3920, 0x71, 0x02, 0x4C, 0x00, 0xD8, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x934, 0x930, 0x92C, 0x1BD, 0x1BE, 0x1BF},
- {
- 178, 5890, 3927, 0x71, 0x02, 0x4D, 0x00, 0xD6, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x938, 0x934, 0x930, 0x1BC, 0x1BD, 0x1BE},
- {
- 180, 5900, 3933, 0x71, 0x02, 0x4E, 0x00, 0xD3, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x93C, 0x938, 0x934, 0x1BC, 0x1BC, 0x1BD},
- {
- 182, 5910, 3940, 0x71, 0x02, 0x4F, 0x00, 0xD6, 0x00, 0x04, 0x0A,
- 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
- 0x00, 0x80, 0x940, 0x93C, 0x938, 0x1BB, 0x1BC, 0x1BC},
- {
- 1, 2412, 3216, 0x73, 0x09, 0x6C, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0D, 0x0C, 0x80, 0xFF, 0x88, 0x0D,
- 0x0C, 0x80, 0x3C9, 0x3C5, 0x3C1, 0x43A, 0x43F, 0x443},
- {
- 2, 2417, 3223, 0x73, 0x09, 0x71, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0B, 0x80, 0xFF, 0x88, 0x0C,
- 0x0B, 0x80, 0x3CB, 0x3C7, 0x3C3, 0x438, 0x43D, 0x441},
- {
- 3, 2422, 3229, 0x73, 0x09, 0x76, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, 0x80, 0xFF, 0x88, 0x0C,
- 0x0A, 0x80, 0x3CD, 0x3C9, 0x3C5, 0x436, 0x43A, 0x43F},
- {
- 4, 2427, 3236, 0x73, 0x09, 0x7B, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, 0x80, 0xFF, 0x88, 0x0C,
- 0x0A, 0x80, 0x3CF, 0x3CB, 0x3C7, 0x434, 0x438, 0x43D},
- {
- 5, 2432, 3243, 0x73, 0x09, 0x80, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x09, 0x80, 0xFF, 0x88, 0x0C,
- 0x09, 0x80, 0x3D1, 0x3CD, 0x3C9, 0x431, 0x436, 0x43A},
- {
- 6, 2437, 3249, 0x73, 0x09, 0x85, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0B, 0x08, 0x80, 0xFF, 0x88, 0x0B,
- 0x08, 0x80, 0x3D3, 0x3CF, 0x3CB, 0x42F, 0x434, 0x438},
- {
- 7, 2442, 3256, 0x73, 0x09, 0x8A, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x07, 0x80, 0xFF, 0x88, 0x0A,
- 0x07, 0x80, 0x3D5, 0x3D1, 0x3CD, 0x42D, 0x431, 0x436},
- {
- 8, 2447, 3263, 0x73, 0x09, 0x8F, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x06, 0x80, 0xFF, 0x88, 0x0A,
- 0x06, 0x80, 0x3D7, 0x3D3, 0x3CF, 0x42B, 0x42F, 0x434},
- {
- 9, 2452, 3269, 0x73, 0x09, 0x94, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x09, 0x06, 0x80, 0xFF, 0x88, 0x09,
- 0x06, 0x80, 0x3D9, 0x3D5, 0x3D1, 0x429, 0x42D, 0x431},
- {
- 10, 2457, 3276, 0x73, 0x09, 0x99, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x05, 0x80, 0xFF, 0x88, 0x08,
- 0x05, 0x80, 0x3DB, 0x3D7, 0x3D3, 0x427, 0x42B, 0x42F},
- {
- 11, 2462, 3283, 0x73, 0x09, 0x9E, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x04, 0x80, 0xFF, 0x88, 0x08,
- 0x04, 0x80, 0x3DD, 0x3D9, 0x3D5, 0x424, 0x429, 0x42D},
- {
- 12, 2467, 3289, 0x73, 0x09, 0xA3, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x03, 0x80, 0xFF, 0x88, 0x08,
- 0x03, 0x80, 0x3DF, 0x3DB, 0x3D7, 0x422, 0x427, 0x42B},
- {
- 13, 2472, 3296, 0x73, 0x09, 0xA8, 0x0F, 0x00, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x03, 0x80, 0xFF, 0x88, 0x07,
- 0x03, 0x80, 0x3E1, 0x3DD, 0x3D9, 0x420, 0x424, 0x429},
- {
- 14, 2484, 3312, 0x73, 0x09, 0xB4, 0x0F, 0xFF, 0x01, 0x07, 0x15,
- 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x01, 0x80, 0xFF, 0x88, 0x07,
- 0x01, 0x80, 0x3E6, 0x3E2, 0x3DE, 0x41B, 0x41F, 0x424}
-};
-
-static chan_info_nphy_radio205x_t chan_info_nphyrev3_2056[] = {
- {
- 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
- {
- 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
- {
- 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
- {
- 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
- {
- 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
- {
- 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
- {
- 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
- {
- 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
- {
- 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
- {
- 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
- {
- 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
- {
- 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
- {
- 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
- {
- 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
- {
- 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
- {
- 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
- {
- 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
- {
- 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
- {
- 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xff, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
- {
- 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f,
- 0x00, 0x0b, 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
- 0x00, 0xfc, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
- {
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- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf4, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
- {
- 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf4, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
- {
- 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, 0x10, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf4, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
- {
- 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf4, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
- {
- 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf4, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
- {
- 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf4, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
- {
- 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf2, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf2, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
- {
- 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf2, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
- {
- 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf2, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
- {
- 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x06, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
- 0x00, 0xf2, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
- {
- 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x05, 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05,
- 0x00, 0xf2, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
- {
- 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x05, 0x00, 0xf2, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05,
- 0x00, 0xf2, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
- {
- 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
- {
- 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
- {
- 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
- {
- 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfd, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
- {
- 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfb, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfb, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
- {
- 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xfa, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
- {
- 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf8, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
- {
- 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf7, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf7, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
- {
- 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf6, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0xf6, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0f, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
- {
- 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf5, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0d, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
- {
- 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0d, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
- {
- 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf3, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0d, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
- {
- 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf2, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0d, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
- {
- 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x05, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0d, 0x00, 0xf0, 0x00, 0x05, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0d, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
-};
-
-static chan_info_nphy_radio205x_t chan_info_nphyrev4_2056_A1[] = {
- {
- 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
- {
- 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
- {
- 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
- {
- 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
- {
- 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
- {
- 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
- {
- 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
- {
- 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
- {
- 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
- {
- 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
- {
- 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
- {
- 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
- {
- 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
- 0x00, 0xff, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
- {
- 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
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- 0x00, 0xf2, 0x00, 0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7},
- {
- 156, 5780, 0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f,
- 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
- 0x00, 0xf2, 0x00, 0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6},
- {
- 157, 5785, 0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, 0x10, 0x01,
- 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f,
- 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
- 0x00, 0xf2, 0x00, 0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6},
- {
- 158, 5790, 0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f,
- 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
- 0x00, 0xf2, 0x00, 0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6},
- {
- 159, 5795, 0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, 0x10, 0x01,
- 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f,
- 0x00, 0x0a, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
- 0x00, 0xf2, 0x00, 0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5},
- {
- 160, 5800, 0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5},
- {
- 161, 5805, 0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, 0x10, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4},
- {
- 162, 5810, 0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4},
- {
- 163, 5815, 0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, 0x10, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
- {
- 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
- {
- 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, 0x10, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
- {
- 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
- {
- 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
- {
- 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
- {
- 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
- {
- 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
- {
- 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
- {
- 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f,
- 0x00, 0x09, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
- 0x00, 0xf0, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
- {
- 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x07, 0x00, 0xf0, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07,
- 0x00, 0xf0, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
- {
- 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f,
- 0x00, 0x07, 0x00, 0xf0, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07,
- 0x00, 0xf0, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
- {
- 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
- {
- 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
- {
- 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xff, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
- {
- 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfd, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
- {
- 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfb, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfb, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
- {
- 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xfa, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
- {
- 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf8, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
- {
- 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf7, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf7, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
- {
- 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf6, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf6, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
- {
- 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf5, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
- {
- 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
- {
- 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf3, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf3, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
- {
- 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf2, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
- {
- 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x04, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0e, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0e, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
-};
-
-static chan_info_nphy_radio205x_t chan_info_nphyrev5_2056v5[] = {
- {
- 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
- 0x00, 0x0f, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
- {
- 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
- 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
- {
- 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
- 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
- {
- 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
- 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
- {
- 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
- 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
- {
- 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
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-};
-
-static chan_info_nphy_radio205x_t chan_info_nphyrev6_2056v6[] = {
- {
- 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
- {
- 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
- {
- 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
- {
- 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
- {
- 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
- {
- 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
- {
- 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
- {
- 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
- {
- 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
- {
- 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
- {
- 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
- {
- 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
- {
- 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
- {
- 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
- {
- 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
- {
- 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
- {
- 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
- {
- 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
- {
- 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
- {
- 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
- {
- 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
- {
- 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
- {
- 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
- {
- 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
- 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
- {
- 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
- 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
- {
- 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
- 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
- {
- 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
- {
- 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
- {
- 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
- {
- 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
- {
- 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6},
- {
- 48, 5240, 0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5},
- {
- 50, 5250, 0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4},
- {
- 52, 5260, 0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3},
- {
- 54, 5270, 0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77,
- 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2},
- {
- 56, 5280, 0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77,
- 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1},
- {
- 58, 5290, 0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77,
- 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0},
- {
- 60, 5300, 0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77,
- 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0},
- {
- 62, 5310, 0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77,
- 0x00, 0x0c, 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef},
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- 0x0a, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
- {
- 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x23, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
- {
- 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x12, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
- {
- 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
- {
- 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
- {
- 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
- {
- 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
-};
-
-static chan_info_nphy_radio205x_t chan_info_nphyrev5n6_2056v7[] = {
- {
- 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
- 0x00, 0x0f, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
- {
- 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
- 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
- {
- 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
- 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
- {
- 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70,
- 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
- {
- 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
- 0x00, 0x0e, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
- {
- 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
- 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
- {
- 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
- 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
- {
- 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
- 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
- {
- 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
- 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
- {
- 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70,
- 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
- {
- 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x09, 0x00, 0x70,
- 0x00, 0x0d, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d,
- 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
- {
- 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xff, 0x00, 0x09, 0x00, 0x70,
- 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
- {
- 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70,
- 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
- {
- 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70,
- 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
- {
- 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x70,
- 0x00, 0x0c, 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
- 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
- {
- 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x70,
- 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
- 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
- {
- 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
- 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
- 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
- {
- 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
- 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
- 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
- {
- 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
- 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
- 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
- {
- 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
- 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
- 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
- {
- 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70,
- 0x00, 0x0b, 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
- 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
- {
- 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x70,
- 0x00, 0x0a, 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a,
- 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
- {
- 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70,
- 0x00, 0x0a, 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a,
- 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
- {
- 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70,
- 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09,
- 0x00, 0x6e, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
- {
- 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x06, 0x00, 0x70,
- 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
- 0x00, 0x6e, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
- {
- 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
- 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
- 0x00, 0x6e, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
- {
- 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
- 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
- 0x00, 0x6e, 0x00, 0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa},
- {
- 40, 5200, 0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
- 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
- 0x00, 0x6e, 0x00, 0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9},
- {
- 42, 5210, 0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70,
- 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
- 0x00, 0x6e, 0x00, 0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8},
- {
- 44, 5220, 0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xfe, 0xfa, 0x00, 0x06, 0x00, 0x70,
- 0x00, 0x09, 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
- 0x00, 0x6e, 0x00, 0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7},
- {
- 46, 5230, 0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xea, 0x00, 0x06, 0x00, 0x70,
- 0x00, 0x08, 0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08,
- 0x00, 0x6e, 0x00, 0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6},
- {
- 48, 5240, 0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, 0xee, 0xe9, 0x00, 0x05, 0x00, 0x70,
- 0x00, 0x08, 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
- 0x00, 0x6d, 0x00, 0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5},
- {
- 50, 5250, 0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, 0x0c, 0x01,
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- {
- 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x89, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0f, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
- {
- 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0e, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
- {
- 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0e, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
- {
- 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x76, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0e, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
- {
- 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x66, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0e, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0e, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
- {
- 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x55, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0e, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
- {
- 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0e, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0e, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
- {
- 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0d, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
- {
- 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0d, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0d, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
- {
- 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x22, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0d, 0x00, 0x08, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
- {
- 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0d, 0x00, 0x08, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
- {
- 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0d, 0x00, 0x08, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
-};
-
-static chan_info_nphy_radio205x_t chan_info_nphyrev6_2056v8[] = {
- {
- 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
- {
- 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
- {
- 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
- {
- 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
- {
- 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
- {
- 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
- {
- 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
- {
- 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
- {
- 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
- {
- 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
- {
- 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
- {
- 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
- {
- 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
- {
- 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
- {
- 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
- {
- 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
- {
- 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
- {
- 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
- {
- 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
- {
- 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
- {
- 224, 5120, 0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201},
- {
- 226, 5130, 0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200},
- {
- 228, 5140, 0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff},
- {
- 32, 5160, 0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
- 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd},
- {
- 34, 5170, 0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77,
- 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc},
- {
- 36, 5180, 0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
- 0x00, 0x0e, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e,
- 0x00, 0x6f, 0x00, 0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb},
- {
- 38, 5190, 0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77,
- 0x00, 0x0d, 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d,
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- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
- {
- 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
- {
- 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
- {
- 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
- {
- 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
- {
- 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0b, 0x00, 0x0a, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
- {
- 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0b, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
- {
- 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x67, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0b, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
- {
- 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x57, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
- {
- 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x56, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
- {
- 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x46, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
- {
- 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
- {
- 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
- {
- 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x23, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
- {
- 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x12, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
- {
- 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
- {
- 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
- {
- 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
- {
- 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, 0x16, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
-};
-
-static chan_info_nphy_radio205x_t chan_info_nphyrev6_2056v11[] = {
- {
- 184, 4920, 0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216},
- {
- 186, 4930, 0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215},
- {
- 188, 4940, 0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214},
- {
- 190, 4950, 0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213},
- {
- 192, 4960, 0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212},
- {
- 194, 4970, 0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211},
- {
- 196, 4980, 0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f},
- {
- 198, 4990, 0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e},
- {
- 200, 5000, 0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d},
- {
- 202, 5010, 0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c},
- {
- 204, 5020, 0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b},
- {
- 206, 5030, 0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a},
- {
- 208, 5040, 0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209},
- {
- 210, 5050, 0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208},
- {
- 212, 5060, 0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207},
- {
- 214, 5070, 0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206},
- {
- 216, 5080, 0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205},
- {
- 218, 5090, 0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204},
- {
- 220, 5100, 0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203},
- {
- 222, 5110, 0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77,
- 0x00, 0x0f, 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
- 0x00, 0x6f, 0x00, 0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202},
- {
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- 0x00, 0x05, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
- 0x00, 0x6a, 0x00, 0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4},
- {
- 164, 5820, 0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x05, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
- 0x00, 0x6a, 0x00, 0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3},
- {
- 165, 5825, 0xed, 0x00, 0x02, 0x04, 0x8d, 0x05, 0x05, 0x02, 0x15, 0x01,
- 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x05, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
- 0x00, 0x69, 0x00, 0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3},
- {
- 166, 5830, 0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x05, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
- 0x00, 0x69, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2},
- {
- 168, 5840, 0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x69, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2},
- {
- 170, 5850, 0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x69, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1},
- {
- 172, 5860, 0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x69, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0},
- {
- 174, 5870, 0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf},
- {
- 176, 5880, 0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf},
- {
- 178, 5890, 0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be},
- {
- 180, 5900, 0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd},
- {
- 182, 5910, 0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x02, 0x0c, 0x01,
- 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
- 0x00, 0x04, 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
- 0x00, 0x68, 0x00, 0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc},
- {
- 1, 2412, 0x00, 0x01, 0x03, 0x09, 0x6c, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0b, 0x00, 0x0a, 0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443},
- {
- 2, 2417, 0x00, 0x01, 0x03, 0x09, 0x71, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0b, 0x00, 0x0a, 0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441},
- {
- 3, 2422, 0x00, 0x01, 0x03, 0x09, 0x76, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x67, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0b, 0x00, 0x0a, 0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f},
- {
- 4, 2427, 0x00, 0x01, 0x03, 0x09, 0x7b, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x57, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x0a, 0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d},
- {
- 5, 2432, 0x00, 0x01, 0x03, 0x09, 0x80, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x56, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x0a, 0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a},
- {
- 6, 2437, 0x00, 0x01, 0x03, 0x09, 0x85, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x46, 0x00, 0x03, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x0a, 0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438},
- {
- 7, 2442, 0x00, 0x01, 0x03, 0x09, 0x8a, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x45, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x0a, 0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436},
- {
- 8, 2447, 0x00, 0x01, 0x03, 0x09, 0x8f, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x34, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x09, 0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434},
- {
- 9, 2452, 0x00, 0x01, 0x03, 0x09, 0x94, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x23, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x09, 0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431},
- {
- 10, 2457, 0x00, 0x01, 0x03, 0x09, 0x99, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x12, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x0a, 0x00, 0x09, 0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f},
- {
- 11, 2462, 0x00, 0x01, 0x03, 0x09, 0x9e, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d},
- {
- 12, 2467, 0x00, 0x01, 0x03, 0x09, 0xa3, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b},
- {
- 13, 2472, 0x00, 0x01, 0x03, 0x09, 0xa8, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429},
- {
- 14, 2484, 0xff, 0x01, 0x03, 0x09, 0xb4, 0x06, 0x06, 0x04, 0x2b, 0x01,
- 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
- 0x70, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
- 0x09, 0x00, 0x09, 0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424}
-};
-
-static chan_info_nphy_radio2057_t chan_info_nphyrev7_2057_rev4[] = {
- {
- 184, 4920, 0x68, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xec, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07b4, 0x07b0, 0x07ac, 0x0214,
- 0x0215,
- 0x0216,
- },
- {
- 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07b8, 0x07b4, 0x07b0, 0x0213,
- 0x0214,
- 0x0215,
- },
- {
- 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07bc, 0x07b8, 0x07b4, 0x0212,
- 0x0213,
- 0x0214,
- },
- {
- 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c0, 0x07bc, 0x07b8, 0x0211,
- 0x0212,
- 0x0213,
- },
- {
- 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c4, 0x07c0, 0x07bc, 0x020f,
- 0x0211,
- 0x0212,
- },
- {
- 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07c8, 0x07c4, 0x07c0, 0x020e,
- 0x020f,
- 0x0211,
- },
- {
- 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07cc, 0x07c8, 0x07c4, 0x020d,
- 0x020e,
- 0x020f,
- },
- {
- 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d0, 0x07cc, 0x07c8, 0x020c,
- 0x020d,
- 0x020e,
- },
- {
- 200, 5000, 0x82, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf4, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d4, 0x07d0, 0x07cc, 0x020b,
- 0x020c,
- 0x020d,
- },
- {
- 202, 5010, 0x86, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf5, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07d8, 0x07d4, 0x07d0, 0x020a,
- 0x020b,
- 0x020c,
- },
- {
- 204, 5020, 0x89, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf6, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07dc, 0x07d8, 0x07d4, 0x0209,
- 0x020a,
- 0x020b,
- },
- {
- 206, 5030, 0x8c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf7, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e0, 0x07dc, 0x07d8, 0x0208,
- 0x0209,
- 0x020a,
- },
- {
- 208, 5040, 0x90, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf8, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e4, 0x07e0, 0x07dc, 0x0207,
- 0x0208,
- 0x0209,
- },
- {
- 210, 5050, 0x93, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf9, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xf3, 0x00, 0xef, 0x07e8, 0x07e4, 0x07e0, 0x0206,
- 0x0207,
- 0x0208,
- },
- {
- 212, 5060, 0x96, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfa, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xe3, 0x00, 0xef, 0x00,
- 0x00, 0x0f, 0x0f, 0xe3, 0x00, 0xef, 0x07ec, 0x07e8, 0x07e4, 0x0205,
- 0x0206,
- 0x0207,
- },
- {
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- 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x03, 0x00, 0x43, 0x00, 0x00, 0x00,
- 0x00, 0x03, 0x00, 0x43, 0x00, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd,
- 0x01be,
- 0x01bf,
- },
- {
- 178, 5890, 0xab, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4d, 0x02, 0x03,
- 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x03, 0x00, 0x43, 0x00, 0x00, 0x00,
- 0x00, 0x03, 0x00, 0x43, 0x00, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc,
- 0x01bd,
- 0x01be,
- },
- {
- 180, 5900, 0xae, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4e, 0x02, 0x03,
- 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x03, 0x00, 0x43, 0x00, 0x00, 0x00,
- 0x00, 0x03, 0x00, 0x43, 0x00, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc,
- 0x01bc,
- 0x01bd,
- },
- {
- 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0f,
- 0x0a, 0x00, 0x0a, 0x00, 0x71, 0xa3, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x71,
- 0xa3, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03c9, 0x03c5, 0x03c1, 0x043a,
- 0x043f,
- 0x0443,
- },
- {
- 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0f,
- 0x0a, 0x00, 0x0a, 0x00, 0x71, 0xa3, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x71,
- 0xa3, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cb, 0x03c7, 0x03c3, 0x0438,
- 0x043d,
- 0x0441,
- },
- {
- 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0f,
- 0x09, 0x00, 0x09, 0x00, 0x71, 0x93, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x71,
- 0x93, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cd, 0x03c9, 0x03c5, 0x0436,
- 0x043a,
- 0x043f,
- },
- {
- 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0f,
- 0x09, 0x00, 0x09, 0x00, 0x71, 0x93, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x71,
- 0x93, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cf, 0x03cb, 0x03c7, 0x0434,
- 0x0438,
- 0x043d,
- },
- {
- 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0f,
- 0x08, 0x00, 0x08, 0x00, 0x51, 0x83, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x51,
- 0x83, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d1, 0x03cd, 0x03c9, 0x0431,
- 0x0436,
- 0x043a,
- },
- {
- 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0f,
- 0x08, 0x00, 0x08, 0x00, 0x51, 0x83, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x51,
- 0x83, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d3, 0x03cf, 0x03cb, 0x042f,
- 0x0434,
- 0x0438,
- },
- {
- 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0f,
- 0x07, 0x00, 0x07, 0x00, 0x51, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x51,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d5, 0x03d1, 0x03cd, 0x042d,
- 0x0431,
- 0x0436,
- },
- {
- 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0f,
- 0x07, 0x00, 0x07, 0x00, 0x31, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d7, 0x03d3, 0x03cf, 0x042b,
- 0x042f,
- 0x0434,
- },
- {
- 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0f,
- 0x07, 0x00, 0x07, 0x00, 0x31, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d9, 0x03d5, 0x03d1, 0x0429,
- 0x042d,
- 0x0431,
- },
- {
- 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0f,
- 0x06, 0x00, 0x06, 0x00, 0x31, 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
- 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03db, 0x03d7, 0x03d3, 0x0427,
- 0x042b,
- 0x042f,
- },
- {
- 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0f,
- 0x06, 0x00, 0x06, 0x00, 0x31, 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x31,
- 0x63, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03dd, 0x03d9, 0x03d5, 0x0424,
- 0x0429,
- 0x042d,
- },
- {
- 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0f,
- 0x05, 0x00, 0x05, 0x00, 0x11, 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x11,
- 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03df, 0x03db, 0x03d7, 0x0422,
- 0x0427,
- 0x042b,
- },
- {
- 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0f,
- 0x05, 0x00, 0x05, 0x00, 0x11, 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x11,
- 0x53, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03e1, 0x03dd, 0x03d9, 0x0420,
- 0x0424,
- 0x0429,
- },
- {
- 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
- 0x04, 0x00, 0x04, 0x00, 0x11, 0x43, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x11,
- 0x43, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
- 0x041f,
- 0x0424}
-};
-
-static chan_info_nphy_radio2057_rev5_t chan_info_nphyrev8_2057_rev5[] = {
- {
- 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0d,
- 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03c9, 0x03c5, 0x03c1,
- 0x043a, 0x043f, 0x0443},
- {
- 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0d,
- 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03cb, 0x03c7, 0x03c3,
- 0x0438, 0x043d, 0x0441},
- {
- 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0d,
- 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61, 0x03, 0xef, 0x03cd, 0x03c9, 0x03c5,
- 0x0436, 0x043a, 0x043f},
- {
- 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0c,
- 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61, 0x03, 0xdf, 0x03cf, 0x03cb, 0x03c7,
- 0x0434, 0x0438, 0x043d},
- {
- 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0c,
- 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61, 0x03, 0xcf, 0x03d1, 0x03cd, 0x03c9,
- 0x0431, 0x0436, 0x043a},
- {
- 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0c,
- 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61, 0x03, 0xbf, 0x03d3, 0x03cf, 0x03cb,
- 0x042f, 0x0434, 0x0438},
- {
- 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0b,
- 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61, 0x03, 0xaf, 0x03d5, 0x03d1, 0x03cd,
- 0x042d, 0x0431, 0x0436},
- {
- 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0b,
- 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61, 0x03, 0x9f, 0x03d7, 0x03d3, 0x03cf,
- 0x042b, 0x042f, 0x0434},
- {
- 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0b,
- 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61, 0x03, 0x8f, 0x03d9, 0x03d5, 0x03d1,
- 0x0429, 0x042d, 0x0431},
- {
- 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0b,
- 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61, 0x03, 0x7f, 0x03db, 0x03d7, 0x03d3,
- 0x0427, 0x042b, 0x042f},
- {
- 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0b,
- 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61, 0x03, 0x6f, 0x03dd, 0x03d9, 0x03d5,
- 0x0424, 0x0429, 0x042d},
- {
- 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0b,
- 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61, 0x03, 0x5f, 0x03df, 0x03db, 0x03d7,
- 0x0422, 0x0427, 0x042b},
- {
- 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0a,
- 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61, 0x03, 0x4f, 0x03e1, 0x03dd, 0x03d9,
- 0x0420, 0x0424, 0x0429},
- {
- 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0a,
- 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61, 0x03, 0x3f, 0x03e6, 0x03e2, 0x03de,
- 0x041b, 0x041f, 0x0424}
-};
-
-static chan_info_nphy_radio2057_rev5_t chan_info_nphyrev9_2057_rev5v1[] = {
- {
- 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0d,
- 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03c9, 0x03c5, 0x03c1,
- 0x043a, 0x043f, 0x0443},
- {
- 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0d,
- 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, 0x03, 0xff, 0x03cb, 0x03c7, 0x03c3,
- 0x0438, 0x043d, 0x0441},
- {
- 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0d,
- 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61, 0x03, 0xef, 0x03cd, 0x03c9, 0x03c5,
- 0x0436, 0x043a, 0x043f},
- {
- 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0c,
- 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61, 0x03, 0xdf, 0x03cf, 0x03cb, 0x03c7,
- 0x0434, 0x0438, 0x043d},
- {
- 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0c,
- 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61, 0x03, 0xcf, 0x03d1, 0x03cd, 0x03c9,
- 0x0431, 0x0436, 0x043a},
- {
- 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0c,
- 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61, 0x03, 0xbf, 0x03d3, 0x03cf, 0x03cb,
- 0x042f, 0x0434, 0x0438},
- {
- 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0b,
- 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61, 0x03, 0xaf, 0x03d5, 0x03d1, 0x03cd,
- 0x042d, 0x0431, 0x0436},
- {
- 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0b,
- 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61, 0x03, 0x9f, 0x03d7, 0x03d3, 0x03cf,
- 0x042b, 0x042f, 0x0434},
- {
- 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0b,
- 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61, 0x03, 0x8f, 0x03d9, 0x03d5, 0x03d1,
- 0x0429, 0x042d, 0x0431},
- {
- 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0b,
- 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61, 0x03, 0x7f, 0x03db, 0x03d7, 0x03d3,
- 0x0427, 0x042b, 0x042f},
- {
- 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0b,
- 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61, 0x03, 0x6f, 0x03dd, 0x03d9, 0x03d5,
- 0x0424, 0x0429, 0x042d},
- {
- 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0b,
- 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61, 0x03, 0x5f, 0x03df, 0x03db, 0x03d7,
- 0x0422, 0x0427, 0x042b},
- {
- 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0a,
- 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61, 0x03, 0x4f, 0x03e1, 0x03dd, 0x03d9,
- 0x0420, 0x0424, 0x0429},
- {
- 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0a,
- 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61, 0x03, 0x3f, 0x03e6, 0x03e2, 0x03de,
- 0x041b, 0x041f, 0x0424}
-};
-
-static chan_info_nphy_radio2057_t chan_info_nphyrev8_2057_rev7[] = {
- {
- 184, 4920, 0x68, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xec, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b4, 0x07b0, 0x07ac, 0x0214,
- 0x0215,
- 0x0216},
- {
- 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b8, 0x07b4, 0x07b0, 0x0213,
- 0x0214,
- 0x0215},
- {
- 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07bc, 0x07b8, 0x07b4, 0x0212,
- 0x0213,
- 0x0214},
- {
- 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c0, 0x07bc, 0x07b8, 0x0211,
- 0x0212,
- 0x0213},
- {
- 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c4, 0x07c0, 0x07bc, 0x020f,
- 0x0211,
- 0x0212},
- {
- 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c8, 0x07c4, 0x07c0, 0x020e,
- 0x020f,
- 0x0211},
- {
- 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07cc, 0x07c8, 0x07c4, 0x020d,
- 0x020e,
- 0x020f},
- {
- 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07d0, 0x07cc, 0x07c8, 0x020c,
- 0x020d,
- 0x020e},
- {
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- 0x00, 0x05, 0x00, 0x55, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
- 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0920, 0x091c, 0x0918, 0x01c1,
- 0x01c2,
- 0x01c2},
- {
- 168, 5840, 0x9a, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x48, 0x02, 0x05,
- 0x00, 0x05, 0x00, 0x55, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
- 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0924, 0x0920, 0x091c, 0x01c0,
- 0x01c1,
- 0x01c2},
- {
- 170, 5850, 0x9e, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x49, 0x02, 0x04,
- 0x00, 0x04, 0x00, 0x44, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
- 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0928, 0x0924, 0x0920, 0x01bf,
- 0x01c0,
- 0x01c1},
- {
- 172, 5860, 0xa1, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4a, 0x02, 0x04,
- 0x00, 0x04, 0x00, 0x44, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
- 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x092c, 0x0928, 0x0924, 0x01bf,
- 0x01bf,
- 0x01c0},
- {
- 174, 5870, 0xa4, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4b, 0x02, 0x04,
- 0x00, 0x04, 0x00, 0x44, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
- 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0930, 0x092c, 0x0928, 0x01be,
- 0x01bf,
- 0x01bf},
- {
- 176, 5880, 0xa8, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4c, 0x02, 0x03,
- 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
- 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0934, 0x0930, 0x092c, 0x01bd,
- 0x01be,
- 0x01bf},
- {
- 178, 5890, 0xab, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4d, 0x02, 0x03,
- 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
- 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x0938, 0x0934, 0x0930, 0x01bc,
- 0x01bd,
- 0x01be},
- {
- 180, 5900, 0xae, 0x17, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x4e, 0x02, 0x03,
- 0x00, 0x03, 0x00, 0x33, 0x00, 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x00,
- 0x00, 0x06, 0x01, 0x03, 0x00, 0x00, 0x093c, 0x0938, 0x0934, 0x01bc,
- 0x01bc,
- 0x01bd},
- {
- 1, 2412, 0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 0x09, 0x0f,
- 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03c9, 0x03c5, 0x03c1, 0x043a,
- 0x043f,
- 0x0443},
- {
- 2, 2417, 0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 0x09, 0x0f,
- 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cb, 0x03c7, 0x03c3, 0x0438,
- 0x043d,
- 0x0441},
- {
- 3, 2422, 0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 0x09, 0x0f,
- 0x09, 0x00, 0x09, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cd, 0x03c9, 0x03c5, 0x0436,
- 0x043a,
- 0x043f},
- {
- 4, 2427, 0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 0x09, 0x0f,
- 0x09, 0x00, 0x09, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03cf, 0x03cb, 0x03c7, 0x0434,
- 0x0438,
- 0x043d},
- {
- 5, 2432, 0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 0x09, 0x0f,
- 0x08, 0x00, 0x08, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d1, 0x03cd, 0x03c9, 0x0431,
- 0x0436,
- 0x043a},
- {
- 6, 2437, 0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 0x09, 0x0f,
- 0x08, 0x00, 0x08, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d3, 0x03cf, 0x03cb, 0x042f,
- 0x0434,
- 0x0438},
- {
- 7, 2442, 0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 0x09, 0x0f,
- 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d5, 0x03d1, 0x03cd, 0x042d,
- 0x0431,
- 0x0436},
- {
- 8, 2447, 0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 0x09, 0x0f,
- 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d7, 0x03d3, 0x03cf, 0x042b,
- 0x042f,
- 0x0434},
- {
- 9, 2452, 0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 0x09, 0x0f,
- 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03d9, 0x03d5, 0x03d1, 0x0429,
- 0x042d,
- 0x0431},
- {
- 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0f,
- 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03db, 0x03d7, 0x03d3, 0x0427,
- 0x042b,
- 0x042f},
- {
- 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0f,
- 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03dd, 0x03d9, 0x03d5, 0x0424,
- 0x0429,
- 0x042d},
- {
- 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0f,
- 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03df, 0x03db, 0x03d7, 0x0422,
- 0x0427,
- 0x042b},
- {
- 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0f,
- 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03e1, 0x03dd, 0x03d9, 0x0420,
- 0x0424,
- 0x0429},
- {
- 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
- 0x04, 0x00, 0x04, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
- 0x041f,
- 0x0424}
-};
-
-static chan_info_nphy_radio2057_t chan_info_nphyrev8_2057_rev8[] = {
- {
- 186, 4930, 0x6b, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xed, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07b8, 0x07b4, 0x07b0, 0x0213,
- 0x0214,
- 0x0215},
- {
- 188, 4940, 0x6e, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xee, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0xd3, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07bc, 0x07b8, 0x07b4, 0x0212,
- 0x0213,
- 0x0214},
- {
- 190, 4950, 0x72, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xef, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c0, 0x07bc, 0x07b8, 0x0211,
- 0x0212,
- 0x0213},
- {
- 192, 4960, 0x75, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf0, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c4, 0x07c0, 0x07bc, 0x020f,
- 0x0211,
- 0x0212},
- {
- 194, 4970, 0x78, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf1, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07c8, 0x07c4, 0x07c0, 0x020e,
- 0x020f,
- 0x0211},
- {
- 196, 4980, 0x7c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf2, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07cc, 0x07c8, 0x07c4, 0x020d,
- 0x020e,
- 0x020f},
- {
- 198, 4990, 0x7f, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf3, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xd3, 0x00, 0xff, 0x07d0, 0x07cc, 0x07c8, 0x020c,
- 0x020d,
- 0x020e},
- {
- 200, 5000, 0x82, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf4, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d4, 0x07d0, 0x07cc, 0x020b,
- 0x020c,
- 0x020d},
- {
- 202, 5010, 0x86, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf5, 0x01, 0x0f,
- 0x00, 0x0f, 0x00, 0xff, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07d8, 0x07d4, 0x07d0, 0x020a,
- 0x020b,
- 0x020c},
- {
- 204, 5020, 0x89, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf6, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07dc, 0x07d8, 0x07d4, 0x0209,
- 0x020a,
- 0x020b},
- {
- 206, 5030, 0x8c, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf7, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e0, 0x07dc, 0x07d8, 0x0208,
- 0x0209,
- 0x020a},
- {
- 208, 5040, 0x90, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf8, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e4, 0x07e0, 0x07dc, 0x0207,
- 0x0208,
- 0x0209},
- {
- 210, 5050, 0x93, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xf9, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07e8, 0x07e4, 0x07e0, 0x0206,
- 0x0207,
- 0x0208},
- {
- 212, 5060, 0x96, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfa, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07ec, 0x07e8, 0x07e4, 0x0205,
- 0x0206,
- 0x0207},
- {
- 214, 5070, 0x9a, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfb, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f0, 0x07ec, 0x07e8, 0x0204,
- 0x0205,
- 0x0206},
- {
- 216, 5080, 0x9d, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfc, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f4, 0x07f0, 0x07ec, 0x0203,
- 0x0204,
- 0x0205},
- {
- 218, 5090, 0xa0, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfd, 0x01, 0x0e,
- 0x00, 0x0e, 0x00, 0xee, 0x00, 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x00,
- 0x00, 0x0f, 0x0f, 0xb3, 0x00, 0xff, 0x07f8, 0x07f4, 0x07f0, 0x0202,
- 0x0203,
- 0x0204},
- {
- 220, 5100, 0xa4, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xfe, 0x01, 0x0d,
- 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
- 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x07fc, 0x07f8, 0x07f4, 0x0201,
- 0x0202,
- 0x0203},
- {
- 222, 5110, 0xa7, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0xff, 0x01, 0x0d,
- 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
- 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0800, 0x07fc, 0x07f8, 0x0200,
- 0x0201,
- 0x0202},
- {
- 224, 5120, 0xaa, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x00, 0x02, 0x0d,
- 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
- 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0804, 0x0800, 0x07fc, 0x01ff,
- 0x0200,
- 0x0201},
- {
- 226, 5130, 0xae, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x01, 0x02, 0x0d,
- 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
- 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0808, 0x0804, 0x0800, 0x01fe,
- 0x01ff,
- 0x0200},
- {
- 228, 5140, 0xb1, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x02, 0x02, 0x0d,
- 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
- 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x080c, 0x0808, 0x0804, 0x01fd,
- 0x01fe,
- 0x01ff},
- {
- 32, 5160, 0xb8, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x04, 0x02, 0x0d,
- 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
- 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0814, 0x0810, 0x080c, 0x01fb,
- 0x01fc,
- 0x01fd},
- {
- 34, 5170, 0xbb, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x05, 0x02, 0x0d,
- 0x00, 0x0d, 0x00, 0xdd, 0x00, 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x00,
- 0x00, 0x0f, 0x0f, 0xa3, 0x00, 0xfc, 0x0818, 0x0814, 0x0810, 0x01fa,
- 0x01fb,
- 0x01fc},
- {
- 36, 5180, 0xbe, 0x16, 0x10, 0x0c, 0x0c, 0x0c, 0x30, 0x06, 0x02, 0x0c,
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- 10, 2457, 0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 0x09, 0x0f,
- 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03db, 0x03d7, 0x03d3, 0x0427,
- 0x042b,
- 0x042f},
- {
- 11, 2462, 0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 0x09, 0x0f,
- 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03dd, 0x03d9, 0x03d5, 0x0424,
- 0x0429,
- 0x042d},
- {
- 12, 2467, 0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 0x09, 0x0f,
- 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03df, 0x03db, 0x03d7, 0x0422,
- 0x0427,
- 0x042b},
- {
- 13, 2472, 0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 0x09, 0x0f,
- 0x05, 0x00, 0x05, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x03e1, 0x03dd, 0x03d9, 0x0420,
- 0x0424,
- 0x0429},
- {
- 14, 2484, 0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, 0x09, 0x0f,
- 0x04, 0x00, 0x04, 0x00, 0x61, 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x61,
- 0x73, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x03e6, 0x03e2, 0x03de, 0x041b,
- 0x041f,
- 0x0424}
-};
-
-radio_regs_t regs_2055[] = {
- {0x02, 0x80, 0x80, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0x27, 0x27, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0x27, 0x27, 0, 0},
- {0x07, 0x7f, 0x7f, 1, 1},
- {0x08, 0x7, 0x7, 1, 1},
- {0x09, 0x7f, 0x7f, 1, 1},
- {0x0A, 0x7, 0x7, 1, 1},
- {0x0B, 0x15, 0x15, 0, 0},
- {0x0C, 0x15, 0x15, 0, 0},
- {0x0D, 0x4f, 0x4f, 1, 1},
- {0x0E, 0x5, 0x5, 1, 1},
- {0x0F, 0x4f, 0x4f, 1, 1},
- {0x10, 0x5, 0x5, 1, 1},
- {0x11, 0xd0, 0xd0, 0, 0},
- {0x12, 0x2, 0x2, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0x40, 0x40, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0xc0, 0xc0, 0, 0},
- {0x1E, 0xff, 0xff, 0, 0},
- {0x1F, 0xc0, 0xc0, 0, 0},
- {0x20, 0xff, 0xff, 0, 0},
- {0x21, 0xc0, 0xc0, 0, 0},
- {0x22, 0, 0, 0, 0},
- {0x23, 0x2c, 0x2c, 0, 0},
- {0x24, 0, 0, 0, 0},
- {0x25, 0, 0, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0, 0, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0, 0, 0, 0},
- {0x2A, 0, 0, 0, 0},
- {0x2B, 0, 0, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0xa4, 0xa4, 0, 0},
- {0x2E, 0x38, 0x38, 0, 0},
- {0x2F, 0, 0, 0, 0},
- {0x30, 0x4, 0x4, 1, 1},
- {0x31, 0, 0, 0, 0},
- {0x32, 0xa, 0xa, 0, 0},
- {0x33, 0x87, 0x87, 0, 0},
- {0x34, 0x9, 0x9, 0, 0},
- {0x35, 0x70, 0x70, 0, 0},
- {0x36, 0x11, 0x11, 0, 0},
- {0x37, 0x18, 0x18, 1, 1},
- {0x38, 0x6, 0x6, 0, 0},
- {0x39, 0x4, 0x4, 1, 1},
- {0x3A, 0x6, 0x6, 0, 0},
- {0x3B, 0x9e, 0x9e, 0, 0},
- {0x3C, 0x9, 0x9, 0, 0},
- {0x3D, 0xc8, 0xc8, 1, 1},
- {0x3E, 0x88, 0x88, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0, 0, 0, 0},
- {0x42, 0x1, 0x1, 0, 0},
- {0x43, 0x2, 0x2, 0, 0},
- {0x44, 0x96, 0x96, 0, 0},
- {0x45, 0x3e, 0x3e, 0, 0},
- {0x46, 0x3e, 0x3e, 0, 0},
- {0x47, 0x13, 0x13, 0, 0},
- {0x48, 0x2, 0x2, 0, 0},
- {0x49, 0x15, 0x15, 0, 0},
- {0x4A, 0x7, 0x7, 0, 0},
- {0x4B, 0, 0, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0, 0, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0, 0, 0, 0},
- {0x50, 0x8, 0x8, 0, 0},
- {0x51, 0x8, 0x8, 0, 0},
- {0x52, 0x6, 0x6, 0, 0},
- {0x53, 0x84, 0x84, 1, 1},
- {0x54, 0xc3, 0xc3, 0, 0},
- {0x55, 0x8f, 0x8f, 0, 0},
- {0x56, 0xff, 0xff, 0, 0},
- {0x57, 0xff, 0xff, 0, 0},
- {0x58, 0x88, 0x88, 0, 0},
- {0x59, 0x88, 0x88, 0, 0},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0xcc, 0xcc, 0, 0},
- {0x5C, 0x6, 0x6, 0, 0},
- {0x5D, 0x80, 0x80, 0, 0},
- {0x5E, 0x80, 0x80, 0, 0},
- {0x5F, 0xf8, 0xf8, 0, 0},
- {0x60, 0x88, 0x88, 0, 0},
- {0x61, 0x88, 0x88, 0, 0},
- {0x62, 0x88, 0x8, 1, 1},
- {0x63, 0x88, 0x88, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0x1, 0x1, 1, 1},
- {0x66, 0x8a, 0x8a, 0, 0},
- {0x67, 0x8, 0x8, 0, 0},
- {0x68, 0x83, 0x83, 0, 0},
- {0x69, 0x6, 0x6, 0, 0},
- {0x6A, 0xa0, 0xa0, 0, 0},
- {0x6B, 0xa, 0xa, 0, 0},
- {0x6C, 0x87, 0x87, 1, 1},
- {0x6D, 0x2a, 0x2a, 0, 0},
- {0x6E, 0x2a, 0x2a, 0, 0},
- {0x6F, 0x2a, 0x2a, 0, 0},
- {0x70, 0x2a, 0x2a, 0, 0},
- {0x71, 0x18, 0x18, 0, 0},
- {0x72, 0x6a, 0x6a, 1, 1},
- {0x73, 0xab, 0xab, 1, 1},
- {0x74, 0x13, 0x13, 1, 1},
- {0x75, 0xc1, 0xc1, 1, 1},
- {0x76, 0xaa, 0xaa, 1, 1},
- {0x77, 0x87, 0x87, 1, 1},
- {0x78, 0, 0, 0, 0},
- {0x79, 0x6, 0x6, 0, 0},
- {0x7A, 0x7, 0x7, 0, 0},
- {0x7B, 0x7, 0x7, 0, 0},
- {0x7C, 0x15, 0x15, 0, 0},
- {0x7D, 0x55, 0x55, 0, 0},
- {0x7E, 0x97, 0x97, 1, 1},
- {0x7F, 0x8, 0x8, 0, 0},
- {0x80, 0x14, 0x14, 1, 1},
- {0x81, 0x33, 0x33, 0, 0},
- {0x82, 0x88, 0x88, 0, 0},
- {0x83, 0x6, 0x6, 0, 0},
- {0x84, 0x3, 0x3, 1, 1},
- {0x85, 0xa, 0xa, 0, 0},
- {0x86, 0x3, 0x3, 1, 1},
- {0x87, 0x2a, 0x2a, 0, 0},
- {0x88, 0xa4, 0xa4, 0, 0},
- {0x89, 0x18, 0x18, 0, 0},
- {0x8A, 0x28, 0x28, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0x4a, 0x4a, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0xf8, 0xf8, 0, 0},
- {0x8F, 0x88, 0x88, 0, 0},
- {0x90, 0x88, 0x88, 0, 0},
- {0x91, 0x88, 0x8, 1, 1},
- {0x92, 0x88, 0x88, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0x1, 0x1, 1, 1},
- {0x95, 0x8a, 0x8a, 0, 0},
- {0x96, 0x8, 0x8, 0, 0},
- {0x97, 0x83, 0x83, 0, 0},
- {0x98, 0x6, 0x6, 0, 0},
- {0x99, 0xa0, 0xa0, 0, 0},
- {0x9A, 0xa, 0xa, 0, 0},
- {0x9B, 0x87, 0x87, 1, 1},
- {0x9C, 0x2a, 0x2a, 0, 0},
- {0x9D, 0x2a, 0x2a, 0, 0},
- {0x9E, 0x2a, 0x2a, 0, 0},
- {0x9F, 0x2a, 0x2a, 0, 0},
- {0xA0, 0x18, 0x18, 0, 0},
- {0xA1, 0x6a, 0x6a, 1, 1},
- {0xA2, 0xab, 0xab, 1, 1},
- {0xA3, 0x13, 0x13, 1, 1},
- {0xA4, 0xc1, 0xc1, 1, 1},
- {0xA5, 0xaa, 0xaa, 1, 1},
- {0xA6, 0x87, 0x87, 1, 1},
- {0xA7, 0, 0, 0, 0},
- {0xA8, 0x6, 0x6, 0, 0},
- {0xA9, 0x7, 0x7, 0, 0},
- {0xAA, 0x7, 0x7, 0, 0},
- {0xAB, 0x15, 0x15, 0, 0},
- {0xAC, 0x55, 0x55, 0, 0},
- {0xAD, 0x97, 0x97, 1, 1},
- {0xAE, 0x8, 0x8, 0, 0},
- {0xAF, 0x14, 0x14, 1, 1},
- {0xB0, 0x33, 0x33, 0, 0},
- {0xB1, 0x88, 0x88, 0, 0},
- {0xB2, 0x6, 0x6, 0, 0},
- {0xB3, 0x3, 0x3, 1, 1},
- {0xB4, 0xa, 0xa, 0, 0},
- {0xB5, 0x3, 0x3, 1, 1},
- {0xB6, 0x2a, 0x2a, 0, 0},
- {0xB7, 0xa4, 0xa4, 0, 0},
- {0xB8, 0x18, 0x18, 0, 0},
- {0xB9, 0x28, 0x28, 0, 0},
- {0xBA, 0, 0, 0, 0},
- {0xBB, 0x4a, 0x4a, 0, 0},
- {0xBC, 0, 0, 0, 0},
- {0xBD, 0x71, 0x71, 0, 0},
- {0xBE, 0x72, 0x72, 0, 0},
- {0xBF, 0x73, 0x73, 0, 0},
- {0xC0, 0x74, 0x74, 0, 0},
- {0xC1, 0x75, 0x75, 0, 0},
- {0xC2, 0x76, 0x76, 0, 0},
- {0xC3, 0x77, 0x77, 0, 0},
- {0xC4, 0x78, 0x78, 0, 0},
- {0xC5, 0x79, 0x79, 0, 0},
- {0xC6, 0x7a, 0x7a, 0, 0},
- {0xC7, 0, 0, 0, 0},
- {0xC8, 0, 0, 0, 0},
- {0xC9, 0, 0, 0, 0},
- {0xCA, 0, 0, 0, 0},
- {0xCB, 0, 0, 0, 0},
- {0xCC, 0, 0, 0, 0},
- {0xCD, 0, 0, 0, 0},
- {0xCE, 0x6, 0x6, 0, 0},
- {0xCF, 0, 0, 0, 0},
- {0xD0, 0, 0, 0, 0},
- {0xD1, 0x18, 0x18, 0, 0},
- {0xD2, 0x88, 0x88, 0, 0},
- {0xD3, 0, 0, 0, 0},
- {0xD4, 0, 0, 0, 0},
- {0xD5, 0, 0, 0, 0},
- {0xD6, 0, 0, 0, 0},
- {0xD7, 0, 0, 0, 0},
- {0xD8, 0, 0, 0, 0},
- {0xD9, 0, 0, 0, 0},
- {0xDA, 0x6, 0x6, 0, 0},
- {0xDB, 0, 0, 0, 0},
- {0xDC, 0, 0, 0, 0},
- {0xDD, 0x18, 0x18, 0, 0},
- {0xDE, 0x88, 0x88, 0, 0},
- {0xDF, 0, 0, 0, 0},
- {0xE0, 0, 0, 0, 0},
- {0xE1, 0, 0, 0, 0},
- {0xE2, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_SYN_2056[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0x1, 0x1, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0x60, 0x60, 0, 0},
- {0x23, 0x6, 0x6, 0, 0},
- {0x24, 0xc, 0xc, 0, 0},
- {0x25, 0, 0, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0, 0, 0, 0},
- {0x28, 0x1, 0x1, 0, 0},
- {0x29, 0, 0, 0, 0},
- {0x2A, 0, 0, 0, 0},
- {0x2B, 0, 0, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0xd, 0xd, 0, 0},
- {0x2F, 0x1f, 0x1f, 0, 0},
- {0x30, 0x15, 0x15, 0, 0},
- {0x31, 0xf, 0xf, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0, 0, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0, 0, 0, 0},
- {0x38, 0, 0, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0, 0, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x13, 0x13, 0, 0},
- {0x3D, 0xf, 0xf, 0, 0},
- {0x3E, 0x18, 0x18, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x20, 0x20, 0, 0},
- {0x42, 0x20, 0x20, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x77, 0x77, 0, 0},
- {0x45, 0x7, 0x7, 0, 0},
- {0x46, 0x1, 0x1, 0, 0},
- {0x47, 0x4, 0x4, 0, 0},
- {0x48, 0xf, 0xf, 0, 0},
- {0x49, 0x30, 0x30, 0, 0},
- {0x4A, 0x32, 0x32, 0, 0},
- {0x4B, 0xd, 0xd, 0, 0},
- {0x4C, 0xd, 0xd, 0, 0},
- {0x4D, 0x4, 0x4, 0, 0},
- {0x4E, 0x6, 0x6, 0, 0},
- {0x4F, 0x1, 0x1, 0, 0},
- {0x50, 0x1c, 0x1c, 0, 0},
- {0x51, 0x2, 0x2, 0, 0},
- {0x52, 0x2, 0x2, 0, 0},
- {0x53, 0xf7, 0xf7, 1, 1},
- {0x54, 0xb4, 0xb4, 0, 0},
- {0x55, 0xd2, 0xd2, 0, 0},
- {0x56, 0, 0, 0, 0},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x4, 0x4, 0, 0},
- {0x59, 0x96, 0x96, 0, 0},
- {0x5A, 0x3e, 0x3e, 0, 0},
- {0x5B, 0x3e, 0x3e, 0, 0},
- {0x5C, 0x13, 0x13, 0, 0},
- {0x5D, 0x2, 0x2, 0, 0},
- {0x5E, 0, 0, 0, 0},
- {0x5F, 0x7, 0x7, 0, 0},
- {0x60, 0x7, 0x7, 1, 1},
- {0x61, 0x8, 0x8, 0, 0},
- {0x62, 0x3, 0x3, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0x40, 0x40, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0x1, 0x1, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0x60, 0x60, 0, 0},
- {0x71, 0x66, 0x66, 0, 0},
- {0x72, 0xc, 0xc, 0, 0},
- {0x73, 0x66, 0x66, 0, 0},
- {0x74, 0x8f, 0x8f, 1, 1},
- {0x75, 0, 0, 0, 0},
- {0x76, 0xcc, 0xcc, 0, 0},
- {0x77, 0x1, 0x1, 0, 0},
- {0x78, 0x66, 0x66, 0, 0},
- {0x79, 0x66, 0x66, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0xff, 0xff, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0x95, 0, 0, 0, 0},
- {0x96, 0, 0, 0, 0},
- {0x97, 0, 0, 0, 0},
- {0x98, 0, 0, 0, 0},
- {0x99, 0, 0, 0, 0},
- {0x9A, 0, 0, 0, 0},
- {0x9B, 0, 0, 0, 0},
- {0x9C, 0, 0, 0, 0},
- {0x9D, 0, 0, 0, 0},
- {0x9E, 0, 0, 0, 0},
- {0x9F, 0x6, 0x6, 0, 0},
- {0xA0, 0x66, 0x66, 0, 0},
- {0xA1, 0x66, 0x66, 0, 0},
- {0xA2, 0x66, 0x66, 0, 0},
- {0xA3, 0x66, 0x66, 0, 0},
- {0xA4, 0x66, 0x66, 0, 0},
- {0xA5, 0x66, 0x66, 0, 0},
- {0xA6, 0x66, 0x66, 0, 0},
- {0xA7, 0x66, 0x66, 0, 0},
- {0xA8, 0x66, 0x66, 0, 0},
- {0xA9, 0x66, 0x66, 0, 0},
- {0xAA, 0x66, 0x66, 0, 0},
- {0xAB, 0x66, 0x66, 0, 0},
- {0xAC, 0x66, 0x66, 0, 0},
- {0xAD, 0x66, 0x66, 0, 0},
- {0xAE, 0x66, 0x66, 0, 0},
- {0xAF, 0x66, 0x66, 0, 0},
- {0xB0, 0x66, 0x66, 0, 0},
- {0xB1, 0x66, 0x66, 0, 0},
- {0xB2, 0x66, 0x66, 0, 0},
- {0xB3, 0xa, 0xa, 0, 0},
- {0xB4, 0, 0, 0, 0},
- {0xB5, 0, 0, 0, 0},
- {0xB6, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_TX_2056[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0x88, 0x88, 0, 0},
- {0x22, 0x88, 0x88, 0, 0},
- {0x23, 0x88, 0x88, 0, 0},
- {0x24, 0x88, 0x88, 0, 0},
- {0x25, 0xc, 0xc, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0x3, 0x3, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0x3, 0x3, 0, 0},
- {0x2A, 0x37, 0x37, 0, 0},
- {0x2B, 0x3, 0x3, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0x1, 0x1, 0, 0},
- {0x2F, 0x1, 0x1, 0, 0},
- {0x30, 0, 0, 0, 0},
- {0x31, 0, 0, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0x11, 0x11, 0, 0},
- {0x34, 0x11, 0x11, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0x3, 0x3, 0, 0},
- {0x38, 0xf, 0xf, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0x2d, 0x2d, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x6e, 0x6e, 0, 0},
- {0x3D, 0xf0, 0xf0, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x3, 0x3, 0, 0},
- {0x42, 0x3, 0x3, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x1e, 0x1e, 0, 0},
- {0x45, 0, 0, 0, 0},
- {0x46, 0x6e, 0x6e, 0, 0},
- {0x47, 0xf0, 0xf0, 1, 1},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x2, 0x2, 0, 0},
- {0x4A, 0xff, 0xff, 1, 1},
- {0x4B, 0xc, 0xc, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0x38, 0x38, 0, 0},
- {0x4E, 0x70, 0x70, 1, 1},
- {0x4F, 0x2, 0x2, 0, 0},
- {0x50, 0x88, 0x88, 0, 0},
- {0x51, 0xc, 0xc, 0, 0},
- {0x52, 0, 0, 0, 0},
- {0x53, 0x8, 0x8, 0, 0},
- {0x54, 0x70, 0x70, 1, 1},
- {0x55, 0x2, 0x2, 0, 0},
- {0x56, 0xff, 0xff, 1, 1},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x83, 0x83, 0, 0},
- {0x59, 0x77, 0x77, 1, 1},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x88, 0x88, 0, 0},
- {0x5D, 0, 0, 0, 0},
- {0x5E, 0x8, 0x8, 0, 0},
- {0x5F, 0x77, 0x77, 1, 1},
- {0x60, 0x1, 0x1, 0, 0},
- {0x61, 0, 0, 0, 0},
- {0x62, 0x7, 0x7, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0x7, 0x7, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0x74, 0x74, 1, 1},
- {0x68, 0, 0, 0, 0},
- {0x69, 0xa, 0xa, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0x2, 0x2, 0, 0},
- {0x72, 0, 0, 0, 0},
- {0x73, 0, 0, 0, 0},
- {0x74, 0xe, 0xe, 0, 0},
- {0x75, 0xe, 0xe, 0, 0},
- {0x76, 0xe, 0xe, 0, 0},
- {0x77, 0x13, 0x13, 0, 0},
- {0x78, 0x13, 0x13, 0, 0},
- {0x79, 0x1b, 0x1b, 0, 0},
- {0x7A, 0x1b, 0x1b, 0, 0},
- {0x7B, 0x55, 0x55, 0, 0},
- {0x7C, 0x5b, 0x5b, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_RX_2056[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0x3, 0x3, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0, 0, 0, 0},
- {0x23, 0x90, 0x90, 0, 0},
- {0x24, 0x55, 0x55, 0, 0},
- {0x25, 0x15, 0x15, 0, 0},
- {0x26, 0x5, 0x5, 0, 0},
- {0x27, 0x15, 0x15, 0, 0},
- {0x28, 0x5, 0x5, 0, 0},
- {0x29, 0x20, 0x20, 0, 0},
- {0x2A, 0x11, 0x11, 0, 0},
- {0x2B, 0x90, 0x90, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0x88, 0x88, 0, 0},
- {0x2E, 0x32, 0x32, 0, 0},
- {0x2F, 0x77, 0x77, 0, 0},
- {0x30, 0x17, 0x17, 1, 1},
- {0x31, 0xff, 0xff, 1, 1},
- {0x32, 0x20, 0x20, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0x88, 0x88, 0, 0},
- {0x35, 0x32, 0x32, 0, 0},
- {0x36, 0x77, 0x77, 0, 0},
- {0x37, 0x17, 0x17, 1, 1},
- {0x38, 0xf0, 0xf0, 1, 1},
- {0x39, 0x20, 0x20, 0, 0},
- {0x3A, 0x8, 0x8, 0, 0},
- {0x3B, 0x99, 0x99, 0, 0},
- {0x3C, 0, 0, 0, 0},
- {0x3D, 0x44, 0x44, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0x44, 0x44, 0, 0},
- {0x40, 0xf, 0xf, 1, 1},
- {0x41, 0x6, 0x6, 0, 0},
- {0x42, 0x4, 0x4, 0, 0},
- {0x43, 0x50, 0x50, 1, 1},
- {0x44, 0x8, 0x8, 0, 0},
- {0x45, 0x99, 0x99, 0, 0},
- {0x46, 0, 0, 0, 0},
- {0x47, 0x11, 0x11, 0, 0},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x44, 0x44, 0, 0},
- {0x4A, 0x7, 0x7, 0, 0},
- {0x4B, 0x6, 0x6, 0, 0},
- {0x4C, 0x4, 0x4, 0, 0},
- {0x4D, 0, 0, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0x66, 0x66, 0, 0},
- {0x50, 0x66, 0x66, 0, 0},
- {0x51, 0x57, 0x57, 0, 0},
- {0x52, 0x57, 0x57, 0, 0},
- {0x53, 0x44, 0x44, 0, 0},
- {0x54, 0, 0, 0, 0},
- {0x55, 0, 0, 0, 0},
- {0x56, 0x8, 0x8, 0, 0},
- {0x57, 0x8, 0x8, 0, 0},
- {0x58, 0x7, 0x7, 0, 0},
- {0x59, 0x22, 0x22, 0, 0},
- {0x5A, 0x22, 0x22, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x23, 0x23, 0, 0},
- {0x5D, 0x7, 0x7, 0, 0},
- {0x5E, 0x55, 0x55, 0, 0},
- {0x5F, 0x23, 0x23, 0, 0},
- {0x60, 0x41, 0x41, 0, 0},
- {0x61, 0x1, 0x1, 0, 0},
- {0x62, 0xa, 0xa, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0, 0, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0xc, 0xc, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0, 0, 0, 0},
- {0x72, 0x22, 0x22, 0, 0},
- {0x73, 0x22, 0x22, 0, 0},
- {0x74, 0x2, 0x2, 0, 0},
- {0x75, 0xa, 0xa, 0, 0},
- {0x76, 0x1, 0x1, 0, 0},
- {0x77, 0x22, 0x22, 0, 0},
- {0x78, 0x30, 0x30, 0, 0},
- {0x79, 0, 0, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_SYN_2056_A1[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0x1, 0x1, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0x60, 0x60, 0, 0},
- {0x23, 0x6, 0x6, 0, 0},
- {0x24, 0xc, 0xc, 0, 0},
- {0x25, 0, 0, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0, 0, 0, 0},
- {0x28, 0x1, 0x1, 0, 0},
- {0x29, 0, 0, 0, 0},
- {0x2A, 0, 0, 0, 0},
- {0x2B, 0, 0, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0xd, 0xd, 0, 0},
- {0x2F, 0x1f, 0x1f, 0, 0},
- {0x30, 0x15, 0x15, 0, 0},
- {0x31, 0xf, 0xf, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0, 0, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0, 0, 0, 0},
- {0x38, 0, 0, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0, 0, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x13, 0x13, 0, 0},
- {0x3D, 0xf, 0xf, 0, 0},
- {0x3E, 0x18, 0x18, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x20, 0x20, 0, 0},
- {0x42, 0x20, 0x20, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x77, 0x77, 0, 0},
- {0x45, 0x7, 0x7, 0, 0},
- {0x46, 0x1, 0x1, 0, 0},
- {0x47, 0x4, 0x4, 0, 0},
- {0x48, 0xf, 0xf, 0, 0},
- {0x49, 0x30, 0x30, 0, 0},
- {0x4A, 0x32, 0x32, 0, 0},
- {0x4B, 0xd, 0xd, 0, 0},
- {0x4C, 0xd, 0xd, 0, 0},
- {0x4D, 0x4, 0x4, 0, 0},
- {0x4E, 0x6, 0x6, 0, 0},
- {0x4F, 0x1, 0x1, 0, 0},
- {0x50, 0x1c, 0x1c, 0, 0},
- {0x51, 0x2, 0x2, 0, 0},
- {0x52, 0x2, 0x2, 0, 0},
- {0x53, 0xf7, 0xf7, 1, 1},
- {0x54, 0xb4, 0xb4, 0, 0},
- {0x55, 0xd2, 0xd2, 0, 0},
- {0x56, 0, 0, 0, 0},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x4, 0x4, 0, 0},
- {0x59, 0x96, 0x96, 0, 0},
- {0x5A, 0x3e, 0x3e, 0, 0},
- {0x5B, 0x3e, 0x3e, 0, 0},
- {0x5C, 0x13, 0x13, 0, 0},
- {0x5D, 0x2, 0x2, 0, 0},
- {0x5E, 0, 0, 0, 0},
- {0x5F, 0x7, 0x7, 0, 0},
- {0x60, 0x7, 0x7, 1, 1},
- {0x61, 0x8, 0x8, 0, 0},
- {0x62, 0x3, 0x3, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0x40, 0x40, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0x1, 0x1, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0x60, 0x60, 0, 0},
- {0x71, 0x66, 0x66, 0, 0},
- {0x72, 0xc, 0xc, 0, 0},
- {0x73, 0x66, 0x66, 0, 0},
- {0x74, 0x8f, 0x8f, 1, 1},
- {0x75, 0, 0, 0, 0},
- {0x76, 0xcc, 0xcc, 0, 0},
- {0x77, 0x1, 0x1, 0, 0},
- {0x78, 0x66, 0x66, 0, 0},
- {0x79, 0x66, 0x66, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0xff, 0xff, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0x95, 0, 0, 0, 0},
- {0x96, 0, 0, 0, 0},
- {0x97, 0, 0, 0, 0},
- {0x98, 0, 0, 0, 0},
- {0x99, 0, 0, 0, 0},
- {0x9A, 0, 0, 0, 0},
- {0x9B, 0, 0, 0, 0},
- {0x9C, 0, 0, 0, 0},
- {0x9D, 0, 0, 0, 0},
- {0x9E, 0, 0, 0, 0},
- {0x9F, 0x6, 0x6, 0, 0},
- {0xA0, 0x66, 0x66, 0, 0},
- {0xA1, 0x66, 0x66, 0, 0},
- {0xA2, 0x66, 0x66, 0, 0},
- {0xA3, 0x66, 0x66, 0, 0},
- {0xA4, 0x66, 0x66, 0, 0},
- {0xA5, 0x66, 0x66, 0, 0},
- {0xA6, 0x66, 0x66, 0, 0},
- {0xA7, 0x66, 0x66, 0, 0},
- {0xA8, 0x66, 0x66, 0, 0},
- {0xA9, 0x66, 0x66, 0, 0},
- {0xAA, 0x66, 0x66, 0, 0},
- {0xAB, 0x66, 0x66, 0, 0},
- {0xAC, 0x66, 0x66, 0, 0},
- {0xAD, 0x66, 0x66, 0, 0},
- {0xAE, 0x66, 0x66, 0, 0},
- {0xAF, 0x66, 0x66, 0, 0},
- {0xB0, 0x66, 0x66, 0, 0},
- {0xB1, 0x66, 0x66, 0, 0},
- {0xB2, 0x66, 0x66, 0, 0},
- {0xB3, 0xa, 0xa, 0, 0},
- {0xB4, 0, 0, 0, 0},
- {0xB5, 0, 0, 0, 0},
- {0xB6, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_TX_2056_A1[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0x88, 0x88, 0, 0},
- {0x22, 0x88, 0x88, 0, 0},
- {0x23, 0x88, 0x88, 0, 0},
- {0x24, 0x88, 0x88, 0, 0},
- {0x25, 0xc, 0xc, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0x3, 0x3, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0x3, 0x3, 0, 0},
- {0x2A, 0x37, 0x37, 0, 0},
- {0x2B, 0x3, 0x3, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0x1, 0x1, 0, 0},
- {0x2F, 0x1, 0x1, 0, 0},
- {0x30, 0, 0, 0, 0},
- {0x31, 0, 0, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0x11, 0x11, 0, 0},
- {0x34, 0x11, 0x11, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0x3, 0x3, 0, 0},
- {0x38, 0xf, 0xf, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0x2d, 0x2d, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x6e, 0x6e, 0, 0},
- {0x3D, 0xf0, 0xf0, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x3, 0x3, 0, 0},
- {0x42, 0x3, 0x3, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x1e, 0x1e, 0, 0},
- {0x45, 0, 0, 0, 0},
- {0x46, 0x6e, 0x6e, 0, 0},
- {0x47, 0xf0, 0xf0, 1, 1},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x2, 0x2, 0, 0},
- {0x4A, 0xff, 0xff, 1, 1},
- {0x4B, 0xc, 0xc, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0x38, 0x38, 0, 0},
- {0x4E, 0x70, 0x70, 1, 1},
- {0x4F, 0x2, 0x2, 0, 0},
- {0x50, 0x88, 0x88, 0, 0},
- {0x51, 0xc, 0xc, 0, 0},
- {0x52, 0, 0, 0, 0},
- {0x53, 0x8, 0x8, 0, 0},
- {0x54, 0x70, 0x70, 1, 1},
- {0x55, 0x2, 0x2, 0, 0},
- {0x56, 0xff, 0xff, 1, 1},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x83, 0x83, 0, 0},
- {0x59, 0x77, 0x77, 1, 1},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x88, 0x88, 0, 0},
- {0x5D, 0, 0, 0, 0},
- {0x5E, 0x8, 0x8, 0, 0},
- {0x5F, 0x77, 0x77, 1, 1},
- {0x60, 0x1, 0x1, 0, 0},
- {0x61, 0, 0, 0, 0},
- {0x62, 0x7, 0x7, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0x7, 0x7, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0x72, 0x72, 1, 1},
- {0x68, 0, 0, 0, 0},
- {0x69, 0xa, 0xa, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0x2, 0x2, 0, 0},
- {0x72, 0, 0, 0, 0},
- {0x73, 0, 0, 0, 0},
- {0x74, 0xe, 0xe, 0, 0},
- {0x75, 0xe, 0xe, 0, 0},
- {0x76, 0xe, 0xe, 0, 0},
- {0x77, 0x13, 0x13, 0, 0},
- {0x78, 0x13, 0x13, 0, 0},
- {0x79, 0x1b, 0x1b, 0, 0},
- {0x7A, 0x1b, 0x1b, 0, 0},
- {0x7B, 0x55, 0x55, 0, 0},
- {0x7C, 0x5b, 0x5b, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_RX_2056_A1[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0x3, 0x3, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0, 0, 0, 0},
- {0x23, 0x90, 0x90, 0, 0},
- {0x24, 0x55, 0x55, 0, 0},
- {0x25, 0x15, 0x15, 0, 0},
- {0x26, 0x5, 0x5, 0, 0},
- {0x27, 0x15, 0x15, 0, 0},
- {0x28, 0x5, 0x5, 0, 0},
- {0x29, 0x20, 0x20, 0, 0},
- {0x2A, 0x11, 0x11, 0, 0},
- {0x2B, 0x90, 0x90, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0x88, 0x88, 0, 0},
- {0x2E, 0x32, 0x32, 0, 0},
- {0x2F, 0x77, 0x77, 0, 0},
- {0x30, 0x17, 0x17, 1, 1},
- {0x31, 0xff, 0xff, 1, 1},
- {0x32, 0x20, 0x20, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0x88, 0x88, 0, 0},
- {0x35, 0x32, 0x32, 0, 0},
- {0x36, 0x77, 0x77, 0, 0},
- {0x37, 0x17, 0x17, 1, 1},
- {0x38, 0xf0, 0xf0, 1, 1},
- {0x39, 0x20, 0x20, 0, 0},
- {0x3A, 0x8, 0x8, 0, 0},
- {0x3B, 0x55, 0x55, 1, 1},
- {0x3C, 0, 0, 0, 0},
- {0x3D, 0x44, 0x44, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0x44, 0x44, 0, 0},
- {0x40, 0xf, 0xf, 1, 1},
- {0x41, 0x6, 0x6, 0, 0},
- {0x42, 0x4, 0x4, 0, 0},
- {0x43, 0x50, 0x50, 1, 1},
- {0x44, 0x8, 0x8, 0, 0},
- {0x45, 0x55, 0x55, 1, 1},
- {0x46, 0, 0, 0, 0},
- {0x47, 0x11, 0x11, 0, 0},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x44, 0x44, 0, 0},
- {0x4A, 0x7, 0x7, 0, 0},
- {0x4B, 0x6, 0x6, 0, 0},
- {0x4C, 0x4, 0x4, 0, 0},
- {0x4D, 0, 0, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0x26, 0x26, 1, 1},
- {0x50, 0x26, 0x26, 1, 1},
- {0x51, 0xf, 0xf, 1, 1},
- {0x52, 0xf, 0xf, 1, 1},
- {0x53, 0x44, 0x44, 0, 0},
- {0x54, 0, 0, 0, 0},
- {0x55, 0, 0, 0, 0},
- {0x56, 0x8, 0x8, 0, 0},
- {0x57, 0x8, 0x8, 0, 0},
- {0x58, 0x7, 0x7, 0, 0},
- {0x59, 0x22, 0x22, 0, 0},
- {0x5A, 0x22, 0x22, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x2f, 0x2f, 1, 1},
- {0x5D, 0x7, 0x7, 0, 0},
- {0x5E, 0x55, 0x55, 0, 0},
- {0x5F, 0x23, 0x23, 0, 0},
- {0x60, 0x41, 0x41, 0, 0},
- {0x61, 0x1, 0x1, 0, 0},
- {0x62, 0xa, 0xa, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0, 0, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0xc, 0xc, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0, 0, 0, 0},
- {0x72, 0x22, 0x22, 0, 0},
- {0x73, 0x22, 0x22, 0, 0},
- {0x74, 0, 0, 1, 1},
- {0x75, 0xa, 0xa, 0, 0},
- {0x76, 0x1, 0x1, 0, 0},
- {0x77, 0x22, 0x22, 0, 0},
- {0x78, 0x30, 0x30, 0, 0},
- {0x79, 0, 0, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_SYN_2056_rev5[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0x1, 0x1, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0x60, 0x60, 0, 0},
- {0x23, 0x6, 0x6, 0, 0},
- {0x24, 0xc, 0xc, 0, 0},
- {0x25, 0, 0, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0, 0, 0, 0},
- {0x28, 0x1, 0x1, 0, 0},
- {0x29, 0, 0, 0, 0},
- {0x2A, 0, 0, 0, 0},
- {0x2B, 0, 0, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0, 0, 0, 0},
- {0x2F, 0x1f, 0x1f, 0, 0},
- {0x30, 0x15, 0x15, 0, 0},
- {0x31, 0xf, 0xf, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0, 0, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0, 0, 0, 0},
- {0x38, 0, 0, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0, 0, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x13, 0x13, 0, 0},
- {0x3D, 0xf, 0xf, 0, 0},
- {0x3E, 0x18, 0x18, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x20, 0x20, 0, 0},
- {0x42, 0x20, 0x20, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x77, 0x77, 0, 0},
- {0x45, 0x7, 0x7, 0, 0},
- {0x46, 0x1, 0x1, 0, 0},
- {0x47, 0x4, 0x4, 0, 0},
- {0x48, 0xf, 0xf, 0, 0},
- {0x49, 0x30, 0x30, 0, 0},
- {0x4A, 0x32, 0x32, 0, 0},
- {0x4B, 0xd, 0xd, 0, 0},
- {0x4C, 0xd, 0xd, 0, 0},
- {0x4D, 0x4, 0x4, 0, 0},
- {0x4E, 0x6, 0x6, 0, 0},
- {0x4F, 0x1, 0x1, 0, 0},
- {0x50, 0x1c, 0x1c, 0, 0},
- {0x51, 0x2, 0x2, 0, 0},
- {0x52, 0x2, 0x2, 0, 0},
- {0x53, 0xf7, 0xf7, 1, 1},
- {0x54, 0xb4, 0xb4, 0, 0},
- {0x55, 0xd2, 0xd2, 0, 0},
- {0x56, 0, 0, 0, 0},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x4, 0x4, 0, 0},
- {0x59, 0x96, 0x96, 0, 0},
- {0x5A, 0x3e, 0x3e, 0, 0},
- {0x5B, 0x3e, 0x3e, 0, 0},
- {0x5C, 0x13, 0x13, 0, 0},
- {0x5D, 0x2, 0x2, 0, 0},
- {0x5E, 0, 0, 0, 0},
- {0x5F, 0x7, 0x7, 0, 0},
- {0x60, 0x7, 0x7, 1, 1},
- {0x61, 0x8, 0x8, 0, 0},
- {0x62, 0x3, 0x3, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0x40, 0x40, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0x1, 0x1, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0x60, 0x60, 0, 0},
- {0x71, 0x66, 0x66, 0, 0},
- {0x72, 0xc, 0xc, 0, 0},
- {0x73, 0x66, 0x66, 0, 0},
- {0x74, 0x8f, 0x8f, 1, 1},
- {0x75, 0, 0, 0, 0},
- {0x76, 0xcc, 0xcc, 0, 0},
- {0x77, 0x1, 0x1, 0, 0},
- {0x78, 0x66, 0x66, 0, 0},
- {0x79, 0x66, 0x66, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0xff, 0xff, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0x95, 0, 0, 0, 0},
- {0x96, 0, 0, 0, 0},
- {0x97, 0, 0, 0, 0},
- {0x98, 0, 0, 0, 0},
- {0x99, 0, 0, 0, 0},
- {0x9A, 0, 0, 0, 0},
- {0x9B, 0, 0, 0, 0},
- {0x9C, 0, 0, 0, 0},
- {0x9D, 0, 0, 0, 0},
- {0x9E, 0, 0, 0, 0},
- {0x9F, 0x6, 0x6, 0, 0},
- {0xA0, 0x66, 0x66, 0, 0},
- {0xA1, 0x66, 0x66, 0, 0},
- {0xA2, 0x66, 0x66, 0, 0},
- {0xA3, 0x66, 0x66, 0, 0},
- {0xA4, 0x66, 0x66, 0, 0},
- {0xA5, 0x66, 0x66, 0, 0},
- {0xA6, 0x66, 0x66, 0, 0},
- {0xA7, 0x66, 0x66, 0, 0},
- {0xA8, 0x66, 0x66, 0, 0},
- {0xA9, 0x66, 0x66, 0, 0},
- {0xAA, 0x66, 0x66, 0, 0},
- {0xAB, 0x66, 0x66, 0, 0},
- {0xAC, 0x66, 0x66, 0, 0},
- {0xAD, 0x66, 0x66, 0, 0},
- {0xAE, 0x66, 0x66, 0, 0},
- {0xAF, 0x66, 0x66, 0, 0},
- {0xB0, 0x66, 0x66, 0, 0},
- {0xB1, 0x66, 0x66, 0, 0},
- {0xB2, 0x66, 0x66, 0, 0},
- {0xB3, 0xa, 0xa, 0, 0},
- {0xB4, 0, 0, 0, 0},
- {0xB5, 0, 0, 0, 0},
- {0xB6, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_TX_2056_rev5[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0x88, 0x88, 0, 0},
- {0x22, 0x88, 0x88, 0, 0},
- {0x23, 0x88, 0x88, 0, 0},
- {0x24, 0x88, 0x88, 0, 0},
- {0x25, 0xc, 0xc, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0x3, 0x3, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0x3, 0x3, 0, 0},
- {0x2A, 0x37, 0x37, 0, 0},
- {0x2B, 0x3, 0x3, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0x1, 0x1, 0, 0},
- {0x2F, 0x1, 0x1, 0, 0},
- {0x30, 0, 0, 0, 0},
- {0x31, 0, 0, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0x11, 0x11, 0, 0},
- {0x34, 0x11, 0x11, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0x3, 0x3, 0, 0},
- {0x38, 0xf, 0xf, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0x2d, 0x2d, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x6e, 0x6e, 0, 0},
- {0x3D, 0xf0, 0xf0, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x3, 0x3, 0, 0},
- {0x42, 0x3, 0x3, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x1e, 0x1e, 0, 0},
- {0x45, 0, 0, 0, 0},
- {0x46, 0x6e, 0x6e, 0, 0},
- {0x47, 0xf0, 0xf0, 1, 1},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x2, 0x2, 0, 0},
- {0x4A, 0xff, 0xff, 1, 1},
- {0x4B, 0xc, 0xc, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0x38, 0x38, 0, 0},
- {0x4E, 0x70, 0x70, 1, 1},
- {0x4F, 0x2, 0x2, 0, 0},
- {0x50, 0x88, 0x88, 0, 0},
- {0x51, 0xc, 0xc, 0, 0},
- {0x52, 0, 0, 0, 0},
- {0x53, 0x8, 0x8, 0, 0},
- {0x54, 0x70, 0x70, 1, 1},
- {0x55, 0x2, 0x2, 0, 0},
- {0x56, 0xff, 0xff, 1, 1},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x83, 0x83, 0, 0},
- {0x59, 0x77, 0x77, 1, 1},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x88, 0x88, 0, 0},
- {0x5D, 0, 0, 0, 0},
- {0x5E, 0x8, 0x8, 0, 0},
- {0x5F, 0x77, 0x77, 1, 1},
- {0x60, 0x1, 0x1, 0, 0},
- {0x61, 0, 0, 0, 0},
- {0x62, 0x7, 0x7, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0x7, 0x7, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 1, 1},
- {0x68, 0, 0, 0, 0},
- {0x69, 0xa, 0xa, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0x2, 0x2, 0, 0},
- {0x72, 0, 0, 0, 0},
- {0x73, 0, 0, 0, 0},
- {0x74, 0xe, 0xe, 0, 0},
- {0x75, 0xe, 0xe, 0, 0},
- {0x76, 0xe, 0xe, 0, 0},
- {0x77, 0x13, 0x13, 0, 0},
- {0x78, 0x13, 0x13, 0, 0},
- {0x79, 0x1b, 0x1b, 0, 0},
- {0x7A, 0x1b, 0x1b, 0, 0},
- {0x7B, 0x55, 0x55, 0, 0},
- {0x7C, 0x5b, 0x5b, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0x70, 0x70, 0, 0},
- {0x94, 0x70, 0x70, 0, 0},
- {0x95, 0x71, 0x71, 1, 1},
- {0x96, 0x71, 0x71, 1, 1},
- {0x97, 0x72, 0x72, 1, 1},
- {0x98, 0x73, 0x73, 1, 1},
- {0x99, 0x74, 0x74, 1, 1},
- {0x9A, 0x75, 0x75, 1, 1},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_RX_2056_rev5[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0x3, 0x3, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0, 0, 0, 0},
- {0x23, 0x90, 0x90, 0, 0},
- {0x24, 0x55, 0x55, 0, 0},
- {0x25, 0x15, 0x15, 0, 0},
- {0x26, 0x5, 0x5, 0, 0},
- {0x27, 0x15, 0x15, 0, 0},
- {0x28, 0x5, 0x5, 0, 0},
- {0x29, 0x20, 0x20, 0, 0},
- {0x2A, 0x11, 0x11, 0, 0},
- {0x2B, 0x90, 0x90, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0x88, 0x88, 0, 0},
- {0x2E, 0x32, 0x32, 0, 0},
- {0x2F, 0x77, 0x77, 0, 0},
- {0x30, 0x17, 0x17, 1, 1},
- {0x31, 0xff, 0xff, 1, 1},
- {0x32, 0x20, 0x20, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0x88, 0x88, 0, 0},
- {0x35, 0x32, 0x32, 0, 0},
- {0x36, 0x77, 0x77, 0, 0},
- {0x37, 0x17, 0x17, 1, 1},
- {0x38, 0xf0, 0xf0, 1, 1},
- {0x39, 0x20, 0x20, 0, 0},
- {0x3A, 0x8, 0x8, 0, 0},
- {0x3B, 0x55, 0x55, 1, 1},
- {0x3C, 0, 0, 0, 0},
- {0x3D, 0x88, 0x88, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 1, 1},
- {0x40, 0x7, 0x7, 1, 1},
- {0x41, 0x6, 0x6, 0, 0},
- {0x42, 0x4, 0x4, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x8, 0x8, 0, 0},
- {0x45, 0x55, 0x55, 1, 1},
- {0x46, 0, 0, 0, 0},
- {0x47, 0x11, 0x11, 0, 0},
- {0x48, 0, 0, 0, 0},
- {0x49, 0, 0, 1, 1},
- {0x4A, 0x7, 0x7, 0, 0},
- {0x4B, 0x6, 0x6, 0, 0},
- {0x4C, 0x4, 0x4, 0, 0},
- {0x4D, 0, 0, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0x26, 0x26, 1, 1},
- {0x50, 0x26, 0x26, 1, 1},
- {0x51, 0xf, 0xf, 1, 1},
- {0x52, 0xf, 0xf, 1, 1},
- {0x53, 0x44, 0x44, 0, 0},
- {0x54, 0, 0, 0, 0},
- {0x55, 0, 0, 0, 0},
- {0x56, 0x8, 0x8, 0, 0},
- {0x57, 0x8, 0x8, 0, 0},
- {0x58, 0x7, 0x7, 0, 0},
- {0x59, 0x22, 0x22, 0, 0},
- {0x5A, 0x22, 0x22, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x4, 0x4, 1, 1},
- {0x5D, 0x7, 0x7, 0, 0},
- {0x5E, 0x55, 0x55, 0, 0},
- {0x5F, 0x23, 0x23, 0, 0},
- {0x60, 0x41, 0x41, 0, 0},
- {0x61, 0x1, 0x1, 0, 0},
- {0x62, 0xa, 0xa, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0, 0, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0xc, 0xc, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0, 0, 0, 0},
- {0x72, 0x22, 0x22, 0, 0},
- {0x73, 0x22, 0x22, 0, 0},
- {0x74, 0, 0, 1, 1},
- {0x75, 0xa, 0xa, 0, 0},
- {0x76, 0x1, 0x1, 0, 0},
- {0x77, 0x22, 0x22, 0, 0},
- {0x78, 0x30, 0x30, 0, 0},
- {0x79, 0, 0, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_SYN_2056_rev6[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0x1, 0x1, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0x60, 0x60, 0, 0},
- {0x23, 0x6, 0x6, 0, 0},
- {0x24, 0xc, 0xc, 0, 0},
- {0x25, 0, 0, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0, 0, 0, 0},
- {0x28, 0x1, 0x1, 0, 0},
- {0x29, 0, 0, 0, 0},
- {0x2A, 0, 0, 0, 0},
- {0x2B, 0, 0, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0, 0, 0, 0},
- {0x2F, 0x1f, 0x1f, 0, 0},
- {0x30, 0x15, 0x15, 0, 0},
- {0x31, 0xf, 0xf, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0, 0, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0, 0, 0, 0},
- {0x38, 0, 0, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0, 0, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x13, 0x13, 0, 0},
- {0x3D, 0xf, 0xf, 0, 0},
- {0x3E, 0x18, 0x18, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x20, 0x20, 0, 0},
- {0x42, 0x20, 0x20, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x77, 0x77, 0, 0},
- {0x45, 0x7, 0x7, 0, 0},
- {0x46, 0x1, 0x1, 0, 0},
- {0x47, 0x4, 0x4, 0, 0},
- {0x48, 0xf, 0xf, 0, 0},
- {0x49, 0x30, 0x30, 0, 0},
- {0x4A, 0x32, 0x32, 0, 0},
- {0x4B, 0xd, 0xd, 0, 0},
- {0x4C, 0xd, 0xd, 0, 0},
- {0x4D, 0x4, 0x4, 0, 0},
- {0x4E, 0x6, 0x6, 0, 0},
- {0x4F, 0x1, 0x1, 0, 0},
- {0x50, 0x1c, 0x1c, 0, 0},
- {0x51, 0x2, 0x2, 0, 0},
- {0x52, 0x2, 0x2, 0, 0},
- {0x53, 0xf7, 0xf7, 1, 1},
- {0x54, 0xb4, 0xb4, 0, 0},
- {0x55, 0xd2, 0xd2, 0, 0},
- {0x56, 0, 0, 0, 0},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x4, 0x4, 0, 0},
- {0x59, 0x96, 0x96, 0, 0},
- {0x5A, 0x3e, 0x3e, 0, 0},
- {0x5B, 0x3e, 0x3e, 0, 0},
- {0x5C, 0x13, 0x13, 0, 0},
- {0x5D, 0x2, 0x2, 0, 0},
- {0x5E, 0, 0, 0, 0},
- {0x5F, 0x7, 0x7, 0, 0},
- {0x60, 0x7, 0x7, 1, 1},
- {0x61, 0x8, 0x8, 0, 0},
- {0x62, 0x3, 0x3, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0x40, 0x40, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0x1, 0x1, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0x60, 0x60, 0, 0},
- {0x71, 0x66, 0x66, 0, 0},
- {0x72, 0xc, 0xc, 0, 0},
- {0x73, 0x66, 0x66, 0, 0},
- {0x74, 0x8f, 0x8f, 1, 1},
- {0x75, 0, 0, 0, 0},
- {0x76, 0xcc, 0xcc, 0, 0},
- {0x77, 0x1, 0x1, 0, 0},
- {0x78, 0x66, 0x66, 0, 0},
- {0x79, 0x66, 0x66, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0xff, 0xff, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0x95, 0, 0, 0, 0},
- {0x96, 0, 0, 0, 0},
- {0x97, 0, 0, 0, 0},
- {0x98, 0, 0, 0, 0},
- {0x99, 0, 0, 0, 0},
- {0x9A, 0, 0, 0, 0},
- {0x9B, 0, 0, 0, 0},
- {0x9C, 0, 0, 0, 0},
- {0x9D, 0, 0, 0, 0},
- {0x9E, 0, 0, 0, 0},
- {0x9F, 0x6, 0x6, 0, 0},
- {0xA0, 0x66, 0x66, 0, 0},
- {0xA1, 0x66, 0x66, 0, 0},
- {0xA2, 0x66, 0x66, 0, 0},
- {0xA3, 0x66, 0x66, 0, 0},
- {0xA4, 0x66, 0x66, 0, 0},
- {0xA5, 0x66, 0x66, 0, 0},
- {0xA6, 0x66, 0x66, 0, 0},
- {0xA7, 0x66, 0x66, 0, 0},
- {0xA8, 0x66, 0x66, 0, 0},
- {0xA9, 0x66, 0x66, 0, 0},
- {0xAA, 0x66, 0x66, 0, 0},
- {0xAB, 0x66, 0x66, 0, 0},
- {0xAC, 0x66, 0x66, 0, 0},
- {0xAD, 0x66, 0x66, 0, 0},
- {0xAE, 0x66, 0x66, 0, 0},
- {0xAF, 0x66, 0x66, 0, 0},
- {0xB0, 0x66, 0x66, 0, 0},
- {0xB1, 0x66, 0x66, 0, 0},
- {0xB2, 0x66, 0x66, 0, 0},
- {0xB3, 0xa, 0xa, 0, 0},
- {0xB4, 0, 0, 0, 0},
- {0xB5, 0, 0, 0, 0},
- {0xB6, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_TX_2056_rev6[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0x88, 0x88, 0, 0},
- {0x22, 0x88, 0x88, 0, 0},
- {0x23, 0x88, 0x88, 0, 0},
- {0x24, 0x88, 0x88, 0, 0},
- {0x25, 0xc, 0xc, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0x3, 0x3, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0x3, 0x3, 0, 0},
- {0x2A, 0x37, 0x37, 0, 0},
- {0x2B, 0x3, 0x3, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0x1, 0x1, 0, 0},
- {0x2F, 0x1, 0x1, 0, 0},
- {0x30, 0, 0, 0, 0},
- {0x31, 0, 0, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0x11, 0x11, 0, 0},
- {0x34, 0xee, 0xee, 1, 1},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0x3, 0x3, 0, 0},
- {0x38, 0x50, 0x50, 1, 1},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0x50, 0x50, 1, 1},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x6e, 0x6e, 0, 0},
- {0x3D, 0xf0, 0xf0, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x3, 0x3, 0, 0},
- {0x42, 0x3, 0x3, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x1e, 0x1e, 0, 0},
- {0x45, 0, 0, 0, 0},
- {0x46, 0x6e, 0x6e, 0, 0},
- {0x47, 0xf0, 0xf0, 1, 1},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x2, 0x2, 0, 0},
- {0x4A, 0xff, 0xff, 1, 1},
- {0x4B, 0xc, 0xc, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0x38, 0x38, 0, 0},
- {0x4E, 0x70, 0x70, 1, 1},
- {0x4F, 0x2, 0x2, 0, 0},
- {0x50, 0x88, 0x88, 0, 0},
- {0x51, 0xc, 0xc, 0, 0},
- {0x52, 0, 0, 0, 0},
- {0x53, 0x8, 0x8, 0, 0},
- {0x54, 0x70, 0x70, 1, 1},
- {0x55, 0x2, 0x2, 0, 0},
- {0x56, 0xff, 0xff, 1, 1},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x83, 0x83, 0, 0},
- {0x59, 0x77, 0x77, 1, 1},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x88, 0x88, 0, 0},
- {0x5D, 0, 0, 0, 0},
- {0x5E, 0x8, 0x8, 0, 0},
- {0x5F, 0x77, 0x77, 1, 1},
- {0x60, 0x1, 0x1, 0, 0},
- {0x61, 0, 0, 0, 0},
- {0x62, 0x7, 0x7, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0x7, 0x7, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 1, 1},
- {0x68, 0, 0, 0, 0},
- {0x69, 0xa, 0xa, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0x2, 0x2, 0, 0},
- {0x72, 0, 0, 0, 0},
- {0x73, 0, 0, 0, 0},
- {0x74, 0xe, 0xe, 0, 0},
- {0x75, 0xe, 0xe, 0, 0},
- {0x76, 0xe, 0xe, 0, 0},
- {0x77, 0x13, 0x13, 0, 0},
- {0x78, 0x13, 0x13, 0, 0},
- {0x79, 0x1b, 0x1b, 0, 0},
- {0x7A, 0x1b, 0x1b, 0, 0},
- {0x7B, 0x55, 0x55, 0, 0},
- {0x7C, 0x5b, 0x5b, 0, 0},
- {0x7D, 0x30, 0x30, 1, 1},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0x70, 0x70, 0, 0},
- {0x94, 0x70, 0x70, 0, 0},
- {0x95, 0x70, 0x70, 0, 0},
- {0x96, 0x70, 0x70, 0, 0},
- {0x97, 0x70, 0x70, 0, 0},
- {0x98, 0x70, 0x70, 0, 0},
- {0x99, 0x70, 0x70, 0, 0},
- {0x9A, 0x70, 0x70, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_RX_2056_rev6[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0x3, 0x3, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0, 0, 0, 0},
- {0x23, 0x90, 0x90, 0, 0},
- {0x24, 0x55, 0x55, 0, 0},
- {0x25, 0x15, 0x15, 0, 0},
- {0x26, 0x5, 0x5, 0, 0},
- {0x27, 0x15, 0x15, 0, 0},
- {0x28, 0x5, 0x5, 0, 0},
- {0x29, 0x20, 0x20, 0, 0},
- {0x2A, 0x11, 0x11, 0, 0},
- {0x2B, 0x90, 0x90, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0x88, 0x88, 0, 0},
- {0x2E, 0x32, 0x32, 0, 0},
- {0x2F, 0x77, 0x77, 0, 0},
- {0x30, 0x17, 0x17, 1, 1},
- {0x31, 0xff, 0xff, 1, 1},
- {0x32, 0x20, 0x20, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0x88, 0x88, 0, 0},
- {0x35, 0x32, 0x32, 0, 0},
- {0x36, 0x77, 0x77, 0, 0},
- {0x37, 0x17, 0x17, 1, 1},
- {0x38, 0xf0, 0xf0, 1, 1},
- {0x39, 0x20, 0x20, 0, 0},
- {0x3A, 0x8, 0x8, 0, 0},
- {0x3B, 0x55, 0x55, 1, 1},
- {0x3C, 0, 0, 0, 0},
- {0x3D, 0x88, 0x88, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0x44, 0x44, 0, 0},
- {0x40, 0x7, 0x7, 1, 1},
- {0x41, 0x6, 0x6, 0, 0},
- {0x42, 0x4, 0x4, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x8, 0x8, 0, 0},
- {0x45, 0x55, 0x55, 1, 1},
- {0x46, 0, 0, 0, 0},
- {0x47, 0x11, 0x11, 0, 0},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x44, 0x44, 0, 0},
- {0x4A, 0x7, 0x7, 0, 0},
- {0x4B, 0x6, 0x6, 0, 0},
- {0x4C, 0x4, 0x4, 0, 0},
- {0x4D, 0, 0, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0x26, 0x26, 1, 1},
- {0x50, 0x26, 0x26, 1, 1},
- {0x51, 0xf, 0xf, 1, 1},
- {0x52, 0xf, 0xf, 1, 1},
- {0x53, 0x44, 0x44, 0, 0},
- {0x54, 0, 0, 0, 0},
- {0x55, 0, 0, 0, 0},
- {0x56, 0x8, 0x8, 0, 0},
- {0x57, 0x8, 0x8, 0, 0},
- {0x58, 0x7, 0x7, 0, 0},
- {0x59, 0x22, 0x22, 0, 0},
- {0x5A, 0x22, 0x22, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x4, 0x4, 1, 1},
- {0x5D, 0x7, 0x7, 0, 0},
- {0x5E, 0x55, 0x55, 0, 0},
- {0x5F, 0x23, 0x23, 0, 0},
- {0x60, 0x41, 0x41, 0, 0},
- {0x61, 0x1, 0x1, 0, 0},
- {0x62, 0xa, 0xa, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0, 0, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0xc, 0xc, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0, 0, 0, 0},
- {0x72, 0x22, 0x22, 0, 0},
- {0x73, 0x22, 0x22, 0, 0},
- {0x74, 0, 0, 1, 1},
- {0x75, 0xa, 0xa, 0, 0},
- {0x76, 0x1, 0x1, 0, 0},
- {0x77, 0x22, 0x22, 0, 0},
- {0x78, 0x30, 0x30, 0, 0},
- {0x79, 0, 0, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0x5, 0x5, 1, 1},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0}
-};
-
-radio_regs_t regs_SYN_2056_rev7[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0x1, 0x1, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0x60, 0x60, 0, 0},
- {0x23, 0x6, 0x6, 0, 0},
- {0x24, 0xc, 0xc, 0, 0},
- {0x25, 0, 0, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0, 0, 0, 0},
- {0x28, 0x1, 0x1, 0, 0},
- {0x29, 0, 0, 0, 0},
- {0x2A, 0, 0, 0, 0},
- {0x2B, 0, 0, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0, 0, 0, 0},
- {0x2F, 0x1f, 0x1f, 0, 0},
- {0x30, 0x15, 0x15, 0, 0},
- {0x31, 0xf, 0xf, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0, 0, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0, 0, 0, 0},
- {0x38, 0, 0, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0, 0, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x13, 0x13, 0, 0},
- {0x3D, 0xf, 0xf, 0, 0},
- {0x3E, 0x18, 0x18, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x20, 0x20, 0, 0},
- {0x42, 0x20, 0x20, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x77, 0x77, 0, 0},
- {0x45, 0x7, 0x7, 0, 0},
- {0x46, 0x1, 0x1, 0, 0},
- {0x47, 0x4, 0x4, 0, 0},
- {0x48, 0xf, 0xf, 0, 0},
- {0x49, 0x30, 0x30, 0, 0},
- {0x4A, 0x32, 0x32, 0, 0},
- {0x4B, 0xd, 0xd, 0, 0},
- {0x4C, 0xd, 0xd, 0, 0},
- {0x4D, 0x4, 0x4, 0, 0},
- {0x4E, 0x6, 0x6, 0, 0},
- {0x4F, 0x1, 0x1, 0, 0},
- {0x50, 0x1c, 0x1c, 0, 0},
- {0x51, 0x2, 0x2, 0, 0},
- {0x52, 0x2, 0x2, 0, 0},
- {0x53, 0xf7, 0xf7, 1, 1},
- {0x54, 0xb4, 0xb4, 0, 0},
- {0x55, 0xd2, 0xd2, 0, 0},
- {0x56, 0, 0, 0, 0},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x4, 0x4, 0, 0},
- {0x59, 0x96, 0x96, 0, 0},
- {0x5A, 0x3e, 0x3e, 0, 0},
- {0x5B, 0x3e, 0x3e, 0, 0},
- {0x5C, 0x13, 0x13, 0, 0},
- {0x5D, 0x2, 0x2, 0, 0},
- {0x5E, 0, 0, 0, 0},
- {0x5F, 0x7, 0x7, 0, 0},
- {0x60, 0x7, 0x7, 1, 1},
- {0x61, 0x8, 0x8, 0, 0},
- {0x62, 0x3, 0x3, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0x40, 0x40, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0x1, 0x1, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0x60, 0x60, 0, 0},
- {0x71, 0x66, 0x66, 0, 0},
- {0x72, 0xc, 0xc, 0, 0},
- {0x73, 0x66, 0x66, 0, 0},
- {0x74, 0x8f, 0x8f, 1, 1},
- {0x75, 0, 0, 0, 0},
- {0x76, 0xcc, 0xcc, 0, 0},
- {0x77, 0x1, 0x1, 0, 0},
- {0x78, 0x66, 0x66, 0, 0},
- {0x79, 0x66, 0x66, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0xff, 0xff, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0x95, 0, 0, 0, 0},
- {0x96, 0, 0, 0, 0},
- {0x97, 0, 0, 0, 0},
- {0x98, 0, 0, 0, 0},
- {0x99, 0, 0, 0, 0},
- {0x9A, 0, 0, 0, 0},
- {0x9B, 0, 0, 0, 0},
- {0x9C, 0, 0, 0, 0},
- {0x9D, 0, 0, 0, 0},
- {0x9E, 0, 0, 0, 0},
- {0x9F, 0x6, 0x6, 0, 0},
- {0xA0, 0x66, 0x66, 0, 0},
- {0xA1, 0x66, 0x66, 0, 0},
- {0xA2, 0x66, 0x66, 0, 0},
- {0xA3, 0x66, 0x66, 0, 0},
- {0xA4, 0x66, 0x66, 0, 0},
- {0xA5, 0x66, 0x66, 0, 0},
- {0xA6, 0x66, 0x66, 0, 0},
- {0xA7, 0x66, 0x66, 0, 0},
- {0xA8, 0x66, 0x66, 0, 0},
- {0xA9, 0x66, 0x66, 0, 0},
- {0xAA, 0x66, 0x66, 0, 0},
- {0xAB, 0x66, 0x66, 0, 0},
- {0xAC, 0x66, 0x66, 0, 0},
- {0xAD, 0x66, 0x66, 0, 0},
- {0xAE, 0x66, 0x66, 0, 0},
- {0xAF, 0x66, 0x66, 0, 0},
- {0xB0, 0x66, 0x66, 0, 0},
- {0xB1, 0x66, 0x66, 0, 0},
- {0xB2, 0x66, 0x66, 0, 0},
- {0xB3, 0xa, 0xa, 0, 0},
- {0xB4, 0, 0, 0, 0},
- {0xB5, 0, 0, 0, 0},
- {0xB6, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_TX_2056_rev7[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0x88, 0x88, 0, 0},
- {0x22, 0x88, 0x88, 0, 0},
- {0x23, 0x88, 0x88, 0, 0},
- {0x24, 0x88, 0x88, 0, 0},
- {0x25, 0xc, 0xc, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0x3, 0x3, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0x3, 0x3, 0, 0},
- {0x2A, 0x37, 0x37, 0, 0},
- {0x2B, 0x3, 0x3, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0x1, 0x1, 0, 0},
- {0x2F, 0x1, 0x1, 0, 0},
- {0x30, 0, 0, 0, 0},
- {0x31, 0, 0, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0x11, 0x11, 0, 0},
- {0x34, 0xee, 0xee, 1, 1},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0x3, 0x3, 0, 0},
- {0x38, 0x50, 0x50, 1, 1},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0x50, 0x50, 1, 1},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x6e, 0x6e, 0, 0},
- {0x3D, 0xf0, 0xf0, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x3, 0x3, 0, 0},
- {0x42, 0x3, 0x3, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x1e, 0x1e, 0, 0},
- {0x45, 0, 0, 0, 0},
- {0x46, 0x6e, 0x6e, 0, 0},
- {0x47, 0xf0, 0xf0, 1, 1},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x2, 0x2, 0, 0},
- {0x4A, 0xff, 0xff, 1, 1},
- {0x4B, 0xc, 0xc, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0x38, 0x38, 0, 0},
- {0x4E, 0x70, 0x70, 1, 1},
- {0x4F, 0x2, 0x2, 0, 0},
- {0x50, 0x88, 0x88, 0, 0},
- {0x51, 0xc, 0xc, 0, 0},
- {0x52, 0, 0, 0, 0},
- {0x53, 0x8, 0x8, 0, 0},
- {0x54, 0x70, 0x70, 1, 1},
- {0x55, 0x2, 0x2, 0, 0},
- {0x56, 0xff, 0xff, 1, 1},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x83, 0x83, 0, 0},
- {0x59, 0x77, 0x77, 1, 1},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x88, 0x88, 0, 0},
- {0x5D, 0, 0, 0, 0},
- {0x5E, 0x8, 0x8, 0, 0},
- {0x5F, 0x77, 0x77, 1, 1},
- {0x60, 0x1, 0x1, 0, 0},
- {0x61, 0, 0, 0, 0},
- {0x62, 0x7, 0x7, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0x7, 0x7, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 1, 1},
- {0x68, 0, 0, 0, 0},
- {0x69, 0xa, 0xa, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0x2, 0x2, 0, 0},
- {0x72, 0, 0, 0, 0},
- {0x73, 0, 0, 0, 0},
- {0x74, 0xe, 0xe, 0, 0},
- {0x75, 0xe, 0xe, 0, 0},
- {0x76, 0xe, 0xe, 0, 0},
- {0x77, 0x13, 0x13, 0, 0},
- {0x78, 0x13, 0x13, 0, 0},
- {0x79, 0x1b, 0x1b, 0, 0},
- {0x7A, 0x1b, 0x1b, 0, 0},
- {0x7B, 0x55, 0x55, 0, 0},
- {0x7C, 0x5b, 0x5b, 0, 0},
- {0x7D, 0x30, 0x30, 1, 1},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0x70, 0x70, 0, 0},
- {0x94, 0x70, 0x70, 0, 0},
- {0x95, 0x71, 0x71, 1, 1},
- {0x96, 0x71, 0x71, 1, 1},
- {0x97, 0x72, 0x72, 1, 1},
- {0x98, 0x73, 0x73, 1, 1},
- {0x99, 0x74, 0x74, 1, 1},
- {0x9A, 0x75, 0x75, 1, 1},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_RX_2056_rev7[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0x3, 0x3, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0, 0, 0, 0},
- {0x23, 0x90, 0x90, 0, 0},
- {0x24, 0x55, 0x55, 0, 0},
- {0x25, 0x15, 0x15, 0, 0},
- {0x26, 0x5, 0x5, 0, 0},
- {0x27, 0x15, 0x15, 0, 0},
- {0x28, 0x5, 0x5, 0, 0},
- {0x29, 0x20, 0x20, 0, 0},
- {0x2A, 0x11, 0x11, 0, 0},
- {0x2B, 0x90, 0x90, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0x88, 0x88, 0, 0},
- {0x2E, 0x32, 0x32, 0, 0},
- {0x2F, 0x77, 0x77, 0, 0},
- {0x30, 0x17, 0x17, 1, 1},
- {0x31, 0xff, 0xff, 1, 1},
- {0x32, 0x20, 0x20, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0x88, 0x88, 0, 0},
- {0x35, 0x32, 0x32, 0, 0},
- {0x36, 0x77, 0x77, 0, 0},
- {0x37, 0x17, 0x17, 1, 1},
- {0x38, 0xf0, 0xf0, 1, 1},
- {0x39, 0x20, 0x20, 0, 0},
- {0x3A, 0x8, 0x8, 0, 0},
- {0x3B, 0x55, 0x55, 1, 1},
- {0x3C, 0, 0, 0, 0},
- {0x3D, 0x88, 0x88, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 1, 1},
- {0x40, 0x7, 0x7, 1, 1},
- {0x41, 0x6, 0x6, 0, 0},
- {0x42, 0x4, 0x4, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x8, 0x8, 0, 0},
- {0x45, 0x55, 0x55, 1, 1},
- {0x46, 0, 0, 0, 0},
- {0x47, 0x11, 0x11, 0, 0},
- {0x48, 0, 0, 0, 0},
- {0x49, 0, 0, 1, 1},
- {0x4A, 0x7, 0x7, 0, 0},
- {0x4B, 0x6, 0x6, 0, 0},
- {0x4C, 0x4, 0x4, 0, 0},
- {0x4D, 0, 0, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0x26, 0x26, 1, 1},
- {0x50, 0x26, 0x26, 1, 1},
- {0x51, 0xf, 0xf, 1, 1},
- {0x52, 0xf, 0xf, 1, 1},
- {0x53, 0x44, 0x44, 0, 0},
- {0x54, 0, 0, 0, 0},
- {0x55, 0, 0, 0, 0},
- {0x56, 0x8, 0x8, 0, 0},
- {0x57, 0x8, 0x8, 0, 0},
- {0x58, 0x7, 0x7, 0, 0},
- {0x59, 0x22, 0x22, 0, 0},
- {0x5A, 0x22, 0x22, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x4, 0x4, 1, 1},
- {0x5D, 0x7, 0x7, 0, 0},
- {0x5E, 0x55, 0x55, 0, 0},
- {0x5F, 0x23, 0x23, 0, 0},
- {0x60, 0x41, 0x41, 0, 0},
- {0x61, 0x1, 0x1, 0, 0},
- {0x62, 0xa, 0xa, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0, 0, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0xc, 0xc, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0, 0, 0, 0},
- {0x72, 0x22, 0x22, 0, 0},
- {0x73, 0x22, 0x22, 0, 0},
- {0x74, 0, 0, 1, 1},
- {0x75, 0xa, 0xa, 0, 0},
- {0x76, 0x1, 0x1, 0, 0},
- {0x77, 0x22, 0x22, 0, 0},
- {0x78, 0x30, 0x30, 0, 0},
- {0x79, 0, 0, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_SYN_2056_rev8[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0x1, 0x1, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0x60, 0x60, 0, 0},
- {0x23, 0x6, 0x6, 0, 0},
- {0x24, 0xc, 0xc, 0, 0},
- {0x25, 0, 0, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0, 0, 0, 0},
- {0x28, 0x1, 0x1, 0, 0},
- {0x29, 0, 0, 0, 0},
- {0x2A, 0, 0, 0, 0},
- {0x2B, 0, 0, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0, 0, 0, 0},
- {0x2F, 0x1f, 0x1f, 0, 0},
- {0x30, 0x15, 0x15, 0, 0},
- {0x31, 0xf, 0xf, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0, 0, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0, 0, 0, 0},
- {0x38, 0, 0, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0, 0, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x13, 0x13, 0, 0},
- {0x3D, 0xf, 0xf, 0, 0},
- {0x3E, 0x18, 0x18, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x20, 0x20, 0, 0},
- {0x42, 0x20, 0x20, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x77, 0x77, 0, 0},
- {0x45, 0x7, 0x7, 0, 0},
- {0x46, 0x1, 0x1, 0, 0},
- {0x47, 0x4, 0x4, 0, 0},
- {0x48, 0xf, 0xf, 0, 0},
- {0x49, 0x30, 0x30, 0, 0},
- {0x4A, 0x32, 0x32, 0, 0},
- {0x4B, 0xd, 0xd, 0, 0},
- {0x4C, 0xd, 0xd, 0, 0},
- {0x4D, 0x4, 0x4, 0, 0},
- {0x4E, 0x6, 0x6, 0, 0},
- {0x4F, 0x1, 0x1, 0, 0},
- {0x50, 0x1c, 0x1c, 0, 0},
- {0x51, 0x2, 0x2, 0, 0},
- {0x52, 0x2, 0x2, 0, 0},
- {0x53, 0xf7, 0xf7, 1, 1},
- {0x54, 0xb4, 0xb4, 0, 0},
- {0x55, 0xd2, 0xd2, 0, 0},
- {0x56, 0, 0, 0, 0},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x4, 0x4, 0, 0},
- {0x59, 0x96, 0x96, 0, 0},
- {0x5A, 0x3e, 0x3e, 0, 0},
- {0x5B, 0x3e, 0x3e, 0, 0},
- {0x5C, 0x13, 0x13, 0, 0},
- {0x5D, 0x2, 0x2, 0, 0},
- {0x5E, 0, 0, 0, 0},
- {0x5F, 0x7, 0x7, 0, 0},
- {0x60, 0x7, 0x7, 1, 1},
- {0x61, 0x8, 0x8, 0, 0},
- {0x62, 0x3, 0x3, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0x40, 0x40, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0x1, 0x1, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0x60, 0x60, 0, 0},
- {0x71, 0x66, 0x66, 0, 0},
- {0x72, 0xc, 0xc, 0, 0},
- {0x73, 0x66, 0x66, 0, 0},
- {0x74, 0x8f, 0x8f, 1, 1},
- {0x75, 0, 0, 0, 0},
- {0x76, 0xcc, 0xcc, 0, 0},
- {0x77, 0x1, 0x1, 0, 0},
- {0x78, 0x66, 0x66, 0, 0},
- {0x79, 0x66, 0x66, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0xff, 0xff, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0x95, 0, 0, 0, 0},
- {0x96, 0, 0, 0, 0},
- {0x97, 0, 0, 0, 0},
- {0x98, 0, 0, 0, 0},
- {0x99, 0, 0, 0, 0},
- {0x9A, 0, 0, 0, 0},
- {0x9B, 0, 0, 0, 0},
- {0x9C, 0, 0, 0, 0},
- {0x9D, 0, 0, 0, 0},
- {0x9E, 0, 0, 0, 0},
- {0x9F, 0x6, 0x6, 0, 0},
- {0xA0, 0x66, 0x66, 0, 0},
- {0xA1, 0x66, 0x66, 0, 0},
- {0xA2, 0x66, 0x66, 0, 0},
- {0xA3, 0x66, 0x66, 0, 0},
- {0xA4, 0x66, 0x66, 0, 0},
- {0xA5, 0x66, 0x66, 0, 0},
- {0xA6, 0x66, 0x66, 0, 0},
- {0xA7, 0x66, 0x66, 0, 0},
- {0xA8, 0x66, 0x66, 0, 0},
- {0xA9, 0x66, 0x66, 0, 0},
- {0xAA, 0x66, 0x66, 0, 0},
- {0xAB, 0x66, 0x66, 0, 0},
- {0xAC, 0x66, 0x66, 0, 0},
- {0xAD, 0x66, 0x66, 0, 0},
- {0xAE, 0x66, 0x66, 0, 0},
- {0xAF, 0x66, 0x66, 0, 0},
- {0xB0, 0x66, 0x66, 0, 0},
- {0xB1, 0x66, 0x66, 0, 0},
- {0xB2, 0x66, 0x66, 0, 0},
- {0xB3, 0xa, 0xa, 0, 0},
- {0xB4, 0, 0, 0, 0},
- {0xB5, 0, 0, 0, 0},
- {0xB6, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_TX_2056_rev8[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0x88, 0x88, 0, 0},
- {0x22, 0x88, 0x88, 0, 0},
- {0x23, 0x88, 0x88, 0, 0},
- {0x24, 0x88, 0x88, 0, 0},
- {0x25, 0xc, 0xc, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0x3, 0x3, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0x3, 0x3, 0, 0},
- {0x2A, 0x37, 0x37, 0, 0},
- {0x2B, 0x3, 0x3, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0x1, 0x1, 0, 0},
- {0x2F, 0x1, 0x1, 0, 0},
- {0x30, 0, 0, 0, 0},
- {0x31, 0, 0, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0x11, 0x11, 0, 0},
- {0x34, 0xee, 0xee, 1, 1},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0x3, 0x3, 0, 0},
- {0x38, 0x50, 0x50, 1, 1},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0x50, 0x50, 1, 1},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x6e, 0x6e, 0, 0},
- {0x3D, 0xf0, 0xf0, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x3, 0x3, 0, 0},
- {0x42, 0x3, 0x3, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x1e, 0x1e, 0, 0},
- {0x45, 0, 0, 0, 0},
- {0x46, 0x6e, 0x6e, 0, 0},
- {0x47, 0xf0, 0xf0, 1, 1},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x2, 0x2, 0, 0},
- {0x4A, 0xff, 0xff, 1, 1},
- {0x4B, 0xc, 0xc, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0x38, 0x38, 0, 0},
- {0x4E, 0x70, 0x70, 1, 1},
- {0x4F, 0x2, 0x2, 0, 0},
- {0x50, 0x88, 0x88, 0, 0},
- {0x51, 0xc, 0xc, 0, 0},
- {0x52, 0, 0, 0, 0},
- {0x53, 0x8, 0x8, 0, 0},
- {0x54, 0x70, 0x70, 1, 1},
- {0x55, 0x2, 0x2, 0, 0},
- {0x56, 0xff, 0xff, 1, 1},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x83, 0x83, 0, 0},
- {0x59, 0x77, 0x77, 1, 1},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x88, 0x88, 0, 0},
- {0x5D, 0, 0, 0, 0},
- {0x5E, 0x8, 0x8, 0, 0},
- {0x5F, 0x77, 0x77, 1, 1},
- {0x60, 0x1, 0x1, 0, 0},
- {0x61, 0, 0, 0, 0},
- {0x62, 0x7, 0x7, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0x7, 0x7, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 1, 1},
- {0x68, 0, 0, 0, 0},
- {0x69, 0xa, 0xa, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0x2, 0x2, 0, 0},
- {0x72, 0, 0, 0, 0},
- {0x73, 0, 0, 0, 0},
- {0x74, 0xe, 0xe, 0, 0},
- {0x75, 0xe, 0xe, 0, 0},
- {0x76, 0xe, 0xe, 0, 0},
- {0x77, 0x13, 0x13, 0, 0},
- {0x78, 0x13, 0x13, 0, 0},
- {0x79, 0x1b, 0x1b, 0, 0},
- {0x7A, 0x1b, 0x1b, 0, 0},
- {0x7B, 0x55, 0x55, 0, 0},
- {0x7C, 0x5b, 0x5b, 0, 0},
- {0x7D, 0x30, 0x30, 1, 1},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0x70, 0x70, 0, 0},
- {0x94, 0x70, 0x70, 0, 0},
- {0x95, 0x70, 0x70, 0, 0},
- {0x96, 0x70, 0x70, 0, 0},
- {0x97, 0x70, 0x70, 0, 0},
- {0x98, 0x70, 0x70, 0, 0},
- {0x99, 0x70, 0x70, 0, 0},
- {0x9A, 0x70, 0x70, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_RX_2056_rev8[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0x3, 0x3, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0, 0, 0, 0},
- {0x23, 0x90, 0x90, 0, 0},
- {0x24, 0x55, 0x55, 0, 0},
- {0x25, 0x15, 0x15, 0, 0},
- {0x26, 0x5, 0x5, 0, 0},
- {0x27, 0x15, 0x15, 0, 0},
- {0x28, 0x5, 0x5, 0, 0},
- {0x29, 0x20, 0x20, 0, 0},
- {0x2A, 0x11, 0x11, 0, 0},
- {0x2B, 0x90, 0x90, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0x88, 0x88, 0, 0},
- {0x2E, 0x32, 0x32, 0, 0},
- {0x2F, 0x77, 0x77, 0, 0},
- {0x30, 0x17, 0x17, 1, 1},
- {0x31, 0xff, 0xff, 1, 1},
- {0x32, 0x20, 0x20, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0x88, 0x88, 0, 0},
- {0x35, 0x32, 0x32, 0, 0},
- {0x36, 0x77, 0x77, 0, 0},
- {0x37, 0x17, 0x17, 1, 1},
- {0x38, 0xf0, 0xf0, 1, 1},
- {0x39, 0x20, 0x20, 0, 0},
- {0x3A, 0x8, 0x8, 0, 0},
- {0x3B, 0x55, 0x55, 1, 1},
- {0x3C, 0, 0, 0, 0},
- {0x3D, 0x88, 0x88, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0x44, 0x44, 0, 0},
- {0x40, 0x7, 0x7, 1, 1},
- {0x41, 0x6, 0x6, 0, 0},
- {0x42, 0x4, 0x4, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x8, 0x8, 0, 0},
- {0x45, 0x55, 0x55, 1, 1},
- {0x46, 0, 0, 0, 0},
- {0x47, 0x11, 0x11, 0, 0},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x44, 0x44, 0, 0},
- {0x4A, 0x7, 0x7, 0, 0},
- {0x4B, 0x6, 0x6, 0, 0},
- {0x4C, 0x4, 0x4, 0, 0},
- {0x4D, 0, 0, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0x26, 0x26, 1, 1},
- {0x50, 0x26, 0x26, 1, 1},
- {0x51, 0xf, 0xf, 1, 1},
- {0x52, 0xf, 0xf, 1, 1},
- {0x53, 0x44, 0x44, 0, 0},
- {0x54, 0, 0, 0, 0},
- {0x55, 0, 0, 0, 0},
- {0x56, 0x8, 0x8, 0, 0},
- {0x57, 0x8, 0x8, 0, 0},
- {0x58, 0x7, 0x7, 0, 0},
- {0x59, 0x22, 0x22, 0, 0},
- {0x5A, 0x22, 0x22, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x4, 0x4, 1, 1},
- {0x5D, 0x7, 0x7, 0, 0},
- {0x5E, 0x55, 0x55, 0, 0},
- {0x5F, 0x23, 0x23, 0, 0},
- {0x60, 0x41, 0x41, 0, 0},
- {0x61, 0x1, 0x1, 0, 0},
- {0x62, 0xa, 0xa, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0, 0, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0xc, 0xc, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0, 0, 0, 0},
- {0x72, 0x22, 0x22, 0, 0},
- {0x73, 0x22, 0x22, 0, 0},
- {0x74, 0, 0, 1, 1},
- {0x75, 0xa, 0xa, 0, 0},
- {0x76, 0x1, 0x1, 0, 0},
- {0x77, 0x22, 0x22, 0, 0},
- {0x78, 0x30, 0x30, 0, 0},
- {0x79, 0, 0, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0x5, 0x5, 1, 1},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_SYN_2056_rev11[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0x1, 0x1, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0x60, 0x60, 0, 0},
- {0x23, 0x6, 0x6, 0, 0},
- {0x24, 0xc, 0xc, 0, 0},
- {0x25, 0, 0, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0, 0, 0, 0},
- {0x28, 0x1, 0x1, 0, 0},
- {0x29, 0, 0, 0, 0},
- {0x2A, 0, 0, 0, 0},
- {0x2B, 0, 0, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0, 0, 0, 0},
- {0x2F, 0x1f, 0x1f, 0, 0},
- {0x30, 0x15, 0x15, 0, 0},
- {0x31, 0xf, 0xf, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0, 0, 0, 0},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0, 0, 0, 0},
- {0x38, 0, 0, 0, 0},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0, 0, 0, 0},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x13, 0x13, 0, 0},
- {0x3D, 0xf, 0xf, 0, 0},
- {0x3E, 0x18, 0x18, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x20, 0x20, 0, 0},
- {0x42, 0x20, 0x20, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x77, 0x77, 0, 0},
- {0x45, 0x7, 0x7, 0, 0},
- {0x46, 0x1, 0x1, 0, 0},
- {0x47, 0x6, 0x6, 1, 1},
- {0x48, 0xf, 0xf, 0, 0},
- {0x49, 0x3f, 0x3f, 1, 1},
- {0x4A, 0x32, 0x32, 0, 0},
- {0x4B, 0x6, 0x6, 1, 1},
- {0x4C, 0x6, 0x6, 1, 1},
- {0x4D, 0x4, 0x4, 0, 0},
- {0x4E, 0x2b, 0x2b, 1, 1},
- {0x4F, 0x1, 0x1, 0, 0},
- {0x50, 0x1c, 0x1c, 0, 0},
- {0x51, 0x2, 0x2, 0, 0},
- {0x52, 0x2, 0x2, 0, 0},
- {0x53, 0xf7, 0xf7, 1, 1},
- {0x54, 0xb4, 0xb4, 0, 0},
- {0x55, 0xd2, 0xd2, 0, 0},
- {0x56, 0, 0, 0, 0},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x4, 0x4, 0, 0},
- {0x59, 0x96, 0x96, 0, 0},
- {0x5A, 0x3e, 0x3e, 0, 0},
- {0x5B, 0x3e, 0x3e, 0, 0},
- {0x5C, 0x13, 0x13, 0, 0},
- {0x5D, 0x2, 0x2, 0, 0},
- {0x5E, 0, 0, 0, 0},
- {0x5F, 0x7, 0x7, 0, 0},
- {0x60, 0x7, 0x7, 1, 1},
- {0x61, 0x8, 0x8, 0, 0},
- {0x62, 0x3, 0x3, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0x40, 0x40, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0x1, 0x1, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0x60, 0x60, 0, 0},
- {0x71, 0x66, 0x66, 0, 0},
- {0x72, 0xc, 0xc, 0, 0},
- {0x73, 0x66, 0x66, 0, 0},
- {0x74, 0x8f, 0x8f, 1, 1},
- {0x75, 0, 0, 0, 0},
- {0x76, 0xcc, 0xcc, 0, 0},
- {0x77, 0x1, 0x1, 0, 0},
- {0x78, 0x66, 0x66, 0, 0},
- {0x79, 0x66, 0x66, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0, 0, 0, 0},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0xff, 0xff, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0x95, 0, 0, 0, 0},
- {0x96, 0, 0, 0, 0},
- {0x97, 0, 0, 0, 0},
- {0x98, 0, 0, 0, 0},
- {0x99, 0, 0, 0, 0},
- {0x9A, 0, 0, 0, 0},
- {0x9B, 0, 0, 0, 0},
- {0x9C, 0, 0, 0, 0},
- {0x9D, 0, 0, 0, 0},
- {0x9E, 0, 0, 0, 0},
- {0x9F, 0x6, 0x6, 0, 0},
- {0xA0, 0x66, 0x66, 0, 0},
- {0xA1, 0x66, 0x66, 0, 0},
- {0xA2, 0x66, 0x66, 0, 0},
- {0xA3, 0x66, 0x66, 0, 0},
- {0xA4, 0x66, 0x66, 0, 0},
- {0xA5, 0x66, 0x66, 0, 0},
- {0xA6, 0x66, 0x66, 0, 0},
- {0xA7, 0x66, 0x66, 0, 0},
- {0xA8, 0x66, 0x66, 0, 0},
- {0xA9, 0x66, 0x66, 0, 0},
- {0xAA, 0x66, 0x66, 0, 0},
- {0xAB, 0x66, 0x66, 0, 0},
- {0xAC, 0x66, 0x66, 0, 0},
- {0xAD, 0x66, 0x66, 0, 0},
- {0xAE, 0x66, 0x66, 0, 0},
- {0xAF, 0x66, 0x66, 0, 0},
- {0xB0, 0x66, 0x66, 0, 0},
- {0xB1, 0x66, 0x66, 0, 0},
- {0xB2, 0x66, 0x66, 0, 0},
- {0xB3, 0xa, 0xa, 0, 0},
- {0xB4, 0, 0, 0, 0},
- {0xB5, 0, 0, 0, 0},
- {0xB6, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_TX_2056_rev11[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0, 0, 0, 0},
- {0x21, 0x88, 0x88, 0, 0},
- {0x22, 0x88, 0x88, 0, 0},
- {0x23, 0x88, 0x88, 0, 0},
- {0x24, 0x88, 0x88, 0, 0},
- {0x25, 0xc, 0xc, 0, 0},
- {0x26, 0, 0, 0, 0},
- {0x27, 0x3, 0x3, 0, 0},
- {0x28, 0, 0, 0, 0},
- {0x29, 0x3, 0x3, 0, 0},
- {0x2A, 0x37, 0x37, 0, 0},
- {0x2B, 0x3, 0x3, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0, 0, 0, 0},
- {0x2E, 0x1, 0x1, 0, 0},
- {0x2F, 0x1, 0x1, 0, 0},
- {0x30, 0, 0, 0, 0},
- {0x31, 0, 0, 0, 0},
- {0x32, 0, 0, 0, 0},
- {0x33, 0x11, 0x11, 0, 0},
- {0x34, 0xee, 0xee, 1, 1},
- {0x35, 0, 0, 0, 0},
- {0x36, 0, 0, 0, 0},
- {0x37, 0x3, 0x3, 0, 0},
- {0x38, 0x50, 0x50, 1, 1},
- {0x39, 0, 0, 0, 0},
- {0x3A, 0x50, 0x50, 1, 1},
- {0x3B, 0, 0, 0, 0},
- {0x3C, 0x6e, 0x6e, 0, 0},
- {0x3D, 0xf0, 0xf0, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0, 0, 0, 0},
- {0x40, 0, 0, 0, 0},
- {0x41, 0x3, 0x3, 0, 0},
- {0x42, 0x3, 0x3, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x1e, 0x1e, 0, 0},
- {0x45, 0, 0, 0, 0},
- {0x46, 0x6e, 0x6e, 0, 0},
- {0x47, 0xf0, 0xf0, 1, 1},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x2, 0x2, 0, 0},
- {0x4A, 0xff, 0xff, 1, 1},
- {0x4B, 0xc, 0xc, 0, 0},
- {0x4C, 0, 0, 0, 0},
- {0x4D, 0x38, 0x38, 0, 0},
- {0x4E, 0x70, 0x70, 1, 1},
- {0x4F, 0x2, 0x2, 0, 0},
- {0x50, 0x88, 0x88, 0, 0},
- {0x51, 0xc, 0xc, 0, 0},
- {0x52, 0, 0, 0, 0},
- {0x53, 0x8, 0x8, 0, 0},
- {0x54, 0x70, 0x70, 1, 1},
- {0x55, 0x2, 0x2, 0, 0},
- {0x56, 0xff, 0xff, 1, 1},
- {0x57, 0, 0, 0, 0},
- {0x58, 0x83, 0x83, 0, 0},
- {0x59, 0x77, 0x77, 1, 1},
- {0x5A, 0, 0, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x88, 0x88, 0, 0},
- {0x5D, 0, 0, 0, 0},
- {0x5E, 0x8, 0x8, 0, 0},
- {0x5F, 0x77, 0x77, 1, 1},
- {0x60, 0x1, 0x1, 0, 0},
- {0x61, 0, 0, 0, 0},
- {0x62, 0x7, 0x7, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0x7, 0x7, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 1, 1},
- {0x68, 0, 0, 0, 0},
- {0x69, 0xa, 0xa, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0, 0, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0x2, 0x2, 0, 0},
- {0x72, 0, 0, 0, 0},
- {0x73, 0, 0, 0, 0},
- {0x74, 0xe, 0xe, 0, 0},
- {0x75, 0xe, 0xe, 0, 0},
- {0x76, 0xe, 0xe, 0, 0},
- {0x77, 0x13, 0x13, 0, 0},
- {0x78, 0x13, 0x13, 0, 0},
- {0x79, 0x1b, 0x1b, 0, 0},
- {0x7A, 0x1b, 0x1b, 0, 0},
- {0x7B, 0x55, 0x55, 0, 0},
- {0x7C, 0x5b, 0x5b, 0, 0},
- {0x7D, 0x30, 0x30, 1, 1},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0x70, 0x70, 0, 0},
- {0x94, 0x70, 0x70, 0, 0},
- {0x95, 0x70, 0x70, 0, 0},
- {0x96, 0x70, 0x70, 0, 0},
- {0x97, 0x70, 0x70, 0, 0},
- {0x98, 0x70, 0x70, 0, 0},
- {0x99, 0x70, 0x70, 0, 0},
- {0x9A, 0x70, 0x70, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_regs_t regs_RX_2056_rev11[] = {
- {0x02, 0, 0, 0, 0},
- {0x03, 0, 0, 0, 0},
- {0x04, 0, 0, 0, 0},
- {0x05, 0, 0, 0, 0},
- {0x06, 0, 0, 0, 0},
- {0x07, 0, 0, 0, 0},
- {0x08, 0, 0, 0, 0},
- {0x09, 0, 0, 0, 0},
- {0x0A, 0, 0, 0, 0},
- {0x0B, 0, 0, 0, 0},
- {0x0C, 0, 0, 0, 0},
- {0x0D, 0, 0, 0, 0},
- {0x0E, 0, 0, 0, 0},
- {0x0F, 0, 0, 0, 0},
- {0x10, 0, 0, 0, 0},
- {0x11, 0, 0, 0, 0},
- {0x12, 0, 0, 0, 0},
- {0x13, 0, 0, 0, 0},
- {0x14, 0, 0, 0, 0},
- {0x15, 0, 0, 0, 0},
- {0x16, 0, 0, 0, 0},
- {0x17, 0, 0, 0, 0},
- {0x18, 0, 0, 0, 0},
- {0x19, 0, 0, 0, 0},
- {0x1A, 0, 0, 0, 0},
- {0x1B, 0, 0, 0, 0},
- {0x1C, 0, 0, 0, 0},
- {0x1D, 0, 0, 0, 0},
- {0x1E, 0, 0, 0, 0},
- {0x1F, 0, 0, 0, 0},
- {0x20, 0x3, 0x3, 0, 0},
- {0x21, 0, 0, 0, 0},
- {0x22, 0, 0, 0, 0},
- {0x23, 0x90, 0x90, 0, 0},
- {0x24, 0x55, 0x55, 0, 0},
- {0x25, 0x15, 0x15, 0, 0},
- {0x26, 0x5, 0x5, 0, 0},
- {0x27, 0x15, 0x15, 0, 0},
- {0x28, 0x5, 0x5, 0, 0},
- {0x29, 0x20, 0x20, 0, 0},
- {0x2A, 0x11, 0x11, 0, 0},
- {0x2B, 0x90, 0x90, 0, 0},
- {0x2C, 0, 0, 0, 0},
- {0x2D, 0x88, 0x88, 0, 0},
- {0x2E, 0x32, 0x32, 0, 0},
- {0x2F, 0x77, 0x77, 0, 0},
- {0x30, 0x17, 0x17, 1, 1},
- {0x31, 0xff, 0xff, 1, 1},
- {0x32, 0x20, 0x20, 0, 0},
- {0x33, 0, 0, 0, 0},
- {0x34, 0x88, 0x88, 0, 0},
- {0x35, 0x32, 0x32, 0, 0},
- {0x36, 0x77, 0x77, 0, 0},
- {0x37, 0x17, 0x17, 1, 1},
- {0x38, 0xf0, 0xf0, 1, 1},
- {0x39, 0x20, 0x20, 0, 0},
- {0x3A, 0x8, 0x8, 0, 0},
- {0x3B, 0x55, 0x55, 1, 1},
- {0x3C, 0, 0, 0, 0},
- {0x3D, 0x88, 0x88, 1, 1},
- {0x3E, 0, 0, 0, 0},
- {0x3F, 0x44, 0x44, 0, 0},
- {0x40, 0x7, 0x7, 1, 1},
- {0x41, 0x6, 0x6, 0, 0},
- {0x42, 0x4, 0x4, 0, 0},
- {0x43, 0, 0, 0, 0},
- {0x44, 0x8, 0x8, 0, 0},
- {0x45, 0x55, 0x55, 1, 1},
- {0x46, 0, 0, 0, 0},
- {0x47, 0x11, 0x11, 0, 0},
- {0x48, 0, 0, 0, 0},
- {0x49, 0x44, 0x44, 0, 0},
- {0x4A, 0x7, 0x7, 0, 0},
- {0x4B, 0x6, 0x6, 0, 0},
- {0x4C, 0x4, 0x4, 0, 0},
- {0x4D, 0, 0, 0, 0},
- {0x4E, 0, 0, 0, 0},
- {0x4F, 0x26, 0x26, 1, 1},
- {0x50, 0x26, 0x26, 1, 1},
- {0x51, 0xf, 0xf, 1, 1},
- {0x52, 0xf, 0xf, 1, 1},
- {0x53, 0x44, 0x44, 0, 0},
- {0x54, 0, 0, 0, 0},
- {0x55, 0, 0, 0, 0},
- {0x56, 0x8, 0x8, 0, 0},
- {0x57, 0x8, 0x8, 0, 0},
- {0x58, 0x7, 0x7, 0, 0},
- {0x59, 0x22, 0x22, 0, 0},
- {0x5A, 0x22, 0x22, 0, 0},
- {0x5B, 0x2, 0x2, 0, 0},
- {0x5C, 0x4, 0x4, 1, 1},
- {0x5D, 0x7, 0x7, 0, 0},
- {0x5E, 0x55, 0x55, 0, 0},
- {0x5F, 0x23, 0x23, 0, 0},
- {0x60, 0x41, 0x41, 0, 0},
- {0x61, 0x1, 0x1, 0, 0},
- {0x62, 0xa, 0xa, 0, 0},
- {0x63, 0, 0, 0, 0},
- {0x64, 0, 0, 0, 0},
- {0x65, 0, 0, 0, 0},
- {0x66, 0, 0, 0, 0},
- {0x67, 0, 0, 0, 0},
- {0x68, 0, 0, 0, 0},
- {0x69, 0, 0, 0, 0},
- {0x6A, 0, 0, 0, 0},
- {0x6B, 0xc, 0xc, 0, 0},
- {0x6C, 0, 0, 0, 0},
- {0x6D, 0, 0, 0, 0},
- {0x6E, 0, 0, 0, 0},
- {0x6F, 0, 0, 0, 0},
- {0x70, 0, 0, 0, 0},
- {0x71, 0, 0, 0, 0},
- {0x72, 0x22, 0x22, 0, 0},
- {0x73, 0x22, 0x22, 0, 0},
- {0x74, 0, 0, 1, 1},
- {0x75, 0xa, 0xa, 0, 0},
- {0x76, 0x1, 0x1, 0, 0},
- {0x77, 0x22, 0x22, 0, 0},
- {0x78, 0x30, 0x30, 0, 0},
- {0x79, 0, 0, 0, 0},
- {0x7A, 0, 0, 0, 0},
- {0x7B, 0, 0, 0, 0},
- {0x7C, 0, 0, 0, 0},
- {0x7D, 0x5, 0x5, 1, 1},
- {0x7E, 0, 0, 0, 0},
- {0x7F, 0, 0, 0, 0},
- {0x80, 0, 0, 0, 0},
- {0x81, 0, 0, 0, 0},
- {0x82, 0, 0, 0, 0},
- {0x83, 0, 0, 0, 0},
- {0x84, 0, 0, 0, 0},
- {0x85, 0, 0, 0, 0},
- {0x86, 0, 0, 0, 0},
- {0x87, 0, 0, 0, 0},
- {0x88, 0, 0, 0, 0},
- {0x89, 0, 0, 0, 0},
- {0x8A, 0, 0, 0, 0},
- {0x8B, 0, 0, 0, 0},
- {0x8C, 0, 0, 0, 0},
- {0x8D, 0, 0, 0, 0},
- {0x8E, 0, 0, 0, 0},
- {0x8F, 0, 0, 0, 0},
- {0x90, 0, 0, 0, 0},
- {0x91, 0, 0, 0, 0},
- {0x92, 0, 0, 0, 0},
- {0x93, 0, 0, 0, 0},
- {0x94, 0, 0, 0, 0},
- {0xFFFF, 0, 0, 0, 0},
-};
-
-radio_20xx_regs_t regs_2057_rev4[] = {
- {0x00, 0x84, 0},
- {0x01, 0, 0},
- {0x02, 0x60, 0},
- {0x03, 0x1f, 0},
- {0x04, 0x4, 0},
- {0x05, 0x2, 0},
- {0x06, 0x1, 0},
- {0x07, 0x1, 0},
- {0x08, 0x1, 0},
- {0x09, 0x69, 0},
- {0x0A, 0x66, 0},
- {0x0B, 0x6, 0},
- {0x0C, 0x18, 0},
- {0x0D, 0x3, 0},
- {0x0E, 0x20, 1},
- {0x0F, 0x20, 0},
- {0x10, 0, 0},
- {0x11, 0x7c, 0},
- {0x12, 0x42, 0},
- {0x13, 0xbd, 0},
- {0x14, 0x7, 0},
- {0x15, 0xf7, 0},
- {0x16, 0x8, 0},
- {0x17, 0x17, 0},
- {0x18, 0x7, 0},
- {0x19, 0, 0},
- {0x1A, 0x2, 0},
- {0x1B, 0x13, 0},
- {0x1C, 0x3e, 0},
- {0x1D, 0x3e, 0},
- {0x1E, 0x96, 0},
- {0x1F, 0x4, 0},
- {0x20, 0, 0},
- {0x21, 0, 0},
- {0x22, 0x17, 0},
- {0x23, 0x4, 0},
- {0x24, 0x1, 0},
- {0x25, 0x6, 0},
- {0x26, 0x4, 0},
- {0x27, 0xd, 0},
- {0x28, 0xd, 0},
- {0x29, 0x30, 0},
- {0x2A, 0x32, 0},
- {0x2B, 0x8, 0},
- {0x2C, 0x1c, 0},
- {0x2D, 0x2, 0},
- {0x2E, 0x4, 0},
- {0x2F, 0x7f, 0},
- {0x30, 0x27, 0},
- {0x31, 0, 1},
- {0x32, 0, 1},
- {0x33, 0, 1},
- {0x34, 0, 0},
- {0x35, 0x26, 1},
- {0x36, 0x18, 0},
- {0x37, 0x7, 0},
- {0x38, 0x66, 0},
- {0x39, 0x66, 0},
- {0x3A, 0x66, 0},
- {0x3B, 0x66, 0},
- {0x3C, 0xff, 1},
- {0x3D, 0xff, 1},
- {0x3E, 0xff, 1},
- {0x3F, 0xff, 1},
- {0x40, 0x16, 0},
- {0x41, 0x7, 0},
- {0x42, 0x19, 0},
- {0x43, 0x7, 0},
- {0x44, 0x6, 0},
- {0x45, 0x3, 0},
- {0x46, 0x1, 0},
- {0x47, 0x7, 0},
- {0x48, 0x33, 0},
- {0x49, 0x5, 0},
- {0x4A, 0x77, 0},
- {0x4B, 0x66, 0},
- {0x4C, 0x66, 0},
- {0x4D, 0, 0},
- {0x4E, 0x4, 0},
- {0x4F, 0xc, 0},
- {0x50, 0, 0},
- {0x51, 0x75, 0},
- {0x56, 0x7, 0},
- {0x57, 0, 0},
- {0x58, 0, 0},
- {0x59, 0xa8, 0},
- {0x5A, 0, 0},
- {0x5B, 0x1f, 0},
- {0x5C, 0x30, 0},
- {0x5D, 0x1, 0},
- {0x5E, 0x30, 0},
- {0x5F, 0x70, 0},
- {0x60, 0, 0},
- {0x61, 0, 0},
- {0x62, 0x33, 1},
- {0x63, 0x19, 0},
- {0x64, 0x62, 0},
- {0x65, 0, 0},
- {0x66, 0x11, 0},
- {0x69, 0, 0},
- {0x6A, 0x7e, 0},
- {0x6B, 0x3f, 0},
- {0x6C, 0x7f, 0},
- {0x6D, 0x78, 0},
- {0x6E, 0xc8, 0},
- {0x6F, 0x88, 0},
- {0x70, 0x8, 0},
- {0x71, 0xf, 0},
- {0x72, 0xbc, 0},
- {0x73, 0x8, 0},
- {0x74, 0x60, 0},
- {0x75, 0x1e, 0},
- {0x76, 0x70, 0},
- {0x77, 0, 0},
- {0x78, 0, 0},
- {0x79, 0, 0},
- {0x7A, 0x33, 0},
- {0x7B, 0x1e, 0},
- {0x7C, 0x62, 0},
- {0x7D, 0x11, 0},
- {0x80, 0x3c, 0},
- {0x81, 0x9c, 0},
- {0x82, 0xa, 0},
- {0x83, 0x9d, 0},
- {0x84, 0xa, 0},
- {0x85, 0, 0},
- {0x86, 0x40, 0},
- {0x87, 0x40, 0},
- {0x88, 0x88, 0},
- {0x89, 0x10, 0},
- {0x8A, 0xf0, 1},
- {0x8B, 0x10, 1},
- {0x8C, 0xf0, 1},
- {0x8D, 0, 0},
- {0x8E, 0, 0},
- {0x8F, 0x10, 0},
- {0x90, 0x55, 0},
- {0x91, 0x3f, 1},
- {0x92, 0x36, 1},
- {0x93, 0, 0},
- {0x94, 0, 0},
- {0x95, 0, 0},
- {0x96, 0x87, 0},
- {0x97, 0x11, 0},
- {0x98, 0, 0},
- {0x99, 0x33, 0},
- {0x9A, 0x88, 0},
- {0x9B, 0, 0},
- {0x9C, 0x87, 0},
- {0x9D, 0x11, 0},
- {0x9E, 0, 0},
- {0x9F, 0x33, 0},
- {0xA0, 0x88, 0},
- {0xA1, 0xe1, 0},
- {0xA2, 0x3f, 0},
- {0xA3, 0x44, 0},
- {0xA4, 0x8c, 1},
- {0xA5, 0x6d, 0},
- {0xA6, 0x22, 0},
- {0xA7, 0xbe, 0},
- {0xA8, 0x55, 1},
- {0xA9, 0xc, 0},
- {0xAA, 0xc, 0},
- {0xAB, 0xaa, 0},
- {0xAC, 0x2, 0},
- {0xAD, 0, 0},
- {0xAE, 0x10, 0},
- {0xAF, 0x1, 1},
- {0xB0, 0, 0},
- {0xB1, 0, 0},
- {0xB2, 0x80, 0},
- {0xB3, 0x60, 0},
- {0xB4, 0x44, 0},
- {0xB5, 0x55, 0},
- {0xB6, 0x1, 0},
- {0xB7, 0x55, 0},
- {0xB8, 0x1, 0},
- {0xB9, 0x5, 0},
- {0xBA, 0x55, 0},
- {0xBB, 0x55, 0},
- {0xC1, 0, 0},
- {0xC2, 0, 0},
- {0xC3, 0, 0},
- {0xC4, 0, 0},
- {0xC5, 0, 0},
- {0xC6, 0, 0},
- {0xC7, 0, 0},
- {0xC8, 0, 0},
- {0xC9, 0, 0},
- {0xCA, 0, 0},
- {0xCB, 0, 0},
- {0xCC, 0, 0},
- {0xCD, 0, 0},
- {0xCE, 0x5e, 0},
- {0xCF, 0xc, 0},
- {0xD0, 0xc, 0},
- {0xD1, 0xc, 0},
- {0xD2, 0, 0},
- {0xD3, 0x2b, 0},
- {0xD4, 0xc, 0},
- {0xD5, 0, 0},
- {0xD6, 0x75, 0},
- {0xDB, 0x7, 0},
- {0xDC, 0, 0},
- {0xDD, 0, 0},
- {0xDE, 0xa8, 0},
- {0xDF, 0, 0},
- {0xE0, 0x1f, 0},
- {0xE1, 0x30, 0},
- {0xE2, 0x1, 0},
- {0xE3, 0x30, 0},
- {0xE4, 0x70, 0},
- {0xE5, 0, 0},
- {0xE6, 0, 0},
- {0xE7, 0x33, 0},
- {0xE8, 0x19, 0},
- {0xE9, 0x62, 0},
- {0xEA, 0, 0},
- {0xEB, 0x11, 0},
- {0xEE, 0, 0},
- {0xEF, 0x7e, 0},
- {0xF0, 0x3f, 0},
- {0xF1, 0x7f, 0},
- {0xF2, 0x78, 0},
- {0xF3, 0xc8, 0},
- {0xF4, 0x88, 0},
- {0xF5, 0x8, 0},
- {0xF6, 0xf, 0},
- {0xF7, 0xbc, 0},
- {0xF8, 0x8, 0},
- {0xF9, 0x60, 0},
- {0xFA, 0x1e, 0},
- {0xFB, 0x70, 0},
- {0xFC, 0, 0},
- {0xFD, 0, 0},
- {0xFE, 0, 0},
- {0xFF, 0x33, 0},
- {0x100, 0x1e, 0},
- {0x101, 0x62, 0},
- {0x102, 0x11, 0},
- {0x105, 0x3c, 0},
- {0x106, 0x9c, 0},
- {0x107, 0xa, 0},
- {0x108, 0x9d, 0},
- {0x109, 0xa, 0},
- {0x10A, 0, 0},
- {0x10B, 0x40, 0},
- {0x10C, 0x40, 0},
- {0x10D, 0x88, 0},
- {0x10E, 0x10, 0},
- {0x10F, 0xf0, 1},
- {0x110, 0x10, 1},
- {0x111, 0xf0, 1},
- {0x112, 0, 0},
- {0x113, 0, 0},
- {0x114, 0x10, 0},
- {0x115, 0x55, 0},
- {0x116, 0x3f, 1},
- {0x117, 0x36, 1},
- {0x118, 0, 0},
- {0x119, 0, 0},
- {0x11A, 0, 0},
- {0x11B, 0x87, 0},
- {0x11C, 0x11, 0},
- {0x11D, 0, 0},
- {0x11E, 0x33, 0},
- {0x11F, 0x88, 0},
- {0x120, 0, 0},
- {0x121, 0x87, 0},
- {0x122, 0x11, 0},
- {0x123, 0, 0},
- {0x124, 0x33, 0},
- {0x125, 0x88, 0},
- {0x126, 0xe1, 0},
- {0x127, 0x3f, 0},
- {0x128, 0x44, 0},
- {0x129, 0x8c, 1},
- {0x12A, 0x6d, 0},
- {0x12B, 0x22, 0},
- {0x12C, 0xbe, 0},
- {0x12D, 0x55, 1},
- {0x12E, 0xc, 0},
- {0x12F, 0xc, 0},
- {0x130, 0xaa, 0},
- {0x131, 0x2, 0},
- {0x132, 0, 0},
- {0x133, 0x10, 0},
- {0x134, 0x1, 1},
- {0x135, 0, 0},
- {0x136, 0, 0},
- {0x137, 0x80, 0},
- {0x138, 0x60, 0},
- {0x139, 0x44, 0},
- {0x13A, 0x55, 0},
- {0x13B, 0x1, 0},
- {0x13C, 0x55, 0},
- {0x13D, 0x1, 0},
- {0x13E, 0x5, 0},
- {0x13F, 0x55, 0},
- {0x140, 0x55, 0},
- {0x146, 0, 0},
- {0x147, 0, 0},
- {0x148, 0, 0},
- {0x149, 0, 0},
- {0x14A, 0, 0},
- {0x14B, 0, 0},
- {0x14C, 0, 0},
- {0x14D, 0, 0},
- {0x14E, 0, 0},
- {0x14F, 0, 0},
- {0x150, 0, 0},
- {0x151, 0, 0},
- {0x152, 0, 0},
- {0x153, 0, 0},
- {0x154, 0xc, 0},
- {0x155, 0xc, 0},
- {0x156, 0xc, 0},
- {0x157, 0, 0},
- {0x158, 0x2b, 0},
- {0x159, 0x84, 0},
- {0x15A, 0x15, 0},
- {0x15B, 0xf, 0},
- {0x15C, 0, 0},
- {0x15D, 0, 0},
- {0x15E, 0, 1},
- {0x15F, 0, 1},
- {0x160, 0, 1},
- {0x161, 0, 1},
- {0x162, 0, 1},
- {0x163, 0, 1},
- {0x164, 0, 0},
- {0x165, 0, 0},
- {0x166, 0, 0},
- {0x167, 0, 0},
- {0x168, 0, 0},
- {0x169, 0x2, 1},
- {0x16A, 0, 1},
- {0x16B, 0, 1},
- {0x16C, 0, 1},
- {0x16D, 0, 0},
- {0x170, 0, 0},
- {0x171, 0x77, 0},
- {0x172, 0x77, 0},
- {0x173, 0x77, 0},
- {0x174, 0x77, 0},
- {0x175, 0, 0},
- {0x176, 0x3, 0},
- {0x177, 0x37, 0},
- {0x178, 0x3, 0},
- {0x179, 0, 0},
- {0x17A, 0x21, 0},
- {0x17B, 0x21, 0},
- {0x17C, 0, 0},
- {0x17D, 0xaa, 0},
- {0x17E, 0, 0},
- {0x17F, 0xaa, 0},
- {0x180, 0, 0},
- {0x190, 0, 0},
- {0x191, 0x77, 0},
- {0x192, 0x77, 0},
- {0x193, 0x77, 0},
- {0x194, 0x77, 0},
- {0x195, 0, 0},
- {0x196, 0x3, 0},
- {0x197, 0x37, 0},
- {0x198, 0x3, 0},
- {0x199, 0, 0},
- {0x19A, 0x21, 0},
- {0x19B, 0x21, 0},
- {0x19C, 0, 0},
- {0x19D, 0xaa, 0},
- {0x19E, 0, 0},
- {0x19F, 0xaa, 0},
- {0x1A0, 0, 0},
- {0x1A1, 0x2, 0},
- {0x1A2, 0xf, 0},
- {0x1A3, 0xf, 0},
- {0x1A4, 0, 1},
- {0x1A5, 0, 1},
- {0x1A6, 0, 1},
- {0x1A7, 0x2, 0},
- {0x1A8, 0xf, 0},
- {0x1A9, 0xf, 0},
- {0x1AA, 0, 1},
- {0x1AB, 0, 1},
- {0x1AC, 0, 1},
- {0xFFFF, 0, 0},
-};
-
-radio_20xx_regs_t regs_2057_rev5[] = {
- {0x00, 0, 1},
- {0x01, 0x57, 1},
- {0x02, 0x20, 1},
- {0x03, 0x1f, 0},
- {0x04, 0x4, 0},
- {0x05, 0x2, 0},
- {0x06, 0x1, 0},
- {0x07, 0x1, 0},
- {0x08, 0x1, 0},
- {0x09, 0x69, 0},
- {0x0A, 0x66, 0},
- {0x0B, 0x6, 0},
- {0x0C, 0x18, 0},
- {0x0D, 0x3, 0},
- {0x0E, 0x20, 0},
- {0x0F, 0x20, 0},
- {0x10, 0, 0},
- {0x11, 0x7c, 0},
- {0x12, 0x42, 0},
- {0x13, 0xbd, 0},
- {0x14, 0x7, 0},
- {0x15, 0x87, 0},
- {0x16, 0x8, 0},
- {0x17, 0x17, 0},
- {0x18, 0x7, 0},
- {0x19, 0, 0},
- {0x1A, 0x2, 0},
- {0x1B, 0x13, 0},
- {0x1C, 0x3e, 0},
- {0x1D, 0x3e, 0},
- {0x1E, 0x96, 0},
- {0x1F, 0x4, 0},
- {0x20, 0, 0},
- {0x21, 0, 0},
- {0x22, 0x17, 0},
- {0x23, 0x6, 1},
- {0x24, 0x1, 0},
- {0x25, 0x6, 0},
- {0x26, 0x4, 0},
- {0x27, 0xd, 0},
- {0x28, 0xd, 0},
- {0x29, 0x30, 0},
- {0x2A, 0x32, 0},
- {0x2B, 0x8, 0},
- {0x2C, 0x1c, 0},
- {0x2D, 0x2, 0},
- {0x2E, 0x4, 0},
- {0x2F, 0x7f, 0},
- {0x30, 0x27, 0},
- {0x31, 0, 1},
- {0x32, 0, 1},
- {0x33, 0, 1},
- {0x34, 0, 0},
- {0x35, 0x20, 0},
- {0x36, 0x18, 0},
- {0x37, 0x7, 0},
- {0x38, 0x66, 0},
- {0x39, 0x66, 0},
- {0x3C, 0xff, 0},
- {0x3D, 0xff, 0},
- {0x40, 0x16, 0},
- {0x41, 0x7, 0},
- {0x45, 0x3, 0},
- {0x46, 0x1, 0},
- {0x47, 0x7, 0},
- {0x4B, 0x66, 0},
- {0x4C, 0x66, 0},
- {0x4D, 0, 0},
- {0x4E, 0x4, 0},
- {0x4F, 0xc, 0},
- {0x50, 0, 0},
- {0x51, 0x70, 1},
- {0x56, 0x7, 0},
- {0x57, 0, 0},
- {0x58, 0, 0},
- {0x59, 0x88, 1},
- {0x5A, 0, 0},
- {0x5B, 0x1f, 0},
- {0x5C, 0x20, 1},
- {0x5D, 0x1, 0},
- {0x5E, 0x30, 0},
- {0x5F, 0x70, 0},
- {0x60, 0, 0},
- {0x61, 0, 0},
- {0x62, 0x33, 1},
- {0x63, 0xf, 1},
- {0x64, 0xf, 1},
- {0x65, 0, 0},
- {0x66, 0x11, 0},
- {0x80, 0x3c, 0},
- {0x81, 0x1, 1},
- {0x82, 0xa, 0},
- {0x85, 0, 0},
- {0x86, 0x40, 0},
- {0x87, 0x40, 0},
- {0x88, 0x88, 0},
- {0x89, 0x10, 0},
- {0x8A, 0xf0, 0},
- {0x8B, 0x10, 0},
- {0x8C, 0xf0, 0},
- {0x8F, 0x10, 0},
- {0x90, 0x55, 0},
- {0x91, 0x3f, 1},
- {0x92, 0x36, 1},
- {0x93, 0, 0},
- {0x94, 0, 0},
- {0x95, 0, 0},
- {0x96, 0x87, 0},
- {0x97, 0x11, 0},
- {0x98, 0, 0},
- {0x99, 0x33, 0},
- {0x9A, 0x88, 0},
- {0xA1, 0x20, 1},
- {0xA2, 0x3f, 0},
- {0xA3, 0x44, 0},
- {0xA4, 0x8c, 0},
- {0xA5, 0x6c, 0},
- {0xA6, 0x22, 0},
- {0xA7, 0xbe, 0},
- {0xA8, 0x55, 0},
- {0xAA, 0xc, 0},
- {0xAB, 0xaa, 0},
- {0xAC, 0x2, 0},
- {0xAD, 0, 0},
- {0xAE, 0x10, 0},
- {0xAF, 0x1, 0},
- {0xB0, 0, 0},
- {0xB1, 0, 0},
- {0xB2, 0x80, 0},
- {0xB3, 0x60, 0},
- {0xB4, 0x44, 0},
- {0xB5, 0x55, 0},
- {0xB6, 0x1, 0},
- {0xB7, 0x55, 0},
- {0xB8, 0x1, 0},
- {0xB9, 0x5, 0},
- {0xBA, 0x55, 0},
- {0xBB, 0x55, 0},
- {0xC3, 0, 0},
- {0xC4, 0, 0},
- {0xC5, 0, 0},
- {0xC6, 0, 0},
- {0xC7, 0, 0},
- {0xC8, 0, 0},
- {0xC9, 0, 0},
- {0xCA, 0, 0},
- {0xCB, 0, 0},
- {0xCD, 0, 0},
- {0xCE, 0x5e, 0},
- {0xCF, 0xc, 0},
- {0xD0, 0xc, 0},
- {0xD1, 0xc, 0},
- {0xD2, 0, 0},
- {0xD3, 0x2b, 0},
- {0xD4, 0xc, 0},
- {0xD5, 0, 0},
- {0xD6, 0x70, 1},
- {0xDB, 0x7, 0},
- {0xDC, 0, 0},
- {0xDD, 0, 0},
- {0xDE, 0x88, 1},
- {0xDF, 0, 0},
- {0xE0, 0x1f, 0},
- {0xE1, 0x20, 1},
- {0xE2, 0x1, 0},
- {0xE3, 0x30, 0},
- {0xE4, 0x70, 0},
- {0xE5, 0, 0},
- {0xE6, 0, 0},
- {0xE7, 0x33, 0},
- {0xE8, 0xf, 1},
- {0xE9, 0xf, 1},
- {0xEA, 0, 0},
- {0xEB, 0x11, 0},
- {0x105, 0x3c, 0},
- {0x106, 0x1, 1},
- {0x107, 0xa, 0},
- {0x10A, 0, 0},
- {0x10B, 0x40, 0},
- {0x10C, 0x40, 0},
- {0x10D, 0x88, 0},
- {0x10E, 0x10, 0},
- {0x10F, 0xf0, 0},
- {0x110, 0x10, 0},
- {0x111, 0xf0, 0},
- {0x114, 0x10, 0},
- {0x115, 0x55, 0},
- {0x116, 0x3f, 1},
- {0x117, 0x36, 1},
- {0x118, 0, 0},
- {0x119, 0, 0},
- {0x11A, 0, 0},
- {0x11B, 0x87, 0},
- {0x11C, 0x11, 0},
- {0x11D, 0, 0},
- {0x11E, 0x33, 0},
- {0x11F, 0x88, 0},
- {0x126, 0x20, 1},
- {0x127, 0x3f, 0},
- {0x128, 0x44, 0},
- {0x129, 0x8c, 0},
- {0x12A, 0x6c, 0},
- {0x12B, 0x22, 0},
- {0x12C, 0xbe, 0},
- {0x12D, 0x55, 0},
- {0x12F, 0xc, 0},
- {0x130, 0xaa, 0},
- {0x131, 0x2, 0},
- {0x132, 0, 0},
- {0x133, 0x10, 0},
- {0x134, 0x1, 0},
- {0x135, 0, 0},
- {0x136, 0, 0},
- {0x137, 0x80, 0},
- {0x138, 0x60, 0},
- {0x139, 0x44, 0},
- {0x13A, 0x55, 0},
- {0x13B, 0x1, 0},
- {0x13C, 0x55, 0},
- {0x13D, 0x1, 0},
- {0x13E, 0x5, 0},
- {0x13F, 0x55, 0},
- {0x140, 0x55, 0},
- {0x148, 0, 0},
- {0x149, 0, 0},
- {0x14A, 0, 0},
- {0x14B, 0, 0},
- {0x14C, 0, 0},
- {0x14D, 0, 0},
- {0x14E, 0, 0},
- {0x14F, 0, 0},
- {0x150, 0, 0},
- {0x154, 0xc, 0},
- {0x155, 0xc, 0},
- {0x156, 0xc, 0},
- {0x157, 0, 0},
- {0x158, 0x2b, 0},
- {0x159, 0x84, 0},
- {0x15A, 0x15, 0},
- {0x15B, 0xf, 0},
- {0x15C, 0, 0},
- {0x15D, 0, 0},
- {0x15E, 0, 1},
- {0x15F, 0, 1},
- {0x160, 0, 1},
- {0x161, 0, 1},
- {0x162, 0, 1},
- {0x163, 0, 1},
- {0x164, 0, 0},
- {0x165, 0, 0},
- {0x166, 0, 0},
- {0x167, 0, 0},
- {0x168, 0, 0},
- {0x169, 0, 0},
- {0x16A, 0, 1},
- {0x16B, 0, 1},
- {0x16C, 0, 1},
- {0x16D, 0, 0},
- {0x170, 0, 0},
- {0x171, 0x77, 0},
- {0x172, 0x77, 0},
- {0x173, 0x77, 0},
- {0x174, 0x77, 0},
- {0x175, 0, 0},
- {0x176, 0x3, 0},
- {0x177, 0x37, 0},
- {0x178, 0x3, 0},
- {0x179, 0, 0},
- {0x17B, 0x21, 0},
- {0x17C, 0, 0},
- {0x17D, 0xaa, 0},
- {0x17E, 0, 0},
- {0x190, 0, 0},
- {0x191, 0x77, 0},
- {0x192, 0x77, 0},
- {0x193, 0x77, 0},
- {0x194, 0x77, 0},
- {0x195, 0, 0},
- {0x196, 0x3, 0},
- {0x197, 0x37, 0},
- {0x198, 0x3, 0},
- {0x199, 0, 0},
- {0x19B, 0x21, 0},
- {0x19C, 0, 0},
- {0x19D, 0xaa, 0},
- {0x19E, 0, 0},
- {0x1A1, 0x2, 0},
- {0x1A2, 0xf, 0},
- {0x1A3, 0xf, 0},
- {0x1A4, 0, 1},
- {0x1A5, 0, 1},
- {0x1A6, 0, 1},
- {0x1A7, 0x2, 0},
- {0x1A8, 0xf, 0},
- {0x1A9, 0xf, 0},
- {0x1AA, 0, 1},
- {0x1AB, 0, 1},
- {0x1AC, 0, 1},
- {0x1AD, 0x84, 0},
- {0x1AE, 0x60, 0},
- {0x1AF, 0x47, 0},
- {0x1B0, 0x47, 0},
- {0x1B1, 0, 0},
- {0x1B2, 0, 0},
- {0x1B3, 0, 0},
- {0x1B4, 0, 0},
- {0x1B5, 0, 0},
- {0x1B6, 0, 0},
- {0x1B7, 0xc, 1},
- {0x1B8, 0, 0},
- {0x1B9, 0, 0},
- {0x1BA, 0, 0},
- {0x1BB, 0, 0},
- {0x1BC, 0, 0},
- {0x1BD, 0, 0},
- {0x1BE, 0, 0},
- {0x1BF, 0, 0},
- {0x1C0, 0, 0},
- {0x1C1, 0x1, 1},
- {0x1C2, 0x80, 1},
- {0x1C3, 0, 0},
- {0x1C4, 0, 0},
- {0x1C5, 0, 0},
- {0x1C6, 0, 0},
- {0x1C7, 0, 0},
- {0x1C8, 0, 0},
- {0x1C9, 0, 0},
- {0x1CA, 0, 0},
- {0xFFFF, 0, 0}
-};
-
-radio_20xx_regs_t regs_2057_rev5v1[] = {
- {0x00, 0x15, 1},
- {0x01, 0x57, 1},
- {0x02, 0x20, 1},
- {0x03, 0x1f, 0},
- {0x04, 0x4, 0},
- {0x05, 0x2, 0},
- {0x06, 0x1, 0},
- {0x07, 0x1, 0},
- {0x08, 0x1, 0},
- {0x09, 0x69, 0},
- {0x0A, 0x66, 0},
- {0x0B, 0x6, 0},
- {0x0C, 0x18, 0},
- {0x0D, 0x3, 0},
- {0x0E, 0x20, 0},
- {0x0F, 0x20, 0},
- {0x10, 0, 0},
- {0x11, 0x7c, 0},
- {0x12, 0x42, 0},
- {0x13, 0xbd, 0},
- {0x14, 0x7, 0},
- {0x15, 0x87, 0},
- {0x16, 0x8, 0},
- {0x17, 0x17, 0},
- {0x18, 0x7, 0},
- {0x19, 0, 0},
- {0x1A, 0x2, 0},
- {0x1B, 0x13, 0},
- {0x1C, 0x3e, 0},
- {0x1D, 0x3e, 0},
- {0x1E, 0x96, 0},
- {0x1F, 0x4, 0},
- {0x20, 0, 0},
- {0x21, 0, 0},
- {0x22, 0x17, 0},
- {0x23, 0x6, 1},
- {0x24, 0x1, 0},
- {0x25, 0x6, 0},
- {0x26, 0x4, 0},
- {0x27, 0xd, 0},
- {0x28, 0xd, 0},
- {0x29, 0x30, 0},
- {0x2A, 0x32, 0},
- {0x2B, 0x8, 0},
- {0x2C, 0x1c, 0},
- {0x2D, 0x2, 0},
- {0x2E, 0x4, 0},
- {0x2F, 0x7f, 0},
- {0x30, 0x27, 0},
- {0x31, 0, 1},
- {0x32, 0, 1},
- {0x33, 0, 1},
- {0x34, 0, 0},
- {0x35, 0x20, 0},
- {0x36, 0x18, 0},
- {0x37, 0x7, 0},
- {0x38, 0x66, 0},
- {0x39, 0x66, 0},
- {0x3C, 0xff, 0},
- {0x3D, 0xff, 0},
- {0x40, 0x16, 0},
- {0x41, 0x7, 0},
- {0x45, 0x3, 0},
- {0x46, 0x1, 0},
- {0x47, 0x7, 0},
- {0x4B, 0x66, 0},
- {0x4C, 0x66, 0},
- {0x4D, 0, 0},
- {0x4E, 0x4, 0},
- {0x4F, 0xc, 0},
- {0x50, 0, 0},
- {0x51, 0x70, 1},
- {0x56, 0x7, 0},
- {0x57, 0, 0},
- {0x58, 0, 0},
- {0x59, 0x88, 1},
- {0x5A, 0, 0},
- {0x5B, 0x1f, 0},
- {0x5C, 0x20, 1},
- {0x5D, 0x1, 0},
- {0x5E, 0x30, 0},
- {0x5F, 0x70, 0},
- {0x60, 0, 0},
- {0x61, 0, 0},
- {0x62, 0x33, 1},
- {0x63, 0xf, 1},
- {0x64, 0xf, 1},
- {0x65, 0, 0},
- {0x66, 0x11, 0},
- {0x80, 0x3c, 0},
- {0x81, 0x1, 1},
- {0x82, 0xa, 0},
- {0x85, 0, 0},
- {0x86, 0x40, 0},
- {0x87, 0x40, 0},
- {0x88, 0x88, 0},
- {0x89, 0x10, 0},
- {0x8A, 0xf0, 0},
- {0x8B, 0x10, 0},
- {0x8C, 0xf0, 0},
- {0x8F, 0x10, 0},
- {0x90, 0x55, 0},
- {0x91, 0x3f, 1},
- {0x92, 0x36, 1},
- {0x93, 0, 0},
- {0x94, 0, 0},
- {0x95, 0, 0},
- {0x96, 0x87, 0},
- {0x97, 0x11, 0},
- {0x98, 0, 0},
- {0x99, 0x33, 0},
- {0x9A, 0x88, 0},
- {0xA1, 0x20, 1},
- {0xA2, 0x3f, 0},
- {0xA3, 0x44, 0},
- {0xA4, 0x8c, 0},
- {0xA5, 0x6c, 0},
- {0xA6, 0x22, 0},
- {0xA7, 0xbe, 0},
- {0xA8, 0x55, 0},
- {0xAA, 0xc, 0},
- {0xAB, 0xaa, 0},
- {0xAC, 0x2, 0},
- {0xAD, 0, 0},
- {0xAE, 0x10, 0},
- {0xAF, 0x1, 0},
- {0xB0, 0, 0},
- {0xB1, 0, 0},
- {0xB2, 0x80, 0},
- {0xB3, 0x60, 0},
- {0xB4, 0x44, 0},
- {0xB5, 0x55, 0},
- {0xB6, 0x1, 0},
- {0xB7, 0x55, 0},
- {0xB8, 0x1, 0},
- {0xB9, 0x5, 0},
- {0xBA, 0x55, 0},
- {0xBB, 0x55, 0},
- {0xC3, 0, 0},
- {0xC4, 0, 0},
- {0xC5, 0, 0},
- {0xC6, 0, 0},
- {0xC7, 0, 0},
- {0xC8, 0, 0},
- {0xC9, 0x1, 1},
- {0xCA, 0, 0},
- {0xCB, 0, 0},
- {0xCD, 0, 0},
- {0xCE, 0x5e, 0},
- {0xCF, 0xc, 0},
- {0xD0, 0xc, 0},
- {0xD1, 0xc, 0},
- {0xD2, 0, 0},
- {0xD3, 0x2b, 0},
- {0xD4, 0xc, 0},
- {0xD5, 0, 0},
- {0xD6, 0x70, 1},
- {0xDB, 0x7, 0},
- {0xDC, 0, 0},
- {0xDD, 0, 0},
- {0xDE, 0x88, 1},
- {0xDF, 0, 0},
- {0xE0, 0x1f, 0},
- {0xE1, 0x20, 1},
- {0xE2, 0x1, 0},
- {0xE3, 0x30, 0},
- {0xE4, 0x70, 0},
- {0xE5, 0, 0},
- {0xE6, 0, 0},
- {0xE7, 0x33, 0},
- {0xE8, 0xf, 1},
- {0xE9, 0xf, 1},
- {0xEA, 0, 0},
- {0xEB, 0x11, 0},
- {0x105, 0x3c, 0},
- {0x106, 0x1, 1},
- {0x107, 0xa, 0},
- {0x10A, 0, 0},
- {0x10B, 0x40, 0},
- {0x10C, 0x40, 0},
- {0x10D, 0x88, 0},
- {0x10E, 0x10, 0},
- {0x10F, 0xf0, 0},
- {0x110, 0x10, 0},
- {0x111, 0xf0, 0},
- {0x114, 0x10, 0},
- {0x115, 0x55, 0},
- {0x116, 0x3f, 1},
- {0x117, 0x36, 1},
- {0x118, 0, 0},
- {0x119, 0, 0},
- {0x11A, 0, 0},
- {0x11B, 0x87, 0},
- {0x11C, 0x11, 0},
- {0x11D, 0, 0},
- {0x11E, 0x33, 0},
- {0x11F, 0x88, 0},
- {0x126, 0x20, 1},
- {0x127, 0x3f, 0},
- {0x128, 0x44, 0},
- {0x129, 0x8c, 0},
- {0x12A, 0x6c, 0},
- {0x12B, 0x22, 0},
- {0x12C, 0xbe, 0},
- {0x12D, 0x55, 0},
- {0x12F, 0xc, 0},
- {0x130, 0xaa, 0},
- {0x131, 0x2, 0},
- {0x132, 0, 0},
- {0x133, 0x10, 0},
- {0x134, 0x1, 0},
- {0x135, 0, 0},
- {0x136, 0, 0},
- {0x137, 0x80, 0},
- {0x138, 0x60, 0},
- {0x139, 0x44, 0},
- {0x13A, 0x55, 0},
- {0x13B, 0x1, 0},
- {0x13C, 0x55, 0},
- {0x13D, 0x1, 0},
- {0x13E, 0x5, 0},
- {0x13F, 0x55, 0},
- {0x140, 0x55, 0},
- {0x148, 0, 0},
- {0x149, 0, 0},
- {0x14A, 0, 0},
- {0x14B, 0, 0},
- {0x14C, 0, 0},
- {0x14D, 0, 0},
- {0x14E, 0x1, 1},
- {0x14F, 0, 0},
- {0x150, 0, 0},
- {0x154, 0xc, 0},
- {0x155, 0xc, 0},
- {0x156, 0xc, 0},
- {0x157, 0, 0},
- {0x158, 0x2b, 0},
- {0x159, 0x84, 0},
- {0x15A, 0x15, 0},
- {0x15B, 0xf, 0},
- {0x15C, 0, 0},
- {0x15D, 0, 0},
- {0x15E, 0, 1},
- {0x15F, 0, 1},
- {0x160, 0, 1},
- {0x161, 0, 1},
- {0x162, 0, 1},
- {0x163, 0, 1},
- {0x164, 0, 0},
- {0x165, 0, 0},
- {0x166, 0, 0},
- {0x167, 0, 0},
- {0x168, 0, 0},
- {0x169, 0, 0},
- {0x16A, 0, 1},
- {0x16B, 0, 1},
- {0x16C, 0, 1},
- {0x16D, 0, 0},
- {0x170, 0, 0},
- {0x171, 0x77, 0},
- {0x172, 0x77, 0},
- {0x173, 0x77, 0},
- {0x174, 0x77, 0},
- {0x175, 0, 0},
- {0x176, 0x3, 0},
- {0x177, 0x37, 0},
- {0x178, 0x3, 0},
- {0x179, 0, 0},
- {0x17B, 0x21, 0},
- {0x17C, 0, 0},
- {0x17D, 0xaa, 0},
- {0x17E, 0, 0},
- {0x190, 0, 0},
- {0x191, 0x77, 0},
- {0x192, 0x77, 0},
- {0x193, 0x77, 0},
- {0x194, 0x77, 0},
- {0x195, 0, 0},
- {0x196, 0x3, 0},
- {0x197, 0x37, 0},
- {0x198, 0x3, 0},
- {0x199, 0, 0},
- {0x19B, 0x21, 0},
- {0x19C, 0, 0},
- {0x19D, 0xaa, 0},
- {0x19E, 0, 0},
- {0x1A1, 0x2, 0},
- {0x1A2, 0xf, 0},
- {0x1A3, 0xf, 0},
- {0x1A4, 0, 1},
- {0x1A5, 0, 1},
- {0x1A6, 0, 1},
- {0x1A7, 0x2, 0},
- {0x1A8, 0xf, 0},
- {0x1A9, 0xf, 0},
- {0x1AA, 0, 1},
- {0x1AB, 0, 1},
- {0x1AC, 0, 1},
- {0x1AD, 0x84, 0},
- {0x1AE, 0x60, 0},
- {0x1AF, 0x47, 0},
- {0x1B0, 0x47, 0},
- {0x1B1, 0, 0},
- {0x1B2, 0, 0},
- {0x1B3, 0, 0},
- {0x1B4, 0, 0},
- {0x1B5, 0, 0},
- {0x1B6, 0, 0},
- {0x1B7, 0xc, 1},
- {0x1B8, 0, 0},
- {0x1B9, 0, 0},
- {0x1BA, 0, 0},
- {0x1BB, 0, 0},
- {0x1BC, 0, 0},
- {0x1BD, 0, 0},
- {0x1BE, 0, 0},
- {0x1BF, 0, 0},
- {0x1C0, 0, 0},
- {0x1C1, 0x1, 1},
- {0x1C2, 0x80, 1},
- {0x1C3, 0, 0},
- {0x1C4, 0, 0},
- {0x1C5, 0, 0},
- {0x1C6, 0, 0},
- {0x1C7, 0, 0},
- {0x1C8, 0, 0},
- {0x1C9, 0, 0},
- {0x1CA, 0, 0},
- {0xFFFF, 0, 0}
-};
-
-radio_20xx_regs_t regs_2057_rev7[] = {
- {0x00, 0, 1},
- {0x01, 0x57, 1},
- {0x02, 0x20, 1},
- {0x03, 0x1f, 0},
- {0x04, 0x4, 0},
- {0x05, 0x2, 0},
- {0x06, 0x1, 0},
- {0x07, 0x1, 0},
- {0x08, 0x1, 0},
- {0x09, 0x69, 0},
- {0x0A, 0x66, 0},
- {0x0B, 0x6, 0},
- {0x0C, 0x18, 0},
- {0x0D, 0x3, 0},
- {0x0E, 0x20, 0},
- {0x0F, 0x20, 0},
- {0x10, 0, 0},
- {0x11, 0x7c, 0},
- {0x12, 0x42, 0},
- {0x13, 0xbd, 0},
- {0x14, 0x7, 0},
- {0x15, 0x87, 0},
- {0x16, 0x8, 0},
- {0x17, 0x17, 0},
- {0x18, 0x7, 0},
- {0x19, 0, 0},
- {0x1A, 0x2, 0},
- {0x1B, 0x13, 0},
- {0x1C, 0x3e, 0},
- {0x1D, 0x3e, 0},
- {0x1E, 0x96, 0},
- {0x1F, 0x4, 0},
- {0x20, 0, 0},
- {0x21, 0, 0},
- {0x22, 0x17, 0},
- {0x23, 0x6, 0},
- {0x24, 0x1, 0},
- {0x25, 0x6, 0},
- {0x26, 0x4, 0},
- {0x27, 0xd, 0},
- {0x28, 0xd, 0},
- {0x29, 0x30, 0},
- {0x2A, 0x32, 0},
- {0x2B, 0x8, 0},
- {0x2C, 0x1c, 0},
- {0x2D, 0x2, 0},
- {0x2E, 0x4, 0},
- {0x2F, 0x7f, 0},
- {0x30, 0x27, 0},
- {0x31, 0, 1},
- {0x32, 0, 1},
- {0x33, 0, 1},
- {0x34, 0, 0},
- {0x35, 0x20, 0},
- {0x36, 0x18, 0},
- {0x37, 0x7, 0},
- {0x38, 0x66, 0},
- {0x39, 0x66, 0},
- {0x3A, 0x66, 0},
- {0x3B, 0x66, 0},
- {0x3C, 0xff, 0},
- {0x3D, 0xff, 0},
- {0x3E, 0xff, 0},
- {0x3F, 0xff, 0},
- {0x40, 0x16, 0},
- {0x41, 0x7, 0},
- {0x42, 0x19, 0},
- {0x43, 0x7, 0},
- {0x44, 0x6, 0},
- {0x45, 0x3, 0},
- {0x46, 0x1, 0},
- {0x47, 0x7, 0},
- {0x48, 0x33, 0},
- {0x49, 0x5, 0},
- {0x4A, 0x77, 0},
- {0x4B, 0x66, 0},
- {0x4C, 0x66, 0},
- {0x4D, 0, 0},
- {0x4E, 0x4, 0},
- {0x4F, 0xc, 0},
- {0x50, 0, 0},
- {0x51, 0x70, 1},
- {0x56, 0x7, 0},
- {0x57, 0, 0},
- {0x58, 0, 0},
- {0x59, 0x88, 1},
- {0x5A, 0, 0},
- {0x5B, 0x1f, 0},
- {0x5C, 0x20, 1},
- {0x5D, 0x1, 0},
- {0x5E, 0x30, 0},
- {0x5F, 0x70, 0},
- {0x60, 0, 0},
- {0x61, 0, 0},
- {0x62, 0x33, 1},
- {0x63, 0xf, 1},
- {0x64, 0x13, 1},
- {0x65, 0, 0},
- {0x66, 0xee, 1},
- {0x69, 0, 0},
- {0x6A, 0x7e, 0},
- {0x6B, 0x3f, 0},
- {0x6C, 0x7f, 0},
- {0x6D, 0x78, 0},
- {0x6E, 0x58, 1},
- {0x6F, 0x88, 0},
- {0x70, 0x8, 0},
- {0x71, 0xf, 0},
- {0x72, 0xbc, 0},
- {0x73, 0x8, 0},
- {0x74, 0x60, 0},
- {0x75, 0x13, 1},
- {0x76, 0x70, 0},
- {0x77, 0, 0},
- {0x78, 0, 0},
- {0x79, 0, 0},
- {0x7A, 0x33, 0},
- {0x7B, 0x13, 1},
- {0x7C, 0x14, 1},
- {0x7D, 0xee, 1},
- {0x80, 0x3c, 0},
- {0x81, 0x1, 1},
- {0x82, 0xa, 0},
- {0x83, 0x9d, 0},
- {0x84, 0xa, 0},
- {0x85, 0, 0},
- {0x86, 0x40, 0},
- {0x87, 0x40, 0},
- {0x88, 0x88, 0},
- {0x89, 0x10, 0},
- {0x8A, 0xf0, 0},
- {0x8B, 0x10, 0},
- {0x8C, 0xf0, 0},
- {0x8D, 0, 0},
- {0x8E, 0, 0},
- {0x8F, 0x10, 0},
- {0x90, 0x55, 0},
- {0x91, 0x3f, 1},
- {0x92, 0x36, 1},
- {0x93, 0, 0},
- {0x94, 0, 0},
- {0x95, 0, 0},
- {0x96, 0x87, 0},
- {0x97, 0x11, 0},
- {0x98, 0, 0},
- {0x99, 0x33, 0},
- {0x9A, 0x88, 0},
- {0x9B, 0, 0},
- {0x9C, 0x87, 0},
- {0x9D, 0x11, 0},
- {0x9E, 0, 0},
- {0x9F, 0x33, 0},
- {0xA0, 0x88, 0},
- {0xA1, 0x20, 1},
- {0xA2, 0x3f, 0},
- {0xA3, 0x44, 0},
- {0xA4, 0x8c, 0},
- {0xA5, 0x6c, 0},
- {0xA6, 0x22, 0},
- {0xA7, 0xbe, 0},
- {0xA8, 0x55, 0},
- {0xAA, 0xc, 0},
- {0xAB, 0xaa, 0},
- {0xAC, 0x2, 0},
- {0xAD, 0, 0},
- {0xAE, 0x10, 0},
- {0xAF, 0x1, 0},
- {0xB0, 0, 0},
- {0xB1, 0, 0},
- {0xB2, 0x80, 0},
- {0xB3, 0x60, 0},
- {0xB4, 0x44, 0},
- {0xB5, 0x55, 0},
- {0xB6, 0x1, 0},
- {0xB7, 0x55, 0},
- {0xB8, 0x1, 0},
- {0xB9, 0x5, 0},
- {0xBA, 0x55, 0},
- {0xBB, 0x55, 0},
- {0xC1, 0, 0},
- {0xC2, 0, 0},
- {0xC3, 0, 0},
- {0xC4, 0, 0},
- {0xC5, 0, 0},
- {0xC6, 0, 0},
- {0xC7, 0, 0},
- {0xC8, 0, 0},
- {0xC9, 0, 0},
- {0xCA, 0, 0},
- {0xCB, 0, 0},
- {0xCC, 0, 0},
- {0xCD, 0, 0},
- {0xCE, 0x5e, 0},
- {0xCF, 0xc, 0},
- {0xD0, 0xc, 0},
- {0xD1, 0xc, 0},
- {0xD2, 0, 0},
- {0xD3, 0x2b, 0},
- {0xD4, 0xc, 0},
- {0xD5, 0, 0},
- {0xD6, 0x70, 1},
- {0xDB, 0x7, 0},
- {0xDC, 0, 0},
- {0xDD, 0, 0},
- {0xDE, 0x88, 1},
- {0xDF, 0, 0},
- {0xE0, 0x1f, 0},
- {0xE1, 0x20, 1},
- {0xE2, 0x1, 0},
- {0xE3, 0x30, 0},
- {0xE4, 0x70, 0},
- {0xE5, 0, 0},
- {0xE6, 0, 0},
- {0xE7, 0x33, 0},
- {0xE8, 0xf, 1},
- {0xE9, 0x13, 1},
- {0xEA, 0, 0},
- {0xEB, 0xee, 1},
- {0xEE, 0, 0},
- {0xEF, 0x7e, 0},
- {0xF0, 0x3f, 0},
- {0xF1, 0x7f, 0},
- {0xF2, 0x78, 0},
- {0xF3, 0x58, 1},
- {0xF4, 0x88, 0},
- {0xF5, 0x8, 0},
- {0xF6, 0xf, 0},
- {0xF7, 0xbc, 0},
- {0xF8, 0x8, 0},
- {0xF9, 0x60, 0},
- {0xFA, 0x13, 1},
- {0xFB, 0x70, 0},
- {0xFC, 0, 0},
- {0xFD, 0, 0},
- {0xFE, 0, 0},
- {0xFF, 0x33, 0},
- {0x100, 0x13, 1},
- {0x101, 0x14, 1},
- {0x102, 0xee, 1},
- {0x105, 0x3c, 0},
- {0x106, 0x1, 1},
- {0x107, 0xa, 0},
- {0x108, 0x9d, 0},
- {0x109, 0xa, 0},
- {0x10A, 0, 0},
- {0x10B, 0x40, 0},
- {0x10C, 0x40, 0},
- {0x10D, 0x88, 0},
- {0x10E, 0x10, 0},
- {0x10F, 0xf0, 0},
- {0x110, 0x10, 0},
- {0x111, 0xf0, 0},
- {0x112, 0, 0},
- {0x113, 0, 0},
- {0x114, 0x10, 0},
- {0x115, 0x55, 0},
- {0x116, 0x3f, 1},
- {0x117, 0x36, 1},
- {0x118, 0, 0},
- {0x119, 0, 0},
- {0x11A, 0, 0},
- {0x11B, 0x87, 0},
- {0x11C, 0x11, 0},
- {0x11D, 0, 0},
- {0x11E, 0x33, 0},
- {0x11F, 0x88, 0},
- {0x120, 0, 0},
- {0x121, 0x87, 0},
- {0x122, 0x11, 0},
- {0x123, 0, 0},
- {0x124, 0x33, 0},
- {0x125, 0x88, 0},
- {0x126, 0x20, 1},
- {0x127, 0x3f, 0},
- {0x128, 0x44, 0},
- {0x129, 0x8c, 0},
- {0x12A, 0x6c, 0},
- {0x12B, 0x22, 0},
- {0x12C, 0xbe, 0},
- {0x12D, 0x55, 0},
- {0x12F, 0xc, 0},
- {0x130, 0xaa, 0},
- {0x131, 0x2, 0},
- {0x132, 0, 0},
- {0x133, 0x10, 0},
- {0x134, 0x1, 0},
- {0x135, 0, 0},
- {0x136, 0, 0},
- {0x137, 0x80, 0},
- {0x138, 0x60, 0},
- {0x139, 0x44, 0},
- {0x13A, 0x55, 0},
- {0x13B, 0x1, 0},
- {0x13C, 0x55, 0},
- {0x13D, 0x1, 0},
- {0x13E, 0x5, 0},
- {0x13F, 0x55, 0},
- {0x140, 0x55, 0},
- {0x146, 0, 0},
- {0x147, 0, 0},
- {0x148, 0, 0},
- {0x149, 0, 0},
- {0x14A, 0, 0},
- {0x14B, 0, 0},
- {0x14C, 0, 0},
- {0x14D, 0, 0},
- {0x14E, 0, 0},
- {0x14F, 0, 0},
- {0x150, 0, 0},
- {0x151, 0, 0},
- {0x154, 0xc, 0},
- {0x155, 0xc, 0},
- {0x156, 0xc, 0},
- {0x157, 0, 0},
- {0x158, 0x2b, 0},
- {0x159, 0x84, 0},
- {0x15A, 0x15, 0},
- {0x15B, 0xf, 0},
- {0x15C, 0, 0},
- {0x15D, 0, 0},
- {0x15E, 0, 1},
- {0x15F, 0, 1},
- {0x160, 0, 1},
- {0x161, 0, 1},
- {0x162, 0, 1},
- {0x163, 0, 1},
- {0x164, 0, 0},
- {0x165, 0, 0},
- {0x166, 0, 0},
- {0x167, 0, 0},
- {0x168, 0, 0},
- {0x169, 0, 0},
- {0x16A, 0, 1},
- {0x16B, 0, 1},
- {0x16C, 0, 1},
- {0x16D, 0, 0},
- {0x170, 0, 0},
- {0x171, 0x77, 0},
- {0x172, 0x77, 0},
- {0x173, 0x77, 0},
- {0x174, 0x77, 0},
- {0x175, 0, 0},
- {0x176, 0x3, 0},
- {0x177, 0x37, 0},
- {0x178, 0x3, 0},
- {0x179, 0, 0},
- {0x17A, 0x21, 0},
- {0x17B, 0x21, 0},
- {0x17C, 0, 0},
- {0x17D, 0xaa, 0},
- {0x17E, 0, 0},
- {0x17F, 0xaa, 0},
- {0x180, 0, 0},
- {0x190, 0, 0},
- {0x191, 0x77, 0},
- {0x192, 0x77, 0},
- {0x193, 0x77, 0},
- {0x194, 0x77, 0},
- {0x195, 0, 0},
- {0x196, 0x3, 0},
- {0x197, 0x37, 0},
- {0x198, 0x3, 0},
- {0x199, 0, 0},
- {0x19A, 0x21, 0},
- {0x19B, 0x21, 0},
- {0x19C, 0, 0},
- {0x19D, 0xaa, 0},
- {0x19E, 0, 0},
- {0x19F, 0xaa, 0},
- {0x1A0, 0, 0},
- {0x1A1, 0x2, 0},
- {0x1A2, 0xf, 0},
- {0x1A3, 0xf, 0},
- {0x1A4, 0, 1},
- {0x1A5, 0, 1},
- {0x1A6, 0, 1},
- {0x1A7, 0x2, 0},
- {0x1A8, 0xf, 0},
- {0x1A9, 0xf, 0},
- {0x1AA, 0, 1},
- {0x1AB, 0, 1},
- {0x1AC, 0, 1},
- {0x1AD, 0x84, 0},
- {0x1AE, 0x60, 0},
- {0x1AF, 0x47, 0},
- {0x1B0, 0x47, 0},
- {0x1B1, 0, 0},
- {0x1B2, 0, 0},
- {0x1B3, 0, 0},
- {0x1B4, 0, 0},
- {0x1B5, 0, 0},
- {0x1B6, 0, 0},
- {0x1B7, 0x5, 1},
- {0x1B8, 0, 0},
- {0x1B9, 0, 0},
- {0x1BA, 0, 0},
- {0x1BB, 0, 0},
- {0x1BC, 0, 0},
- {0x1BD, 0, 0},
- {0x1BE, 0, 0},
- {0x1BF, 0, 0},
- {0x1C0, 0, 0},
- {0x1C1, 0, 0},
- {0x1C2, 0xa0, 1},
- {0x1C3, 0, 0},
- {0x1C4, 0, 0},
- {0x1C5, 0, 0},
- {0x1C6, 0, 0},
- {0x1C7, 0, 0},
- {0x1C8, 0, 0},
- {0x1C9, 0, 0},
- {0x1CA, 0, 0},
- {0xFFFF, 0, 0}
-};
-
-radio_20xx_regs_t regs_2057_rev8[] = {
- {0x00, 0x8, 1},
- {0x01, 0x57, 1},
- {0x02, 0x20, 1},
- {0x03, 0x1f, 0},
- {0x04, 0x4, 0},
- {0x05, 0x2, 0},
- {0x06, 0x1, 0},
- {0x07, 0x1, 0},
- {0x08, 0x1, 0},
- {0x09, 0x69, 0},
- {0x0A, 0x66, 0},
- {0x0B, 0x6, 0},
- {0x0C, 0x18, 0},
- {0x0D, 0x3, 0},
- {0x0E, 0x20, 0},
- {0x0F, 0x20, 0},
- {0x10, 0, 0},
- {0x11, 0x7c, 0},
- {0x12, 0x42, 0},
- {0x13, 0xbd, 0},
- {0x14, 0x7, 0},
- {0x15, 0x87, 0},
- {0x16, 0x8, 0},
- {0x17, 0x17, 0},
- {0x18, 0x7, 0},
- {0x19, 0, 0},
- {0x1A, 0x2, 0},
- {0x1B, 0x13, 0},
- {0x1C, 0x3e, 0},
- {0x1D, 0x3e, 0},
- {0x1E, 0x96, 0},
- {0x1F, 0x4, 0},
- {0x20, 0, 0},
- {0x21, 0, 0},
- {0x22, 0x17, 0},
- {0x23, 0x6, 0},
- {0x24, 0x1, 0},
- {0x25, 0x6, 0},
- {0x26, 0x4, 0},
- {0x27, 0xd, 0},
- {0x28, 0xd, 0},
- {0x29, 0x30, 0},
- {0x2A, 0x32, 0},
- {0x2B, 0x8, 0},
- {0x2C, 0x1c, 0},
- {0x2D, 0x2, 0},
- {0x2E, 0x4, 0},
- {0x2F, 0x7f, 0},
- {0x30, 0x27, 0},
- {0x31, 0, 1},
- {0x32, 0, 1},
- {0x33, 0, 1},
- {0x34, 0, 0},
- {0x35, 0x20, 0},
- {0x36, 0x18, 0},
- {0x37, 0x7, 0},
- {0x38, 0x66, 0},
- {0x39, 0x66, 0},
- {0x3A, 0x66, 0},
- {0x3B, 0x66, 0},
- {0x3C, 0xff, 0},
- {0x3D, 0xff, 0},
- {0x3E, 0xff, 0},
- {0x3F, 0xff, 0},
- {0x40, 0x16, 0},
- {0x41, 0x7, 0},
- {0x42, 0x19, 0},
- {0x43, 0x7, 0},
- {0x44, 0x6, 0},
- {0x45, 0x3, 0},
- {0x46, 0x1, 0},
- {0x47, 0x7, 0},
- {0x48, 0x33, 0},
- {0x49, 0x5, 0},
- {0x4A, 0x77, 0},
- {0x4B, 0x66, 0},
- {0x4C, 0x66, 0},
- {0x4D, 0, 0},
- {0x4E, 0x4, 0},
- {0x4F, 0xc, 0},
- {0x50, 0, 0},
- {0x51, 0x70, 1},
- {0x56, 0x7, 0},
- {0x57, 0, 0},
- {0x58, 0, 0},
- {0x59, 0x88, 1},
- {0x5A, 0, 0},
- {0x5B, 0x1f, 0},
- {0x5C, 0x20, 1},
- {0x5D, 0x1, 0},
- {0x5E, 0x30, 0},
- {0x5F, 0x70, 0},
- {0x60, 0, 0},
- {0x61, 0, 0},
- {0x62, 0x33, 1},
- {0x63, 0xf, 1},
- {0x64, 0xf, 1},
- {0x65, 0, 0},
- {0x66, 0x11, 0},
- {0x69, 0, 0},
- {0x6A, 0x7e, 0},
- {0x6B, 0x3f, 0},
- {0x6C, 0x7f, 0},
- {0x6D, 0x78, 0},
- {0x6E, 0x58, 1},
- {0x6F, 0x88, 0},
- {0x70, 0x8, 0},
- {0x71, 0xf, 0},
- {0x72, 0xbc, 0},
- {0x73, 0x8, 0},
- {0x74, 0x60, 0},
- {0x75, 0x13, 1},
- {0x76, 0x70, 0},
- {0x77, 0, 0},
- {0x78, 0, 0},
- {0x79, 0, 0},
- {0x7A, 0x33, 0},
- {0x7B, 0x13, 1},
- {0x7C, 0xf, 1},
- {0x7D, 0xee, 1},
- {0x80, 0x3c, 0},
- {0x81, 0x1, 1},
- {0x82, 0xa, 0},
- {0x83, 0x9d, 0},
- {0x84, 0xa, 0},
- {0x85, 0, 0},
- {0x86, 0x40, 0},
- {0x87, 0x40, 0},
- {0x88, 0x88, 0},
- {0x89, 0x10, 0},
- {0x8A, 0xf0, 0},
- {0x8B, 0x10, 0},
- {0x8C, 0xf0, 0},
- {0x8D, 0, 0},
- {0x8E, 0, 0},
- {0x8F, 0x10, 0},
- {0x90, 0x55, 0},
- {0x91, 0x3f, 1},
- {0x92, 0x36, 1},
- {0x93, 0, 0},
- {0x94, 0, 0},
- {0x95, 0, 0},
- {0x96, 0x87, 0},
- {0x97, 0x11, 0},
- {0x98, 0, 0},
- {0x99, 0x33, 0},
- {0x9A, 0x88, 0},
- {0x9B, 0, 0},
- {0x9C, 0x87, 0},
- {0x9D, 0x11, 0},
- {0x9E, 0, 0},
- {0x9F, 0x33, 0},
- {0xA0, 0x88, 0},
- {0xA1, 0x20, 1},
- {0xA2, 0x3f, 0},
- {0xA3, 0x44, 0},
- {0xA4, 0x8c, 0},
- {0xA5, 0x6c, 0},
- {0xA6, 0x22, 0},
- {0xA7, 0xbe, 0},
- {0xA8, 0x55, 0},
- {0xAA, 0xc, 0},
- {0xAB, 0xaa, 0},
- {0xAC, 0x2, 0},
- {0xAD, 0, 0},
- {0xAE, 0x10, 0},
- {0xAF, 0x1, 0},
- {0xB0, 0, 0},
- {0xB1, 0, 0},
- {0xB2, 0x80, 0},
- {0xB3, 0x60, 0},
- {0xB4, 0x44, 0},
- {0xB5, 0x55, 0},
- {0xB6, 0x1, 0},
- {0xB7, 0x55, 0},
- {0xB8, 0x1, 0},
- {0xB9, 0x5, 0},
- {0xBA, 0x55, 0},
- {0xBB, 0x55, 0},
- {0xC1, 0, 0},
- {0xC2, 0, 0},
- {0xC3, 0, 0},
- {0xC4, 0, 0},
- {0xC5, 0, 0},
- {0xC6, 0, 0},
- {0xC7, 0, 0},
- {0xC8, 0, 0},
- {0xC9, 0x1, 1},
- {0xCA, 0, 0},
- {0xCB, 0, 0},
- {0xCC, 0, 0},
- {0xCD, 0, 0},
- {0xCE, 0x5e, 0},
- {0xCF, 0xc, 0},
- {0xD0, 0xc, 0},
- {0xD1, 0xc, 0},
- {0xD2, 0, 0},
- {0xD3, 0x2b, 0},
- {0xD4, 0xc, 0},
- {0xD5, 0, 0},
- {0xD6, 0x70, 1},
- {0xDB, 0x7, 0},
- {0xDC, 0, 0},
- {0xDD, 0, 0},
- {0xDE, 0x88, 1},
- {0xDF, 0, 0},
- {0xE0, 0x1f, 0},
- {0xE1, 0x20, 1},
- {0xE2, 0x1, 0},
- {0xE3, 0x30, 0},
- {0xE4, 0x70, 0},
- {0xE5, 0, 0},
- {0xE6, 0, 0},
- {0xE7, 0x33, 0},
- {0xE8, 0xf, 1},
- {0xE9, 0xf, 1},
- {0xEA, 0, 0},
- {0xEB, 0x11, 0},
- {0xEE, 0, 0},
- {0xEF, 0x7e, 0},
- {0xF0, 0x3f, 0},
- {0xF1, 0x7f, 0},
- {0xF2, 0x78, 0},
- {0xF3, 0x58, 1},
- {0xF4, 0x88, 0},
- {0xF5, 0x8, 0},
- {0xF6, 0xf, 0},
- {0xF7, 0xbc, 0},
- {0xF8, 0x8, 0},
- {0xF9, 0x60, 0},
- {0xFA, 0x13, 1},
- {0xFB, 0x70, 0},
- {0xFC, 0, 0},
- {0xFD, 0, 0},
- {0xFE, 0, 0},
- {0xFF, 0x33, 0},
- {0x100, 0x13, 1},
- {0x101, 0xf, 1},
- {0x102, 0xee, 1},
- {0x105, 0x3c, 0},
- {0x106, 0x1, 1},
- {0x107, 0xa, 0},
- {0x108, 0x9d, 0},
- {0x109, 0xa, 0},
- {0x10A, 0, 0},
- {0x10B, 0x40, 0},
- {0x10C, 0x40, 0},
- {0x10D, 0x88, 0},
- {0x10E, 0x10, 0},
- {0x10F, 0xf0, 0},
- {0x110, 0x10, 0},
- {0x111, 0xf0, 0},
- {0x112, 0, 0},
- {0x113, 0, 0},
- {0x114, 0x10, 0},
- {0x115, 0x55, 0},
- {0x116, 0x3f, 1},
- {0x117, 0x36, 1},
- {0x118, 0, 0},
- {0x119, 0, 0},
- {0x11A, 0, 0},
- {0x11B, 0x87, 0},
- {0x11C, 0x11, 0},
- {0x11D, 0, 0},
- {0x11E, 0x33, 0},
- {0x11F, 0x88, 0},
- {0x120, 0, 0},
- {0x121, 0x87, 0},
- {0x122, 0x11, 0},
- {0x123, 0, 0},
- {0x124, 0x33, 0},
- {0x125, 0x88, 0},
- {0x126, 0x20, 1},
- {0x127, 0x3f, 0},
- {0x128, 0x44, 0},
- {0x129, 0x8c, 0},
- {0x12A, 0x6c, 0},
- {0x12B, 0x22, 0},
- {0x12C, 0xbe, 0},
- {0x12D, 0x55, 0},
- {0x12F, 0xc, 0},
- {0x130, 0xaa, 0},
- {0x131, 0x2, 0},
- {0x132, 0, 0},
- {0x133, 0x10, 0},
- {0x134, 0x1, 0},
- {0x135, 0, 0},
- {0x136, 0, 0},
- {0x137, 0x80, 0},
- {0x138, 0x60, 0},
- {0x139, 0x44, 0},
- {0x13A, 0x55, 0},
- {0x13B, 0x1, 0},
- {0x13C, 0x55, 0},
- {0x13D, 0x1, 0},
- {0x13E, 0x5, 0},
- {0x13F, 0x55, 0},
- {0x140, 0x55, 0},
- {0x146, 0, 0},
- {0x147, 0, 0},
- {0x148, 0, 0},
- {0x149, 0, 0},
- {0x14A, 0, 0},
- {0x14B, 0, 0},
- {0x14C, 0, 0},
- {0x14D, 0, 0},
- {0x14E, 0x1, 1},
- {0x14F, 0, 0},
- {0x150, 0, 0},
- {0x151, 0, 0},
- {0x154, 0xc, 0},
- {0x155, 0xc, 0},
- {0x156, 0xc, 0},
- {0x157, 0, 0},
- {0x158, 0x2b, 0},
- {0x159, 0x84, 0},
- {0x15A, 0x15, 0},
- {0x15B, 0xf, 0},
- {0x15C, 0, 0},
- {0x15D, 0, 0},
- {0x15E, 0, 1},
- {0x15F, 0, 1},
- {0x160, 0, 1},
- {0x161, 0, 1},
- {0x162, 0, 1},
- {0x163, 0, 1},
- {0x164, 0, 0},
- {0x165, 0, 0},
- {0x166, 0, 0},
- {0x167, 0, 0},
- {0x168, 0, 0},
- {0x169, 0, 0},
- {0x16A, 0, 1},
- {0x16B, 0, 1},
- {0x16C, 0, 1},
- {0x16D, 0, 0},
- {0x170, 0, 0},
- {0x171, 0x77, 0},
- {0x172, 0x77, 0},
- {0x173, 0x77, 0},
- {0x174, 0x77, 0},
- {0x175, 0, 0},
- {0x176, 0x3, 0},
- {0x177, 0x37, 0},
- {0x178, 0x3, 0},
- {0x179, 0, 0},
- {0x17A, 0x21, 0},
- {0x17B, 0x21, 0},
- {0x17C, 0, 0},
- {0x17D, 0xaa, 0},
- {0x17E, 0, 0},
- {0x17F, 0xaa, 0},
- {0x180, 0, 0},
- {0x190, 0, 0},
- {0x191, 0x77, 0},
- {0x192, 0x77, 0},
- {0x193, 0x77, 0},
- {0x194, 0x77, 0},
- {0x195, 0, 0},
- {0x196, 0x3, 0},
- {0x197, 0x37, 0},
- {0x198, 0x3, 0},
- {0x199, 0, 0},
- {0x19A, 0x21, 0},
- {0x19B, 0x21, 0},
- {0x19C, 0, 0},
- {0x19D, 0xaa, 0},
- {0x19E, 0, 0},
- {0x19F, 0xaa, 0},
- {0x1A0, 0, 0},
- {0x1A1, 0x2, 0},
- {0x1A2, 0xf, 0},
- {0x1A3, 0xf, 0},
- {0x1A4, 0, 1},
- {0x1A5, 0, 1},
- {0x1A6, 0, 1},
- {0x1A7, 0x2, 0},
- {0x1A8, 0xf, 0},
- {0x1A9, 0xf, 0},
- {0x1AA, 0, 1},
- {0x1AB, 0, 1},
- {0x1AC, 0, 1},
- {0x1AD, 0x84, 0},
- {0x1AE, 0x60, 0},
- {0x1AF, 0x47, 0},
- {0x1B0, 0x47, 0},
- {0x1B1, 0, 0},
- {0x1B2, 0, 0},
- {0x1B3, 0, 0},
- {0x1B4, 0, 0},
- {0x1B5, 0, 0},
- {0x1B6, 0, 0},
- {0x1B7, 0x5, 1},
- {0x1B8, 0, 0},
- {0x1B9, 0, 0},
- {0x1BA, 0, 0},
- {0x1BB, 0, 0},
- {0x1BC, 0, 0},
- {0x1BD, 0, 0},
- {0x1BE, 0, 0},
- {0x1BF, 0, 0},
- {0x1C0, 0, 0},
- {0x1C1, 0, 0},
- {0x1C2, 0xa0, 1},
- {0x1C3, 0, 0},
- {0x1C4, 0, 0},
- {0x1C5, 0, 0},
- {0x1C6, 0, 0},
- {0x1C7, 0, 0},
- {0x1C8, 0, 0},
- {0x1C9, 0, 0},
- {0x1CA, 0, 0},
- {0xFFFF, 0, 0}
-};
-
-static s16 nphy_def_lnagains[] = { -2, 10, 19, 25 };
-
-static s32 nphy_lnagain_est0[] = { -315, 40370 };
-static s32 nphy_lnagain_est1[] = { -224, 23242 };
-
-static const u16 tbl_iqcal_gainparams_nphy[2][NPHY_IQCAL_NUMGAINS][8] = {
- {
- {0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69},
- {0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69},
- {0x710, 7, 1, 0, 0x68, 0x68, 0x68, 0x68},
- {0x720, 7, 2, 0, 0x67, 0x67, 0x67, 0x67},
- {0x730, 7, 3, 0, 0x66, 0x66, 0x66, 0x66},
- {0x740, 7, 4, 0, 0x65, 0x65, 0x65, 0x65},
- {0x741, 7, 4, 1, 0x65, 0x65, 0x65, 0x65},
- {0x742, 7, 4, 2, 0x65, 0x65, 0x65, 0x65},
- {0x743, 7, 4, 3, 0x65, 0x65, 0x65, 0x65}
- },
- {
- {0x000, 7, 0, 0, 0x79, 0x79, 0x79, 0x79},
- {0x700, 7, 0, 0, 0x79, 0x79, 0x79, 0x79},
- {0x710, 7, 1, 0, 0x79, 0x79, 0x79, 0x79},
- {0x720, 7, 2, 0, 0x78, 0x78, 0x78, 0x78},
- {0x730, 7, 3, 0, 0x78, 0x78, 0x78, 0x78},
- {0x740, 7, 4, 0, 0x78, 0x78, 0x78, 0x78},
- {0x741, 7, 4, 1, 0x78, 0x78, 0x78, 0x78},
- {0x742, 7, 4, 2, 0x78, 0x78, 0x78, 0x78},
- {0x743, 7, 4, 3, 0x78, 0x78, 0x78, 0x78}
- }
-};
-
-static const u32 nphy_tpc_txgain[] = {
- 0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42,
- 0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44,
- 0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844,
- 0x03c82842, 0x03c42b44, 0x03c42b42, 0x03c42a44,
- 0x03c42a42, 0x03c42944, 0x03c42942, 0x03c42844,
- 0x03c42842, 0x03c42744, 0x03c42742, 0x03c42644,
- 0x03c42642, 0x03c42544, 0x03c42542, 0x03c42444,
- 0x03c42442, 0x03c02b44, 0x03c02b42, 0x03c02a44,
- 0x03c02a42, 0x03c02944, 0x03c02942, 0x03c02844,
- 0x03c02842, 0x03c02744, 0x03c02742, 0x03b02b44,
- 0x03b02b42, 0x03b02a44, 0x03b02a42, 0x03b02944,
- 0x03b02942, 0x03b02844, 0x03b02842, 0x03b02744,
- 0x03b02742, 0x03b02644, 0x03b02642, 0x03b02544,
- 0x03b02542, 0x03a02b44, 0x03a02b42, 0x03a02a44,
- 0x03a02a42, 0x03a02944, 0x03a02942, 0x03a02844,
- 0x03a02842, 0x03a02744, 0x03a02742, 0x03902b44,
- 0x03902b42, 0x03902a44, 0x03902a42, 0x03902944,
- 0x03902942, 0x03902844, 0x03902842, 0x03902744,
- 0x03902742, 0x03902644, 0x03902642, 0x03902544,
- 0x03902542, 0x03802b44, 0x03802b42, 0x03802a44,
- 0x03802a42, 0x03802944, 0x03802942, 0x03802844,
- 0x03802842, 0x03802744, 0x03802742, 0x03802644,
- 0x03802642, 0x03802544, 0x03802542, 0x03802444,
- 0x03802442, 0x03802344, 0x03802342, 0x03802244,
- 0x03802242, 0x03802144, 0x03802142, 0x03802044,
- 0x03802042, 0x03801f44, 0x03801f42, 0x03801e44,
- 0x03801e42, 0x03801d44, 0x03801d42, 0x03801c44,
- 0x03801c42, 0x03801b44, 0x03801b42, 0x03801a44,
- 0x03801a42, 0x03801944, 0x03801942, 0x03801844,
- 0x03801842, 0x03801744, 0x03801742, 0x03801644,
- 0x03801642, 0x03801544, 0x03801542, 0x03801444,
- 0x03801442, 0x03801344, 0x03801342, 0x00002b00
-};
-
-static const u16 nphy_tpc_loscale[] = {
- 256, 256, 271, 271, 287, 256, 256, 271,
- 271, 287, 287, 304, 304, 256, 256, 271,
- 271, 287, 287, 304, 304, 322, 322, 341,
- 341, 362, 362, 383, 383, 256, 256, 271,
- 271, 287, 287, 304, 304, 322, 322, 256,
- 256, 271, 271, 287, 287, 304, 304, 322,
- 322, 341, 341, 362, 362, 256, 256, 271,
- 271, 287, 287, 304, 304, 322, 322, 256,
- 256, 271, 271, 287, 287, 304, 304, 322,
- 322, 341, 341, 362, 362, 256, 256, 271,
- 271, 287, 287, 304, 304, 322, 322, 341,
- 341, 362, 362, 383, 383, 406, 406, 430,
- 430, 455, 455, 482, 482, 511, 511, 541,
- 541, 573, 573, 607, 607, 643, 643, 681,
- 681, 722, 722, 764, 764, 810, 810, 858,
- 858, 908, 908, 962, 962, 1019, 1019, 256
-};
-
-static u32 nphy_tpc_txgain_ipa[] = {
- 0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029,
- 0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025,
- 0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029,
- 0x5ef70028, 0x5ef70027, 0x5ef70026, 0x5ef70025,
- 0x5df7002d, 0x5df7002b, 0x5df7002a, 0x5df70029,
- 0x5df70028, 0x5df70027, 0x5df70026, 0x5df70025,
- 0x5cf7002d, 0x5cf7002b, 0x5cf7002a, 0x5cf70029,
- 0x5cf70028, 0x5cf70027, 0x5cf70026, 0x5cf70025,
- 0x5bf7002d, 0x5bf7002b, 0x5bf7002a, 0x5bf70029,
- 0x5bf70028, 0x5bf70027, 0x5bf70026, 0x5bf70025,
- 0x5af7002d, 0x5af7002b, 0x5af7002a, 0x5af70029,
- 0x5af70028, 0x5af70027, 0x5af70026, 0x5af70025,
- 0x59f7002d, 0x59f7002b, 0x59f7002a, 0x59f70029,
- 0x59f70028, 0x59f70027, 0x59f70026, 0x59f70025,
- 0x58f7002d, 0x58f7002b, 0x58f7002a, 0x58f70029,
- 0x58f70028, 0x58f70027, 0x58f70026, 0x58f70025,
- 0x57f7002d, 0x57f7002b, 0x57f7002a, 0x57f70029,
- 0x57f70028, 0x57f70027, 0x57f70026, 0x57f70025,
- 0x56f7002d, 0x56f7002b, 0x56f7002a, 0x56f70029,
- 0x56f70028, 0x56f70027, 0x56f70026, 0x56f70025,
- 0x55f7002d, 0x55f7002b, 0x55f7002a, 0x55f70029,
- 0x55f70028, 0x55f70027, 0x55f70026, 0x55f70025,
- 0x54f7002d, 0x54f7002b, 0x54f7002a, 0x54f70029,
- 0x54f70028, 0x54f70027, 0x54f70026, 0x54f70025,
- 0x53f7002d, 0x53f7002b, 0x53f7002a, 0x53f70029,
- 0x53f70028, 0x53f70027, 0x53f70026, 0x53f70025,
- 0x52f7002d, 0x52f7002b, 0x52f7002a, 0x52f70029,
- 0x52f70028, 0x52f70027, 0x52f70026, 0x52f70025,
- 0x51f7002d, 0x51f7002b, 0x51f7002a, 0x51f70029,
- 0x51f70028, 0x51f70027, 0x51f70026, 0x51f70025,
- 0x50f7002d, 0x50f7002b, 0x50f7002a, 0x50f70029,
- 0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025
-};
-
-static u32 nphy_tpc_txgain_ipa_rev5[] = {
- 0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029,
- 0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025,
- 0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029,
- 0x1ef70028, 0x1ef70027, 0x1ef70026, 0x1ef70025,
- 0x1df7002d, 0x1df7002b, 0x1df7002a, 0x1df70029,
- 0x1df70028, 0x1df70027, 0x1df70026, 0x1df70025,
- 0x1cf7002d, 0x1cf7002b, 0x1cf7002a, 0x1cf70029,
- 0x1cf70028, 0x1cf70027, 0x1cf70026, 0x1cf70025,
- 0x1bf7002d, 0x1bf7002b, 0x1bf7002a, 0x1bf70029,
- 0x1bf70028, 0x1bf70027, 0x1bf70026, 0x1bf70025,
- 0x1af7002d, 0x1af7002b, 0x1af7002a, 0x1af70029,
- 0x1af70028, 0x1af70027, 0x1af70026, 0x1af70025,
- 0x19f7002d, 0x19f7002b, 0x19f7002a, 0x19f70029,
- 0x19f70028, 0x19f70027, 0x19f70026, 0x19f70025,
- 0x18f7002d, 0x18f7002b, 0x18f7002a, 0x18f70029,
- 0x18f70028, 0x18f70027, 0x18f70026, 0x18f70025,
- 0x17f7002d, 0x17f7002b, 0x17f7002a, 0x17f70029,
- 0x17f70028, 0x17f70027, 0x17f70026, 0x17f70025,
- 0x16f7002d, 0x16f7002b, 0x16f7002a, 0x16f70029,
- 0x16f70028, 0x16f70027, 0x16f70026, 0x16f70025,
- 0x15f7002d, 0x15f7002b, 0x15f7002a, 0x15f70029,
- 0x15f70028, 0x15f70027, 0x15f70026, 0x15f70025,
- 0x14f7002d, 0x14f7002b, 0x14f7002a, 0x14f70029,
- 0x14f70028, 0x14f70027, 0x14f70026, 0x14f70025,
- 0x13f7002d, 0x13f7002b, 0x13f7002a, 0x13f70029,
- 0x13f70028, 0x13f70027, 0x13f70026, 0x13f70025,
- 0x12f7002d, 0x12f7002b, 0x12f7002a, 0x12f70029,
- 0x12f70028, 0x12f70027, 0x12f70026, 0x12f70025,
- 0x11f7002d, 0x11f7002b, 0x11f7002a, 0x11f70029,
- 0x11f70028, 0x11f70027, 0x11f70026, 0x11f70025,
- 0x10f7002d, 0x10f7002b, 0x10f7002a, 0x10f70029,
- 0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025
-};
-
-static u32 nphy_tpc_txgain_ipa_rev6[] = {
- 0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029,
- 0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025,
- 0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029,
- 0x0ef70028, 0x0ef70027, 0x0ef70026, 0x0ef70025,
- 0x0df7002d, 0x0df7002b, 0x0df7002a, 0x0df70029,
- 0x0df70028, 0x0df70027, 0x0df70026, 0x0df70025,
- 0x0cf7002d, 0x0cf7002b, 0x0cf7002a, 0x0cf70029,
- 0x0cf70028, 0x0cf70027, 0x0cf70026, 0x0cf70025,
- 0x0bf7002d, 0x0bf7002b, 0x0bf7002a, 0x0bf70029,
- 0x0bf70028, 0x0bf70027, 0x0bf70026, 0x0bf70025,
- 0x0af7002d, 0x0af7002b, 0x0af7002a, 0x0af70029,
- 0x0af70028, 0x0af70027, 0x0af70026, 0x0af70025,
- 0x09f7002d, 0x09f7002b, 0x09f7002a, 0x09f70029,
- 0x09f70028, 0x09f70027, 0x09f70026, 0x09f70025,
- 0x08f7002d, 0x08f7002b, 0x08f7002a, 0x08f70029,
- 0x08f70028, 0x08f70027, 0x08f70026, 0x08f70025,
- 0x07f7002d, 0x07f7002b, 0x07f7002a, 0x07f70029,
- 0x07f70028, 0x07f70027, 0x07f70026, 0x07f70025,
- 0x06f7002d, 0x06f7002b, 0x06f7002a, 0x06f70029,
- 0x06f70028, 0x06f70027, 0x06f70026, 0x06f70025,
- 0x05f7002d, 0x05f7002b, 0x05f7002a, 0x05f70029,
- 0x05f70028, 0x05f70027, 0x05f70026, 0x05f70025,
- 0x04f7002d, 0x04f7002b, 0x04f7002a, 0x04f70029,
- 0x04f70028, 0x04f70027, 0x04f70026, 0x04f70025,
- 0x03f7002d, 0x03f7002b, 0x03f7002a, 0x03f70029,
- 0x03f70028, 0x03f70027, 0x03f70026, 0x03f70025,
- 0x02f7002d, 0x02f7002b, 0x02f7002a, 0x02f70029,
- 0x02f70028, 0x02f70027, 0x02f70026, 0x02f70025,
- 0x01f7002d, 0x01f7002b, 0x01f7002a, 0x01f70029,
- 0x01f70028, 0x01f70027, 0x01f70026, 0x01f70025,
- 0x00f7002d, 0x00f7002b, 0x00f7002a, 0x00f70029,
- 0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025
-};
-
-static u32 nphy_tpc_txgain_ipa_2g_2057rev3[] = {
- 0x70ff0040, 0x70f7003e, 0x70ef003b, 0x70e70039,
- 0x70df0037, 0x70d70036, 0x70cf0033, 0x70c70032,
- 0x70bf0031, 0x70b7002f, 0x70af002e, 0x70a7002d,
- 0x709f002d, 0x7097002c, 0x708f002c, 0x7087002c,
- 0x707f002b, 0x7077002c, 0x706f002c, 0x7067002d,
- 0x705f002e, 0x705f002b, 0x705f0029, 0x7057002a,
- 0x70570028, 0x704f002a, 0x7047002c, 0x7047002a,
- 0x70470028, 0x70470026, 0x70470024, 0x70470022,
- 0x7047001f, 0x70370027, 0x70370024, 0x70370022,
- 0x70370020, 0x7037001f, 0x7037001d, 0x7037001b,
- 0x7037001a, 0x70370018, 0x70370017, 0x7027001e,
- 0x7027001d, 0x7027001a, 0x701f0024, 0x701f0022,
- 0x701f0020, 0x701f001f, 0x701f001d, 0x701f001b,
- 0x701f001a, 0x701f0018, 0x701f0017, 0x701f0015,
- 0x701f0014, 0x701f0013, 0x701f0012, 0x701f0011,
- 0x70170019, 0x70170018, 0x70170016, 0x70170015,
- 0x70170014, 0x70170013, 0x70170012, 0x70170010,
- 0x70170010, 0x7017000f, 0x700f001d, 0x700f001b,
- 0x700f001a, 0x700f0018, 0x700f0017, 0x700f0015,
- 0x700f0015, 0x700f0013, 0x700f0013, 0x700f0011,
- 0x700f0010, 0x700f0010, 0x700f000f, 0x700f000e,
- 0x700f000d, 0x700f000c, 0x700f000b, 0x700f000b,
- 0x700f000b, 0x700f000a, 0x700f0009, 0x700f0009,
- 0x700f0009, 0x700f0008, 0x700f0007, 0x700f0007,
- 0x700f0006, 0x700f0006, 0x700f0006, 0x700f0006,
- 0x700f0005, 0x700f0005, 0x700f0005, 0x700f0004,
- 0x700f0004, 0x700f0004, 0x700f0004, 0x700f0004,
- 0x700f0004, 0x700f0003, 0x700f0003, 0x700f0003,
- 0x700f0003, 0x700f0002, 0x700f0002, 0x700f0002,
- 0x700f0002, 0x700f0002, 0x700f0002, 0x700f0001,
- 0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001,
- 0x700f0001, 0x700f0001, 0x700f0001, 0x700f0001
-};
-
-static u32 nphy_tpc_txgain_ipa_2g_2057rev4n6[] = {
- 0xf0ff0040, 0xf0f7003e, 0xf0ef003b, 0xf0e70039,
- 0xf0df0037, 0xf0d70036, 0xf0cf0033, 0xf0c70032,
- 0xf0bf0031, 0xf0b7002f, 0xf0af002e, 0xf0a7002d,
- 0xf09f002d, 0xf097002c, 0xf08f002c, 0xf087002c,
- 0xf07f002b, 0xf077002c, 0xf06f002c, 0xf067002d,
- 0xf05f002e, 0xf05f002b, 0xf05f0029, 0xf057002a,
- 0xf0570028, 0xf04f002a, 0xf047002c, 0xf047002a,
- 0xf0470028, 0xf0470026, 0xf0470024, 0xf0470022,
- 0xf047001f, 0xf0370027, 0xf0370024, 0xf0370022,
- 0xf0370020, 0xf037001f, 0xf037001d, 0xf037001b,
- 0xf037001a, 0xf0370018, 0xf0370017, 0xf027001e,
- 0xf027001d, 0xf027001a, 0xf01f0024, 0xf01f0022,
- 0xf01f0020, 0xf01f001f, 0xf01f001d, 0xf01f001b,
- 0xf01f001a, 0xf01f0018, 0xf01f0017, 0xf01f0015,
- 0xf01f0014, 0xf01f0013, 0xf01f0012, 0xf01f0011,
- 0xf0170019, 0xf0170018, 0xf0170016, 0xf0170015,
- 0xf0170014, 0xf0170013, 0xf0170012, 0xf0170010,
- 0xf0170010, 0xf017000f, 0xf00f001d, 0xf00f001b,
- 0xf00f001a, 0xf00f0018, 0xf00f0017, 0xf00f0015,
- 0xf00f0015, 0xf00f0013, 0xf00f0013, 0xf00f0011,
- 0xf00f0010, 0xf00f0010, 0xf00f000f, 0xf00f000e,
- 0xf00f000d, 0xf00f000c, 0xf00f000b, 0xf00f000b,
- 0xf00f000b, 0xf00f000a, 0xf00f0009, 0xf00f0009,
- 0xf00f0009, 0xf00f0008, 0xf00f0007, 0xf00f0007,
- 0xf00f0006, 0xf00f0006, 0xf00f0006, 0xf00f0006,
- 0xf00f0005, 0xf00f0005, 0xf00f0005, 0xf00f0004,
- 0xf00f0004, 0xf00f0004, 0xf00f0004, 0xf00f0004,
- 0xf00f0004, 0xf00f0003, 0xf00f0003, 0xf00f0003,
- 0xf00f0003, 0xf00f0002, 0xf00f0002, 0xf00f0002,
- 0xf00f0002, 0xf00f0002, 0xf00f0002, 0xf00f0001,
- 0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001,
- 0xf00f0001, 0xf00f0001, 0xf00f0001, 0xf00f0001
-};
-
-static u32 nphy_tpc_txgain_ipa_2g_2057rev5[] = {
- 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
- 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
- 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
- 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d,
- 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c,
- 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d,
- 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a,
- 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029,
- 0x30270027, 0x30270025, 0x30270023, 0x301f002c,
- 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024,
- 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b,
- 0x30170028, 0x30170026, 0x30170024, 0x30170022,
- 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b,
- 0x3017001a, 0x30170018, 0x30170017, 0x30170015,
- 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024,
- 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d,
- 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017,
- 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215,
- 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
-};
-
-static u32 nphy_tpc_txgain_ipa_2g_2057rev7[] = {
- 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e,
- 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033,
- 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e,
- 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d,
- 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c,
- 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d,
- 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a,
- 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029,
- 0x30270027, 0x30270025, 0x30270023, 0x301f002c,
- 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024,
- 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b,
- 0x30170028, 0x30170026, 0x30170024, 0x30170022,
- 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b,
- 0x3017001a, 0x30170018, 0x30170017, 0x30170015,
- 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024,
- 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d,
- 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017,
- 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215,
- 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715,
- 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715
-};
-
-static u32 nphy_tpc_txgain_ipa_5g[] = {
- 0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031,
- 0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b,
- 0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027,
- 0x7ff70026, 0x7ff70024, 0x7ff70023, 0x7ff70022,
- 0x7ef70028, 0x7ef70027, 0x7ef70026, 0x7ef70025,
- 0x7ef70024, 0x7ef70023, 0x7df70028, 0x7df70027,
- 0x7df70026, 0x7df70025, 0x7df70024, 0x7df70023,
- 0x7df70022, 0x7cf70029, 0x7cf70028, 0x7cf70027,
- 0x7cf70026, 0x7cf70025, 0x7cf70023, 0x7cf70022,
- 0x7bf70029, 0x7bf70028, 0x7bf70026, 0x7bf70025,
- 0x7bf70024, 0x7bf70023, 0x7bf70022, 0x7bf70021,
- 0x7af70029, 0x7af70028, 0x7af70027, 0x7af70026,
- 0x7af70025, 0x7af70024, 0x7af70023, 0x7af70022,
- 0x79f70029, 0x79f70028, 0x79f70027, 0x79f70026,
- 0x79f70025, 0x79f70024, 0x79f70023, 0x79f70022,
- 0x78f70029, 0x78f70028, 0x78f70027, 0x78f70026,
- 0x78f70025, 0x78f70024, 0x78f70023, 0x78f70022,
- 0x77f70029, 0x77f70028, 0x77f70027, 0x77f70026,
- 0x77f70025, 0x77f70024, 0x77f70023, 0x77f70022,
- 0x76f70029, 0x76f70028, 0x76f70027, 0x76f70026,
- 0x76f70024, 0x76f70023, 0x76f70022, 0x76f70021,
- 0x75f70029, 0x75f70028, 0x75f70027, 0x75f70026,
- 0x75f70025, 0x75f70024, 0x75f70023, 0x74f70029,
- 0x74f70028, 0x74f70026, 0x74f70025, 0x74f70024,
- 0x74f70023, 0x74f70022, 0x73f70029, 0x73f70027,
- 0x73f70026, 0x73f70025, 0x73f70024, 0x73f70023,
- 0x73f70022, 0x72f70028, 0x72f70027, 0x72f70026,
- 0x72f70025, 0x72f70024, 0x72f70023, 0x72f70022,
- 0x71f70028, 0x71f70027, 0x71f70026, 0x71f70025,
- 0x71f70024, 0x71f70023, 0x70f70028, 0x70f70027,
- 0x70f70026, 0x70f70024, 0x70f70023, 0x70f70022,
- 0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f
-};
-
-static u32 nphy_tpc_txgain_ipa_5g_2057[] = {
- 0x7f7f0044, 0x7f7f0040, 0x7f7f003c, 0x7f7f0039,
- 0x7f7f0036, 0x7e7f003c, 0x7e7f0038, 0x7e7f0035,
- 0x7d7f003c, 0x7d7f0039, 0x7d7f0036, 0x7d7f0033,
- 0x7c7f003b, 0x7c7f0037, 0x7c7f0034, 0x7b7f003a,
- 0x7b7f0036, 0x7b7f0033, 0x7a7f003c, 0x7a7f0039,
- 0x7a7f0036, 0x7a7f0033, 0x797f003b, 0x797f0038,
- 0x797f0035, 0x797f0032, 0x787f003b, 0x787f0038,
- 0x787f0035, 0x787f0032, 0x777f003a, 0x777f0037,
- 0x777f0034, 0x777f0031, 0x767f003a, 0x767f0036,
- 0x767f0033, 0x767f0031, 0x757f003a, 0x757f0037,
- 0x757f0034, 0x747f003c, 0x747f0039, 0x747f0036,
- 0x747f0033, 0x737f003b, 0x737f0038, 0x737f0035,
- 0x737f0032, 0x727f0039, 0x727f0036, 0x727f0033,
- 0x727f0030, 0x717f003a, 0x717f0037, 0x717f0034,
- 0x707f003b, 0x707f0038, 0x707f0035, 0x707f0032,
- 0x707f002f, 0x707f002d, 0x707f002a, 0x707f0028,
- 0x707f0025, 0x707f0023, 0x707f0021, 0x707f0020,
- 0x707f001e, 0x707f001c, 0x707f001b, 0x707f0019,
- 0x707f0018, 0x707f0016, 0x707f0015, 0x707f0014,
- 0x707f0013, 0x707f0012, 0x707f0011, 0x707f0010,
- 0x707f000f, 0x707f000e, 0x707f000d, 0x707f000d,
- 0x707f000c, 0x707f000b, 0x707f000b, 0x707f000a,
- 0x707f0009, 0x707f0009, 0x707f0008, 0x707f0008,
- 0x707f0007, 0x707f0007, 0x707f0007, 0x707f0006,
- 0x707f0006, 0x707f0006, 0x707f0005, 0x707f0005,
- 0x707f0005, 0x707f0004, 0x707f0004, 0x707f0004,
- 0x707f0004, 0x707f0004, 0x707f0003, 0x707f0003,
- 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003,
- 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002,
- 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002,
- 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001,
- 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001
-};
-
-static u32 nphy_tpc_txgain_ipa_5g_2057rev7[] = {
- 0x6f7f0031, 0x6f7f002e, 0x6f7f002c, 0x6f7f002a,
- 0x6f7f0027, 0x6e7f002e, 0x6e7f002c, 0x6e7f002a,
- 0x6d7f0030, 0x6d7f002d, 0x6d7f002a, 0x6d7f0028,
- 0x6c7f0030, 0x6c7f002d, 0x6c7f002b, 0x6b7f002e,
- 0x6b7f002c, 0x6b7f002a, 0x6b7f0027, 0x6a7f002e,
- 0x6a7f002c, 0x6a7f002a, 0x697f0030, 0x697f002e,
- 0x697f002b, 0x697f0029, 0x687f002f, 0x687f002d,
- 0x687f002a, 0x687f0027, 0x677f002f, 0x677f002d,
- 0x677f002a, 0x667f0031, 0x667f002e, 0x667f002c,
- 0x667f002a, 0x657f0030, 0x657f002e, 0x657f002b,
- 0x657f0029, 0x647f0030, 0x647f002d, 0x647f002b,
- 0x647f0029, 0x637f002f, 0x637f002d, 0x637f002a,
- 0x627f0030, 0x627f002d, 0x627f002b, 0x627f0029,
- 0x617f0030, 0x617f002e, 0x617f002b, 0x617f0029,
- 0x607f002f, 0x607f002d, 0x607f002a, 0x607f0027,
- 0x607f0026, 0x607f0023, 0x607f0021, 0x607f0020,
- 0x607f001e, 0x607f001c, 0x607f001a, 0x607f0019,
- 0x607f0018, 0x607f0016, 0x607f0015, 0x607f0014,
- 0x607f0012, 0x607f0012, 0x607f0011, 0x607f000f,
- 0x607f000f, 0x607f000e, 0x607f000d, 0x607f000c,
- 0x607f000c, 0x607f000b, 0x607f000b, 0x607f000a,
- 0x607f0009, 0x607f0009, 0x607f0008, 0x607f0008,
- 0x607f0008, 0x607f0007, 0x607f0007, 0x607f0006,
- 0x607f0006, 0x607f0005, 0x607f0005, 0x607f0005,
- 0x607f0005, 0x607f0005, 0x607f0004, 0x607f0004,
- 0x607f0004, 0x607f0004, 0x607f0003, 0x607f0003,
- 0x607f0003, 0x607f0003, 0x607f0002, 0x607f0002,
- 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
- 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
- 0x607f0002, 0x607f0002, 0x607f0002, 0x607f0002,
- 0x607f0002, 0x607f0001, 0x607f0001, 0x607f0001,
- 0x607f0001, 0x607f0001, 0x607f0001, 0x607f0001
-};
-
-static s8 nphy_papd_pga_gain_delta_ipa_2g[] = {
- -114, -108, -98, -91, -84, -78, -70, -62,
- -54, -46, -39, -31, -23, -15, -8, 0
-};
-
-static s8 nphy_papd_pga_gain_delta_ipa_5g[] = {
- -100, -95, -89, -83, -77, -70, -63, -56,
- -48, -41, -33, -25, -19, -12, -6, 0
-};
-
-static s16 nphy_papd_padgain_dlt_2g_2057rev3n4[] = {
- -159, -113, -86, -72, -62, -54, -48, -43,
- -39, -35, -31, -28, -25, -23, -20, -18,
- -17, -15, -13, -11, -10, -8, -7, -6,
- -5, -4, -3, -3, -2, -1, -1, 0
-};
-
-static s16 nphy_papd_padgain_dlt_2g_2057rev5[] = {
- -109, -109, -82, -68, -58, -50, -44, -39,
- -35, -31, -28, -26, -23, -21, -19, -17,
- -16, -14, -13, -11, -10, -9, -8, -7,
- -5, -5, -4, -3, -2, -1, -1, 0
-};
-
-static s16 nphy_papd_padgain_dlt_2g_2057rev7[] = {
- -122, -122, -95, -80, -69, -61, -54, -49,
- -43, -39, -35, -32, -28, -26, -23, -21,
- -18, -16, -15, -13, -11, -10, -8, -7,
- -6, -5, -4, -3, -2, -1, -1, 0
-};
-
-static s8 nphy_papd_pgagain_dlt_5g_2057[] = {
- -107, -101, -92, -85, -78, -71, -62, -55,
- -47, -39, -32, -24, -19, -12, -6, 0
-};
-
-static s8 nphy_papd_pgagain_dlt_5g_2057rev7[] = {
- -110, -104, -95, -88, -81, -74, -66, -58,
- -50, -44, -36, -28, -23, -15, -8, 0
-};
-
-static u8 pad_gain_codes_used_2057rev5[] = {
- 20, 19, 18, 17, 16, 15, 14, 13, 12, 11,
- 10, 9, 8, 7, 6, 5, 4, 3, 2, 1
-};
-
-static u8 pad_gain_codes_used_2057rev7[] = {
- 15, 14, 13, 12, 11, 10, 9, 8, 7, 6,
- 5, 4, 3, 2, 1
-};
-
-static u8 pad_all_gain_codes_2057[] = {
- 31, 30, 29, 28, 27, 26, 25, 24, 23, 22,
- 21, 20, 19, 18, 17, 16, 15, 14, 13, 12,
- 11, 10, 9, 8, 7, 6, 5, 4, 3, 2,
- 1, 0
-};
-
-static u8 pga_all_gain_codes_2057[] = {
- 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
-};
-
-static u32 nphy_papd_scaltbl[] = {
- 0x0ae2002f, 0x0a3b0032, 0x09a70035, 0x09220038,
- 0x0887003c, 0x081f003f, 0x07a20043, 0x07340047,
- 0x06d2004b, 0x067a004f, 0x06170054, 0x05bf0059,
- 0x0571005e, 0x051e0064, 0x04d3006a, 0x04910070,
- 0x044c0077, 0x040f007e, 0x03d90085, 0x03a1008d,
- 0x036f0095, 0x033d009e, 0x030b00a8, 0x02e000b2,
- 0x02b900bc, 0x029200c7, 0x026d00d3, 0x024900e0,
- 0x022900ed, 0x020a00fb, 0x01ec010a, 0x01d0011a,
- 0x01b7012a, 0x019e013c, 0x0187014f, 0x01720162,
- 0x015d0177, 0x0149018e, 0x013701a5, 0x012601be,
- 0x011501d9, 0x010501f5, 0x00f70212, 0x00e90232,
- 0x00dc0253, 0x00d00276, 0x00c4029c, 0x00b902c3,
- 0x00af02ed, 0x00a5031a, 0x009c0349, 0x0093037a,
- 0x008b03af, 0x008303e7, 0x007c0422, 0x00750461,
- 0x006e04a3, 0x006804ea, 0x00620534, 0x005d0583,
- 0x005805d7, 0x0053062f, 0x004e068d, 0x004a06f1
-};
-
-static u32 nphy_tpc_txgain_rev3[] = {
- 0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e,
- 0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037,
- 0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e,
- 0x1e41003c, 0x1e41003b, 0x1e410039, 0x1e410037,
- 0x1d410044, 0x1d410042, 0x1d410040, 0x1d41003e,
- 0x1d41003c, 0x1d41003b, 0x1d410039, 0x1d410037,
- 0x1c410044, 0x1c410042, 0x1c410040, 0x1c41003e,
- 0x1c41003c, 0x1c41003b, 0x1c410039, 0x1c410037,
- 0x1b410044, 0x1b410042, 0x1b410040, 0x1b41003e,
- 0x1b41003c, 0x1b41003b, 0x1b410039, 0x1b410037,
- 0x1a410044, 0x1a410042, 0x1a410040, 0x1a41003e,
- 0x1a41003c, 0x1a41003b, 0x1a410039, 0x1a410037,
- 0x19410044, 0x19410042, 0x19410040, 0x1941003e,
- 0x1941003c, 0x1941003b, 0x19410039, 0x19410037,
- 0x18410044, 0x18410042, 0x18410040, 0x1841003e,
- 0x1841003c, 0x1841003b, 0x18410039, 0x18410037,
- 0x17410044, 0x17410042, 0x17410040, 0x1741003e,
- 0x1741003c, 0x1741003b, 0x17410039, 0x17410037,
- 0x16410044, 0x16410042, 0x16410040, 0x1641003e,
- 0x1641003c, 0x1641003b, 0x16410039, 0x16410037,
- 0x15410044, 0x15410042, 0x15410040, 0x1541003e,
- 0x1541003c, 0x1541003b, 0x15410039, 0x15410037,
- 0x14410044, 0x14410042, 0x14410040, 0x1441003e,
- 0x1441003c, 0x1441003b, 0x14410039, 0x14410037,
- 0x13410044, 0x13410042, 0x13410040, 0x1341003e,
- 0x1341003c, 0x1341003b, 0x13410039, 0x13410037,
- 0x12410044, 0x12410042, 0x12410040, 0x1241003e,
- 0x1241003c, 0x1241003b, 0x12410039, 0x12410037,
- 0x11410044, 0x11410042, 0x11410040, 0x1141003e,
- 0x1141003c, 0x1141003b, 0x11410039, 0x11410037,
- 0x10410044, 0x10410042, 0x10410040, 0x1041003e,
- 0x1041003c, 0x1041003b, 0x10410039, 0x10410037
-};
-
-static u32 nphy_tpc_txgain_HiPwrEPA[] = {
- 0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e,
- 0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037,
- 0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e,
- 0x0e41003c, 0x0e41003b, 0x0e410039, 0x0e410037,
- 0x0d410044, 0x0d410042, 0x0d410040, 0x0d41003e,
- 0x0d41003c, 0x0d41003b, 0x0d410039, 0x0d410037,
- 0x0c410044, 0x0c410042, 0x0c410040, 0x0c41003e,
- 0x0c41003c, 0x0c41003b, 0x0c410039, 0x0c410037,
- 0x0b410044, 0x0b410042, 0x0b410040, 0x0b41003e,
- 0x0b41003c, 0x0b41003b, 0x0b410039, 0x0b410037,
- 0x0a410044, 0x0a410042, 0x0a410040, 0x0a41003e,
- 0x0a41003c, 0x0a41003b, 0x0a410039, 0x0a410037,
- 0x09410044, 0x09410042, 0x09410040, 0x0941003e,
- 0x0941003c, 0x0941003b, 0x09410039, 0x09410037,
- 0x08410044, 0x08410042, 0x08410040, 0x0841003e,
- 0x0841003c, 0x0841003b, 0x08410039, 0x08410037,
- 0x07410044, 0x07410042, 0x07410040, 0x0741003e,
- 0x0741003c, 0x0741003b, 0x07410039, 0x07410037,
- 0x06410044, 0x06410042, 0x06410040, 0x0641003e,
- 0x0641003c, 0x0641003b, 0x06410039, 0x06410037,
- 0x05410044, 0x05410042, 0x05410040, 0x0541003e,
- 0x0541003c, 0x0541003b, 0x05410039, 0x05410037,
- 0x04410044, 0x04410042, 0x04410040, 0x0441003e,
- 0x0441003c, 0x0441003b, 0x04410039, 0x04410037,
- 0x03410044, 0x03410042, 0x03410040, 0x0341003e,
- 0x0341003c, 0x0341003b, 0x03410039, 0x03410037,
- 0x02410044, 0x02410042, 0x02410040, 0x0241003e,
- 0x0241003c, 0x0241003b, 0x02410039, 0x02410037,
- 0x01410044, 0x01410042, 0x01410040, 0x0141003e,
- 0x0141003c, 0x0141003b, 0x01410039, 0x01410037,
- 0x00410044, 0x00410042, 0x00410040, 0x0041003e,
- 0x0041003c, 0x0041003b, 0x00410039, 0x00410037
-};
-
-static u32 nphy_tpc_txgain_epa_2057rev3[] = {
- 0x80f90040, 0x80e10040, 0x80e1003c, 0x80c9003d,
- 0x80b9003c, 0x80a9003d, 0x80a1003c, 0x8099003b,
- 0x8091003b, 0x8089003a, 0x8081003a, 0x80790039,
- 0x80710039, 0x8069003a, 0x8061003b, 0x8059003d,
- 0x8051003f, 0x80490042, 0x8049003e, 0x8049003b,
- 0x8041003e, 0x8041003b, 0x8039003e, 0x8039003b,
- 0x80390038, 0x80390035, 0x8031003a, 0x80310036,
- 0x80310033, 0x8029003a, 0x80290037, 0x80290034,
- 0x80290031, 0x80210039, 0x80210036, 0x80210033,
- 0x80210030, 0x8019003c, 0x80190039, 0x80190036,
- 0x80190033, 0x80190030, 0x8019002d, 0x8019002b,
- 0x80190028, 0x8011003a, 0x80110036, 0x80110033,
- 0x80110030, 0x8011002e, 0x8011002b, 0x80110029,
- 0x80110027, 0x80110024, 0x80110022, 0x80110020,
- 0x8011001f, 0x8011001d, 0x8009003a, 0x80090037,
- 0x80090034, 0x80090031, 0x8009002e, 0x8009002c,
- 0x80090029, 0x80090027, 0x80090025, 0x80090023,
- 0x80090021, 0x8009001f, 0x8009001d, 0x8009011d,
- 0x8009021d, 0x8009031d, 0x8009041d, 0x8009051d,
- 0x8009061d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d,
- 0x8009071d, 0x8009071d, 0x8009071d, 0x8009071d
-};
-
-static u32 nphy_tpc_txgain_epa_2057rev5[] = {
- 0x10f90040, 0x10e10040, 0x10e1003c, 0x10c9003d,
- 0x10b9003c, 0x10a9003d, 0x10a1003c, 0x1099003b,
- 0x1091003b, 0x1089003a, 0x1081003a, 0x10790039,
- 0x10710039, 0x1069003a, 0x1061003b, 0x1059003d,
- 0x1051003f, 0x10490042, 0x1049003e, 0x1049003b,
- 0x1041003e, 0x1041003b, 0x1039003e, 0x1039003b,
- 0x10390038, 0x10390035, 0x1031003a, 0x10310036,
- 0x10310033, 0x1029003a, 0x10290037, 0x10290034,
- 0x10290031, 0x10210039, 0x10210036, 0x10210033,
- 0x10210030, 0x1019003c, 0x10190039, 0x10190036,
- 0x10190033, 0x10190030, 0x1019002d, 0x1019002b,
- 0x10190028, 0x1011003a, 0x10110036, 0x10110033,
- 0x10110030, 0x1011002e, 0x1011002b, 0x10110029,
- 0x10110027, 0x10110024, 0x10110022, 0x10110020,
- 0x1011001f, 0x1011001d, 0x1009003a, 0x10090037,
- 0x10090034, 0x10090031, 0x1009002e, 0x1009002c,
- 0x10090029, 0x10090027, 0x10090025, 0x10090023,
- 0x10090021, 0x1009001f, 0x1009001d, 0x1009001b,
- 0x1009001a, 0x10090018, 0x10090017, 0x10090016,
- 0x10090015, 0x10090013, 0x10090012, 0x10090011,
- 0x10090010, 0x1009000f, 0x1009000f, 0x1009000e,
- 0x1009000d, 0x1009000c, 0x1009000c, 0x1009000b,
- 0x1009000a, 0x1009000a, 0x10090009, 0x10090009,
- 0x10090008, 0x10090008, 0x10090007, 0x10090007,
- 0x10090007, 0x10090006, 0x10090006, 0x10090005,
- 0x10090005, 0x10090005, 0x10090005, 0x10090004,
- 0x10090004, 0x10090004, 0x10090004, 0x10090003,
- 0x10090003, 0x10090003, 0x10090003, 0x10090003,
- 0x10090003, 0x10090002, 0x10090002, 0x10090002,
- 0x10090002, 0x10090002, 0x10090002, 0x10090002,
- 0x10090002, 0x10090002, 0x10090001, 0x10090001,
- 0x10090001, 0x10090001, 0x10090001, 0x10090001
-};
-
-static u32 nphy_tpc_5GHz_txgain_rev3[] = {
- 0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e,
- 0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037,
- 0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e,
- 0xcef7003c, 0xcef7003b, 0xcef70039, 0xcef70037,
- 0xcdf70044, 0xcdf70042, 0xcdf70040, 0xcdf7003e,
- 0xcdf7003c, 0xcdf7003b, 0xcdf70039, 0xcdf70037,
- 0xccf70044, 0xccf70042, 0xccf70040, 0xccf7003e,
- 0xccf7003c, 0xccf7003b, 0xccf70039, 0xccf70037,
- 0xcbf70044, 0xcbf70042, 0xcbf70040, 0xcbf7003e,
- 0xcbf7003c, 0xcbf7003b, 0xcbf70039, 0xcbf70037,
- 0xcaf70044, 0xcaf70042, 0xcaf70040, 0xcaf7003e,
- 0xcaf7003c, 0xcaf7003b, 0xcaf70039, 0xcaf70037,
- 0xc9f70044, 0xc9f70042, 0xc9f70040, 0xc9f7003e,
- 0xc9f7003c, 0xc9f7003b, 0xc9f70039, 0xc9f70037,
- 0xc8f70044, 0xc8f70042, 0xc8f70040, 0xc8f7003e,
- 0xc8f7003c, 0xc8f7003b, 0xc8f70039, 0xc8f70037,
- 0xc7f70044, 0xc7f70042, 0xc7f70040, 0xc7f7003e,
- 0xc7f7003c, 0xc7f7003b, 0xc7f70039, 0xc7f70037,
- 0xc6f70044, 0xc6f70042, 0xc6f70040, 0xc6f7003e,
- 0xc6f7003c, 0xc6f7003b, 0xc6f70039, 0xc6f70037,
- 0xc5f70044, 0xc5f70042, 0xc5f70040, 0xc5f7003e,
- 0xc5f7003c, 0xc5f7003b, 0xc5f70039, 0xc5f70037,
- 0xc4f70044, 0xc4f70042, 0xc4f70040, 0xc4f7003e,
- 0xc4f7003c, 0xc4f7003b, 0xc4f70039, 0xc4f70037,
- 0xc3f70044, 0xc3f70042, 0xc3f70040, 0xc3f7003e,
- 0xc3f7003c, 0xc3f7003b, 0xc3f70039, 0xc3f70037,
- 0xc2f70044, 0xc2f70042, 0xc2f70040, 0xc2f7003e,
- 0xc2f7003c, 0xc2f7003b, 0xc2f70039, 0xc2f70037,
- 0xc1f70044, 0xc1f70042, 0xc1f70040, 0xc1f7003e,
- 0xc1f7003c, 0xc1f7003b, 0xc1f70039, 0xc1f70037,
- 0xc0f70044, 0xc0f70042, 0xc0f70040, 0xc0f7003e,
- 0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037
-};
-
-static u32 nphy_tpc_5GHz_txgain_rev4[] = {
- 0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e,
- 0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037,
- 0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e,
- 0x2ef2003c, 0x2ef2003b, 0x2ef20039, 0x2ef20037,
- 0x2df20044, 0x2df20042, 0x2df20040, 0x2df2003e,
- 0x2df2003c, 0x2df2003b, 0x2df20039, 0x2df20037,
- 0x2cf20044, 0x2cf20042, 0x2cf20040, 0x2cf2003e,
- 0x2cf2003c, 0x2cf2003b, 0x2cf20039, 0x2cf20037,
- 0x2bf20044, 0x2bf20042, 0x2bf20040, 0x2bf2003e,
- 0x2bf2003c, 0x2bf2003b, 0x2bf20039, 0x2bf20037,
- 0x2af20044, 0x2af20042, 0x2af20040, 0x2af2003e,
- 0x2af2003c, 0x2af2003b, 0x2af20039, 0x2af20037,
- 0x29f20044, 0x29f20042, 0x29f20040, 0x29f2003e,
- 0x29f2003c, 0x29f2003b, 0x29f20039, 0x29f20037,
- 0x28f20044, 0x28f20042, 0x28f20040, 0x28f2003e,
- 0x28f2003c, 0x28f2003b, 0x28f20039, 0x28f20037,
- 0x27f20044, 0x27f20042, 0x27f20040, 0x27f2003e,
- 0x27f2003c, 0x27f2003b, 0x27f20039, 0x27f20037,
- 0x26f20044, 0x26f20042, 0x26f20040, 0x26f2003e,
- 0x26f2003c, 0x26f2003b, 0x26f20039, 0x26f20037,
- 0x25f20044, 0x25f20042, 0x25f20040, 0x25f2003e,
- 0x25f2003c, 0x25f2003b, 0x25f20039, 0x25f20037,
- 0x24f20044, 0x24f20042, 0x24f20040, 0x24f2003e,
- 0x24f2003c, 0x24f2003b, 0x24f20039, 0x24f20038,
- 0x23f20041, 0x23f20040, 0x23f2003f, 0x23f2003e,
- 0x23f2003c, 0x23f2003b, 0x23f20039, 0x23f20037,
- 0x22f20044, 0x22f20042, 0x22f20040, 0x22f2003e,
- 0x22f2003c, 0x22f2003b, 0x22f20039, 0x22f20037,
- 0x21f20044, 0x21f20042, 0x21f20040, 0x21f2003e,
- 0x21f2003c, 0x21f2003b, 0x21f20039, 0x21f20037,
- 0x20d20043, 0x20d20041, 0x20d2003e, 0x20d2003c,
- 0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034
-};
-
-static u32 nphy_tpc_5GHz_txgain_rev5[] = {
- 0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044,
- 0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c,
- 0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e,
- 0x0e62003c, 0x0e62003d, 0x0e62003b, 0x0e62003a,
- 0x0d620043, 0x0d620041, 0x0d620040, 0x0d62003e,
- 0x0d62003d, 0x0d62003c, 0x0d62003b, 0x0d62003a,
- 0x0c620041, 0x0c620040, 0x0c62003f, 0x0c62003e,
- 0x0c62003c, 0x0c62003b, 0x0c620039, 0x0c620037,
- 0x0b620046, 0x0b620044, 0x0b620042, 0x0b620040,
- 0x0b62003e, 0x0b62003c, 0x0b62003b, 0x0b62003a,
- 0x0a620041, 0x0a620040, 0x0a62003e, 0x0a62003c,
- 0x0a62003b, 0x0a62003a, 0x0a620039, 0x0a620038,
- 0x0962003e, 0x0962003d, 0x0962003c, 0x0962003b,
- 0x09620039, 0x09620037, 0x09620035, 0x09620033,
- 0x08620044, 0x08620042, 0x08620040, 0x0862003e,
- 0x0862003c, 0x0862003b, 0x0862003a, 0x08620039,
- 0x07620043, 0x07620042, 0x07620040, 0x0762003f,
- 0x0762003d, 0x0762003b, 0x0762003a, 0x07620039,
- 0x0662003e, 0x0662003d, 0x0662003c, 0x0662003b,
- 0x06620039, 0x06620037, 0x06620035, 0x06620033,
- 0x05620046, 0x05620044, 0x05620042, 0x05620040,
- 0x0562003e, 0x0562003c, 0x0562003b, 0x05620039,
- 0x04620044, 0x04620042, 0x04620040, 0x0462003e,
- 0x0462003c, 0x0462003b, 0x04620039, 0x04620038,
- 0x0362003c, 0x0362003b, 0x0362003a, 0x03620039,
- 0x03620038, 0x03620037, 0x03620035, 0x03620033,
- 0x0262004c, 0x0262004a, 0x02620048, 0x02620047,
- 0x02620046, 0x02620044, 0x02620043, 0x02620042,
- 0x0162004a, 0x01620048, 0x01620046, 0x01620044,
- 0x01620043, 0x01620042, 0x01620041, 0x01620040,
- 0x00620042, 0x00620040, 0x0062003e, 0x0062003c,
- 0x0062003b, 0x00620039, 0x00620037, 0x00620035
-};
-
-static u32 nphy_tpc_5GHz_txgain_HiPwrEPA[] = {
- 0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e,
- 0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037,
- 0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e,
- 0x2ef1003c, 0x2ef1003b, 0x2ef10039, 0x2ef10037,
- 0x2df10044, 0x2df10042, 0x2df10040, 0x2df1003e,
- 0x2df1003c, 0x2df1003b, 0x2df10039, 0x2df10037,
- 0x2cf10044, 0x2cf10042, 0x2cf10040, 0x2cf1003e,
- 0x2cf1003c, 0x2cf1003b, 0x2cf10039, 0x2cf10037,
- 0x2bf10044, 0x2bf10042, 0x2bf10040, 0x2bf1003e,
- 0x2bf1003c, 0x2bf1003b, 0x2bf10039, 0x2bf10037,
- 0x2af10044, 0x2af10042, 0x2af10040, 0x2af1003e,
- 0x2af1003c, 0x2af1003b, 0x2af10039, 0x2af10037,
- 0x29f10044, 0x29f10042, 0x29f10040, 0x29f1003e,
- 0x29f1003c, 0x29f1003b, 0x29f10039, 0x29f10037,
- 0x28f10044, 0x28f10042, 0x28f10040, 0x28f1003e,
- 0x28f1003c, 0x28f1003b, 0x28f10039, 0x28f10037,
- 0x27f10044, 0x27f10042, 0x27f10040, 0x27f1003e,
- 0x27f1003c, 0x27f1003b, 0x27f10039, 0x27f10037,
- 0x26f10044, 0x26f10042, 0x26f10040, 0x26f1003e,
- 0x26f1003c, 0x26f1003b, 0x26f10039, 0x26f10037,
- 0x25f10044, 0x25f10042, 0x25f10040, 0x25f1003e,
- 0x25f1003c, 0x25f1003b, 0x25f10039, 0x25f10037,
- 0x24f10044, 0x24f10042, 0x24f10040, 0x24f1003e,
- 0x24f1003c, 0x24f1003b, 0x24f10039, 0x24f10038,
- 0x23f10041, 0x23f10040, 0x23f1003f, 0x23f1003e,
- 0x23f1003c, 0x23f1003b, 0x23f10039, 0x23f10037,
- 0x22f10044, 0x22f10042, 0x22f10040, 0x22f1003e,
- 0x22f1003c, 0x22f1003b, 0x22f10039, 0x22f10037,
- 0x21f10044, 0x21f10042, 0x21f10040, 0x21f1003e,
- 0x21f1003c, 0x21f1003b, 0x21f10039, 0x21f10037,
- 0x20d10043, 0x20d10041, 0x20d1003e, 0x20d1003c,
- 0x20d1003a, 0x20d10038, 0x20d10036, 0x20d10034
-};
-
-static u8 ant_sw_ctrl_tbl_rev8_2o3[] = { 0x14, 0x18 };
-static u8 ant_sw_ctrl_tbl_rev8[] = { 0x4, 0x8, 0x4, 0x8, 0x11, 0x12 };
-static u8 ant_sw_ctrl_tbl_rev8_2057v7_core0[] = {
- 0x09, 0x0a, 0x15, 0x16, 0x09, 0x0a };
-static u8 ant_sw_ctrl_tbl_rev8_2057v7_core1[] = {
- 0x09, 0x0a, 0x09, 0x0a, 0x15, 0x16 };
-
-static bool wlc_phy_chan2freq_nphy(phy_info_t *pi, uint channel, int *f,
- chan_info_nphy_radio2057_t **t0,
- chan_info_nphy_radio205x_t **t1,
- chan_info_nphy_radio2057_rev5_t **t2,
- chan_info_nphy_2055_t **t3);
-static void wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chans,
- const nphy_sfo_cfg_t *c);
-
-static void wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi,
- u16 reduction_factr);
-static void wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *,
- u32 *buf);
-static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr);
-static void wlc_phy_txlpfbw_nphy(phy_info_t *pi);
-static void wlc_phy_spurwar_nphy(phy_info_t *pi);
-
-static void wlc_phy_radio_preinit_2055(phy_info_t *pi);
-static void wlc_phy_radio_init_2055(phy_info_t *pi);
-static void wlc_phy_radio_postinit_2055(phy_info_t *pi);
-static void wlc_phy_radio_preinit_205x(phy_info_t *pi);
-static void wlc_phy_radio_init_2056(phy_info_t *pi);
-static void wlc_phy_radio_postinit_2056(phy_info_t *pi);
-static void wlc_phy_radio_init_2057(phy_info_t *pi);
-static void wlc_phy_radio_postinit_2057(phy_info_t *pi);
-static void wlc_phy_workarounds_nphy(phy_info_t *pi);
-static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi);
-static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(phy_info_t *pi);
-static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi);
-static void wlc_phy_adjust_lnagaintbl_nphy(phy_info_t *pi);
-
-static void wlc_phy_restore_rssical_nphy(phy_info_t *pi);
-static void wlc_phy_reapply_txcal_coeffs_nphy(phy_info_t *pi);
-static void wlc_phy_tx_iq_war_nphy(phy_info_t *pi);
-static int wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t tg,
- u8 type, bool d);
-static void wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rxcore,
- u16 *rg, u8 type);
-static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, s32 preamble);
-static void wlc_phy_savecal_nphy(phy_info_t *pi);
-static void wlc_phy_restorecal_nphy(phy_info_t *pi);
-static void wlc_phy_resetcca_nphy(phy_info_t *pi);
-
-static void wlc_phy_txpwrctrl_config_nphy(phy_info_t *pi);
-static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi);
-static void wlc_phy_precal_txgain_nphy(phy_info_t *pi);
-static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core);
-
-static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi);
-static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi);
-static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi);
-static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi);
-static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1);
-static u32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi);
-
-static void wlc_phy_a1_nphy(phy_info_t *pi, u8 core, u32 winsz, u32,
- u32 e);
-static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core);
-static void wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *,
- phy_cal_mode_t, u8);
-static void wlc_phy_papd_cal_cleanup_nphy(phy_info_t *pi,
- nphy_papd_restore_state *state);
-static void wlc_phy_papd_cal_setup_nphy(phy_info_t *pi,
- nphy_papd_restore_state *state, u8);
-
-static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, u16 *vals);
-
-static void wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *evts,
- u8 *dlys, u8 len);
-
-static u16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, u16 offset);
-
-static void
-wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, u16 field, u16 value,
- u8 core_mask, u8 off,
- u8 override_id);
-
-static void wlc_phy_rssi_cal_nphy_rev2(phy_info_t *pi, u8 rssi_type);
-static void wlc_phy_rssi_cal_nphy_rev3(phy_info_t *pi);
-
-static bool wlc_phy_txpwr_srom_read_nphy(phy_info_t *pi);
-static void wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max,
- u16 *pwr_offset,
- u8 tmp_max_pwr, u8 rate_start,
- u8 rate_end);
-
-static void wlc_phy_txpwr_limit_to_tbl_nphy(phy_info_t *pi);
-static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi);
-static void wlc_phy_txpwrctrl_idle_tssi_nphy(phy_info_t *pi);
-static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi);
-
-static bool wlc_phy_txpwr_ison_nphy(phy_info_t *pi);
-static u8 wlc_phy_txpwr_idx_cur_get_nphy(phy_info_t *pi, u8 core);
-static void wlc_phy_txpwr_idx_cur_set_nphy(phy_info_t *pi, u8 idx0,
- u8 idx1);
-static void wlc_phy_a4(phy_info_t *pi, bool full_cal);
-
-static u16 wlc_phy_radio205x_rcal(phy_info_t *pi);
-
-static u16 wlc_phy_radio2057_rccal(phy_info_t *pi);
-
-static u16 wlc_phy_gen_load_samples_nphy(phy_info_t *pi, u32 f_kHz,
- u16 max_val,
- u8 dac_test_mode);
-static void wlc_phy_loadsampletable_nphy(phy_info_t *pi, cs32 *tone_buf,
- u16 num_samps);
-static void wlc_phy_runsamples_nphy(phy_info_t *pi, u16 n, u16 lps,
- u16 wait, u8 iq, u8 dac_test_mode,
- bool modify_bbmult);
-
-bool wlc_phy_bist_check_phy(wlc_phy_t *pih)
-{
- phy_info_t *pi = (phy_info_t *) pih;
- u32 phybist0, phybist1, phybist2, phybist3, phybist4;
-
- if (NREV_GE(pi->pubpi.phy_rev, 16))
- return true;
-
- phybist0 = read_phy_reg(pi, 0x0e);
- phybist1 = read_phy_reg(pi, 0x0f);
- phybist2 = read_phy_reg(pi, 0xea);
- phybist3 = read_phy_reg(pi, 0xeb);
- phybist4 = read_phy_reg(pi, 0x156);
-
- if ((phybist0 == 0) && (phybist1 == 0x4000) && (phybist2 == 0x1fe0) &&
- (phybist3 == 0) && (phybist4 == 0)) {
- return true;
- }
-
- return false;
-}
-
-static void WLBANDINITFN(wlc_phy_bphy_init_nphy) (phy_info_t *pi)
-{
- u16 addr, val;
-
- val = 0x1e1f;
- for (addr = (NPHY_TO_BPHY_OFF + BPHY_RSSI_LUT);
- addr <= (NPHY_TO_BPHY_OFF + BPHY_RSSI_LUT_END); addr++) {
- write_phy_reg(pi, addr, val);
- if (addr == (NPHY_TO_BPHY_OFF + 0x97))
- val = 0x3e3f;
- else
- val -= 0x0202;
- }
-
- if (NORADIO_ENAB(pi->pubpi)) {
-
- write_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_PHYCRSTH, 0x3206);
-
- write_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_RSSI_TRESH, 0x281e);
-
- or_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_LNA_GAIN_RANGE, 0x1a);
-
- } else {
-
- write_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_STEP, 0x668);
- }
-}
-
-void
-wlc_phy_table_write_nphy(phy_info_t *pi, u32 id, u32 len, u32 offset,
- u32 width, const void *data)
-{
- mimophytbl_info_t tbl;
-
- tbl.tbl_id = id;
- tbl.tbl_len = len;
- tbl.tbl_offset = offset;
- tbl.tbl_width = width;
- tbl.tbl_ptr = data;
- wlc_phy_write_table_nphy(pi, &tbl);
-}
-
-void
-wlc_phy_table_read_nphy(phy_info_t *pi, u32 id, u32 len, u32 offset,
- u32 width, void *data)
-{
- mimophytbl_info_t tbl;
-
- tbl.tbl_id = id;
- tbl.tbl_len = len;
- tbl.tbl_offset = offset;
- tbl.tbl_width = width;
- tbl.tbl_ptr = data;
- wlc_phy_read_table_nphy(pi, &tbl);
-}
-
-static void WLBANDINITFN(wlc_phy_static_table_download_nphy) (phy_info_t *pi)
-{
- uint idx;
-
- if (NREV_GE(pi->pubpi.phy_rev, 16)) {
- for (idx = 0; idx < mimophytbl_info_sz_rev16; idx++)
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev16[idx]);
- } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- for (idx = 0; idx < mimophytbl_info_sz_rev7; idx++)
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev7[idx]);
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- for (idx = 0; idx < mimophytbl_info_sz_rev3; idx++)
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev3[idx]);
- } else {
- for (idx = 0; idx < mimophytbl_info_sz_rev0; idx++)
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev0[idx]);
- }
-}
-
-static void WLBANDINITFN(wlc_phy_tbl_init_nphy) (phy_info_t *pi)
-{
- uint idx = 0;
- u8 antswctrllut;
-
- if (pi->phy_init_por)
- wlc_phy_static_table_download_nphy(pi);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- antswctrllut = CHSPEC_IS2G(pi->radio_chanspec) ?
- pi->srom_fem2g.antswctrllut : pi->srom_fem5g.antswctrllut;
-
- switch (antswctrllut) {
- case 0:
-
- break;
-
- case 1:
-
- if (pi->aa2g == 7) {
-
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x21, 8,
- &ant_sw_ctrl_tbl_rev8_2o3
- [0]);
- } else {
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x21, 8,
- &ant_sw_ctrl_tbl_rev8
- [0]);
- }
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x25, 8,
- &ant_sw_ctrl_tbl_rev8[2]);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x29, 8,
- &ant_sw_ctrl_tbl_rev8[4]);
- break;
-
- case 2:
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x1, 8,
- &ant_sw_ctrl_tbl_rev8_2057v7_core0
- [0]);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x5, 8,
- &ant_sw_ctrl_tbl_rev8_2057v7_core0
- [2]);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x9, 8,
- &ant_sw_ctrl_tbl_rev8_2057v7_core0
- [4]);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x21, 8,
- &ant_sw_ctrl_tbl_rev8_2057v7_core1
- [0]);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x25, 8,
- &ant_sw_ctrl_tbl_rev8_2057v7_core1
- [2]);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 2, 0x29, 8,
- &ant_sw_ctrl_tbl_rev8_2057v7_core1
- [4]);
- break;
-
- default:
- break;
- }
-
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- for (idx = 0; idx < mimophytbl_info_sz_rev3_volatile; idx++) {
-
- if (idx == ANT_SWCTRL_TBL_REV3_IDX) {
- antswctrllut = CHSPEC_IS2G(pi->radio_chanspec) ?
- pi->srom_fem2g.antswctrllut : pi->
- srom_fem5g.antswctrllut;
- switch (antswctrllut) {
- case 0:
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev3_volatile
- [idx]);
- break;
- case 1:
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev3_volatile1
- [idx]);
- break;
- case 2:
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev3_volatile2
- [idx]);
- break;
- case 3:
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev3_volatile3
- [idx]);
- break;
- default:
- break;
- }
- } else {
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev3_volatile
- [idx]);
- }
- }
- } else {
- for (idx = 0; idx < mimophytbl_info_sz_rev0_volatile; idx++) {
- wlc_phy_write_table_nphy(pi,
- &mimophytbl_info_rev0_volatile
- [idx]);
- }
- }
-}
-
-static void
-wlc_phy_write_txmacreg_nphy(phy_info_t *pi, u16 holdoff, u16 delay)
-{
- write_phy_reg(pi, 0x77, holdoff);
- write_phy_reg(pi, 0xb4, delay);
-}
-
-void wlc_phy_nphy_tkip_rifs_war(phy_info_t *pi, u8 rifs)
-{
- u16 holdoff, delay;
-
- if (rifs) {
-
- holdoff = 0x10;
- delay = 0x258;
- } else {
-
- holdoff = 0x15;
- delay = 0x320;
- }
-
- wlc_phy_write_txmacreg_nphy(pi, holdoff, delay);
-
- if (pi && pi->sh && (pi->sh->_rifs_phy != rifs)) {
- pi->sh->_rifs_phy = rifs;
- }
-}
-
-bool wlc_phy_attach_nphy(phy_info_t *pi)
-{
- uint i;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 6)) {
- pi->phyhang_avoid = true;
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
-
- pi->nphy_gband_spurwar_en = true;
-
- if (pi->sh->boardflags2 & BFL2_SPUR_WAR) {
- pi->nphy_aband_spurwar_en = true;
- }
- }
- if (NREV_GE(pi->pubpi.phy_rev, 6) && NREV_LT(pi->pubpi.phy_rev, 7)) {
-
- if (pi->sh->boardflags2 & BFL2_2G_SPUR_WAR) {
- pi->nphy_gband_spurwar2_en = true;
- }
- }
-
- pi->n_preamble_override = AUTO;
- if (NREV_IS(pi->pubpi.phy_rev, 3) || NREV_IS(pi->pubpi.phy_rev, 4))
- pi->n_preamble_override = WLC_N_PREAMBLE_MIXEDMODE;
-
- pi->nphy_txrx_chain = AUTO;
- pi->phy_scraminit = AUTO;
-
- pi->nphy_rxcalparams = 0x010100B5;
-
- pi->nphy_perical = PHY_PERICAL_MPHASE;
- pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
- pi->mphase_txcal_numcmds = MPHASE_TXCAL_NUMCMDS;
-
- pi->nphy_gain_boost = true;
- pi->nphy_elna_gain_config = false;
- pi->radio_is_on = false;
-
- for (i = 0; i < pi->pubpi.phy_corenum; i++) {
- pi->nphy_txpwrindex[i].index = AUTO;
- }
-
- wlc_phy_txpwrctrl_config_nphy(pi);
- if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
- pi->hwpwrctrl_capable = true;
-
- pi->pi_fptr.init = wlc_phy_init_nphy;
- pi->pi_fptr.calinit = wlc_phy_cal_init_nphy;
- pi->pi_fptr.chanset = wlc_phy_chanspec_set_nphy;
- pi->pi_fptr.txpwrrecalc = wlc_phy_txpower_recalc_target_nphy;
-
- if (!wlc_phy_txpwr_srom_read_nphy(pi))
- return false;
-
- return true;
-}
-
-static void wlc_phy_txpwrctrl_config_nphy(phy_info_t *pi)
-{
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- pi->nphy_txpwrctrl = PHY_TPC_HW_ON;
- pi->phy_5g_pwrgain = true;
- return;
- }
-
- pi->nphy_txpwrctrl = PHY_TPC_HW_OFF;
- pi->phy_5g_pwrgain = false;
-
- if ((pi->sh->boardflags2 & BFL2_TXPWRCTRL_EN) &&
- NREV_GE(pi->pubpi.phy_rev, 2) && (pi->sh->sromrev >= 4))
- pi->nphy_txpwrctrl = PHY_TPC_HW_ON;
- else if ((pi->sh->sromrev >= 4)
- && (pi->sh->boardflags2 & BFL2_5G_PWRGAIN))
- pi->phy_5g_pwrgain = true;
-}
-
-void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
-{
- u16 val;
- u16 clip1_ths[2];
- nphy_txgains_t target_gain;
- u8 tx_pwr_ctrl_state;
- bool do_nphy_cal = false;
- uint core;
- uint origidx, intr_val;
- d11regs_t *regs;
- u32 d11_clk_ctl_st;
-
- core = 0;
-
- if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN)) {
- pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
- }
-
- if ((ISNPHY(pi)) && (NREV_GE(pi->pubpi.phy_rev, 5)) &&
- ((pi->sh->chippkg == BCM4717_PKG_ID) ||
- (pi->sh->chippkg == BCM4718_PKG_ID))) {
- if ((pi->sh->boardflags & BFL_EXTLNA) &&
- (CHSPEC_IS2G(pi->radio_chanspec))) {
- ai_corereg(pi->sh->sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol), 0x40,
- 0x40);
- }
- }
-
- if ((!PHY_IPA(pi)) && (pi->sh->chip == BCM5357_CHIP_ID)) {
- si_pmu_chipcontrol(pi->sh->sih, 1, CCTRL5357_EXTPA,
- CCTRL5357_EXTPA);
- }
-
- if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
- CHSPEC_IS40(pi->radio_chanspec)) {
-
- regs = (d11regs_t *) ai_switch_core(pi->sh->sih, D11_CORE_ID,
- &origidx, &intr_val);
- d11_clk_ctl_st = R_REG(®s->clk_ctl_st);
- AND_REG(®s->clk_ctl_st,
- ~(CCS_FORCEHT | CCS_HTAREQ));
-
- W_REG(®s->clk_ctl_st, d11_clk_ctl_st);
-
- ai_restore_core(pi->sh->sih, origidx, intr_val);
- }
-
- pi->use_int_tx_iqlo_cal_nphy =
- (PHY_IPA(pi) ||
- (NREV_GE(pi->pubpi.phy_rev, 7) ||
- (NREV_GE(pi->pubpi.phy_rev, 5)
- && pi->sh->boardflags2 & BFL2_INTERNDET_TXIQCAL)));
-
- pi->internal_tx_iqlo_cal_tapoff_intpa_nphy = false;
-
- pi->nphy_deaf_count = 0;
-
- wlc_phy_tbl_init_nphy(pi);
-
- pi->nphy_crsminpwr_adjusted = false;
- pi->nphy_noisevars_adjusted = false;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- write_phy_reg(pi, 0xe7, 0);
- write_phy_reg(pi, 0xec, 0);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- write_phy_reg(pi, 0x342, 0);
- write_phy_reg(pi, 0x343, 0);
- write_phy_reg(pi, 0x346, 0);
- write_phy_reg(pi, 0x347, 0);
- }
- write_phy_reg(pi, 0xe5, 0);
- write_phy_reg(pi, 0xe6, 0);
- } else {
- write_phy_reg(pi, 0xec, 0);
- }
-
- write_phy_reg(pi, 0x91, 0);
- write_phy_reg(pi, 0x92, 0);
- if (NREV_LT(pi->pubpi.phy_rev, 6)) {
- write_phy_reg(pi, 0x93, 0);
- write_phy_reg(pi, 0x94, 0);
- }
-
- and_phy_reg(pi, 0xa1, ~3);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- write_phy_reg(pi, 0x8f, 0);
- write_phy_reg(pi, 0xa5, 0);
- } else {
- write_phy_reg(pi, 0xa5, 0);
- }
-
- if (NREV_IS(pi->pubpi.phy_rev, 2))
- mod_phy_reg(pi, 0xdc, 0x00ff, 0x3b);
- else if (NREV_LT(pi->pubpi.phy_rev, 2))
- mod_phy_reg(pi, 0xdc, 0x00ff, 0x40);
-
- write_phy_reg(pi, 0x203, 32);
- write_phy_reg(pi, 0x201, 32);
-
- if (pi->sh->boardflags2 & BFL2_SKWRKFEM_BRD)
- write_phy_reg(pi, 0x20d, 160);
- else
- write_phy_reg(pi, 0x20d, 184);
-
- write_phy_reg(pi, 0x13a, 200);
-
- write_phy_reg(pi, 0x70, 80);
-
- write_phy_reg(pi, 0x1ff, 48);
-
- if (NREV_LT(pi->pubpi.phy_rev, 8)) {
- wlc_phy_update_mimoconfig_nphy(pi, pi->n_preamble_override);
- }
-
- wlc_phy_stf_chain_upd_nphy(pi);
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
- write_phy_reg(pi, 0x180, 0xaa8);
- write_phy_reg(pi, 0x181, 0x9a4);
- }
-
- if (PHY_IPA(pi)) {
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (1) << 0);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x298 :
- 0x29c, (0x1ff << 7),
- (pi->nphy_papd_epsilon_offset[core]) << 7);
-
- }
-
- wlc_phy_ipa_set_tx_digi_filts_nphy(pi);
- } else {
-
- if (NREV_GE(pi->pubpi.phy_rev, 5)) {
- wlc_phy_extpa_set_tx_digi_filts_nphy(pi);
- }
- }
-
- wlc_phy_workarounds_nphy(pi);
-
- wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
-
- val = read_phy_reg(pi, 0x01);
- write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
- write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
- wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
-
- wlapi_bmac_macphyclk_set(pi->sh->physhim, ON);
-
- wlc_phy_pa_override_nphy(pi, OFF);
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX);
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
- wlc_phy_pa_override_nphy(pi, ON);
-
- wlc_phy_classifier_nphy(pi, 0, 0);
- wlc_phy_clip_det_nphy(pi, 0, clip1_ths);
-
- if (CHSPEC_IS2G(pi->radio_chanspec))
- wlc_phy_bphy_init_nphy(pi);
-
- tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
- wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
-
- wlc_phy_txpwr_fixpower_nphy(pi);
-
- wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
-
- wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- u32 *tx_pwrctrl_tbl = NULL;
- u16 idx;
- s16 pga_gn = 0;
- s16 pad_gn = 0;
- s32 rfpwr_offset = 0;
-
- if (PHY_IPA(pi)) {
- tx_pwrctrl_tbl = wlc_phy_get_ipa_gaintbl_nphy(pi);
- } else {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if NREV_IS
- (pi->pubpi.phy_rev, 3) {
- tx_pwrctrl_tbl =
- nphy_tpc_5GHz_txgain_rev3;
- } else if NREV_IS
- (pi->pubpi.phy_rev, 4) {
- tx_pwrctrl_tbl =
- (pi->srom_fem5g.extpagain == 3) ?
- nphy_tpc_5GHz_txgain_HiPwrEPA :
- nphy_tpc_5GHz_txgain_rev4;
- } else {
- tx_pwrctrl_tbl =
- nphy_tpc_5GHz_txgain_rev5;
- }
-
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (pi->pubpi.radiorev == 5) {
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_epa_2057rev5;
- } else if (pi->pubpi.radiorev == 3) {
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_epa_2057rev3;
- }
-
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 5) &&
- (pi->srom_fem2g.extpagain == 3)) {
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_HiPwrEPA;
- } else {
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_rev3;
- }
- }
- }
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 128,
- 192, 32, tx_pwrctrl_tbl);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128,
- 192, 32, tx_pwrctrl_tbl);
-
- pi->nphy_gmval = (u16) ((*tx_pwrctrl_tbl >> 16) & 0x7000);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- for (idx = 0; idx < 128; idx++) {
- pga_gn = (tx_pwrctrl_tbl[idx] >> 24) & 0xf;
- pad_gn = (tx_pwrctrl_tbl[idx] >> 19) & 0x1f;
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if ((pi->pubpi.radiorev == 3) ||
- (pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
- rfpwr_offset = (s16)
- nphy_papd_padgain_dlt_2g_2057rev3n4
- [pad_gn];
- } else if (pi->pubpi.radiorev == 5) {
- rfpwr_offset = (s16)
- nphy_papd_padgain_dlt_2g_2057rev5
- [pad_gn];
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev ==
- 8)) {
- rfpwr_offset = (s16)
- nphy_papd_padgain_dlt_2g_2057rev7
- [pad_gn];
- }
- } else {
- if ((pi->pubpi.radiorev == 3) ||
- (pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
- rfpwr_offset = (s16)
- nphy_papd_pgagain_dlt_5g_2057
- [pga_gn];
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev ==
- 8)) {
- rfpwr_offset = (s16)
- nphy_papd_pgagain_dlt_5g_2057rev7
- [pga_gn];
- }
- }
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_CORE1TXPWRCTL,
- 1, 576 + idx, 32,
- &rfpwr_offset);
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_CORE2TXPWRCTL,
- 1, 576 + idx, 32,
- &rfpwr_offset);
- }
- } else {
-
- for (idx = 0; idx < 128; idx++) {
- pga_gn = (tx_pwrctrl_tbl[idx] >> 24) & 0xf;
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- rfpwr_offset = (s16)
- nphy_papd_pga_gain_delta_ipa_2g
- [pga_gn];
- } else {
- rfpwr_offset = (s16)
- nphy_papd_pga_gain_delta_ipa_5g
- [pga_gn];
- }
-
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_CORE1TXPWRCTL,
- 1, 576 + idx, 32,
- &rfpwr_offset);
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_CORE2TXPWRCTL,
- 1, 576 + idx, 32,
- &rfpwr_offset);
- }
-
- }
- } else {
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 128,
- 192, 32, nphy_tpc_txgain);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 128,
- 192, 32, nphy_tpc_txgain);
- }
-
- if (pi->sh->phyrxchain != 0x3) {
- wlc_phy_rxcore_setstate_nphy((wlc_phy_t *) pi,
- pi->sh->phyrxchain);
- }
-
- if (PHY_PERICAL_MPHASE_PENDING(pi)) {
- wlc_phy_cal_perical_mphase_restart(pi);
- }
-
- if (!NORADIO_ENAB(pi->pubpi)) {
- bool do_rssi_cal = false;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- do_rssi_cal = (CHSPEC_IS2G(pi->radio_chanspec)) ?
- (pi->nphy_rssical_chanspec_2G == 0) :
- (pi->nphy_rssical_chanspec_5G == 0);
-
- if (do_rssi_cal) {
- wlc_phy_rssi_cal_nphy(pi);
- } else {
- wlc_phy_restore_rssical_nphy(pi);
- }
- } else {
- wlc_phy_rssi_cal_nphy(pi);
- }
-
- if (!SCAN_RM_IN_PROGRESS(pi)) {
- do_nphy_cal = (CHSPEC_IS2G(pi->radio_chanspec)) ?
- (pi->nphy_iqcal_chanspec_2G == 0) :
- (pi->nphy_iqcal_chanspec_5G == 0);
- }
-
- if (!pi->do_initcal)
- do_nphy_cal = false;
-
- if (do_nphy_cal) {
-
- target_gain = wlc_phy_get_tx_gain_nphy(pi);
-
- if (pi->antsel_type == ANTSEL_2x3)
- wlc_phy_antsel_init((wlc_phy_t *) pi, true);
-
- if (pi->nphy_perical != PHY_PERICAL_MPHASE) {
- wlc_phy_rssi_cal_nphy(pi);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- pi->nphy_cal_orig_pwr_idx[0] =
- pi->nphy_txpwrindex[PHY_CORE_0].
- index_internal;
- pi->nphy_cal_orig_pwr_idx[1] =
- pi->nphy_txpwrindex[PHY_CORE_1].
- index_internal;
-
- wlc_phy_precal_txgain_nphy(pi);
- target_gain =
- wlc_phy_get_tx_gain_nphy(pi);
- }
-
- if (wlc_phy_cal_txiqlo_nphy
- (pi, target_gain, true, false) == 0) {
- if (wlc_phy_cal_rxiq_nphy
- (pi, target_gain, 2,
- false) == 0) {
- wlc_phy_savecal_nphy(pi);
-
- }
- }
- } else if (pi->mphase_cal_phase_id ==
- MPHASE_CAL_STATE_IDLE) {
-
- wlc_phy_cal_perical((wlc_phy_t *) pi,
- PHY_PERICAL_PHYINIT);
- }
- } else {
- wlc_phy_restorecal_nphy(pi);
- }
- }
-
- wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
-
- wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
-
- wlc_phy_nphy_tkip_rifs_war(pi, pi->sh->_rifs_phy);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LE(pi->pubpi.phy_rev, 6))
-
- write_phy_reg(pi, 0x70, 50);
-
- wlc_phy_txlpfbw_nphy(pi);
-
- wlc_phy_spurwar_nphy(pi);
-
-}
-
-static void wlc_phy_update_mimoconfig_nphy(phy_info_t *pi, s32 preamble)
-{
- bool gf_preamble = false;
- u16 val;
-
- if (preamble == WLC_N_PREAMBLE_GF) {
- gf_preamble = true;
- }
-
- val = read_phy_reg(pi, 0xed);
-
- val |= RX_GF_MM_AUTO;
- val &= ~RX_GF_OR_MM;
- if (gf_preamble)
- val |= RX_GF_OR_MM;
-
- write_phy_reg(pi, 0xed, val);
-}
-
-static void wlc_phy_resetcca_nphy(phy_info_t *pi)
-{
- u16 val;
-
- wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
-
- val = read_phy_reg(pi, 0x01);
- write_phy_reg(pi, 0x01, val | BBCFG_RESETCCA);
- udelay(1);
- write_phy_reg(pi, 0x01, val & (~BBCFG_RESETCCA));
-
- wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
-
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
-}
-
-void wlc_phy_pa_override_nphy(phy_info_t *pi, bool en)
-{
- u16 rfctrlintc_override_val;
-
- if (!en) {
-
- pi->rfctrlIntc1_save = read_phy_reg(pi, 0x91);
- pi->rfctrlIntc2_save = read_phy_reg(pi, 0x92);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- rfctrlintc_override_val = 0x1480;
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- rfctrlintc_override_val =
- CHSPEC_IS5G(pi->radio_chanspec) ? 0x600 : 0x480;
- } else {
- rfctrlintc_override_val =
- CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120;
- }
-
- write_phy_reg(pi, 0x91, rfctrlintc_override_val);
- write_phy_reg(pi, 0x92, rfctrlintc_override_val);
- } else {
-
- write_phy_reg(pi, 0x91, pi->rfctrlIntc1_save);
- write_phy_reg(pi, 0x92, pi->rfctrlIntc2_save);
- }
-
-}
-
-void wlc_phy_stf_chain_upd_nphy(phy_info_t *pi)
-{
-
- u16 txrx_chain =
- (NPHY_RfseqCoreActv_TxRxChain0 | NPHY_RfseqCoreActv_TxRxChain1);
- bool CoreActv_override = false;
-
- if (pi->nphy_txrx_chain == WLC_N_TXRX_CHAIN0) {
- txrx_chain = NPHY_RfseqCoreActv_TxRxChain0;
- CoreActv_override = true;
-
- if (NREV_LE(pi->pubpi.phy_rev, 2)) {
- and_phy_reg(pi, 0xa0, ~0x20);
- }
- } else if (pi->nphy_txrx_chain == WLC_N_TXRX_CHAIN1) {
- txrx_chain = NPHY_RfseqCoreActv_TxRxChain1;
- CoreActv_override = true;
-
- if (NREV_LE(pi->pubpi.phy_rev, 2)) {
- or_phy_reg(pi, 0xa0, 0x20);
- }
- }
-
- mod_phy_reg(pi, 0xa2, ((0xf << 0) | (0xf << 4)), txrx_chain);
-
- if (CoreActv_override) {
-
- pi->nphy_perical = PHY_PERICAL_DISABLE;
- or_phy_reg(pi, 0xa1, NPHY_RfseqMode_CoreActv_override);
- } else {
- pi->nphy_perical = PHY_PERICAL_MPHASE;
- and_phy_reg(pi, 0xa1, ~NPHY_RfseqMode_CoreActv_override);
- }
-}
-
-void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask)
-{
- u16 regval;
- u16 tbl_buf[16];
- uint i;
- phy_info_t *pi = (phy_info_t *) pih;
- u16 tbl_opcode;
- bool suspend;
-
- pi->sh->phyrxchain = rxcore_bitmask;
-
- if (!pi->sh->clk)
- return;
-
- suspend =
- (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!suspend)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- regval = read_phy_reg(pi, 0xa2);
- regval &= ~(0xf << 4);
- regval |= ((u16) (rxcore_bitmask & 0x3)) << 4;
- write_phy_reg(pi, 0xa2, regval);
-
- if ((rxcore_bitmask & 0x3) != 0x3) {
-
- write_phy_reg(pi, 0x20e, 1);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (pi->rx2tx_biasentry == -1) {
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ,
- ARRAY_SIZE(tbl_buf), 80,
- 16, tbl_buf);
-
- for (i = 0; i < ARRAY_SIZE(tbl_buf); i++) {
- if (tbl_buf[i] ==
- NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS) {
-
- pi->rx2tx_biasentry = (u8) i;
- tbl_opcode =
- NPHY_REV3_RFSEQ_CMD_NOP;
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_RFSEQ,
- 1, i,
- 16,
- &tbl_opcode);
- break;
- } else if (tbl_buf[i] ==
- NPHY_REV3_RFSEQ_CMD_END) {
- break;
- }
- }
- }
- }
- } else {
-
- write_phy_reg(pi, 0x20e, 30);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (pi->rx2tx_biasentry != -1) {
- tbl_opcode = NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1, pi->rx2tx_biasentry,
- 16, &tbl_opcode);
- pi->rx2tx_biasentry = -1;
- }
- }
- }
-
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-
- if (!suspend)
- wlapi_enable_mac(pi->sh->physhim);
-}
-
-u8 wlc_phy_rxcore_getstate_nphy(wlc_phy_t *pih)
-{
- u16 regval, rxen_bits;
- phy_info_t *pi = (phy_info_t *) pih;
-
- regval = read_phy_reg(pi, 0xa2);
- rxen_bits = (regval >> 4) & 0xf;
-
- return (u8) rxen_bits;
-}
-
-bool wlc_phy_n_txpower_ipa_ison(phy_info_t *pi)
-{
- return PHY_IPA(pi);
-}
-
-static void wlc_phy_txpwr_limit_to_tbl_nphy(phy_info_t *pi)
-{
- u8 idx, idx2, i, delta_ind;
-
- for (idx = TXP_FIRST_CCK; idx <= TXP_LAST_CCK; idx++) {
- pi->adj_pwr_tbl_nphy[idx] = pi->tx_power_offset[idx];
- }
-
- for (i = 0; i < 4; i++) {
- idx2 = 0;
-
- delta_ind = 0;
-
- switch (i) {
- case 0:
-
- if (CHSPEC_IS40(pi->radio_chanspec)
- && NPHY_IS_SROM_REINTERPRET) {
- idx = TXP_FIRST_MCS_40_SISO;
- } else {
- idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
- TXP_FIRST_OFDM_40_SISO : TXP_FIRST_OFDM;
- delta_ind = 1;
- }
- break;
-
- case 1:
-
- idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
- TXP_FIRST_MCS_40_CDD : TXP_FIRST_MCS_20_CDD;
- break;
-
- case 2:
-
- idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
- TXP_FIRST_MCS_40_STBC : TXP_FIRST_MCS_20_STBC;
- break;
-
- case 3:
-
- idx = (CHSPEC_IS40(pi->radio_chanspec)) ?
- TXP_FIRST_MCS_40_SDM : TXP_FIRST_MCS_20_SDM;
- break;
- }
-
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- idx = idx + delta_ind;
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx++];
-
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx++];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx++];
-
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx++];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx++];
-
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx++];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- idx = idx + 1 - delta_ind;
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
-
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- pi->adj_pwr_tbl_nphy[4 + 4 * (idx2++) + i] =
- pi->tx_power_offset[idx];
- }
-}
-
-void wlc_phy_cal_init_nphy(phy_info_t *pi)
-{
-}
-
-static void wlc_phy_war_force_trsw_to_R_cliplo_nphy(phy_info_t *pi, u8 core)
-{
- if (core == PHY_CORE_0) {
- write_phy_reg(pi, 0x38, 0x4);
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- write_phy_reg(pi, 0x37, 0x0060);
- } else {
- write_phy_reg(pi, 0x37, 0x1080);
- }
- } else if (core == PHY_CORE_1) {
- write_phy_reg(pi, 0x2ae, 0x4);
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- write_phy_reg(pi, 0x2ad, 0x0060);
- } else {
- write_phy_reg(pi, 0x2ad, 0x1080);
- }
- }
-}
-
-static void wlc_phy_war_txchain_upd_nphy(phy_info_t *pi, u8 txchain)
-{
- u8 txchain0, txchain1;
-
- txchain0 = txchain & 0x1;
- txchain1 = (txchain & 0x2) >> 1;
- if (!txchain0) {
- wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_0);
- }
-
- if (!txchain1) {
- wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_1);
- }
-}
-
-static void wlc_phy_workarounds_nphy(phy_info_t *pi)
-{
- u8 rfseq_rx2tx_events[] = {
- NPHY_RFSEQ_CMD_NOP,
- NPHY_RFSEQ_CMD_RXG_FBW,
- NPHY_RFSEQ_CMD_TR_SWITCH,
- NPHY_RFSEQ_CMD_CLR_HIQ_DIS,
- NPHY_RFSEQ_CMD_RXPD_TXPD,
- NPHY_RFSEQ_CMD_TX_GAIN,
- NPHY_RFSEQ_CMD_EXT_PA
- };
- u8 rfseq_rx2tx_dlys[] = { 8, 6, 6, 2, 4, 60, 1 };
- u8 rfseq_tx2rx_events[] = {
- NPHY_RFSEQ_CMD_NOP,
- NPHY_RFSEQ_CMD_EXT_PA,
- NPHY_RFSEQ_CMD_TX_GAIN,
- NPHY_RFSEQ_CMD_RXPD_TXPD,
- NPHY_RFSEQ_CMD_TR_SWITCH,
- NPHY_RFSEQ_CMD_RXG_FBW,
- NPHY_RFSEQ_CMD_CLR_HIQ_DIS
- };
- u8 rfseq_tx2rx_dlys[] = { 8, 6, 2, 4, 4, 6, 1 };
- u8 rfseq_tx2rx_events_rev3[] = {
- NPHY_REV3_RFSEQ_CMD_EXT_PA,
- NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
- NPHY_REV3_RFSEQ_CMD_TX_GAIN,
- NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
- NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
- NPHY_REV3_RFSEQ_CMD_RXG_FBW,
- NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
- NPHY_REV3_RFSEQ_CMD_END
- };
- u8 rfseq_tx2rx_dlys_rev3[] = { 8, 4, 2, 2, 4, 4, 6, 1 };
- u8 rfseq_rx2tx_events_rev3[] = {
- NPHY_REV3_RFSEQ_CMD_NOP,
- NPHY_REV3_RFSEQ_CMD_RXG_FBW,
- NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
- NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
- NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
- NPHY_REV3_RFSEQ_CMD_TX_GAIN,
- NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
- NPHY_REV3_RFSEQ_CMD_EXT_PA,
- NPHY_REV3_RFSEQ_CMD_END
- };
- u8 rfseq_rx2tx_dlys_rev3[] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
-
- u8 rfseq_rx2tx_events_rev3_ipa[] = {
- NPHY_REV3_RFSEQ_CMD_NOP,
- NPHY_REV3_RFSEQ_CMD_RXG_FBW,
- NPHY_REV3_RFSEQ_CMD_TR_SWITCH,
- NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS,
- NPHY_REV3_RFSEQ_CMD_RXPD_TXPD,
- NPHY_REV3_RFSEQ_CMD_TX_GAIN,
- NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS,
- NPHY_REV3_RFSEQ_CMD_INT_PA_PU,
- NPHY_REV3_RFSEQ_CMD_END
- };
- u8 rfseq_rx2tx_dlys_rev3_ipa[] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
- u16 rfseq_rx2tx_dacbufpu_rev7[] = { 0x10f, 0x10f };
-
- s16 alpha0, alpha1, alpha2;
- s16 beta0, beta1, beta2;
- u32 leg_data_weights, ht_data_weights, nss1_data_weights,
- stbc_data_weights;
- u8 chan_freq_range = 0;
- u16 dac_control = 0x0002;
- u16 aux_adc_vmid_rev7_core0[] = { 0x8e, 0x96, 0x96, 0x96 };
- u16 aux_adc_vmid_rev7_core1[] = { 0x8f, 0x9f, 0x9f, 0x96 };
- u16 aux_adc_vmid_rev4[] = { 0xa2, 0xb4, 0xb4, 0x89 };
- u16 aux_adc_vmid_rev3[] = { 0xa2, 0xb4, 0xb4, 0x89 };
- u16 *aux_adc_vmid;
- u16 aux_adc_gain_rev7[] = { 0x02, 0x02, 0x02, 0x02 };
- u16 aux_adc_gain_rev4[] = { 0x02, 0x02, 0x02, 0x00 };
- u16 aux_adc_gain_rev3[] = { 0x02, 0x02, 0x02, 0x00 };
- u16 *aux_adc_gain;
- u16 sk_adc_vmid[] = { 0xb4, 0xb4, 0xb4, 0x24 };
- u16 sk_adc_gain[] = { 0x02, 0x02, 0x02, 0x02 };
- s32 min_nvar_val = 0x18d;
- s32 min_nvar_offset_6mbps = 20;
- u8 pdetrange;
- u8 triso;
- u16 regval;
- u16 afectrl_adc_ctrl1_rev7 = 0x20;
- u16 afectrl_adc_ctrl2_rev7 = 0x0;
- u16 rfseq_rx2tx_lpf_h_hpc_rev7 = 0x77;
- u16 rfseq_tx2rx_lpf_h_hpc_rev7 = 0x77;
- u16 rfseq_pktgn_lpf_h_hpc_rev7 = 0x77;
- u16 rfseq_htpktgn_lpf_hpc_rev7[] = { 0x77, 0x11, 0x11 };
- u16 rfseq_pktgn_lpf_hpc_rev7[] = { 0x11, 0x11 };
- u16 rfseq_cckpktgn_lpf_hpc_rev7[] = { 0x11, 0x11 };
- u16 ipalvlshift_3p3_war_en = 0;
- u16 rccal_bcap_val, rccal_scap_val;
- u16 rccal_tx20_11b_bcap = 0;
- u16 rccal_tx20_11b_scap = 0;
- u16 rccal_tx20_11n_bcap = 0;
- u16 rccal_tx20_11n_scap = 0;
- u16 rccal_tx40_11n_bcap = 0;
- u16 rccal_tx40_11n_scap = 0;
- u16 rx2tx_lpf_rc_lut_tx20_11b = 0;
- u16 rx2tx_lpf_rc_lut_tx20_11n = 0;
- u16 rx2tx_lpf_rc_lut_tx40_11n = 0;
- u16 tx_lpf_bw_ofdm_20mhz = 0;
- u16 tx_lpf_bw_ofdm_40mhz = 0;
- u16 tx_lpf_bw_11b = 0;
- u16 ipa2g_mainbias, ipa2g_casconv, ipa2g_biasfilt;
- u16 txgm_idac_bleed = 0;
- bool rccal_ovrd = false;
- u16 freq;
- int coreNum;
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_cck_en, 0);
- } else {
- wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_cck_en, 1);
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- if (!ISSIM_ENAB(pi->sh->sih)) {
- or_phy_reg(pi, 0xb1, NPHY_IQFlip_ADC1 | NPHY_IQFlip_ADC2);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)) {
- mod_phy_reg(pi, 0x221, (0x1 << 4), (1 << 4));
-
- mod_phy_reg(pi, 0x160, (0x7f << 0), (32 << 0));
- mod_phy_reg(pi, 0x160, (0x7f << 8), (39 << 8));
- mod_phy_reg(pi, 0x161, (0x7f << 0), (46 << 0));
- mod_phy_reg(pi, 0x161, (0x7f << 8), (51 << 8));
- mod_phy_reg(pi, 0x162, (0x7f << 0), (55 << 0));
- mod_phy_reg(pi, 0x162, (0x7f << 8), (58 << 8));
- mod_phy_reg(pi, 0x163, (0x7f << 0), (60 << 0));
- mod_phy_reg(pi, 0x163, (0x7f << 8), (62 << 8));
- mod_phy_reg(pi, 0x164, (0x7f << 0), (62 << 0));
- mod_phy_reg(pi, 0x164, (0x7f << 8), (63 << 8));
- mod_phy_reg(pi, 0x165, (0x7f << 0), (63 << 0));
- mod_phy_reg(pi, 0x165, (0x7f << 8), (64 << 8));
- mod_phy_reg(pi, 0x166, (0x7f << 0), (64 << 0));
- mod_phy_reg(pi, 0x166, (0x7f << 8), (64 << 8));
- mod_phy_reg(pi, 0x167, (0x7f << 0), (64 << 0));
- mod_phy_reg(pi, 0x167, (0x7f << 8), (64 << 8));
- }
-
- if (NREV_LE(pi->pubpi.phy_rev, 8)) {
- write_phy_reg(pi, 0x23f, 0x1b0);
- write_phy_reg(pi, 0x240, 0x1b0);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 8)) {
- mod_phy_reg(pi, 0xbd, (0xff << 0), (114 << 0));
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x00, 16,
- &dac_control);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x10, 16,
- &dac_control);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
- 1, 0, 32, &leg_data_weights);
- leg_data_weights = leg_data_weights & 0xffffff;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
- 1, 0, 32, &leg_data_weights);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 2, 0x15e, 16,
- rfseq_rx2tx_dacbufpu_rev7);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x16e, 16,
- rfseq_rx2tx_dacbufpu_rev7);
-
- if (PHY_IPA(pi)) {
- wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
- rfseq_rx2tx_events_rev3_ipa,
- rfseq_rx2tx_dlys_rev3_ipa,
- sizeof
- (rfseq_rx2tx_events_rev3_ipa) /
- sizeof
- (rfseq_rx2tx_events_rev3_ipa
- [0]));
- }
-
- mod_phy_reg(pi, 0x299, (0x3 << 14), (0x1 << 14));
- mod_phy_reg(pi, 0x29d, (0x3 << 14), (0x1 << 14));
-
- tx_lpf_bw_ofdm_20mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x154);
- tx_lpf_bw_ofdm_40mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x159);
- tx_lpf_bw_11b = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0x152);
-
- if (PHY_IPA(pi)) {
-
- if (((pi->pubpi.radiorev == 5)
- && (CHSPEC_IS40(pi->radio_chanspec) == 1))
- || (pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- rccal_bcap_val =
- read_radio_reg(pi,
- RADIO_2057_RCCAL_BCAP_VAL);
- rccal_scap_val =
- read_radio_reg(pi,
- RADIO_2057_RCCAL_SCAP_VAL);
-
- rccal_tx20_11b_bcap = rccal_bcap_val;
- rccal_tx20_11b_scap = rccal_scap_val;
-
- if ((pi->pubpi.radiorev == 5) &&
- (CHSPEC_IS40(pi->radio_chanspec) == 1)) {
-
- rccal_tx20_11n_bcap = rccal_bcap_val;
- rccal_tx20_11n_scap = rccal_scap_val;
- rccal_tx40_11n_bcap = 0xc;
- rccal_tx40_11n_scap = 0xc;
-
- rccal_ovrd = true;
-
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- tx_lpf_bw_ofdm_20mhz = 4;
- tx_lpf_bw_11b = 1;
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- rccal_tx20_11n_bcap = 0xc;
- rccal_tx20_11n_scap = 0xc;
- rccal_tx40_11n_bcap = 0xa;
- rccal_tx40_11n_scap = 0xa;
- } else {
- rccal_tx20_11n_bcap = 0x14;
- rccal_tx20_11n_scap = 0x14;
- rccal_tx40_11n_bcap = 0xf;
- rccal_tx40_11n_scap = 0xf;
- }
-
- rccal_ovrd = true;
- }
- }
-
- } else {
-
- if (pi->pubpi.radiorev == 5) {
-
- tx_lpf_bw_ofdm_20mhz = 1;
- tx_lpf_bw_ofdm_40mhz = 3;
-
- rccal_bcap_val =
- read_radio_reg(pi,
- RADIO_2057_RCCAL_BCAP_VAL);
- rccal_scap_val =
- read_radio_reg(pi,
- RADIO_2057_RCCAL_SCAP_VAL);
-
- rccal_tx20_11b_bcap = rccal_bcap_val;
- rccal_tx20_11b_scap = rccal_scap_val;
-
- rccal_tx20_11n_bcap = 0x13;
- rccal_tx20_11n_scap = 0x11;
- rccal_tx40_11n_bcap = 0x13;
- rccal_tx40_11n_scap = 0x11;
-
- rccal_ovrd = true;
- }
- }
-
- if (rccal_ovrd) {
-
- rx2tx_lpf_rc_lut_tx20_11b = (rccal_tx20_11b_bcap << 8) |
- (rccal_tx20_11b_scap << 3) | tx_lpf_bw_11b;
- rx2tx_lpf_rc_lut_tx20_11n = (rccal_tx20_11n_bcap << 8) |
- (rccal_tx20_11n_scap << 3) | tx_lpf_bw_ofdm_20mhz;
- rx2tx_lpf_rc_lut_tx40_11n = (rccal_tx40_11n_bcap << 8) |
- (rccal_tx40_11n_scap << 3) | tx_lpf_bw_ofdm_40mhz;
-
- for (coreNum = 0; coreNum <= 1; coreNum++) {
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1,
- 0x152 + coreNum * 0x10,
- 16,
- &rx2tx_lpf_rc_lut_tx20_11b);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1,
- 0x153 + coreNum * 0x10,
- 16,
- &rx2tx_lpf_rc_lut_tx20_11n);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1,
- 0x154 + coreNum * 0x10,
- 16,
- &rx2tx_lpf_rc_lut_tx20_11n);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1,
- 0x155 + coreNum * 0x10,
- 16,
- &rx2tx_lpf_rc_lut_tx40_11n);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1,
- 0x156 + coreNum * 0x10,
- 16,
- &rx2tx_lpf_rc_lut_tx40_11n);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1,
- 0x157 + coreNum * 0x10,
- 16,
- &rx2tx_lpf_rc_lut_tx40_11n);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1,
- 0x158 + coreNum * 0x10,
- 16,
- &rx2tx_lpf_rc_lut_tx40_11n);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 1,
- 0x159 + coreNum * 0x10,
- 16,
- &rx2tx_lpf_rc_lut_tx40_11n);
- }
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4),
- 1, 0x3, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- }
-
- if (!NORADIO_ENAB(pi->pubpi)) {
- write_phy_reg(pi, 0x32f, 0x3);
- }
-
- if ((pi->pubpi.radiorev == 4) || (pi->pubpi.radiorev == 6)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
- 1, 0x3, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- }
-
- if ((pi->pubpi.radiorev == 3) || (pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
- if ((pi->sh->sromrev >= 8)
- && (pi->sh->boardflags2 & BFL2_IPALVLSHIFT_3P3))
- ipalvlshift_3p3_war_en = 1;
-
- if (ipalvlshift_3p3_war_en) {
- write_radio_reg(pi, RADIO_2057_GPAIO_CONFIG,
- 0x5);
- write_radio_reg(pi, RADIO_2057_GPAIO_SEL1,
- 0x30);
- write_radio_reg(pi, RADIO_2057_GPAIO_SEL0, 0x0);
- or_radio_reg(pi,
- RADIO_2057_RXTXBIAS_CONFIG_CORE0,
- 0x1);
- or_radio_reg(pi,
- RADIO_2057_RXTXBIAS_CONFIG_CORE1,
- 0x1);
-
- ipa2g_mainbias = 0x1f;
-
- ipa2g_casconv = 0x6f;
-
- ipa2g_biasfilt = 0xaa;
- } else {
-
- ipa2g_mainbias = 0x2b;
-
- ipa2g_casconv = 0x7f;
-
- ipa2g_biasfilt = 0xee;
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- for (coreNum = 0; coreNum <= 1; coreNum++) {
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
- coreNum, IPA2G_IMAIN,
- ipa2g_mainbias);
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
- coreNum, IPA2G_CASCONV,
- ipa2g_casconv);
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
- coreNum,
- IPA2G_BIAS_FILTER,
- ipa2g_biasfilt);
- }
- }
- }
-
- if (PHY_IPA(pi)) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if ((pi->pubpi.radiorev == 3)
- || (pi->pubpi.radiorev == 4)
- || (pi->pubpi.radiorev == 6)) {
-
- txgm_idac_bleed = 0x7f;
- }
-
- for (coreNum = 0; coreNum <= 1; coreNum++) {
- if (txgm_idac_bleed != 0)
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, coreNum,
- TXGM_IDAC_BLEED,
- txgm_idac_bleed);
- }
-
- if (pi->pubpi.radiorev == 5) {
-
- for (coreNum = 0; coreNum <= 1;
- coreNum++) {
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, coreNum,
- IPA2G_CASCONV,
- 0x13);
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, coreNum,
- IPA2G_IMAIN,
- 0x1f);
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, coreNum,
- IPA2G_BIAS_FILTER,
- 0xee);
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, coreNum,
- PAD2G_IDACS,
- 0x8a);
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, coreNum,
- PAD_BIAS_FILTER_BWS,
- 0x3e);
- }
-
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- if (CHSPEC_IS40(pi->radio_chanspec) ==
- 0) {
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, 0,
- IPA2G_IMAIN,
- 0x14);
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, 1,
- IPA2G_IMAIN,
- 0x12);
- } else {
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, 0,
- IPA2G_IMAIN,
- 0x16);
- WRITE_RADIO_REG4(pi, RADIO_2057,
- CORE, 1,
- IPA2G_IMAIN,
- 0x16);
- }
- }
-
- } else {
- freq =
- CHAN5G_FREQ(CHSPEC_CHANNEL
- (pi->radio_chanspec));
- if (((freq >= 5180) && (freq <= 5230))
- || ((freq >= 5745) && (freq <= 5805))) {
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
- 0, IPA5G_BIAS_FILTER,
- 0xff);
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
- 1, IPA5G_BIAS_FILTER,
- 0xff);
- }
- }
- } else {
-
- if (pi->pubpi.radiorev != 5) {
- for (coreNum = 0; coreNum <= 1; coreNum++) {
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
- coreNum,
- TXMIX2G_TUNE_BOOST_PU,
- 0x61);
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
- coreNum,
- TXGM_IDAC_BLEED, 0x70);
- }
- }
- }
-
- if (pi->pubpi.radiorev == 4) {
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
- 0x05, 16,
- &afectrl_adc_ctrl1_rev7);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
- 0x15, 16,
- &afectrl_adc_ctrl1_rev7);
-
- for (coreNum = 0; coreNum <= 1; coreNum++) {
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
- AFE_VCM_CAL_MASTER, 0x0);
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
- AFE_SET_VCM_I, 0x3f);
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
- AFE_SET_VCM_Q, 0x3f);
- }
- } else {
- mod_phy_reg(pi, 0xa6, (0x1 << 2), (0x1 << 2));
- mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
- mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
- mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
-
- mod_phy_reg(pi, 0xa6, (0x1 << 0), 0);
- mod_phy_reg(pi, 0x8f, (0x1 << 0), (0x1 << 0));
- mod_phy_reg(pi, 0xa7, (0x1 << 0), 0);
- mod_phy_reg(pi, 0xa5, (0x1 << 0), (0x1 << 0));
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
- 0x05, 16,
- &afectrl_adc_ctrl2_rev7);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1,
- 0x15, 16,
- &afectrl_adc_ctrl2_rev7);
-
- mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
- mod_phy_reg(pi, 0x8f, (0x1 << 2), 0);
- mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
- mod_phy_reg(pi, 0xa5, (0x1 << 2), 0);
- }
-
- write_phy_reg(pi, 0x6a, 0x2);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 256, 32,
- &min_nvar_offset_6mbps);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x138, 16,
- &rfseq_pktgn_lpf_hpc_rev7);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x141, 16,
- &rfseq_pktgn_lpf_h_hpc_rev7);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 3, 0x133, 16,
- &rfseq_htpktgn_lpf_hpc_rev7);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x146, 16,
- &rfseq_cckpktgn_lpf_hpc_rev7);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x123, 16,
- &rfseq_tx2rx_lpf_h_hpc_rev7);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1, 0x12A, 16,
- &rfseq_rx2tx_lpf_h_hpc_rev7);
-
- if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
- 32, &min_nvar_val);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
- 127, 32, &min_nvar_val);
- } else {
- min_nvar_val = noise_var_tbl_rev7[3];
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
- 32, &min_nvar_val);
-
- min_nvar_val = noise_var_tbl_rev7[127];
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
- 127, 32, &min_nvar_val);
- }
-
- wlc_phy_workarounds_nphy_gainctrl(pi);
-
- pdetrange =
- (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
- pdetrange : pi->srom_fem2g.pdetrange;
-
- if (pdetrange == 0) {
- chan_freq_range =
- wlc_phy_get_chan_freq_range_nphy(pi, 0);
- if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
- aux_adc_vmid_rev7_core0[3] = 0x70;
- aux_adc_vmid_rev7_core1[3] = 0x70;
- aux_adc_gain_rev7[3] = 2;
- } else {
- aux_adc_vmid_rev7_core0[3] = 0x80;
- aux_adc_vmid_rev7_core1[3] = 0x80;
- aux_adc_gain_rev7[3] = 3;
- }
- } else if (pdetrange == 1) {
- if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
- aux_adc_vmid_rev7_core0[3] = 0x7c;
- aux_adc_vmid_rev7_core1[3] = 0x7c;
- aux_adc_gain_rev7[3] = 2;
- } else {
- aux_adc_vmid_rev7_core0[3] = 0x8c;
- aux_adc_vmid_rev7_core1[3] = 0x8c;
- aux_adc_gain_rev7[3] = 1;
- }
- } else if (pdetrange == 2) {
- if (pi->pubpi.radioid == BCM2057_ID) {
- if ((pi->pubpi.radiorev == 5)
- || (pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
- if (chan_freq_range ==
- WL_CHAN_FREQ_RANGE_2G) {
- aux_adc_vmid_rev7_core0[3] =
- 0x8c;
- aux_adc_vmid_rev7_core1[3] =
- 0x8c;
- aux_adc_gain_rev7[3] = 0;
- } else {
- aux_adc_vmid_rev7_core0[3] =
- 0x96;
- aux_adc_vmid_rev7_core1[3] =
- 0x96;
- aux_adc_gain_rev7[3] = 0;
- }
- }
- }
-
- } else if (pdetrange == 3) {
- if (chan_freq_range == WL_CHAN_FREQ_RANGE_2G) {
- aux_adc_vmid_rev7_core0[3] = 0x89;
- aux_adc_vmid_rev7_core1[3] = 0x89;
- aux_adc_gain_rev7[3] = 0;
- }
-
- } else if (pdetrange == 5) {
-
- if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
- aux_adc_vmid_rev7_core0[3] = 0x80;
- aux_adc_vmid_rev7_core1[3] = 0x80;
- aux_adc_gain_rev7[3] = 3;
- } else {
- aux_adc_vmid_rev7_core0[3] = 0x70;
- aux_adc_vmid_rev7_core1[3] = 0x70;
- aux_adc_gain_rev7[3] = 2;
- }
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x08, 16,
- &aux_adc_vmid_rev7_core0);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x18, 16,
- &aux_adc_vmid_rev7_core1);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x0c, 16,
- &aux_adc_gain_rev7);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4, 0x1c, 16,
- &aux_adc_gain_rev7);
-
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- write_phy_reg(pi, 0x23f, 0x1f8);
- write_phy_reg(pi, 0x240, 0x1f8);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
- 1, 0, 32, &leg_data_weights);
- leg_data_weights = leg_data_weights & 0xffffff;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
- 1, 0, 32, &leg_data_weights);
-
- alpha0 = 293;
- alpha1 = 435;
- alpha2 = 261;
- beta0 = 366;
- beta1 = 205;
- beta2 = 32;
- write_phy_reg(pi, 0x145, alpha0);
- write_phy_reg(pi, 0x146, alpha1);
- write_phy_reg(pi, 0x147, alpha2);
- write_phy_reg(pi, 0x148, beta0);
- write_phy_reg(pi, 0x149, beta1);
- write_phy_reg(pi, 0x14a, beta2);
-
- write_phy_reg(pi, 0x38, 0xC);
- write_phy_reg(pi, 0x2ae, 0xC);
-
- wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_TX2RX,
- rfseq_tx2rx_events_rev3,
- rfseq_tx2rx_dlys_rev3,
- sizeof(rfseq_tx2rx_events_rev3) /
- sizeof(rfseq_tx2rx_events_rev3[0]));
-
- if (PHY_IPA(pi)) {
- wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
- rfseq_rx2tx_events_rev3_ipa,
- rfseq_rx2tx_dlys_rev3_ipa,
- sizeof
- (rfseq_rx2tx_events_rev3_ipa) /
- sizeof
- (rfseq_rx2tx_events_rev3_ipa
- [0]));
- }
-
- if ((pi->sh->hw_phyrxchain != 0x3) &&
- (pi->sh->hw_phyrxchain != pi->sh->hw_phytxchain)) {
-
- if (PHY_IPA(pi)) {
- rfseq_rx2tx_dlys_rev3[5] = 59;
- rfseq_rx2tx_dlys_rev3[6] = 1;
- rfseq_rx2tx_events_rev3[7] =
- NPHY_REV3_RFSEQ_CMD_END;
- }
-
- wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX,
- rfseq_rx2tx_events_rev3,
- rfseq_rx2tx_dlys_rev3,
- sizeof(rfseq_rx2tx_events_rev3) /
- sizeof(rfseq_rx2tx_events_rev3
- [0]));
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- write_phy_reg(pi, 0x6a, 0x2);
- } else {
- write_phy_reg(pi, 0x6a, 0x9c40);
- }
-
- mod_phy_reg(pi, 0x294, (0xf << 8), (7 << 8));
-
- if (CHSPEC_IS40(pi->radio_chanspec) == 0) {
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
- 32, &min_nvar_val);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
- 127, 32, &min_nvar_val);
- } else {
- min_nvar_val = noise_var_tbl_rev3[3];
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1, 3,
- 32, &min_nvar_val);
-
- min_nvar_val = noise_var_tbl_rev3[127];
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
- 127, 32, &min_nvar_val);
- }
-
- wlc_phy_workarounds_nphy_gainctrl(pi);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x00, 16,
- &dac_control);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x10, 16,
- &dac_control);
-
- pdetrange =
- (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
- pdetrange : pi->srom_fem2g.pdetrange;
-
- if (pdetrange == 0) {
- if (NREV_GE(pi->pubpi.phy_rev, 4)) {
- aux_adc_vmid = aux_adc_vmid_rev4;
- aux_adc_gain = aux_adc_gain_rev4;
- } else {
- aux_adc_vmid = aux_adc_vmid_rev3;
- aux_adc_gain = aux_adc_gain_rev3;
- }
- chan_freq_range =
- wlc_phy_get_chan_freq_range_nphy(pi, 0);
- if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
- switch (chan_freq_range) {
- case WL_CHAN_FREQ_RANGE_5GL:
- aux_adc_vmid[3] = 0x89;
- aux_adc_gain[3] = 0;
- break;
- case WL_CHAN_FREQ_RANGE_5GM:
- aux_adc_vmid[3] = 0x89;
- aux_adc_gain[3] = 0;
- break;
- case WL_CHAN_FREQ_RANGE_5GH:
- aux_adc_vmid[3] = 0x89;
- aux_adc_gain[3] = 0;
- break;
- default:
- break;
- }
- }
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x08, 16, aux_adc_vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x18, 16, aux_adc_vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x0c, 16, aux_adc_gain);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x1c, 16, aux_adc_gain);
- } else if (pdetrange == 1) {
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x08, 16, sk_adc_vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x18, 16, sk_adc_vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x0c, 16, sk_adc_gain);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x1c, 16, sk_adc_gain);
- } else if (pdetrange == 2) {
-
- u16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x74 };
- u16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x04 };
-
- if (NREV_GE(pi->pubpi.phy_rev, 6)) {
- chan_freq_range =
- wlc_phy_get_chan_freq_range_nphy(pi, 0);
- if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
- bcm_adc_vmid[3] = 0x8e;
- bcm_adc_gain[3] = 0x03;
- } else {
- bcm_adc_vmid[3] = 0x94;
- bcm_adc_gain[3] = 0x03;
- }
- } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
- bcm_adc_vmid[3] = 0x84;
- bcm_adc_gain[3] = 0x02;
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x08, 16, bcm_adc_vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x18, 16, bcm_adc_vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x0c, 16, bcm_adc_gain);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x1c, 16, bcm_adc_gain);
- } else if (pdetrange == 3) {
- chan_freq_range =
- wlc_phy_get_chan_freq_range_nphy(pi, 0);
- if ((NREV_GE(pi->pubpi.phy_rev, 4))
- && (chan_freq_range == WL_CHAN_FREQ_RANGE_2G)) {
-
- u16 auxadc_vmid[] = {
- 0xa2, 0xb4, 0xb4, 0x270 };
- u16 auxadc_gain[] = {
- 0x02, 0x02, 0x02, 0x00 };
-
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_AFECTRL, 4,
- 0x08, 16, auxadc_vmid);
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_AFECTRL, 4,
- 0x18, 16, auxadc_vmid);
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_AFECTRL, 4,
- 0x0c, 16, auxadc_gain);
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_AFECTRL, 4,
- 0x1c, 16, auxadc_gain);
- }
- } else if ((pdetrange == 4) || (pdetrange == 5)) {
- u16 bcm_adc_vmid[] = { 0xa2, 0xb4, 0xb4, 0x0 };
- u16 bcm_adc_gain[] = { 0x02, 0x02, 0x02, 0x0 };
- u16 Vmid[2], Av[2];
-
- chan_freq_range =
- wlc_phy_get_chan_freq_range_nphy(pi, 0);
- if (chan_freq_range != WL_CHAN_FREQ_RANGE_2G) {
- Vmid[0] = (pdetrange == 4) ? 0x8e : 0x89;
- Vmid[1] = (pdetrange == 4) ? 0x96 : 0x89;
- Av[0] = (pdetrange == 4) ? 2 : 0;
- Av[1] = (pdetrange == 4) ? 2 : 0;
- } else {
- Vmid[0] = (pdetrange == 4) ? 0x89 : 0x74;
- Vmid[1] = (pdetrange == 4) ? 0x8b : 0x70;
- Av[0] = (pdetrange == 4) ? 2 : 0;
- Av[1] = (pdetrange == 4) ? 2 : 0;
- }
-
- bcm_adc_vmid[3] = Vmid[0];
- bcm_adc_gain[3] = Av[0];
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x08, 16, bcm_adc_vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x0c, 16, bcm_adc_gain);
-
- bcm_adc_vmid[3] = Vmid[1];
- bcm_adc_gain[3] = Av[1];
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x18, 16, bcm_adc_vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
- 0x1c, 16, bcm_adc_gain);
- }
-
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_MAST_BIAS | RADIO_2056_RX0),
- 0x0);
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_MAST_BIAS | RADIO_2056_RX1),
- 0x0);
-
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_BIAS_MAIN | RADIO_2056_RX0),
- 0x6);
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_BIAS_MAIN | RADIO_2056_RX1),
- 0x6);
-
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_BIAS_AUX | RADIO_2056_RX0),
- 0x7);
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_BIAS_AUX | RADIO_2056_RX1),
- 0x7);
-
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_LOB_BIAS | RADIO_2056_RX0),
- 0x88);
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_LOB_BIAS | RADIO_2056_RX1),
- 0x88);
-
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_CMFB_IDAC | RADIO_2056_RX0),
- 0x0);
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXA_CMFB_IDAC | RADIO_2056_RX1),
- 0x0);
-
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXG_CMFB_IDAC | RADIO_2056_RX0),
- 0x0);
- write_radio_reg(pi,
- (RADIO_2056_RX_MIXG_CMFB_IDAC | RADIO_2056_RX1),
- 0x0);
-
- triso =
- (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.
- triso : pi->srom_fem2g.triso;
- if (triso == 7) {
- wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_0);
- wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, PHY_CORE_1);
- }
-
- wlc_phy_war_txchain_upd_nphy(pi, pi->sh->hw_phytxchain);
-
- if (((pi->sh->boardflags2 & BFL2_APLL_WAR) &&
- (CHSPEC_IS5G(pi->radio_chanspec))) ||
- (((pi->sh->boardflags2 & BFL2_GPLL_WAR) ||
- (pi->sh->boardflags2 & BFL2_GPLL_WAR2)) &&
- (CHSPEC_IS2G(pi->radio_chanspec)))) {
- nss1_data_weights = 0x00088888;
- ht_data_weights = 0x00088888;
- stbc_data_weights = 0x00088888;
- } else {
- nss1_data_weights = 0x88888888;
- ht_data_weights = 0x88888888;
- stbc_data_weights = 0x88888888;
- }
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
- 1, 1, 32, &nss1_data_weights);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
- 1, 2, 32, &ht_data_weights);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL,
- 1, 3, 32, &stbc_data_weights);
-
- if (NREV_IS(pi->pubpi.phy_rev, 4)) {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- write_radio_reg(pi,
- RADIO_2056_TX_GMBB_IDAC |
- RADIO_2056_TX0, 0x70);
- write_radio_reg(pi,
- RADIO_2056_TX_GMBB_IDAC |
- RADIO_2056_TX1, 0x70);
- }
- }
-
- if (!pi->edcrs_threshold_lock) {
- write_phy_reg(pi, 0x224, 0x3eb);
- write_phy_reg(pi, 0x225, 0x3eb);
- write_phy_reg(pi, 0x226, 0x341);
- write_phy_reg(pi, 0x227, 0x341);
- write_phy_reg(pi, 0x228, 0x42b);
- write_phy_reg(pi, 0x229, 0x42b);
- write_phy_reg(pi, 0x22a, 0x381);
- write_phy_reg(pi, 0x22b, 0x381);
- write_phy_reg(pi, 0x22c, 0x42b);
- write_phy_reg(pi, 0x22d, 0x42b);
- write_phy_reg(pi, 0x22e, 0x381);
- write_phy_reg(pi, 0x22f, 0x381);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 6)) {
-
- if (pi->sh->boardflags2 & BFL2_SINGLEANT_CCK) {
- wlapi_bmac_mhf(pi->sh->physhim, MHF4,
- MHF4_BPHY_TXCORE0,
- MHF4_BPHY_TXCORE0, WLC_BAND_ALL);
- }
- }
- } else {
-
- if (pi->sh->boardflags2 & BFL2_SKWRKFEM_BRD ||
- (pi->sh->boardtype == 0x8b)) {
- uint i;
- u8 war_dlys[] = { 1, 6, 6, 2, 4, 20, 1 };
- for (i = 0; i < ARRAY_SIZE(rfseq_rx2tx_dlys); i++)
- rfseq_rx2tx_dlys[i] = war_dlys[i];
- }
-
- if (CHSPEC_IS5G(pi->radio_chanspec) && pi->phy_5g_pwrgain) {
- and_radio_reg(pi, RADIO_2055_CORE1_TX_RF_SPARE, 0xf7);
- and_radio_reg(pi, RADIO_2055_CORE2_TX_RF_SPARE, 0xf7);
- } else {
- or_radio_reg(pi, RADIO_2055_CORE1_TX_RF_SPARE, 0x8);
- or_radio_reg(pi, RADIO_2055_CORE2_TX_RF_SPARE, 0x8);
- }
-
- regval = 0x000a;
- wlc_phy_table_write_nphy(pi, 8, 1, 0, 16, ®val);
- wlc_phy_table_write_nphy(pi, 8, 1, 0x10, 16, ®val);
-
- if (NREV_LT(pi->pubpi.phy_rev, 3)) {
- regval = 0xcdaa;
- wlc_phy_table_write_nphy(pi, 8, 1, 0x02, 16, ®val);
- wlc_phy_table_write_nphy(pi, 8, 1, 0x12, 16, ®val);
- }
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
- regval = 0x0000;
- wlc_phy_table_write_nphy(pi, 8, 1, 0x08, 16, ®val);
- wlc_phy_table_write_nphy(pi, 8, 1, 0x18, 16, ®val);
-
- regval = 0x7aab;
- wlc_phy_table_write_nphy(pi, 8, 1, 0x07, 16, ®val);
- wlc_phy_table_write_nphy(pi, 8, 1, 0x17, 16, ®val);
-
- regval = 0x0800;
- wlc_phy_table_write_nphy(pi, 8, 1, 0x06, 16, ®val);
- wlc_phy_table_write_nphy(pi, 8, 1, 0x16, 16, ®val);
- }
-
- write_phy_reg(pi, 0xf8, 0x02d8);
- write_phy_reg(pi, 0xf9, 0x0301);
- write_phy_reg(pi, 0xfa, 0x02d8);
- write_phy_reg(pi, 0xfb, 0x0301);
-
- wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX, rfseq_rx2tx_events,
- rfseq_rx2tx_dlys,
- sizeof(rfseq_rx2tx_events) /
- sizeof(rfseq_rx2tx_events[0]));
-
- wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_TX2RX, rfseq_tx2rx_events,
- rfseq_tx2rx_dlys,
- sizeof(rfseq_tx2rx_events) /
- sizeof(rfseq_tx2rx_events[0]));
-
- wlc_phy_workarounds_nphy_gainctrl(pi);
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
-
- if (read_phy_reg(pi, 0xa0) & NPHY_MLenable)
- wlapi_bmac_mhf(pi->sh->physhim, MHF3,
- MHF3_NPHY_MLADV_WAR,
- MHF3_NPHY_MLADV_WAR,
- WLC_BAND_ALL);
-
- } else if (NREV_IS(pi->pubpi.phy_rev, 2)) {
- write_phy_reg(pi, 0x1e3, 0x0);
- write_phy_reg(pi, 0x1e4, 0x0);
- }
-
- if (NREV_LT(pi->pubpi.phy_rev, 2))
- mod_phy_reg(pi, 0x90, (0x1 << 7), 0);
-
- alpha0 = 293;
- alpha1 = 435;
- alpha2 = 261;
- beta0 = 366;
- beta1 = 205;
- beta2 = 32;
- write_phy_reg(pi, 0x145, alpha0);
- write_phy_reg(pi, 0x146, alpha1);
- write_phy_reg(pi, 0x147, alpha2);
- write_phy_reg(pi, 0x148, beta0);
- write_phy_reg(pi, 0x149, beta1);
- write_phy_reg(pi, 0x14a, beta2);
-
- if (NREV_LT(pi->pubpi.phy_rev, 3)) {
- mod_phy_reg(pi, 0x142, (0xf << 12), 0);
-
- write_phy_reg(pi, 0x192, 0xb5);
- write_phy_reg(pi, 0x193, 0xa4);
- write_phy_reg(pi, 0x194, 0x0);
- }
-
- if (NREV_IS(pi->pubpi.phy_rev, 2)) {
- mod_phy_reg(pi, 0x221,
- NPHY_FORCESIG_DECODEGATEDCLKS,
- NPHY_FORCESIG_DECODEGATEDCLKS);
- }
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-static void wlc_phy_workarounds_nphy_gainctrl(phy_info_t *pi)
-{
- u16 w1th, hpf_code, currband;
- int ctr;
- u8 rfseq_updategainu_events[] = {
- NPHY_RFSEQ_CMD_RX_GAIN,
- NPHY_RFSEQ_CMD_CLR_HIQ_DIS,
- NPHY_RFSEQ_CMD_SET_HPF_BW
- };
- u8 rfseq_updategainu_dlys[] = { 10, 30, 1 };
- s8 lna1G_gain_db[] = { 7, 11, 16, 23 };
- s8 lna1G_gain_db_rev4[] = { 8, 12, 17, 25 };
- s8 lna1G_gain_db_rev5[] = { 9, 13, 18, 26 };
- s8 lna1G_gain_db_rev6[] = { 8, 13, 18, 25 };
- s8 lna1G_gain_db_rev6_224B0[] = { 10, 14, 19, 27 };
- s8 lna1A_gain_db[] = { 7, 11, 17, 23 };
- s8 lna1A_gain_db_rev4[] = { 8, 12, 18, 23 };
- s8 lna1A_gain_db_rev5[] = { 6, 10, 16, 21 };
- s8 lna1A_gain_db_rev6[] = { 6, 10, 16, 21 };
- s8 *lna1_gain_db = NULL;
- s8 lna2G_gain_db[] = { -5, 6, 10, 14 };
- s8 lna2G_gain_db_rev5[] = { -3, 7, 11, 16 };
- s8 lna2G_gain_db_rev6[] = { -5, 6, 10, 14 };
- s8 lna2G_gain_db_rev6_224B0[] = { -5, 6, 10, 15 };
- s8 lna2A_gain_db[] = { -6, 2, 6, 10 };
- s8 lna2A_gain_db_rev4[] = { -5, 2, 6, 10 };
- s8 lna2A_gain_db_rev5[] = { -7, 0, 4, 8 };
- s8 lna2A_gain_db_rev6[] = { -7, 0, 4, 8 };
- s8 *lna2_gain_db = NULL;
- s8 tiaG_gain_db[] = {
- 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A };
- s8 tiaA_gain_db[] = {
- 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 };
- s8 tiaA_gain_db_rev4[] = {
- 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
- s8 tiaA_gain_db_rev5[] = {
- 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
- s8 tiaA_gain_db_rev6[] = {
- 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d, 0x0d };
- s8 *tia_gain_db;
- s8 tiaG_gainbits[] = {
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
- s8 tiaA_gainbits[] = {
- 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 };
- s8 tiaA_gainbits_rev4[] = {
- 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
- s8 tiaA_gainbits_rev5[] = {
- 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
- s8 tiaA_gainbits_rev6[] = {
- 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 };
- s8 *tia_gainbits;
- s8 lpf_gain_db[] = { 0x00, 0x06, 0x0c, 0x12, 0x12, 0x12 };
- s8 lpf_gainbits[] = { 0x00, 0x01, 0x02, 0x03, 0x03, 0x03 };
- u16 rfseqG_init_gain[] = { 0x613f, 0x613f, 0x613f, 0x613f };
- u16 rfseqG_init_gain_rev4[] = { 0x513f, 0x513f, 0x513f, 0x513f };
- u16 rfseqG_init_gain_rev5[] = { 0x413f, 0x413f, 0x413f, 0x413f };
- u16 rfseqG_init_gain_rev5_elna[] = {
- 0x013f, 0x013f, 0x013f, 0x013f };
- u16 rfseqG_init_gain_rev6[] = { 0x513f, 0x513f };
- u16 rfseqG_init_gain_rev6_224B0[] = { 0x413f, 0x413f };
- u16 rfseqG_init_gain_rev6_elna[] = { 0x113f, 0x113f };
- u16 rfseqA_init_gain[] = { 0x516f, 0x516f, 0x516f, 0x516f };
- u16 rfseqA_init_gain_rev4[] = { 0x614f, 0x614f, 0x614f, 0x614f };
- u16 rfseqA_init_gain_rev4_elna[] = {
- 0x314f, 0x314f, 0x314f, 0x314f };
- u16 rfseqA_init_gain_rev5[] = { 0x714f, 0x714f, 0x714f, 0x714f };
- u16 rfseqA_init_gain_rev6[] = { 0x714f, 0x714f };
- u16 *rfseq_init_gain;
- u16 initG_gaincode = 0x627e;
- u16 initG_gaincode_rev4 = 0x527e;
- u16 initG_gaincode_rev5 = 0x427e;
- u16 initG_gaincode_rev5_elna = 0x027e;
- u16 initG_gaincode_rev6 = 0x527e;
- u16 initG_gaincode_rev6_224B0 = 0x427e;
- u16 initG_gaincode_rev6_elna = 0x127e;
- u16 initA_gaincode = 0x52de;
- u16 initA_gaincode_rev4 = 0x629e;
- u16 initA_gaincode_rev4_elna = 0x329e;
- u16 initA_gaincode_rev5 = 0x729e;
- u16 initA_gaincode_rev6 = 0x729e;
- u16 init_gaincode;
- u16 clip1hiG_gaincode = 0x107e;
- u16 clip1hiG_gaincode_rev4 = 0x007e;
- u16 clip1hiG_gaincode_rev5 = 0x1076;
- u16 clip1hiG_gaincode_rev6 = 0x007e;
- u16 clip1hiA_gaincode = 0x00de;
- u16 clip1hiA_gaincode_rev4 = 0x029e;
- u16 clip1hiA_gaincode_rev5 = 0x029e;
- u16 clip1hiA_gaincode_rev6 = 0x029e;
- u16 clip1hi_gaincode;
- u16 clip1mdG_gaincode = 0x0066;
- u16 clip1mdA_gaincode = 0x00ca;
- u16 clip1mdA_gaincode_rev4 = 0x1084;
- u16 clip1mdA_gaincode_rev5 = 0x2084;
- u16 clip1mdA_gaincode_rev6 = 0x2084;
- u16 clip1md_gaincode = 0;
- u16 clip1loG_gaincode = 0x0074;
- u16 clip1loG_gaincode_rev5[] = {
- 0x0062, 0x0064, 0x006a, 0x106a, 0x106c, 0x1074, 0x107c, 0x207c
- };
- u16 clip1loG_gaincode_rev6[] = {
- 0x106a, 0x106c, 0x1074, 0x107c, 0x007e, 0x107e, 0x207e, 0x307e
- };
- u16 clip1loG_gaincode_rev6_224B0 = 0x1074;
- u16 clip1loA_gaincode = 0x00cc;
- u16 clip1loA_gaincode_rev4 = 0x0086;
- u16 clip1loA_gaincode_rev5 = 0x2086;
- u16 clip1loA_gaincode_rev6 = 0x2086;
- u16 clip1lo_gaincode;
- u8 crsminG_th = 0x18;
- u8 crsminG_th_rev5 = 0x18;
- u8 crsminG_th_rev6 = 0x18;
- u8 crsminA_th = 0x1e;
- u8 crsminA_th_rev4 = 0x24;
- u8 crsminA_th_rev5 = 0x24;
- u8 crsminA_th_rev6 = 0x24;
- u8 crsmin_th;
- u8 crsminlG_th = 0x18;
- u8 crsminlG_th_rev5 = 0x18;
- u8 crsminlG_th_rev6 = 0x18;
- u8 crsminlA_th = 0x1e;
- u8 crsminlA_th_rev4 = 0x24;
- u8 crsminlA_th_rev5 = 0x24;
- u8 crsminlA_th_rev6 = 0x24;
- u8 crsminl_th = 0;
- u8 crsminuG_th = 0x18;
- u8 crsminuG_th_rev5 = 0x18;
- u8 crsminuG_th_rev6 = 0x18;
- u8 crsminuA_th = 0x1e;
- u8 crsminuA_th_rev4 = 0x24;
- u8 crsminuA_th_rev5 = 0x24;
- u8 crsminuA_th_rev6 = 0x24;
- u8 crsminuA_th_rev6_224B0 = 0x2d;
- u8 crsminu_th;
- u16 nbclipG_th = 0x20d;
- u16 nbclipG_th_rev4 = 0x1a1;
- u16 nbclipG_th_rev5 = 0x1d0;
- u16 nbclipG_th_rev6 = 0x1d0;
- u16 nbclipA_th = 0x1a1;
- u16 nbclipA_th_rev4 = 0x107;
- u16 nbclipA_th_rev5 = 0x0a9;
- u16 nbclipA_th_rev6 = 0x0f0;
- u16 nbclip_th = 0;
- u8 w1clipG_th = 5;
- u8 w1clipG_th_rev5 = 9;
- u8 w1clipG_th_rev6 = 5;
- u8 w1clipA_th = 25, w1clip_th;
- u8 rssi_gain_default = 0x50;
- u8 rssiG_gain_rev6_224B0 = 0x50;
- u8 rssiA_gain_rev5 = 0x90;
- u8 rssiA_gain_rev6 = 0x90;
- u8 rssi_gain;
- u16 regval[21];
- u8 triso;
-
- triso = (CHSPEC_IS5G(pi->radio_chanspec)) ? pi->srom_fem5g.triso :
- pi->srom_fem2g.triso;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (pi->pubpi.radiorev == 5) {
-
- wlc_phy_workarounds_nphy_gainctrl_2057_rev5(pi);
- } else if (pi->pubpi.radiorev == 7) {
- wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
-
- mod_phy_reg(pi, 0x283, (0xff << 0), (0x44 << 0));
- mod_phy_reg(pi, 0x280, (0xff << 0), (0x44 << 0));
-
- } else if ((pi->pubpi.radiorev == 3)
- || (pi->pubpi.radiorev == 8)) {
- wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
-
- if (pi->pubpi.radiorev == 8) {
- mod_phy_reg(pi, 0x283,
- (0xff << 0), (0x44 << 0));
- mod_phy_reg(pi, 0x280,
- (0xff << 0), (0x44 << 0));
- }
- } else {
- wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi);
- }
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- mod_phy_reg(pi, 0xa0, (0x1 << 6), (1 << 6));
-
- mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
- mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
-
- currband =
- read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
- if (currband == 0) {
- if (NREV_GE(pi->pubpi.phy_rev, 6)) {
- if (pi->pubpi.radiorev == 11) {
- lna1_gain_db = lna1G_gain_db_rev6_224B0;
- lna2_gain_db = lna2G_gain_db_rev6_224B0;
- rfseq_init_gain =
- rfseqG_init_gain_rev6_224B0;
- init_gaincode =
- initG_gaincode_rev6_224B0;
- clip1hi_gaincode =
- clip1hiG_gaincode_rev6;
- clip1lo_gaincode =
- clip1loG_gaincode_rev6_224B0;
- nbclip_th = nbclipG_th_rev6;
- w1clip_th = w1clipG_th_rev6;
- crsmin_th = crsminG_th_rev6;
- crsminl_th = crsminlG_th_rev6;
- crsminu_th = crsminuG_th_rev6;
- rssi_gain = rssiG_gain_rev6_224B0;
- } else {
- lna1_gain_db = lna1G_gain_db_rev6;
- lna2_gain_db = lna2G_gain_db_rev6;
- if (pi->sh->boardflags & BFL_EXTLNA) {
-
- rfseq_init_gain =
- rfseqG_init_gain_rev6_elna;
- init_gaincode =
- initG_gaincode_rev6_elna;
- } else {
- rfseq_init_gain =
- rfseqG_init_gain_rev6;
- init_gaincode =
- initG_gaincode_rev6;
- }
- clip1hi_gaincode =
- clip1hiG_gaincode_rev6;
- switch (triso) {
- case 0:
- clip1lo_gaincode =
- clip1loG_gaincode_rev6[0];
- break;
- case 1:
- clip1lo_gaincode =
- clip1loG_gaincode_rev6[1];
- break;
- case 2:
- clip1lo_gaincode =
- clip1loG_gaincode_rev6[2];
- break;
- case 3:
- default:
-
- clip1lo_gaincode =
- clip1loG_gaincode_rev6[3];
- break;
- case 4:
- clip1lo_gaincode =
- clip1loG_gaincode_rev6[4];
- break;
- case 5:
- clip1lo_gaincode =
- clip1loG_gaincode_rev6[5];
- break;
- case 6:
- clip1lo_gaincode =
- clip1loG_gaincode_rev6[6];
- break;
- case 7:
- clip1lo_gaincode =
- clip1loG_gaincode_rev6[7];
- break;
- }
- nbclip_th = nbclipG_th_rev6;
- w1clip_th = w1clipG_th_rev6;
- crsmin_th = crsminG_th_rev6;
- crsminl_th = crsminlG_th_rev6;
- crsminu_th = crsminuG_th_rev6;
- rssi_gain = rssi_gain_default;
- }
- } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
- lna1_gain_db = lna1G_gain_db_rev5;
- lna2_gain_db = lna2G_gain_db_rev5;
- if (pi->sh->boardflags & BFL_EXTLNA) {
-
- rfseq_init_gain =
- rfseqG_init_gain_rev5_elna;
- init_gaincode =
- initG_gaincode_rev5_elna;
- } else {
- rfseq_init_gain = rfseqG_init_gain_rev5;
- init_gaincode = initG_gaincode_rev5;
- }
- clip1hi_gaincode = clip1hiG_gaincode_rev5;
- switch (triso) {
- case 0:
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[0];
- break;
- case 1:
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[1];
- break;
- case 2:
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[2];
- break;
- case 3:
-
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[3];
- break;
- case 4:
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[4];
- break;
- case 5:
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[5];
- break;
- case 6:
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[6];
- break;
- case 7:
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[7];
- break;
- default:
- clip1lo_gaincode =
- clip1loG_gaincode_rev5[3];
- break;
- }
- nbclip_th = nbclipG_th_rev5;
- w1clip_th = w1clipG_th_rev5;
- crsmin_th = crsminG_th_rev5;
- crsminl_th = crsminlG_th_rev5;
- crsminu_th = crsminuG_th_rev5;
- rssi_gain = rssi_gain_default;
- } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
- lna1_gain_db = lna1G_gain_db_rev4;
- lna2_gain_db = lna2G_gain_db;
- rfseq_init_gain = rfseqG_init_gain_rev4;
- init_gaincode = initG_gaincode_rev4;
- clip1hi_gaincode = clip1hiG_gaincode_rev4;
- clip1lo_gaincode = clip1loG_gaincode;
- nbclip_th = nbclipG_th_rev4;
- w1clip_th = w1clipG_th;
- crsmin_th = crsminG_th;
- crsminl_th = crsminlG_th;
- crsminu_th = crsminuG_th;
- rssi_gain = rssi_gain_default;
- } else {
- lna1_gain_db = lna1G_gain_db;
- lna2_gain_db = lna2G_gain_db;
- rfseq_init_gain = rfseqG_init_gain;
- init_gaincode = initG_gaincode;
- clip1hi_gaincode = clip1hiG_gaincode;
- clip1lo_gaincode = clip1loG_gaincode;
- nbclip_th = nbclipG_th;
- w1clip_th = w1clipG_th;
- crsmin_th = crsminG_th;
- crsminl_th = crsminlG_th;
- crsminu_th = crsminuG_th;
- rssi_gain = rssi_gain_default;
- }
- tia_gain_db = tiaG_gain_db;
- tia_gainbits = tiaG_gainbits;
- clip1md_gaincode = clip1mdG_gaincode;
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 6)) {
- lna1_gain_db = lna1A_gain_db_rev6;
- lna2_gain_db = lna2A_gain_db_rev6;
- tia_gain_db = tiaA_gain_db_rev6;
- tia_gainbits = tiaA_gainbits_rev6;
- rfseq_init_gain = rfseqA_init_gain_rev6;
- init_gaincode = initA_gaincode_rev6;
- clip1hi_gaincode = clip1hiA_gaincode_rev6;
- clip1md_gaincode = clip1mdA_gaincode_rev6;
- clip1lo_gaincode = clip1loA_gaincode_rev6;
- crsmin_th = crsminA_th_rev6;
- crsminl_th = crsminlA_th_rev6;
- if ((pi->pubpi.radiorev == 11) &&
- (CHSPEC_IS40(pi->radio_chanspec) == 0)) {
- crsminu_th = crsminuA_th_rev6_224B0;
- } else {
- crsminu_th = crsminuA_th_rev6;
- }
- nbclip_th = nbclipA_th_rev6;
- rssi_gain = rssiA_gain_rev6;
- } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
- lna1_gain_db = lna1A_gain_db_rev5;
- lna2_gain_db = lna2A_gain_db_rev5;
- tia_gain_db = tiaA_gain_db_rev5;
- tia_gainbits = tiaA_gainbits_rev5;
- rfseq_init_gain = rfseqA_init_gain_rev5;
- init_gaincode = initA_gaincode_rev5;
- clip1hi_gaincode = clip1hiA_gaincode_rev5;
- clip1md_gaincode = clip1mdA_gaincode_rev5;
- clip1lo_gaincode = clip1loA_gaincode_rev5;
- crsmin_th = crsminA_th_rev5;
- crsminl_th = crsminlA_th_rev5;
- crsminu_th = crsminuA_th_rev5;
- nbclip_th = nbclipA_th_rev5;
- rssi_gain = rssiA_gain_rev5;
- } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
- lna1_gain_db = lna1A_gain_db_rev4;
- lna2_gain_db = lna2A_gain_db_rev4;
- tia_gain_db = tiaA_gain_db_rev4;
- tia_gainbits = tiaA_gainbits_rev4;
- if (pi->sh->boardflags & BFL_EXTLNA_5GHz) {
-
- rfseq_init_gain =
- rfseqA_init_gain_rev4_elna;
- init_gaincode =
- initA_gaincode_rev4_elna;
- } else {
- rfseq_init_gain = rfseqA_init_gain_rev4;
- init_gaincode = initA_gaincode_rev4;
- }
- clip1hi_gaincode = clip1hiA_gaincode_rev4;
- clip1md_gaincode = clip1mdA_gaincode_rev4;
- clip1lo_gaincode = clip1loA_gaincode_rev4;
- crsmin_th = crsminA_th_rev4;
- crsminl_th = crsminlA_th_rev4;
- crsminu_th = crsminuA_th_rev4;
- nbclip_th = nbclipA_th_rev4;
- rssi_gain = rssi_gain_default;
- } else {
- lna1_gain_db = lna1A_gain_db;
- lna2_gain_db = lna2A_gain_db;
- tia_gain_db = tiaA_gain_db;
- tia_gainbits = tiaA_gainbits;
- rfseq_init_gain = rfseqA_init_gain;
- init_gaincode = initA_gaincode;
- clip1hi_gaincode = clip1hiA_gaincode;
- clip1md_gaincode = clip1mdA_gaincode;
- clip1lo_gaincode = clip1loA_gaincode;
- crsmin_th = crsminA_th;
- crsminl_th = crsminlA_th;
- crsminu_th = crsminuA_th;
- nbclip_th = nbclipA_th;
- rssi_gain = rssi_gain_default;
- }
- w1clip_th = w1clipA_th;
- }
-
- write_radio_reg(pi,
- (RADIO_2056_RX_BIASPOLE_LNAG1_IDAC |
- RADIO_2056_RX0), 0x17);
- write_radio_reg(pi,
- (RADIO_2056_RX_BIASPOLE_LNAG1_IDAC |
- RADIO_2056_RX1), 0x17);
-
- write_radio_reg(pi, (RADIO_2056_RX_LNAG2_IDAC | RADIO_2056_RX0),
- 0xf0);
- write_radio_reg(pi, (RADIO_2056_RX_LNAG2_IDAC | RADIO_2056_RX1),
- 0xf0);
-
- write_radio_reg(pi, (RADIO_2056_RX_RSSI_POLE | RADIO_2056_RX0),
- 0x0);
- write_radio_reg(pi, (RADIO_2056_RX_RSSI_POLE | RADIO_2056_RX1),
- 0x0);
-
- write_radio_reg(pi, (RADIO_2056_RX_RSSI_GAIN | RADIO_2056_RX0),
- rssi_gain);
- write_radio_reg(pi, (RADIO_2056_RX_RSSI_GAIN | RADIO_2056_RX1),
- rssi_gain);
-
- write_radio_reg(pi,
- (RADIO_2056_RX_BIASPOLE_LNAA1_IDAC |
- RADIO_2056_RX0), 0x17);
- write_radio_reg(pi,
- (RADIO_2056_RX_BIASPOLE_LNAA1_IDAC |
- RADIO_2056_RX1), 0x17);
-
- write_radio_reg(pi, (RADIO_2056_RX_LNAA2_IDAC | RADIO_2056_RX0),
- 0xFF);
- write_radio_reg(pi, (RADIO_2056_RX_LNAA2_IDAC | RADIO_2056_RX1),
- 0xFF);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8,
- 8, lna1_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8,
- 8, lna1_gain_db);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10,
- 8, lna2_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10,
- 8, lna2_gain_db);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20,
- 8, tia_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20,
- 8, tia_gain_db);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20,
- 8, tia_gainbits);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20,
- 8, tia_gainbits);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 6, 0x40,
- 8, &lpf_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 6, 0x40,
- 8, &lpf_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 6, 0x40,
- 8, &lpf_gainbits);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 6, 0x40,
- 8, &lpf_gainbits);
-
- write_phy_reg(pi, 0x20, init_gaincode);
- write_phy_reg(pi, 0x2a7, init_gaincode);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- pi->pubpi.phy_corenum, 0x106, 16,
- rfseq_init_gain);
-
- write_phy_reg(pi, 0x22, clip1hi_gaincode);
- write_phy_reg(pi, 0x2a9, clip1hi_gaincode);
-
- write_phy_reg(pi, 0x24, clip1md_gaincode);
- write_phy_reg(pi, 0x2ab, clip1md_gaincode);
-
- write_phy_reg(pi, 0x37, clip1lo_gaincode);
- write_phy_reg(pi, 0x2ad, clip1lo_gaincode);
-
- mod_phy_reg(pi, 0x27d, (0xff << 0), (crsmin_th << 0));
- mod_phy_reg(pi, 0x280, (0xff << 0), (crsminl_th << 0));
- mod_phy_reg(pi, 0x283, (0xff << 0), (crsminu_th << 0));
-
- write_phy_reg(pi, 0x2b, nbclip_th);
- write_phy_reg(pi, 0x41, nbclip_th);
-
- mod_phy_reg(pi, 0x27, (0x3f << 0), (w1clip_th << 0));
- mod_phy_reg(pi, 0x3d, (0x3f << 0), (w1clip_th << 0));
-
- write_phy_reg(pi, 0x150, 0x809c);
-
- } else {
-
- mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
- mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
-
- write_phy_reg(pi, 0x2b, 0x84);
- write_phy_reg(pi, 0x41, 0x84);
-
- if (CHSPEC_IS20(pi->radio_chanspec)) {
- write_phy_reg(pi, 0x6b, 0x2b);
- write_phy_reg(pi, 0x6c, 0x2b);
- write_phy_reg(pi, 0x6d, 0x9);
- write_phy_reg(pi, 0x6e, 0x9);
- }
-
- w1th = NPHY_RSSICAL_W1_TARGET - 4;
- mod_phy_reg(pi, 0x27, (0x3f << 0), (w1th << 0));
- mod_phy_reg(pi, 0x3d, (0x3f << 0), (w1th << 0));
-
- if (CHSPEC_IS20(pi->radio_chanspec)) {
- mod_phy_reg(pi, 0x1c, (0x1f << 0), (0x1 << 0));
- mod_phy_reg(pi, 0x32, (0x1f << 0), (0x1 << 0));
-
- mod_phy_reg(pi, 0x1d, (0x1f << 0), (0x1 << 0));
- mod_phy_reg(pi, 0x33, (0x1f << 0), (0x1 << 0));
- }
-
- write_phy_reg(pi, 0x150, 0x809c);
-
- if (pi->nphy_gain_boost)
- if ((CHSPEC_IS2G(pi->radio_chanspec)) &&
- (CHSPEC_IS40(pi->radio_chanspec)))
- hpf_code = 4;
- else
- hpf_code = 5;
- else if (CHSPEC_IS40(pi->radio_chanspec))
- hpf_code = 6;
- else
- hpf_code = 7;
-
- mod_phy_reg(pi, 0x20, (0x1f << 7), (hpf_code << 7));
- mod_phy_reg(pi, 0x36, (0x1f << 7), (hpf_code << 7));
-
- for (ctr = 0; ctr < 4; ctr++) {
- regval[ctr] = (hpf_code << 8) | 0x7c;
- }
- wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);
-
- wlc_phy_adjust_lnagaintbl_nphy(pi);
-
- if (pi->nphy_elna_gain_config) {
- regval[0] = 0;
- regval[1] = 1;
- regval[2] = 1;
- regval[3] = 1;
- wlc_phy_table_write_nphy(pi, 2, 4, 8, 16, regval);
- wlc_phy_table_write_nphy(pi, 3, 4, 8, 16, regval);
-
- for (ctr = 0; ctr < 4; ctr++) {
- regval[ctr] = (hpf_code << 8) | 0x74;
- }
- wlc_phy_table_write_nphy(pi, 7, 4, 0x106, 16, regval);
- }
-
- if (NREV_IS(pi->pubpi.phy_rev, 2)) {
- for (ctr = 0; ctr < 21; ctr++) {
- regval[ctr] = 3 * ctr;
- }
- wlc_phy_table_write_nphy(pi, 0, 21, 32, 16, regval);
- wlc_phy_table_write_nphy(pi, 1, 21, 32, 16, regval);
-
- for (ctr = 0; ctr < 21; ctr++) {
- regval[ctr] = (u16) ctr;
- }
- wlc_phy_table_write_nphy(pi, 2, 21, 32, 16, regval);
- wlc_phy_table_write_nphy(pi, 3, 21, 32, 16, regval);
- }
-
- wlc_phy_set_rfseq_nphy(pi, NPHY_RFSEQ_UPDATEGAINU,
- rfseq_updategainu_events,
- rfseq_updategainu_dlys,
- sizeof(rfseq_updategainu_events) /
- sizeof(rfseq_updategainu_events[0]));
-
- mod_phy_reg(pi, 0x153, (0xff << 8), (90 << 8));
-
- if (CHSPEC_IS2G(pi->radio_chanspec))
- mod_phy_reg(pi,
- (NPHY_TO_BPHY_OFF + BPHY_OPTIONAL_MODES),
- 0x7f, 0x4);
- }
-}
-
-static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(phy_info_t *pi)
-{
- s8 lna1_gain_db[] = { 8, 13, 17, 22 };
- s8 lna2_gain_db[] = { -2, 7, 11, 15 };
- s8 tia_gain_db[] = { -4, -1, 2, 5, 5, 5, 5, 5, 5, 5 };
- s8 tia_gainbits[] = {
- 0x0, 0x01, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 };
-
- mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
- mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
-
- mod_phy_reg(pi, 0x289, (0xff << 0), (0x46 << 0));
-
- mod_phy_reg(pi, 0x283, (0xff << 0), (0x3c << 0));
- mod_phy_reg(pi, 0x280, (0xff << 0), (0x3c << 0));
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x8, 8,
- lna1_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x8, 8,
- lna1_gain_db);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10, 8,
- lna2_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10, 8,
- lna2_gain_db);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20, 8,
- tia_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20, 8,
- tia_gain_db);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20, 8,
- tia_gainbits);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20, 8,
- tia_gainbits);
-
- write_phy_reg(pi, 0x37, 0x74);
- write_phy_reg(pi, 0x2ad, 0x74);
- write_phy_reg(pi, 0x38, 0x18);
- write_phy_reg(pi, 0x2ae, 0x18);
-
- write_phy_reg(pi, 0x2b, 0xe8);
- write_phy_reg(pi, 0x41, 0xe8);
-
- if (CHSPEC_IS20(pi->radio_chanspec)) {
-
- mod_phy_reg(pi, 0x300, (0x3f << 0), (0x12 << 0));
- mod_phy_reg(pi, 0x301, (0x3f << 0), (0x12 << 0));
- } else {
-
- mod_phy_reg(pi, 0x300, (0x3f << 0), (0x10 << 0));
- mod_phy_reg(pi, 0x301, (0x3f << 0), (0x10 << 0));
- }
-}
-
-static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(phy_info_t *pi)
-{
- u16 currband;
- s8 lna1G_gain_db_rev7[] = { 9, 14, 19, 24 };
- s8 *lna1_gain_db = NULL;
- s8 *lna1_gain_db_2 = NULL;
- s8 *lna2_gain_db = NULL;
- s8 tiaA_gain_db_rev7[] = { -9, -6, -3, 0, 3, 3, 3, 3, 3, 3 };
- s8 *tia_gain_db;
- s8 tiaA_gainbits_rev7[] = { 0, 1, 2, 3, 4, 4, 4, 4, 4, 4 };
- s8 *tia_gainbits;
- u16 rfseqA_init_gain_rev7[] = { 0x624f, 0x624f };
- u16 *rfseq_init_gain;
- u16 init_gaincode;
- u16 clip1hi_gaincode;
- u16 clip1md_gaincode = 0;
- u16 clip1md_gaincode_B;
- u16 clip1lo_gaincode;
- u16 clip1lo_gaincode_B;
- u8 crsminl_th = 0;
- u8 crsminu_th;
- u16 nbclip_th = 0;
- u8 w1clip_th;
- u16 freq;
- s8 nvar_baseline_offset0 = 0, nvar_baseline_offset1 = 0;
- u8 chg_nbclip_th = 0;
-
- mod_phy_reg(pi, 0x1c, (0x1 << 13), (1 << 13));
- mod_phy_reg(pi, 0x32, (0x1 << 13), (1 << 13));
-
- currband = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
- if (currband == 0) {
-
- lna1_gain_db = lna1G_gain_db_rev7;
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8, 8,
- lna1_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8, 8,
- lna1_gain_db);
-
- mod_phy_reg(pi, 0x283, (0xff << 0), (0x40 << 0));
-
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- mod_phy_reg(pi, 0x280, (0xff << 0), (0x3e << 0));
- mod_phy_reg(pi, 0x283, (0xff << 0), (0x3e << 0));
- }
-
- mod_phy_reg(pi, 0x289, (0xff << 0), (0x46 << 0));
-
- if (CHSPEC_IS20(pi->radio_chanspec)) {
- mod_phy_reg(pi, 0x300, (0x3f << 0), (13 << 0));
- mod_phy_reg(pi, 0x301, (0x3f << 0), (13 << 0));
- }
- } else {
-
- init_gaincode = 0x9e;
- clip1hi_gaincode = 0x9e;
- clip1md_gaincode_B = 0x24;
- clip1lo_gaincode = 0x8a;
- clip1lo_gaincode_B = 8;
- rfseq_init_gain = rfseqA_init_gain_rev7;
-
- tia_gain_db = tiaA_gain_db_rev7;
- tia_gainbits = tiaA_gainbits_rev7;
-
- freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec));
- if (CHSPEC_IS20(pi->radio_chanspec)) {
-
- w1clip_th = 25;
- clip1md_gaincode = 0x82;
-
- if ((freq <= 5080) || (freq == 5825)) {
-
- s8 lna1A_gain_db_rev7[] = { 11, 16, 20, 24 };
- s8 lna1A_gain_db_2_rev7[] = {
- 11, 17, 22, 25 };
- s8 lna2A_gain_db_rev7[] = { -1, 6, 10, 14 };
-
- crsminu_th = 0x3e;
- lna1_gain_db = lna1A_gain_db_rev7;
- lna1_gain_db_2 = lna1A_gain_db_2_rev7;
- lna2_gain_db = lna2A_gain_db_rev7;
- } else if ((freq >= 5500) && (freq <= 5700)) {
-
- s8 lna1A_gain_db_rev7[] = { 11, 17, 21, 25 };
- s8 lna1A_gain_db_2_rev7[] = {
- 12, 18, 22, 26 };
- s8 lna2A_gain_db_rev7[] = { 1, 8, 12, 16 };
-
- crsminu_th = 0x45;
- clip1md_gaincode_B = 0x14;
- nbclip_th = 0xff;
- chg_nbclip_th = 1;
- lna1_gain_db = lna1A_gain_db_rev7;
- lna1_gain_db_2 = lna1A_gain_db_2_rev7;
- lna2_gain_db = lna2A_gain_db_rev7;
- } else {
-
- s8 lna1A_gain_db_rev7[] = { 12, 18, 22, 26 };
- s8 lna1A_gain_db_2_rev7[] = {
- 12, 18, 22, 26 };
- s8 lna2A_gain_db_rev7[] = { -1, 6, 10, 14 };
-
- crsminu_th = 0x41;
- lna1_gain_db = lna1A_gain_db_rev7;
- lna1_gain_db_2 = lna1A_gain_db_2_rev7;
- lna2_gain_db = lna2A_gain_db_rev7;
- }
-
- if (freq <= 4920) {
- nvar_baseline_offset0 = 5;
- nvar_baseline_offset1 = 5;
- } else if ((freq > 4920) && (freq <= 5320)) {
- nvar_baseline_offset0 = 3;
- nvar_baseline_offset1 = 5;
- } else if ((freq > 5320) && (freq <= 5700)) {
- nvar_baseline_offset0 = 3;
- nvar_baseline_offset1 = 2;
- } else {
- nvar_baseline_offset0 = 4;
- nvar_baseline_offset1 = 0;
- }
- } else {
-
- crsminu_th = 0x3a;
- crsminl_th = 0x3a;
- w1clip_th = 20;
-
- if ((freq >= 4920) && (freq <= 5320)) {
- nvar_baseline_offset0 = 4;
- nvar_baseline_offset1 = 5;
- } else if ((freq > 5320) && (freq <= 5550)) {
- nvar_baseline_offset0 = 4;
- nvar_baseline_offset1 = 2;
- } else {
- nvar_baseline_offset0 = 5;
- nvar_baseline_offset1 = 3;
- }
- }
-
- write_phy_reg(pi, 0x20, init_gaincode);
- write_phy_reg(pi, 0x2a7, init_gaincode);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- pi->pubpi.phy_corenum, 0x106, 16,
- rfseq_init_gain);
-
- write_phy_reg(pi, 0x22, clip1hi_gaincode);
- write_phy_reg(pi, 0x2a9, clip1hi_gaincode);
-
- write_phy_reg(pi, 0x36, clip1md_gaincode_B);
- write_phy_reg(pi, 0x2ac, clip1md_gaincode_B);
-
- write_phy_reg(pi, 0x37, clip1lo_gaincode);
- write_phy_reg(pi, 0x2ad, clip1lo_gaincode);
- write_phy_reg(pi, 0x38, clip1lo_gaincode_B);
- write_phy_reg(pi, 0x2ae, clip1lo_gaincode_B);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 10, 0x20, 8,
- tia_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 10, 0x20, 8,
- tia_gain_db);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS1, 10, 0x20, 8,
- tia_gainbits);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAINBITS2, 10, 0x20, 8,
- tia_gainbits);
-
- mod_phy_reg(pi, 0x283, (0xff << 0), (crsminu_th << 0));
-
- if (chg_nbclip_th == 1) {
- write_phy_reg(pi, 0x2b, nbclip_th);
- write_phy_reg(pi, 0x41, nbclip_th);
- }
-
- mod_phy_reg(pi, 0x300, (0x3f << 0), (w1clip_th << 0));
- mod_phy_reg(pi, 0x301, (0x3f << 0), (w1clip_th << 0));
-
- mod_phy_reg(pi, 0x2e4,
- (0x3f << 0), (nvar_baseline_offset0 << 0));
-
- mod_phy_reg(pi, 0x2e4,
- (0x3f << 6), (nvar_baseline_offset1 << 6));
-
- if (CHSPEC_IS20(pi->radio_chanspec)) {
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 8, 8,
- lna1_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 8, 8,
- lna1_gain_db_2);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN1, 4, 0x10,
- 8, lna2_gain_db);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_GAIN2, 4, 0x10,
- 8, lna2_gain_db);
-
- write_phy_reg(pi, 0x24, clip1md_gaincode);
- write_phy_reg(pi, 0x2ab, clip1md_gaincode);
- } else {
- mod_phy_reg(pi, 0x280, (0xff << 0), (crsminl_th << 0));
- }
-
- }
-
-}
-
-static void wlc_phy_adjust_lnagaintbl_nphy(phy_info_t *pi)
-{
- uint core;
- int ctr;
- s16 gain_delta[2];
- u8 curr_channel;
- u16 minmax_gain[2];
- u16 regval[4];
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- if (pi->nphy_gain_boost) {
- if ((CHSPEC_IS2G(pi->radio_chanspec))) {
-
- gain_delta[0] = 6;
- gain_delta[1] = 6;
- } else {
-
- curr_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
- gain_delta[0] =
- (s16)
- PHY_HW_ROUND(((nphy_lnagain_est0[0] *
- curr_channel) +
- nphy_lnagain_est0[1]), 13);
- gain_delta[1] =
- (s16)
- PHY_HW_ROUND(((nphy_lnagain_est1[0] *
- curr_channel) +
- nphy_lnagain_est1[1]), 13);
- }
- } else {
-
- gain_delta[0] = 0;
- gain_delta[1] = 0;
- }
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- if (pi->nphy_elna_gain_config) {
-
- regval[0] = nphy_def_lnagains[2] + gain_delta[core];
- regval[1] = nphy_def_lnagains[3] + gain_delta[core];
- regval[2] = nphy_def_lnagains[3] + gain_delta[core];
- regval[3] = nphy_def_lnagains[3] + gain_delta[core];
- } else {
- for (ctr = 0; ctr < 4; ctr++) {
- regval[ctr] =
- nphy_def_lnagains[ctr] + gain_delta[core];
- }
- }
- wlc_phy_table_write_nphy(pi, core, 4, 8, 16, regval);
-
- minmax_gain[core] =
- (u16) (nphy_def_lnagains[2] + gain_delta[core] + 4);
- }
-
- mod_phy_reg(pi, 0x1e, (0xff << 0), (minmax_gain[0] << 0));
- mod_phy_reg(pi, 0x34, (0xff << 0), (minmax_gain[1] << 0));
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-void wlc_phy_switch_radio_nphy(phy_info_t *pi, bool on)
-{
- if (on) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (!pi->radio_is_on) {
- wlc_phy_radio_preinit_205x(pi);
- wlc_phy_radio_init_2057(pi);
- wlc_phy_radio_postinit_2057(pi);
- }
-
- wlc_phy_chanspec_set((wlc_phy_t *) pi,
- pi->radio_chanspec);
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- wlc_phy_radio_preinit_205x(pi);
- wlc_phy_radio_init_2056(pi);
- wlc_phy_radio_postinit_2056(pi);
-
- wlc_phy_chanspec_set((wlc_phy_t *) pi,
- pi->radio_chanspec);
- } else {
- wlc_phy_radio_preinit_2055(pi);
- wlc_phy_radio_init_2055(pi);
- wlc_phy_radio_postinit_2055(pi);
- }
-
- pi->radio_is_on = true;
-
- } else {
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)
- && NREV_LT(pi->pubpi.phy_rev, 7)) {
- and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
- mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x0);
-
- write_radio_reg(pi,
- RADIO_2056_TX_PADA_BOOST_TUNE |
- RADIO_2056_TX0, 0);
- write_radio_reg(pi,
- RADIO_2056_TX_PADG_BOOST_TUNE |
- RADIO_2056_TX0, 0);
- write_radio_reg(pi,
- RADIO_2056_TX_PGAA_BOOST_TUNE |
- RADIO_2056_TX0, 0);
- write_radio_reg(pi,
- RADIO_2056_TX_PGAG_BOOST_TUNE |
- RADIO_2056_TX0, 0);
- mod_radio_reg(pi,
- RADIO_2056_TX_MIXA_BOOST_TUNE |
- RADIO_2056_TX0, 0xf0, 0);
- write_radio_reg(pi,
- RADIO_2056_TX_MIXG_BOOST_TUNE |
- RADIO_2056_TX0, 0);
-
- write_radio_reg(pi,
- RADIO_2056_TX_PADA_BOOST_TUNE |
- RADIO_2056_TX1, 0);
- write_radio_reg(pi,
- RADIO_2056_TX_PADG_BOOST_TUNE |
- RADIO_2056_TX1, 0);
- write_radio_reg(pi,
- RADIO_2056_TX_PGAA_BOOST_TUNE |
- RADIO_2056_TX1, 0);
- write_radio_reg(pi,
- RADIO_2056_TX_PGAG_BOOST_TUNE |
- RADIO_2056_TX1, 0);
- mod_radio_reg(pi,
- RADIO_2056_TX_MIXA_BOOST_TUNE |
- RADIO_2056_TX1, 0xf0, 0);
- write_radio_reg(pi,
- RADIO_2056_TX_MIXG_BOOST_TUNE |
- RADIO_2056_TX1, 0);
-
- pi->radio_is_on = false;
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 8)) {
- and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
- pi->radio_is_on = false;
- }
-
- }
-}
-
-static void wlc_phy_radio_preinit_2055(phy_info_t *pi)
-{
-
- and_phy_reg(pi, 0x78, ~RFCC_POR_FORCE);
- or_phy_reg(pi, 0x78, RFCC_CHIP0_PU | RFCC_OE_POR_FORCE);
-
- or_phy_reg(pi, 0x78, RFCC_POR_FORCE);
-}
-
-static void wlc_phy_radio_init_2055(phy_info_t *pi)
-{
- wlc_phy_init_radio_regs(pi, regs_2055, RADIO_DEFAULT_CORE);
-}
-
-static void wlc_phy_radio_postinit_2055(phy_info_t *pi)
-{
-
- and_radio_reg(pi, RADIO_2055_MASTER_CNTRL1,
- ~(RADIO_2055_JTAGCTRL_MASK | RADIO_2055_JTAGSYNC_MASK));
-
- if (((pi->sh->sromrev >= 4)
- && !(pi->sh->boardflags2 & BFL2_RXBB_INT_REG_DIS))
- || ((pi->sh->sromrev < 4))) {
- and_radio_reg(pi, RADIO_2055_CORE1_RXBB_REGULATOR, 0x7F);
- and_radio_reg(pi, RADIO_2055_CORE2_RXBB_REGULATOR, 0x7F);
- }
-
- mod_radio_reg(pi, RADIO_2055_RRCCAL_N_OPT_SEL, 0x3F, 0x2C);
- write_radio_reg(pi, RADIO_2055_CAL_MISC, 0x3C);
-
- and_radio_reg(pi, RADIO_2055_CAL_MISC,
- ~(RADIO_2055_RRCAL_START | RADIO_2055_RRCAL_RST_N));
-
- or_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL, RADIO_2055_CAL_LPO_ENABLE);
-
- or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_RST_N);
-
- udelay(1000);
-
- or_radio_reg(pi, RADIO_2055_CAL_MISC, RADIO_2055_RRCAL_START);
-
- SPINWAIT(((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
- RADIO_2055_RCAL_DONE) != RADIO_2055_RCAL_DONE), 2000);
-
- if (WARN((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
- RADIO_2055_RCAL_DONE) != RADIO_2055_RCAL_DONE,
- "HW error: radio calibration1\n"))
- return;
-
- and_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL,
- ~(RADIO_2055_CAL_LPO_ENABLE));
-
- wlc_phy_chanspec_set((wlc_phy_t *) pi, pi->radio_chanspec);
-
- write_radio_reg(pi, RADIO_2055_CORE1_RXBB_LPF, 9);
- write_radio_reg(pi, RADIO_2055_CORE2_RXBB_LPF, 9);
-
- write_radio_reg(pi, RADIO_2055_CORE1_RXBB_MIDAC_HIPAS, 0x83);
- write_radio_reg(pi, RADIO_2055_CORE2_RXBB_MIDAC_HIPAS, 0x83);
-
- mod_radio_reg(pi, RADIO_2055_CORE1_LNA_GAINBST,
- RADIO_2055_GAINBST_VAL_MASK, RADIO_2055_GAINBST_CODE);
- mod_radio_reg(pi, RADIO_2055_CORE2_LNA_GAINBST,
- RADIO_2055_GAINBST_VAL_MASK, RADIO_2055_GAINBST_CODE);
- if (pi->nphy_gain_boost) {
- and_radio_reg(pi, RADIO_2055_CORE1_RXRF_SPC1,
- ~(RADIO_2055_GAINBST_DISABLE));
- and_radio_reg(pi, RADIO_2055_CORE2_RXRF_SPC1,
- ~(RADIO_2055_GAINBST_DISABLE));
- } else {
- or_radio_reg(pi, RADIO_2055_CORE1_RXRF_SPC1,
- RADIO_2055_GAINBST_DISABLE);
- or_radio_reg(pi, RADIO_2055_CORE2_RXRF_SPC1,
- RADIO_2055_GAINBST_DISABLE);
- }
-
- udelay(2);
-}
-
-static void wlc_phy_radio_preinit_205x(phy_info_t *pi)
-{
-
- and_phy_reg(pi, 0x78, ~RFCC_CHIP0_PU);
- and_phy_reg(pi, 0x78, RFCC_OE_POR_FORCE);
-
- or_phy_reg(pi, 0x78, ~RFCC_OE_POR_FORCE);
- or_phy_reg(pi, 0x78, RFCC_CHIP0_PU);
-
-}
-
-static void wlc_phy_radio_init_2056(phy_info_t *pi)
-{
- radio_regs_t *regs_SYN_2056_ptr = NULL;
- radio_regs_t *regs_TX_2056_ptr = NULL;
- radio_regs_t *regs_RX_2056_ptr = NULL;
-
- if (NREV_IS(pi->pubpi.phy_rev, 3)) {
- regs_SYN_2056_ptr = regs_SYN_2056;
- regs_TX_2056_ptr = regs_TX_2056;
- regs_RX_2056_ptr = regs_RX_2056;
- } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
- regs_SYN_2056_ptr = regs_SYN_2056_A1;
- regs_TX_2056_ptr = regs_TX_2056_A1;
- regs_RX_2056_ptr = regs_RX_2056_A1;
- } else {
- switch (pi->pubpi.radiorev) {
- case 5:
- regs_SYN_2056_ptr = regs_SYN_2056_rev5;
- regs_TX_2056_ptr = regs_TX_2056_rev5;
- regs_RX_2056_ptr = regs_RX_2056_rev5;
- break;
-
- case 6:
- regs_SYN_2056_ptr = regs_SYN_2056_rev6;
- regs_TX_2056_ptr = regs_TX_2056_rev6;
- regs_RX_2056_ptr = regs_RX_2056_rev6;
- break;
-
- case 7:
- case 9:
- regs_SYN_2056_ptr = regs_SYN_2056_rev7;
- regs_TX_2056_ptr = regs_TX_2056_rev7;
- regs_RX_2056_ptr = regs_RX_2056_rev7;
- break;
-
- case 8:
- regs_SYN_2056_ptr = regs_SYN_2056_rev8;
- regs_TX_2056_ptr = regs_TX_2056_rev8;
- regs_RX_2056_ptr = regs_RX_2056_rev8;
- break;
-
- case 11:
- regs_SYN_2056_ptr = regs_SYN_2056_rev11;
- regs_TX_2056_ptr = regs_TX_2056_rev11;
- regs_RX_2056_ptr = regs_RX_2056_rev11;
- break;
-
- default:
- break;
- }
- }
-
- wlc_phy_init_radio_regs(pi, regs_SYN_2056_ptr, (u16) RADIO_2056_SYN);
-
- wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX0);
-
- wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, (u16) RADIO_2056_TX1);
-
- wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX0);
-
- wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, (u16) RADIO_2056_RX1);
-}
-
-static void wlc_phy_radio_postinit_2056(phy_info_t *pi)
-{
- mod_radio_reg(pi, RADIO_2056_SYN_COM_CTRL, 0xb, 0xb);
-
- mod_radio_reg(pi, RADIO_2056_SYN_COM_PU, 0x2, 0x2);
- mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x2);
- udelay(1000);
- mod_radio_reg(pi, RADIO_2056_SYN_COM_RESET, 0x2, 0x0);
-
- if ((pi->sh->boardflags2 & BFL2_LEGACY)
- || (pi->sh->boardflags2 & BFL2_XTALBUFOUTEN)) {
-
- mod_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2, 0xf4, 0x0);
- } else {
-
- mod_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2, 0xfc, 0x0);
- }
-
- mod_radio_reg(pi, RADIO_2056_SYN_RCCAL_CTRL0, 0x1, 0x0);
-
- if (pi->phy_init_por) {
- wlc_phy_radio205x_rcal(pi);
- }
-}
-
-static void wlc_phy_radio_init_2057(phy_info_t *pi)
-{
- radio_20xx_regs_t *regs_2057_ptr = NULL;
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)) {
-
- regs_2057_ptr = regs_2057_rev4;
- } else if (NREV_IS(pi->pubpi.phy_rev, 8)
- || NREV_IS(pi->pubpi.phy_rev, 9)) {
- switch (pi->pubpi.radiorev) {
- case 5:
-
- if (pi->pubpi.radiover == 0x0) {
-
- regs_2057_ptr = regs_2057_rev5;
-
- } else if (pi->pubpi.radiover == 0x1) {
-
- regs_2057_ptr = regs_2057_rev5v1;
- } else {
- break;
- }
-
- case 7:
-
- regs_2057_ptr = regs_2057_rev7;
- break;
-
- case 8:
-
- regs_2057_ptr = regs_2057_rev8;
- break;
-
- default:
- break;
- }
- }
-
- wlc_phy_init_radio_regs_allbands(pi, regs_2057_ptr);
-}
-
-static void wlc_phy_radio_postinit_2057(phy_info_t *pi)
-{
-
- mod_radio_reg(pi, RADIO_2057_XTALPUOVR_PINCTRL, 0x1, 0x1);
-
- if (pi->sh->chip == !BCM6362_CHIP_ID) {
-
- mod_radio_reg(pi, RADIO_2057_XTALPUOVR_PINCTRL, 0x2, 0x2);
- }
-
- mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x78);
- mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x80);
- mdelay(2);
- mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x78, 0x0);
- mod_radio_reg(pi, RADIO_2057_XTAL_CONFIG2, 0x80, 0x0);
-
- if (pi->phy_init_por) {
- wlc_phy_radio205x_rcal(pi);
- wlc_phy_radio2057_rccal(pi);
- }
-
- mod_radio_reg(pi, RADIO_2057_RFPLL_MASTER, 0x8, 0x0);
-}
-
-static bool
-wlc_phy_chan2freq_nphy(phy_info_t *pi, uint channel, int *f,
- chan_info_nphy_radio2057_t **t0,
- chan_info_nphy_radio205x_t **t1,
- chan_info_nphy_radio2057_rev5_t **t2,
- chan_info_nphy_2055_t **t3)
-{
- uint i;
- chan_info_nphy_radio2057_t *chan_info_tbl_p_0 = NULL;
- chan_info_nphy_radio205x_t *chan_info_tbl_p_1 = NULL;
- chan_info_nphy_radio2057_rev5_t *chan_info_tbl_p_2 = NULL;
- u32 tbl_len = 0;
-
- int freq = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)) {
-
- chan_info_tbl_p_0 = chan_info_nphyrev7_2057_rev4;
- tbl_len = ARRAY_SIZE(chan_info_nphyrev7_2057_rev4);
-
- } else if (NREV_IS(pi->pubpi.phy_rev, 8)
- || NREV_IS(pi->pubpi.phy_rev, 9)) {
- switch (pi->pubpi.radiorev) {
-
- case 5:
-
- if (pi->pubpi.radiover == 0x0) {
-
- chan_info_tbl_p_2 =
- chan_info_nphyrev8_2057_rev5;
- tbl_len =
- ARRAY_SIZE
- (chan_info_nphyrev8_2057_rev5);
-
- } else if (pi->pubpi.radiover == 0x1) {
-
- chan_info_tbl_p_2 =
- chan_info_nphyrev9_2057_rev5v1;
- tbl_len =
- ARRAY_SIZE
- (chan_info_nphyrev9_2057_rev5v1);
-
- }
- break;
-
- case 7:
- chan_info_tbl_p_0 =
- chan_info_nphyrev8_2057_rev7;
- tbl_len =
- ARRAY_SIZE(chan_info_nphyrev8_2057_rev7);
- break;
-
- case 8:
- chan_info_tbl_p_0 =
- chan_info_nphyrev8_2057_rev8;
- tbl_len =
- ARRAY_SIZE(chan_info_nphyrev8_2057_rev8);
- break;
-
- default:
- if (NORADIO_ENAB(pi->pubpi)) {
- goto fail;
- }
- break;
- }
- } else if (NREV_IS(pi->pubpi.phy_rev, 16)) {
-
- chan_info_tbl_p_0 = chan_info_nphyrev8_2057_rev8;
- tbl_len = ARRAY_SIZE(chan_info_nphyrev8_2057_rev8);
- } else {
- goto fail;
- }
-
- for (i = 0; i < tbl_len; i++) {
- if (pi->pubpi.radiorev == 5) {
-
- if (chan_info_tbl_p_2[i].chan == channel)
- break;
- } else {
-
- if (chan_info_tbl_p_0[i].chan == channel)
- break;
- }
- }
-
- if (i >= tbl_len) {
- goto fail;
- }
- if (pi->pubpi.radiorev == 5) {
- *t2 = &chan_info_tbl_p_2[i];
- freq = chan_info_tbl_p_2[i].freq;
- } else {
- *t0 = &chan_info_tbl_p_0[i];
- freq = chan_info_tbl_p_0[i].freq;
- }
-
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (NREV_IS(pi->pubpi.phy_rev, 3)) {
- chan_info_tbl_p_1 = chan_info_nphyrev3_2056;
- tbl_len = ARRAY_SIZE(chan_info_nphyrev3_2056);
- } else if (NREV_IS(pi->pubpi.phy_rev, 4)) {
- chan_info_tbl_p_1 = chan_info_nphyrev4_2056_A1;
- tbl_len = ARRAY_SIZE(chan_info_nphyrev4_2056_A1);
- } else if (NREV_IS(pi->pubpi.phy_rev, 5)
- || NREV_IS(pi->pubpi.phy_rev, 6)) {
- switch (pi->pubpi.radiorev) {
- case 5:
- chan_info_tbl_p_1 = chan_info_nphyrev5_2056v5;
- tbl_len = ARRAY_SIZE(chan_info_nphyrev5_2056v5);
- break;
- case 6:
- chan_info_tbl_p_1 = chan_info_nphyrev6_2056v6;
- tbl_len = ARRAY_SIZE(chan_info_nphyrev6_2056v6);
- break;
- case 7:
- case 9:
- chan_info_tbl_p_1 = chan_info_nphyrev5n6_2056v7;
- tbl_len =
- ARRAY_SIZE(chan_info_nphyrev5n6_2056v7);
- break;
- case 8:
- chan_info_tbl_p_1 = chan_info_nphyrev6_2056v8;
- tbl_len = ARRAY_SIZE(chan_info_nphyrev6_2056v8);
- break;
- case 11:
- chan_info_tbl_p_1 = chan_info_nphyrev6_2056v11;
- tbl_len = ARRAY_SIZE(chan_info_nphyrev6_2056v11);
- break;
- default:
- if (NORADIO_ENAB(pi->pubpi)) {
- goto fail;
- }
- break;
- }
- }
-
- for (i = 0; i < tbl_len; i++) {
- if (chan_info_tbl_p_1[i].chan == channel)
- break;
- }
-
- if (i >= tbl_len) {
- goto fail;
- }
- *t1 = &chan_info_tbl_p_1[i];
- freq = chan_info_tbl_p_1[i].freq;
-
- } else {
- for (i = 0; i < ARRAY_SIZE(chan_info_nphy_2055); i++)
- if (chan_info_nphy_2055[i].chan == channel)
- break;
-
- if (i >= ARRAY_SIZE(chan_info_nphy_2055)) {
- goto fail;
- }
- *t3 = &chan_info_nphy_2055[i];
- freq = chan_info_nphy_2055[i].freq;
- }
-
- *f = freq;
- return true;
-
- fail:
- *f = WL_CHAN_FREQ_RANGE_2G;
- return false;
-}
-
-u8 wlc_phy_get_chan_freq_range_nphy(phy_info_t *pi, uint channel)
-{
- int freq;
- chan_info_nphy_radio2057_t *t0 = NULL;
- chan_info_nphy_radio205x_t *t1 = NULL;
- chan_info_nphy_radio2057_rev5_t *t2 = NULL;
- chan_info_nphy_2055_t *t3 = NULL;
-
- if (NORADIO_ENAB(pi->pubpi))
- return WL_CHAN_FREQ_RANGE_2G;
-
- if (channel == 0)
- channel = CHSPEC_CHANNEL(pi->radio_chanspec);
-
- wlc_phy_chan2freq_nphy(pi, channel, &freq, &t0, &t1, &t2, &t3);
-
- if (CHSPEC_IS2G(pi->radio_chanspec))
- return WL_CHAN_FREQ_RANGE_2G;
-
- if ((freq >= BASE_LOW_5G_CHAN) && (freq < BASE_MID_5G_CHAN)) {
- return WL_CHAN_FREQ_RANGE_5GL;
- } else if ((freq >= BASE_MID_5G_CHAN) && (freq < BASE_HIGH_5G_CHAN)) {
- return WL_CHAN_FREQ_RANGE_5GM;
- } else {
- return WL_CHAN_FREQ_RANGE_5GH;
- }
-}
-
-static void
-wlc_phy_chanspec_radio2055_setup(phy_info_t *pi, chan_info_nphy_2055_t *ci)
-{
-
- write_radio_reg(pi, RADIO_2055_PLL_REF, ci->RF_pll_ref);
- write_radio_reg(pi, RADIO_2055_RF_PLL_MOD0, ci->RF_rf_pll_mod0);
- write_radio_reg(pi, RADIO_2055_RF_PLL_MOD1, ci->RF_rf_pll_mod1);
- write_radio_reg(pi, RADIO_2055_VCO_CAP_TAIL, ci->RF_vco_cap_tail);
-
- WLC_PHY_WAR_PR51571(pi);
-
- write_radio_reg(pi, RADIO_2055_VCO_CAL1, ci->RF_vco_cal1);
- write_radio_reg(pi, RADIO_2055_VCO_CAL2, ci->RF_vco_cal2);
- write_radio_reg(pi, RADIO_2055_PLL_LF_C1, ci->RF_pll_lf_c1);
- write_radio_reg(pi, RADIO_2055_PLL_LF_R1, ci->RF_pll_lf_r1);
-
- WLC_PHY_WAR_PR51571(pi);
-
- write_radio_reg(pi, RADIO_2055_PLL_LF_C2, ci->RF_pll_lf_c2);
- write_radio_reg(pi, RADIO_2055_LGBUF_CEN_BUF, ci->RF_lgbuf_cen_buf);
- write_radio_reg(pi, RADIO_2055_LGEN_TUNE1, ci->RF_lgen_tune1);
- write_radio_reg(pi, RADIO_2055_LGEN_TUNE2, ci->RF_lgen_tune2);
-
- WLC_PHY_WAR_PR51571(pi);
-
- write_radio_reg(pi, RADIO_2055_CORE1_LGBUF_A_TUNE,
- ci->RF_core1_lgbuf_a_tune);
- write_radio_reg(pi, RADIO_2055_CORE1_LGBUF_G_TUNE,
- ci->RF_core1_lgbuf_g_tune);
- write_radio_reg(pi, RADIO_2055_CORE1_RXRF_REG1, ci->RF_core1_rxrf_reg1);
- write_radio_reg(pi, RADIO_2055_CORE1_TX_PGA_PAD_TN,
- ci->RF_core1_tx_pga_pad_tn);
-
- WLC_PHY_WAR_PR51571(pi);
-
- write_radio_reg(pi, RADIO_2055_CORE1_TX_MX_BGTRIM,
- ci->RF_core1_tx_mx_bgtrim);
- write_radio_reg(pi, RADIO_2055_CORE2_LGBUF_A_TUNE,
- ci->RF_core2_lgbuf_a_tune);
- write_radio_reg(pi, RADIO_2055_CORE2_LGBUF_G_TUNE,
- ci->RF_core2_lgbuf_g_tune);
- write_radio_reg(pi, RADIO_2055_CORE2_RXRF_REG1, ci->RF_core2_rxrf_reg1);
-
- WLC_PHY_WAR_PR51571(pi);
-
- write_radio_reg(pi, RADIO_2055_CORE2_TX_PGA_PAD_TN,
- ci->RF_core2_tx_pga_pad_tn);
- write_radio_reg(pi, RADIO_2055_CORE2_TX_MX_BGTRIM,
- ci->RF_core2_tx_mx_bgtrim);
-
- udelay(50);
-
- write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x05);
- write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x45);
-
- WLC_PHY_WAR_PR51571(pi);
-
- write_radio_reg(pi, RADIO_2055_VCO_CAL10, 0x65);
-
- udelay(300);
-}
-
-static void
-wlc_phy_chanspec_radio2056_setup(phy_info_t *pi,
- const chan_info_nphy_radio205x_t *ci)
-{
- radio_regs_t *regs_SYN_2056_ptr = NULL;
-
- write_radio_reg(pi,
- RADIO_2056_SYN_PLL_VCOCAL1 | RADIO_2056_SYN,
- ci->RF_SYN_pll_vcocal1);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_VCOCAL2 | RADIO_2056_SYN,
- ci->RF_SYN_pll_vcocal2);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_REFDIV | RADIO_2056_SYN,
- ci->RF_SYN_pll_refdiv);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_MMD2 | RADIO_2056_SYN,
- ci->RF_SYN_pll_mmd2);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_MMD1 | RADIO_2056_SYN,
- ci->RF_SYN_pll_mmd1);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 | RADIO_2056_SYN,
- ci->RF_SYN_pll_loopfilter1);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 | RADIO_2056_SYN,
- ci->RF_SYN_pll_loopfilter2);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER3 | RADIO_2056_SYN,
- ci->RF_SYN_pll_loopfilter3);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER4 | RADIO_2056_SYN,
- ci->RF_SYN_pll_loopfilter4);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER5 | RADIO_2056_SYN,
- ci->RF_SYN_pll_loopfilter5);
- write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR27 | RADIO_2056_SYN,
- ci->RF_SYN_reserved_addr27);
- write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR28 | RADIO_2056_SYN,
- ci->RF_SYN_reserved_addr28);
- write_radio_reg(pi, RADIO_2056_SYN_RESERVED_ADDR29 | RADIO_2056_SYN,
- ci->RF_SYN_reserved_addr29);
- write_radio_reg(pi, RADIO_2056_SYN_LOGEN_VCOBUF1 | RADIO_2056_SYN,
- ci->RF_SYN_logen_VCOBUF1);
- write_radio_reg(pi, RADIO_2056_SYN_LOGEN_MIXER2 | RADIO_2056_SYN,
- ci->RF_SYN_logen_MIXER2);
- write_radio_reg(pi, RADIO_2056_SYN_LOGEN_BUF3 | RADIO_2056_SYN,
- ci->RF_SYN_logen_BUF3);
- write_radio_reg(pi, RADIO_2056_SYN_LOGEN_BUF4 | RADIO_2056_SYN,
- ci->RF_SYN_logen_BUF4);
-
- write_radio_reg(pi,
- RADIO_2056_RX_LNAA_TUNE | RADIO_2056_RX0,
- ci->RF_RX0_lnaa_tune);
- write_radio_reg(pi, RADIO_2056_RX_LNAG_TUNE | RADIO_2056_RX0,
- ci->RF_RX0_lnag_tune);
- write_radio_reg(pi, RADIO_2056_TX_INTPAA_BOOST_TUNE | RADIO_2056_TX0,
- ci->RF_TX0_intpaa_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_INTPAG_BOOST_TUNE | RADIO_2056_TX0,
- ci->RF_TX0_intpag_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_PADA_BOOST_TUNE | RADIO_2056_TX0,
- ci->RF_TX0_pada_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_PADG_BOOST_TUNE | RADIO_2056_TX0,
- ci->RF_TX0_padg_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_PGAA_BOOST_TUNE | RADIO_2056_TX0,
- ci->RF_TX0_pgaa_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_PGAG_BOOST_TUNE | RADIO_2056_TX0,
- ci->RF_TX0_pgag_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_MIXA_BOOST_TUNE | RADIO_2056_TX0,
- ci->RF_TX0_mixa_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_MIXG_BOOST_TUNE | RADIO_2056_TX0,
- ci->RF_TX0_mixg_boost_tune);
-
- write_radio_reg(pi,
- RADIO_2056_RX_LNAA_TUNE | RADIO_2056_RX1,
- ci->RF_RX1_lnaa_tune);
- write_radio_reg(pi, RADIO_2056_RX_LNAG_TUNE | RADIO_2056_RX1,
- ci->RF_RX1_lnag_tune);
- write_radio_reg(pi, RADIO_2056_TX_INTPAA_BOOST_TUNE | RADIO_2056_TX1,
- ci->RF_TX1_intpaa_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_INTPAG_BOOST_TUNE | RADIO_2056_TX1,
- ci->RF_TX1_intpag_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_PADA_BOOST_TUNE | RADIO_2056_TX1,
- ci->RF_TX1_pada_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_PADG_BOOST_TUNE | RADIO_2056_TX1,
- ci->RF_TX1_padg_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_PGAA_BOOST_TUNE | RADIO_2056_TX1,
- ci->RF_TX1_pgaa_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_PGAG_BOOST_TUNE | RADIO_2056_TX1,
- ci->RF_TX1_pgag_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_MIXA_BOOST_TUNE | RADIO_2056_TX1,
- ci->RF_TX1_mixa_boost_tune);
- write_radio_reg(pi, RADIO_2056_TX_MIXG_BOOST_TUNE | RADIO_2056_TX1,
- ci->RF_TX1_mixg_boost_tune);
-
- if (NREV_IS(pi->pubpi.phy_rev, 3))
- regs_SYN_2056_ptr = regs_SYN_2056;
- else if (NREV_IS(pi->pubpi.phy_rev, 4))
- regs_SYN_2056_ptr = regs_SYN_2056_A1;
- else {
- switch (pi->pubpi.radiorev) {
- case 5:
- regs_SYN_2056_ptr = regs_SYN_2056_rev5;
- break;
- case 6:
- regs_SYN_2056_ptr = regs_SYN_2056_rev6;
- break;
- case 7:
- case 9:
- regs_SYN_2056_ptr = regs_SYN_2056_rev7;
- break;
- case 8:
- regs_SYN_2056_ptr = regs_SYN_2056_rev8;
- break;
- case 11:
- regs_SYN_2056_ptr = regs_SYN_2056_rev11;
- break;
- }
- }
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
- RADIO_2056_SYN,
- (u16) regs_SYN_2056_ptr[0x49 - 2].init_g);
- } else {
- write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
- RADIO_2056_SYN,
- (u16) regs_SYN_2056_ptr[0x49 - 2].init_a);
- }
-
- if (pi->sh->boardflags2 & BFL2_GPLL_WAR) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 |
- RADIO_2056_SYN, 0x1f);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
- RADIO_2056_SYN, 0x1f);
-
- if ((pi->sh->chip == BCM4716_CHIP_ID) ||
- (pi->sh->chip == BCM47162_CHIP_ID)) {
-
- write_radio_reg(pi,
- RADIO_2056_SYN_PLL_LOOPFILTER4 |
- RADIO_2056_SYN, 0x14);
- write_radio_reg(pi,
- RADIO_2056_SYN_PLL_CP2 |
- RADIO_2056_SYN, 0x00);
- } else {
- write_radio_reg(pi,
- RADIO_2056_SYN_PLL_LOOPFILTER4 |
- RADIO_2056_SYN, 0xb);
- write_radio_reg(pi,
- RADIO_2056_SYN_PLL_CP2 |
- RADIO_2056_SYN, 0x14);
- }
- }
- }
-
- if ((pi->sh->boardflags2 & BFL2_GPLL_WAR2) &&
- (CHSPEC_IS2G(pi->radio_chanspec))) {
- write_radio_reg(pi,
- RADIO_2056_SYN_PLL_LOOPFILTER1 | RADIO_2056_SYN,
- 0x1f);
- write_radio_reg(pi,
- RADIO_2056_SYN_PLL_LOOPFILTER2 | RADIO_2056_SYN,
- 0x1f);
- write_radio_reg(pi,
- RADIO_2056_SYN_PLL_LOOPFILTER4 | RADIO_2056_SYN,
- 0xb);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 | RADIO_2056_SYN,
- 0x20);
- }
-
- if (pi->sh->boardflags2 & BFL2_APLL_WAR) {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER1 |
- RADIO_2056_SYN, 0x1f);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
- RADIO_2056_SYN, 0x1f);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER4 |
- RADIO_2056_SYN, 0x5);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_CP2 |
- RADIO_2056_SYN, 0xc);
- }
- }
-
- if (PHY_IPA(pi) && CHSPEC_IS2G(pi->radio_chanspec)) {
- u16 pag_boost_tune;
- u16 padg_boost_tune;
- u16 pgag_boost_tune;
- u16 mixg_boost_tune;
- u16 bias, cascbias;
- uint core;
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
-
- if (NREV_GE(pi->pubpi.phy_rev, 5)) {
-
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- PADG_IDAC, 0xcc);
-
- if ((pi->sh->chip == BCM4716_CHIP_ID) ||
- (pi->sh->chip ==
- BCM47162_CHIP_ID)) {
- bias = 0x40;
- cascbias = 0x45;
- pag_boost_tune = 0x5;
- pgag_boost_tune = 0x33;
- padg_boost_tune = 0x77;
- mixg_boost_tune = 0x55;
- } else {
- bias = 0x25;
- cascbias = 0x20;
-
- if ((pi->sh->chip ==
- BCM43224_CHIP_ID)
- || (pi->sh->chip ==
- BCM43225_CHIP_ID)
- || (pi->sh->chip ==
- BCM43421_CHIP_ID)) {
- if (pi->sh->chippkg ==
- BCM43224_FAB_SMIC) {
- bias = 0x2a;
- cascbias = 0x38;
- }
- }
-
- pag_boost_tune = 0x4;
- pgag_boost_tune = 0x03;
- padg_boost_tune = 0x77;
- mixg_boost_tune = 0x65;
- }
-
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_IMAIN_STAT, bias);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_IAUX_STAT, bias);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_CASCBIAS, cascbias);
-
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_BOOST_TUNE,
- pag_boost_tune);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- PGAG_BOOST_TUNE,
- pgag_boost_tune);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- PADG_BOOST_TUNE,
- padg_boost_tune);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- MIXG_BOOST_TUNE,
- mixg_boost_tune);
- } else {
-
- bias = IS40MHZ(pi) ? 0x40 : 0x20;
-
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_IMAIN_STAT, bias);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_IAUX_STAT, bias);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_CASCBIAS, 0x30);
- }
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, PA_SPARE1,
- 0xee);
- }
- }
-
- if (PHY_IPA(pi) && NREV_IS(pi->pubpi.phy_rev, 6)
- && CHSPEC_IS5G(pi->radio_chanspec)) {
- u16 paa_boost_tune;
- u16 pada_boost_tune;
- u16 pgaa_boost_tune;
- u16 mixa_boost_tune;
- u16 freq, pabias, cascbias;
- uint core;
-
- freq = CHAN5G_FREQ(CHSPEC_CHANNEL(pi->radio_chanspec));
-
- if (freq < 5150) {
-
- paa_boost_tune = 0xa;
- pada_boost_tune = 0x77;
- pgaa_boost_tune = 0xf;
- mixa_boost_tune = 0xf;
- } else if (freq < 5340) {
-
- paa_boost_tune = 0x8;
- pada_boost_tune = 0x77;
- pgaa_boost_tune = 0xfb;
- mixa_boost_tune = 0xf;
- } else if (freq < 5650) {
-
- paa_boost_tune = 0x0;
- pada_boost_tune = 0x77;
- pgaa_boost_tune = 0xb;
- mixa_boost_tune = 0xf;
- } else {
-
- paa_boost_tune = 0x0;
- pada_boost_tune = 0x77;
- if (freq != 5825) {
- pgaa_boost_tune = -(int)(freq - 18) / 36 + 168;
- } else {
- pgaa_boost_tune = 6;
- }
- mixa_boost_tune = 0xf;
- }
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAA_BOOST_TUNE, paa_boost_tune);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- PADA_BOOST_TUNE, pada_boost_tune);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- PGAA_BOOST_TUNE, pgaa_boost_tune);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- MIXA_BOOST_TUNE, mixa_boost_tune);
-
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- TXSPARE1, 0x30);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- PA_SPARE2, 0xee);
-
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- PADA_CASCBIAS, 0x3);
-
- cascbias = 0x30;
-
- if ((pi->sh->chip == BCM43224_CHIP_ID) ||
- (pi->sh->chip == BCM43225_CHIP_ID) ||
- (pi->sh->chip == BCM43421_CHIP_ID)) {
- if (pi->sh->chippkg == BCM43224_FAB_SMIC) {
- cascbias = 0x35;
- }
- }
-
- pabias = (pi->phy_pabias == 0) ? 0x30 : pi->phy_pabias;
-
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAA_IAUX_STAT, pabias);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAA_IMAIN_STAT, pabias);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAA_CASCBIAS, cascbias);
- }
- }
-
- udelay(50);
-
- wlc_phy_radio205x_vcocal_nphy(pi);
-}
-
-void wlc_phy_radio205x_vcocal_nphy(phy_info_t *pi)
-{
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_EN, 0x01, 0x0);
- mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x04, 0x0);
- mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_CAL_RESETN, 0x04,
- (1 << 2));
- mod_radio_reg(pi, RADIO_2057_RFPLL_MISC_EN, 0x01, 0x01);
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- write_radio_reg(pi, RADIO_2056_SYN_PLL_VCOCAL12, 0x0);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x38);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x18);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x38);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST3, 0x39);
- }
-
- udelay(300);
-}
-
-#define MAX_205x_RCAL_WAITLOOPS 10000
-
-static u16 wlc_phy_radio205x_rcal(phy_info_t *pi)
-{
- u16 rcal_reg = 0;
- int i;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- if (pi->pubpi.radiorev == 5) {
-
- and_phy_reg(pi, 0x342, ~(0x1 << 1));
-
- udelay(10);
-
- mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x1);
- mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
- 0x1);
- }
- mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x1);
-
- udelay(10);
-
- mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x3, 0x3);
-
- for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
- rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS);
- if (rcal_reg & 0x1) {
- break;
- }
- udelay(100);
- }
-
- if (WARN(i == MAX_205x_RCAL_WAITLOOPS,
- "HW error: radio calib2"))
- return 0;
-
- mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x2, 0x0);
-
- rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS) & 0x3e;
-
- mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x1, 0x0);
- if (pi->pubpi.radiorev == 5) {
-
- mod_radio_reg(pi, RADIO_2057_IQTEST_SEL_PU, 0x1, 0x0);
- mod_radio_reg(pi, RADIO_2057v7_IQTEST_SEL_PU2, 0x2,
- 0x0);
- }
-
- if ((pi->pubpi.radiorev <= 4) || (pi->pubpi.radiorev == 6)) {
-
- mod_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG, 0x3c,
- rcal_reg);
- mod_radio_reg(pi, RADIO_2057_BANDGAP_RCAL_TRIM, 0xf0,
- rcal_reg << 2);
- }
-
- } else if (NREV_IS(pi->pubpi.phy_rev, 3)) {
- u16 savereg;
-
- savereg =
- read_radio_reg(pi,
- RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN);
- write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
- savereg | 0x7);
- udelay(10);
-
- write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
- 0x1);
- udelay(10);
-
- write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
- 0x9);
-
- for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
- rcal_reg = read_radio_reg(pi,
- RADIO_2056_SYN_RCAL_CODE_OUT |
- RADIO_2056_SYN);
- if (rcal_reg & 0x80) {
- break;
- }
- udelay(100);
- }
-
- if (WARN(i == MAX_205x_RCAL_WAITLOOPS,
- "HW error: radio calib3"))
- return 0;
-
- write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
- 0x1);
-
- rcal_reg =
- read_radio_reg(pi,
- RADIO_2056_SYN_RCAL_CODE_OUT |
- RADIO_2056_SYN);
-
- write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
- 0x0);
-
- write_radio_reg(pi, RADIO_2056_SYN_PLL_MAST2 | RADIO_2056_SYN,
- savereg);
-
- return rcal_reg & 0x1f;
- }
- return rcal_reg & 0x3e;
-}
-
-static void
-wlc_phy_chanspec_radio2057_setup(phy_info_t *pi,
- const chan_info_nphy_radio2057_t *ci,
- const chan_info_nphy_radio2057_rev5_t *ci2)
-{
- int coreNum;
- u16 txmix2g_tune_boost_pu = 0;
- u16 pad2g_tune_pus = 0;
-
- if (pi->pubpi.radiorev == 5) {
-
- write_radio_reg(pi,
- RADIO_2057_VCOCAL_COUNTVAL0,
- ci2->RF_vcocal_countval0);
- write_radio_reg(pi, RADIO_2057_VCOCAL_COUNTVAL1,
- ci2->RF_vcocal_countval1);
- write_radio_reg(pi, RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE,
- ci2->RF_rfpll_refmaster_sparextalsize);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
- ci2->RF_rfpll_loopfilter_r1);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
- ci2->RF_rfpll_loopfilter_c2);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
- ci2->RF_rfpll_loopfilter_c1);
- write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC,
- ci2->RF_cp_kpd_idac);
- write_radio_reg(pi, RADIO_2057_RFPLL_MMD0, ci2->RF_rfpll_mmd0);
- write_radio_reg(pi, RADIO_2057_RFPLL_MMD1, ci2->RF_rfpll_mmd1);
- write_radio_reg(pi,
- RADIO_2057_VCOBUF_TUNE, ci2->RF_vcobuf_tune);
- write_radio_reg(pi,
- RADIO_2057_LOGEN_MX2G_TUNE,
- ci2->RF_logen_mx2g_tune);
- write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF2G_TUNE,
- ci2->RF_logen_indbuf2g_tune);
-
- write_radio_reg(pi,
- RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
- ci2->RF_txmix2g_tune_boost_pu_core0);
- write_radio_reg(pi,
- RADIO_2057_PAD2G_TUNE_PUS_CORE0,
- ci2->RF_pad2g_tune_pus_core0);
- write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE0,
- ci2->RF_lna2g_tune_core0);
-
- write_radio_reg(pi,
- RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
- ci2->RF_txmix2g_tune_boost_pu_core1);
- write_radio_reg(pi,
- RADIO_2057_PAD2G_TUNE_PUS_CORE1,
- ci2->RF_pad2g_tune_pus_core1);
- write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE1,
- ci2->RF_lna2g_tune_core1);
-
- } else {
-
- write_radio_reg(pi,
- RADIO_2057_VCOCAL_COUNTVAL0,
- ci->RF_vcocal_countval0);
- write_radio_reg(pi, RADIO_2057_VCOCAL_COUNTVAL1,
- ci->RF_vcocal_countval1);
- write_radio_reg(pi, RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE,
- ci->RF_rfpll_refmaster_sparextalsize);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
- ci->RF_rfpll_loopfilter_r1);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
- ci->RF_rfpll_loopfilter_c2);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
- ci->RF_rfpll_loopfilter_c1);
- write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, ci->RF_cp_kpd_idac);
- write_radio_reg(pi, RADIO_2057_RFPLL_MMD0, ci->RF_rfpll_mmd0);
- write_radio_reg(pi, RADIO_2057_RFPLL_MMD1, ci->RF_rfpll_mmd1);
- write_radio_reg(pi, RADIO_2057_VCOBUF_TUNE, ci->RF_vcobuf_tune);
- write_radio_reg(pi,
- RADIO_2057_LOGEN_MX2G_TUNE,
- ci->RF_logen_mx2g_tune);
- write_radio_reg(pi, RADIO_2057_LOGEN_MX5G_TUNE,
- ci->RF_logen_mx5g_tune);
- write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF2G_TUNE,
- ci->RF_logen_indbuf2g_tune);
- write_radio_reg(pi, RADIO_2057_LOGEN_INDBUF5G_TUNE,
- ci->RF_logen_indbuf5g_tune);
-
- write_radio_reg(pi,
- RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0,
- ci->RF_txmix2g_tune_boost_pu_core0);
- write_radio_reg(pi,
- RADIO_2057_PAD2G_TUNE_PUS_CORE0,
- ci->RF_pad2g_tune_pus_core0);
- write_radio_reg(pi, RADIO_2057_PGA_BOOST_TUNE_CORE0,
- ci->RF_pga_boost_tune_core0);
- write_radio_reg(pi, RADIO_2057_TXMIX5G_BOOST_TUNE_CORE0,
- ci->RF_txmix5g_boost_tune_core0);
- write_radio_reg(pi, RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE0,
- ci->RF_pad5g_tune_misc_pus_core0);
- write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE0,
- ci->RF_lna2g_tune_core0);
- write_radio_reg(pi, RADIO_2057_LNA5G_TUNE_CORE0,
- ci->RF_lna5g_tune_core0);
-
- write_radio_reg(pi,
- RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1,
- ci->RF_txmix2g_tune_boost_pu_core1);
- write_radio_reg(pi,
- RADIO_2057_PAD2G_TUNE_PUS_CORE1,
- ci->RF_pad2g_tune_pus_core1);
- write_radio_reg(pi, RADIO_2057_PGA_BOOST_TUNE_CORE1,
- ci->RF_pga_boost_tune_core1);
- write_radio_reg(pi, RADIO_2057_TXMIX5G_BOOST_TUNE_CORE1,
- ci->RF_txmix5g_boost_tune_core1);
- write_radio_reg(pi, RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE1,
- ci->RF_pad5g_tune_misc_pus_core1);
- write_radio_reg(pi, RADIO_2057_LNA2G_TUNE_CORE1,
- ci->RF_lna2g_tune_core1);
- write_radio_reg(pi, RADIO_2057_LNA5G_TUNE_CORE1,
- ci->RF_lna5g_tune_core1);
- }
-
- if ((pi->pubpi.radiorev <= 4) || (pi->pubpi.radiorev == 6)) {
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
- 0x3f);
- write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
- 0x8);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
- 0x8);
- } else {
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
- 0x1f);
- write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
- 0x8);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
- 0x8);
- }
- } else if ((pi->pubpi.radiorev == 5) || (pi->pubpi.radiorev == 7) ||
- (pi->pubpi.radiorev == 8)) {
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
- 0x1b);
- write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x30);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
- 0xa);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
- 0xa);
- } else {
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_R1,
- 0x1f);
- write_radio_reg(pi, RADIO_2057_CP_KPD_IDAC, 0x3f);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C1,
- 0x8);
- write_radio_reg(pi, RADIO_2057_RFPLL_LOOPFILTER_C2,
- 0x8);
- }
-
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (PHY_IPA(pi)) {
- if (pi->pubpi.radiorev == 3) {
- txmix2g_tune_boost_pu = 0x6b;
- }
-
- if (pi->pubpi.radiorev == 5)
- pad2g_tune_pus = 0x73;
-
- } else {
- if (pi->pubpi.radiorev != 5) {
- pad2g_tune_pus = 0x3;
-
- txmix2g_tune_boost_pu = 0x61;
- }
- }
-
- for (coreNum = 0; coreNum <= 1; coreNum++) {
-
- if (txmix2g_tune_boost_pu != 0)
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
- TXMIX2G_TUNE_BOOST_PU,
- txmix2g_tune_boost_pu);
-
- if (pad2g_tune_pus != 0)
- WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
- PAD2G_TUNE_PUS,
- pad2g_tune_pus);
- }
- }
-
- udelay(50);
-
- wlc_phy_radio205x_vcocal_nphy(pi);
-}
-
-static u16 wlc_phy_radio2057_rccal(phy_info_t *pi)
-{
- u16 rccal_valid;
- int i;
- bool chip43226_6362A0;
-
- chip43226_6362A0 = ((pi->pubpi.radiorev == 3)
- || (pi->pubpi.radiorev == 4)
- || (pi->pubpi.radiorev == 6));
-
- rccal_valid = 0;
- if (chip43226_6362A0) {
- write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x61);
- write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xc0);
- } else {
- write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x61);
-
- write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xe9);
- }
- write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
- write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
-
- for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
- rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
- if (rccal_valid & 0x2) {
- break;
- }
- udelay(500);
- }
-
- write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
-
- rccal_valid = 0;
- if (chip43226_6362A0) {
- write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x69);
- write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xb0);
- } else {
- write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x69);
-
- write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xd5);
- }
- write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
- write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
-
- for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
- rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
- if (rccal_valid & 0x2) {
- break;
- }
- udelay(500);
- }
-
- write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
-
- rccal_valid = 0;
- if (chip43226_6362A0) {
- write_radio_reg(pi, RADIO_2057_RCCAL_MASTER, 0x73);
-
- write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x28);
- write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0xb0);
- } else {
- write_radio_reg(pi, RADIO_2057v7_RCCAL_MASTER, 0x73);
- write_radio_reg(pi, RADIO_2057_RCCAL_X1, 0x6e);
- write_radio_reg(pi, RADIO_2057_RCCAL_TRC0, 0x99);
- }
- write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x55);
-
- for (i = 0; i < MAX_205x_RCAL_WAITLOOPS; i++) {
- rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
- if (rccal_valid & 0x2) {
- break;
- }
- udelay(500);
- }
-
- if (WARN(!(rccal_valid & 0x2), "HW error: radio calib4"))
- return 0;
-
- write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
-
- return rccal_valid;
-}
-
-static void
-wlc_phy_adjust_rx_analpfbw_nphy(phy_info_t *pi, u16 reduction_factr)
-{
- if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
- if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) &&
- CHSPEC_IS40(pi->radio_chanspec)) {
- if (!pi->nphy_anarxlpf_adjusted) {
- write_radio_reg(pi,
- (RADIO_2056_RX_RXLPF_RCCAL_LPC |
- RADIO_2056_RX0),
- ((pi->nphy_rccal_value +
- reduction_factr) | 0x80));
-
- pi->nphy_anarxlpf_adjusted = true;
- }
- } else {
- if (pi->nphy_anarxlpf_adjusted) {
- write_radio_reg(pi,
- (RADIO_2056_RX_RXLPF_RCCAL_LPC |
- RADIO_2056_RX0),
- (pi->nphy_rccal_value | 0x80));
-
- pi->nphy_anarxlpf_adjusted = false;
- }
- }
- }
-}
-
-static void
-wlc_phy_adjust_min_noisevar_nphy(phy_info_t *pi, int ntones, int *tone_id_buf,
- u32 *noise_var_buf)
-{
- int i;
- u32 offset;
- int tone_id;
- int tbllen =
- CHSPEC_IS40(pi->
- radio_chanspec) ? NPHY_NOISEVAR_TBLLEN40 :
- NPHY_NOISEVAR_TBLLEN20;
-
- if (pi->nphy_noisevars_adjusted) {
- for (i = 0; i < pi->nphy_saved_noisevars.bufcount; i++) {
- tone_id = pi->nphy_saved_noisevars.tone_id[i];
- offset = (tone_id >= 0) ?
- ((tone_id * 2) + 1) : (tbllen + (tone_id * 2) + 1);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
- offset, 32,
- (void *)&pi->
- nphy_saved_noisevars.
- min_noise_vars[i]);
- }
-
- pi->nphy_saved_noisevars.bufcount = 0;
- pi->nphy_noisevars_adjusted = false;
- }
-
- if ((noise_var_buf != NULL) && (tone_id_buf != NULL)) {
- pi->nphy_saved_noisevars.bufcount = 0;
-
- for (i = 0; i < ntones; i++) {
- tone_id = tone_id_buf[i];
- offset = (tone_id >= 0) ?
- ((tone_id * 2) + 1) : (tbllen + (tone_id * 2) + 1);
- pi->nphy_saved_noisevars.tone_id[i] = tone_id;
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
- offset, 32,
- &pi->nphy_saved_noisevars.
- min_noise_vars[i]);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_NOISEVAR, 1,
- offset, 32,
- (void *)&noise_var_buf[i]);
- pi->nphy_saved_noisevars.bufcount++;
- }
-
- pi->nphy_noisevars_adjusted = true;
- }
-}
-
-static void wlc_phy_adjust_crsminpwr_nphy(phy_info_t *pi, u8 minpwr)
-{
- u16 regval;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if ((CHSPEC_CHANNEL(pi->radio_chanspec) == 11) &&
- CHSPEC_IS40(pi->radio_chanspec)) {
- if (!pi->nphy_crsminpwr_adjusted) {
- regval = read_phy_reg(pi, 0x27d);
- pi->nphy_crsminpwr[0] = regval & 0xff;
- regval &= 0xff00;
- regval |= (u16) minpwr;
- write_phy_reg(pi, 0x27d, regval);
-
- regval = read_phy_reg(pi, 0x280);
- pi->nphy_crsminpwr[1] = regval & 0xff;
- regval &= 0xff00;
- regval |= (u16) minpwr;
- write_phy_reg(pi, 0x280, regval);
-
- regval = read_phy_reg(pi, 0x283);
- pi->nphy_crsminpwr[2] = regval & 0xff;
- regval &= 0xff00;
- regval |= (u16) minpwr;
- write_phy_reg(pi, 0x283, regval);
-
- pi->nphy_crsminpwr_adjusted = true;
- }
- } else {
- if (pi->nphy_crsminpwr_adjusted) {
- regval = read_phy_reg(pi, 0x27d);
- regval &= 0xff00;
- regval |= pi->nphy_crsminpwr[0];
- write_phy_reg(pi, 0x27d, regval);
-
- regval = read_phy_reg(pi, 0x280);
- regval &= 0xff00;
- regval |= pi->nphy_crsminpwr[1];
- write_phy_reg(pi, 0x280, regval);
-
- regval = read_phy_reg(pi, 0x283);
- regval &= 0xff00;
- regval |= pi->nphy_crsminpwr[2];
- write_phy_reg(pi, 0x283, regval);
-
- pi->nphy_crsminpwr_adjusted = false;
- }
- }
- }
-}
-
-static void wlc_phy_txlpfbw_nphy(phy_info_t *pi)
-{
- u8 tx_lpf_bw = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- tx_lpf_bw = 3;
- } else {
- tx_lpf_bw = 1;
- }
-
- if (PHY_IPA(pi)) {
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- tx_lpf_bw = 5;
- } else {
- tx_lpf_bw = 4;
- }
- }
- write_phy_reg(pi, 0xe8,
- (tx_lpf_bw << 0) |
- (tx_lpf_bw << 3) |
- (tx_lpf_bw << 6) | (tx_lpf_bw << 9));
-
- if (PHY_IPA(pi)) {
-
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- tx_lpf_bw = 4;
- } else {
- tx_lpf_bw = 1;
- }
-
- write_phy_reg(pi, 0xe9,
- (tx_lpf_bw << 0) |
- (tx_lpf_bw << 3) |
- (tx_lpf_bw << 6) | (tx_lpf_bw << 9));
- }
- }
-}
-
-static void wlc_phy_spurwar_nphy(phy_info_t *pi)
-{
- u16 cur_channel = 0;
- int nphy_adj_tone_id_buf[] = { 57, 58 };
- u32 nphy_adj_noise_var_buf[] = { 0x3ff, 0x3ff };
- bool isAdjustNoiseVar = false;
- uint numTonesAdjust = 0;
- u32 tempval = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- cur_channel = CHSPEC_CHANNEL(pi->radio_chanspec);
-
- if (pi->nphy_gband_spurwar_en) {
-
- wlc_phy_adjust_rx_analpfbw_nphy(pi,
- NPHY_ANARXLPFBW_REDUCTIONFACT);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if ((cur_channel == 11)
- && CHSPEC_IS40(pi->radio_chanspec)) {
-
- wlc_phy_adjust_min_noisevar_nphy(pi, 2,
- nphy_adj_tone_id_buf,
- nphy_adj_noise_var_buf);
- } else {
-
- wlc_phy_adjust_min_noisevar_nphy(pi, 0,
- NULL,
- NULL);
- }
- }
- wlc_phy_adjust_crsminpwr_nphy(pi,
- NPHY_ADJUSTED_MINCRSPOWER);
- }
-
- if ((pi->nphy_gband_spurwar2_en)
- && CHSPEC_IS2G(pi->radio_chanspec)) {
-
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- switch (cur_channel) {
- case 3:
- nphy_adj_tone_id_buf[0] = 57;
- nphy_adj_tone_id_buf[1] = 58;
- nphy_adj_noise_var_buf[0] = 0x22f;
- nphy_adj_noise_var_buf[1] = 0x25f;
- isAdjustNoiseVar = true;
- break;
- case 4:
- nphy_adj_tone_id_buf[0] = 41;
- nphy_adj_tone_id_buf[1] = 42;
- nphy_adj_noise_var_buf[0] = 0x22f;
- nphy_adj_noise_var_buf[1] = 0x25f;
- isAdjustNoiseVar = true;
- break;
- case 5:
- nphy_adj_tone_id_buf[0] = 25;
- nphy_adj_tone_id_buf[1] = 26;
- nphy_adj_noise_var_buf[0] = 0x24f;
- nphy_adj_noise_var_buf[1] = 0x25f;
- isAdjustNoiseVar = true;
- break;
- case 6:
- nphy_adj_tone_id_buf[0] = 9;
- nphy_adj_tone_id_buf[1] = 10;
- nphy_adj_noise_var_buf[0] = 0x22f;
- nphy_adj_noise_var_buf[1] = 0x24f;
- isAdjustNoiseVar = true;
- break;
- case 7:
- nphy_adj_tone_id_buf[0] = 121;
- nphy_adj_tone_id_buf[1] = 122;
- nphy_adj_noise_var_buf[0] = 0x18f;
- nphy_adj_noise_var_buf[1] = 0x24f;
- isAdjustNoiseVar = true;
- break;
- case 8:
- nphy_adj_tone_id_buf[0] = 105;
- nphy_adj_tone_id_buf[1] = 106;
- nphy_adj_noise_var_buf[0] = 0x22f;
- nphy_adj_noise_var_buf[1] = 0x25f;
- isAdjustNoiseVar = true;
- break;
- case 9:
- nphy_adj_tone_id_buf[0] = 89;
- nphy_adj_tone_id_buf[1] = 90;
- nphy_adj_noise_var_buf[0] = 0x22f;
- nphy_adj_noise_var_buf[1] = 0x24f;
- isAdjustNoiseVar = true;
- break;
- case 10:
- nphy_adj_tone_id_buf[0] = 73;
- nphy_adj_tone_id_buf[1] = 74;
- nphy_adj_noise_var_buf[0] = 0x22f;
- nphy_adj_noise_var_buf[1] = 0x24f;
- isAdjustNoiseVar = true;
- break;
- default:
- isAdjustNoiseVar = false;
- break;
- }
- }
-
- if (isAdjustNoiseVar) {
- numTonesAdjust = sizeof(nphy_adj_tone_id_buf) /
- sizeof(nphy_adj_tone_id_buf[0]);
-
- wlc_phy_adjust_min_noisevar_nphy(pi,
- numTonesAdjust,
- nphy_adj_tone_id_buf,
- nphy_adj_noise_var_buf);
-
- tempval = 0;
-
- } else {
-
- wlc_phy_adjust_min_noisevar_nphy(pi, 0, NULL,
- NULL);
- }
- }
-
- if ((pi->nphy_aband_spurwar_en) &&
- (CHSPEC_IS5G(pi->radio_chanspec))) {
- switch (cur_channel) {
- case 54:
- nphy_adj_tone_id_buf[0] = 32;
- nphy_adj_noise_var_buf[0] = 0x25f;
- break;
- case 38:
- case 102:
- case 118:
- if ((pi->sh->chip == BCM4716_CHIP_ID) &&
- (pi->sh->chippkg == BCM4717_PKG_ID)) {
- nphy_adj_tone_id_buf[0] = 32;
- nphy_adj_noise_var_buf[0] = 0x21f;
- } else {
- nphy_adj_tone_id_buf[0] = 0;
- nphy_adj_noise_var_buf[0] = 0x0;
- }
- break;
- case 134:
- nphy_adj_tone_id_buf[0] = 32;
- nphy_adj_noise_var_buf[0] = 0x21f;
- break;
- case 151:
- nphy_adj_tone_id_buf[0] = 16;
- nphy_adj_noise_var_buf[0] = 0x23f;
- break;
- case 153:
- case 161:
- nphy_adj_tone_id_buf[0] = 48;
- nphy_adj_noise_var_buf[0] = 0x23f;
- break;
- default:
- nphy_adj_tone_id_buf[0] = 0;
- nphy_adj_noise_var_buf[0] = 0x0;
- break;
- }
-
- if (nphy_adj_tone_id_buf[0]
- && nphy_adj_noise_var_buf[0]) {
- wlc_phy_adjust_min_noisevar_nphy(pi, 1,
- nphy_adj_tone_id_buf,
- nphy_adj_noise_var_buf);
- } else {
- wlc_phy_adjust_min_noisevar_nphy(pi, 0, NULL,
- NULL);
- }
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
- }
-}
-
-static void
-wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec,
- const nphy_sfo_cfg_t *ci)
-{
- u16 val;
-
- val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
- if (CHSPEC_IS5G(chanspec) && !val) {
-
- val = R_REG(&pi->regs->psm_phy_hdr_param);
- W_REG(&pi->regs->psm_phy_hdr_param,
- (val | MAC_PHY_FORCE_CLK));
-
- or_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
- (BBCFG_RESETCCA | BBCFG_RESETRX));
-
- W_REG(&pi->regs->psm_phy_hdr_param, val);
-
- or_phy_reg(pi, 0x09, NPHY_BandControl_currentBand);
- } else if (!CHSPEC_IS5G(chanspec) && val) {
-
- and_phy_reg(pi, 0x09, ~NPHY_BandControl_currentBand);
-
- val = R_REG(&pi->regs->psm_phy_hdr_param);
- W_REG(&pi->regs->psm_phy_hdr_param,
- (val | MAC_PHY_FORCE_CLK));
-
- and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
- (u16) (~(BBCFG_RESETCCA | BBCFG_RESETRX)));
-
- W_REG(&pi->regs->psm_phy_hdr_param, val);
- }
-
- write_phy_reg(pi, 0x1ce, ci->PHY_BW1a);
- write_phy_reg(pi, 0x1cf, ci->PHY_BW2);
- write_phy_reg(pi, 0x1d0, ci->PHY_BW3);
-
- write_phy_reg(pi, 0x1d1, ci->PHY_BW4);
- write_phy_reg(pi, 0x1d2, ci->PHY_BW5);
- write_phy_reg(pi, 0x1d3, ci->PHY_BW6);
-
- if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
- wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_ofdm_en, 0);
-
- or_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, 0x800);
- } else {
- wlc_phy_classifier_nphy(pi, NPHY_ClassifierCtrl_ofdm_en,
- NPHY_ClassifierCtrl_ofdm_en);
-
- if (CHSPEC_IS2G(chanspec))
- and_phy_reg(pi, NPHY_TO_BPHY_OFF + BPHY_TEST, ~0x840);
- }
-
- if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
- wlc_phy_txpwr_fixpower_nphy(pi);
- }
-
- if (NREV_LT(pi->pubpi.phy_rev, 3)) {
-
- wlc_phy_adjust_lnagaintbl_nphy(pi);
- }
-
- wlc_phy_txlpfbw_nphy(pi);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)
- && (pi->phy_spuravoid != SPURAVOID_DISABLE)) {
- u8 spuravoid = 0;
-
- val = CHSPEC_CHANNEL(chanspec);
- if (!CHSPEC_IS40(pi->radio_chanspec)) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if ((val == 13) || (val == 14) || (val == 153)) {
- spuravoid = 1;
- }
- } else {
-
- if (((val >= 5) && (val <= 8)) || (val == 13)
- || (val == 14)) {
- spuravoid = 1;
- }
- }
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (val == 54) {
- spuravoid = 1;
- }
- } else {
-
- if (pi->nphy_aband_spurwar_en &&
- ((val == 38) || (val == 102)
- || (val == 118))) {
- if ((pi->sh->chip ==
- BCM4716_CHIP_ID)
- && (pi->sh->chippkg ==
- BCM4717_PKG_ID)) {
- spuravoid = 0;
- } else {
- spuravoid = 1;
- }
- }
- }
- }
-
- if (pi->phy_spuravoid == SPURAVOID_FORCEON)
- spuravoid = 1;
-
- if ((pi->sh->chip == BCM4716_CHIP_ID) ||
- (pi->sh->chip == BCM47162_CHIP_ID)) {
- si_pmu_spuravoid(pi->sh->sih, spuravoid);
- } else {
- wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
- si_pmu_spuravoid(pi->sh->sih, spuravoid);
- wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
- }
-
- if ((pi->sh->chip == BCM43224_CHIP_ID) ||
- (pi->sh->chip == BCM43225_CHIP_ID) ||
- (pi->sh->chip == BCM43421_CHIP_ID)) {
-
- if (spuravoid == 1) {
-
- W_REG(&pi->regs->tsf_clk_frac_l,
- 0x5341);
- W_REG(&pi->regs->tsf_clk_frac_h,
- 0x8);
- } else {
-
- W_REG(&pi->regs->tsf_clk_frac_l,
- 0x8889);
- W_REG(&pi->regs->tsf_clk_frac_h,
- 0x8);
- }
- }
-
- if (!((pi->sh->chip == BCM4716_CHIP_ID) ||
- (pi->sh->chip == BCM47162_CHIP_ID))) {
- wlapi_bmac_core_phypll_reset(pi->sh->physhim);
- }
-
- mod_phy_reg(pi, 0x01, (0x1 << 15),
- ((spuravoid > 0) ? (0x1 << 15) : 0));
-
- wlc_phy_resetcca_nphy(pi);
-
- pi->phy_isspuravoid = (spuravoid > 0);
- }
-
- if (NREV_LT(pi->pubpi.phy_rev, 7))
- write_phy_reg(pi, 0x17e, 0x3830);
-
- wlc_phy_spurwar_nphy(pi);
-}
-
-void wlc_phy_chanspec_set_nphy(phy_info_t *pi, chanspec_t chanspec)
-{
- int freq;
- chan_info_nphy_radio2057_t *t0 = NULL;
- chan_info_nphy_radio205x_t *t1 = NULL;
- chan_info_nphy_radio2057_rev5_t *t2 = NULL;
- chan_info_nphy_2055_t *t3 = NULL;
-
- if (NORADIO_ENAB(pi->pubpi)) {
- return;
- }
-
- if (!wlc_phy_chan2freq_nphy
- (pi, CHSPEC_CHANNEL(chanspec), &freq, &t0, &t1, &t2, &t3))
- return;
-
- wlc_phy_chanspec_radio_set((wlc_phy_t *) pi, chanspec);
-
- if (CHSPEC_BW(chanspec) != pi->bw)
- wlapi_bmac_bw_set(pi->sh->physhim, CHSPEC_BW(chanspec));
-
- if (CHSPEC_IS40(chanspec)) {
- if (CHSPEC_SB_UPPER(chanspec)) {
- or_phy_reg(pi, 0xa0, BPHY_BAND_SEL_UP20);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- or_phy_reg(pi, 0x310, PRIM_SEL_UP20);
- }
- } else {
- and_phy_reg(pi, 0xa0, ~BPHY_BAND_SEL_UP20);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- and_phy_reg(pi, 0x310,
- (~PRIM_SEL_UP20 & 0xffff));
- }
- }
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- if ((pi->pubpi.radiorev <= 4)
- || (pi->pubpi.radiorev == 6)) {
- mod_radio_reg(pi, RADIO_2057_TIA_CONFIG_CORE0,
- 0x2,
- (CHSPEC_IS5G(chanspec) ? (1 << 1)
- : 0));
- mod_radio_reg(pi, RADIO_2057_TIA_CONFIG_CORE1,
- 0x2,
- (CHSPEC_IS5G(chanspec) ? (1 << 1)
- : 0));
- }
-
- wlc_phy_chanspec_radio2057_setup(pi, t0, t2);
- wlc_phy_chanspec_nphy_setup(pi, chanspec,
- (pi->pubpi.radiorev ==
- 5) ? (const nphy_sfo_cfg_t
- *)&(t2->
- PHY_BW1a)
- : (const nphy_sfo_cfg_t *)
- &(t0->PHY_BW1a));
-
- } else {
-
- mod_radio_reg(pi,
- RADIO_2056_SYN_COM_CTRL | RADIO_2056_SYN,
- 0x4,
- (CHSPEC_IS5G(chanspec) ? (0x1 << 2) : 0));
- wlc_phy_chanspec_radio2056_setup(pi, t1);
-
- wlc_phy_chanspec_nphy_setup(pi, chanspec,
- (const nphy_sfo_cfg_t *)
- &(t1->PHY_BW1a));
- }
-
- } else {
-
- mod_radio_reg(pi, RADIO_2055_MASTER_CNTRL1, 0x70,
- (CHSPEC_IS5G(chanspec) ? (0x02 << 4)
- : (0x05 << 4)));
-
- wlc_phy_chanspec_radio2055_setup(pi, t3);
- wlc_phy_chanspec_nphy_setup(pi, chanspec,
- (const nphy_sfo_cfg_t *)&(t3->
- PHY_BW1a));
- }
-
-}
-
-static void wlc_phy_savecal_nphy(phy_info_t *pi)
-{
- void *tbl_ptr;
- int coreNum;
- u16 *txcal_radio_regs = NULL;
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
-
- wlc_phy_rx_iq_coeffs_nphy(pi, 0,
- &pi->calibration_cache.
- rxcal_coeffs_2G);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- txcal_radio_regs =
- pi->calibration_cache.txcal_radio_regs_2G;
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- pi->calibration_cache.txcal_radio_regs_2G[0] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_I |
- RADIO_2056_TX0);
- pi->calibration_cache.txcal_radio_regs_2G[1] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_Q |
- RADIO_2056_TX0);
- pi->calibration_cache.txcal_radio_regs_2G[2] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_I |
- RADIO_2056_TX1);
- pi->calibration_cache.txcal_radio_regs_2G[3] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_Q |
- RADIO_2056_TX1);
-
- pi->calibration_cache.txcal_radio_regs_2G[4] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_I |
- RADIO_2056_TX0);
- pi->calibration_cache.txcal_radio_regs_2G[5] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_Q |
- RADIO_2056_TX0);
- pi->calibration_cache.txcal_radio_regs_2G[6] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_I |
- RADIO_2056_TX1);
- pi->calibration_cache.txcal_radio_regs_2G[7] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_Q |
- RADIO_2056_TX1);
- } else {
- pi->calibration_cache.txcal_radio_regs_2G[0] =
- read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
- pi->calibration_cache.txcal_radio_regs_2G[1] =
- read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
- pi->calibration_cache.txcal_radio_regs_2G[2] =
- read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
- pi->calibration_cache.txcal_radio_regs_2G[3] =
- read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
- }
-
- pi->nphy_iqcal_chanspec_2G = pi->radio_chanspec;
- tbl_ptr = pi->calibration_cache.txcal_coeffs_2G;
- } else {
-
- wlc_phy_rx_iq_coeffs_nphy(pi, 0,
- &pi->calibration_cache.
- rxcal_coeffs_5G);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- txcal_radio_regs =
- pi->calibration_cache.txcal_radio_regs_5G;
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- pi->calibration_cache.txcal_radio_regs_5G[0] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_I |
- RADIO_2056_TX0);
- pi->calibration_cache.txcal_radio_regs_5G[1] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_Q |
- RADIO_2056_TX0);
- pi->calibration_cache.txcal_radio_regs_5G[2] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_I |
- RADIO_2056_TX1);
- pi->calibration_cache.txcal_radio_regs_5G[3] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_Q |
- RADIO_2056_TX1);
-
- pi->calibration_cache.txcal_radio_regs_5G[4] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_I |
- RADIO_2056_TX0);
- pi->calibration_cache.txcal_radio_regs_5G[5] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_Q |
- RADIO_2056_TX0);
- pi->calibration_cache.txcal_radio_regs_5G[6] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_I |
- RADIO_2056_TX1);
- pi->calibration_cache.txcal_radio_regs_5G[7] =
- read_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_Q |
- RADIO_2056_TX1);
- } else {
- pi->calibration_cache.txcal_radio_regs_5G[0] =
- read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
- pi->calibration_cache.txcal_radio_regs_5G[1] =
- read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
- pi->calibration_cache.txcal_radio_regs_5G[2] =
- read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
- pi->calibration_cache.txcal_radio_regs_5G[3] =
- read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
- }
-
- pi->nphy_iqcal_chanspec_5G = pi->radio_chanspec;
- tbl_ptr = pi->calibration_cache.txcal_coeffs_5G;
- }
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- for (coreNum = 0; coreNum <= 1; coreNum++) {
-
- txcal_radio_regs[2 * coreNum] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
- LOFT_FINE_I);
- txcal_radio_regs[2 * coreNum + 1] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
- LOFT_FINE_Q);
-
- txcal_radio_regs[2 * coreNum + 4] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
- LOFT_COARSE_I);
- txcal_radio_regs[2 * coreNum + 5] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
- LOFT_COARSE_Q);
- }
- }
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 8, 80, 16, tbl_ptr);
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-static void wlc_phy_restorecal_nphy(phy_info_t *pi)
-{
- u16 *loft_comp;
- u16 txcal_coeffs_bphy[4];
- u16 *tbl_ptr;
- int coreNum;
- u16 *txcal_radio_regs = NULL;
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (pi->nphy_iqcal_chanspec_2G == 0)
- return;
-
- tbl_ptr = pi->calibration_cache.txcal_coeffs_2G;
- loft_comp = &pi->calibration_cache.txcal_coeffs_2G[5];
- } else {
- if (pi->nphy_iqcal_chanspec_5G == 0)
- return;
-
- tbl_ptr = pi->calibration_cache.txcal_coeffs_5G;
- loft_comp = &pi->calibration_cache.txcal_coeffs_5G[5];
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80, 16,
- (void *)tbl_ptr);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- txcal_coeffs_bphy[0] = tbl_ptr[0];
- txcal_coeffs_bphy[1] = tbl_ptr[1];
- txcal_coeffs_bphy[2] = tbl_ptr[2];
- txcal_coeffs_bphy[3] = tbl_ptr[3];
- } else {
- txcal_coeffs_bphy[0] = 0;
- txcal_coeffs_bphy[1] = 0;
- txcal_coeffs_bphy[2] = 0;
- txcal_coeffs_bphy[3] = 0;
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88, 16,
- txcal_coeffs_bphy);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85, 16, loft_comp);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93, 16, loft_comp);
-
- if (NREV_LT(pi->pubpi.phy_rev, 2))
- wlc_phy_tx_iq_war_nphy(pi);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- txcal_radio_regs =
- pi->calibration_cache.txcal_radio_regs_2G;
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_I |
- RADIO_2056_TX0,
- pi->calibration_cache.
- txcal_radio_regs_2G[0]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_Q |
- RADIO_2056_TX0,
- pi->calibration_cache.
- txcal_radio_regs_2G[1]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_I |
- RADIO_2056_TX1,
- pi->calibration_cache.
- txcal_radio_regs_2G[2]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_Q |
- RADIO_2056_TX1,
- pi->calibration_cache.
- txcal_radio_regs_2G[3]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_I |
- RADIO_2056_TX0,
- pi->calibration_cache.
- txcal_radio_regs_2G[4]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_Q |
- RADIO_2056_TX0,
- pi->calibration_cache.
- txcal_radio_regs_2G[5]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_I |
- RADIO_2056_TX1,
- pi->calibration_cache.
- txcal_radio_regs_2G[6]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_Q |
- RADIO_2056_TX1,
- pi->calibration_cache.
- txcal_radio_regs_2G[7]);
- } else {
- write_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL,
- pi->calibration_cache.
- txcal_radio_regs_2G[0]);
- write_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL,
- pi->calibration_cache.
- txcal_radio_regs_2G[1]);
- write_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM,
- pi->calibration_cache.
- txcal_radio_regs_2G[2]);
- write_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM,
- pi->calibration_cache.
- txcal_radio_regs_2G[3]);
- }
-
- wlc_phy_rx_iq_coeffs_nphy(pi, 1,
- &pi->calibration_cache.
- rxcal_coeffs_2G);
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- txcal_radio_regs =
- pi->calibration_cache.txcal_radio_regs_5G;
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_I |
- RADIO_2056_TX0,
- pi->calibration_cache.
- txcal_radio_regs_5G[0]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_Q |
- RADIO_2056_TX0,
- pi->calibration_cache.
- txcal_radio_regs_5G[1]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_I |
- RADIO_2056_TX1,
- pi->calibration_cache.
- txcal_radio_regs_5G[2]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_FINE_Q |
- RADIO_2056_TX1,
- pi->calibration_cache.
- txcal_radio_regs_5G[3]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_I |
- RADIO_2056_TX0,
- pi->calibration_cache.
- txcal_radio_regs_5G[4]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_Q |
- RADIO_2056_TX0,
- pi->calibration_cache.
- txcal_radio_regs_5G[5]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_I |
- RADIO_2056_TX1,
- pi->calibration_cache.
- txcal_radio_regs_5G[6]);
- write_radio_reg(pi,
- RADIO_2056_TX_LOFT_COARSE_Q |
- RADIO_2056_TX1,
- pi->calibration_cache.
- txcal_radio_regs_5G[7]);
- } else {
- write_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL,
- pi->calibration_cache.
- txcal_radio_regs_5G[0]);
- write_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL,
- pi->calibration_cache.
- txcal_radio_regs_5G[1]);
- write_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM,
- pi->calibration_cache.
- txcal_radio_regs_5G[2]);
- write_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM,
- pi->calibration_cache.
- txcal_radio_regs_5G[3]);
- }
-
- wlc_phy_rx_iq_coeffs_nphy(pi, 1,
- &pi->calibration_cache.
- rxcal_coeffs_5G);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- for (coreNum = 0; coreNum <= 1; coreNum++) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
- LOFT_FINE_I,
- txcal_radio_regs[2 * coreNum]);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
- LOFT_FINE_Q,
- txcal_radio_regs[2 * coreNum + 1]);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
- LOFT_COARSE_I,
- txcal_radio_regs[2 * coreNum + 4]);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, coreNum,
- LOFT_COARSE_Q,
- txcal_radio_regs[2 * coreNum + 5]);
- }
- }
-}
-
-void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init)
-{
- phy_info_t *pi = (phy_info_t *) ppi;
- u16 mask = 0xfc00;
- u32 mc = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7))
- return;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- u16 v0 = 0x211, v1 = 0x222, v2 = 0x144, v3 = 0x188;
-
- if (lut_init == false)
- return;
-
- if (pi->srom_fem2g.antswctrllut == 0) {
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 1, 0x02, 16, &v0);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 1, 0x03, 16, &v1);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 1, 0x08, 16, &v2);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 1, 0x0C, 16, &v3);
- }
-
- if (pi->srom_fem5g.antswctrllut == 0) {
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 1, 0x12, 16, &v0);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 1, 0x13, 16, &v1);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 1, 0x18, 16, &v2);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
- 1, 0x1C, 16, &v3);
- }
- } else {
-
- write_phy_reg(pi, 0xc8, 0x0);
- write_phy_reg(pi, 0xc9, 0x0);
-
- ai_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
-
- mc = R_REG(&pi->regs->maccontrol);
- mc &= ~MCTL_GPOUT_SEL_MASK;
- W_REG(&pi->regs->maccontrol, mc);
-
- OR_REG(&pi->regs->psm_gpio_oe, mask);
-
- AND_REG(&pi->regs->psm_gpio_out, ~mask);
-
- if (lut_init) {
- write_phy_reg(pi, 0xf8, 0x02d8);
- write_phy_reg(pi, 0xf9, 0x0301);
- write_phy_reg(pi, 0xfa, 0x02d8);
- write_phy_reg(pi, 0xfb, 0x0301);
- }
- }
-}
-
-u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val)
-{
- u16 curr_ctl, new_ctl;
- bool suspended = false;
-
- if (D11REV_IS(pi->sh->corerev, 16)) {
- suspended =
- (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) ?
- false : true;
- if (!suspended)
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- }
-
- curr_ctl = read_phy_reg(pi, 0xb0) & (0x7 << 0);
-
- new_ctl = (curr_ctl & (~mask)) | (val & mask);
-
- mod_phy_reg(pi, 0xb0, (0x7 << 0), new_ctl);
-
- if (D11REV_IS(pi->sh->corerev, 16) && !suspended)
- wlapi_enable_mac(pi->sh->physhim);
-
- return new_ctl;
-}
-
-static void wlc_phy_clip_det_nphy(phy_info_t *pi, u8 write, u16 *vals)
-{
-
- if (write == 0) {
- vals[0] = read_phy_reg(pi, 0x2c);
- vals[1] = read_phy_reg(pi, 0x42);
- } else {
- write_phy_reg(pi, 0x2c, vals[0]);
- write_phy_reg(pi, 0x42, vals[1]);
- }
-}
-
-void wlc_phy_force_rfseq_nphy(phy_info_t *pi, u8 cmd)
-{
- u16 trigger_mask, status_mask;
- u16 orig_RfseqCoreActv;
-
- switch (cmd) {
- case NPHY_RFSEQ_RX2TX:
- trigger_mask = NPHY_RfseqTrigger_rx2tx;
- status_mask = NPHY_RfseqStatus_rx2tx;
- break;
- case NPHY_RFSEQ_TX2RX:
- trigger_mask = NPHY_RfseqTrigger_tx2rx;
- status_mask = NPHY_RfseqStatus_tx2rx;
- break;
- case NPHY_RFSEQ_RESET2RX:
- trigger_mask = NPHY_RfseqTrigger_reset2rx;
- status_mask = NPHY_RfseqStatus_reset2rx;
- break;
- case NPHY_RFSEQ_UPDATEGAINH:
- trigger_mask = NPHY_RfseqTrigger_updategainh;
- status_mask = NPHY_RfseqStatus_updategainh;
- break;
- case NPHY_RFSEQ_UPDATEGAINL:
- trigger_mask = NPHY_RfseqTrigger_updategainl;
- status_mask = NPHY_RfseqStatus_updategainl;
- break;
- case NPHY_RFSEQ_UPDATEGAINU:
- trigger_mask = NPHY_RfseqTrigger_updategainu;
- status_mask = NPHY_RfseqStatus_updategainu;
- break;
- default:
- return;
- }
-
- orig_RfseqCoreActv = read_phy_reg(pi, 0xa1);
- or_phy_reg(pi, 0xa1,
- (NPHY_RfseqMode_CoreActv_override |
- NPHY_RfseqMode_Trigger_override));
- or_phy_reg(pi, 0xa3, trigger_mask);
- SPINWAIT((read_phy_reg(pi, 0xa4) & status_mask), 200000);
- write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
- WARN(read_phy_reg(pi, 0xa4) & status_mask, "HW error in rf");
-}
-
-static void
-wlc_phy_set_rfseq_nphy(phy_info_t *pi, u8 cmd, u8 *events, u8 *dlys,
- u8 len)
-{
- u32 t1_offset, t2_offset;
- u8 ctr;
- u8 end_event =
- NREV_GE(pi->pubpi.phy_rev,
- 3) ? NPHY_REV3_RFSEQ_CMD_END : NPHY_RFSEQ_CMD_END;
- u8 end_dly = 1;
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- t1_offset = cmd << 4;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, len, t1_offset, 8,
- events);
- t2_offset = t1_offset + 0x080;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, len, t2_offset, 8,
- dlys);
-
- for (ctr = len; ctr < 16; ctr++) {
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
- t1_offset + ctr, 8, &end_event);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
- t2_offset + ctr, 8, &end_dly);
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-static u16 wlc_phy_read_lpf_bw_ctl_nphy(phy_info_t *pi, u16 offset)
-{
- u16 lpf_bw_ctl_val = 0;
- u16 rx2tx_lpf_rc_lut_offset = 0;
-
- if (offset == 0) {
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- rx2tx_lpf_rc_lut_offset = 0x159;
- } else {
- rx2tx_lpf_rc_lut_offset = 0x154;
- }
- } else {
- rx2tx_lpf_rc_lut_offset = offset;
- }
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 1,
- (u32) rx2tx_lpf_rc_lut_offset, 16,
- &lpf_bw_ctl_val);
-
- lpf_bw_ctl_val = lpf_bw_ctl_val & 0x7;
-
- return lpf_bw_ctl_val;
-}
-
-static void
-wlc_phy_rfctrl_override_nphy_rev7(phy_info_t *pi, u16 field, u16 value,
- u8 core_mask, u8 off, u8 override_id)
-{
- u8 core_num;
- u16 addr = 0, en_addr = 0, val_addr = 0, en_mask = 0, val_mask = 0;
- u8 val_shift = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- en_mask = field;
- for (core_num = 0; core_num < 2; core_num++) {
- if (override_id == NPHY_REV7_RFCTRLOVERRIDE_ID0) {
-
- switch (field) {
- case (0x1 << 2):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a :
- 0x7d;
- val_mask = (0x1 << 1);
- val_shift = 1;
- break;
- case (0x1 << 3):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a :
- 0x7d;
- val_mask = (0x1 << 2);
- val_shift = 2;
- break;
- case (0x1 << 4):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a :
- 0x7d;
- val_mask = (0x1 << 4);
- val_shift = 4;
- break;
- case (0x1 << 5):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a :
- 0x7d;
- val_mask = (0x1 << 5);
- val_shift = 5;
- break;
- case (0x1 << 6):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a :
- 0x7d;
- val_mask = (0x1 << 6);
- val_shift = 6;
- break;
- case (0x1 << 7):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a :
- 0x7d;
- val_mask = (0x1 << 7);
- val_shift = 7;
- break;
- case (0x1 << 10):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0xf8 :
- 0xfa;
- val_mask = (0x7 << 4);
- val_shift = 4;
- break;
- case (0x1 << 11):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7b :
- 0x7e;
- val_mask = (0xffff << 0);
- val_shift = 0;
- break;
- case (0x1 << 12):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7c :
- 0x7f;
- val_mask = (0xffff << 0);
- val_shift = 0;
- break;
- case (0x3 << 13):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x348 :
- 0x349;
- val_mask = (0xff << 0);
- val_shift = 0;
- break;
- case (0x1 << 13):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x348 :
- 0x349;
- val_mask = (0xf << 0);
- val_shift = 0;
- break;
- default:
- addr = 0xffff;
- break;
- }
- } else if (override_id == NPHY_REV7_RFCTRLOVERRIDE_ID1) {
-
- switch (field) {
- case (0x1 << 1):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 1);
- val_shift = 1;
- break;
- case (0x1 << 3):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 3);
- val_shift = 3;
- break;
- case (0x1 << 5):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 5);
- val_shift = 5;
- break;
- case (0x1 << 4):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 4);
- val_shift = 4;
- break;
- case (0x1 << 2):
-
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 2);
- val_shift = 2;
- break;
- case (0x1 << 7):
-
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x7 << 8);
- val_shift = 8;
- break;
- case (0x1 << 11):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 14);
- val_shift = 14;
- break;
- case (0x1 << 10):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 13);
- val_shift = 13;
- break;
- case (0x1 << 9):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 12);
- val_shift = 12;
- break;
- case (0x1 << 8):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 11);
- val_shift = 11;
- break;
- case (0x1 << 6):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 6);
- val_shift = 6;
- break;
- case (0x1 << 0):
- en_addr = (core_num == 0) ? 0x342 :
- 0x343;
- val_addr = (core_num == 0) ? 0x340 :
- 0x341;
- val_mask = (0x1 << 0);
- val_shift = 0;
- break;
- default:
- addr = 0xffff;
- break;
- }
- } else if (override_id == NPHY_REV7_RFCTRLOVERRIDE_ID2) {
-
- switch (field) {
- case (0x1 << 3):
- en_addr = (core_num == 0) ? 0x346 :
- 0x347;
- val_addr = (core_num == 0) ? 0x344 :
- 0x345;
- val_mask = (0x1 << 3);
- val_shift = 3;
- break;
- case (0x1 << 1):
- en_addr = (core_num == 0) ? 0x346 :
- 0x347;
- val_addr = (core_num == 0) ? 0x344 :
- 0x345;
- val_mask = (0x1 << 1);
- val_shift = 1;
- break;
- case (0x1 << 0):
- en_addr = (core_num == 0) ? 0x346 :
- 0x347;
- val_addr = (core_num == 0) ? 0x344 :
- 0x345;
- val_mask = (0x1 << 0);
- val_shift = 0;
- break;
- case (0x1 << 2):
- en_addr = (core_num == 0) ? 0x346 :
- 0x347;
- val_addr = (core_num == 0) ? 0x344 :
- 0x345;
- val_mask = (0x1 << 2);
- val_shift = 2;
- break;
- case (0x1 << 4):
- en_addr = (core_num == 0) ? 0x346 :
- 0x347;
- val_addr = (core_num == 0) ? 0x344 :
- 0x345;
- val_mask = (0x1 << 4);
- val_shift = 4;
- break;
- default:
- addr = 0xffff;
- break;
- }
- }
-
- if (off) {
- and_phy_reg(pi, en_addr, ~en_mask);
- and_phy_reg(pi, val_addr, ~val_mask);
- } else {
-
- if ((core_mask == 0)
- || (core_mask & (1 << core_num))) {
- or_phy_reg(pi, en_addr, en_mask);
-
- if (addr != 0xffff) {
- mod_phy_reg(pi, val_addr,
- val_mask,
- (value <<
- val_shift));
- }
- }
- }
- }
- }
-}
-
-static void
-wlc_phy_rfctrl_override_nphy(phy_info_t *pi, u16 field, u16 value,
- u8 core_mask, u8 off)
-{
- u8 core_num;
- u16 addr = 0, mask = 0, en_addr = 0, val_addr = 0, en_mask =
- 0, val_mask = 0;
- u8 shift = 0, val_shift = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3) && NREV_LT(pi->pubpi.phy_rev, 7)) {
-
- en_mask = field;
- for (core_num = 0; core_num < 2; core_num++) {
-
- switch (field) {
- case (0x1 << 1):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x1 << 0);
- val_shift = 0;
- break;
- case (0x1 << 2):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x1 << 1);
- val_shift = 1;
- break;
- case (0x1 << 3):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x1 << 2);
- val_shift = 2;
- break;
- case (0x1 << 4):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x1 << 4);
- val_shift = 4;
- break;
- case (0x1 << 5):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x1 << 5);
- val_shift = 5;
- break;
- case (0x1 << 6):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x1 << 6);
- val_shift = 6;
- break;
- case (0x1 << 7):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x1 << 7);
- val_shift = 7;
- break;
- case (0x1 << 8):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x7 << 8);
- val_shift = 8;
- break;
- case (0x1 << 11):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7a : 0x7d;
- val_mask = (0x7 << 13);
- val_shift = 13;
- break;
-
- case (0x1 << 9):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0xf8 : 0xfa;
- val_mask = (0x7 << 0);
- val_shift = 0;
- break;
-
- case (0x1 << 10):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0xf8 : 0xfa;
- val_mask = (0x7 << 4);
- val_shift = 4;
- break;
-
- case (0x1 << 12):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7b : 0x7e;
- val_mask = (0xffff << 0);
- val_shift = 0;
- break;
- case (0x1 << 13):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0x7c : 0x7f;
- val_mask = (0xffff << 0);
- val_shift = 0;
- break;
- case (0x1 << 14):
- en_addr = (core_num == 0) ? 0xe7 : 0xec;
- val_addr = (core_num == 0) ? 0xf9 : 0xfb;
- val_mask = (0x3 << 6);
- val_shift = 6;
- break;
- case (0x1 << 0):
- en_addr = (core_num == 0) ? 0xe5 : 0xe6;
- val_addr = (core_num == 0) ? 0xf9 : 0xfb;
- val_mask = (0x1 << 15);
- val_shift = 15;
- break;
- default:
- addr = 0xffff;
- break;
- }
-
- if (off) {
- and_phy_reg(pi, en_addr, ~en_mask);
- and_phy_reg(pi, val_addr, ~val_mask);
- } else {
-
- if ((core_mask == 0)
- || (core_mask & (1 << core_num))) {
- or_phy_reg(pi, en_addr, en_mask);
-
- if (addr != 0xffff) {
- mod_phy_reg(pi, val_addr,
- val_mask,
- (value <<
- val_shift));
- }
- }
- }
- }
- } else {
-
- if (off) {
- and_phy_reg(pi, 0xec, ~field);
- value = 0x0;
- } else {
- or_phy_reg(pi, 0xec, field);
- }
-
- for (core_num = 0; core_num < 2; core_num++) {
-
- switch (field) {
- case (0x1 << 1):
- case (0x1 << 9):
- case (0x1 << 12):
- case (0x1 << 13):
- case (0x1 << 14):
- addr = 0x78;
-
- core_mask = 0x1;
- break;
- case (0x1 << 2):
- case (0x1 << 3):
- case (0x1 << 4):
- case (0x1 << 5):
- case (0x1 << 6):
- case (0x1 << 7):
- case (0x1 << 8):
- addr = (core_num == 0) ? 0x7a : 0x7d;
- break;
- case (0x1 << 10):
- addr = (core_num == 0) ? 0x7b : 0x7e;
- break;
- case (0x1 << 11):
- addr = (core_num == 0) ? 0x7c : 0x7f;
- break;
- default:
- addr = 0xffff;
- }
-
- switch (field) {
- case (0x1 << 1):
- mask = (0x7 << 3);
- shift = 3;
- break;
- case (0x1 << 9):
- mask = (0x1 << 2);
- shift = 2;
- break;
- case (0x1 << 12):
- mask = (0x1 << 8);
- shift = 8;
- break;
- case (0x1 << 13):
- mask = (0x1 << 9);
- shift = 9;
- break;
- case (0x1 << 14):
- mask = (0xf << 12);
- shift = 12;
- break;
- case (0x1 << 2):
- mask = (0x1 << 0);
- shift = 0;
- break;
- case (0x1 << 3):
- mask = (0x1 << 1);
- shift = 1;
- break;
- case (0x1 << 4):
- mask = (0x1 << 2);
- shift = 2;
- break;
- case (0x1 << 5):
- mask = (0x3 << 4);
- shift = 4;
- break;
- case (0x1 << 6):
- mask = (0x3 << 6);
- shift = 6;
- break;
- case (0x1 << 7):
- mask = (0x1 << 8);
- shift = 8;
- break;
- case (0x1 << 8):
- mask = (0x1 << 9);
- shift = 9;
- break;
- case (0x1 << 10):
- mask = 0x1fff;
- shift = 0x0;
- break;
- case (0x1 << 11):
- mask = 0x1fff;
- shift = 0x0;
- break;
- default:
- mask = 0x0;
- shift = 0x0;
- break;
- }
-
- if ((addr != 0xffff) && (core_mask & (1 << core_num))) {
- mod_phy_reg(pi, addr, mask, (value << shift));
- }
- }
-
- or_phy_reg(pi, 0xec, (0x1 << 0));
- or_phy_reg(pi, 0x78, (0x1 << 0));
- udelay(1);
- and_phy_reg(pi, 0xec, ~(0x1 << 0));
- }
-}
-
-static void
-wlc_phy_rfctrl_override_1tomany_nphy(phy_info_t *pi, u16 cmd, u16 value,
- u8 core_mask, u8 off)
-{
- u16 rfmxgain = 0, lpfgain = 0;
- u16 tgain = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- switch (cmd) {
- case NPHY_REV7_RfctrlOverride_cmd_rxrf_pu:
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5),
- value, core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), value,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), value,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- break;
- case NPHY_REV7_RfctrlOverride_cmd_rx_pu:
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
- value, core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), value,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), value,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), value,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- break;
- case NPHY_REV7_RfctrlOverride_cmd_tx_pu:
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
- value, core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), value,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), value,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), value,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 1,
- core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- break;
- case NPHY_REV7_RfctrlOverride_cmd_rxgain:
- rfmxgain = value & 0x000ff;
- lpfgain = value & 0x0ff00;
- lpfgain = lpfgain >> 8;
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11),
- rfmxgain, core_mask,
- off,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x3 << 13),
- lpfgain, core_mask,
- off,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- break;
- case NPHY_REV7_RfctrlOverride_cmd_txgain:
- tgain = value & 0x7fff;
- lpfgain = value & 0x8000;
- lpfgain = lpfgain >> 14;
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
- tgain, core_mask, off,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 13),
- lpfgain, core_mask,
- off,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- break;
- }
- }
-}
-
-static void
-wlc_phy_scale_offset_rssi_nphy(phy_info_t *pi, u16 scale, s8 offset,
- u8 coresel, u8 rail, u8 rssi_type)
-{
- u16 valuetostuff;
-
- offset = (offset > NPHY_RSSICAL_MAXREAD) ?
- NPHY_RSSICAL_MAXREAD : offset;
- offset = (offset < (-NPHY_RSSICAL_MAXREAD - 1)) ?
- -NPHY_RSSICAL_MAXREAD - 1 : offset;
-
- valuetostuff = ((scale & 0x3f) << 8) | (offset & 0x3f);
-
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_NB)) {
- write_phy_reg(pi, 0x1a6, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_NB)) {
- write_phy_reg(pi, 0x1ac, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_NB)) {
- write_phy_reg(pi, 0x1b2, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_NB)) {
- write_phy_reg(pi, 0x1b8, valuetostuff);
- }
-
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W1)) {
- write_phy_reg(pi, 0x1a4, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W1)) {
- write_phy_reg(pi, 0x1aa, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W1)) {
- write_phy_reg(pi, 0x1b0, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W1)) {
- write_phy_reg(pi, 0x1b6, valuetostuff);
- }
-
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W2)) {
- write_phy_reg(pi, 0x1a5, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W2)) {
- write_phy_reg(pi, 0x1ab, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_W2)) {
- write_phy_reg(pi, 0x1b1, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_W2)) {
- write_phy_reg(pi, 0x1b7, valuetostuff);
- }
-
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_TBD)) {
- write_phy_reg(pi, 0x1a7, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_TBD)) {
- write_phy_reg(pi, 0x1ad, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_TBD)) {
- write_phy_reg(pi, 0x1b3, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_TBD)) {
- write_phy_reg(pi, 0x1b9, valuetostuff);
- }
-
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_IQ)) {
- write_phy_reg(pi, 0x1a8, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_IQ)) {
- write_phy_reg(pi, 0x1ae, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_I) && (rssi_type == NPHY_RSSI_SEL_IQ)) {
- write_phy_reg(pi, 0x1b4, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rail == NPHY_RAIL_Q) && (rssi_type == NPHY_RSSI_SEL_IQ)) {
- write_phy_reg(pi, 0x1ba, valuetostuff);
- }
-
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rssi_type == NPHY_RSSI_SEL_TSSI_2G)) {
- write_phy_reg(pi, 0x1a9, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rssi_type == NPHY_RSSI_SEL_TSSI_2G)) {
- write_phy_reg(pi, 0x1b5, valuetostuff);
- }
-
- if (((coresel == RADIO_MIMO_CORESEL_CORE1) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rssi_type == NPHY_RSSI_SEL_TSSI_5G)) {
- write_phy_reg(pi, 0x1af, valuetostuff);
- }
- if (((coresel == RADIO_MIMO_CORESEL_CORE2) ||
- (coresel == RADIO_MIMO_CORESEL_ALLRX)) &&
- (rssi_type == NPHY_RSSI_SEL_TSSI_5G)) {
- write_phy_reg(pi, 0x1bb, valuetostuff);
- }
-}
-
-void wlc_phy_rssisel_nphy(phy_info_t *pi, u8 core_code, u8 rssi_type)
-{
- u16 mask, val;
- u16 afectrlovr_rssi_val, rfctrlcmd_rxen_val, rfctrlcmd_coresel_val,
- startseq;
- u16 rfctrlovr_rssi_val, rfctrlovr_rxen_val, rfctrlovr_coresel_val,
- rfctrlovr_trigger_val;
- u16 afectrlovr_rssi_mask, rfctrlcmd_mask, rfctrlovr_mask;
- u16 rfctrlcmd_val, rfctrlovr_val;
- u8 core;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (core_code == RADIO_MIMO_CORESEL_OFF) {
- mod_phy_reg(pi, 0x8f, (0x1 << 9), 0);
- mod_phy_reg(pi, 0xa5, (0x1 << 9), 0);
-
- mod_phy_reg(pi, 0xa6, (0x3 << 8), 0);
- mod_phy_reg(pi, 0xa7, (0x3 << 8), 0);
-
- mod_phy_reg(pi, 0xe5, (0x1 << 5), 0);
- mod_phy_reg(pi, 0xe6, (0x1 << 5), 0);
-
- mask = (0x1 << 2) |
- (0x1 << 3) | (0x1 << 4) | (0x1 << 5);
- mod_phy_reg(pi, 0xf9, mask, 0);
- mod_phy_reg(pi, 0xfb, mask, 0);
-
- } else {
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- if (core_code == RADIO_MIMO_CORESEL_CORE1
- && core == PHY_CORE_1)
- continue;
- else if (core_code == RADIO_MIMO_CORESEL_CORE2
- && core == PHY_CORE_0)
- continue;
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ?
- 0x8f : 0xa5, (0x1 << 9), 1 << 9);
-
- if (rssi_type == NPHY_RSSI_SEL_W1 ||
- rssi_type == NPHY_RSSI_SEL_W2 ||
- rssi_type == NPHY_RSSI_SEL_NB) {
-
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xa6 : 0xa7,
- (0x3 << 8), 0);
-
- mask = (0x1 << 2) |
- (0x1 << 3) |
- (0x1 << 4) | (0x1 << 5);
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xf9 : 0xfb,
- mask, 0);
-
- if (rssi_type == NPHY_RSSI_SEL_W1) {
- if (CHSPEC_IS5G
- (pi->radio_chanspec)) {
- mask = (0x1 << 2);
- val = 1 << 2;
- } else {
- mask = (0x1 << 3);
- val = 1 << 3;
- }
- } else if (rssi_type ==
- NPHY_RSSI_SEL_W2) {
- mask = (0x1 << 4);
- val = 1 << 4;
- } else {
- mask = (0x1 << 5);
- val = 1 << 5;
- }
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xf9 : 0xfb,
- mask, val);
-
- mask = (0x1 << 5);
- val = 1 << 5;
- mod_phy_reg(pi, (core == PHY_CORE_0) ?
- 0xe5 : 0xe6, mask, val);
- } else {
- if (rssi_type == NPHY_RSSI_SEL_TBD) {
-
- mask = (0x3 << 8);
- val = 1 << 8;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xa6
- : 0xa7, mask, val);
- mask = (0x3 << 10);
- val = 1 << 10;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xa6
- : 0xa7, mask, val);
- } else if (rssi_type ==
- NPHY_RSSI_SEL_IQ) {
-
- mask = (0x3 << 8);
- val = 2 << 8;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xa6
- : 0xa7, mask, val);
- mask = (0x3 << 10);
- val = 2 << 10;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xa6
- : 0xa7, mask, val);
- } else {
-
- mask = (0x3 << 8);
- val = 3 << 8;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xa6
- : 0xa7, mask, val);
- mask = (0x3 << 10);
- val = 3 << 10;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xa6
- : 0xa7, mask, val);
-
- if (PHY_IPA(pi)) {
- if (NREV_GE
- (pi->pubpi.phy_rev,
- 7)) {
-
- write_radio_reg
- (pi,
- ((core ==
- PHY_CORE_0)
- ?
- RADIO_2057_TX0_TX_SSI_MUX
- :
- RADIO_2057_TX1_TX_SSI_MUX),
- (CHSPEC_IS5G
- (pi->
- radio_chanspec)
- ? 0xc :
- 0xe));
- } else {
- write_radio_reg
- (pi,
- RADIO_2056_TX_TX_SSI_MUX
- |
- ((core ==
- PHY_CORE_0)
- ?
- RADIO_2056_TX0
- :
- RADIO_2056_TX1),
- (CHSPEC_IS5G
- (pi->
- radio_chanspec)
- ? 0xc :
- 0xe));
- }
- } else {
-
- if (NREV_GE
- (pi->pubpi.phy_rev,
- 7)) {
- write_radio_reg
- (pi,
- ((core ==
- PHY_CORE_0)
- ?
- RADIO_2057_TX0_TX_SSI_MUX
- :
- RADIO_2057_TX1_TX_SSI_MUX),
- 0x11);
-
- if (pi->pubpi.
- radioid ==
- BCM2057_ID)
- write_radio_reg
- (pi,
- RADIO_2057_IQTEST_SEL_PU,
- 0x1);
-
- } else {
- write_radio_reg
- (pi,
- RADIO_2056_TX_TX_SSI_MUX
- |
- ((core ==
- PHY_CORE_0)
- ?
- RADIO_2056_TX0
- :
- RADIO_2056_TX1),
- 0x11);
- }
- }
-
- afectrlovr_rssi_val = 1 << 9;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x8f
- : 0xa5, (0x1 << 9),
- afectrlovr_rssi_val);
- }
- }
- }
- }
- } else {
-
- if ((rssi_type == NPHY_RSSI_SEL_W1) ||
- (rssi_type == NPHY_RSSI_SEL_W2) ||
- (rssi_type == NPHY_RSSI_SEL_NB)) {
-
- val = 0x0;
- } else if (rssi_type == NPHY_RSSI_SEL_TBD) {
-
- val = 0x1;
- } else if (rssi_type == NPHY_RSSI_SEL_IQ) {
-
- val = 0x2;
- } else {
-
- val = 0x3;
- }
- mask = ((0x3 << 12) | (0x3 << 14));
- val = (val << 12) | (val << 14);
- mod_phy_reg(pi, 0xa6, mask, val);
- mod_phy_reg(pi, 0xa7, mask, val);
-
- if ((rssi_type == NPHY_RSSI_SEL_W1) ||
- (rssi_type == NPHY_RSSI_SEL_W2) ||
- (rssi_type == NPHY_RSSI_SEL_NB)) {
- if (rssi_type == NPHY_RSSI_SEL_W1) {
- val = 0x1;
- }
- if (rssi_type == NPHY_RSSI_SEL_W2) {
- val = 0x2;
- }
- if (rssi_type == NPHY_RSSI_SEL_NB) {
- val = 0x3;
- }
- mask = (0x3 << 4);
- val = (val << 4);
- mod_phy_reg(pi, 0x7a, mask, val);
- mod_phy_reg(pi, 0x7d, mask, val);
- }
-
- if (core_code == RADIO_MIMO_CORESEL_OFF) {
- afectrlovr_rssi_val = 0;
- rfctrlcmd_rxen_val = 0;
- rfctrlcmd_coresel_val = 0;
- rfctrlovr_rssi_val = 0;
- rfctrlovr_rxen_val = 0;
- rfctrlovr_coresel_val = 0;
- rfctrlovr_trigger_val = 0;
- startseq = 0;
- } else {
- afectrlovr_rssi_val = 1;
- rfctrlcmd_rxen_val = 1;
- rfctrlcmd_coresel_val = core_code;
- rfctrlovr_rssi_val = 1;
- rfctrlovr_rxen_val = 1;
- rfctrlovr_coresel_val = 1;
- rfctrlovr_trigger_val = 1;
- startseq = 1;
- }
-
- afectrlovr_rssi_mask = ((0x1 << 12) | (0x1 << 13));
- afectrlovr_rssi_val = (afectrlovr_rssi_val <<
- 12) | (afectrlovr_rssi_val << 13);
- mod_phy_reg(pi, 0xa5, afectrlovr_rssi_mask,
- afectrlovr_rssi_val);
-
- if ((rssi_type == NPHY_RSSI_SEL_W1) ||
- (rssi_type == NPHY_RSSI_SEL_W2) ||
- (rssi_type == NPHY_RSSI_SEL_NB)) {
- rfctrlcmd_mask = ((0x1 << 8) | (0x7 << 3));
- rfctrlcmd_val = (rfctrlcmd_rxen_val << 8) |
- (rfctrlcmd_coresel_val << 3);
-
- rfctrlovr_mask = ((0x1 << 5) |
- (0x1 << 12) |
- (0x1 << 1) | (0x1 << 0));
- rfctrlovr_val = (rfctrlovr_rssi_val <<
- 5) |
- (rfctrlovr_rxen_val << 12) |
- (rfctrlovr_coresel_val << 1) |
- (rfctrlovr_trigger_val << 0);
-
- mod_phy_reg(pi, 0x78, rfctrlcmd_mask, rfctrlcmd_val);
- mod_phy_reg(pi, 0xec, rfctrlovr_mask, rfctrlovr_val);
-
- mod_phy_reg(pi, 0x78, (0x1 << 0), (startseq << 0));
- udelay(20);
-
- mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
- }
- }
-}
-
-int
-wlc_phy_poll_rssi_nphy(phy_info_t *pi, u8 rssi_type, s32 *rssi_buf,
- u8 nsamps)
-{
- s16 rssi0, rssi1;
- u16 afectrlCore1_save = 0;
- u16 afectrlCore2_save = 0;
- u16 afectrlOverride1_save = 0;
- u16 afectrlOverride2_save = 0;
- u16 rfctrlOverrideAux0_save = 0;
- u16 rfctrlOverrideAux1_save = 0;
- u16 rfctrlMiscReg1_save = 0;
- u16 rfctrlMiscReg2_save = 0;
- u16 rfctrlcmd_save = 0;
- u16 rfctrloverride_save = 0;
- u16 rfctrlrssiothers1_save = 0;
- u16 rfctrlrssiothers2_save = 0;
- s8 tmp_buf[4];
- u8 ctr = 0, samp = 0;
- s32 rssi_out_val;
- u16 gpiosel_orig;
-
- afectrlCore1_save = read_phy_reg(pi, 0xa6);
- afectrlCore2_save = read_phy_reg(pi, 0xa7);
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- rfctrlMiscReg1_save = read_phy_reg(pi, 0xf9);
- rfctrlMiscReg2_save = read_phy_reg(pi, 0xfb);
- afectrlOverride1_save = read_phy_reg(pi, 0x8f);
- afectrlOverride2_save = read_phy_reg(pi, 0xa5);
- rfctrlOverrideAux0_save = read_phy_reg(pi, 0xe5);
- rfctrlOverrideAux1_save = read_phy_reg(pi, 0xe6);
- } else {
- afectrlOverride1_save = read_phy_reg(pi, 0xa5);
- rfctrlcmd_save = read_phy_reg(pi, 0x78);
- rfctrloverride_save = read_phy_reg(pi, 0xec);
- rfctrlrssiothers1_save = read_phy_reg(pi, 0x7a);
- rfctrlrssiothers2_save = read_phy_reg(pi, 0x7d);
- }
-
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_ALLRX, rssi_type);
-
- gpiosel_orig = read_phy_reg(pi, 0xca);
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
- write_phy_reg(pi, 0xca, 5);
- }
-
- for (ctr = 0; ctr < 4; ctr++) {
- rssi_buf[ctr] = 0;
- }
-
- for (samp = 0; samp < nsamps; samp++) {
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
- rssi0 = read_phy_reg(pi, 0x1c9);
- rssi1 = read_phy_reg(pi, 0x1ca);
- } else {
- rssi0 = read_phy_reg(pi, 0x219);
- rssi1 = read_phy_reg(pi, 0x21a);
- }
-
- ctr = 0;
- tmp_buf[ctr++] = ((s8) ((rssi0 & 0x3f) << 2)) >> 2;
- tmp_buf[ctr++] = ((s8) (((rssi0 >> 8) & 0x3f) << 2)) >> 2;
- tmp_buf[ctr++] = ((s8) ((rssi1 & 0x3f) << 2)) >> 2;
- tmp_buf[ctr++] = ((s8) (((rssi1 >> 8) & 0x3f) << 2)) >> 2;
-
- for (ctr = 0; ctr < 4; ctr++) {
- rssi_buf[ctr] += tmp_buf[ctr];
- }
-
- }
-
- rssi_out_val = rssi_buf[3] & 0xff;
- rssi_out_val |= (rssi_buf[2] & 0xff) << 8;
- rssi_out_val |= (rssi_buf[1] & 0xff) << 16;
- rssi_out_val |= (rssi_buf[0] & 0xff) << 24;
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
- write_phy_reg(pi, 0xca, gpiosel_orig);
- }
-
- write_phy_reg(pi, 0xa6, afectrlCore1_save);
- write_phy_reg(pi, 0xa7, afectrlCore2_save);
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- write_phy_reg(pi, 0xf9, rfctrlMiscReg1_save);
- write_phy_reg(pi, 0xfb, rfctrlMiscReg2_save);
- write_phy_reg(pi, 0x8f, afectrlOverride1_save);
- write_phy_reg(pi, 0xa5, afectrlOverride2_save);
- write_phy_reg(pi, 0xe5, rfctrlOverrideAux0_save);
- write_phy_reg(pi, 0xe6, rfctrlOverrideAux1_save);
- } else {
- write_phy_reg(pi, 0xa5, afectrlOverride1_save);
- write_phy_reg(pi, 0x78, rfctrlcmd_save);
- write_phy_reg(pi, 0xec, rfctrloverride_save);
- write_phy_reg(pi, 0x7a, rfctrlrssiothers1_save);
- write_phy_reg(pi, 0x7d, rfctrlrssiothers2_save);
- }
-
- return rssi_out_val;
-}
-
-s16 wlc_phy_tempsense_nphy(phy_info_t *pi)
-{
- u16 core1_txrf_iqcal1_save, core1_txrf_iqcal2_save;
- u16 core2_txrf_iqcal1_save, core2_txrf_iqcal2_save;
- u16 pwrdet_rxtx_core1_save;
- u16 pwrdet_rxtx_core2_save;
- u16 afectrlCore1_save;
- u16 afectrlCore2_save;
- u16 afectrlOverride_save;
- u16 afectrlOverride2_save;
- u16 pd_pll_ts_save;
- u16 gpioSel_save;
- s32 radio_temp[4];
- s32 radio_temp2[4];
- u16 syn_tempprocsense_save;
- s16 offset = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- u16 auxADC_Vmid, auxADC_Av, auxADC_Vmid_save, auxADC_Av_save;
- u16 auxADC_rssi_ctrlL_save, auxADC_rssi_ctrlH_save;
- u16 auxADC_rssi_ctrlL, auxADC_rssi_ctrlH;
- s32 auxADC_Vl;
- u16 RfctrlOverride5_save, RfctrlOverride6_save;
- u16 RfctrlMiscReg5_save, RfctrlMiscReg6_save;
- u16 RSSIMultCoef0QPowerDet_save;
- u16 tempsense_Rcal;
-
- syn_tempprocsense_save =
- read_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG);
-
- afectrlCore1_save = read_phy_reg(pi, 0xa6);
- afectrlCore2_save = read_phy_reg(pi, 0xa7);
- afectrlOverride_save = read_phy_reg(pi, 0x8f);
- afectrlOverride2_save = read_phy_reg(pi, 0xa5);
- RSSIMultCoef0QPowerDet_save = read_phy_reg(pi, 0x1ae);
- RfctrlOverride5_save = read_phy_reg(pi, 0x346);
- RfctrlOverride6_save = read_phy_reg(pi, 0x347);
- RfctrlMiscReg5_save = read_phy_reg(pi, 0x344);
- RfctrlMiscReg6_save = read_phy_reg(pi, 0x345);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
- &auxADC_Vmid_save);
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
- &auxADC_Av_save);
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
- &auxADC_rssi_ctrlL_save);
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
- &auxADC_rssi_ctrlH_save);
-
- write_phy_reg(pi, 0x1ae, 0x0);
-
- auxADC_rssi_ctrlL = 0x0;
- auxADC_rssi_ctrlH = 0x20;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
- &auxADC_rssi_ctrlL);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
- &auxADC_rssi_ctrlH);
-
- tempsense_Rcal = syn_tempprocsense_save & 0x1c;
-
- write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
- tempsense_Rcal | 0x01);
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1),
- 1, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- mod_phy_reg(pi, 0xa6, (0x1 << 7), 0);
- mod_phy_reg(pi, 0xa7, (0x1 << 7), 0);
- mod_phy_reg(pi, 0x8f, (0x1 << 7), (0x1 << 7));
- mod_phy_reg(pi, 0xa5, (0x1 << 7), (0x1 << 7));
-
- mod_phy_reg(pi, 0xa6, (0x1 << 2), (0x1 << 2));
- mod_phy_reg(pi, 0xa7, (0x1 << 2), (0x1 << 2));
- mod_phy_reg(pi, 0x8f, (0x1 << 2), (0x1 << 2));
- mod_phy_reg(pi, 0xa5, (0x1 << 2), (0x1 << 2));
- udelay(5);
- mod_phy_reg(pi, 0xa6, (0x1 << 2), 0);
- mod_phy_reg(pi, 0xa7, (0x1 << 2), 0);
- mod_phy_reg(pi, 0xa6, (0x1 << 3), 0);
- mod_phy_reg(pi, 0xa7, (0x1 << 3), 0);
- mod_phy_reg(pi, 0x8f, (0x1 << 3), (0x1 << 3));
- mod_phy_reg(pi, 0xa5, (0x1 << 3), (0x1 << 3));
- mod_phy_reg(pi, 0xa6, (0x1 << 6), 0);
- mod_phy_reg(pi, 0xa7, (0x1 << 6), 0);
- mod_phy_reg(pi, 0x8f, (0x1 << 6), (0x1 << 6));
- mod_phy_reg(pi, 0xa5, (0x1 << 6), (0x1 << 6));
-
- auxADC_Vmid = 0xA3;
- auxADC_Av = 0x0;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
- &auxADC_Vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
- &auxADC_Av);
-
- udelay(3);
-
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
- write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
- tempsense_Rcal | 0x03);
-
- udelay(5);
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
-
- auxADC_Av = 0x7;
- if (radio_temp[1] + radio_temp2[1] < -30) {
- auxADC_Vmid = 0x45;
- auxADC_Vl = 263;
- } else if (radio_temp[1] + radio_temp2[1] < -9) {
- auxADC_Vmid = 0x200;
- auxADC_Vl = 467;
- } else if (radio_temp[1] + radio_temp2[1] < 11) {
- auxADC_Vmid = 0x266;
- auxADC_Vl = 634;
- } else {
- auxADC_Vmid = 0x2D5;
- auxADC_Vl = 816;
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
- &auxADC_Vmid);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
- &auxADC_Av);
-
- udelay(3);
-
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
- write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
- tempsense_Rcal | 0x01);
-
- udelay(5);
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
-
- write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG,
- syn_tempprocsense_save);
-
- write_phy_reg(pi, 0xa6, afectrlCore1_save);
- write_phy_reg(pi, 0xa7, afectrlCore2_save);
- write_phy_reg(pi, 0x8f, afectrlOverride_save);
- write_phy_reg(pi, 0xa5, afectrlOverride2_save);
- write_phy_reg(pi, 0x1ae, RSSIMultCoef0QPowerDet_save);
- write_phy_reg(pi, 0x346, RfctrlOverride5_save);
- write_phy_reg(pi, 0x347, RfctrlOverride6_save);
- write_phy_reg(pi, 0x344, RfctrlMiscReg5_save);
- write_phy_reg(pi, 0x345, RfctrlMiscReg5_save);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0A, 16,
- &auxADC_Vmid_save);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x0E, 16,
- &auxADC_Av_save);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x02, 16,
- &auxADC_rssi_ctrlL_save);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
- &auxADC_rssi_ctrlH_save);
-
- if (pi->sh->chip == BCM5357_CHIP_ID) {
- radio_temp[0] = (193 * (radio_temp[1] + radio_temp2[1])
- + 88 * (auxADC_Vl) - 27111 +
- 128) / 256;
- } else if (pi->sh->chip == BCM43236_CHIP_ID) {
- radio_temp[0] = (198 * (radio_temp[1] + radio_temp2[1])
- + 91 * (auxADC_Vl) - 27243 +
- 128) / 256;
- } else {
- radio_temp[0] = (179 * (radio_temp[1] + radio_temp2[1])
- + 82 * (auxADC_Vl) - 28861 +
- 128) / 256;
- }
-
- offset = (s16) pi->phy_tempsense_offset;
-
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- syn_tempprocsense_save =
- read_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE);
-
- afectrlCore1_save = read_phy_reg(pi, 0xa6);
- afectrlCore2_save = read_phy_reg(pi, 0xa7);
- afectrlOverride_save = read_phy_reg(pi, 0x8f);
- afectrlOverride2_save = read_phy_reg(pi, 0xa5);
- gpioSel_save = read_phy_reg(pi, 0xca);
-
- write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x01);
-
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- } else {
- write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x05);
- }
-
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- write_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG, 0x01);
- } else {
- write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE, 0x01);
- }
-
- radio_temp[0] =
- (126 * (radio_temp[1] + radio_temp2[1]) + 3987) / 64;
-
- write_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE,
- syn_tempprocsense_save);
-
- write_phy_reg(pi, 0xca, gpioSel_save);
- write_phy_reg(pi, 0xa6, afectrlCore1_save);
- write_phy_reg(pi, 0xa7, afectrlCore2_save);
- write_phy_reg(pi, 0x8f, afectrlOverride_save);
- write_phy_reg(pi, 0xa5, afectrlOverride2_save);
-
- offset = (s16) pi->phy_tempsense_offset;
- } else {
-
- pwrdet_rxtx_core1_save =
- read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
- pwrdet_rxtx_core2_save =
- read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
- core1_txrf_iqcal1_save =
- read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
- core1_txrf_iqcal2_save =
- read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
- core2_txrf_iqcal1_save =
- read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
- core2_txrf_iqcal2_save =
- read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
- pd_pll_ts_save = read_radio_reg(pi, RADIO_2055_PD_PLL_TS);
-
- afectrlCore1_save = read_phy_reg(pi, 0xa6);
- afectrlCore2_save = read_phy_reg(pi, 0xa7);
- afectrlOverride_save = read_phy_reg(pi, 0xa5);
- gpioSel_save = read_phy_reg(pi, 0xca);
-
- write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1, 0x01);
- write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1, 0x01);
- write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2, 0x08);
- write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2, 0x08);
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x04);
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x04);
- write_radio_reg(pi, RADIO_2055_PD_PLL_TS, 0x00);
-
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
- xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
-
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp, 1);
- xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
-
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_IQ, radio_temp2, 1);
- xor_radio_reg(pi, RADIO_2055_CAL_TS, 0x80);
-
- radio_temp[0] = (radio_temp[0] + radio_temp2[0]);
- radio_temp[1] = (radio_temp[1] + radio_temp2[1]);
- radio_temp[2] = (radio_temp[2] + radio_temp2[2]);
- radio_temp[3] = (radio_temp[3] + radio_temp2[3]);
-
- radio_temp[0] =
- (radio_temp[0] + radio_temp[1] + radio_temp[2] +
- radio_temp[3]);
-
- radio_temp[0] =
- (radio_temp[0] + (8 * 32)) * (950 - 350) / 63 + (350 * 8);
-
- radio_temp[0] = (radio_temp[0] - (8 * 420)) / 38;
-
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1,
- pwrdet_rxtx_core1_save);
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2,
- pwrdet_rxtx_core2_save);
- write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1,
- core1_txrf_iqcal1_save);
- write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1,
- core2_txrf_iqcal1_save);
- write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2,
- core1_txrf_iqcal2_save);
- write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2,
- core2_txrf_iqcal2_save);
- write_radio_reg(pi, RADIO_2055_PD_PLL_TS, pd_pll_ts_save);
-
- write_phy_reg(pi, 0xca, gpioSel_save);
- write_phy_reg(pi, 0xa6, afectrlCore1_save);
- write_phy_reg(pi, 0xa7, afectrlCore2_save);
- write_phy_reg(pi, 0xa5, afectrlOverride_save);
- }
-
- return (s16) radio_temp[0] + offset;
-}
-
-static void
-wlc_phy_set_rssi_2055_vcm(phy_info_t *pi, u8 rssi_type, u8 *vcm_buf)
-{
- u8 core;
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- if (rssi_type == NPHY_RSSI_SEL_NB) {
- if (core == PHY_CORE_0) {
- mod_radio_reg(pi,
- RADIO_2055_CORE1_B0_NBRSSI_VCM,
- RADIO_2055_NBRSSI_VCM_I_MASK,
- vcm_buf[2 *
- core] <<
- RADIO_2055_NBRSSI_VCM_I_SHIFT);
- mod_radio_reg(pi,
- RADIO_2055_CORE1_RXBB_RSSI_CTRL5,
- RADIO_2055_NBRSSI_VCM_Q_MASK,
- vcm_buf[2 * core +
- 1] <<
- RADIO_2055_NBRSSI_VCM_Q_SHIFT);
- } else {
- mod_radio_reg(pi,
- RADIO_2055_CORE2_B0_NBRSSI_VCM,
- RADIO_2055_NBRSSI_VCM_I_MASK,
- vcm_buf[2 *
- core] <<
- RADIO_2055_NBRSSI_VCM_I_SHIFT);
- mod_radio_reg(pi,
- RADIO_2055_CORE2_RXBB_RSSI_CTRL5,
- RADIO_2055_NBRSSI_VCM_Q_MASK,
- vcm_buf[2 * core +
- 1] <<
- RADIO_2055_NBRSSI_VCM_Q_SHIFT);
- }
- } else {
-
- if (core == PHY_CORE_0) {
- mod_radio_reg(pi,
- RADIO_2055_CORE1_RXBB_RSSI_CTRL5,
- RADIO_2055_WBRSSI_VCM_IQ_MASK,
- vcm_buf[2 *
- core] <<
- RADIO_2055_WBRSSI_VCM_IQ_SHIFT);
- } else {
- mod_radio_reg(pi,
- RADIO_2055_CORE2_RXBB_RSSI_CTRL5,
- RADIO_2055_WBRSSI_VCM_IQ_MASK,
- vcm_buf[2 *
- core] <<
- RADIO_2055_WBRSSI_VCM_IQ_SHIFT);
- }
- }
- }
-}
-
-void wlc_phy_rssi_cal_nphy(phy_info_t *pi)
-{
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- wlc_phy_rssi_cal_nphy_rev3(pi);
- } else {
- wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_NB);
- wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_W1);
- wlc_phy_rssi_cal_nphy_rev2(pi, NPHY_RSSI_SEL_W2);
- }
-}
-
-static void wlc_phy_rssi_cal_nphy_rev2(phy_info_t *pi, u8 rssi_type)
-{
- s32 target_code;
- u16 classif_state;
- u16 clip_state[2];
- u16 rssi_ctrl_state[2], pd_state[2];
- u16 rfctrlintc_state[2], rfpdcorerxtx_state[2];
- u16 rfctrlintc_override_val;
- u16 clip_off[] = { 0xffff, 0xffff };
- u16 rf_pd_val, pd_mask, rssi_ctrl_mask;
- u8 vcm, min_vcm, vcm_tmp[4];
- u8 vcm_final[4] = { 0, 0, 0, 0 };
- u8 result_idx, ctr;
- s32 poll_results[4][4] = {
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0}
- };
- s32 poll_miniq[4][2] = {
- {0, 0},
- {0, 0},
- {0, 0},
- {0, 0}
- };
- s32 min_d, curr_d;
- s32 fine_digital_offset[4];
- s32 poll_results_min[4] = { 0, 0, 0, 0 };
- s32 min_poll;
-
- switch (rssi_type) {
- case NPHY_RSSI_SEL_NB:
- target_code = NPHY_RSSICAL_NB_TARGET;
- break;
- case NPHY_RSSI_SEL_W1:
- target_code = NPHY_RSSICAL_W1_TARGET;
- break;
- case NPHY_RSSI_SEL_W2:
- target_code = NPHY_RSSICAL_W2_TARGET;
- break;
- default:
- return;
- break;
- }
-
- classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
- wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
- wlc_phy_clip_det_nphy(pi, 0, clip_state);
- wlc_phy_clip_det_nphy(pi, 1, clip_off);
-
- rf_pd_val = (rssi_type == NPHY_RSSI_SEL_NB) ? 0x6 : 0x4;
- rfctrlintc_override_val =
- CHSPEC_IS5G(pi->radio_chanspec) ? 0x140 : 0x110;
-
- rfctrlintc_state[0] = read_phy_reg(pi, 0x91);
- rfpdcorerxtx_state[0] = read_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX);
- write_phy_reg(pi, 0x91, rfctrlintc_override_val);
- write_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX, rf_pd_val);
-
- rfctrlintc_state[1] = read_phy_reg(pi, 0x92);
- rfpdcorerxtx_state[1] = read_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX);
- write_phy_reg(pi, 0x92, rfctrlintc_override_val);
- write_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX, rf_pd_val);
-
- pd_mask = RADIO_2055_NBRSSI_PD | RADIO_2055_WBRSSI_G1_PD |
- RADIO_2055_WBRSSI_G2_PD;
- pd_state[0] =
- read_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC) & pd_mask;
- pd_state[1] =
- read_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC) & pd_mask;
- mod_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC, pd_mask, 0);
- mod_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC, pd_mask, 0);
- rssi_ctrl_mask = RADIO_2055_NBRSSI_SEL | RADIO_2055_WBRSSI_G1_SEL |
- RADIO_2055_WBRSSI_G2_SEL;
- rssi_ctrl_state[0] =
- read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE1) & rssi_ctrl_mask;
- rssi_ctrl_state[1] =
- read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE2) & rssi_ctrl_mask;
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_ALLRX, rssi_type);
-
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0, RADIO_MIMO_CORESEL_ALLRX,
- NPHY_RAIL_I, rssi_type);
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0, RADIO_MIMO_CORESEL_ALLRX,
- NPHY_RAIL_Q, rssi_type);
-
- for (vcm = 0; vcm < 4; vcm++) {
-
- vcm_tmp[0] = vcm_tmp[1] = vcm_tmp[2] = vcm_tmp[3] = vcm;
- if (rssi_type != NPHY_RSSI_SEL_W2) {
- wlc_phy_set_rssi_2055_vcm(pi, rssi_type, vcm_tmp);
- }
-
- wlc_phy_poll_rssi_nphy(pi, rssi_type, &poll_results[vcm][0],
- NPHY_RSSICAL_NPOLL);
-
- if ((rssi_type == NPHY_RSSI_SEL_W1)
- || (rssi_type == NPHY_RSSI_SEL_W2)) {
- for (ctr = 0; ctr < 2; ctr++) {
- poll_miniq[vcm][ctr] =
- min(poll_results[vcm][ctr * 2 + 0],
- poll_results[vcm][ctr * 2 + 1]);
- }
- }
- }
-
- for (result_idx = 0; result_idx < 4; result_idx++) {
- min_d = NPHY_RSSICAL_MAXD;
- min_vcm = 0;
- min_poll = NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL + 1;
- for (vcm = 0; vcm < 4; vcm++) {
- curr_d = ABS(((rssi_type == NPHY_RSSI_SEL_NB) ?
- poll_results[vcm][result_idx] :
- poll_miniq[vcm][result_idx / 2]) -
- (target_code * NPHY_RSSICAL_NPOLL));
- if (curr_d < min_d) {
- min_d = curr_d;
- min_vcm = vcm;
- }
- if (poll_results[vcm][result_idx] < min_poll) {
- min_poll = poll_results[vcm][result_idx];
- }
- }
- vcm_final[result_idx] = min_vcm;
- poll_results_min[result_idx] = min_poll;
- }
-
- if (rssi_type != NPHY_RSSI_SEL_W2) {
- wlc_phy_set_rssi_2055_vcm(pi, rssi_type, vcm_final);
- }
-
- for (result_idx = 0; result_idx < 4; result_idx++) {
- fine_digital_offset[result_idx] =
- (target_code * NPHY_RSSICAL_NPOLL) -
- poll_results[vcm_final[result_idx]][result_idx];
- if (fine_digital_offset[result_idx] < 0) {
- fine_digital_offset[result_idx] =
- ABS(fine_digital_offset[result_idx]);
- fine_digital_offset[result_idx] +=
- (NPHY_RSSICAL_NPOLL / 2);
- fine_digital_offset[result_idx] /= NPHY_RSSICAL_NPOLL;
- fine_digital_offset[result_idx] =
- -fine_digital_offset[result_idx];
- } else {
- fine_digital_offset[result_idx] +=
- (NPHY_RSSICAL_NPOLL / 2);
- fine_digital_offset[result_idx] /= NPHY_RSSICAL_NPOLL;
- }
-
- if (poll_results_min[result_idx] ==
- NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL) {
- fine_digital_offset[result_idx] =
- (target_code - NPHY_RSSICAL_MAXREAD - 1);
- }
-
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0,
- (s8)
- fine_digital_offset[result_idx],
- (result_idx / 2 ==
- 0) ? RADIO_MIMO_CORESEL_CORE1 :
- RADIO_MIMO_CORESEL_CORE2,
- (result_idx % 2 ==
- 0) ? NPHY_RAIL_I : NPHY_RAIL_Q,
- rssi_type);
- }
-
- mod_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC, pd_mask, pd_state[0]);
- mod_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC, pd_mask, pd_state[1]);
- if (rssi_ctrl_state[0] == RADIO_2055_NBRSSI_SEL) {
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
- NPHY_RSSI_SEL_NB);
- } else if (rssi_ctrl_state[0] == RADIO_2055_WBRSSI_G1_SEL) {
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
- NPHY_RSSI_SEL_W1);
- } else if (rssi_ctrl_state[0] == RADIO_2055_WBRSSI_G2_SEL) {
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
- NPHY_RSSI_SEL_W2);
- } else {
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE1,
- NPHY_RSSI_SEL_W2);
- }
- if (rssi_ctrl_state[1] == RADIO_2055_NBRSSI_SEL) {
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
- NPHY_RSSI_SEL_NB);
- } else if (rssi_ctrl_state[1] == RADIO_2055_WBRSSI_G1_SEL) {
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
- NPHY_RSSI_SEL_W1);
- } else if (rssi_ctrl_state[1] == RADIO_2055_WBRSSI_G2_SEL) {
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
- NPHY_RSSI_SEL_W2);
- } else {
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_CORE2,
- NPHY_RSSI_SEL_W2);
- }
-
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_OFF, rssi_type);
-
- write_phy_reg(pi, 0x91, rfctrlintc_state[0]);
- write_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX, rfpdcorerxtx_state[0]);
- write_phy_reg(pi, 0x92, rfctrlintc_state[1]);
- write_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX, rfpdcorerxtx_state[1]);
-
- wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
- wlc_phy_clip_det_nphy(pi, 1, clip_state);
-
- wlc_phy_resetcca_nphy(pi);
-}
-
-int
-wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh)
-{
- d11rxhdr_t *rxh = &wlc_rxh->rxhdr;
- s16 rxpwr, rxpwr0, rxpwr1;
- s16 phyRx0_l, phyRx2_l;
-
- rxpwr = 0;
- rxpwr0 = le16_to_cpu(rxh->PhyRxStatus_1) & PRXS1_nphy_PWR0_MASK;
- rxpwr1 = (le16_to_cpu(rxh->PhyRxStatus_1) & PRXS1_nphy_PWR1_MASK) >> 8;
-
- if (rxpwr0 > 127)
- rxpwr0 -= 256;
- if (rxpwr1 > 127)
- rxpwr1 -= 256;
-
- phyRx0_l = le16_to_cpu(rxh->PhyRxStatus_0) & 0x00ff;
- phyRx2_l = le16_to_cpu(rxh->PhyRxStatus_2) & 0x00ff;
- if (phyRx2_l > 127)
- phyRx2_l -= 256;
-
- if (((rxpwr0 == 16) || (rxpwr0 == 32))) {
- rxpwr0 = rxpwr1;
- rxpwr1 = phyRx2_l;
- }
-
- wlc_rxh->rxpwr[0] = (s8) rxpwr0;
- wlc_rxh->rxpwr[1] = (s8) rxpwr1;
- wlc_rxh->do_rssi_ma = 0;
-
- if (pi->sh->rssi_mode == RSSI_ANT_MERGE_MAX)
- rxpwr = (rxpwr0 > rxpwr1) ? rxpwr0 : rxpwr1;
- else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_MIN)
- rxpwr = (rxpwr0 < rxpwr1) ? rxpwr0 : rxpwr1;
- else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_AVG)
- rxpwr = (rxpwr0 + rxpwr1) >> 1;
-
- return rxpwr;
-}
-
-static void
-wlc_phy_rfctrlintc_override_nphy(phy_info_t *pi, u8 field, u16 value,
- u8 core_code)
-{
- u16 mask;
- u16 val;
- u8 core;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- if (core_code == RADIO_MIMO_CORESEL_CORE1
- && core == PHY_CORE_1)
- continue;
- else if (core_code == RADIO_MIMO_CORESEL_CORE2
- && core == PHY_CORE_0)
- continue;
-
- if (NREV_LT(pi->pubpi.phy_rev, 7)) {
-
- mask = (0x1 << 10);
- val = 1 << 10;
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x91 :
- 0x92, mask, val);
- }
-
- if (field == NPHY_RfctrlIntc_override_OFF) {
-
- write_phy_reg(pi, (core == PHY_CORE_0) ? 0x91 :
- 0x92, 0);
-
- wlc_phy_force_rfseq_nphy(pi,
- NPHY_RFSEQ_RESET2RX);
- } else if (field == NPHY_RfctrlIntc_override_TRSW) {
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- mask = (0x1 << 6) | (0x1 << 7);
-
- val = value << 6;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- mask, val);
-
- or_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- (0x1 << 10));
-
- and_phy_reg(pi, 0x2ff, (u16)
- ~(0x3 << 14));
- or_phy_reg(pi, 0x2ff, (0x1 << 13));
- or_phy_reg(pi, 0x2ff, (0x1 << 0));
- } else {
-
- mask = (0x1 << 6) |
- (0x1 << 7) |
- (0x1 << 8) | (0x1 << 9);
- val = value << 6;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- mask, val);
-
- mask = (0x1 << 0);
- val = 1 << 0;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xe7 : 0xec,
- mask, val);
-
- mask = (core == PHY_CORE_0) ? (0x1 << 0)
- : (0x1 << 1);
- val = 1 << ((core == PHY_CORE_0) ?
- 0 : 1);
- mod_phy_reg(pi, 0x78, mask, val);
-
- SPINWAIT(((read_phy_reg(pi, 0x78) & val)
- != 0), 10000);
- if (WARN(read_phy_reg(pi, 0x78) & val,
- "HW error: override failed"))
- return;
-
- mask = (0x1 << 0);
- val = 0 << 0;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xe7 : 0xec,
- mask, val);
- }
- } else if (field == NPHY_RfctrlIntc_override_PA) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- mask = (0x1 << 4) | (0x1 << 5);
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- val = value << 5;
- } else {
- val = value << 4;
- }
-
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- mask, val);
-
- or_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- (0x1 << 12));
- } else {
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- mask = (0x1 << 5);
- val = value << 5;
- } else {
- mask = (0x1 << 4);
- val = value << 4;
- }
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- mask, val);
- }
- } else if (field == NPHY_RfctrlIntc_override_EXT_LNA_PU) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
-
- mask = (0x1 << 0);
- val = value << 0;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91
- : 0x92, mask, val);
-
- mask = (0x1 << 2);
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91
- : 0x92, mask, 0);
- } else {
-
- mask = (0x1 << 2);
- val = value << 2;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91
- : 0x92, mask, val);
-
- mask = (0x1 << 0);
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91
- : 0x92, mask, 0);
- }
-
- mask = (0x1 << 11);
- val = 1 << 11;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- mask, val);
- } else {
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- mask = (0x1 << 0);
- val = value << 0;
- } else {
- mask = (0x1 << 2);
- val = value << 2;
- }
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- mask, val);
- }
- } else if (field ==
- NPHY_RfctrlIntc_override_EXT_LNA_GAIN) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
-
- mask = (0x1 << 1);
- val = value << 1;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91
- : 0x92, mask, val);
-
- mask = (0x1 << 3);
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91
- : 0x92, mask, 0);
- } else {
-
- mask = (0x1 << 3);
- val = value << 3;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91
- : 0x92, mask, val);
-
- mask = (0x1 << 1);
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91
- : 0x92, mask, 0);
- }
-
- mask = (0x1 << 11);
- val = 1 << 11;
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- mask, val);
- } else {
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- mask = (0x1 << 1);
- val = value << 1;
- } else {
- mask = (0x1 << 3);
- val = value << 3;
- }
- mod_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0x91 : 0x92,
- mask, val);
- }
- }
- }
- } else {
- return;
- }
-}
-
-static void wlc_phy_rssi_cal_nphy_rev3(phy_info_t *pi)
-{
- u16 classif_state;
- u16 clip_state[2];
- u16 clip_off[] = { 0xffff, 0xffff };
- s32 target_code;
- u8 vcm, min_vcm;
- u8 vcm_final = 0;
- u8 result_idx;
- s32 poll_results[8][4] = {
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0}
- };
- s32 poll_result_core[4] = { 0, 0, 0, 0 };
- s32 min_d = NPHY_RSSICAL_MAXD, curr_d;
- s32 fine_digital_offset[4];
- s32 poll_results_min[4] = { 0, 0, 0, 0 };
- s32 min_poll;
- u8 vcm_level_max;
- u8 core;
- u8 wb_cnt;
- u8 rssi_type;
- u16 NPHY_Rfctrlintc1_save, NPHY_Rfctrlintc2_save;
- u16 NPHY_AfectrlOverride1_save, NPHY_AfectrlOverride2_save;
- u16 NPHY_AfectrlCore1_save, NPHY_AfectrlCore2_save;
- u16 NPHY_RfctrlOverride0_save, NPHY_RfctrlOverride1_save;
- u16 NPHY_RfctrlOverrideAux0_save, NPHY_RfctrlOverrideAux1_save;
- u16 NPHY_RfctrlCmd_save;
- u16 NPHY_RfctrlMiscReg1_save, NPHY_RfctrlMiscReg2_save;
- u16 NPHY_RfctrlRSSIOTHERS1_save, NPHY_RfctrlRSSIOTHERS2_save;
- u8 rxcore_state;
- u16 NPHY_REV7_RfctrlOverride3_save, NPHY_REV7_RfctrlOverride4_save;
- u16 NPHY_REV7_RfctrlOverride5_save, NPHY_REV7_RfctrlOverride6_save;
- u16 NPHY_REV7_RfctrlMiscReg3_save, NPHY_REV7_RfctrlMiscReg4_save;
- u16 NPHY_REV7_RfctrlMiscReg5_save, NPHY_REV7_RfctrlMiscReg6_save;
-
- NPHY_REV7_RfctrlOverride3_save = NPHY_REV7_RfctrlOverride4_save =
- NPHY_REV7_RfctrlOverride5_save = NPHY_REV7_RfctrlOverride6_save =
- NPHY_REV7_RfctrlMiscReg3_save = NPHY_REV7_RfctrlMiscReg4_save =
- NPHY_REV7_RfctrlMiscReg5_save = NPHY_REV7_RfctrlMiscReg6_save = 0;
-
- classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
- wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
- wlc_phy_clip_det_nphy(pi, 0, clip_state);
- wlc_phy_clip_det_nphy(pi, 1, clip_off);
-
- NPHY_Rfctrlintc1_save = read_phy_reg(pi, 0x91);
- NPHY_Rfctrlintc2_save = read_phy_reg(pi, 0x92);
- NPHY_AfectrlOverride1_save = read_phy_reg(pi, 0x8f);
- NPHY_AfectrlOverride2_save = read_phy_reg(pi, 0xa5);
- NPHY_AfectrlCore1_save = read_phy_reg(pi, 0xa6);
- NPHY_AfectrlCore2_save = read_phy_reg(pi, 0xa7);
- NPHY_RfctrlOverride0_save = read_phy_reg(pi, 0xe7);
- NPHY_RfctrlOverride1_save = read_phy_reg(pi, 0xec);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- NPHY_REV7_RfctrlOverride3_save = read_phy_reg(pi, 0x342);
- NPHY_REV7_RfctrlOverride4_save = read_phy_reg(pi, 0x343);
- NPHY_REV7_RfctrlOverride5_save = read_phy_reg(pi, 0x346);
- NPHY_REV7_RfctrlOverride6_save = read_phy_reg(pi, 0x347);
- }
- NPHY_RfctrlOverrideAux0_save = read_phy_reg(pi, 0xe5);
- NPHY_RfctrlOverrideAux1_save = read_phy_reg(pi, 0xe6);
- NPHY_RfctrlCmd_save = read_phy_reg(pi, 0x78);
- NPHY_RfctrlMiscReg1_save = read_phy_reg(pi, 0xf9);
- NPHY_RfctrlMiscReg2_save = read_phy_reg(pi, 0xfb);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- NPHY_REV7_RfctrlMiscReg3_save = read_phy_reg(pi, 0x340);
- NPHY_REV7_RfctrlMiscReg4_save = read_phy_reg(pi, 0x341);
- NPHY_REV7_RfctrlMiscReg5_save = read_phy_reg(pi, 0x344);
- NPHY_REV7_RfctrlMiscReg6_save = read_phy_reg(pi, 0x345);
- }
- NPHY_RfctrlRSSIOTHERS1_save = read_phy_reg(pi, 0x7a);
- NPHY_RfctrlRSSIOTHERS2_save = read_phy_reg(pi, 0x7d);
-
- wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_OFF, 0,
- RADIO_MIMO_CORESEL_ALLRXTX);
- wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_TRSW, 1,
- RADIO_MIMO_CORESEL_ALLRXTX);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_rxrf_pu,
- 0, 0, 0);
- } else {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0, 0);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_rx_pu,
- 1, 0, 0);
- } else {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 1, 0, 0);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
- 1, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 6), 1, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- } else {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 7), 1, 0, 0);
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 6), 1, 0, 0);
- }
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5),
- 0, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 1, 0,
- 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- } else {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 5), 0, 0, 0);
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 4), 1, 0, 0);
- }
-
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4),
- 0, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 1, 0,
- 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- } else {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 4), 0, 0, 0);
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 5), 1, 0, 0);
- }
- }
-
- rxcore_state = wlc_phy_rxcore_getstate_nphy((wlc_phy_t *) pi);
-
- vcm_level_max = 8;
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
-
- if ((rxcore_state & (1 << core)) == 0)
- continue;
-
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
- core ==
- PHY_CORE_0 ?
- RADIO_MIMO_CORESEL_CORE1 :
- RADIO_MIMO_CORESEL_CORE2,
- NPHY_RAIL_I, NPHY_RSSI_SEL_NB);
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
- core ==
- PHY_CORE_0 ?
- RADIO_MIMO_CORESEL_CORE1 :
- RADIO_MIMO_CORESEL_CORE2,
- NPHY_RAIL_Q, NPHY_RSSI_SEL_NB);
-
- for (vcm = 0; vcm < vcm_level_max; vcm++) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- mod_radio_reg(pi, (core == PHY_CORE_0) ?
- RADIO_2057_NB_MASTER_CORE0 :
- RADIO_2057_NB_MASTER_CORE1,
- RADIO_2057_VCM_MASK, vcm);
- } else {
-
- mod_radio_reg(pi, RADIO_2056_RX_RSSI_MISC |
- ((core ==
- PHY_CORE_0) ? RADIO_2056_RX0 :
- RADIO_2056_RX1),
- RADIO_2056_VCM_MASK,
- vcm << RADIO_2056_RSSI_VCM_SHIFT);
- }
-
- wlc_phy_poll_rssi_nphy(pi, NPHY_RSSI_SEL_NB,
- &poll_results[vcm][0],
- NPHY_RSSICAL_NPOLL);
- }
-
- for (result_idx = 0; result_idx < 4; result_idx++) {
- if ((core == result_idx / 2) && (result_idx % 2 == 0)) {
-
- min_d = NPHY_RSSICAL_MAXD;
- min_vcm = 0;
- min_poll =
- NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL +
- 1;
- for (vcm = 0; vcm < vcm_level_max; vcm++) {
- curr_d = poll_results[vcm][result_idx] *
- poll_results[vcm][result_idx] +
- poll_results[vcm][result_idx + 1] *
- poll_results[vcm][result_idx + 1];
- if (curr_d < min_d) {
- min_d = curr_d;
- min_vcm = vcm;
- }
- if (poll_results[vcm][result_idx] <
- min_poll) {
- min_poll =
- poll_results[vcm]
- [result_idx];
- }
- }
- vcm_final = min_vcm;
- poll_results_min[result_idx] = min_poll;
- }
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- mod_radio_reg(pi, (core == PHY_CORE_0) ?
- RADIO_2057_NB_MASTER_CORE0 :
- RADIO_2057_NB_MASTER_CORE1,
- RADIO_2057_VCM_MASK, vcm_final);
- } else {
- mod_radio_reg(pi, RADIO_2056_RX_RSSI_MISC |
- ((core ==
- PHY_CORE_0) ? RADIO_2056_RX0 :
- RADIO_2056_RX1), RADIO_2056_VCM_MASK,
- vcm_final << RADIO_2056_RSSI_VCM_SHIFT);
- }
-
- for (result_idx = 0; result_idx < 4; result_idx++) {
- if (core == result_idx / 2) {
- fine_digital_offset[result_idx] =
- (NPHY_RSSICAL_NB_TARGET *
- NPHY_RSSICAL_NPOLL) -
- poll_results[vcm_final][result_idx];
- if (fine_digital_offset[result_idx] < 0) {
- fine_digital_offset[result_idx] =
- ABS(fine_digital_offset
- [result_idx]);
- fine_digital_offset[result_idx] +=
- (NPHY_RSSICAL_NPOLL / 2);
- fine_digital_offset[result_idx] /=
- NPHY_RSSICAL_NPOLL;
- fine_digital_offset[result_idx] =
- -fine_digital_offset[result_idx];
- } else {
- fine_digital_offset[result_idx] +=
- (NPHY_RSSICAL_NPOLL / 2);
- fine_digital_offset[result_idx] /=
- NPHY_RSSICAL_NPOLL;
- }
-
- if (poll_results_min[result_idx] ==
- NPHY_RSSICAL_MAXREAD * NPHY_RSSICAL_NPOLL) {
- fine_digital_offset[result_idx] =
- (NPHY_RSSICAL_NB_TARGET -
- NPHY_RSSICAL_MAXREAD - 1);
- }
-
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0,
- (s8)
- fine_digital_offset
- [result_idx],
- (result_idx /
- 2 ==
- 0) ?
- RADIO_MIMO_CORESEL_CORE1
- :
- RADIO_MIMO_CORESEL_CORE2,
- (result_idx %
- 2 ==
- 0) ? NPHY_RAIL_I
- : NPHY_RAIL_Q,
- NPHY_RSSI_SEL_NB);
- }
- }
-
- }
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
-
- if ((rxcore_state & (1 << core)) == 0)
- continue;
-
- for (wb_cnt = 0; wb_cnt < 2; wb_cnt++) {
- if (wb_cnt == 0) {
- rssi_type = NPHY_RSSI_SEL_W1;
- target_code = NPHY_RSSICAL_W1_TARGET_REV3;
- } else {
- rssi_type = NPHY_RSSI_SEL_W2;
- target_code = NPHY_RSSICAL_W2_TARGET_REV3;
- }
-
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
- core ==
- PHY_CORE_0 ?
- RADIO_MIMO_CORESEL_CORE1
- :
- RADIO_MIMO_CORESEL_CORE2,
- NPHY_RAIL_I, rssi_type);
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0, 0x0,
- core ==
- PHY_CORE_0 ?
- RADIO_MIMO_CORESEL_CORE1
- :
- RADIO_MIMO_CORESEL_CORE2,
- NPHY_RAIL_Q, rssi_type);
-
- wlc_phy_poll_rssi_nphy(pi, rssi_type, poll_result_core,
- NPHY_RSSICAL_NPOLL);
-
- for (result_idx = 0; result_idx < 4; result_idx++) {
- if (core == result_idx / 2) {
- fine_digital_offset[result_idx] =
- (target_code * NPHY_RSSICAL_NPOLL) -
- poll_result_core[result_idx];
- if (fine_digital_offset[result_idx] < 0) {
- fine_digital_offset[result_idx]
- =
- ABS(fine_digital_offset
- [result_idx]);
- fine_digital_offset[result_idx]
- += (NPHY_RSSICAL_NPOLL / 2);
- fine_digital_offset[result_idx]
- /= NPHY_RSSICAL_NPOLL;
- fine_digital_offset[result_idx]
- =
- -fine_digital_offset
- [result_idx];
- } else {
- fine_digital_offset[result_idx]
- += (NPHY_RSSICAL_NPOLL / 2);
- fine_digital_offset[result_idx]
- /= NPHY_RSSICAL_NPOLL;
- }
-
- wlc_phy_scale_offset_rssi_nphy(pi, 0x0,
- (s8)
- fine_digital_offset
- [core *
- 2],
- (core ==
- PHY_CORE_0)
- ?
- RADIO_MIMO_CORESEL_CORE1
- :
- RADIO_MIMO_CORESEL_CORE2,
- (result_idx
- % 2 ==
- 0) ?
- NPHY_RAIL_I
- :
- NPHY_RAIL_Q,
- rssi_type);
- }
- }
-
- }
- }
-
- write_phy_reg(pi, 0x91, NPHY_Rfctrlintc1_save);
- write_phy_reg(pi, 0x92, NPHY_Rfctrlintc2_save);
-
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
-
- mod_phy_reg(pi, 0xe7, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0x78, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0xe7, (0x1 << 0), 0);
-
- mod_phy_reg(pi, 0xec, (0x1 << 0), 1 << 0);
- mod_phy_reg(pi, 0x78, (0x1 << 1), 1 << 1);
- mod_phy_reg(pi, 0xec, (0x1 << 0), 0);
-
- write_phy_reg(pi, 0x8f, NPHY_AfectrlOverride1_save);
- write_phy_reg(pi, 0xa5, NPHY_AfectrlOverride2_save);
- write_phy_reg(pi, 0xa6, NPHY_AfectrlCore1_save);
- write_phy_reg(pi, 0xa7, NPHY_AfectrlCore2_save);
- write_phy_reg(pi, 0xe7, NPHY_RfctrlOverride0_save);
- write_phy_reg(pi, 0xec, NPHY_RfctrlOverride1_save);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- write_phy_reg(pi, 0x342, NPHY_REV7_RfctrlOverride3_save);
- write_phy_reg(pi, 0x343, NPHY_REV7_RfctrlOverride4_save);
- write_phy_reg(pi, 0x346, NPHY_REV7_RfctrlOverride5_save);
- write_phy_reg(pi, 0x347, NPHY_REV7_RfctrlOverride6_save);
- }
- write_phy_reg(pi, 0xe5, NPHY_RfctrlOverrideAux0_save);
- write_phy_reg(pi, 0xe6, NPHY_RfctrlOverrideAux1_save);
- write_phy_reg(pi, 0x78, NPHY_RfctrlCmd_save);
- write_phy_reg(pi, 0xf9, NPHY_RfctrlMiscReg1_save);
- write_phy_reg(pi, 0xfb, NPHY_RfctrlMiscReg2_save);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- write_phy_reg(pi, 0x340, NPHY_REV7_RfctrlMiscReg3_save);
- write_phy_reg(pi, 0x341, NPHY_REV7_RfctrlMiscReg4_save);
- write_phy_reg(pi, 0x344, NPHY_REV7_RfctrlMiscReg5_save);
- write_phy_reg(pi, 0x345, NPHY_REV7_RfctrlMiscReg6_save);
- }
- write_phy_reg(pi, 0x7a, NPHY_RfctrlRSSIOTHERS1_save);
- write_phy_reg(pi, 0x7d, NPHY_RfctrlRSSIOTHERS2_save);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- pi->rssical_cache.rssical_radio_regs_2G[0] =
- read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
- pi->rssical_cache.rssical_radio_regs_2G[1] =
- read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
- } else {
- pi->rssical_cache.rssical_radio_regs_2G[0] =
- read_radio_reg(pi,
- RADIO_2056_RX_RSSI_MISC |
- RADIO_2056_RX0);
- pi->rssical_cache.rssical_radio_regs_2G[1] =
- read_radio_reg(pi,
- RADIO_2056_RX_RSSI_MISC |
- RADIO_2056_RX1);
- }
-
- pi->rssical_cache.rssical_phyregs_2G[0] =
- read_phy_reg(pi, 0x1a6);
- pi->rssical_cache.rssical_phyregs_2G[1] =
- read_phy_reg(pi, 0x1ac);
- pi->rssical_cache.rssical_phyregs_2G[2] =
- read_phy_reg(pi, 0x1b2);
- pi->rssical_cache.rssical_phyregs_2G[3] =
- read_phy_reg(pi, 0x1b8);
- pi->rssical_cache.rssical_phyregs_2G[4] =
- read_phy_reg(pi, 0x1a4);
- pi->rssical_cache.rssical_phyregs_2G[5] =
- read_phy_reg(pi, 0x1aa);
- pi->rssical_cache.rssical_phyregs_2G[6] =
- read_phy_reg(pi, 0x1b0);
- pi->rssical_cache.rssical_phyregs_2G[7] =
- read_phy_reg(pi, 0x1b6);
- pi->rssical_cache.rssical_phyregs_2G[8] =
- read_phy_reg(pi, 0x1a5);
- pi->rssical_cache.rssical_phyregs_2G[9] =
- read_phy_reg(pi, 0x1ab);
- pi->rssical_cache.rssical_phyregs_2G[10] =
- read_phy_reg(pi, 0x1b1);
- pi->rssical_cache.rssical_phyregs_2G[11] =
- read_phy_reg(pi, 0x1b7);
-
- pi->nphy_rssical_chanspec_2G = pi->radio_chanspec;
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- pi->rssical_cache.rssical_radio_regs_5G[0] =
- read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
- pi->rssical_cache.rssical_radio_regs_5G[1] =
- read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
- } else {
- pi->rssical_cache.rssical_radio_regs_5G[0] =
- read_radio_reg(pi,
- RADIO_2056_RX_RSSI_MISC |
- RADIO_2056_RX0);
- pi->rssical_cache.rssical_radio_regs_5G[1] =
- read_radio_reg(pi,
- RADIO_2056_RX_RSSI_MISC |
- RADIO_2056_RX1);
- }
-
- pi->rssical_cache.rssical_phyregs_5G[0] =
- read_phy_reg(pi, 0x1a6);
- pi->rssical_cache.rssical_phyregs_5G[1] =
- read_phy_reg(pi, 0x1ac);
- pi->rssical_cache.rssical_phyregs_5G[2] =
- read_phy_reg(pi, 0x1b2);
- pi->rssical_cache.rssical_phyregs_5G[3] =
- read_phy_reg(pi, 0x1b8);
- pi->rssical_cache.rssical_phyregs_5G[4] =
- read_phy_reg(pi, 0x1a4);
- pi->rssical_cache.rssical_phyregs_5G[5] =
- read_phy_reg(pi, 0x1aa);
- pi->rssical_cache.rssical_phyregs_5G[6] =
- read_phy_reg(pi, 0x1b0);
- pi->rssical_cache.rssical_phyregs_5G[7] =
- read_phy_reg(pi, 0x1b6);
- pi->rssical_cache.rssical_phyregs_5G[8] =
- read_phy_reg(pi, 0x1a5);
- pi->rssical_cache.rssical_phyregs_5G[9] =
- read_phy_reg(pi, 0x1ab);
- pi->rssical_cache.rssical_phyregs_5G[10] =
- read_phy_reg(pi, 0x1b1);
- pi->rssical_cache.rssical_phyregs_5G[11] =
- read_phy_reg(pi, 0x1b7);
-
- pi->nphy_rssical_chanspec_5G = pi->radio_chanspec;
- }
-
- wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
- wlc_phy_clip_det_nphy(pi, 1, clip_state);
-}
-
-static void wlc_phy_restore_rssical_nphy(phy_info_t *pi)
-{
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (pi->nphy_rssical_chanspec_2G == 0)
- return;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0,
- RADIO_2057_VCM_MASK,
- pi->rssical_cache.
- rssical_radio_regs_2G[0]);
- mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1,
- RADIO_2057_VCM_MASK,
- pi->rssical_cache.
- rssical_radio_regs_2G[1]);
- } else {
- mod_radio_reg(pi,
- RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX0,
- RADIO_2056_VCM_MASK,
- pi->rssical_cache.
- rssical_radio_regs_2G[0]);
- mod_radio_reg(pi,
- RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX1,
- RADIO_2056_VCM_MASK,
- pi->rssical_cache.
- rssical_radio_regs_2G[1]);
- }
-
- write_phy_reg(pi, 0x1a6,
- pi->rssical_cache.rssical_phyregs_2G[0]);
- write_phy_reg(pi, 0x1ac,
- pi->rssical_cache.rssical_phyregs_2G[1]);
- write_phy_reg(pi, 0x1b2,
- pi->rssical_cache.rssical_phyregs_2G[2]);
- write_phy_reg(pi, 0x1b8,
- pi->rssical_cache.rssical_phyregs_2G[3]);
- write_phy_reg(pi, 0x1a4,
- pi->rssical_cache.rssical_phyregs_2G[4]);
- write_phy_reg(pi, 0x1aa,
- pi->rssical_cache.rssical_phyregs_2G[5]);
- write_phy_reg(pi, 0x1b0,
- pi->rssical_cache.rssical_phyregs_2G[6]);
- write_phy_reg(pi, 0x1b6,
- pi->rssical_cache.rssical_phyregs_2G[7]);
- write_phy_reg(pi, 0x1a5,
- pi->rssical_cache.rssical_phyregs_2G[8]);
- write_phy_reg(pi, 0x1ab,
- pi->rssical_cache.rssical_phyregs_2G[9]);
- write_phy_reg(pi, 0x1b1,
- pi->rssical_cache.rssical_phyregs_2G[10]);
- write_phy_reg(pi, 0x1b7,
- pi->rssical_cache.rssical_phyregs_2G[11]);
-
- } else {
- if (pi->nphy_rssical_chanspec_5G == 0)
- return;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0,
- RADIO_2057_VCM_MASK,
- pi->rssical_cache.
- rssical_radio_regs_5G[0]);
- mod_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1,
- RADIO_2057_VCM_MASK,
- pi->rssical_cache.
- rssical_radio_regs_5G[1]);
- } else {
- mod_radio_reg(pi,
- RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX0,
- RADIO_2056_VCM_MASK,
- pi->rssical_cache.
- rssical_radio_regs_5G[0]);
- mod_radio_reg(pi,
- RADIO_2056_RX_RSSI_MISC | RADIO_2056_RX1,
- RADIO_2056_VCM_MASK,
- pi->rssical_cache.
- rssical_radio_regs_5G[1]);
- }
-
- write_phy_reg(pi, 0x1a6,
- pi->rssical_cache.rssical_phyregs_5G[0]);
- write_phy_reg(pi, 0x1ac,
- pi->rssical_cache.rssical_phyregs_5G[1]);
- write_phy_reg(pi, 0x1b2,
- pi->rssical_cache.rssical_phyregs_5G[2]);
- write_phy_reg(pi, 0x1b8,
- pi->rssical_cache.rssical_phyregs_5G[3]);
- write_phy_reg(pi, 0x1a4,
- pi->rssical_cache.rssical_phyregs_5G[4]);
- write_phy_reg(pi, 0x1aa,
- pi->rssical_cache.rssical_phyregs_5G[5]);
- write_phy_reg(pi, 0x1b0,
- pi->rssical_cache.rssical_phyregs_5G[6]);
- write_phy_reg(pi, 0x1b6,
- pi->rssical_cache.rssical_phyregs_5G[7]);
- write_phy_reg(pi, 0x1a5,
- pi->rssical_cache.rssical_phyregs_5G[8]);
- write_phy_reg(pi, 0x1ab,
- pi->rssical_cache.rssical_phyregs_5G[9]);
- write_phy_reg(pi, 0x1b1,
- pi->rssical_cache.rssical_phyregs_5G[10]);
- write_phy_reg(pi, 0x1b7,
- pi->rssical_cache.rssical_phyregs_5G[11]);
- }
-}
-
-static u16
-wlc_phy_gen_load_samples_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
- u8 dac_test_mode)
-{
- u8 phy_bw, is_phybw40;
- u16 num_samps, t, spur;
- fixed theta = 0, rot = 0;
- u32 tbl_len;
- cs32 *tone_buf = NULL;
-
- is_phybw40 = CHSPEC_IS40(pi->radio_chanspec);
- phy_bw = (is_phybw40 == 1) ? 40 : 20;
- tbl_len = (phy_bw << 3);
-
- if (dac_test_mode == 1) {
- spur = read_phy_reg(pi, 0x01);
- spur = (spur >> 15) & 1;
- phy_bw = (spur == 1) ? 82 : 80;
- phy_bw = (is_phybw40 == 1) ? (phy_bw << 1) : phy_bw;
-
- tbl_len = (phy_bw << 1);
- }
-
- tone_buf = kmalloc(sizeof(cs32) * tbl_len, GFP_ATOMIC);
- if (tone_buf == NULL) {
- return 0;
- }
-
- num_samps = (u16) tbl_len;
- rot = FIXED((f_kHz * 36) / phy_bw) / 100;
- theta = 0;
-
- for (t = 0; t < num_samps; t++) {
-
- wlc_phy_cordic(theta, &tone_buf[t]);
-
- theta += rot;
-
- tone_buf[t].q = (s32) FLOAT(tone_buf[t].q * max_val);
- tone_buf[t].i = (s32) FLOAT(tone_buf[t].i * max_val);
- }
-
- wlc_phy_loadsampletable_nphy(pi, tone_buf, num_samps);
-
- kfree(tone_buf);
-
- return num_samps;
-}
-
-int
-wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
- u8 iqmode, u8 dac_test_mode, bool modify_bbmult)
-{
- u16 num_samps;
- u16 loops = 0xffff;
- u16 wait = 0;
-
- num_samps =
- wlc_phy_gen_load_samples_nphy(pi, f_kHz, max_val, dac_test_mode);
- if (num_samps == 0) {
- return -EBADE;
- }
-
- wlc_phy_runsamples_nphy(pi, num_samps, loops, wait, iqmode,
- dac_test_mode, modify_bbmult);
-
- return 0;
-}
-
-static void
-wlc_phy_loadsampletable_nphy(phy_info_t *pi, cs32 *tone_buf,
- u16 num_samps)
-{
- u16 t;
- u32 *data_buf = NULL;
-
- data_buf = kmalloc(sizeof(u32) * num_samps, GFP_ATOMIC);
- if (data_buf == NULL) {
- return;
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- for (t = 0; t < num_samps; t++) {
- data_buf[t] = ((((unsigned int)tone_buf[t].i) & 0x3ff) << 10) |
- (((unsigned int)tone_buf[t].q) & 0x3ff);
- }
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SAMPLEPLAY, num_samps, 0, 32,
- data_buf);
-
- kfree(data_buf);
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-static void
-wlc_phy_runsamples_nphy(phy_info_t *pi, u16 num_samps, u16 loops,
- u16 wait, u8 iqmode, u8 dac_test_mode,
- bool modify_bbmult)
-{
- u16 bb_mult;
- u8 phy_bw, sample_cmd;
- u16 orig_RfseqCoreActv;
- u16 lpf_bw_ctl_override3, lpf_bw_ctl_override4, lpf_bw_ctl_miscreg3,
- lpf_bw_ctl_miscreg4;
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- phy_bw = 20;
- if (CHSPEC_IS40(pi->radio_chanspec))
- phy_bw = 40;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- lpf_bw_ctl_override3 = read_phy_reg(pi, 0x342) & (0x1 << 7);
- lpf_bw_ctl_override4 = read_phy_reg(pi, 0x343) & (0x1 << 7);
- if (lpf_bw_ctl_override3 | lpf_bw_ctl_override4) {
- lpf_bw_ctl_miscreg3 = read_phy_reg(pi, 0x340) &
- (0x7 << 8);
- lpf_bw_ctl_miscreg4 = read_phy_reg(pi, 0x341) &
- (0x7 << 8);
- } else {
- wlc_phy_rfctrl_override_nphy_rev7(pi,
- (0x1 << 7),
- wlc_phy_read_lpf_bw_ctl_nphy
- (pi, 0), 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
-
- pi->nphy_sample_play_lpf_bw_ctl_ovr = true;
-
- lpf_bw_ctl_miscreg3 = read_phy_reg(pi, 0x340) &
- (0x7 << 8);
- lpf_bw_ctl_miscreg4 = read_phy_reg(pi, 0x341) &
- (0x7 << 8);
- }
- }
-
- if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) == 0) {
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
- &bb_mult);
- pi->nphy_bb_mult_save =
- BB_MULT_VALID_MASK | (bb_mult & BB_MULT_MASK);
- }
-
- if (modify_bbmult) {
- bb_mult = (phy_bw == 20) ? 100 : 71;
- bb_mult = (bb_mult << 8) + bb_mult;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
- &bb_mult);
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-
- write_phy_reg(pi, 0xc6, num_samps - 1);
-
- if (loops != 0xffff) {
- write_phy_reg(pi, 0xc4, loops - 1);
- } else {
- write_phy_reg(pi, 0xc4, loops);
- }
- write_phy_reg(pi, 0xc5, wait);
-
- orig_RfseqCoreActv = read_phy_reg(pi, 0xa1);
- or_phy_reg(pi, 0xa1, NPHY_RfseqMode_CoreActv_override);
- if (iqmode) {
-
- and_phy_reg(pi, 0xc2, 0x7FFF);
-
- or_phy_reg(pi, 0xc2, 0x8000);
- } else {
-
- sample_cmd = (dac_test_mode == 1) ? 0x5 : 0x1;
- write_phy_reg(pi, 0xc3, sample_cmd);
- }
-
- SPINWAIT(((read_phy_reg(pi, 0xa4) & 0x1) == 1), 1000);
-
- write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
-}
-
-void wlc_phy_stopplayback_nphy(phy_info_t *pi)
-{
- u16 playback_status;
- u16 bb_mult;
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- playback_status = read_phy_reg(pi, 0xc7);
- if (playback_status & 0x1) {
- or_phy_reg(pi, 0xc3, NPHY_sampleCmd_STOP);
- } else if (playback_status & 0x2) {
-
- and_phy_reg(pi, 0xc2,
- (u16) ~NPHY_iqloCalCmdGctl_IQLO_CAL_EN);
- }
-
- and_phy_reg(pi, 0xc3, (u16) ~(0x1 << 2));
-
- if ((pi->nphy_bb_mult_save & BB_MULT_VALID_MASK) != 0) {
-
- bb_mult = pi->nphy_bb_mult_save & BB_MULT_MASK;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, 87, 16,
- &bb_mult);
-
- pi->nphy_bb_mult_save = 0;
- }
-
- if (NREV_IS(pi->pubpi.phy_rev, 7) || NREV_GE(pi->pubpi.phy_rev, 8)) {
- if (pi->nphy_sample_play_lpf_bw_ctl_ovr) {
- wlc_phy_rfctrl_override_nphy_rev7(pi,
- (0x1 << 7),
- 0, 0, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- pi->nphy_sample_play_lpf_bw_ctl_ovr = false;
- }
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-nphy_txgains_t wlc_phy_get_tx_gain_nphy(phy_info_t *pi)
-{
- u16 base_idx[2], curr_gain[2];
- u8 core_no;
- nphy_txgains_t target_gain;
- u32 *tx_pwrctrl_tbl = NULL;
-
- if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF) {
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
- curr_gain);
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-
- for (core_no = 0; core_no < 2; core_no++) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- target_gain.ipa[core_no] =
- curr_gain[core_no] & 0x0007;
- target_gain.pad[core_no] =
- ((curr_gain[core_no] & 0x00F8) >> 3);
- target_gain.pga[core_no] =
- ((curr_gain[core_no] & 0x0F00) >> 8);
- target_gain.txgm[core_no] =
- ((curr_gain[core_no] & 0x7000) >> 12);
- target_gain.txlpf[core_no] =
- ((curr_gain[core_no] & 0x8000) >> 15);
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- target_gain.ipa[core_no] =
- curr_gain[core_no] & 0x000F;
- target_gain.pad[core_no] =
- ((curr_gain[core_no] & 0x00F0) >> 4);
- target_gain.pga[core_no] =
- ((curr_gain[core_no] & 0x0F00) >> 8);
- target_gain.txgm[core_no] =
- ((curr_gain[core_no] & 0x7000) >> 12);
- } else {
- target_gain.ipa[core_no] =
- curr_gain[core_no] & 0x0003;
- target_gain.pad[core_no] =
- ((curr_gain[core_no] & 0x000C) >> 2);
- target_gain.pga[core_no] =
- ((curr_gain[core_no] & 0x0070) >> 4);
- target_gain.txgm[core_no] =
- ((curr_gain[core_no] & 0x0380) >> 7);
- }
- }
- } else {
- base_idx[0] = (read_phy_reg(pi, 0x1ed) >> 8) & 0x7f;
- base_idx[1] = (read_phy_reg(pi, 0x1ee) >> 8) & 0x7f;
- for (core_no = 0; core_no < 2; core_no++) {
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (PHY_IPA(pi)) {
- tx_pwrctrl_tbl =
- wlc_phy_get_ipa_gaintbl_nphy(pi);
- } else {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if NREV_IS
- (pi->pubpi.phy_rev, 3) {
- tx_pwrctrl_tbl =
- nphy_tpc_5GHz_txgain_rev3;
- } else if NREV_IS
- (pi->pubpi.phy_rev, 4) {
- tx_pwrctrl_tbl =
- (pi->srom_fem5g.
- extpagain ==
- 3) ?
- nphy_tpc_5GHz_txgain_HiPwrEPA
- :
- nphy_tpc_5GHz_txgain_rev4;
- } else {
- tx_pwrctrl_tbl =
- nphy_tpc_5GHz_txgain_rev5;
- }
- } else {
- if (NREV_GE
- (pi->pubpi.phy_rev, 7)) {
- if (pi->pubpi.
- radiorev == 3) {
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_epa_2057rev3;
- } else if (pi->pubpi.
- radiorev ==
- 5) {
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_epa_2057rev5;
- }
-
- } else {
- if (NREV_GE
- (pi->pubpi.phy_rev,
- 5)
- && (pi->srom_fem2g.
- extpagain ==
- 3)) {
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_HiPwrEPA;
- } else {
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_rev3;
- }
- }
- }
- }
- if NREV_GE
- (pi->pubpi.phy_rev, 7) {
- target_gain.ipa[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 16) & 0x7;
- target_gain.pad[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 19) & 0x1f;
- target_gain.pga[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 24) & 0xf;
- target_gain.txgm[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 28) & 0x7;
- target_gain.txlpf[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 31) & 0x1;
- } else {
- target_gain.ipa[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 16) & 0xf;
- target_gain.pad[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 20) & 0xf;
- target_gain.pga[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 24) & 0xf;
- target_gain.txgm[core_no] =
- (tx_pwrctrl_tbl[base_idx[core_no]]
- >> 28) & 0x7;
- }
- } else {
- target_gain.ipa[core_no] =
- (nphy_tpc_txgain[base_idx[core_no]] >> 16) &
- 0x3;
- target_gain.pad[core_no] =
- (nphy_tpc_txgain[base_idx[core_no]] >> 18) &
- 0x3;
- target_gain.pga[core_no] =
- (nphy_tpc_txgain[base_idx[core_no]] >> 20) &
- 0x7;
- target_gain.txgm[core_no] =
- (nphy_tpc_txgain[base_idx[core_no]] >> 23) &
- 0x7;
- }
- }
- }
-
- return target_gain;
-}
-
-static void
-wlc_phy_iqcal_gainparams_nphy(phy_info_t *pi, u16 core_no,
- nphy_txgains_t target_gain,
- nphy_iqcal_params_t *params)
-{
- u8 k;
- int idx;
- u16 gain_index;
- u8 band_idx = (CHSPEC_IS5G(pi->radio_chanspec) ? 1 : 0);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- params->txlpf = target_gain.txlpf[core_no];
- }
- params->txgm = target_gain.txgm[core_no];
- params->pga = target_gain.pga[core_no];
- params->pad = target_gain.pad[core_no];
- params->ipa = target_gain.ipa[core_no];
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- params->cal_gain =
- ((params->txlpf << 15) | (params->
- txgm << 12) | (params->
- pga << 8) |
- (params->pad << 3) | (params->ipa));
- } else {
- params->cal_gain =
- ((params->txgm << 12) | (params->
- pga << 8) | (params->
- pad << 4) |
- (params->ipa));
- }
- params->ncorr[0] = 0x79;
- params->ncorr[1] = 0x79;
- params->ncorr[2] = 0x79;
- params->ncorr[3] = 0x79;
- params->ncorr[4] = 0x79;
- } else {
-
- gain_index = ((target_gain.pad[core_no] << 0) |
- (target_gain.pga[core_no] << 4) | (target_gain.
- txgm[core_no]
- << 8));
-
- idx = -1;
- for (k = 0; k < NPHY_IQCAL_NUMGAINS; k++) {
- if (tbl_iqcal_gainparams_nphy[band_idx][k][0] ==
- gain_index) {
- idx = k;
- break;
- }
- }
-
- params->txgm = tbl_iqcal_gainparams_nphy[band_idx][k][1];
- params->pga = tbl_iqcal_gainparams_nphy[band_idx][k][2];
- params->pad = tbl_iqcal_gainparams_nphy[band_idx][k][3];
- params->cal_gain = ((params->txgm << 7) | (params->pga << 4) |
- (params->pad << 2));
- params->ncorr[0] = tbl_iqcal_gainparams_nphy[band_idx][k][4];
- params->ncorr[1] = tbl_iqcal_gainparams_nphy[band_idx][k][5];
- params->ncorr[2] = tbl_iqcal_gainparams_nphy[band_idx][k][6];
- params->ncorr[3] = tbl_iqcal_gainparams_nphy[band_idx][k][7];
- }
-}
-
-static void wlc_phy_txcal_radio_setup_nphy(phy_info_t *pi)
-{
- u16 jtag_core, core;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- for (core = 0; core <= 1; core++) {
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 0] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MASTER);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 1] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- IQCAL_VCM_HG);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 2] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- IQCAL_IDAC);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 3] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 4] = 0;
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 5] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MUX);
-
- if (pi->pubpi.radiorev != 5)
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 6] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSIA);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 7] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core, TSSIG);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 8] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSI_MISC1);
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MASTER, 0x0a);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- IQCAL_VCM_HG, 0x43);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- IQCAL_IDAC, 0x55);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSI_VCM, 0x00);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSIG, 0x00);
- if (pi->use_int_tx_iqlo_cal_nphy) {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX,
- core, TX_SSI_MUX, 0x4);
- if (!
- (pi->
- internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057,
- TX, core,
- TSSIA, 0x31);
- } else {
-
- WRITE_RADIO_REG3(pi, RADIO_2057,
- TX, core,
- TSSIA, 0x21);
- }
- }
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSI_MISC1, 0x00);
- } else {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MASTER, 0x06);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- IQCAL_VCM_HG, 0x43);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- IQCAL_IDAC, 0x55);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSI_VCM, 0x00);
-
- if (pi->pubpi.radiorev != 5)
- WRITE_RADIO_REG3(pi, RADIO_2057, TX,
- core, TSSIA, 0x00);
- if (pi->use_int_tx_iqlo_cal_nphy) {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX,
- core, TX_SSI_MUX,
- 0x06);
- if (!
- (pi->
- internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057,
- TX, core,
- TSSIG, 0x31);
- } else {
-
- WRITE_RADIO_REG3(pi, RADIO_2057,
- TX, core,
- TSSIG, 0x21);
- }
- }
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSI_MISC1, 0x00);
- }
- }
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- for (core = 0; core <= 1; core++) {
- jtag_core =
- (core ==
- PHY_CORE_0) ? RADIO_2056_TX0 : RADIO_2056_TX1;
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 0] =
- read_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MASTER |
- jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 1] =
- read_radio_reg(pi,
- RADIO_2056_TX_IQCAL_VCM_HG |
- jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 2] =
- read_radio_reg(pi,
- RADIO_2056_TX_IQCAL_IDAC |
- jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 3] =
- read_radio_reg(pi,
- RADIO_2056_TX_TSSI_VCM | jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 4] =
- read_radio_reg(pi,
- RADIO_2056_TX_TX_AMP_DET |
- jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 5] =
- read_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MUX |
- jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 6] =
- read_radio_reg(pi, RADIO_2056_TX_TSSIA | jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 7] =
- read_radio_reg(pi, RADIO_2056_TX_TSSIG | jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 8] =
- read_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC1 |
- jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 9] =
- read_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC2 |
- jtag_core);
-
- pi->tx_rx_cal_radio_saveregs[(core * 11) + 10] =
- read_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC3 |
- jtag_core);
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MASTER |
- jtag_core, 0x0a);
- write_radio_reg(pi,
- RADIO_2056_TX_IQCAL_VCM_HG |
- jtag_core, 0x40);
- write_radio_reg(pi,
- RADIO_2056_TX_IQCAL_IDAC |
- jtag_core, 0x55);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_VCM |
- jtag_core, 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TX_AMP_DET |
- jtag_core, 0x00);
-
- if (PHY_IPA(pi)) {
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MUX
- | jtag_core, 0x4);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSIA |
- jtag_core, 0x1);
- } else {
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MUX
- | jtag_core, 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSIA |
- jtag_core, 0x2f);
- }
- write_radio_reg(pi,
- RADIO_2056_TX_TSSIG | jtag_core,
- 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC1 |
- jtag_core, 0x00);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC2 |
- jtag_core, 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC3 |
- jtag_core, 0x00);
- } else {
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MASTER |
- jtag_core, 0x06);
- write_radio_reg(pi,
- RADIO_2056_TX_IQCAL_VCM_HG |
- jtag_core, 0x40);
- write_radio_reg(pi,
- RADIO_2056_TX_IQCAL_IDAC |
- jtag_core, 0x55);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_VCM |
- jtag_core, 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TX_AMP_DET |
- jtag_core, 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSIA | jtag_core,
- 0x00);
-
- if (PHY_IPA(pi)) {
-
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MUX
- | jtag_core, 0x06);
- if (NREV_LT(pi->pubpi.phy_rev, 5)) {
-
- write_radio_reg(pi,
- RADIO_2056_TX_TSSIG
- | jtag_core,
- 0x11);
- } else {
-
- write_radio_reg(pi,
- RADIO_2056_TX_TSSIG
- | jtag_core,
- 0x1);
- }
- } else {
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MUX
- | jtag_core, 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSIG |
- jtag_core, 0x20);
- }
-
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC1 |
- jtag_core, 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC2 |
- jtag_core, 0x00);
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC3 |
- jtag_core, 0x00);
- }
- }
- } else {
-
- pi->tx_rx_cal_radio_saveregs[0] =
- read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
- write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1, 0x29);
- pi->tx_rx_cal_radio_saveregs[1] =
- read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
- write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2, 0x54);
-
- pi->tx_rx_cal_radio_saveregs[2] =
- read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
- write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1, 0x29);
- pi->tx_rx_cal_radio_saveregs[3] =
- read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
- write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2, 0x54);
-
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
- pi->tx_rx_cal_radio_saveregs[5] =
- read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
-
- if ((read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand) ==
- 0) {
-
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x04);
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x04);
- } else {
-
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1, 0x20);
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2, 0x20);
- }
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
-
- or_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM, 0x20);
- or_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM, 0x20);
- } else {
-
- and_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM, 0xdf);
- and_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM, 0xdf);
- }
- }
-}
-
-static void wlc_phy_txcal_radio_cleanup_nphy(phy_info_t *pi)
-{
- u16 jtag_core, core;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- for (core = 0; core <= 1; core++) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MASTER,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 0]);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_VCM_HG,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 1]);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_IDAC,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 2]);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 3]);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TX_SSI_MUX,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 5]);
-
- if (pi->pubpi.radiorev != 5)
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSIA,
- pi->
- tx_rx_cal_radio_saveregs[(core
- *
- 11) +
- 6]);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSIG,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 7]);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_MISC1,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 8]);
- }
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- for (core = 0; core <= 1; core++) {
- jtag_core =
- (core ==
- PHY_CORE_0) ? RADIO_2056_TX0 : RADIO_2056_TX1;
-
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MASTER | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 0]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_IQCAL_VCM_HG | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 1]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_IQCAL_IDAC | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 2]);
-
- write_radio_reg(pi, RADIO_2056_TX_TSSI_VCM | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 3]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TX_AMP_DET | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 4]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MUX | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 5]);
-
- write_radio_reg(pi, RADIO_2056_TX_TSSIA | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 6]);
-
- write_radio_reg(pi, RADIO_2056_TX_TSSIG | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 7]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC1 | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 8]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC2 | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 9]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TSSI_MISC3 | jtag_core,
- pi->
- tx_rx_cal_radio_saveregs[(core * 11) +
- 10]);
- }
- } else {
-
- write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1,
- pi->tx_rx_cal_radio_saveregs[0]);
- write_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2,
- pi->tx_rx_cal_radio_saveregs[1]);
- write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1,
- pi->tx_rx_cal_radio_saveregs[2]);
- write_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2,
- pi->tx_rx_cal_radio_saveregs[3]);
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1,
- pi->tx_rx_cal_radio_saveregs[4]);
- write_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2,
- pi->tx_rx_cal_radio_saveregs[5]);
- }
-}
-
-static void wlc_phy_txcal_physetup_nphy(phy_info_t *pi)
-{
- u16 val, mask;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6);
- pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 0xa7);
-
- mask = ((0x3 << 8) | (0x3 << 10));
- val = (0x2 << 8);
- val |= (0x2 << 10);
- mod_phy_reg(pi, 0xa6, mask, val);
- mod_phy_reg(pi, 0xa7, mask, val);
-
- val = read_phy_reg(pi, 0x8f);
- pi->tx_rx_cal_phy_saveregs[2] = val;
- val |= ((0x1 << 9) | (0x1 << 10));
- write_phy_reg(pi, 0x8f, val);
-
- val = read_phy_reg(pi, 0xa5);
- pi->tx_rx_cal_phy_saveregs[3] = val;
- val |= ((0x1 << 9) | (0x1 << 10));
- write_phy_reg(pi, 0xa5, val);
-
- pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 0x01);
- mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
- &val);
- pi->tx_rx_cal_phy_saveregs[5] = val;
- val = 0;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
- &val);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
- &val);
- pi->tx_rx_cal_phy_saveregs[6] = val;
- val = 0;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
- &val);
-
- pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 0x91);
- pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 0x92);
-
- if (!(pi->use_int_tx_iqlo_cal_nphy)) {
-
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_PA,
- 1,
- RADIO_MIMO_CORESEL_CORE1
- |
- RADIO_MIMO_CORESEL_CORE2);
- } else {
-
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_PA,
- 0,
- RADIO_MIMO_CORESEL_CORE1
- |
- RADIO_MIMO_CORESEL_CORE2);
- }
-
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- 0x2, RADIO_MIMO_CORESEL_CORE1);
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- 0x8, RADIO_MIMO_CORESEL_CORE2);
-
- pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 0x297);
- pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 0x29b);
- mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (0) << 0);
-
- mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (0) << 0);
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)
- || NREV_GE(pi->pubpi.phy_rev, 8)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
- wlc_phy_read_lpf_bw_ctl_nphy
- (pi, 0), 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- }
-
- if (pi->use_int_tx_iqlo_cal_nphy
- && !(pi->internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)) {
-
- mod_radio_reg(pi, RADIO_2057_OVR_REG0, 1 << 4,
- 1 << 4);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- mod_radio_reg(pi,
- RADIO_2057_PAD2G_TUNE_PUS_CORE0,
- 1, 0);
- mod_radio_reg(pi,
- RADIO_2057_PAD2G_TUNE_PUS_CORE1,
- 1, 0);
- } else {
- mod_radio_reg(pi,
- RADIO_2057_IPA5G_CASCOFFV_PU_CORE0,
- 1, 0);
- mod_radio_reg(pi,
- RADIO_2057_IPA5G_CASCOFFV_PU_CORE1,
- 1, 0);
- }
- } else if (NREV_GE(pi->pubpi.phy_rev, 8)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi,
- (0x1 << 3), 0,
- 0x3, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- }
- }
- } else {
- pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa6);
- pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 0xa7);
-
- mask = ((0x3 << 12) | (0x3 << 14));
- val = (0x2 << 12);
- val |= (0x2 << 14);
- mod_phy_reg(pi, 0xa6, mask, val);
- mod_phy_reg(pi, 0xa7, mask, val);
-
- val = read_phy_reg(pi, 0xa5);
- pi->tx_rx_cal_phy_saveregs[2] = val;
- val |= ((0x1 << 12) | (0x1 << 13));
- write_phy_reg(pi, 0xa5, val);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
- &val);
- pi->tx_rx_cal_phy_saveregs[3] = val;
- val |= 0x2000;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
- &val);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
- &val);
- pi->tx_rx_cal_phy_saveregs[4] = val;
- val |= 0x2000;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
- &val);
-
- pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 0x91);
- pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 0x92);
- val = CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 : 0x120;
- write_phy_reg(pi, 0x91, val);
- write_phy_reg(pi, 0x92, val);
- }
-}
-
-static void wlc_phy_txcal_phycleanup_nphy(phy_info_t *pi)
-{
- u16 mask;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- write_phy_reg(pi, 0xa6, pi->tx_rx_cal_phy_saveregs[0]);
- write_phy_reg(pi, 0xa7, pi->tx_rx_cal_phy_saveregs[1]);
- write_phy_reg(pi, 0x8f, pi->tx_rx_cal_phy_saveregs[2]);
- write_phy_reg(pi, 0xa5, pi->tx_rx_cal_phy_saveregs[3]);
- write_phy_reg(pi, 0x01, pi->tx_rx_cal_phy_saveregs[4]);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 3, 16,
- &pi->tx_rx_cal_phy_saveregs[5]);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 19, 16,
- &pi->tx_rx_cal_phy_saveregs[6]);
-
- write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[7]);
- write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[8]);
-
- write_phy_reg(pi, 0x297, pi->tx_rx_cal_phy_saveregs[9]);
- write_phy_reg(pi, 0x29b, pi->tx_rx_cal_phy_saveregs[10]);
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)
- || NREV_GE(pi->pubpi.phy_rev, 8)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7), 0, 0,
- 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- }
-
- wlc_phy_resetcca_nphy(pi);
-
- if (pi->use_int_tx_iqlo_cal_nphy
- && !(pi->internal_tx_iqlo_cal_tapoff_intpa_nphy)) {
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- mod_radio_reg(pi,
- RADIO_2057_PAD2G_TUNE_PUS_CORE0,
- 1, 1);
- mod_radio_reg(pi,
- RADIO_2057_PAD2G_TUNE_PUS_CORE1,
- 1, 1);
- } else {
- mod_radio_reg(pi,
- RADIO_2057_IPA5G_CASCOFFV_PU_CORE0,
- 1, 1);
- mod_radio_reg(pi,
- RADIO_2057_IPA5G_CASCOFFV_PU_CORE1,
- 1, 1);
- }
-
- mod_radio_reg(pi, RADIO_2057_OVR_REG0, 1 << 4,
- 0);
- } else if (NREV_GE(pi->pubpi.phy_rev, 8)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi,
- (0x1 << 3), 0,
- 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- }
- }
- } else {
- mask = ((0x3 << 12) | (0x3 << 14));
- mod_phy_reg(pi, 0xa6, mask, pi->tx_rx_cal_phy_saveregs[0]);
- mod_phy_reg(pi, 0xa7, mask, pi->tx_rx_cal_phy_saveregs[1]);
- write_phy_reg(pi, 0xa5, pi->tx_rx_cal_phy_saveregs[2]);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 2, 16,
- &pi->tx_rx_cal_phy_saveregs[3]);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 18, 16,
- &pi->tx_rx_cal_phy_saveregs[4]);
-
- write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[5]);
- write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[6]);
- }
-}
-
-#define NPHY_CAL_TSSISAMPS 64
-#define NPHY_TEST_TONE_FREQ_40MHz 4000
-#define NPHY_TEST_TONE_FREQ_20MHz 2500
-
-void
-wlc_phy_est_tonepwr_nphy(phy_info_t *pi, s32 *qdBm_pwrbuf, u8 num_samps)
-{
- u16 tssi_reg;
- s32 temp, pwrindex[2];
- s32 idle_tssi[2];
- s32 rssi_buf[4];
- s32 tssival[2];
- u8 tssi_type;
-
- tssi_reg = read_phy_reg(pi, 0x1e9);
-
- temp = (s32) (tssi_reg & 0x3f);
- idle_tssi[0] = (temp <= 31) ? temp : (temp - 64);
-
- temp = (s32) ((tssi_reg >> 8) & 0x3f);
- idle_tssi[1] = (temp <= 31) ? temp : (temp - 64);
-
- tssi_type =
- CHSPEC_IS5G(pi->radio_chanspec) ?
- (u8)NPHY_RSSI_SEL_TSSI_5G:(u8)NPHY_RSSI_SEL_TSSI_2G;
-
- wlc_phy_poll_rssi_nphy(pi, tssi_type, rssi_buf, num_samps);
-
- tssival[0] = rssi_buf[0] / ((s32) num_samps);
- tssival[1] = rssi_buf[2] / ((s32) num_samps);
-
- pwrindex[0] = idle_tssi[0] - tssival[0] + 64;
- pwrindex[1] = idle_tssi[1] - tssival[1] + 64;
-
- if (pwrindex[0] < 0) {
- pwrindex[0] = 0;
- } else if (pwrindex[0] > 63) {
- pwrindex[0] = 63;
- }
-
- if (pwrindex[1] < 0) {
- pwrindex[1] = 0;
- } else if (pwrindex[1] > 63) {
- pwrindex[1] = 63;
- }
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 1,
- (u32) pwrindex[0], 32, &qdBm_pwrbuf[0]);
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 1,
- (u32) pwrindex[1], 32, &qdBm_pwrbuf[1]);
-}
-
-static void wlc_phy_internal_cal_txgain_nphy(phy_info_t *pi)
-{
- u16 txcal_gain[2];
-
- pi->nphy_txcal_pwr_idx[0] = pi->nphy_cal_orig_pwr_idx[0];
- pi->nphy_txcal_pwr_idx[1] = pi->nphy_cal_orig_pwr_idx[0];
- wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_cal_orig_pwr_idx[0], true);
- wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_cal_orig_pwr_idx[1], true);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
- txcal_gain);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- txcal_gain[0] = (txcal_gain[0] & 0xF000) | 0x0F40;
- txcal_gain[1] = (txcal_gain[1] & 0xF000) | 0x0F40;
- } else {
- txcal_gain[0] = (txcal_gain[0] & 0xF000) | 0x0F60;
- txcal_gain[1] = (txcal_gain[1] & 0xF000) | 0x0F60;
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
- txcal_gain);
-}
-
-static void wlc_phy_precal_txgain_nphy(phy_info_t *pi)
-{
- bool save_bbmult = false;
- u8 txcal_index_2057_rev5n7 = 0;
- u8 txcal_index_2057_rev3n4n6 = 10;
-
- if (pi->use_int_tx_iqlo_cal_nphy) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if ((pi->pubpi.radiorev == 3) ||
- (pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
-
- pi->nphy_txcal_pwr_idx[0] =
- txcal_index_2057_rev3n4n6;
- pi->nphy_txcal_pwr_idx[1] =
- txcal_index_2057_rev3n4n6;
- wlc_phy_txpwr_index_nphy(pi, 3,
- txcal_index_2057_rev3n4n6,
- false);
- } else {
-
- pi->nphy_txcal_pwr_idx[0] =
- txcal_index_2057_rev5n7;
- pi->nphy_txcal_pwr_idx[1] =
- txcal_index_2057_rev5n7;
- wlc_phy_txpwr_index_nphy(pi, 3,
- txcal_index_2057_rev5n7,
- false);
- }
- save_bbmult = true;
-
- } else if (NREV_LT(pi->pubpi.phy_rev, 5)) {
- wlc_phy_cal_txgainctrl_nphy(pi, 11, false);
- if (pi->sh->hw_phytxchain != 3) {
- pi->nphy_txcal_pwr_idx[1] =
- pi->nphy_txcal_pwr_idx[0];
- wlc_phy_txpwr_index_nphy(pi, 3,
- pi->
- nphy_txcal_pwr_idx[0],
- true);
- save_bbmult = true;
- }
-
- } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
- if (PHY_IPA(pi)) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- wlc_phy_cal_txgainctrl_nphy(pi, 12,
- false);
- } else {
- pi->nphy_txcal_pwr_idx[0] = 80;
- pi->nphy_txcal_pwr_idx[1] = 80;
- wlc_phy_txpwr_index_nphy(pi, 3, 80,
- false);
- save_bbmult = true;
- }
- } else {
-
- wlc_phy_internal_cal_txgain_nphy(pi);
- save_bbmult = true;
- }
-
- } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
- if (PHY_IPA(pi)) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- wlc_phy_cal_txgainctrl_nphy(pi, 12,
- false);
- } else {
- wlc_phy_cal_txgainctrl_nphy(pi, 14,
- false);
- }
- } else {
-
- wlc_phy_internal_cal_txgain_nphy(pi);
- save_bbmult = true;
- }
- }
-
- } else {
- wlc_phy_cal_txgainctrl_nphy(pi, 10, false);
- }
-
- if (save_bbmult) {
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16,
- &pi->nphy_txcal_bbmult);
- }
-}
-
-void
-wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, s32 dBm_targetpower, bool debug)
-{
- int gainctrl_loopidx;
- uint core;
- u16 m0m1, curr_m0m1;
- s32 delta_power;
- s32 txpwrindex;
- s32 qdBm_power[2];
- u16 orig_BBConfig;
- u16 phy_saveregs[4];
- u32 freq_test;
- u16 ampl_test = 250;
- uint stepsize;
- bool phyhang_avoid_state = false;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- stepsize = 2;
- } else {
-
- stepsize = 1;
- }
-
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- freq_test = 5000;
- } else {
- freq_test = 2500;
- }
-
- wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_cal_orig_pwr_idx[0], true);
- wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_cal_orig_pwr_idx[1], true);
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- phyhang_avoid_state = pi->phyhang_avoid;
- pi->phyhang_avoid = false;
-
- phy_saveregs[0] = read_phy_reg(pi, 0x91);
- phy_saveregs[1] = read_phy_reg(pi, 0x92);
- phy_saveregs[2] = read_phy_reg(pi, 0xe7);
- phy_saveregs[3] = read_phy_reg(pi, 0xec);
- wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_PA, 1,
- RADIO_MIMO_CORESEL_CORE1 |
- RADIO_MIMO_CORESEL_CORE2);
-
- if (!debug) {
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- 0x2, RADIO_MIMO_CORESEL_CORE1);
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- 0x8, RADIO_MIMO_CORESEL_CORE2);
- } else {
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- 0x1, RADIO_MIMO_CORESEL_CORE1);
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- 0x7, RADIO_MIMO_CORESEL_CORE2);
- }
-
- orig_BBConfig = read_phy_reg(pi, 0x01);
- mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
-
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1);
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- txpwrindex = (s32) pi->nphy_cal_orig_pwr_idx[core];
-
- for (gainctrl_loopidx = 0; gainctrl_loopidx < 2;
- gainctrl_loopidx++) {
- wlc_phy_tx_tone_nphy(pi, freq_test, ampl_test, 0, 0,
- false);
-
- if (core == PHY_CORE_0) {
- curr_m0m1 = m0m1 & 0xff00;
- } else {
- curr_m0m1 = m0m1 & 0x00ff;
- }
-
- wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &curr_m0m1);
- wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &curr_m0m1);
-
- udelay(50);
-
- wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
- NPHY_CAL_TSSISAMPS);
-
- pi->nphy_bb_mult_save = 0;
- wlc_phy_stopplayback_nphy(pi);
-
- delta_power = (dBm_targetpower * 4) - qdBm_power[core];
-
- txpwrindex -= stepsize * delta_power;
- if (txpwrindex < 0) {
- txpwrindex = 0;
- } else if (txpwrindex > 127) {
- txpwrindex = 127;
- }
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if (NREV_IS(pi->pubpi.phy_rev, 4) &&
- (pi->srom_fem5g.extpagain == 3)) {
- if (txpwrindex < 30) {
- txpwrindex = 30;
- }
- }
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 5) &&
- (pi->srom_fem2g.extpagain == 3)) {
- if (txpwrindex < 50) {
- txpwrindex = 50;
- }
- }
- }
-
- wlc_phy_txpwr_index_nphy(pi, (1 << core),
- (u8) txpwrindex, true);
- }
-
- pi->nphy_txcal_pwr_idx[core] = (u8) txpwrindex;
-
- if (debug) {
- u16 radio_gain;
- u16 dbg_m0m1;
-
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
-
- wlc_phy_tx_tone_nphy(pi, freq_test, ampl_test, 0, 0,
- false);
-
- wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &dbg_m0m1);
- wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &dbg_m0m1);
-
- udelay(100);
-
- wlc_phy_est_tonepwr_nphy(pi, qdBm_power,
- NPHY_CAL_TSSISAMPS);
-
- wlc_phy_table_read_nphy(pi, 7, 1, (0x110 + core), 16,
- &radio_gain);
-
- mdelay(4000);
- pi->nphy_bb_mult_save = 0;
- wlc_phy_stopplayback_nphy(pi);
- }
- }
-
- wlc_phy_txpwr_index_nphy(pi, 1, pi->nphy_txcal_pwr_idx[0], true);
- wlc_phy_txpwr_index_nphy(pi, 2, pi->nphy_txcal_pwr_idx[1], true);
-
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &pi->nphy_txcal_bbmult);
-
- write_phy_reg(pi, 0x01, orig_BBConfig);
-
- write_phy_reg(pi, 0x91, phy_saveregs[0]);
- write_phy_reg(pi, 0x92, phy_saveregs[1]);
- write_phy_reg(pi, 0xe7, phy_saveregs[2]);
- write_phy_reg(pi, 0xec, phy_saveregs[3]);
-
- pi->phyhang_avoid = phyhang_avoid_state;
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-static void wlc_phy_update_txcal_ladder_nphy(phy_info_t *pi, u16 core)
-{
- int index;
- u32 bbmult_scale;
- u16 bbmult;
- u16 tblentry;
-
- nphy_txiqcal_ladder_t ladder_lo[] = {
- {3, 0}, {4, 0}, {6, 0}, {9, 0}, {13, 0}, {18, 0},
- {25, 0}, {25, 1}, {25, 2}, {25, 3}, {25, 4}, {25, 5},
- {25, 6}, {25, 7}, {35, 7}, {50, 7}, {71, 7}, {100, 7}
- };
-
- nphy_txiqcal_ladder_t ladder_iq[] = {
- {3, 0}, {4, 0}, {6, 0}, {9, 0}, {13, 0}, {18, 0},
- {25, 0}, {35, 0}, {50, 0}, {71, 0}, {100, 0}, {100, 1},
- {100, 2}, {100, 3}, {100, 4}, {100, 5}, {100, 6}, {100, 7}
- };
-
- bbmult = (core == PHY_CORE_0) ?
- ((pi->nphy_txcal_bbmult >> 8) & 0xff) : (pi->
- nphy_txcal_bbmult & 0xff);
-
- for (index = 0; index < 18; index++) {
- bbmult_scale = ladder_lo[index].percent * bbmult;
- bbmult_scale /= 100;
-
- tblentry =
- ((bbmult_scale & 0xff) << 8) | ladder_lo[index].g_env;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, index, 16,
- &tblentry);
-
- bbmult_scale = ladder_iq[index].percent * bbmult;
- bbmult_scale /= 100;
-
- tblentry =
- ((bbmult_scale & 0xff) << 8) | ladder_iq[index].g_env;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 1, index + 32,
- 16, &tblentry);
- }
-}
-
-void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype)
-{
- nphy_txgains_t target_gain;
- u8 tx_pwr_ctrl_state;
- bool fullcal = true;
- bool restore_tx_gain = false;
- bool mphase;
-
- if (NORADIO_ENAB(pi->pubpi)) {
- wlc_phy_cal_perical_mphase_reset(pi);
- return;
- }
-
- if (PHY_MUTED(pi))
- return;
-
- if (caltype == PHY_PERICAL_AUTO)
- fullcal = (pi->radio_chanspec != pi->nphy_txiqlocal_chanspec);
- else if (caltype == PHY_PERICAL_PARTIAL)
- fullcal = false;
-
- if (pi->cal_type_override != PHY_PERICAL_AUTO) {
- fullcal =
- (pi->cal_type_override == PHY_PERICAL_FULL) ? true : false;
- }
-
- if ((pi->mphase_cal_phase_id > MPHASE_CAL_STATE_INIT)) {
- if (pi->nphy_txiqlocal_chanspec != pi->radio_chanspec)
- wlc_phy_cal_perical_mphase_restart(pi);
- }
-
- if ((pi->mphase_cal_phase_id == MPHASE_CAL_STATE_RXCAL)) {
- wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
- }
-
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- wlc_phyreg_enter((wlc_phy_t *) pi);
-
- if ((pi->mphase_cal_phase_id == MPHASE_CAL_STATE_IDLE) ||
- (pi->mphase_cal_phase_id == MPHASE_CAL_STATE_INIT)) {
- pi->nphy_cal_orig_pwr_idx[0] =
- (u8) ((read_phy_reg(pi, 0x1ed) >> 8) & 0x7f);
- pi->nphy_cal_orig_pwr_idx[1] =
- (u8) ((read_phy_reg(pi, 0x1ee) >> 8) & 0x7f);
-
- if (pi->nphy_txpwrctrl != PHY_TPC_HW_OFF) {
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2,
- 0x110, 16,
- pi->nphy_cal_orig_tx_gain);
- } else {
- pi->nphy_cal_orig_tx_gain[0] = 0;
- pi->nphy_cal_orig_tx_gain[1] = 0;
- }
- }
- target_gain = wlc_phy_get_tx_gain_nphy(pi);
- tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
- wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
-
- if (pi->antsel_type == ANTSEL_2x3)
- wlc_phy_antsel_init((wlc_phy_t *) pi, true);
-
- mphase = (pi->mphase_cal_phase_id != MPHASE_CAL_STATE_IDLE);
- if (!mphase) {
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- wlc_phy_precal_txgain_nphy(pi);
- pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi);
- restore_tx_gain = true;
-
- target_gain = pi->nphy_cal_target_gain;
- }
- if (0 ==
- wlc_phy_cal_txiqlo_nphy(pi, target_gain, fullcal, mphase)) {
- if (PHY_IPA(pi))
- wlc_phy_a4(pi, true);
-
- wlc_phyreg_exit((wlc_phy_t *) pi);
- wlapi_enable_mac(pi->sh->physhim);
- wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION,
- 10000);
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- wlc_phyreg_enter((wlc_phy_t *) pi);
-
- if (0 == wlc_phy_cal_rxiq_nphy(pi, target_gain,
- (pi->
- first_cal_after_assoc
- || (pi->
- cal_type_override
- ==
- PHY_PERICAL_FULL))
- ? 2 : 0, false)) {
- wlc_phy_savecal_nphy(pi);
-
- wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
-
- pi->nphy_perical_last = pi->sh->now;
- }
- }
- if (caltype != PHY_PERICAL_AUTO) {
- wlc_phy_rssi_cal_nphy(pi);
- }
-
- if (pi->first_cal_after_assoc
- || (pi->cal_type_override == PHY_PERICAL_FULL)) {
- pi->first_cal_after_assoc = false;
- wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
- wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- wlc_phy_radio205x_vcocal_nphy(pi);
- }
- } else {
- switch (pi->mphase_cal_phase_id) {
- case MPHASE_CAL_STATE_INIT:
- pi->nphy_perical_last = pi->sh->now;
- pi->nphy_txiqlocal_chanspec = pi->radio_chanspec;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- wlc_phy_precal_txgain_nphy(pi);
- }
- pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi);
- pi->mphase_cal_phase_id++;
- break;
-
- case MPHASE_CAL_STATE_TXPHASE0:
- case MPHASE_CAL_STATE_TXPHASE1:
- case MPHASE_CAL_STATE_TXPHASE2:
- case MPHASE_CAL_STATE_TXPHASE3:
- case MPHASE_CAL_STATE_TXPHASE4:
- case MPHASE_CAL_STATE_TXPHASE5:
- if ((pi->radar_percal_mask & 0x10) != 0)
- pi->nphy_rxcal_active = true;
-
- if (wlc_phy_cal_txiqlo_nphy
- (pi, pi->nphy_cal_target_gain, fullcal,
- true) != 0) {
-
- wlc_phy_cal_perical_mphase_reset(pi);
- break;
- }
-
- if (NREV_LE(pi->pubpi.phy_rev, 2) &&
- (pi->mphase_cal_phase_id ==
- MPHASE_CAL_STATE_TXPHASE4)) {
- pi->mphase_cal_phase_id += 2;
- } else {
- pi->mphase_cal_phase_id++;
- }
- break;
-
- case MPHASE_CAL_STATE_PAPDCAL:
- if ((pi->radar_percal_mask & 0x2) != 0)
- pi->nphy_rxcal_active = true;
-
- if (PHY_IPA(pi)) {
- wlc_phy_a4(pi, true);
- }
- pi->mphase_cal_phase_id++;
- break;
-
- case MPHASE_CAL_STATE_RXCAL:
- if ((pi->radar_percal_mask & 0x1) != 0)
- pi->nphy_rxcal_active = true;
- if (wlc_phy_cal_rxiq_nphy(pi, target_gain,
- (pi->first_cal_after_assoc ||
- (pi->cal_type_override ==
- PHY_PERICAL_FULL)) ? 2 : 0,
- false) == 0) {
- wlc_phy_savecal_nphy(pi);
- }
-
- pi->mphase_cal_phase_id++;
- break;
-
- case MPHASE_CAL_STATE_RSSICAL:
- if ((pi->radar_percal_mask & 0x4) != 0)
- pi->nphy_rxcal_active = true;
- wlc_phy_txpwrctrl_coeff_setup_nphy(pi);
- wlc_phy_rssi_cal_nphy(pi);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- wlc_phy_radio205x_vcocal_nphy(pi);
- }
- restore_tx_gain = true;
-
- if (pi->first_cal_after_assoc) {
- pi->mphase_cal_phase_id++;
- } else {
- wlc_phy_cal_perical_mphase_reset(pi);
- }
-
- break;
-
- case MPHASE_CAL_STATE_IDLETSSI:
- if ((pi->radar_percal_mask & 0x8) != 0)
- pi->nphy_rxcal_active = true;
-
- if (pi->first_cal_after_assoc) {
- pi->first_cal_after_assoc = false;
- wlc_phy_txpwrctrl_idle_tssi_nphy(pi);
- wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
- }
-
- wlc_phy_cal_perical_mphase_reset(pi);
- break;
-
- default:
- wlc_phy_cal_perical_mphase_reset(pi);
- break;
- }
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (restore_tx_gain) {
- if (tx_pwr_ctrl_state != PHY_TPC_HW_OFF) {
-
- wlc_phy_txpwr_index_nphy(pi, 1,
- pi->
- nphy_cal_orig_pwr_idx
- [0], false);
- wlc_phy_txpwr_index_nphy(pi, 2,
- pi->
- nphy_cal_orig_pwr_idx
- [1], false);
-
- pi->nphy_txpwrindex[0].index = -1;
- pi->nphy_txpwrindex[1].index = -1;
- } else {
- wlc_phy_txpwr_index_nphy(pi, (1 << 0),
- (s8) (pi->
- nphy_txpwrindex
- [0].
- index_internal),
- false);
- wlc_phy_txpwr_index_nphy(pi, (1 << 1),
- (s8) (pi->
- nphy_txpwrindex
- [1].
- index_internal),
- false);
- }
- }
- }
-
- wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
- wlc_phyreg_exit((wlc_phy_t *) pi);
- wlapi_enable_mac(pi->sh->physhim);
-}
-
-int
-wlc_phy_cal_txiqlo_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
- bool fullcal, bool mphase)
-{
- u16 val;
- u16 tbl_buf[11];
- u8 cal_cnt;
- u16 cal_cmd;
- u8 num_cals, max_cal_cmds;
- u16 core_no, cal_type;
- u16 diq_start = 0;
- u8 phy_bw;
- u16 max_val;
- u16 tone_freq;
- u16 gain_save[2];
- u16 cal_gain[2];
- nphy_iqcal_params_t cal_params[2];
- u32 tbl_len;
- void *tbl_ptr;
- bool ladder_updated[2];
- u8 mphase_cal_lastphase = 0;
- int bcmerror = 0;
- bool phyhang_avoid_state = false;
-
- u16 tbl_tx_iqlo_cal_loft_ladder_20[] = {
- 0x0300, 0x0500, 0x0700, 0x0900, 0x0d00, 0x1100, 0x1900, 0x1901,
- 0x1902,
- 0x1903, 0x1904, 0x1905, 0x1906, 0x1907, 0x2407, 0x3207, 0x4607,
- 0x6407
- };
-
- u16 tbl_tx_iqlo_cal_iqimb_ladder_20[] = {
- 0x0200, 0x0300, 0x0600, 0x0900, 0x0d00, 0x1100, 0x1900, 0x2400,
- 0x3200,
- 0x4600, 0x6400, 0x6401, 0x6402, 0x6403, 0x6404, 0x6405, 0x6406,
- 0x6407
- };
-
- u16 tbl_tx_iqlo_cal_loft_ladder_40[] = {
- 0x0200, 0x0300, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1201,
- 0x1202,
- 0x1203, 0x1204, 0x1205, 0x1206, 0x1207, 0x1907, 0x2307, 0x3207,
- 0x4707
- };
-
- u16 tbl_tx_iqlo_cal_iqimb_ladder_40[] = {
- 0x0100, 0x0200, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1900,
- 0x2300,
- 0x3200, 0x4700, 0x4701, 0x4702, 0x4703, 0x4704, 0x4705, 0x4706,
- 0x4707
- };
-
- u16 tbl_tx_iqlo_cal_startcoefs[] = {
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000
- };
-
- u16 tbl_tx_iqlo_cal_cmds_fullcal[] = {
- 0x8123, 0x8264, 0x8086, 0x8245, 0x8056,
- 0x9123, 0x9264, 0x9086, 0x9245, 0x9056
- };
-
- u16 tbl_tx_iqlo_cal_cmds_recal[] = {
- 0x8101, 0x8253, 0x8053, 0x8234, 0x8034,
- 0x9101, 0x9253, 0x9053, 0x9234, 0x9034
- };
-
- u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[] = {
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- 0x0000
- };
-
- u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = {
- 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234,
- 0x9434, 0x9334, 0x9084, 0x9267, 0x9056, 0x9234
- };
-
- u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = {
- 0x8423, 0x8323, 0x8073, 0x8256, 0x8045, 0x8223,
- 0x9423, 0x9323, 0x9073, 0x9256, 0x9045, 0x9223
- };
-
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- if (NREV_GE(pi->pubpi.phy_rev, 4)) {
- phyhang_avoid_state = pi->phyhang_avoid;
- pi->phyhang_avoid = false;
- }
-
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- phy_bw = 40;
- } else {
- phy_bw = 20;
- }
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
-
- for (core_no = 0; core_no <= 1; core_no++) {
- wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
- &cal_params[core_no]);
- cal_gain[core_no] = cal_params[core_no].cal_gain;
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
-
- wlc_phy_txcal_radio_setup_nphy(pi);
-
- wlc_phy_txcal_physetup_nphy(pi);
-
- ladder_updated[0] = ladder_updated[1] = false;
- if (!(NREV_GE(pi->pubpi.phy_rev, 6) ||
- (NREV_IS(pi->pubpi.phy_rev, 5) && PHY_IPA(pi)
- && (CHSPEC_IS2G(pi->radio_chanspec))))) {
-
- if (phy_bw == 40) {
- tbl_ptr = tbl_tx_iqlo_cal_loft_ladder_40;
- tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_loft_ladder_40);
- } else {
- tbl_ptr = tbl_tx_iqlo_cal_loft_ladder_20;
- tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_loft_ladder_20);
- }
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 0,
- 16, tbl_ptr);
-
- if (phy_bw == 40) {
- tbl_ptr = tbl_tx_iqlo_cal_iqimb_ladder_40;
- tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_iqimb_ladder_40);
- } else {
- tbl_ptr = tbl_tx_iqlo_cal_iqimb_ladder_20;
- tbl_len = ARRAY_SIZE(tbl_tx_iqlo_cal_iqimb_ladder_20);
- }
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 32,
- 16, tbl_ptr);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- write_phy_reg(pi, 0xc2, 0x8ad9);
- } else {
- write_phy_reg(pi, 0xc2, 0x8aa9);
- }
-
- max_val = 250;
- tone_freq = (phy_bw == 20) ? 2500 : 5000;
-
- if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
- wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff, 0, 1, 0, false);
- bcmerror = 0;
- } else {
- bcmerror =
- wlc_phy_tx_tone_nphy(pi, tone_freq, max_val, 1, 0, false);
- }
-
- if (bcmerror == 0) {
-
- if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
- tbl_ptr = pi->mphase_txcal_bestcoeffs;
- tbl_len = ARRAY_SIZE(pi->mphase_txcal_bestcoeffs);
- if (NREV_LT(pi->pubpi.phy_rev, 3)) {
-
- tbl_len -= 2;
- }
- } else {
- if ((!fullcal) && (pi->nphy_txiqlocal_coeffsvalid)) {
-
- tbl_ptr = pi->nphy_txiqlocal_bestc;
- tbl_len = ARRAY_SIZE(pi->nphy_txiqlocal_bestc);
- if (NREV_LT(pi->pubpi.phy_rev, 3)) {
-
- tbl_len -= 2;
- }
- } else {
-
- fullcal = true;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- tbl_ptr =
- tbl_tx_iqlo_cal_startcoefs_nphyrev3;
- tbl_len =
- ARRAY_SIZE
- (tbl_tx_iqlo_cal_startcoefs_nphyrev3);
- } else {
- tbl_ptr = tbl_tx_iqlo_cal_startcoefs;
- tbl_len =
- ARRAY_SIZE
- (tbl_tx_iqlo_cal_startcoefs);
- }
- }
- }
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, tbl_len, 64,
- 16, tbl_ptr);
-
- if (fullcal) {
- max_cal_cmds = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
- ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3) :
- ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_fullcal);
- } else {
- max_cal_cmds = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
- ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_recal_nphyrev3) :
- ARRAY_SIZE(tbl_tx_iqlo_cal_cmds_recal);
- }
-
- if (mphase) {
- cal_cnt = pi->mphase_txcal_cmdidx;
- if ((cal_cnt + pi->mphase_txcal_numcmds) < max_cal_cmds) {
- num_cals = cal_cnt + pi->mphase_txcal_numcmds;
- } else {
- num_cals = max_cal_cmds;
- }
- } else {
- cal_cnt = 0;
- num_cals = max_cal_cmds;
- }
-
- for (; cal_cnt < num_cals; cal_cnt++) {
-
- if (fullcal) {
- cal_cmd = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
- tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3
- [cal_cnt] :
- tbl_tx_iqlo_cal_cmds_fullcal[cal_cnt];
- } else {
- cal_cmd = (NREV_GE(pi->pubpi.phy_rev, 3)) ?
- tbl_tx_iqlo_cal_cmds_recal_nphyrev3[cal_cnt]
- : tbl_tx_iqlo_cal_cmds_recal[cal_cnt];
- }
-
- core_no = ((cal_cmd & 0x3000) >> 12);
- cal_type = ((cal_cmd & 0x0F00) >> 8);
-
- if (NREV_GE(pi->pubpi.phy_rev, 6) ||
- (NREV_IS(pi->pubpi.phy_rev, 5) &&
- PHY_IPA(pi)
- && (CHSPEC_IS2G(pi->radio_chanspec)))) {
- if (!ladder_updated[core_no]) {
- wlc_phy_update_txcal_ladder_nphy(pi,
- core_no);
- ladder_updated[core_no] = true;
- }
- }
-
- val =
- (cal_params[core_no].
- ncorr[cal_type] << 8) | NPHY_N_GCTL;
- write_phy_reg(pi, 0xc1, val);
-
- if ((cal_type == 1) || (cal_type == 3)
- || (cal_type == 4)) {
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
- 1, 69 + core_no, 16,
- tbl_buf);
-
- diq_start = tbl_buf[0];
-
- tbl_buf[0] = 0;
- wlc_phy_table_write_nphy(pi,
- NPHY_TBL_ID_IQLOCAL, 1,
- 69 + core_no, 16,
- tbl_buf);
- }
-
- write_phy_reg(pi, 0xc0, cal_cmd);
-
- SPINWAIT(((read_phy_reg(pi, 0xc0) & 0xc000) != 0),
- 20000);
- if (WARN(read_phy_reg(pi, 0xc0) & 0xc000,
- "HW error: txiq calib"))
- return -EIO;
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
- tbl_len, 96, 16, tbl_buf);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL,
- tbl_len, 64, 16, tbl_buf);
-
- if ((cal_type == 1) || (cal_type == 3)
- || (cal_type == 4)) {
-
- tbl_buf[0] = diq_start;
-
- }
-
- }
-
- if (mphase) {
- pi->mphase_txcal_cmdidx = num_cals;
- if (pi->mphase_txcal_cmdidx >= max_cal_cmds)
- pi->mphase_txcal_cmdidx = 0;
- }
-
- mphase_cal_lastphase =
- (NREV_LE(pi->pubpi.phy_rev, 2)) ?
- MPHASE_CAL_STATE_TXPHASE4 : MPHASE_CAL_STATE_TXPHASE5;
-
- if (!mphase
- || (pi->mphase_cal_phase_id == mphase_cal_lastphase)) {
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 96,
- 16, tbl_buf);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80,
- 16, tbl_buf);
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
-
- tbl_buf[0] = 0;
- tbl_buf[1] = 0;
- tbl_buf[2] = 0;
- tbl_buf[3] = 0;
-
- }
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88,
- 16, tbl_buf);
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 101,
- 16, tbl_buf);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85,
- 16, tbl_buf);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93,
- 16, tbl_buf);
-
- tbl_len = ARRAY_SIZE(pi->nphy_txiqlocal_bestc);
- if (NREV_LT(pi->pubpi.phy_rev, 3)) {
-
- tbl_len -= 2;
- }
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
- tbl_len, 96, 16,
- pi->nphy_txiqlocal_bestc);
-
- pi->nphy_txiqlocal_coeffsvalid = true;
- pi->nphy_txiqlocal_chanspec = pi->radio_chanspec;
- } else {
- tbl_len = ARRAY_SIZE(pi->mphase_txcal_bestcoeffs);
- if (NREV_LT(pi->pubpi.phy_rev, 3)) {
-
- tbl_len -= 2;
- }
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
- tbl_len, 96, 16,
- pi->mphase_txcal_bestcoeffs);
- }
-
- wlc_phy_stopplayback_nphy(pi);
-
- write_phy_reg(pi, 0xc2, 0x0000);
-
- }
-
- wlc_phy_txcal_phycleanup_nphy(pi);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
- gain_save);
-
- wlc_phy_txcal_radio_cleanup_nphy(pi);
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
- if (!mphase
- || (pi->mphase_cal_phase_id == mphase_cal_lastphase))
- wlc_phy_tx_iq_war_nphy(pi);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 4)) {
- pi->phyhang_avoid = phyhang_avoid_state;
- }
-
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-
- return bcmerror;
-}
-
-static void wlc_phy_reapply_txcal_coeffs_nphy(phy_info_t *pi)
-{
- u16 tbl_buf[7];
-
- if ((pi->nphy_txiqlocal_chanspec == pi->radio_chanspec) &&
- (pi->nphy_txiqlocal_coeffsvalid)) {
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
- ARRAY_SIZE(tbl_buf), 80, 16, tbl_buf);
-
- if ((pi->nphy_txiqlocal_bestc[0] != tbl_buf[0]) ||
- (pi->nphy_txiqlocal_bestc[1] != tbl_buf[1]) ||
- (pi->nphy_txiqlocal_bestc[2] != tbl_buf[2]) ||
- (pi->nphy_txiqlocal_bestc[3] != tbl_buf[3])) {
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 80,
- 16, pi->nphy_txiqlocal_bestc);
-
- tbl_buf[0] = 0;
- tbl_buf[1] = 0;
- tbl_buf[2] = 0;
- tbl_buf[3] = 0;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 4, 88,
- 16, tbl_buf);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 85,
- 16,
- &pi->nphy_txiqlocal_bestc[5]);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_IQLOCAL, 2, 93,
- 16,
- &pi->nphy_txiqlocal_bestc[5]);
- }
- }
-}
-
-static void wlc_phy_tx_iq_war_nphy(phy_info_t *pi)
-{
- nphy_iq_comp_t tx_comp;
-
- wlc_phy_table_read_nphy(pi, 15, 4, 0x50, 16, (void *)&tx_comp);
-
- wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ, tx_comp.a0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 2, tx_comp.b0);
- wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 4, tx_comp.a1);
- wlapi_bmac_write_shm(pi->sh->physhim, M_20IN40_IQ + 6, tx_comp.b1);
-}
-
-void
-wlc_phy_rx_iq_coeffs_nphy(phy_info_t *pi, u8 write, nphy_iq_comp_t *pcomp)
-{
- if (write) {
- write_phy_reg(pi, 0x9a, pcomp->a0);
- write_phy_reg(pi, 0x9b, pcomp->b0);
- write_phy_reg(pi, 0x9c, pcomp->a1);
- write_phy_reg(pi, 0x9d, pcomp->b1);
- } else {
- pcomp->a0 = read_phy_reg(pi, 0x9a);
- pcomp->b0 = read_phy_reg(pi, 0x9b);
- pcomp->a1 = read_phy_reg(pi, 0x9c);
- pcomp->b1 = read_phy_reg(pi, 0x9d);
- }
-}
-
-void
-wlc_phy_rx_iq_est_nphy(phy_info_t *pi, phy_iq_est_t *est, u16 num_samps,
- u8 wait_time, u8 wait_for_crs)
-{
- u8 core;
-
- write_phy_reg(pi, 0x12b, num_samps);
- mod_phy_reg(pi, 0x12a, (0xff << 0), (wait_time << 0));
- mod_phy_reg(pi, 0x129, NPHY_IqestCmd_iqMode,
- (wait_for_crs) ? NPHY_IqestCmd_iqMode : 0);
-
- mod_phy_reg(pi, 0x129, NPHY_IqestCmd_iqstart, NPHY_IqestCmd_iqstart);
-
- SPINWAIT(((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) != 0),
- 10000);
- if (WARN(read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart,
- "HW error: rxiq est"))
- return;
-
- if ((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) == 0) {
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- est[core].i_pwr =
- (read_phy_reg(pi, NPHY_IqestipwrAccHi(core)) << 16)
- | read_phy_reg(pi, NPHY_IqestipwrAccLo(core));
- est[core].q_pwr =
- (read_phy_reg(pi, NPHY_IqestqpwrAccHi(core)) << 16)
- | read_phy_reg(pi, NPHY_IqestqpwrAccLo(core));
- est[core].iq_prod =
- (read_phy_reg(pi, NPHY_IqestIqAccHi(core)) << 16) |
- read_phy_reg(pi, NPHY_IqestIqAccLo(core));
- }
- }
-}
-
-#define CAL_RETRY_CNT 2
-static void wlc_phy_calc_rx_iq_comp_nphy(phy_info_t *pi, u8 core_mask)
-{
- u8 curr_core;
- phy_iq_est_t est[PHY_CORE_MAX];
- nphy_iq_comp_t old_comp, new_comp;
- s32 iq = 0;
- u32 ii = 0, qq = 0;
- s16 iq_nbits, qq_nbits, brsh, arsh;
- s32 a, b, temp;
- int bcmerror = 0;
- uint cal_retry = 0;
-
- if (core_mask == 0x0)
- return;
-
- wlc_phy_rx_iq_coeffs_nphy(pi, 0, &old_comp);
- new_comp.a0 = new_comp.b0 = new_comp.a1 = new_comp.b1 = 0x0;
- wlc_phy_rx_iq_coeffs_nphy(pi, 1, &new_comp);
-
- cal_try:
- wlc_phy_rx_iq_est_nphy(pi, est, 0x4000, 32, 0);
-
- new_comp = old_comp;
-
- for (curr_core = 0; curr_core < pi->pubpi.phy_corenum; curr_core++) {
-
- if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
- iq = est[curr_core].iq_prod;
- ii = est[curr_core].i_pwr;
- qq = est[curr_core].q_pwr;
- } else if ((curr_core == PHY_CORE_1) && (core_mask & 0x2)) {
- iq = est[curr_core].iq_prod;
- ii = est[curr_core].i_pwr;
- qq = est[curr_core].q_pwr;
- } else {
- continue;
- }
-
- if ((ii + qq) < NPHY_MIN_RXIQ_PWR) {
- bcmerror = -EBADE;
- break;
- }
-
- iq_nbits = wlc_phy_nbits(iq);
- qq_nbits = wlc_phy_nbits(qq);
-
- arsh = 10 - (30 - iq_nbits);
- if (arsh >= 0) {
- a = (-(iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
- temp = (s32) (ii >> arsh);
- if (temp == 0) {
- bcmerror = -EBADE;
- break;
- }
- } else {
- a = (-(iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
- temp = (s32) (ii << -arsh);
- if (temp == 0) {
- bcmerror = -EBADE;
- break;
- }
- }
-
- a /= temp;
-
- brsh = qq_nbits - 31 + 20;
- if (brsh >= 0) {
- b = (qq << (31 - qq_nbits));
- temp = (s32) (ii >> brsh);
- if (temp == 0) {
- bcmerror = -EBADE;
- break;
- }
- } else {
- b = (qq << (31 - qq_nbits));
- temp = (s32) (ii << -brsh);
- if (temp == 0) {
- bcmerror = -EBADE;
- break;
- }
- }
- b /= temp;
- b -= a * a;
- b = (s32) int_sqrt((unsigned long) b);
- b -= (1 << 10);
-
- if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- new_comp.a0 = (s16) a & 0x3ff;
- new_comp.b0 = (s16) b & 0x3ff;
- } else {
-
- new_comp.a0 = (s16) b & 0x3ff;
- new_comp.b0 = (s16) a & 0x3ff;
- }
- }
- if ((curr_core == PHY_CORE_1) && (core_mask & 0x2)) {
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- new_comp.a1 = (s16) a & 0x3ff;
- new_comp.b1 = (s16) b & 0x3ff;
- } else {
-
- new_comp.a1 = (s16) b & 0x3ff;
- new_comp.b1 = (s16) a & 0x3ff;
- }
- }
- }
-
- if (bcmerror != 0) {
- printk("%s: Failed, cnt = %d\n", __func__, cal_retry);
-
- if (cal_retry < CAL_RETRY_CNT) {
- cal_retry++;
- goto cal_try;
- }
-
- new_comp = old_comp;
- } else if (cal_retry > 0) {
- }
-
- wlc_phy_rx_iq_coeffs_nphy(pi, 1, &new_comp);
-}
-
-static void wlc_phy_rxcal_radio_setup_nphy(phy_info_t *pi, u8 rx_core)
-{
- u16 offtune_val;
- u16 bias_g = 0;
- u16 bias_a = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (rx_core == PHY_CORE_0) {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- pi->tx_rx_cal_radio_saveregs[0] =
- read_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP);
- pi->tx_rx_cal_radio_saveregs[1] =
- read_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN);
-
- write_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP,
- 0x3);
- write_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN,
- 0xaf);
-
- } else {
- pi->tx_rx_cal_radio_saveregs[0] =
- read_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP);
- pi->tx_rx_cal_radio_saveregs[1] =
- read_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN);
-
- write_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP,
- 0x3);
- write_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN,
- 0x7f);
- }
-
- } else {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- pi->tx_rx_cal_radio_saveregs[0] =
- read_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP);
- pi->tx_rx_cal_radio_saveregs[1] =
- read_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN);
-
- write_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP,
- 0x3);
- write_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN,
- 0xaf);
-
- } else {
- pi->tx_rx_cal_radio_saveregs[0] =
- read_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP);
- pi->tx_rx_cal_radio_saveregs[1] =
- read_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN);
-
- write_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP,
- 0x3);
- write_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN,
- 0x7f);
- }
- }
-
- } else {
- if (rx_core == PHY_CORE_0) {
- pi->tx_rx_cal_radio_saveregs[0] =
- read_radio_reg(pi,
- RADIO_2056_TX_RXIQCAL_TXMUX |
- RADIO_2056_TX1);
- pi->tx_rx_cal_radio_saveregs[1] =
- read_radio_reg(pi,
- RADIO_2056_RX_RXIQCAL_RXMUX |
- RADIO_2056_RX0);
-
- if (pi->pubpi.radiorev >= 5) {
- pi->tx_rx_cal_radio_saveregs[2] =
- read_radio_reg(pi,
- RADIO_2056_RX_RXSPARE2 |
- RADIO_2056_RX0);
- pi->tx_rx_cal_radio_saveregs[3] =
- read_radio_reg(pi,
- RADIO_2056_TX_TXSPARE2 |
- RADIO_2056_TX1);
- }
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
-
- if (pi->pubpi.radiorev >= 5) {
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi,
- RADIO_2056_RX_LNAA_MASTER
- | RADIO_2056_RX0);
-
- write_radio_reg(pi,
- RADIO_2056_RX_LNAA_MASTER
- | RADIO_2056_RX0, 0x40);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TXSPARE2 |
- RADIO_2056_TX1, bias_a);
-
- write_radio_reg(pi,
- RADIO_2056_RX_RXSPARE2 |
- RADIO_2056_RX0, bias_a);
- } else {
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi,
- RADIO_2056_RX_LNAA_TUNE
- | RADIO_2056_RX0);
-
- offtune_val =
- (pi->
- tx_rx_cal_radio_saveregs[2] & 0xF0)
- >> 8;
- offtune_val =
- (offtune_val <= 0x7) ? 0xF : 0;
-
- mod_radio_reg(pi,
- RADIO_2056_RX_LNAA_TUNE |
- RADIO_2056_RX0, 0xF0,
- (offtune_val << 8));
- }
-
- write_radio_reg(pi,
- RADIO_2056_TX_RXIQCAL_TXMUX |
- RADIO_2056_TX1, 0x9);
- write_radio_reg(pi,
- RADIO_2056_RX_RXIQCAL_RXMUX |
- RADIO_2056_RX0, 0x9);
- } else {
- if (pi->pubpi.radiorev >= 5) {
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi,
- RADIO_2056_RX_LNAG_MASTER
- | RADIO_2056_RX0);
-
- write_radio_reg(pi,
- RADIO_2056_RX_LNAG_MASTER
- | RADIO_2056_RX0, 0x40);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TXSPARE2 |
- RADIO_2056_TX1, bias_g);
-
- write_radio_reg(pi,
- RADIO_2056_RX_RXSPARE2 |
- RADIO_2056_RX0, bias_g);
-
- } else {
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi,
- RADIO_2056_RX_LNAG_TUNE
- | RADIO_2056_RX0);
-
- offtune_val =
- (pi->
- tx_rx_cal_radio_saveregs[2] & 0xF0)
- >> 8;
- offtune_val =
- (offtune_val <= 0x7) ? 0xF : 0;
-
- mod_radio_reg(pi,
- RADIO_2056_RX_LNAG_TUNE |
- RADIO_2056_RX0, 0xF0,
- (offtune_val << 8));
- }
-
- write_radio_reg(pi,
- RADIO_2056_TX_RXIQCAL_TXMUX |
- RADIO_2056_TX1, 0x6);
- write_radio_reg(pi,
- RADIO_2056_RX_RXIQCAL_RXMUX |
- RADIO_2056_RX0, 0x6);
- }
-
- } else {
- pi->tx_rx_cal_radio_saveregs[0] =
- read_radio_reg(pi,
- RADIO_2056_TX_RXIQCAL_TXMUX |
- RADIO_2056_TX0);
- pi->tx_rx_cal_radio_saveregs[1] =
- read_radio_reg(pi,
- RADIO_2056_RX_RXIQCAL_RXMUX |
- RADIO_2056_RX1);
-
- if (pi->pubpi.radiorev >= 5) {
- pi->tx_rx_cal_radio_saveregs[2] =
- read_radio_reg(pi,
- RADIO_2056_RX_RXSPARE2 |
- RADIO_2056_RX1);
- pi->tx_rx_cal_radio_saveregs[3] =
- read_radio_reg(pi,
- RADIO_2056_TX_TXSPARE2 |
- RADIO_2056_TX0);
- }
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
-
- if (pi->pubpi.radiorev >= 5) {
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi,
- RADIO_2056_RX_LNAA_MASTER
- | RADIO_2056_RX1);
-
- write_radio_reg(pi,
- RADIO_2056_RX_LNAA_MASTER
- | RADIO_2056_RX1, 0x40);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TXSPARE2 |
- RADIO_2056_TX0, bias_a);
-
- write_radio_reg(pi,
- RADIO_2056_RX_RXSPARE2 |
- RADIO_2056_RX1, bias_a);
- } else {
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi,
- RADIO_2056_RX_LNAA_TUNE
- | RADIO_2056_RX1);
-
- offtune_val =
- (pi->
- tx_rx_cal_radio_saveregs[2] & 0xF0)
- >> 8;
- offtune_val =
- (offtune_val <= 0x7) ? 0xF : 0;
-
- mod_radio_reg(pi,
- RADIO_2056_RX_LNAA_TUNE |
- RADIO_2056_RX1, 0xF0,
- (offtune_val << 8));
- }
-
- write_radio_reg(pi,
- RADIO_2056_TX_RXIQCAL_TXMUX |
- RADIO_2056_TX0, 0x9);
- write_radio_reg(pi,
- RADIO_2056_RX_RXIQCAL_RXMUX |
- RADIO_2056_RX1, 0x9);
- } else {
- if (pi->pubpi.radiorev >= 5) {
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi,
- RADIO_2056_RX_LNAG_MASTER
- | RADIO_2056_RX1);
-
- write_radio_reg(pi,
- RADIO_2056_RX_LNAG_MASTER
- | RADIO_2056_RX1, 0x40);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TXSPARE2 |
- RADIO_2056_TX0, bias_g);
-
- write_radio_reg(pi,
- RADIO_2056_RX_RXSPARE2 |
- RADIO_2056_RX1, bias_g);
- } else {
- pi->tx_rx_cal_radio_saveregs[4] =
- read_radio_reg(pi,
- RADIO_2056_RX_LNAG_TUNE
- | RADIO_2056_RX1);
-
- offtune_val =
- (pi->
- tx_rx_cal_radio_saveregs[2] & 0xF0)
- >> 8;
- offtune_val =
- (offtune_val <= 0x7) ? 0xF : 0;
-
- mod_radio_reg(pi,
- RADIO_2056_RX_LNAG_TUNE |
- RADIO_2056_RX1, 0xF0,
- (offtune_val << 8));
- }
-
- write_radio_reg(pi,
- RADIO_2056_TX_RXIQCAL_TXMUX |
- RADIO_2056_TX0, 0x6);
- write_radio_reg(pi,
- RADIO_2056_RX_RXIQCAL_RXMUX |
- RADIO_2056_RX1, 0x6);
- }
- }
- }
-}
-
-static void wlc_phy_rxcal_radio_cleanup_nphy(phy_info_t *pi, u8 rx_core)
-{
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (rx_core == PHY_CORE_0) {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- write_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP,
- pi->
- tx_rx_cal_radio_saveregs[0]);
- write_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN,
- pi->
- tx_rx_cal_radio_saveregs[1]);
-
- } else {
- write_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP,
- pi->
- tx_rx_cal_radio_saveregs[0]);
- write_radio_reg(pi,
- RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN,
- pi->
- tx_rx_cal_radio_saveregs[1]);
- }
-
- } else {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- write_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP,
- pi->
- tx_rx_cal_radio_saveregs[0]);
- write_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN,
- pi->
- tx_rx_cal_radio_saveregs[1]);
-
- } else {
- write_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP,
- pi->
- tx_rx_cal_radio_saveregs[0]);
- write_radio_reg(pi,
- RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN,
- pi->
- tx_rx_cal_radio_saveregs[1]);
- }
- }
-
- } else {
- if (rx_core == PHY_CORE_0) {
- write_radio_reg(pi,
- RADIO_2056_TX_RXIQCAL_TXMUX |
- RADIO_2056_TX1,
- pi->tx_rx_cal_radio_saveregs[0]);
-
- write_radio_reg(pi,
- RADIO_2056_RX_RXIQCAL_RXMUX |
- RADIO_2056_RX0,
- pi->tx_rx_cal_radio_saveregs[1]);
-
- if (pi->pubpi.radiorev >= 5) {
- write_radio_reg(pi,
- RADIO_2056_RX_RXSPARE2 |
- RADIO_2056_RX0,
- pi->
- tx_rx_cal_radio_saveregs[2]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TXSPARE2 |
- RADIO_2056_TX1,
- pi->
- tx_rx_cal_radio_saveregs[3]);
- }
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if (pi->pubpi.radiorev >= 5) {
- write_radio_reg(pi,
- RADIO_2056_RX_LNAA_MASTER
- | RADIO_2056_RX0,
- pi->
- tx_rx_cal_radio_saveregs
- [4]);
- } else {
- write_radio_reg(pi,
- RADIO_2056_RX_LNAA_TUNE
- | RADIO_2056_RX0,
- pi->
- tx_rx_cal_radio_saveregs
- [4]);
- }
- } else {
- if (pi->pubpi.radiorev >= 5) {
- write_radio_reg(pi,
- RADIO_2056_RX_LNAG_MASTER
- | RADIO_2056_RX0,
- pi->
- tx_rx_cal_radio_saveregs
- [4]);
- } else {
- write_radio_reg(pi,
- RADIO_2056_RX_LNAG_TUNE
- | RADIO_2056_RX0,
- pi->
- tx_rx_cal_radio_saveregs
- [4]);
- }
- }
-
- } else {
- write_radio_reg(pi,
- RADIO_2056_TX_RXIQCAL_TXMUX |
- RADIO_2056_TX0,
- pi->tx_rx_cal_radio_saveregs[0]);
-
- write_radio_reg(pi,
- RADIO_2056_RX_RXIQCAL_RXMUX |
- RADIO_2056_RX1,
- pi->tx_rx_cal_radio_saveregs[1]);
-
- if (pi->pubpi.radiorev >= 5) {
- write_radio_reg(pi,
- RADIO_2056_RX_RXSPARE2 |
- RADIO_2056_RX1,
- pi->
- tx_rx_cal_radio_saveregs[2]);
-
- write_radio_reg(pi,
- RADIO_2056_TX_TXSPARE2 |
- RADIO_2056_TX0,
- pi->
- tx_rx_cal_radio_saveregs[3]);
- }
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if (pi->pubpi.radiorev >= 5) {
- write_radio_reg(pi,
- RADIO_2056_RX_LNAA_MASTER
- | RADIO_2056_RX1,
- pi->
- tx_rx_cal_radio_saveregs
- [4]);
- } else {
- write_radio_reg(pi,
- RADIO_2056_RX_LNAA_TUNE
- | RADIO_2056_RX1,
- pi->
- tx_rx_cal_radio_saveregs
- [4]);
- }
- } else {
- if (pi->pubpi.radiorev >= 5) {
- write_radio_reg(pi,
- RADIO_2056_RX_LNAG_MASTER
- | RADIO_2056_RX1,
- pi->
- tx_rx_cal_radio_saveregs
- [4]);
- } else {
- write_radio_reg(pi,
- RADIO_2056_RX_LNAG_TUNE
- | RADIO_2056_RX1,
- pi->
- tx_rx_cal_radio_saveregs
- [4]);
- }
- }
- }
- }
-}
-
-static void wlc_phy_rxcal_physetup_nphy(phy_info_t *pi, u8 rx_core)
-{
- u8 tx_core;
- u16 rx_antval, tx_antval;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- tx_core = rx_core;
- } else {
- tx_core = (rx_core == PHY_CORE_0) ? 1 : 0;
- }
-
- pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 0xa2);
- pi->tx_rx_cal_phy_saveregs[1] =
- read_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 : 0xa7);
- pi->tx_rx_cal_phy_saveregs[2] =
- read_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5);
- pi->tx_rx_cal_phy_saveregs[3] = read_phy_reg(pi, 0x91);
- pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 0x92);
- pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 0x7a);
- pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 0x7d);
- pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 0xe7);
- pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 0xec);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- pi->tx_rx_cal_phy_saveregs[11] = read_phy_reg(pi, 0x342);
- pi->tx_rx_cal_phy_saveregs[12] = read_phy_reg(pi, 0x343);
- pi->tx_rx_cal_phy_saveregs[13] = read_phy_reg(pi, 0x346);
- pi->tx_rx_cal_phy_saveregs[14] = read_phy_reg(pi, 0x347);
- }
-
- pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 0x297);
- pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 0x29b);
- mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (0) << 0);
-
- mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (0) << 0);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
-
- mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << (1 - rx_core)) << 12);
-
- } else {
-
- mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << tx_core) << 12);
- mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
- mod_phy_reg(pi, 0xa2, (0xf << 4), (1 << rx_core) << 4);
- mod_phy_reg(pi, 0xa2, (0xf << 8), (1 << rx_core) << 8);
- }
-
- mod_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7), (0x1 << 2), 0);
- mod_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5,
- (0x1 << 2), (0x1 << 2));
- if (NREV_LT(pi->pubpi.phy_rev, 7)) {
- mod_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7),
- (0x1 << 0) | (0x1 << 1), 0);
- mod_phy_reg(pi, (rx_core == PHY_CORE_0) ?
- 0x8f : 0xa5,
- (0x1 << 0) | (0x1 << 1), (0x1 << 0) | (0x1 << 1));
- }
-
- wlc_phy_rfctrlintc_override_nphy(pi, NPHY_RfctrlIntc_override_PA, 0,
- RADIO_MIMO_CORESEL_CORE1 |
- RADIO_MIMO_CORESEL_CORE2);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
- 0, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 0, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 1, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 1, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi,
- (0x1 << 7),
- 2, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- } else {
- wlc_phy_rfctrl_override_nphy_rev7(pi,
- (0x1 << 7),
- 0, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- }
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
- 0, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 0, 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- } else {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 3, 0);
- }
-
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RX2TX);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- 0x1, rx_core + 1);
- } else {
-
- if (rx_core == PHY_CORE_0) {
- rx_antval = 0x1;
- tx_antval = 0x8;
- } else {
- rx_antval = 0x4;
- tx_antval = 0x2;
- }
-
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- rx_antval, rx_core + 1);
- wlc_phy_rfctrlintc_override_nphy(pi,
- NPHY_RfctrlIntc_override_TRSW,
- tx_antval, tx_core + 1);
- }
-}
-
-static void wlc_phy_rxcal_phycleanup_nphy(phy_info_t *pi, u8 rx_core)
-{
-
- write_phy_reg(pi, 0xa2, pi->tx_rx_cal_phy_saveregs[0]);
- write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 : 0xa7,
- pi->tx_rx_cal_phy_saveregs[1]);
- write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x8f : 0xa5,
- pi->tx_rx_cal_phy_saveregs[2]);
- write_phy_reg(pi, 0x91, pi->tx_rx_cal_phy_saveregs[3]);
- write_phy_reg(pi, 0x92, pi->tx_rx_cal_phy_saveregs[4]);
-
- write_phy_reg(pi, 0x7a, pi->tx_rx_cal_phy_saveregs[5]);
- write_phy_reg(pi, 0x7d, pi->tx_rx_cal_phy_saveregs[6]);
- write_phy_reg(pi, 0xe7, pi->tx_rx_cal_phy_saveregs[7]);
- write_phy_reg(pi, 0xec, pi->tx_rx_cal_phy_saveregs[8]);
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- write_phy_reg(pi, 0x342, pi->tx_rx_cal_phy_saveregs[11]);
- write_phy_reg(pi, 0x343, pi->tx_rx_cal_phy_saveregs[12]);
- write_phy_reg(pi, 0x346, pi->tx_rx_cal_phy_saveregs[13]);
- write_phy_reg(pi, 0x347, pi->tx_rx_cal_phy_saveregs[14]);
- }
-
- write_phy_reg(pi, 0x297, pi->tx_rx_cal_phy_saveregs[9]);
- write_phy_reg(pi, 0x29b, pi->tx_rx_cal_phy_saveregs[10]);
-}
-
-static void
-wlc_phy_rxcal_gainctrl_nphy_rev5(phy_info_t *pi, u8 rx_core,
- u16 *rxgain, u8 cal_type)
-{
-
- u16 num_samps;
- phy_iq_est_t est[PHY_CORE_MAX];
- u8 tx_core;
- nphy_iq_comp_t save_comp, zero_comp;
- u32 i_pwr, q_pwr, curr_pwr, optim_pwr = 0, prev_pwr = 0, thresh_pwr =
- 10000;
- s16 desired_log2_pwr, actual_log2_pwr, delta_pwr;
- bool gainctrl_done = false;
- u8 mix_tia_gain = 3;
- s8 optim_gaintbl_index = 0, prev_gaintbl_index = 0;
- s8 curr_gaintbl_index = 3;
- u8 gainctrl_dirn = NPHY_RXCAL_GAIN_INIT;
- nphy_ipa_txrxgain_t *nphy_rxcal_gaintbl;
- u16 hpvga, lpf_biq1, lpf_biq0, lna2, lna1;
- int fine_gain_idx;
- s8 txpwrindex;
- u16 nphy_rxcal_txgain[2];
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- tx_core = rx_core;
- } else {
- tx_core = 1 - rx_core;
- }
-
- num_samps = 1024;
- desired_log2_pwr = (cal_type == 0) ? 13 : 13;
-
- wlc_phy_rx_iq_coeffs_nphy(pi, 0, &save_comp);
- zero_comp.a0 = zero_comp.b0 = zero_comp.a1 = zero_comp.b1 = 0x0;
- wlc_phy_rx_iq_coeffs_nphy(pi, 1, &zero_comp);
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- mix_tia_gain = 3;
- } else if (NREV_GE(pi->pubpi.phy_rev, 4)) {
- mix_tia_gain = 4;
- } else {
- mix_tia_gain = 6;
- }
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_5GHz_rev7;
- } else {
- nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_5GHz;
- }
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_2GHz_rev7;
- } else {
- nphy_rxcal_gaintbl = nphy_ipa_rxcal_gaintbl_2GHz;
- }
- }
-
- do {
-
- hpvga = (NREV_GE(pi->pubpi.phy_rev, 7)) ?
- 0 : nphy_rxcal_gaintbl[curr_gaintbl_index].hpvga;
- lpf_biq1 = nphy_rxcal_gaintbl[curr_gaintbl_index].lpf_biq1;
- lpf_biq0 = nphy_rxcal_gaintbl[curr_gaintbl_index].lpf_biq0;
- lna2 = nphy_rxcal_gaintbl[curr_gaintbl_index].lna2;
- lna1 = nphy_rxcal_gaintbl[curr_gaintbl_index].lna1;
- txpwrindex = nphy_rxcal_gaintbl[curr_gaintbl_index].txpwrindex;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_rxgain,
- ((lpf_biq1 << 12) |
- (lpf_biq0 << 8) |
- (mix_tia_gain <<
- 4) | (lna2 << 2)
- | lna1), 0x3, 0);
- } else {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12),
- ((hpvga << 12) |
- (lpf_biq1 << 10) |
- (lpf_biq0 << 8) |
- (mix_tia_gain << 4) |
- (lna2 << 2) | lna1), 0x3,
- 0);
- }
-
- pi->nphy_rxcal_pwr_idx[tx_core] = txpwrindex;
-
- if (txpwrindex == -1) {
- nphy_rxcal_txgain[0] = 0x8ff0 | pi->nphy_gmval;
- nphy_rxcal_txgain[1] = 0x8ff0 | pi->nphy_gmval;
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ,
- 2, 0x110, 16,
- nphy_rxcal_txgain);
- } else {
- wlc_phy_txpwr_index_nphy(pi, tx_core + 1, txpwrindex,
- false);
- }
-
- wlc_phy_tx_tone_nphy(pi, (CHSPEC_IS40(pi->radio_chanspec)) ?
- NPHY_RXCAL_TONEFREQ_40MHz :
- NPHY_RXCAL_TONEFREQ_20MHz,
- NPHY_RXCAL_TONEAMP, 0, cal_type, false);
-
- wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
- i_pwr = (est[rx_core].i_pwr + num_samps / 2) / num_samps;
- q_pwr = (est[rx_core].q_pwr + num_samps / 2) / num_samps;
- curr_pwr = i_pwr + q_pwr;
-
- switch (gainctrl_dirn) {
- case NPHY_RXCAL_GAIN_INIT:
- if (curr_pwr > thresh_pwr) {
- gainctrl_dirn = NPHY_RXCAL_GAIN_DOWN;
- prev_gaintbl_index = curr_gaintbl_index;
- curr_gaintbl_index--;
- } else {
- gainctrl_dirn = NPHY_RXCAL_GAIN_UP;
- prev_gaintbl_index = curr_gaintbl_index;
- curr_gaintbl_index++;
- }
- break;
-
- case NPHY_RXCAL_GAIN_UP:
- if (curr_pwr > thresh_pwr) {
- gainctrl_done = true;
- optim_pwr = prev_pwr;
- optim_gaintbl_index = prev_gaintbl_index;
- } else {
- prev_gaintbl_index = curr_gaintbl_index;
- curr_gaintbl_index++;
- }
- break;
-
- case NPHY_RXCAL_GAIN_DOWN:
- if (curr_pwr > thresh_pwr) {
- prev_gaintbl_index = curr_gaintbl_index;
- curr_gaintbl_index--;
- } else {
- gainctrl_done = true;
- optim_pwr = curr_pwr;
- optim_gaintbl_index = curr_gaintbl_index;
- }
- break;
-
- default:
- break;
- }
-
- if ((curr_gaintbl_index < 0) ||
- (curr_gaintbl_index > NPHY_IPA_RXCAL_MAXGAININDEX)) {
- gainctrl_done = true;
- optim_pwr = curr_pwr;
- optim_gaintbl_index = prev_gaintbl_index;
- } else {
- prev_pwr = curr_pwr;
- }
-
- wlc_phy_stopplayback_nphy(pi);
- } while (!gainctrl_done);
-
- hpvga = nphy_rxcal_gaintbl[optim_gaintbl_index].hpvga;
- lpf_biq1 = nphy_rxcal_gaintbl[optim_gaintbl_index].lpf_biq1;
- lpf_biq0 = nphy_rxcal_gaintbl[optim_gaintbl_index].lpf_biq0;
- lna2 = nphy_rxcal_gaintbl[optim_gaintbl_index].lna2;
- lna1 = nphy_rxcal_gaintbl[optim_gaintbl_index].lna1;
- txpwrindex = nphy_rxcal_gaintbl[optim_gaintbl_index].txpwrindex;
-
- actual_log2_pwr = wlc_phy_nbits(optim_pwr);
- delta_pwr = desired_log2_pwr - actual_log2_pwr;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- fine_gain_idx = (int)lpf_biq1 + delta_pwr;
-
- if (fine_gain_idx + (int)lpf_biq0 > 10) {
- lpf_biq1 = 10 - lpf_biq0;
- } else {
- lpf_biq1 = (u16) max(fine_gain_idx, 0);
- }
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_rxgain,
- ((lpf_biq1 << 12) |
- (lpf_biq0 << 8) |
- (mix_tia_gain << 4) |
- (lna2 << 2) | lna1), 0x3,
- 0);
- } else {
- hpvga = (u16) max(min(((int)hpvga) + delta_pwr, 10), 0);
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12),
- ((hpvga << 12) | (lpf_biq1 << 10) |
- (lpf_biq0 << 8) | (mix_tia_gain <<
- 4) | (lna2 <<
- 2) |
- lna1), 0x3, 0);
-
- }
-
- if (rxgain != NULL) {
- *rxgain++ = lna1;
- *rxgain++ = lna2;
- *rxgain++ = mix_tia_gain;
- *rxgain++ = lpf_biq0;
- *rxgain++ = lpf_biq1;
- *rxgain = hpvga;
- }
-
- wlc_phy_rx_iq_coeffs_nphy(pi, 1, &save_comp);
-}
-
-static void
-wlc_phy_rxcal_gainctrl_nphy(phy_info_t *pi, u8 rx_core, u16 *rxgain,
- u8 cal_type)
-{
- wlc_phy_rxcal_gainctrl_nphy_rev5(pi, rx_core, rxgain, cal_type);
-}
-
-static u8
-wlc_phy_rc_sweep_nphy(phy_info_t *pi, u8 core_idx, u8 loopback_type)
-{
- u32 target_bws[2] = { 9500, 21000 };
- u32 ref_tones[2] = { 3000, 6000 };
- u32 target_bw, ref_tone;
-
- u32 target_pwr_ratios[2] = { 28606, 18468 };
- u32 target_pwr_ratio, pwr_ratio, last_pwr_ratio = 0;
-
- u16 start_rccal_ovr_val = 128;
- u16 txlpf_rccal_lpc_ovr_val = 128;
- u16 rxlpf_rccal_hpc_ovr_val = 159;
-
- u16 orig_txlpf_rccal_lpc_ovr_val;
- u16 orig_rxlpf_rccal_hpc_ovr_val;
- u16 radio_addr_offset_rx;
- u16 radio_addr_offset_tx;
- u16 orig_dcBypass;
- u16 orig_RxStrnFilt40Num[6];
- u16 orig_RxStrnFilt40Den[4];
- u16 orig_rfctrloverride[2];
- u16 orig_rfctrlauxreg[2];
- u16 orig_rfctrlrssiothers;
- u16 tx_lpf_bw = 4;
-
- u16 rx_lpf_bw, rx_lpf_bws[2] = { 2, 4 };
- u16 lpf_hpc = 7, hpvga_hpc = 7;
-
- s8 rccal_stepsize;
- u16 rccal_val, last_rccal_val = 0, best_rccal_val = 0;
- u32 ref_iq_vals = 0, target_iq_vals = 0;
- u16 num_samps, log_num_samps = 10;
- phy_iq_est_t est[PHY_CORE_MAX];
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- return 0;
- }
-
- num_samps = (1 << log_num_samps);
-
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- target_bw = target_bws[1];
- target_pwr_ratio = target_pwr_ratios[1];
- ref_tone = ref_tones[1];
- rx_lpf_bw = rx_lpf_bws[1];
- } else {
- target_bw = target_bws[0];
- target_pwr_ratio = target_pwr_ratios[0];
- ref_tone = ref_tones[0];
- rx_lpf_bw = rx_lpf_bws[0];
- }
-
- if (core_idx == 0) {
- radio_addr_offset_rx = RADIO_2056_RX0;
- radio_addr_offset_tx =
- (loopback_type == 0) ? RADIO_2056_TX0 : RADIO_2056_TX1;
- } else {
- radio_addr_offset_rx = RADIO_2056_RX1;
- radio_addr_offset_tx =
- (loopback_type == 0) ? RADIO_2056_TX1 : RADIO_2056_TX0;
- }
-
- orig_txlpf_rccal_lpc_ovr_val =
- read_radio_reg(pi,
- (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx));
- orig_rxlpf_rccal_hpc_ovr_val =
- read_radio_reg(pi,
- (RADIO_2056_RX_RXLPF_RCCAL_HPC |
- radio_addr_offset_rx));
-
- orig_dcBypass = ((read_phy_reg(pi, 0x48) >> 8) & 1);
-
- orig_RxStrnFilt40Num[0] = read_phy_reg(pi, 0x267);
- orig_RxStrnFilt40Num[1] = read_phy_reg(pi, 0x268);
- orig_RxStrnFilt40Num[2] = read_phy_reg(pi, 0x269);
- orig_RxStrnFilt40Den[0] = read_phy_reg(pi, 0x26a);
- orig_RxStrnFilt40Den[1] = read_phy_reg(pi, 0x26b);
- orig_RxStrnFilt40Num[3] = read_phy_reg(pi, 0x26c);
- orig_RxStrnFilt40Num[4] = read_phy_reg(pi, 0x26d);
- orig_RxStrnFilt40Num[5] = read_phy_reg(pi, 0x26e);
- orig_RxStrnFilt40Den[2] = read_phy_reg(pi, 0x26f);
- orig_RxStrnFilt40Den[3] = read_phy_reg(pi, 0x270);
-
- orig_rfctrloverride[0] = read_phy_reg(pi, 0xe7);
- orig_rfctrloverride[1] = read_phy_reg(pi, 0xec);
- orig_rfctrlauxreg[0] = read_phy_reg(pi, 0xf8);
- orig_rfctrlauxreg[1] = read_phy_reg(pi, 0xfa);
- orig_rfctrlrssiothers = read_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d);
-
- write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx),
- txlpf_rccal_lpc_ovr_val);
-
- write_radio_reg(pi,
- (RADIO_2056_RX_RXLPF_RCCAL_HPC | radio_addr_offset_rx),
- rxlpf_rccal_hpc_ovr_val);
-
- mod_phy_reg(pi, 0x48, (0x1 << 8), (0x1 << 8));
-
- write_phy_reg(pi, 0x267, 0x02d4);
- write_phy_reg(pi, 0x268, 0x0000);
- write_phy_reg(pi, 0x269, 0x0000);
- write_phy_reg(pi, 0x26a, 0x0000);
- write_phy_reg(pi, 0x26b, 0x0000);
- write_phy_reg(pi, 0x26c, 0x02d4);
- write_phy_reg(pi, 0x26d, 0x0000);
- write_phy_reg(pi, 0x26e, 0x0000);
- write_phy_reg(pi, 0x26f, 0x0000);
- write_phy_reg(pi, 0x270, 0x0000);
-
- or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 8));
- or_phy_reg(pi, (core_idx == 0) ? 0xec : 0xe7, (0x1 << 15));
- or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 9));
- or_phy_reg(pi, (core_idx == 0) ? 0xe7 : 0xec, (0x1 << 10));
-
- mod_phy_reg(pi, (core_idx == 0) ? 0xfa : 0xf8,
- (0x7 << 10), (tx_lpf_bw << 10));
- mod_phy_reg(pi, (core_idx == 0) ? 0xf8 : 0xfa,
- (0x7 << 0), (hpvga_hpc << 0));
- mod_phy_reg(pi, (core_idx == 0) ? 0xf8 : 0xfa,
- (0x7 << 4), (lpf_hpc << 4));
- mod_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d,
- (0x7 << 8), (rx_lpf_bw << 8));
-
- rccal_stepsize = 16;
- rccal_val = start_rccal_ovr_val + rccal_stepsize;
-
- while (rccal_stepsize >= 0) {
- write_radio_reg(pi,
- (RADIO_2056_RX_RXLPF_RCCAL_LPC |
- radio_addr_offset_rx), rccal_val);
-
- if (rccal_stepsize == 16) {
-
- wlc_phy_tx_tone_nphy(pi, ref_tone, NPHY_RXCAL_TONEAMP,
- 0, 1, false);
- udelay(2);
-
- wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
-
- if (core_idx == 0) {
- ref_iq_vals =
- max_t(u32, (est[0].i_pwr +
- est[0].q_pwr) >> (log_num_samps + 1),
- 1);
- } else {
- ref_iq_vals =
- max_t(u32, (est[1].i_pwr +
- est[1].q_pwr) >> (log_num_samps + 1),
- 1);
- }
-
- wlc_phy_tx_tone_nphy(pi, target_bw, NPHY_RXCAL_TONEAMP,
- 0, 1, false);
- udelay(2);
- }
-
- wlc_phy_rx_iq_est_nphy(pi, est, num_samps, 32, 0);
-
- if (core_idx == 0) {
- target_iq_vals =
- (est[0].i_pwr + est[0].q_pwr) >> (log_num_samps +
- 1);
- } else {
- target_iq_vals =
- (est[1].i_pwr + est[1].q_pwr) >> (log_num_samps +
- 1);
- }
- pwr_ratio = (uint) ((target_iq_vals << 16) / ref_iq_vals);
-
- if (rccal_stepsize == 0) {
- rccal_stepsize--;
- } else if (rccal_stepsize == 1) {
- last_rccal_val = rccal_val;
- rccal_val += (pwr_ratio > target_pwr_ratio) ? 1 : -1;
- last_pwr_ratio = pwr_ratio;
- rccal_stepsize--;
- } else {
- rccal_stepsize = (rccal_stepsize >> 1);
- rccal_val += ((pwr_ratio > target_pwr_ratio) ?
- rccal_stepsize : (-rccal_stepsize));
- }
-
- if (rccal_stepsize == -1) {
- best_rccal_val =
- (ABS((int)last_pwr_ratio - (int)target_pwr_ratio) <
- ABS((int)pwr_ratio -
- (int)target_pwr_ratio)) ? last_rccal_val :
- rccal_val;
-
- if (CHSPEC_IS40(pi->radio_chanspec)) {
- if ((best_rccal_val > 140)
- || (best_rccal_val < 135)) {
- best_rccal_val = 138;
- }
- } else {
- if ((best_rccal_val > 142)
- || (best_rccal_val < 137)) {
- best_rccal_val = 140;
- }
- }
-
- write_radio_reg(pi,
- (RADIO_2056_RX_RXLPF_RCCAL_LPC |
- radio_addr_offset_rx), best_rccal_val);
- }
- }
-
- wlc_phy_stopplayback_nphy(pi);
-
- write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL | radio_addr_offset_tx),
- orig_txlpf_rccal_lpc_ovr_val);
- write_radio_reg(pi,
- (RADIO_2056_RX_RXLPF_RCCAL_HPC | radio_addr_offset_rx),
- orig_rxlpf_rccal_hpc_ovr_val);
-
- mod_phy_reg(pi, 0x48, (0x1 << 8), (orig_dcBypass << 8));
-
- write_phy_reg(pi, 0x267, orig_RxStrnFilt40Num[0]);
- write_phy_reg(pi, 0x268, orig_RxStrnFilt40Num[1]);
- write_phy_reg(pi, 0x269, orig_RxStrnFilt40Num[2]);
- write_phy_reg(pi, 0x26a, orig_RxStrnFilt40Den[0]);
- write_phy_reg(pi, 0x26b, orig_RxStrnFilt40Den[1]);
- write_phy_reg(pi, 0x26c, orig_RxStrnFilt40Num[3]);
- write_phy_reg(pi, 0x26d, orig_RxStrnFilt40Num[4]);
- write_phy_reg(pi, 0x26e, orig_RxStrnFilt40Num[5]);
- write_phy_reg(pi, 0x26f, orig_RxStrnFilt40Den[2]);
- write_phy_reg(pi, 0x270, orig_RxStrnFilt40Den[3]);
-
- write_phy_reg(pi, 0xe7, orig_rfctrloverride[0]);
- write_phy_reg(pi, 0xec, orig_rfctrloverride[1]);
- write_phy_reg(pi, 0xf8, orig_rfctrlauxreg[0]);
- write_phy_reg(pi, 0xfa, orig_rfctrlauxreg[1]);
- write_phy_reg(pi, (core_idx == 0) ? 0x7a : 0x7d, orig_rfctrlrssiothers);
-
- pi->nphy_anarxlpf_adjusted = false;
-
- return best_rccal_val - 0x80;
-}
-
-#define WAIT_FOR_SCOPE 4000
-static int
-wlc_phy_cal_rxiq_nphy_rev3(phy_info_t *pi, nphy_txgains_t target_gain,
- u8 cal_type, bool debug)
-{
- u16 orig_BBConfig;
- u8 core_no, rx_core;
- u8 best_rccal[2];
- u16 gain_save[2];
- u16 cal_gain[2];
- nphy_iqcal_params_t cal_params[2];
- u8 rxcore_state;
- s8 rxlpf_rccal_hpc, txlpf_rccal_lpc;
- s8 txlpf_idac;
- bool phyhang_avoid_state = false;
- bool skip_rxiqcal = false;
-
- orig_BBConfig = read_phy_reg(pi, 0x01);
- mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
-
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- if (NREV_GE(pi->pubpi.phy_rev, 4)) {
- phyhang_avoid_state = pi->phyhang_avoid;
- pi->phyhang_avoid = false;
- }
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
-
- for (core_no = 0; core_no <= 1; core_no++) {
- wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
- &cal_params[core_no]);
- cal_gain[core_no] = cal_params[core_no].cal_gain;
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
-
- rxcore_state = wlc_phy_rxcore_getstate_nphy((wlc_phy_t *) pi);
-
- for (rx_core = 0; rx_core < pi->pubpi.phy_corenum; rx_core++) {
-
- skip_rxiqcal =
- ((rxcore_state & (1 << rx_core)) == 0) ? true : false;
-
- wlc_phy_rxcal_physetup_nphy(pi, rx_core);
-
- wlc_phy_rxcal_radio_setup_nphy(pi, rx_core);
-
- if ((!skip_rxiqcal) && ((cal_type == 0) || (cal_type == 2))) {
-
- wlc_phy_rxcal_gainctrl_nphy(pi, rx_core, NULL, 0);
-
- wlc_phy_tx_tone_nphy(pi,
- (CHSPEC_IS40(pi->radio_chanspec)) ?
- NPHY_RXCAL_TONEFREQ_40MHz :
- NPHY_RXCAL_TONEFREQ_20MHz,
- NPHY_RXCAL_TONEAMP, 0, cal_type,
- false);
-
- if (debug)
- mdelay(WAIT_FOR_SCOPE);
-
- wlc_phy_calc_rx_iq_comp_nphy(pi, rx_core + 1);
- wlc_phy_stopplayback_nphy(pi);
- }
-
- if (((cal_type == 1) || (cal_type == 2))
- && NREV_LT(pi->pubpi.phy_rev, 7)) {
-
- if (rx_core == PHY_CORE_1) {
-
- if (rxcore_state == 1) {
- wlc_phy_rxcore_setstate_nphy((wlc_phy_t
- *) pi, 3);
- }
-
- wlc_phy_rxcal_gainctrl_nphy(pi, rx_core, NULL,
- 1);
-
- best_rccal[rx_core] =
- wlc_phy_rc_sweep_nphy(pi, rx_core, 1);
- pi->nphy_rccal_value = best_rccal[rx_core];
-
- if (rxcore_state == 1) {
- wlc_phy_rxcore_setstate_nphy((wlc_phy_t
- *) pi,
- rxcore_state);
- }
- }
- }
-
- wlc_phy_rxcal_radio_cleanup_nphy(pi, rx_core);
-
- wlc_phy_rxcal_phycleanup_nphy(pi, rx_core);
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
- }
-
- if ((cal_type == 1) || (cal_type == 2)) {
-
- best_rccal[0] = best_rccal[1];
- write_radio_reg(pi,
- (RADIO_2056_RX_RXLPF_RCCAL_LPC |
- RADIO_2056_RX0), (best_rccal[0] | 0x80));
-
- for (rx_core = 0; rx_core < pi->pubpi.phy_corenum; rx_core++) {
- rxlpf_rccal_hpc =
- (((int)best_rccal[rx_core] - 12) >> 1) + 10;
- txlpf_rccal_lpc = ((int)best_rccal[rx_core] - 12) + 10;
-
- if (PHY_IPA(pi)) {
- txlpf_rccal_lpc += IS40MHZ(pi) ? 24 : 12;
- txlpf_idac = IS40MHZ(pi) ? 0x0e : 0x13;
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, rx_core,
- TXLPF_IDAC_4, txlpf_idac);
- }
-
- rxlpf_rccal_hpc = max(min_t(u8, rxlpf_rccal_hpc, 31), 0);
- txlpf_rccal_lpc = max(min_t(u8, txlpf_rccal_lpc, 31), 0);
-
- write_radio_reg(pi, (RADIO_2056_RX_RXLPF_RCCAL_HPC |
- ((rx_core ==
- PHY_CORE_0) ? RADIO_2056_RX0 :
- RADIO_2056_RX1)),
- (rxlpf_rccal_hpc | 0x80));
-
- write_radio_reg(pi, (RADIO_2056_TX_TXLPF_RCCAL |
- ((rx_core ==
- PHY_CORE_0) ? RADIO_2056_TX0 :
- RADIO_2056_TX1)),
- (txlpf_rccal_lpc | 0x80));
- }
- }
-
- write_phy_reg(pi, 0x01, orig_BBConfig);
-
- wlc_phy_resetcca_nphy(pi);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_rxgain,
- 0, 0x3, 1);
- } else {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 1);
- }
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
- gain_save);
-
- if (NREV_GE(pi->pubpi.phy_rev, 4)) {
- pi->phyhang_avoid = phyhang_avoid_state;
- }
-
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-
- return 0;
-}
-
-static int
-wlc_phy_cal_rxiq_nphy_rev2(phy_info_t *pi, nphy_txgains_t target_gain,
- bool debug)
-{
- phy_iq_est_t est[PHY_CORE_MAX];
- u8 core_num, rx_core, tx_core;
- u16 lna_vals[] = { 0x3, 0x3, 0x1 };
- u16 hpf1_vals[] = { 0x7, 0x2, 0x0 };
- u16 hpf2_vals[] = { 0x2, 0x0, 0x0 };
- s16 curr_hpf1, curr_hpf2, curr_hpf, curr_lna;
- s16 desired_log2_pwr, actual_log2_pwr, hpf_change;
- u16 orig_RfseqCoreActv, orig_AfectrlCore, orig_AfectrlOverride;
- u16 orig_RfctrlIntcRx, orig_RfctrlIntcTx;
- u16 num_samps;
- u32 i_pwr, q_pwr, tot_pwr[3];
- u8 gain_pass, use_hpf_num;
- u16 mask, val1, val2;
- u16 core_no;
- u16 gain_save[2];
- u16 cal_gain[2];
- nphy_iqcal_params_t cal_params[2];
- u8 phy_bw;
- int bcmerror = 0;
- bool first_playtone = true;
-
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
-
- wlc_phy_reapply_txcal_coeffs_nphy(pi);
- }
-
- wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, gain_save);
-
- for (core_no = 0; core_no <= 1; core_no++) {
- wlc_phy_iqcal_gainparams_nphy(pi, core_no, target_gain,
- &cal_params[core_no]);
- cal_gain[core_no] = cal_params[core_no].cal_gain;
- }
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16, cal_gain);
-
- num_samps = 1024;
- desired_log2_pwr = 13;
-
- for (core_num = 0; core_num < 2; core_num++) {
-
- rx_core = core_num;
- tx_core = 1 - core_num;
-
- orig_RfseqCoreActv = read_phy_reg(pi, 0xa2);
- orig_AfectrlCore = read_phy_reg(pi, (rx_core == PHY_CORE_0) ?
- 0xa6 : 0xa7);
- orig_AfectrlOverride = read_phy_reg(pi, 0xa5);
- orig_RfctrlIntcRx = read_phy_reg(pi, (rx_core == PHY_CORE_0) ?
- 0x91 : 0x92);
- orig_RfctrlIntcTx = read_phy_reg(pi, (tx_core == PHY_CORE_0) ?
- 0x91 : 0x92);
-
- mod_phy_reg(pi, 0xa2, (0xf << 12), (1 << tx_core) << 12);
- mod_phy_reg(pi, 0xa2, (0xf << 0), (1 << tx_core) << 0);
-
- or_phy_reg(pi, ((rx_core == PHY_CORE_0) ? 0xa6 : 0xa7),
- ((0x1 << 1) | (0x1 << 2)));
- or_phy_reg(pi, 0xa5, ((0x1 << 1) | (0x1 << 2)));
-
- if (((pi->nphy_rxcalparams) & 0xff000000)) {
-
- write_phy_reg(pi,
- (rx_core == PHY_CORE_0) ? 0x91 : 0x92,
- (CHSPEC_IS5G(pi->radio_chanspec) ? 0x140 :
- 0x110));
- } else {
-
- write_phy_reg(pi,
- (rx_core == PHY_CORE_0) ? 0x91 : 0x92,
- (CHSPEC_IS5G(pi->radio_chanspec) ? 0x180 :
- 0x120));
- }
-
- write_phy_reg(pi, (tx_core == PHY_CORE_0) ? 0x91 : 0x92,
- (CHSPEC_IS5G(pi->radio_chanspec) ? 0x148 :
- 0x114));
-
- mask = RADIO_2055_COUPLE_RX_MASK | RADIO_2055_COUPLE_TX_MASK;
- if (rx_core == PHY_CORE_0) {
- val1 = RADIO_2055_COUPLE_RX_MASK;
- val2 = RADIO_2055_COUPLE_TX_MASK;
- } else {
- val1 = RADIO_2055_COUPLE_TX_MASK;
- val2 = RADIO_2055_COUPLE_RX_MASK;
- }
-
- if ((pi->nphy_rxcalparams & 0x10000)) {
- mod_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, mask,
- val1);
- mod_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, mask,
- val2);
- }
-
- for (gain_pass = 0; gain_pass < 4; gain_pass++) {
-
- if (debug)
- mdelay(WAIT_FOR_SCOPE);
-
- if (gain_pass < 3) {
- curr_lna = lna_vals[gain_pass];
- curr_hpf1 = hpf1_vals[gain_pass];
- curr_hpf2 = hpf2_vals[gain_pass];
- } else {
-
- if (tot_pwr[1] > 10000) {
- curr_lna = lna_vals[2];
- curr_hpf1 = hpf1_vals[2];
- curr_hpf2 = hpf2_vals[2];
- use_hpf_num = 1;
- curr_hpf = curr_hpf1;
- actual_log2_pwr =
- wlc_phy_nbits(tot_pwr[2]);
- } else {
- if (tot_pwr[0] > 10000) {
- curr_lna = lna_vals[1];
- curr_hpf1 = hpf1_vals[1];
- curr_hpf2 = hpf2_vals[1];
- use_hpf_num = 1;
- curr_hpf = curr_hpf1;
- actual_log2_pwr =
- wlc_phy_nbits(tot_pwr[1]);
- } else {
- curr_lna = lna_vals[0];
- curr_hpf1 = hpf1_vals[0];
- curr_hpf2 = hpf2_vals[0];
- use_hpf_num = 2;
- curr_hpf = curr_hpf2;
- actual_log2_pwr =
- wlc_phy_nbits(tot_pwr[0]);
- }
- }
-
- hpf_change = desired_log2_pwr - actual_log2_pwr;
- curr_hpf += hpf_change;
- curr_hpf = max(min_t(u16, curr_hpf, 10), 0);
- if (use_hpf_num == 1) {
- curr_hpf1 = curr_hpf;
- } else {
- curr_hpf2 = curr_hpf;
- }
- }
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 10),
- ((curr_hpf2 << 8) |
- (curr_hpf1 << 4) |
- (curr_lna << 2)), 0x3, 0);
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
-
- wlc_phy_stopplayback_nphy(pi);
-
- if (first_playtone) {
- bcmerror = wlc_phy_tx_tone_nphy(pi, 4000,
- (u16) (pi->
- nphy_rxcalparams
- &
- 0xffff),
- 0, 0, true);
- first_playtone = false;
- } else {
- phy_bw =
- (CHSPEC_IS40(pi->radio_chanspec)) ? 40 : 20;
- wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff,
- 0, 0, 0, true);
- }
-
- if (bcmerror == 0) {
- if (gain_pass < 3) {
-
- wlc_phy_rx_iq_est_nphy(pi, est,
- num_samps, 32,
- 0);
- i_pwr =
- (est[rx_core].i_pwr +
- num_samps / 2) / num_samps;
- q_pwr =
- (est[rx_core].q_pwr +
- num_samps / 2) / num_samps;
- tot_pwr[gain_pass] = i_pwr + q_pwr;
- } else {
-
- wlc_phy_calc_rx_iq_comp_nphy(pi,
- (1 <<
- rx_core));
- }
-
- wlc_phy_stopplayback_nphy(pi);
- }
-
- if (bcmerror != 0)
- break;
- }
-
- and_radio_reg(pi, RADIO_2055_CORE1_GEN_SPARE2, ~mask);
- and_radio_reg(pi, RADIO_2055_CORE2_GEN_SPARE2, ~mask);
-
- write_phy_reg(pi, (tx_core == PHY_CORE_0) ? 0x91 :
- 0x92, orig_RfctrlIntcTx);
- write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0x91 :
- 0x92, orig_RfctrlIntcRx);
- write_phy_reg(pi, 0xa5, orig_AfectrlOverride);
- write_phy_reg(pi, (rx_core == PHY_CORE_0) ? 0xa6 :
- 0xa7, orig_AfectrlCore);
- write_phy_reg(pi, 0xa2, orig_RfseqCoreActv);
-
- if (bcmerror != 0)
- break;
- }
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 10), 0, 0x3, 1);
- wlc_phy_force_rfseq_nphy(pi, NPHY_RFSEQ_RESET2RX);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_RFSEQ, 2, 0x110, 16,
- gain_save);
-
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-
- return bcmerror;
-}
-
-int
-wlc_phy_cal_rxiq_nphy(phy_info_t *pi, nphy_txgains_t target_gain,
- u8 cal_type, bool debug)
-{
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- cal_type = 0;
- }
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- return wlc_phy_cal_rxiq_nphy_rev3(pi, target_gain, cal_type,
- debug);
- } else {
- return wlc_phy_cal_rxiq_nphy_rev2(pi, target_gain, debug);
- }
-}
-
-static void wlc_phy_extpa_set_tx_digi_filts_nphy(phy_info_t *pi)
-{
- int j, type = 2;
- u16 addr_offset = 0x2c5;
-
- for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, addr_offset + j,
- NPHY_IPA_REV4_txdigi_filtcoeffs[type][j]);
- }
-}
-
-static void wlc_phy_ipa_set_tx_digi_filts_nphy(phy_info_t *pi)
-{
- int j, type;
- u16 addr_offset[] = { 0x186, 0x195,
- 0x2c5
- };
-
- for (type = 0; type < 3; type++) {
- for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, addr_offset[type] + j,
- NPHY_IPA_REV4_txdigi_filtcoeffs[type][j]);
- }
- }
-
- if (IS40MHZ(pi)) {
- for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, 0x186 + j,
- NPHY_IPA_REV4_txdigi_filtcoeffs[3][j]);
- }
- } else {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, 0x186 + j,
- NPHY_IPA_REV4_txdigi_filtcoeffs[5]
- [j]);
- }
- }
-
- if (CHSPEC_CHANNEL(pi->radio_chanspec) == 14) {
- for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, 0x2c5 + j,
- NPHY_IPA_REV4_txdigi_filtcoeffs[6]
- [j]);
- }
- }
- }
-}
-
-static void wlc_phy_ipa_restore_tx_digi_filts_nphy(phy_info_t *pi)
-{
- int j;
-
- if (IS40MHZ(pi)) {
- for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, 0x195 + j,
- NPHY_IPA_REV4_txdigi_filtcoeffs[4][j]);
- }
- } else {
- for (j = 0; j < NPHY_NUM_DIG_FILT_COEFFS; j++) {
- write_phy_reg(pi, 0x186 + j,
- NPHY_IPA_REV4_txdigi_filtcoeffs[3][j]);
- }
- }
-}
-
-static u16 wlc_phy_ipa_get_bbmult_nphy(phy_info_t *pi)
-{
- u16 m0m1;
-
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m0m1);
-
- return m0m1;
-}
-
-static void wlc_phy_ipa_set_bbmult_nphy(phy_info_t *pi, u8 m0, u8 m1)
-{
- u16 m0m1 = (u16) ((m0 << 8) | m1);
-
- wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m0m1);
- wlc_phy_table_write_nphy(pi, 15, 1, 95, 16, &m0m1);
-}
-
-static u32 *wlc_phy_get_ipa_gaintbl_nphy(phy_info_t *pi)
-{
- u32 *tx_pwrctrl_tbl = NULL;
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- if ((pi->pubpi.radiorev == 4)
- || (pi->pubpi.radiorev == 6)) {
-
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_ipa_2g_2057rev4n6;
- } else if (pi->pubpi.radiorev == 3) {
-
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_ipa_2g_2057rev3;
- } else if (pi->pubpi.radiorev == 5) {
-
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_ipa_2g_2057rev5;
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_ipa_2g_2057rev7;
- }
-
- } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
-
- tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev6;
- if (pi->sh->chip == BCM47162_CHIP_ID) {
-
- tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
- }
-
- } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
-
- tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
- } else {
-
- tx_pwrctrl_tbl = nphy_tpc_txgain_ipa;
- }
-
- } else {
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if ((pi->pubpi.radiorev == 3) ||
- (pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
-
- tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_5g_2057;
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- tx_pwrctrl_tbl =
- nphy_tpc_txgain_ipa_5g_2057rev7;
- }
-
- } else {
- tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_5g;
- }
- }
-
- return tx_pwrctrl_tbl;
-}
-
-static void
-wlc_phy_papd_cal_setup_nphy(phy_info_t *pi, nphy_papd_restore_state *state,
- u8 core)
-{
- s32 tone_freq;
- u8 off_core;
- u16 mixgain = 0;
-
- off_core = core ^ 0x1;
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)
- || NREV_GE(pi->pubpi.phy_rev, 8)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7),
- wlc_phy_read_lpf_bw_ctl_nphy
- (pi, 0), 0, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (pi->pubpi.radiorev == 5) {
- mixgain = (core == 0) ? 0x20 : 0x00;
-
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- mixgain = 0x00;
-
- } else if ((pi->pubpi.radiorev <= 4)
- || (pi->pubpi.radiorev == 6)) {
-
- mixgain = 0x00;
- }
-
- } else {
- if ((pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
-
- mixgain = 0x50;
- } else if ((pi->pubpi.radiorev == 3)
- || (pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- mixgain = 0x0;
- }
- }
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11),
- mixgain, (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
-
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_tx_pu,
- 1, (1 << core), 0);
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_tx_pu,
- 0, (1 << off_core), 0);
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
- 0, 0x3, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1,
- (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0,
- (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1,
- (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 8), 0,
- (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 1,
- (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 0,
- (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 1,
- (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5),
- 0, (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 0,
- (1 << core), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
-
- state->afectrl[core] = read_phy_reg(pi, (core == PHY_CORE_0) ?
- 0xa6 : 0xa7);
- state->afeoverride[core] =
- read_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f : 0xa5);
- state->afectrl[off_core] =
- read_phy_reg(pi, (core == PHY_CORE_0) ? 0xa7 : 0xa6);
- state->afeoverride[off_core] =
- read_phy_reg(pi, (core == PHY_CORE_0) ? 0xa5 : 0x8f);
-
- mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa6 : 0xa7),
- (0x1 << 2), 0);
- mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
- 0xa5), (0x1 << 2), (0x1 << 2));
-
- mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa7 : 0xa6),
- (0x1 << 2), (0x1 << 2));
- mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa5 :
- 0x8f), (0x1 << 2), (0x1 << 2));
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- state->pwrup[core] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_2G_PWRUP);
- state->atten[core] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_2G_ATTEN);
- state->pwrup[off_core] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
- TXRXCOUPLE_2G_PWRUP);
- state->atten[off_core] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
- TXRXCOUPLE_2G_ATTEN);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_2G_PWRUP, 0xc);
-
- if ((pi->pubpi.radiorev == 3) ||
- (pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_2G_ATTEN, 0xf0);
-
- } else if (pi->pubpi.radiorev == 5) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_2G_ATTEN,
- (core == 0) ? 0xf7 : 0xf2);
-
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_2G_ATTEN, 0xf0);
-
- }
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
- TXRXCOUPLE_2G_PWRUP, 0x0);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
- TXRXCOUPLE_2G_ATTEN, 0xff);
-
- } else {
- state->pwrup[core] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_5G_PWRUP);
- state->atten[core] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_5G_ATTEN);
- state->pwrup[off_core] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
- TXRXCOUPLE_5G_PWRUP);
- state->atten[off_core] =
- READ_RADIO_REG3(pi, RADIO_2057, TX, off_core,
- TXRXCOUPLE_5G_ATTEN);
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_5G_PWRUP, 0xc);
-
- if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_5G_ATTEN, 0xf4);
-
- } else {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_5G_ATTEN, 0xf0);
- }
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
- TXRXCOUPLE_5G_PWRUP, 0x0);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
- TXRXCOUPLE_5G_ATTEN, 0xff);
- }
-
- tone_freq = 4000;
-
- wlc_phy_tx_tone_nphy(pi, tone_freq, 181, 0, 0, false);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 13), (1) << 13);
-
- mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_OFF) << 0);
-
- mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 13), (0) << 13);
-
- } else {
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 0);
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 1, 0, 0);
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0x3, 0);
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 2), 1, 0x3, 0);
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 1, 0x3, 0);
-
- state->afectrl[core] = read_phy_reg(pi, (core == PHY_CORE_0) ?
- 0xa6 : 0xa7);
- state->afeoverride[core] =
- read_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f : 0xa5);
-
- mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0xa6 : 0xa7),
- (0x1 << 0) | (0x1 << 1) | (0x1 << 2), 0);
- mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
- 0xa5),
- (0x1 << 0) |
- (0x1 << 1) |
- (0x1 << 2), (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
-
- state->vga_master[core] =
- READ_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER);
- WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER, 0x2b);
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- state->fbmix[core] =
- READ_RADIO_REG2(pi, RADIO_2056, RX, core,
- TXFBMIX_G);
- state->intpa_master[core] =
- READ_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_MASTER);
-
- WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, TXFBMIX_G,
- 0x03);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_MASTER, 0x04);
- } else {
- state->fbmix[core] =
- READ_RADIO_REG2(pi, RADIO_2056, RX, core,
- TXFBMIX_A);
- state->intpa_master[core] =
- READ_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAA_MASTER);
-
- WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, TXFBMIX_A,
- 0x03);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAA_MASTER, 0x04);
-
- }
-
- tone_freq = 4000;
-
- wlc_phy_tx_tone_nphy(pi, tone_freq, 181, 0, 0, false);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (1) << 0);
-
- mod_phy_reg(pi, (off_core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (0) << 0);
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 0);
- }
-}
-
-static void
-wlc_phy_papd_cal_cleanup_nphy(phy_info_t *pi, nphy_papd_restore_state *state)
-{
- u8 core;
-
- wlc_phy_stopplayback_nphy(pi);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_2G_PWRUP, 0);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_2G_ATTEN,
- state->atten[core]);
- } else {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_5G_PWRUP, 0);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TXRXCOUPLE_5G_ATTEN,
- state->atten[core]);
- }
- }
-
- if ((pi->pubpi.radiorev == 4) || (pi->pubpi.radiorev == 6)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
- 1, 0x3, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- } else {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2),
- 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- }
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1),
- 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 1, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 11), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 2), 1, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 0), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 1), 1, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID2);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 8), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 9), 1, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 10), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3), 1, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 5), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 4), 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
-
- write_phy_reg(pi, (core == PHY_CORE_0) ?
- 0xa6 : 0xa7, state->afectrl[core]);
- write_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f :
- 0xa5, state->afeoverride[core]);
- }
-
- wlc_phy_ipa_set_bbmult_nphy(pi, (state->mm >> 8) & 0xff,
- (state->mm & 0xff));
-
- if (NREV_IS(pi->pubpi.phy_rev, 7)
- || NREV_GE(pi->pubpi.phy_rev, 8)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 7), 0, 0,
- 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID1);
- }
- } else {
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 12), 0, 0x3, 1);
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 0x3, 1);
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 0), 0, 0x3, 1);
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 2), 0, 0x3, 1);
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 1), 0, 0x3, 1);
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
-
- WRITE_RADIO_REG2(pi, RADIO_2056, RX, core, VGA_MASTER,
- state->vga_master[core]);
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- WRITE_RADIO_REG2(pi, RADIO_2056, RX, core,
- TXFBMIX_G, state->fbmix[core]);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAG_MASTER,
- state->intpa_master[core]);
- } else {
- WRITE_RADIO_REG2(pi, RADIO_2056, RX, core,
- TXFBMIX_A, state->fbmix[core]);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- INTPAA_MASTER,
- state->intpa_master[core]);
- }
-
- write_phy_reg(pi, (core == PHY_CORE_0) ?
- 0xa6 : 0xa7, state->afectrl[core]);
- write_phy_reg(pi, (core == PHY_CORE_0) ? 0x8f :
- 0xa5, state->afeoverride[core]);
- }
-
- wlc_phy_ipa_set_bbmult_nphy(pi, (state->mm >> 8) & 0xff,
- (state->mm & 0xff));
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 1);
- }
-}
-
-static void
-wlc_phy_a1_nphy(phy_info_t *pi, u8 core, u32 winsz, u32 start,
- u32 end)
-{
- u32 *buf, *src, *dst, sz;
-
- sz = end - start + 1;
-
- buf = kmalloc(2 * sizeof(u32) * NPHY_PAPD_EPS_TBL_SIZE, GFP_ATOMIC);
- if (NULL == buf) {
- return;
- }
-
- src = buf;
- dst = buf + NPHY_PAPD_EPS_TBL_SIZE;
-
- wlc_phy_table_read_nphy(pi,
- (core ==
- PHY_CORE_0 ? NPHY_TBL_ID_EPSILONTBL0 :
- NPHY_TBL_ID_EPSILONTBL1),
- NPHY_PAPD_EPS_TBL_SIZE, 0, 32, src);
-
- do {
- u32 phy_a1, phy_a2;
- s32 phy_a3, phy_a4, phy_a5, phy_a6, phy_a7;
-
- phy_a1 = end - min(end, (winsz >> 1));
- phy_a2 = min_t(u32, NPHY_PAPD_EPS_TBL_SIZE - 1, end + (winsz >> 1));
- phy_a3 = phy_a2 - phy_a1 + 1;
- phy_a6 = 0;
- phy_a7 = 0;
-
- do {
- wlc_phy_papd_decode_epsilon(src[phy_a2], &phy_a4,
- &phy_a5);
- phy_a6 += phy_a4;
- phy_a7 += phy_a5;
- } while (phy_a2-- != phy_a1);
-
- phy_a6 /= phy_a3;
- phy_a7 /= phy_a3;
- dst[end] = ((u32) phy_a7 << 13) | ((u32) phy_a6 & 0x1fff);
- } while (end-- != start);
-
- wlc_phy_table_write_nphy(pi,
- (core ==
- PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0 :
- NPHY_TBL_ID_EPSILONTBL1, sz, start, 32, dst);
-
- kfree(buf);
-}
-
-static void
-wlc_phy_a2_nphy(phy_info_t *pi, nphy_ipa_txcalgains_t *txgains,
- phy_cal_mode_t cal_mode, u8 core)
-{
- u16 phy_a1, phy_a2, phy_a3;
- u16 phy_a4, phy_a5;
- bool phy_a6;
- u8 phy_a7, m[2];
- u32 phy_a8 = 0;
- nphy_txgains_t phy_a9;
-
- if (NREV_LT(pi->pubpi.phy_rev, 3))
- return;
-
- phy_a7 = (core == PHY_CORE_0) ? 1 : 0;
-
- phy_a6 = ((cal_mode == CAL_GCTRL)
- || (cal_mode == CAL_SOFT)) ? true : false;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- phy_a9 = wlc_phy_get_tx_gain_nphy(pi);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- phy_a5 = ((phy_a9.txlpf[core] << 15) |
- (phy_a9.txgm[core] << 12) |
- (phy_a9.pga[core] << 8) |
- (txgains->gains.pad[core] << 3) |
- (phy_a9.ipa[core]));
- } else {
- phy_a5 = ((phy_a9.txlpf[core] << 15) |
- (phy_a9.txgm[core] << 12) |
- (txgains->gains.pga[core] << 8) |
- (phy_a9.pad[core] << 3) | (phy_a9.ipa[core]));
- }
-
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_txgain,
- phy_a5, (1 << core), 0);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if ((pi->pubpi.radiorev <= 4)
- || (pi->pubpi.radiorev == 6)) {
-
- m[core] = IS40MHZ(pi) ? 60 : 79;
- } else {
-
- m[core] = IS40MHZ(pi) ? 45 : 64;
- }
-
- } else {
- m[core] = IS40MHZ(pi) ? 75 : 107;
- }
-
- m[phy_a7] = 0;
- wlc_phy_ipa_set_bbmult_nphy(pi, m[0], m[1]);
-
- phy_a2 = 63;
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (pi->sh->chip == BCM6362_CHIP_ID) {
- phy_a1 = 35;
- phy_a3 = 35;
- } else if ((pi->pubpi.radiorev == 4)
- || (pi->pubpi.radiorev == 6)) {
- phy_a1 = 30;
- phy_a3 = 30;
- } else {
- phy_a1 = 25;
- phy_a3 = 25;
- }
- } else {
- if ((pi->pubpi.radiorev == 5)
- || (pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
- phy_a1 = 25;
- phy_a3 = 25;
- } else {
- phy_a1 = 35;
- phy_a3 = 35;
- }
- }
-
- if (cal_mode == CAL_GCTRL) {
- if ((pi->pubpi.radiorev == 5)
- && (CHSPEC_IS2G(pi->radio_chanspec))) {
- phy_a1 = 55;
- } else if (((pi->pubpi.radiorev == 7) &&
- (CHSPEC_IS2G(pi->radio_chanspec))) ||
- ((pi->pubpi.radiorev == 8) &&
- (CHSPEC_IS2G(pi->radio_chanspec)))) {
- phy_a1 = 60;
- } else {
- phy_a1 = 63;
- }
-
- } else if ((cal_mode != CAL_FULL) && (cal_mode != CAL_SOFT)) {
-
- phy_a1 = 35;
- phy_a3 = 35;
- }
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (1) << 0);
-
- mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (0) << 0);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 13), (1) << 13);
-
- mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 13), (0) << 13);
-
- write_phy_reg(pi, 0x2a1, 0x80);
- write_phy_reg(pi, 0x2a2, 0x100);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x7 << 4), (11) << 4);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x7 << 8), (11) << 8);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x7 << 0), (0x3) << 0);
-
- write_phy_reg(pi, 0x2e5, 0x20);
-
- mod_phy_reg(pi, 0x2a0, (0x3f << 0), (phy_a3) << 0);
-
- mod_phy_reg(pi, 0x29f, (0x3f << 0), (phy_a1) << 0);
-
- mod_phy_reg(pi, 0x29f, (0x3f << 8), (phy_a2) << 8);
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
- 1, ((core == 0) ? 1 : 2), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
- 0, ((core == 0) ? 2 : 1), 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
-
- write_phy_reg(pi, 0x2be, 1);
- SPINWAIT(read_phy_reg(pi, 0x2be), 10 * 1000 * 1000);
-
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 3),
- 0, 0x3, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
-
- wlc_phy_table_write_nphy(pi,
- (core ==
- PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0
- : NPHY_TBL_ID_EPSILONTBL1, 1, phy_a3,
- 32, &phy_a8);
-
- if (cal_mode != CAL_GCTRL) {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- wlc_phy_a1_nphy(pi, core, 5, 0, 35);
- }
- }
-
- wlc_phy_rfctrl_override_1tomany_nphy(pi,
- NPHY_REV7_RfctrlOverride_cmd_txgain,
- phy_a5, (1 << core), 1);
-
- } else {
-
- if (txgains) {
- if (txgains->useindex) {
- phy_a4 = 15 - ((txgains->index) >> 3);
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (NREV_GE(pi->pubpi.phy_rev, 6)) {
- phy_a5 = 0x00f7 | (phy_a4 << 8);
-
- if (pi->sh->chip ==
- BCM47162_CHIP_ID) {
- phy_a5 =
- 0x10f7 | (phy_a4 <<
- 8);
- }
- } else
- if (NREV_IS(pi->pubpi.phy_rev, 5))
- phy_a5 = 0x10f7 | (phy_a4 << 8);
- else
- phy_a5 = 0x50f7 | (phy_a4 << 8);
- } else {
- phy_a5 = 0x70f7 | (phy_a4 << 8);
- }
- wlc_phy_rfctrl_override_nphy(pi,
- (0x1 << 13),
- phy_a5,
- (1 << core), 0);
- } else {
- wlc_phy_rfctrl_override_nphy(pi,
- (0x1 << 13),
- 0x5bf7,
- (1 << core), 0);
- }
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- m[core] = IS40MHZ(pi) ? 45 : 64;
- } else {
- m[core] = IS40MHZ(pi) ? 75 : 107;
- }
-
- m[phy_a7] = 0;
- wlc_phy_ipa_set_bbmult_nphy(pi, m[0], m[1]);
-
- phy_a2 = 63;
-
- if (cal_mode == CAL_FULL) {
- phy_a1 = 25;
- phy_a3 = 25;
- } else if (cal_mode == CAL_SOFT) {
- phy_a1 = 25;
- phy_a3 = 25;
- } else if (cal_mode == CAL_GCTRL) {
- phy_a1 = 63;
- phy_a3 = 25;
- } else {
-
- phy_a1 = 25;
- phy_a3 = 25;
- }
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (1) << 0);
-
- mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (0) << 0);
-
- if (NREV_GE(pi->pubpi.phy_rev, 6)) {
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 13), (1) << 13);
-
- mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 13), (0) << 13);
-
- write_phy_reg(pi, 0x2a1, 0x20);
- write_phy_reg(pi, 0x2a2, 0x60);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0xf << 4), (9) << 4);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0xf << 8), (9) << 8);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0xf << 0), (0x2) << 0);
-
- write_phy_reg(pi, 0x2e5, 0x20);
- } else {
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 11), (1) << 11);
-
- mod_phy_reg(pi, (phy_a7 == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 11), (0) << 11);
-
- write_phy_reg(pi, 0x2a1, 0x80);
- write_phy_reg(pi, 0x2a2, 0x600);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x7 << 4), (0) << 4);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x7 << 8), (0) << 8);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x7 << 0), (0x3) << 0);
-
- mod_phy_reg(pi, 0x2a0, (0x3f << 8), (0x20) << 8);
-
- }
-
- mod_phy_reg(pi, 0x2a0, (0x3f << 0), (phy_a3) << 0);
-
- mod_phy_reg(pi, 0x29f, (0x3f << 0), (phy_a1) << 0);
-
- mod_phy_reg(pi, 0x29f, (0x3f << 8), (phy_a2) << 8);
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 1, 0x3, 0);
-
- write_phy_reg(pi, 0x2be, 1);
- SPINWAIT(read_phy_reg(pi, 0x2be), 10 * 1000 * 1000);
-
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 3), 0, 0x3, 0);
-
- wlc_phy_table_write_nphy(pi,
- (core ==
- PHY_CORE_0) ? NPHY_TBL_ID_EPSILONTBL0
- : NPHY_TBL_ID_EPSILONTBL1, 1, phy_a3,
- 32, &phy_a8);
-
- if (cal_mode != CAL_GCTRL) {
- wlc_phy_a1_nphy(pi, core, 5, 0, 40);
- }
- }
-}
-
-static u8 wlc_phy_a3_nphy(phy_info_t *pi, u8 start_gain, u8 core)
-{
- int phy_a1;
- int phy_a2;
- bool phy_a3;
- nphy_ipa_txcalgains_t phy_a4;
- bool phy_a5 = false;
- bool phy_a6 = true;
- s32 phy_a7, phy_a8;
- u32 phy_a9;
- int phy_a10;
- bool phy_a11 = false;
- int phy_a12;
- u8 phy_a13 = 0;
- u8 phy_a14;
- u8 *phy_a15 = NULL;
-
- phy_a4.useindex = true;
- phy_a12 = start_gain;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
-
- phy_a2 = 20;
- phy_a1 = 1;
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (pi->pubpi.radiorev == 5) {
-
- phy_a15 = pad_gain_codes_used_2057rev5;
- phy_a13 = sizeof(pad_gain_codes_used_2057rev5) /
- sizeof(pad_gain_codes_used_2057rev5[0]) - 1;
-
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- phy_a15 = pad_gain_codes_used_2057rev7;
- phy_a13 = sizeof(pad_gain_codes_used_2057rev7) /
- sizeof(pad_gain_codes_used_2057rev7[0]) - 1;
-
- } else {
-
- phy_a15 = pad_all_gain_codes_2057;
- phy_a13 = sizeof(pad_all_gain_codes_2057) /
- sizeof(pad_all_gain_codes_2057[0]) - 1;
- }
-
- } else {
-
- phy_a15 = pga_all_gain_codes_2057;
- phy_a13 = sizeof(pga_all_gain_codes_2057) /
- sizeof(pga_all_gain_codes_2057[0]) - 1;
- }
-
- phy_a14 = 0;
-
- for (phy_a10 = 0; phy_a10 < phy_a2; phy_a10++) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- phy_a4.gains.pad[core] =
- (u16) phy_a15[phy_a12];
- } else {
- phy_a4.gains.pga[core] =
- (u16) phy_a15[phy_a12];
- }
-
- wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core);
-
- wlc_phy_table_read_nphy(pi,
- (core ==
- PHY_CORE_0 ?
- NPHY_TBL_ID_EPSILONTBL0 :
- NPHY_TBL_ID_EPSILONTBL1), 1,
- 63, 32, &phy_a9);
-
- wlc_phy_papd_decode_epsilon(phy_a9, &phy_a7, &phy_a8);
-
- phy_a3 = ((phy_a7 == 4095) || (phy_a7 == -4096) ||
- (phy_a8 == 4095) || (phy_a8 == -4096));
-
- if (!phy_a6 && (phy_a3 != phy_a5)) {
- if (!phy_a3) {
- phy_a12 -= (u8) phy_a1;
- }
- phy_a11 = true;
- break;
- }
-
- if (phy_a3)
- phy_a12 += (u8) phy_a1;
- else
- phy_a12 -= (u8) phy_a1;
-
- if ((phy_a12 < phy_a14) || (phy_a12 > phy_a13)) {
- if (phy_a12 < phy_a14) {
- phy_a12 = phy_a14;
- } else {
- phy_a12 = phy_a13;
- }
- phy_a11 = true;
- break;
- }
-
- phy_a6 = false;
- phy_a5 = phy_a3;
- }
-
- } else {
- phy_a2 = 10;
- phy_a1 = 8;
- for (phy_a10 = 0; phy_a10 < phy_a2; phy_a10++) {
- phy_a4.index = (u8) phy_a12;
- wlc_phy_a2_nphy(pi, &phy_a4, CAL_GCTRL, core);
-
- wlc_phy_table_read_nphy(pi,
- (core ==
- PHY_CORE_0 ?
- NPHY_TBL_ID_EPSILONTBL0 :
- NPHY_TBL_ID_EPSILONTBL1), 1,
- 63, 32, &phy_a9);
-
- wlc_phy_papd_decode_epsilon(phy_a9, &phy_a7, &phy_a8);
-
- phy_a3 = ((phy_a7 == 4095) || (phy_a7 == -4096) ||
- (phy_a8 == 4095) || (phy_a8 == -4096));
-
- if (!phy_a6 && (phy_a3 != phy_a5)) {
- if (!phy_a3) {
- phy_a12 -= (u8) phy_a1;
- }
- phy_a11 = true;
- break;
- }
-
- if (phy_a3)
- phy_a12 += (u8) phy_a1;
- else
- phy_a12 -= (u8) phy_a1;
-
- if ((phy_a12 < 0) || (phy_a12 > 127)) {
- if (phy_a12 < 0) {
- phy_a12 = 0;
- } else {
- phy_a12 = 127;
- }
- phy_a11 = true;
- break;
- }
-
- phy_a6 = false;
- phy_a5 = phy_a3;
- }
-
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- return (u8) phy_a15[phy_a12];
- } else {
- return (u8) phy_a12;
- }
-
-}
-
-static void wlc_phy_a4(phy_info_t *pi, bool full_cal)
-{
- nphy_ipa_txcalgains_t phy_b1[2];
- nphy_papd_restore_state phy_b2;
- bool phy_b3;
- u8 phy_b4;
- u8 phy_b5;
- s16 phy_b6, phy_b7, phy_b8;
- u16 phy_b9;
- s16 phy_b10, phy_b11, phy_b12;
-
- phy_b11 = 0;
- phy_b12 = 0;
- phy_b7 = 0;
- phy_b8 = 0;
- phy_b6 = 0;
-
- if (pi->nphy_papd_skip == 1)
- return;
-
- phy_b3 =
- (0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
- if (!phy_b3) {
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
- }
-
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- pi->nphy_force_papd_cal = false;
-
- for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++)
- pi->nphy_papd_tx_gain_at_last_cal[phy_b5] =
- wlc_phy_txpwr_idx_cur_get_nphy(pi, phy_b5);
-
- pi->nphy_papd_last_cal = pi->sh->now;
- pi->nphy_papd_recal_counter++;
-
- if (NORADIO_ENAB(pi->pubpi))
- return;
-
- phy_b4 = pi->nphy_txpwrctrl;
- wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SCALARTBL0, 64, 0, 32,
- nphy_papd_scaltbl);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_SCALARTBL1, 64, 0, 32,
- nphy_papd_scaltbl);
-
- phy_b9 = read_phy_reg(pi, 0x01);
- mod_phy_reg(pi, 0x01, (0x1 << 15), 0);
-
- for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
- s32 i, val = 0;
- for (i = 0; i < 64; i++) {
- wlc_phy_table_write_nphy(pi,
- ((phy_b5 ==
- PHY_CORE_0) ?
- NPHY_TBL_ID_EPSILONTBL0 :
- NPHY_TBL_ID_EPSILONTBL1), 1,
- i, 32, &val);
- }
- }
-
- wlc_phy_ipa_restore_tx_digi_filts_nphy(pi);
-
- phy_b2.mm = wlc_phy_ipa_get_bbmult_nphy(pi);
- for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
- wlc_phy_papd_cal_setup_nphy(pi, &phy_b2, phy_b5);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
-
- if ((pi->pubpi.radiorev == 3)
- || (pi->pubpi.radiorev == 4)
- || (pi->pubpi.radiorev == 6)) {
-
- pi->nphy_papd_cal_gain_index[phy_b5] =
- 23;
-
- } else if (pi->pubpi.radiorev == 5) {
-
- pi->nphy_papd_cal_gain_index[phy_b5] =
- 0;
- pi->nphy_papd_cal_gain_index[phy_b5] =
- wlc_phy_a3_nphy(pi,
- pi->
- nphy_papd_cal_gain_index
- [phy_b5], phy_b5);
-
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
-
- pi->nphy_papd_cal_gain_index[phy_b5] =
- 0;
- pi->nphy_papd_cal_gain_index[phy_b5] =
- wlc_phy_a3_nphy(pi,
- pi->
- nphy_papd_cal_gain_index
- [phy_b5], phy_b5);
-
- }
-
- phy_b1[phy_b5].gains.pad[phy_b5] =
- pi->nphy_papd_cal_gain_index[phy_b5];
-
- } else {
- pi->nphy_papd_cal_gain_index[phy_b5] = 0;
- pi->nphy_papd_cal_gain_index[phy_b5] =
- wlc_phy_a3_nphy(pi,
- pi->
- nphy_papd_cal_gain_index
- [phy_b5], phy_b5);
- phy_b1[phy_b5].gains.pga[phy_b5] =
- pi->nphy_papd_cal_gain_index[phy_b5];
- }
- } else {
- phy_b1[phy_b5].useindex = true;
- phy_b1[phy_b5].index = 16;
- phy_b1[phy_b5].index =
- wlc_phy_a3_nphy(pi, phy_b1[phy_b5].index, phy_b5);
-
- pi->nphy_papd_cal_gain_index[phy_b5] =
- 15 - ((phy_b1[phy_b5].index) >> 3);
- }
-
- switch (pi->nphy_papd_cal_type) {
- case 0:
- wlc_phy_a2_nphy(pi, &phy_b1[phy_b5], CAL_FULL, phy_b5);
- break;
- case 1:
- wlc_phy_a2_nphy(pi, &phy_b1[phy_b5], CAL_SOFT, phy_b5);
- break;
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_papd_cal_cleanup_nphy(pi, &phy_b2);
- }
- }
-
- if (NREV_LT(pi->pubpi.phy_rev, 7)) {
- wlc_phy_papd_cal_cleanup_nphy(pi, &phy_b2);
- }
-
- for (phy_b5 = 0; phy_b5 < pi->pubpi.phy_corenum; phy_b5++) {
- int eps_offset = 0;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- if (pi->pubpi.radiorev == 3) {
- eps_offset = -2;
- } else if (pi->pubpi.radiorev == 5) {
- eps_offset = 3;
- } else {
- eps_offset = -1;
- }
- } else {
- eps_offset = 2;
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- phy_b8 = phy_b1[phy_b5].gains.pad[phy_b5];
- phy_b10 = 0;
- if ((pi->pubpi.radiorev == 3) ||
- (pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
- phy_b12 =
- -
- (nphy_papd_padgain_dlt_2g_2057rev3n4
- [phy_b8]
- + 1) / 2;
- phy_b10 = -1;
- } else if (pi->pubpi.radiorev == 5) {
- phy_b12 =
- -(nphy_papd_padgain_dlt_2g_2057rev5
- [phy_b8]
- + 1) / 2;
- } else if ((pi->pubpi.radiorev == 7) ||
- (pi->pubpi.radiorev == 8)) {
- phy_b12 =
- -(nphy_papd_padgain_dlt_2g_2057rev7
- [phy_b8]
- + 1) / 2;
- }
- } else {
- phy_b7 = phy_b1[phy_b5].gains.pga[phy_b5];
- if ((pi->pubpi.radiorev == 3) ||
- (pi->pubpi.radiorev == 4) ||
- (pi->pubpi.radiorev == 6)) {
- phy_b11 =
- -(nphy_papd_pgagain_dlt_5g_2057
- [phy_b7]
- + 1) / 2;
- } else if ((pi->pubpi.radiorev == 7)
- || (pi->pubpi.radiorev == 8)) {
- phy_b11 =
- -(nphy_papd_pgagain_dlt_5g_2057rev7
- [phy_b7]
- + 1) / 2;
- }
-
- phy_b10 = -9;
- }
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- phy_b6 =
- -60 + 27 + eps_offset + phy_b12 + phy_b10;
- } else {
- phy_b6 =
- -60 + 27 + eps_offset + phy_b11 + phy_b10;
- }
-
- mod_phy_reg(pi, (phy_b5 == PHY_CORE_0) ? 0x298 :
- 0x29c, (0x1ff << 7), (phy_b6) << 7);
-
- pi->nphy_papd_epsilon_offset[phy_b5] = phy_b6;
- } else {
- if (NREV_LT(pi->pubpi.phy_rev, 5)) {
- eps_offset = 4;
- } else {
- eps_offset = 2;
- }
-
- phy_b7 = 15 - ((phy_b1[phy_b5].index) >> 3);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- phy_b11 =
- -(nphy_papd_pga_gain_delta_ipa_2g[phy_b7] +
- 1) / 2;
- phy_b10 = 0;
- } else {
- phy_b11 =
- -(nphy_papd_pga_gain_delta_ipa_5g[phy_b7] +
- 1) / 2;
- phy_b10 = -9;
- }
-
- phy_b6 = -60 + 27 + eps_offset + phy_b11 + phy_b10;
-
- mod_phy_reg(pi, (phy_b5 == PHY_CORE_0) ? 0x298 :
- 0x29c, (0x1ff << 7), (phy_b6) << 7);
-
- pi->nphy_papd_epsilon_offset[phy_b5] = phy_b6;
- }
- }
-
- mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
-
- mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 0), (NPHY_PAPD_COMP_ON) << 0);
-
- if (NREV_GE(pi->pubpi.phy_rev, 6)) {
- mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 13), (0) << 13);
-
- mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 13), (0) << 13);
-
- } else {
- mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 11), (0) << 11);
-
- mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x2a3 :
- 0x2a4, (0x1 << 11), (0) << 11);
-
- }
- pi->nphy_papdcomp = NPHY_PAPD_COMP_ON;
-
- write_phy_reg(pi, 0x01, phy_b9);
-
- wlc_phy_ipa_set_tx_digi_filts_nphy(pi);
-
- wlc_phy_txpwrctrl_enable_nphy(pi, phy_b4);
- if (phy_b4 == PHY_TPC_HW_OFF) {
- wlc_phy_txpwr_index_nphy(pi, (1 << 0),
- (s8) (pi->nphy_txpwrindex[0].
- index_internal), false);
- wlc_phy_txpwr_index_nphy(pi, (1 << 1),
- (s8) (pi->nphy_txpwrindex[1].
- index_internal), false);
- }
-
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-
- if (!phy_b3) {
- wlapi_enable_mac(pi->sh->physhim);
- }
-}
-
-void wlc_phy_txpwr_fixpower_nphy(phy_info_t *pi)
-{
- uint core;
- u32 txgain;
- u16 rad_gain, dac_gain, bbmult, m1m2;
- u8 txpi[2], chan_freq_range;
- s32 rfpwr_offset;
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- if (pi->sh->sromrev < 4) {
- txpi[0] = txpi[1] = 72;
- } else {
-
- chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
- switch (chan_freq_range) {
- case WL_CHAN_FREQ_RANGE_2G:
- txpi[0] = pi->nphy_txpid2g[0];
- txpi[1] = pi->nphy_txpid2g[1];
- break;
- case WL_CHAN_FREQ_RANGE_5GL:
- txpi[0] = pi->nphy_txpid5gl[0];
- txpi[1] = pi->nphy_txpid5gl[1];
- break;
- case WL_CHAN_FREQ_RANGE_5GM:
- txpi[0] = pi->nphy_txpid5g[0];
- txpi[1] = pi->nphy_txpid5g[1];
- break;
- case WL_CHAN_FREQ_RANGE_5GH:
- txpi[0] = pi->nphy_txpid5gh[0];
- txpi[1] = pi->nphy_txpid5gh[1];
- break;
- default:
- txpi[0] = txpi[1] = 91;
- break;
- }
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- txpi[0] = txpi[1] = 30;
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- txpi[0] = txpi[1] = 40;
- }
-
- if (NREV_LT(pi->pubpi.phy_rev, 7)) {
-
- if ((txpi[0] < 40) || (txpi[0] > 100) ||
- (txpi[1] < 40) || (txpi[1] > 100))
- txpi[0] = txpi[1] = 91;
- }
-
- pi->nphy_txpwrindex[PHY_CORE_0].index_internal = txpi[0];
- pi->nphy_txpwrindex[PHY_CORE_1].index_internal = txpi[1];
- pi->nphy_txpwrindex[PHY_CORE_0].index_internal_save = txpi[0];
- pi->nphy_txpwrindex[PHY_CORE_1].index_internal_save = txpi[1];
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (PHY_IPA(pi)) {
- u32 *tx_gaintbl =
- wlc_phy_get_ipa_gaintbl_nphy(pi);
- txgain = tx_gaintbl[txpi[core]];
- } else {
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if NREV_IS
- (pi->pubpi.phy_rev, 3) {
- txgain =
- nphy_tpc_5GHz_txgain_rev3
- [txpi[core]];
- } else if NREV_IS
- (pi->pubpi.phy_rev, 4) {
- txgain =
- (pi->srom_fem5g.extpagain ==
- 3) ?
- nphy_tpc_5GHz_txgain_HiPwrEPA
- [txpi[core]] :
- nphy_tpc_5GHz_txgain_rev4
- [txpi[core]];
- } else {
- txgain =
- nphy_tpc_5GHz_txgain_rev5
- [txpi[core]];
- }
- } else {
- if (NREV_GE(pi->pubpi.phy_rev, 5) &&
- (pi->srom_fem2g.extpagain == 3)) {
- txgain =
- nphy_tpc_txgain_HiPwrEPA
- [txpi[core]];
- } else {
- txgain =
- nphy_tpc_txgain_rev3[txpi
- [core]];
- }
- }
- }
- } else {
- txgain = nphy_tpc_txgain[txpi[core]];
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- rad_gain = (txgain >> 16) & ((1 << (32 - 16 + 1)) - 1);
- } else {
- rad_gain = (txgain >> 16) & ((1 << (28 - 16 + 1)) - 1);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- dac_gain = (txgain >> 8) & ((1 << (10 - 8 + 1)) - 1);
- } else {
- dac_gain = (txgain >> 8) & ((1 << (13 - 8 + 1)) - 1);
- }
- bbmult = (txgain >> 0) & ((1 << (7 - 0 + 1)) - 1);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
- 0xa5), (0x1 << 8), (0x1 << 8));
- } else {
- mod_phy_reg(pi, 0xa5, (0x1 << 14), (0x1 << 14));
- }
- write_phy_reg(pi, (core == PHY_CORE_0) ? 0xaa : 0xab, dac_gain);
-
- wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
- &rad_gain);
-
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
- m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
- m1m2 |= ((core == PHY_CORE_0) ? (bbmult << 8) : (bbmult << 0));
- wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
-
- if (PHY_IPA(pi)) {
- wlc_phy_table_read_nphy(pi,
- (core ==
- PHY_CORE_0 ?
- NPHY_TBL_ID_CORE1TXPWRCTL :
- NPHY_TBL_ID_CORE2TXPWRCTL), 1,
- 576 + txpi[core], 32,
- &rfpwr_offset);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1ff << 4),
- ((s16) rfpwr_offset) << 4);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 2), (1) << 2);
-
- }
- }
-
- and_phy_reg(pi, 0xbf, (u16) (~(0x1f << 0)));
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-static void
-wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max, u16 *pwr_offset,
- u8 tmp_max_pwr, u8 rate_start,
- u8 rate_end)
-{
- u8 rate;
- u8 word_num, nibble_num;
- u8 tmp_nibble;
-
- for (rate = rate_start; rate <= rate_end; rate++) {
- word_num = (rate - rate_start) >> 2;
- nibble_num = (rate - rate_start) & 0x3;
- tmp_nibble = (pwr_offset[word_num] >> 4 * nibble_num) & 0xf;
-
- srom_max[rate] = tmp_max_pwr - 2 * tmp_nibble;
- }
-}
-
-static void
-wlc_phy_txpwr_nphy_po_apply(u8 *srom_max, u8 pwr_offset,
- u8 rate_start, u8 rate_end)
-{
- u8 rate;
-
- for (rate = rate_start; rate <= rate_end; rate++) {
- srom_max[rate] -= 2 * pwr_offset;
- }
-}
-
-void
-wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
- u8 rate_mcs_end, u8 rate_ofdm_start)
-{
- u8 rate1, rate2;
-
- rate2 = rate_ofdm_start;
- for (rate1 = rate_mcs_start; rate1 <= rate_mcs_end - 1; rate1++) {
- power[rate1] = power[rate2];
- rate2 += (rate1 == rate_mcs_start) ? 2 : 1;
- }
- power[rate_mcs_end] = power[rate_mcs_end - 1];
-}
-
-void
-wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, u8 rate_ofdm_start,
- u8 rate_ofdm_end, u8 rate_mcs_start)
-{
- u8 rate1, rate2;
-
- for (rate1 = rate_ofdm_start, rate2 = rate_mcs_start;
- rate1 <= rate_ofdm_end; rate1++, rate2++) {
- power[rate1] = power[rate2];
- if (rate1 == rate_ofdm_start)
- power[++rate1] = power[rate2];
- }
-}
-
-void wlc_phy_txpwr_apply_nphy(phy_info_t *pi)
-{
- uint rate1, rate2, band_num;
- u8 tmp_bw40po = 0, tmp_cddpo = 0, tmp_stbcpo = 0;
- u8 tmp_max_pwr = 0;
- u16 pwr_offsets1[2], *pwr_offsets2 = NULL;
- u8 *tx_srom_max_rate = NULL;
-
- for (band_num = 0; band_num < (CH_2G_GROUP + CH_5G_GROUP); band_num++) {
- switch (band_num) {
- case 0:
-
- tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_2g,
- pi->nphy_pwrctrl_info[1].max_pwr_2g);
-
- pwr_offsets1[0] = pi->cck2gpo;
- wlc_phy_txpwr_nphy_srom_convert(pi->tx_srom_max_rate_2g,
- pwr_offsets1,
- tmp_max_pwr,
- TXP_FIRST_CCK,
- TXP_LAST_CCK);
-
- pwr_offsets1[0] = (u16) (pi->ofdm2gpo & 0xffff);
- pwr_offsets1[1] =
- (u16) (pi->ofdm2gpo >> 16) & 0xffff;
-
- pwr_offsets2 = pi->mcs2gpo;
-
- tmp_cddpo = pi->cdd2gpo;
- tmp_stbcpo = pi->stbc2gpo;
- tmp_bw40po = pi->bw402gpo;
-
- tx_srom_max_rate = pi->tx_srom_max_rate_2g;
- break;
- case 1:
-
- tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gm,
- pi->nphy_pwrctrl_info[1].max_pwr_5gm);
-
- pwr_offsets1[0] = (u16) (pi->ofdm5gpo & 0xffff);
- pwr_offsets1[1] =
- (u16) (pi->ofdm5gpo >> 16) & 0xffff;
-
- pwr_offsets2 = pi->mcs5gpo;
-
- tmp_cddpo = pi->cdd5gpo;
- tmp_stbcpo = pi->stbc5gpo;
- tmp_bw40po = pi->bw405gpo;
-
- tx_srom_max_rate = pi->tx_srom_max_rate_5g_mid;
- break;
- case 2:
-
- tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gl,
- pi->nphy_pwrctrl_info[1].max_pwr_5gl);
-
- pwr_offsets1[0] = (u16) (pi->ofdm5glpo & 0xffff);
- pwr_offsets1[1] =
- (u16) (pi->ofdm5glpo >> 16) & 0xffff;
-
- pwr_offsets2 = pi->mcs5glpo;
-
- tmp_cddpo = pi->cdd5glpo;
- tmp_stbcpo = pi->stbc5glpo;
- tmp_bw40po = pi->bw405glpo;
-
- tx_srom_max_rate = pi->tx_srom_max_rate_5g_low;
- break;
- case 3:
-
- tmp_max_pwr = min(pi->nphy_pwrctrl_info[0].max_pwr_5gh,
- pi->nphy_pwrctrl_info[1].max_pwr_5gh);
-
- pwr_offsets1[0] = (u16) (pi->ofdm5ghpo & 0xffff);
- pwr_offsets1[1] =
- (u16) (pi->ofdm5ghpo >> 16) & 0xffff;
-
- pwr_offsets2 = pi->mcs5ghpo;
-
- tmp_cddpo = pi->cdd5ghpo;
- tmp_stbcpo = pi->stbc5ghpo;
- tmp_bw40po = pi->bw405ghpo;
-
- tx_srom_max_rate = pi->tx_srom_max_rate_5g_hi;
- break;
- }
-
- wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets1,
- tmp_max_pwr, TXP_FIRST_OFDM,
- TXP_LAST_OFDM);
-
- wlc_phy_ofdm_to_mcs_powers_nphy(tx_srom_max_rate,
- TXP_FIRST_MCS_20_SISO,
- TXP_LAST_MCS_20_SISO,
- TXP_FIRST_OFDM);
-
- wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2,
- tmp_max_pwr,
- TXP_FIRST_MCS_20_CDD,
- TXP_LAST_MCS_20_CDD);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, tmp_cddpo,
- TXP_FIRST_MCS_20_CDD,
- TXP_LAST_MCS_20_CDD);
- }
-
- wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
- TXP_FIRST_OFDM_20_CDD,
- TXP_LAST_OFDM_20_CDD,
- TXP_FIRST_MCS_20_CDD);
-
- wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2,
- tmp_max_pwr,
- TXP_FIRST_MCS_20_STBC,
- TXP_LAST_MCS_20_STBC);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
- tmp_stbcpo,
- TXP_FIRST_MCS_20_STBC,
- TXP_LAST_MCS_20_STBC);
- }
-
- wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
- &pwr_offsets2[2], tmp_max_pwr,
- TXP_FIRST_MCS_20_SDM,
- TXP_LAST_MCS_20_SDM);
-
- if (NPHY_IS_SROM_REINTERPRET) {
-
- wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
- &pwr_offsets2[4],
- tmp_max_pwr,
- TXP_FIRST_MCS_40_SISO,
- TXP_LAST_MCS_40_SISO);
-
- wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
- TXP_FIRST_OFDM_40_SISO,
- TXP_LAST_OFDM_40_SISO,
- TXP_FIRST_MCS_40_SISO);
-
- wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
- &pwr_offsets2[4],
- tmp_max_pwr,
- TXP_FIRST_MCS_40_CDD,
- TXP_LAST_MCS_40_CDD);
-
- wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, tmp_cddpo,
- TXP_FIRST_MCS_40_CDD,
- TXP_LAST_MCS_40_CDD);
-
- wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate,
- TXP_FIRST_OFDM_40_CDD,
- TXP_LAST_OFDM_40_CDD,
- TXP_FIRST_MCS_40_CDD);
-
- wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
- &pwr_offsets2[4],
- tmp_max_pwr,
- TXP_FIRST_MCS_40_STBC,
- TXP_LAST_MCS_40_STBC);
-
- wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
- tmp_stbcpo,
- TXP_FIRST_MCS_40_STBC,
- TXP_LAST_MCS_40_STBC);
-
- wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate,
- &pwr_offsets2[6],
- tmp_max_pwr,
- TXP_FIRST_MCS_40_SDM,
- TXP_LAST_MCS_40_SDM);
- } else {
-
- for (rate1 = TXP_FIRST_OFDM_40_SISO, rate2 =
- TXP_FIRST_OFDM; rate1 <= TXP_LAST_MCS_40_SDM;
- rate1++, rate2++)
- tx_srom_max_rate[rate1] =
- tx_srom_max_rate[rate2];
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate,
- tmp_bw40po,
- TXP_FIRST_OFDM_40_SISO,
- TXP_LAST_MCS_40_SDM);
- }
-
- tx_srom_max_rate[TXP_MCS_32] =
- tx_srom_max_rate[TXP_FIRST_MCS_40_CDD];
- }
-
- return;
-}
-
-static void wlc_phy_txpwr_srom_read_ppr_nphy(phy_info_t *pi)
-{
- u16 bw40po, cddpo, stbcpo, bwduppo;
- uint band_num;
-
- if (pi->sh->sromrev >= 9) {
-
- return;
- }
-
- bw40po = (u16) PHY_GETINTVAR(pi, "bw40po");
- pi->bw402gpo = bw40po & 0xf;
- pi->bw405gpo = (bw40po & 0xf0) >> 4;
- pi->bw405glpo = (bw40po & 0xf00) >> 8;
- pi->bw405ghpo = (bw40po & 0xf000) >> 12;
-
- cddpo = (u16) PHY_GETINTVAR(pi, "cddpo");
- pi->cdd2gpo = cddpo & 0xf;
- pi->cdd5gpo = (cddpo & 0xf0) >> 4;
- pi->cdd5glpo = (cddpo & 0xf00) >> 8;
- pi->cdd5ghpo = (cddpo & 0xf000) >> 12;
-
- stbcpo = (u16) PHY_GETINTVAR(pi, "stbcpo");
- pi->stbc2gpo = stbcpo & 0xf;
- pi->stbc5gpo = (stbcpo & 0xf0) >> 4;
- pi->stbc5glpo = (stbcpo & 0xf00) >> 8;
- pi->stbc5ghpo = (stbcpo & 0xf000) >> 12;
-
- bwduppo = (u16) PHY_GETINTVAR(pi, "bwduppo");
- pi->bwdup2gpo = bwduppo & 0xf;
- pi->bwdup5gpo = (bwduppo & 0xf0) >> 4;
- pi->bwdup5glpo = (bwduppo & 0xf00) >> 8;
- pi->bwdup5ghpo = (bwduppo & 0xf000) >> 12;
-
- for (band_num = 0; band_num < (CH_2G_GROUP + CH_5G_GROUP); band_num++) {
- switch (band_num) {
- case 0:
-
- pi->nphy_txpid2g[PHY_CORE_0] =
- (u8) PHY_GETINTVAR(pi, "txpid2ga0");
- pi->nphy_txpid2g[PHY_CORE_1] =
- (u8) PHY_GETINTVAR(pi, "txpid2ga1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g =
- (s8) PHY_GETINTVAR(pi, "maxp2ga0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_2g =
- (s8) PHY_GETINTVAR(pi, "maxp2ga1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_a1 =
- (s16) PHY_GETINTVAR(pi, "pa2gw0a0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_a1 =
- (s16) PHY_GETINTVAR(pi, "pa2gw0a1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b0 =
- (s16) PHY_GETINTVAR(pi, "pa2gw1a0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b0 =
- (s16) PHY_GETINTVAR(pi, "pa2gw1a1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b1 =
- (s16) PHY_GETINTVAR(pi, "pa2gw2a0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b1 =
- (s16) PHY_GETINTVAR(pi, "pa2gw2a1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_2g =
- (s8) PHY_GETINTVAR(pi, "itt2ga0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g =
- (s8) PHY_GETINTVAR(pi, "itt2ga1");
-
- pi->cck2gpo = (u16) PHY_GETINTVAR(pi, "cck2gpo");
-
- pi->ofdm2gpo = (u32) PHY_GETINTVAR(pi, "ofdm2gpo");
-
- pi->mcs2gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs2gpo0");
- pi->mcs2gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs2gpo1");
- pi->mcs2gpo[2] = (u16) PHY_GETINTVAR(pi, "mcs2gpo2");
- pi->mcs2gpo[3] = (u16) PHY_GETINTVAR(pi, "mcs2gpo3");
- pi->mcs2gpo[4] = (u16) PHY_GETINTVAR(pi, "mcs2gpo4");
- pi->mcs2gpo[5] = (u16) PHY_GETINTVAR(pi, "mcs2gpo5");
- pi->mcs2gpo[6] = (u16) PHY_GETINTVAR(pi, "mcs2gpo6");
- pi->mcs2gpo[7] = (u16) PHY_GETINTVAR(pi, "mcs2gpo7");
- break;
- case 1:
-
- pi->nphy_txpid5g[PHY_CORE_0] =
- (u8) PHY_GETINTVAR(pi, "txpid5ga0");
- pi->nphy_txpid5g[PHY_CORE_1] =
- (u8) PHY_GETINTVAR(pi, "txpid5ga1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm =
- (s8) PHY_GETINTVAR(pi, "maxp5ga0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm =
- (s8) PHY_GETINTVAR(pi, "maxp5ga1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_a1 =
- (s16) PHY_GETINTVAR(pi, "pa5gw0a0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_a1 =
- (s16) PHY_GETINTVAR(pi, "pa5gw0a1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b0 =
- (s16) PHY_GETINTVAR(pi, "pa5gw1a0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b0 =
- (s16) PHY_GETINTVAR(pi, "pa5gw1a1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b1 =
- (s16) PHY_GETINTVAR(pi, "pa5gw2a0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b1 =
- (s16) PHY_GETINTVAR(pi, "pa5gw2a1");
- pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_5gm =
- (s8) PHY_GETINTVAR(pi, "itt5ga0");
- pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
- (s8) PHY_GETINTVAR(pi, "itt5ga1");
-
- pi->ofdm5gpo = (u32) PHY_GETINTVAR(pi, "ofdm5gpo");
-
- pi->mcs5gpo[0] = (u16) PHY_GETINTVAR(pi, "mcs5gpo0");
- pi->mcs5gpo[1] = (u16) PHY_GETINTVAR(pi, "mcs5gpo1");
- pi->mcs5gpo[2] = (u16) PHY_GETINTVAR(pi, "mcs5gpo2");
- pi->mcs5gpo[3] = (u16) PHY_GETINTVAR(pi, "mcs5gpo3");
- pi->mcs5gpo[4] = (u16) PHY_GETINTVAR(pi, "mcs5gpo4");
- pi->mcs5gpo[5] = (u16) PHY_GETINTVAR(pi, "mcs5gpo5");
- pi->mcs5gpo[6] = (u16) PHY_GETINTVAR(pi, "mcs5gpo6");
- pi->mcs5gpo[7] = (u16) PHY_GETINTVAR(pi, "mcs5gpo7");
- break;
- case 2:
-
- pi->nphy_txpid5gl[0] =
- (u8) PHY_GETINTVAR(pi, "txpid5gla0");
- pi->nphy_txpid5gl[1] =
- (u8) PHY_GETINTVAR(pi, "txpid5gla1");
- pi->nphy_pwrctrl_info[0].max_pwr_5gl =
- (s8) PHY_GETINTVAR(pi, "maxp5gla0");
- pi->nphy_pwrctrl_info[1].max_pwr_5gl =
- (s8) PHY_GETINTVAR(pi, "maxp5gla1");
- pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 =
- (s16) PHY_GETINTVAR(pi, "pa5glw0a0");
- pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 =
- (s16) PHY_GETINTVAR(pi, "pa5glw0a1");
- pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 =
- (s16) PHY_GETINTVAR(pi, "pa5glw1a0");
- pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 =
- (s16) PHY_GETINTVAR(pi, "pa5glw1a1");
- pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 =
- (s16) PHY_GETINTVAR(pi, "pa5glw2a0");
- pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 =
- (s16) PHY_GETINTVAR(pi, "pa5glw2a1");
- pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
- pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
-
- pi->ofdm5glpo = (u32) PHY_GETINTVAR(pi, "ofdm5glpo");
-
- pi->mcs5glpo[0] =
- (u16) PHY_GETINTVAR(pi, "mcs5glpo0");
- pi->mcs5glpo[1] =
- (u16) PHY_GETINTVAR(pi, "mcs5glpo1");
- pi->mcs5glpo[2] =
- (u16) PHY_GETINTVAR(pi, "mcs5glpo2");
- pi->mcs5glpo[3] =
- (u16) PHY_GETINTVAR(pi, "mcs5glpo3");
- pi->mcs5glpo[4] =
- (u16) PHY_GETINTVAR(pi, "mcs5glpo4");
- pi->mcs5glpo[5] =
- (u16) PHY_GETINTVAR(pi, "mcs5glpo5");
- pi->mcs5glpo[6] =
- (u16) PHY_GETINTVAR(pi, "mcs5glpo6");
- pi->mcs5glpo[7] =
- (u16) PHY_GETINTVAR(pi, "mcs5glpo7");
- break;
- case 3:
-
- pi->nphy_txpid5gh[0] =
- (u8) PHY_GETINTVAR(pi, "txpid5gha0");
- pi->nphy_txpid5gh[1] =
- (u8) PHY_GETINTVAR(pi, "txpid5gha1");
- pi->nphy_pwrctrl_info[0].max_pwr_5gh =
- (s8) PHY_GETINTVAR(pi, "maxp5gha0");
- pi->nphy_pwrctrl_info[1].max_pwr_5gh =
- (s8) PHY_GETINTVAR(pi, "maxp5gha1");
- pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 =
- (s16) PHY_GETINTVAR(pi, "pa5ghw0a0");
- pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 =
- (s16) PHY_GETINTVAR(pi, "pa5ghw0a1");
- pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 =
- (s16) PHY_GETINTVAR(pi, "pa5ghw1a0");
- pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 =
- (s16) PHY_GETINTVAR(pi, "pa5ghw1a1");
- pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 =
- (s16) PHY_GETINTVAR(pi, "pa5ghw2a0");
- pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 =
- (s16) PHY_GETINTVAR(pi, "pa5ghw2a1");
- pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
- pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
-
- pi->ofdm5ghpo = (u32) PHY_GETINTVAR(pi, "ofdm5ghpo");
-
- pi->mcs5ghpo[0] =
- (u16) PHY_GETINTVAR(pi, "mcs5ghpo0");
- pi->mcs5ghpo[1] =
- (u16) PHY_GETINTVAR(pi, "mcs5ghpo1");
- pi->mcs5ghpo[2] =
- (u16) PHY_GETINTVAR(pi, "mcs5ghpo2");
- pi->mcs5ghpo[3] =
- (u16) PHY_GETINTVAR(pi, "mcs5ghpo3");
- pi->mcs5ghpo[4] =
- (u16) PHY_GETINTVAR(pi, "mcs5ghpo4");
- pi->mcs5ghpo[5] =
- (u16) PHY_GETINTVAR(pi, "mcs5ghpo5");
- pi->mcs5ghpo[6] =
- (u16) PHY_GETINTVAR(pi, "mcs5ghpo6");
- pi->mcs5ghpo[7] =
- (u16) PHY_GETINTVAR(pi, "mcs5ghpo7");
- break;
- }
- }
-
- wlc_phy_txpwr_apply_nphy(pi);
-}
-
-static bool wlc_phy_txpwr_srom_read_nphy(phy_info_t *pi)
-{
-
- pi->antswitch = (u8) PHY_GETINTVAR(pi, "antswitch");
- pi->aa2g = (u8) PHY_GETINTVAR(pi, "aa2g");
- pi->aa5g = (u8) PHY_GETINTVAR(pi, "aa5g");
-
- pi->srom_fem2g.tssipos = (u8) PHY_GETINTVAR(pi, "tssipos2g");
- pi->srom_fem2g.extpagain = (u8) PHY_GETINTVAR(pi, "extpagain2g");
- pi->srom_fem2g.pdetrange = (u8) PHY_GETINTVAR(pi, "pdetrange2g");
- pi->srom_fem2g.triso = (u8) PHY_GETINTVAR(pi, "triso2g");
- pi->srom_fem2g.antswctrllut = (u8) PHY_GETINTVAR(pi, "antswctl2g");
-
- pi->srom_fem5g.tssipos = (u8) PHY_GETINTVAR(pi, "tssipos5g");
- pi->srom_fem5g.extpagain = (u8) PHY_GETINTVAR(pi, "extpagain5g");
- pi->srom_fem5g.pdetrange = (u8) PHY_GETINTVAR(pi, "pdetrange5g");
- pi->srom_fem5g.triso = (u8) PHY_GETINTVAR(pi, "triso5g");
- if (PHY_GETVAR(pi, "antswctl5g")) {
-
- pi->srom_fem5g.antswctrllut =
- (u8) PHY_GETINTVAR(pi, "antswctl5g");
- } else {
-
- pi->srom_fem5g.antswctrllut =
- (u8) PHY_GETINTVAR(pi, "antswctl2g");
- }
-
- wlc_phy_txpower_ipa_upd(pi);
-
- pi->phy_txcore_disable_temp = (s16) PHY_GETINTVAR(pi, "tempthresh");
- if (pi->phy_txcore_disable_temp == 0) {
- pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
- }
-
- pi->phy_tempsense_offset = (s8) PHY_GETINTVAR(pi, "tempoffset");
- if (pi->phy_tempsense_offset != 0) {
- if (pi->phy_tempsense_offset >
- (NPHY_SROM_TEMPSHIFT + NPHY_SROM_MAXTEMPOFFSET)) {
- pi->phy_tempsense_offset = NPHY_SROM_MAXTEMPOFFSET;
- } else if (pi->phy_tempsense_offset < (NPHY_SROM_TEMPSHIFT +
- NPHY_SROM_MINTEMPOFFSET)) {
- pi->phy_tempsense_offset = NPHY_SROM_MINTEMPOFFSET;
- } else {
- pi->phy_tempsense_offset -= NPHY_SROM_TEMPSHIFT;
- }
- }
-
- pi->phy_txcore_enable_temp =
- pi->phy_txcore_disable_temp - PHY_HYSTERESIS_DELTATEMP;
-
- pi->phycal_tempdelta = (u8) PHY_GETINTVAR(pi, "phycal_tempdelta");
- if (pi->phycal_tempdelta > NPHY_CAL_MAXTEMPDELTA) {
- pi->phycal_tempdelta = 0;
- }
-
- wlc_phy_txpwr_srom_read_ppr_nphy(pi);
-
- return true;
-}
-
-void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi)
-{
- u8 tx_pwr_ctrl_state;
- wlc_phy_txpwr_limit_to_tbl_nphy(pi);
- wlc_phy_txpwrctrl_pwr_setup_nphy(pi);
-
- tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
-
- if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
- wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
- (void)R_REG(&pi->regs->maccontrol);
- udelay(1);
- }
-
- wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
-
- if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
- wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
-}
-
-static void wlc_phy_txpwrctrl_coeff_setup_nphy(phy_info_t *pi)
-{
- u32 idx;
- u16 iqloCalbuf[7];
- u32 iqcomp, locomp, curr_locomp;
- s8 locomp_i, locomp_q;
- s8 curr_locomp_i, curr_locomp_q;
- u32 tbl_id, tbl_len, tbl_offset;
- u32 regval[128];
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- wlc_phy_table_read_nphy(pi, 15, 7, 80, 16, iqloCalbuf);
-
- tbl_len = 128;
- tbl_offset = 320;
- for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
- tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
- iqcomp =
- (tbl_id ==
- 26) ? (((u32) (iqloCalbuf[0] & 0x3ff)) << 10) |
- (iqloCalbuf[1] & 0x3ff)
- : (((u32) (iqloCalbuf[2] & 0x3ff)) << 10) |
- (iqloCalbuf[3] & 0x3ff);
-
- for (idx = 0; idx < tbl_len; idx++) {
- regval[idx] = iqcomp;
- }
- wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
- regval);
- }
-
- tbl_offset = 448;
- for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
- tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
-
- locomp =
- (u32) ((tbl_id == 26) ? iqloCalbuf[5] : iqloCalbuf[6]);
- locomp_i = (s8) ((locomp >> 8) & 0xff);
- locomp_q = (s8) ((locomp) & 0xff);
- for (idx = 0; idx < tbl_len; idx++) {
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- curr_locomp_i = locomp_i;
- curr_locomp_q = locomp_q;
- } else {
- curr_locomp_i = (s8) ((locomp_i *
- nphy_tpc_loscale[idx] +
- 128) >> 8);
- curr_locomp_q =
- (s8) ((locomp_q * nphy_tpc_loscale[idx] +
- 128) >> 8);
- }
- curr_locomp = (u32) ((curr_locomp_i & 0xff) << 8);
- curr_locomp |= (u32) (curr_locomp_q & 0xff);
- regval[idx] = curr_locomp;
- }
- wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
- regval);
- }
-
- if (NREV_LT(pi->pubpi.phy_rev, 2)) {
-
- wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX1, 0xFFFF);
- wlapi_bmac_write_shm(pi->sh->physhim, M_CURR_IDX2, 0xFFFF);
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-static void wlc_phy_ipa_internal_tssi_setup_nphy(phy_info_t *pi)
-{
- u8 core;
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MASTER, 0x5);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MUX, 0xe);
-
- if (pi->pubpi.radiorev != 5)
- WRITE_RADIO_REG3(pi, RADIO_2057, TX,
- core, TSSIA, 0);
-
- if (!NREV_IS(pi->pubpi.phy_rev, 7)) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX,
- core, TSSIG, 0x1);
- } else {
-
- WRITE_RADIO_REG3(pi, RADIO_2057, TX,
- core, TSSIG, 0x31);
- }
- } else {
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MASTER, 0x9);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TX_SSI_MUX, 0xc);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
- TSSIG, 0);
-
- if (pi->pubpi.radiorev != 5) {
- if (!NREV_IS(pi->pubpi.phy_rev, 7)) {
-
- WRITE_RADIO_REG3(pi, RADIO_2057,
- TX, core,
- TSSIA, 0x1);
- } else {
-
- WRITE_RADIO_REG3(pi, RADIO_2057,
- TX, core,
- TSSIA, 0x31);
- }
- }
- }
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_VCM_HG,
- 0);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, IQCAL_IDAC,
- 0);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_VCM,
- 0x3);
- WRITE_RADIO_REG3(pi, RADIO_2057, TX, core, TSSI_MISC1,
- 0x0);
- }
- } else {
- WRITE_RADIO_SYN(pi, RADIO_2056, RESERVED_ADDR31,
- (CHSPEC_IS2G(pi->radio_chanspec)) ? 0x128 :
- 0x80);
- WRITE_RADIO_SYN(pi, RADIO_2056, RESERVED_ADDR30, 0x0);
- WRITE_RADIO_SYN(pi, RADIO_2056, GPIO_MASTER1, 0x29);
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, IQCAL_VCM_HG,
- 0x0);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, IQCAL_IDAC,
- 0x0);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_VCM,
- 0x3);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TX_AMP_DET,
- 0x0);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC1,
- 0x8);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC2,
- 0x0);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core, TSSI_MISC3,
- 0x0);
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- TX_SSI_MASTER, 0x5);
-
- if (pi->pubpi.radiorev != 5)
- WRITE_RADIO_REG2(pi, RADIO_2056, TX,
- core, TSSIA, 0x0);
- if (NREV_GE(pi->pubpi.phy_rev, 5)) {
-
- WRITE_RADIO_REG2(pi, RADIO_2056, TX,
- core, TSSIG, 0x31);
- } else {
- WRITE_RADIO_REG2(pi, RADIO_2056, TX,
- core, TSSIG, 0x11);
- }
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- TX_SSI_MUX, 0xe);
- } else {
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- TX_SSI_MASTER, 0x9);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- TSSIA, 0x31);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- TSSIG, 0x0);
- WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
- TX_SSI_MUX, 0xc);
- }
- }
- }
-}
-
-static void wlc_phy_txpwrctrl_idle_tssi_nphy(phy_info_t *pi)
-{
- s32 rssi_buf[4];
- s32 int_val;
-
- if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi) || PHY_MUTED(pi))
-
- return;
-
- if (PHY_IPA(pi)) {
- wlc_phy_ipa_internal_tssi_setup_nphy(pi);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
- 0, 0x3, 0,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 3, 0);
- }
-
- wlc_phy_stopplayback_nphy(pi);
-
- wlc_phy_tx_tone_nphy(pi, 4000, 0, 0, 0, false);
-
- udelay(20);
- int_val =
- wlc_phy_poll_rssi_nphy(pi, (u8) NPHY_RSSI_SEL_TSSI_2G, rssi_buf,
- 1);
- wlc_phy_stopplayback_nphy(pi);
- wlc_phy_rssisel_nphy(pi, RADIO_MIMO_CORESEL_OFF, 0);
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- wlc_phy_rfctrl_override_nphy_rev7(pi, (0x1 << 12),
- 0, 0x3, 1,
- NPHY_REV7_RFCTRLOVERRIDE_ID0);
- } else if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- wlc_phy_rfctrl_override_nphy(pi, (0x1 << 13), 0, 3, 1);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_2g =
- (u8) ((int_val >> 24) & 0xff);
- pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_5g =
- (u8) ((int_val >> 24) & 0xff);
-
- pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_2g =
- (u8) ((int_val >> 8) & 0xff);
- pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_5g =
- (u8) ((int_val >> 8) & 0xff);
- } else {
- pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_2g =
- (u8) ((int_val >> 24) & 0xff);
-
- pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_2g =
- (u8) ((int_val >> 8) & 0xff);
-
- pi->nphy_pwrctrl_info[PHY_CORE_0].idle_tssi_5g =
- (u8) ((int_val >> 16) & 0xff);
- pi->nphy_pwrctrl_info[PHY_CORE_1].idle_tssi_5g =
- (u8) ((int_val) & 0xff);
- }
-
-}
-
-static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
-{
- u32 idx;
- s16 a1[2], b0[2], b1[2];
- s8 target_pwr_qtrdbm[2];
- s32 num, den, pwr_est;
- u8 chan_freq_range;
- u8 idle_tssi[2];
- u32 tbl_id, tbl_len, tbl_offset;
- u32 regval[64];
- u8 core;
-
- if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
- wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
- (void)R_REG(&pi->regs->maccontrol);
- udelay(1);
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- or_phy_reg(pi, 0x122, (0x1 << 0));
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- and_phy_reg(pi, 0x1e7, (u16) (~(0x1 << 15)));
- } else {
-
- or_phy_reg(pi, 0x1e7, (0x1 << 15));
- }
-
- if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
- wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
-
- if (pi->sh->sromrev < 4) {
- idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
- idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
- target_pwr_qtrdbm[0] = 13 * 4;
- target_pwr_qtrdbm[1] = 13 * 4;
- a1[0] = -424;
- a1[1] = -424;
- b0[0] = 5612;
- b0[1] = 5612;
- b1[1] = -1393;
- b1[0] = -1393;
- } else {
-
- chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0);
- switch (chan_freq_range) {
- case WL_CHAN_FREQ_RANGE_2G:
- idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
- idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
- target_pwr_qtrdbm[0] =
- pi->nphy_pwrctrl_info[0].max_pwr_2g;
- target_pwr_qtrdbm[1] =
- pi->nphy_pwrctrl_info[1].max_pwr_2g;
- a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_a1;
- a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_a1;
- b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b0;
- b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b0;
- b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b1;
- b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b1;
- break;
- case WL_CHAN_FREQ_RANGE_5GL:
- idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
- idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
- target_pwr_qtrdbm[0] =
- pi->nphy_pwrctrl_info[0].max_pwr_5gl;
- target_pwr_qtrdbm[1] =
- pi->nphy_pwrctrl_info[1].max_pwr_5gl;
- a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1;
- a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1;
- b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0;
- b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0;
- b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1;
- b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1;
- break;
- case WL_CHAN_FREQ_RANGE_5GM:
- idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
- idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
- target_pwr_qtrdbm[0] =
- pi->nphy_pwrctrl_info[0].max_pwr_5gm;
- target_pwr_qtrdbm[1] =
- pi->nphy_pwrctrl_info[1].max_pwr_5gm;
- a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_a1;
- a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_a1;
- b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b0;
- b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b0;
- b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b1;
- b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b1;
- break;
- case WL_CHAN_FREQ_RANGE_5GH:
- idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_5g;
- idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_5g;
- target_pwr_qtrdbm[0] =
- pi->nphy_pwrctrl_info[0].max_pwr_5gh;
- target_pwr_qtrdbm[1] =
- pi->nphy_pwrctrl_info[1].max_pwr_5gh;
- a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1;
- a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1;
- b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0;
- b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0;
- b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1;
- b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1;
- break;
- default:
- idle_tssi[0] = pi->nphy_pwrctrl_info[0].idle_tssi_2g;
- idle_tssi[1] = pi->nphy_pwrctrl_info[1].idle_tssi_2g;
- target_pwr_qtrdbm[0] = 13 * 4;
- target_pwr_qtrdbm[1] = 13 * 4;
- a1[0] = -424;
- a1[1] = -424;
- b0[0] = 5612;
- b0[1] = 5612;
- b1[1] = -1393;
- b1[0] = -1393;
- break;
- }
- }
-
- target_pwr_qtrdbm[0] = (s8) pi->tx_power_max;
- target_pwr_qtrdbm[1] = (s8) pi->tx_power_max;
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if (pi->srom_fem2g.tssipos) {
- or_phy_reg(pi, 0x1e9, (0x1 << 14));
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- for (core = 0; core <= 1; core++) {
- if (PHY_IPA(pi)) {
-
- if (CHSPEC_IS2G(pi->radio_chanspec)) {
- WRITE_RADIO_REG3(pi, RADIO_2057,
- TX, core,
- TX_SSI_MUX,
- 0xe);
- } else {
- WRITE_RADIO_REG3(pi, RADIO_2057,
- TX, core,
- TX_SSI_MUX,
- 0xc);
- }
- } else {
- }
- }
- } else {
- if (PHY_IPA(pi)) {
-
- write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
- RADIO_2056_TX0,
- (CHSPEC_IS5G
- (pi->
- radio_chanspec)) ? 0xc : 0xe);
- write_radio_reg(pi,
- RADIO_2056_TX_TX_SSI_MUX |
- RADIO_2056_TX1,
- (CHSPEC_IS5G
- (pi->
- radio_chanspec)) ? 0xc : 0xe);
- } else {
-
- write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
- RADIO_2056_TX0, 0x11);
- write_radio_reg(pi, RADIO_2056_TX_TX_SSI_MUX |
- RADIO_2056_TX1, 0x11);
- }
- }
- }
-
- if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
- wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
- (void)R_REG(&pi->regs->maccontrol);
- udelay(1);
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- mod_phy_reg(pi, 0x1e7, (0x7f << 0),
- (NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 << 0));
- } else {
- mod_phy_reg(pi, 0x1e7, (0x7f << 0),
- (NPHY_TxPwrCtrlCmd_pwrIndex_init << 0));
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- mod_phy_reg(pi, 0x222, (0xff << 0),
- (NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 << 0));
- } else if (NREV_GT(pi->pubpi.phy_rev, 1)) {
- mod_phy_reg(pi, 0x222, (0xff << 0),
- (NPHY_TxPwrCtrlCmd_pwrIndex_init << 0));
- }
-
- if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
- wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, 0);
-
- write_phy_reg(pi, 0x1e8, (0x3 << 8) | (240 << 0));
-
- write_phy_reg(pi, 0x1e9,
- (1 << 15) | (idle_tssi[0] << 0) | (idle_tssi[1] << 8));
-
- write_phy_reg(pi, 0x1ea,
- (target_pwr_qtrdbm[0] << 0) |
- (target_pwr_qtrdbm[1] << 8));
-
- tbl_len = 64;
- tbl_offset = 0;
- for (tbl_id = NPHY_TBL_ID_CORE1TXPWRCTL;
- tbl_id <= NPHY_TBL_ID_CORE2TXPWRCTL; tbl_id++) {
-
- for (idx = 0; idx < tbl_len; idx++) {
- num =
- 8 * (16 * b0[tbl_id - 26] + b1[tbl_id - 26] * idx);
- den = 32768 + a1[tbl_id - 26] * idx;
- pwr_est = max(((4 * num + den / 2) / den), -8);
- if (NREV_LT(pi->pubpi.phy_rev, 3)) {
- if (idx <=
- (uint) (31 - idle_tssi[tbl_id - 26] + 1))
- pwr_est =
- max(pwr_est,
- target_pwr_qtrdbm[tbl_id - 26] +
- 1);
- }
- regval[idx] = (u32) pwr_est;
- }
- wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32,
- regval);
- }
-
- wlc_phy_txpwr_limit_to_tbl_nphy(pi);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 84, 64, 8,
- pi->adj_pwr_tbl_nphy);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 84, 64, 8,
- pi->adj_pwr_tbl_nphy);
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-static bool wlc_phy_txpwr_ison_nphy(phy_info_t *pi)
-{
- return read_phy_reg((pi), 0x1e7) & ((0x1 << 15) |
- (0x1 << 14) | (0x1 << 13));
-}
-
-static u8 wlc_phy_txpwr_idx_cur_get_nphy(phy_info_t *pi, u8 core)
-{
- u16 tmp;
- tmp = read_phy_reg(pi, ((core == PHY_CORE_0) ? 0x1ed : 0x1ee));
-
- tmp = (tmp & (0x7f << 8)) >> 8;
- return (u8) tmp;
-}
-
-static void
-wlc_phy_txpwr_idx_cur_set_nphy(phy_info_t *pi, u8 idx0, u8 idx1)
-{
- mod_phy_reg(pi, 0x1e7, (0x7f << 0), idx0);
-
- if (NREV_GT(pi->pubpi.phy_rev, 1))
- mod_phy_reg(pi, 0x222, (0xff << 0), idx1);
-}
-
-u16 wlc_phy_txpwr_idx_get_nphy(phy_info_t *pi)
-{
- u16 tmp;
- u16 pwr_idx[2];
-
- if (wlc_phy_txpwr_ison_nphy(pi)) {
- pwr_idx[0] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_0);
- pwr_idx[1] = wlc_phy_txpwr_idx_cur_get_nphy(pi, PHY_CORE_1);
-
- tmp = (pwr_idx[0] << 8) | pwr_idx[1];
- } else {
- tmp =
- ((pi->nphy_txpwrindex[PHY_CORE_0].
- index_internal & 0xff) << 8) | (pi->
- nphy_txpwrindex
- [PHY_CORE_1].
- index_internal & 0xff);
- }
-
- return tmp;
-}
-
-void wlc_phy_txpwr_papd_cal_nphy(phy_info_t *pi)
-{
- if (PHY_IPA(pi)
- && (pi->nphy_force_papd_cal
- || (wlc_phy_txpwr_ison_nphy(pi)
- &&
- (((u32)
- ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 0) -
- pi->nphy_papd_tx_gain_at_last_cal[0]) >= 4)
- || ((u32)
- ABS(wlc_phy_txpwr_idx_cur_get_nphy(pi, 1) -
- pi->nphy_papd_tx_gain_at_last_cal[1]) >= 4))))) {
- wlc_phy_a4(pi, true);
- }
-}
-
-void wlc_phy_txpwrctrl_enable_nphy(phy_info_t *pi, u8 ctrl_type)
-{
- u16 mask = 0, val = 0, ishw = 0;
- u8 ctr;
- uint core;
- u32 tbl_offset;
- u32 tbl_len;
- u16 regval[84];
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- switch (ctrl_type) {
- case PHY_TPC_HW_OFF:
- case PHY_TPC_HW_ON:
- pi->nphy_txpwrctrl = ctrl_type;
- break;
- default:
- break;
- }
-
- if (ctrl_type == PHY_TPC_HW_OFF) {
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- if (wlc_phy_txpwr_ison_nphy(pi)) {
- for (core = 0; core < pi->pubpi.phy_corenum;
- core++)
- pi->nphy_txpwr_idx[core] =
- wlc_phy_txpwr_idx_cur_get_nphy(pi,
- (u8)
- core);
- }
-
- }
-
- tbl_len = 84;
- tbl_offset = 64;
- for (ctr = 0; ctr < tbl_len; ctr++) {
- regval[ctr] = 0;
- }
- wlc_phy_table_write_nphy(pi, 26, tbl_len, tbl_offset, 16,
- regval);
- wlc_phy_table_write_nphy(pi, 27, tbl_len, tbl_offset, 16,
- regval);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
-
- and_phy_reg(pi, 0x1e7,
- (u16) (~((0x1 << 15) |
- (0x1 << 14) | (0x1 << 13))));
- } else {
- and_phy_reg(pi, 0x1e7,
- (u16) (~((0x1 << 14) | (0x1 << 13))));
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- or_phy_reg(pi, 0x8f, (0x1 << 8));
- or_phy_reg(pi, 0xa5, (0x1 << 8));
- } else {
- or_phy_reg(pi, 0xa5, (0x1 << 14));
- }
-
- if (NREV_IS(pi->pubpi.phy_rev, 2))
- mod_phy_reg(pi, 0xdc, 0x00ff, 0x53);
- else if (NREV_LT(pi->pubpi.phy_rev, 2))
- mod_phy_reg(pi, 0xdc, 0x00ff, 0x5a);
-
- if (NREV_LT(pi->pubpi.phy_rev, 2) && IS40MHZ(pi))
- wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_IQSWAP_WAR,
- MHF1_IQSWAP_WAR, WLC_BAND_ALL);
-
- } else {
-
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE1TXPWRCTL, 84, 64,
- 8, pi->adj_pwr_tbl_nphy);
- wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_CORE2TXPWRCTL, 84, 64,
- 8, pi->adj_pwr_tbl_nphy);
-
- ishw = (ctrl_type == PHY_TPC_HW_ON) ? 0x1 : 0x0;
- mask = (0x1 << 14) | (0x1 << 13);
- val = (ishw << 14) | (ishw << 13);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- mask |= (0x1 << 15);
- val |= (ishw << 15);
- }
-
- mod_phy_reg(pi, 0x1e7, mask, val);
-
- if (CHSPEC_IS5G(pi->radio_chanspec)) {
- if (NREV_GE(pi->pubpi.phy_rev, 7)) {
- mod_phy_reg(pi, 0x1e7, (0x7f << 0), 0x32);
- mod_phy_reg(pi, 0x222, (0xff << 0), 0x32);
- } else {
- mod_phy_reg(pi, 0x1e7, (0x7f << 0), 0x64);
- if (NREV_GT(pi->pubpi.phy_rev, 1))
- mod_phy_reg(pi, 0x222,
- (0xff << 0), 0x64);
- }
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- if ((pi->nphy_txpwr_idx[0] != 128)
- && (pi->nphy_txpwr_idx[1] != 128)) {
- wlc_phy_txpwr_idx_cur_set_nphy(pi,
- pi->
- nphy_txpwr_idx
- [0],
- pi->
- nphy_txpwr_idx
- [1]);
- }
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- and_phy_reg(pi, 0x8f, ~(0x1 << 8));
- and_phy_reg(pi, 0xa5, ~(0x1 << 8));
- } else {
- and_phy_reg(pi, 0xa5, ~(0x1 << 14));
- }
-
- if (NREV_IS(pi->pubpi.phy_rev, 2))
- mod_phy_reg(pi, 0xdc, 0x00ff, 0x3b);
- else if (NREV_LT(pi->pubpi.phy_rev, 2))
- mod_phy_reg(pi, 0xdc, 0x00ff, 0x40);
-
- if (NREV_LT(pi->pubpi.phy_rev, 2) && IS40MHZ(pi))
- wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_IQSWAP_WAR,
- 0x0, WLC_BAND_ALL);
-
- if (PHY_IPA(pi)) {
- mod_phy_reg(pi, (0 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 2), (0) << 2);
-
- mod_phy_reg(pi, (1 == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 2), (0) << 2);
-
- }
-
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-void
-wlc_phy_txpwr_index_nphy(phy_info_t *pi, u8 core_mask, s8 txpwrindex,
- bool restore_cals)
-{
- u8 core, txpwrctl_tbl;
- u16 tx_ind0, iq_ind0, lo_ind0;
- u16 m1m2;
- u32 txgain;
- u16 rad_gain, dac_gain;
- u8 bbmult;
- u32 iqcomp;
- u16 iqcomp_a, iqcomp_b;
- u32 locomp;
- u16 tmpval;
- u8 tx_pwr_ctrl_state;
- s32 rfpwr_offset;
- u16 regval[2];
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
-
- tx_ind0 = 192;
- iq_ind0 = 320;
- lo_ind0 = 448;
-
- for (core = 0; core < pi->pubpi.phy_corenum; core++) {
-
- if ((core_mask & (1 << core)) == 0) {
- continue;
- }
-
- txpwrctl_tbl = (core == PHY_CORE_0) ? 26 : 27;
-
- if (txpwrindex < 0) {
- if (pi->nphy_txpwrindex[core].index < 0) {
-
- continue;
- }
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- mod_phy_reg(pi, 0x8f,
- (0x1 << 8),
- pi->nphy_txpwrindex[core].
- AfectrlOverride);
- mod_phy_reg(pi, 0xa5, (0x1 << 8),
- pi->nphy_txpwrindex[core].
- AfectrlOverride);
- } else {
- mod_phy_reg(pi, 0xa5,
- (0x1 << 14),
- pi->nphy_txpwrindex[core].
- AfectrlOverride);
- }
-
- write_phy_reg(pi, (core == PHY_CORE_0) ?
- 0xaa : 0xab,
- pi->nphy_txpwrindex[core].AfeCtrlDacGain);
-
- wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
- &pi->nphy_txpwrindex[core].
- rad_gain);
-
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
- m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
- m1m2 |= ((core == PHY_CORE_0) ?
- (pi->nphy_txpwrindex[core].bbmult << 8) :
- (pi->nphy_txpwrindex[core].bbmult << 0));
- wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
-
- if (restore_cals) {
-
- wlc_phy_table_write_nphy(pi, 15, 2,
- (80 + 2 * core), 16,
- (void *)&pi->
- nphy_txpwrindex[core].
- iqcomp_a);
-
- wlc_phy_table_write_nphy(pi, 15, 1, (85 + core),
- 16,
- &pi->
- nphy_txpwrindex[core].
- locomp);
- wlc_phy_table_write_nphy(pi, 15, 1, (93 + core),
- 16,
- (void *)&pi->
- nphy_txpwrindex[core].
- locomp);
- }
-
- wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
-
- pi->nphy_txpwrindex[core].index_internal =
- pi->nphy_txpwrindex[core].index_internal_save;
- } else {
-
- if (pi->nphy_txpwrindex[core].index < 0) {
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- mod_phy_reg(pi, 0x8f,
- (0x1 << 8),
- pi->nphy_txpwrindex[core].
- AfectrlOverride);
- mod_phy_reg(pi, 0xa5, (0x1 << 8),
- pi->nphy_txpwrindex[core].
- AfectrlOverride);
- } else {
- pi->nphy_txpwrindex[core].
- AfectrlOverride =
- read_phy_reg(pi, 0xa5);
- }
-
- pi->nphy_txpwrindex[core].AfeCtrlDacGain =
- read_phy_reg(pi,
- (core ==
- PHY_CORE_0) ? 0xaa : 0xab);
-
- wlc_phy_table_read_nphy(pi, 7, 1,
- (0x110 + core), 16,
- &pi->
- nphy_txpwrindex[core].
- rad_gain);
-
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16,
- &tmpval);
- tmpval >>= ((core == PHY_CORE_0) ? 8 : 0);
- tmpval &= 0xff;
- pi->nphy_txpwrindex[core].bbmult =
- (u8) tmpval;
-
- wlc_phy_table_read_nphy(pi, 15, 2,
- (80 + 2 * core), 16,
- (void *)&pi->
- nphy_txpwrindex[core].
- iqcomp_a);
-
- wlc_phy_table_read_nphy(pi, 15, 1, (85 + core),
- 16,
- (void *)&pi->
- nphy_txpwrindex[core].
- locomp);
-
- pi->nphy_txpwrindex[core].index_internal_save =
- pi->nphy_txpwrindex[core].index_internal;
- }
-
- tx_pwr_ctrl_state = pi->nphy_txpwrctrl;
- wlc_phy_txpwrctrl_enable_nphy(pi, PHY_TPC_HW_OFF);
-
- if (NREV_IS(pi->pubpi.phy_rev, 1))
- wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
-
- wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
- (tx_ind0 + txpwrindex), 32,
- &txgain);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- rad_gain =
- (txgain >> 16) & ((1 << (32 - 16 + 1)) - 1);
- } else {
- rad_gain =
- (txgain >> 16) & ((1 << (28 - 16 + 1)) - 1);
- }
- dac_gain = (txgain >> 8) & ((1 << (13 - 8 + 1)) - 1);
- bbmult = (txgain >> 0) & ((1 << (7 - 0 + 1)) - 1);
-
- if (NREV_GE(pi->pubpi.phy_rev, 3)) {
- mod_phy_reg(pi, ((core == PHY_CORE_0) ? 0x8f :
- 0xa5), (0x1 << 8), (0x1 << 8));
- } else {
- mod_phy_reg(pi, 0xa5, (0x1 << 14), (0x1 << 14));
- }
- write_phy_reg(pi, (core == PHY_CORE_0) ?
- 0xaa : 0xab, dac_gain);
-
- wlc_phy_table_write_nphy(pi, 7, 1, (0x110 + core), 16,
- &rad_gain);
-
- wlc_phy_table_read_nphy(pi, 15, 1, 87, 16, &m1m2);
- m1m2 &= ((core == PHY_CORE_0) ? 0x00ff : 0xff00);
- m1m2 |=
- ((core ==
- PHY_CORE_0) ? (bbmult << 8) : (bbmult << 0));
-
- wlc_phy_table_write_nphy(pi, 15, 1, 87, 16, &m1m2);
-
- wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
- (iq_ind0 + txpwrindex), 32,
- &iqcomp);
- iqcomp_a = (iqcomp >> 10) & ((1 << (19 - 10 + 1)) - 1);
- iqcomp_b = (iqcomp >> 0) & ((1 << (9 - 0 + 1)) - 1);
-
- if (restore_cals) {
- regval[0] = (u16) iqcomp_a;
- regval[1] = (u16) iqcomp_b;
- wlc_phy_table_write_nphy(pi, 15, 2,
- (80 + 2 * core), 16,
- regval);
- }
-
- wlc_phy_table_read_nphy(pi, txpwrctl_tbl, 1,
- (lo_ind0 + txpwrindex), 32,
- &locomp);
- if (restore_cals) {
- wlc_phy_table_write_nphy(pi, 15, 1, (85 + core),
- 16, &locomp);
- }
-
- if (NREV_IS(pi->pubpi.phy_rev, 1))
- wlapi_bmac_phyclk_fgc(pi->sh->physhim, OFF);
-
- if (PHY_IPA(pi)) {
- wlc_phy_table_read_nphy(pi,
- (core ==
- PHY_CORE_0 ?
- NPHY_TBL_ID_CORE1TXPWRCTL
- :
- NPHY_TBL_ID_CORE2TXPWRCTL),
- 1, 576 + txpwrindex, 32,
- &rfpwr_offset);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1ff << 4),
- ((s16) rfpwr_offset) << 4);
-
- mod_phy_reg(pi, (core == PHY_CORE_0) ? 0x297 :
- 0x29b, (0x1 << 2), (1) << 2);
-
- }
-
- wlc_phy_txpwrctrl_enable_nphy(pi, tx_pwr_ctrl_state);
- }
-
- pi->nphy_txpwrindex[core].index = txpwrindex;
- }
-
- if (pi->phyhang_avoid)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
-}
-
-void
-wlc_phy_txpower_sromlimit_get_nphy(phy_info_t *pi, uint chan, u8 *max_pwr,
- u8 txp_rate_idx)
-{
- u8 chan_freq_range;
-
- chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, chan);
- switch (chan_freq_range) {
- case WL_CHAN_FREQ_RANGE_2G:
- *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
- break;
- case WL_CHAN_FREQ_RANGE_5GM:
- *max_pwr = pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
- break;
- case WL_CHAN_FREQ_RANGE_5GL:
- *max_pwr = pi->tx_srom_max_rate_5g_low[txp_rate_idx];
- break;
- case WL_CHAN_FREQ_RANGE_5GH:
- *max_pwr = pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
- break;
- default:
- *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
- break;
- }
-
- return;
-}
-
-void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable)
-{
- u16 clip_off[] = { 0xffff, 0xffff };
-
- if (enable) {
- if (pi->nphy_deaf_count == 0) {
- pi->classifier_state =
- wlc_phy_classifier_nphy(pi, 0, 0);
- wlc_phy_classifier_nphy(pi, (0x7 << 0), 4);
- wlc_phy_clip_det_nphy(pi, 0, pi->clip_state);
- wlc_phy_clip_det_nphy(pi, 1, clip_off);
- }
-
- pi->nphy_deaf_count++;
-
- wlc_phy_resetcca_nphy(pi);
-
- } else {
- pi->nphy_deaf_count--;
-
- if (pi->nphy_deaf_count == 0) {
- wlc_phy_classifier_nphy(pi, (0x7 << 0),
- pi->classifier_state);
- wlc_phy_clip_det_nphy(pi, 1, pi->clip_state);
- }
- }
-}
-
-void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode)
-{
- wlapi_suspend_mac_and_wait(pi->sh->physhim);
-
- if (mode) {
- if (pi->nphy_deaf_count == 0)
- wlc_phy_stay_in_carriersearch_nphy(pi, true);
- } else {
- if (pi->nphy_deaf_count > 0)
- wlc_phy_stay_in_carriersearch_nphy(pi, false);
- }
- wlapi_enable_mac(pi->sh->physhim);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/types.h>
-
-#include "wlc_phy_qmath.h"
-
-/*
-Description: This function make 16 bit unsigned multiplication. To fit the output into
-16 bits the 32 bit multiplication result is right shifted by 16 bits.
-*/
-u16 qm_mulu16(u16 op1, u16 op2)
-{
- return (u16) (((u32) op1 * (u32) op2) >> 16);
-}
-
-/*
-Description: This function make 16 bit multiplication and return the result in 16 bits.
-To fit the multiplication result into 16 bits the multiplication result is right shifted by
-15 bits. Right shifting 15 bits instead of 16 bits is done to remove the extra sign bit formed
-due to the multiplication.
-When both the 16bit inputs are 0x8000 then the output is saturated to 0x7fffffff.
-*/
-s16 qm_muls16(s16 op1, s16 op2)
-{
- s32 result;
- if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000) {
- result = 0x7fffffff;
- } else {
- result = ((s32) (op1) * (s32) (op2));
- }
- return (s16) (result >> 15);
-}
-
-/*
-Description: This function add two 32 bit numbers and return the 32bit result.
-If the result overflow 32 bits, the output will be saturated to 32bits.
-*/
-s32 qm_add32(s32 op1, s32 op2)
-{
- s32 result;
- result = op1 + op2;
- if (op1 < 0 && op2 < 0 && result > 0) {
- result = 0x80000000;
- } else if (op1 > 0 && op2 > 0 && result < 0) {
- result = 0x7fffffff;
- }
- return result;
-}
-
-/*
-Description: This function add two 16 bit numbers and return the 16bit result.
-If the result overflow 16 bits, the output will be saturated to 16bits.
-*/
-s16 qm_add16(s16 op1, s16 op2)
-{
- s16 result;
- s32 temp = (s32) op1 + (s32) op2;
- if (temp > (s32) 0x7fff) {
- result = (s16) 0x7fff;
- } else if (temp < (s32) 0xffff8000) {
- result = (s16) 0xffff8000;
- } else {
- result = (s16) temp;
- }
- return result;
-}
-
-/*
-Description: This function make 16 bit subtraction and return the 16bit result.
-If the result overflow 16 bits, the output will be saturated to 16bits.
-*/
-s16 qm_sub16(s16 op1, s16 op2)
-{
- s16 result;
- s32 temp = (s32) op1 - (s32) op2;
- if (temp > (s32) 0x7fff) {
- result = (s16) 0x7fff;
- } else if (temp < (s32) 0xffff8000) {
- result = (s16) 0xffff8000;
- } else {
- result = (s16) temp;
- }
- return result;
-}
-
-/*
-Description: This function make a 32 bit saturated left shift when the specified shift
-is +ve. This function will make a 32 bit right shift when the specified shift is -ve.
-This function return the result after shifting operation.
-*/
-s32 qm_shl32(s32 op, int shift)
-{
- int i;
- s32 result;
- result = op;
- if (shift > 31)
- shift = 31;
- else if (shift < -31)
- shift = -31;
- if (shift >= 0) {
- for (i = 0; i < shift; i++) {
- result = qm_add32(result, result);
- }
- } else {
- result = result >> (-shift);
- }
- return result;
-}
-
-/*
-Description: This function make a 16 bit saturated left shift when the specified shift
-is +ve. This function will make a 16 bit right shift when the specified shift is -ve.
-This function return the result after shifting operation.
-*/
-s16 qm_shl16(s16 op, int shift)
-{
- int i;
- s16 result;
- result = op;
- if (shift > 15)
- shift = 15;
- else if (shift < -15)
- shift = -15;
- if (shift > 0) {
- for (i = 0; i < shift; i++) {
- result = qm_add16(result, result);
- }
- } else {
- result = result >> (-shift);
- }
- return result;
-}
-
-/*
-Description: This function make a 16 bit right shift when shift is +ve.
-This function make a 16 bit saturated left shift when shift is -ve. This function
-return the result of the shift operation.
-*/
-s16 qm_shr16(s16 op, int shift)
-{
- return qm_shl16(op, -shift);
-}
-
-/*
-Description: This function return the number of redundant sign bits in a 32 bit number.
-Example: qm_norm32(0x00000080) = 23
-*/
-s16 qm_norm32(s32 op)
-{
- u16 u16extraSignBits;
- if (op == 0) {
- return 31;
- } else {
- u16extraSignBits = 0;
- while ((op >> 31) == (op >> 30)) {
- u16extraSignBits++;
- op = op << 1;
- }
- }
- return u16extraSignBits;
-}
-
-/* This table is log2(1+(i/32)) where i=[0:1:31], in q.15 format */
-static const s16 log_table[] = {
- 0,
- 1455,
- 2866,
- 4236,
- 5568,
- 6863,
- 8124,
- 9352,
- 10549,
- 11716,
- 12855,
- 13968,
- 15055,
- 16117,
- 17156,
- 18173,
- 19168,
- 20143,
- 21098,
- 22034,
- 22952,
- 23852,
- 24736,
- 25604,
- 26455,
- 27292,
- 28114,
- 28922,
- 29717,
- 30498,
- 31267,
- 32024
-};
-
-#define LOG_TABLE_SIZE 32 /* log_table size */
-#define LOG2_LOG_TABLE_SIZE 5 /* log2(log_table size) */
-#define Q_LOG_TABLE 15 /* qformat of log_table */
-#define LOG10_2 19728 /* log10(2) in q.16 */
-
-/*
-Description:
-This routine takes the input number N and its q format qN and compute
-the log10(N). This routine first normalizes the input no N. Then N is in mag*(2^x) format.
-mag is any number in the range 2^30-(2^31 - 1). Then log2(mag * 2^x) = log2(mag) + x is computed.
-From that log10(mag * 2^x) = log2(mag * 2^x) * log10(2) is computed.
-This routine looks the log2 value in the table considering LOG2_LOG_TABLE_SIZE+1 MSBs.
-As the MSB is always 1, only next LOG2_OF_LOG_TABLE_SIZE MSBs are used for table lookup.
-Next 16 MSBs are used for interpolation.
-Inputs:
-N - number to which log10 has to be found.
-qN - q format of N
-log10N - address where log10(N) will be written.
-qLog10N - address where log10N qformat will be written.
-Note/Problem:
-For accurate results input should be in normalized or near normalized form.
-*/
-void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N)
-{
- s16 s16norm, s16tableIndex, s16errorApproximation;
- u16 u16offset;
- s32 s32log;
-
- /* normalize the N. */
- s16norm = qm_norm32(N);
- N = N << s16norm;
-
- /* The qformat of N after normalization.
- * -30 is added to treat the no as between 1.0 to 2.0
- * i.e. after adding the -30 to the qformat the decimal point will be
- * just rigtht of the MSB. (i.e. after sign bit and 1st MSB). i.e.
- * at the right side of 30th bit.
- */
- qN = qN + s16norm - 30;
-
- /* take the table index as the LOG2_OF_LOG_TABLE_SIZE bits right of the MSB */
- s16tableIndex = (s16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE)));
-
- /* remove the MSB. the MSB is always 1 after normalization. */
- s16tableIndex =
- s16tableIndex & (s16) ((1 << LOG2_LOG_TABLE_SIZE) - 1);
-
- /* remove the (1+LOG2_OF_LOG_TABLE_SIZE) MSBs in the N. */
- N = N & ((1 << (32 - (2 + LOG2_LOG_TABLE_SIZE))) - 1);
-
- /* take the offset as the 16 MSBS after table index.
- */
- u16offset = (u16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE + 16)));
-
- /* look the log value in the table. */
- s32log = log_table[s16tableIndex]; /* q.15 format */
-
- /* interpolate using the offset. */
- s16errorApproximation = (s16) qm_mulu16(u16offset, (u16) (log_table[s16tableIndex + 1] - log_table[s16tableIndex])); /* q.15 */
-
- s32log = qm_add16((s16) s32log, s16errorApproximation); /* q.15 format */
-
- /* adjust for the qformat of the N as
- * log2(mag * 2^x) = log2(mag) + x
- */
- s32log = qm_add32(s32log, ((s32) -qN) << 15); /* q.15 format */
-
- /* normalize the result. */
- s16norm = qm_norm32(s32log);
-
- /* bring all the important bits into lower 16 bits */
- s32log = qm_shl32(s32log, s16norm - 16); /* q.15+s16norm-16 format */
-
- /* compute the log10(N) by multiplying log2(N) with log10(2).
- * as log10(mag * 2^x) = log2(mag * 2^x) * log10(2)
- * log10N in q.15+s16norm-16+1 (LOG10_2 is in q.16)
- */
- *log10N = qm_muls16((s16) s32log, (s16) LOG10_2);
-
- /* write the q format of the result. */
- *qLog10N = 15 + s16norm - 16 + 1;
-
- return;
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_QMATH_H_
-#define _BRCM_QMATH_H_
-
-u16 qm_mulu16(u16 op1, u16 op2);
-
-s16 qm_muls16(s16 op1, s16 op2);
-
-s32 qm_add32(s32 op1, s32 op2);
-
-s16 qm_add16(s16 op1, s16 op2);
-
-s16 qm_sub16(s16 op1, s16 op2);
-
-s32 qm_shl32(s32 op, int shift);
-
-s16 qm_shl16(s16 op, int shift);
-
-s16 qm_shr16(s16 op, int shift);
-
-s16 qm_norm32(s32 op);
-
-void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N);
-
-#endif /* #ifndef _BRCM_QMATH_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_PHY_RADIO_H_
-#define _BRCM_PHY_RADIO_H_
-
-#define RADIO_IDCODE 0x01
-
-#define RADIO_DEFAULT_CORE 0
-
-#define RXC0_RSSI_RST 0x80
-#define RXC0_MODE_RSSI 0x40
-#define RXC0_MODE_OFF 0x20
-#define RXC0_MODE_CM 0x10
-#define RXC0_LAN_LOAD 0x08
-#define RXC0_OFF_ADJ_MASK 0x07
-
-#define TXC0_MODE_TXLPF 0x04
-#define TXC0_PA_TSSI_EN 0x02
-#define TXC0_TSSI_EN 0x01
-
-#define TXC1_PA_GAIN_MASK 0x60
-#define TXC1_PA_GAIN_3DB 0x40
-#define TXC1_PA_GAIN_2DB 0x20
-#define TXC1_TX_MIX_GAIN 0x10
-#define TXC1_OFF_I_MASK 0x0c
-#define TXC1_OFF_Q_MASK 0x03
-
-#define RADIO_2055_READ_OFF 0x100
-#define RADIO_2057_READ_OFF 0x200
-
-#define RADIO_2055_GEN_SPARE 0x00
-#define RADIO_2055_SP_PIN_PD 0x02
-#define RADIO_2055_SP_RSSI_CORE1 0x03
-#define RADIO_2055_SP_PD_MISC_CORE1 0x04
-#define RADIO_2055_SP_RSSI_CORE2 0x05
-#define RADIO_2055_SP_PD_MISC_CORE2 0x06
-#define RADIO_2055_SP_RX_GC1_CORE1 0x07
-#define RADIO_2055_SP_RX_GC2_CORE1 0x08
-#define RADIO_2055_SP_RX_GC1_CORE2 0x09
-#define RADIO_2055_SP_RX_GC2_CORE2 0x0a
-#define RADIO_2055_SP_LPF_BW_SELECT_CORE1 0x0b
-#define RADIO_2055_SP_LPF_BW_SELECT_CORE2 0x0c
-#define RADIO_2055_SP_TX_GC1_CORE1 0x0d
-#define RADIO_2055_SP_TX_GC2_CORE1 0x0e
-#define RADIO_2055_SP_TX_GC1_CORE2 0x0f
-#define RADIO_2055_SP_TX_GC2_CORE2 0x10
-#define RADIO_2055_MASTER_CNTRL1 0x11
-#define RADIO_2055_MASTER_CNTRL2 0x12
-#define RADIO_2055_PD_LGEN 0x13
-#define RADIO_2055_PD_PLL_TS 0x14
-#define RADIO_2055_PD_CORE1_LGBUF 0x15
-#define RADIO_2055_PD_CORE1_TX 0x16
-#define RADIO_2055_PD_CORE1_RXTX 0x17
-#define RADIO_2055_PD_CORE1_RSSI_MISC 0x18
-#define RADIO_2055_PD_CORE2_LGBUF 0x19
-#define RADIO_2055_PD_CORE2_TX 0x1a
-#define RADIO_2055_PD_CORE2_RXTX 0x1b
-#define RADIO_2055_PD_CORE2_RSSI_MISC 0x1c
-#define RADIO_2055_PWRDET_LGEN 0x1d
-#define RADIO_2055_PWRDET_LGBUF_CORE1 0x1e
-#define RADIO_2055_PWRDET_RXTX_CORE1 0x1f
-#define RADIO_2055_PWRDET_LGBUF_CORE2 0x20
-#define RADIO_2055_PWRDET_RXTX_CORE2 0x21
-#define RADIO_2055_RRCCAL_CNTRL_SPARE 0x22
-#define RADIO_2055_RRCCAL_N_OPT_SEL 0x23
-#define RADIO_2055_CAL_MISC 0x24
-#define RADIO_2055_CAL_COUNTER_OUT 0x25
-#define RADIO_2055_CAL_COUNTER_OUT2 0x26
-#define RADIO_2055_CAL_CVAR_CNTRL 0x27
-#define RADIO_2055_CAL_RVAR_CNTRL 0x28
-#define RADIO_2055_CAL_LPO_CNTRL 0x29
-#define RADIO_2055_CAL_TS 0x2a
-#define RADIO_2055_CAL_RCCAL_READ_TS 0x2b
-#define RADIO_2055_CAL_RCAL_READ_TS 0x2c
-#define RADIO_2055_PAD_DRIVER 0x2d
-#define RADIO_2055_XO_CNTRL1 0x2e
-#define RADIO_2055_XO_CNTRL2 0x2f
-#define RADIO_2055_XO_REGULATOR 0x30
-#define RADIO_2055_XO_MISC 0x31
-#define RADIO_2055_PLL_LF_C1 0x32
-#define RADIO_2055_PLL_CAL_VTH 0x33
-#define RADIO_2055_PLL_LF_C2 0x34
-#define RADIO_2055_PLL_REF 0x35
-#define RADIO_2055_PLL_LF_R1 0x36
-#define RADIO_2055_PLL_PFD_CP 0x37
-#define RADIO_2055_PLL_IDAC_CPOPAMP 0x38
-#define RADIO_2055_PLL_CP_REGULATOR 0x39
-#define RADIO_2055_PLL_RCAL 0x3a
-#define RADIO_2055_RF_PLL_MOD0 0x3b
-#define RADIO_2055_RF_PLL_MOD1 0x3c
-#define RADIO_2055_RF_MMD_IDAC1 0x3d
-#define RADIO_2055_RF_MMD_IDAC0 0x3e
-#define RADIO_2055_RF_MMD_SPARE 0x3f
-#define RADIO_2055_VCO_CAL1 0x40
-#define RADIO_2055_VCO_CAL2 0x41
-#define RADIO_2055_VCO_CAL3 0x42
-#define RADIO_2055_VCO_CAL4 0x43
-#define RADIO_2055_VCO_CAL5 0x44
-#define RADIO_2055_VCO_CAL6 0x45
-#define RADIO_2055_VCO_CAL7 0x46
-#define RADIO_2055_VCO_CAL8 0x47
-#define RADIO_2055_VCO_CAL9 0x48
-#define RADIO_2055_VCO_CAL10 0x49
-#define RADIO_2055_VCO_CAL11 0x4a
-#define RADIO_2055_VCO_CAL12 0x4b
-#define RADIO_2055_VCO_CAL13 0x4c
-#define RADIO_2055_VCO_CAL14 0x4d
-#define RADIO_2055_VCO_CAL15 0x4e
-#define RADIO_2055_VCO_CAL16 0x4f
-#define RADIO_2055_VCO_KVCO 0x50
-#define RADIO_2055_VCO_CAP_TAIL 0x51
-#define RADIO_2055_VCO_IDAC_VCO 0x52
-#define RADIO_2055_VCO_REGULATOR 0x53
-#define RADIO_2055_PLL_RF_VTH 0x54
-#define RADIO_2055_LGBUF_CEN_BUF 0x55
-#define RADIO_2055_LGEN_TUNE1 0x56
-#define RADIO_2055_LGEN_TUNE2 0x57
-#define RADIO_2055_LGEN_IDAC1 0x58
-#define RADIO_2055_LGEN_IDAC2 0x59
-#define RADIO_2055_LGEN_BIAS_CNT 0x5a
-#define RADIO_2055_LGEN_BIAS_IDAC 0x5b
-#define RADIO_2055_LGEN_RCAL 0x5c
-#define RADIO_2055_LGEN_DIV 0x5d
-#define RADIO_2055_LGEN_SPARE2 0x5e
-#define RADIO_2055_CORE1_LGBUF_A_TUNE 0x5f
-#define RADIO_2055_CORE1_LGBUF_G_TUNE 0x60
-#define RADIO_2055_CORE1_LGBUF_DIV 0x61
-#define RADIO_2055_CORE1_LGBUF_A_IDAC 0x62
-#define RADIO_2055_CORE1_LGBUF_G_IDAC 0x63
-#define RADIO_2055_CORE1_LGBUF_IDACFIL_OVR 0x64
-#define RADIO_2055_CORE1_LGBUF_SPARE 0x65
-#define RADIO_2055_CORE1_RXRF_SPC1 0x66
-#define RADIO_2055_CORE1_RXRF_REG1 0x67
-#define RADIO_2055_CORE1_RXRF_REG2 0x68
-#define RADIO_2055_CORE1_RXRF_RCAL 0x69
-#define RADIO_2055_CORE1_RXBB_BUFI_LPFCMP 0x6a
-#define RADIO_2055_CORE1_RXBB_LPF 0x6b
-#define RADIO_2055_CORE1_RXBB_MIDAC_HIPAS 0x6c
-#define RADIO_2055_CORE1_RXBB_VGA1_IDAC 0x6d
-#define RADIO_2055_CORE1_RXBB_VGA2_IDAC 0x6e
-#define RADIO_2055_CORE1_RXBB_VGA3_IDAC 0x6f
-#define RADIO_2055_CORE1_RXBB_BUFO_CTRL 0x70
-#define RADIO_2055_CORE1_RXBB_RCCAL_CTRL 0x71
-#define RADIO_2055_CORE1_RXBB_RSSI_CTRL1 0x72
-#define RADIO_2055_CORE1_RXBB_RSSI_CTRL2 0x73
-#define RADIO_2055_CORE1_RXBB_RSSI_CTRL3 0x74
-#define RADIO_2055_CORE1_RXBB_RSSI_CTRL4 0x75
-#define RADIO_2055_CORE1_RXBB_RSSI_CTRL5 0x76
-#define RADIO_2055_CORE1_RXBB_REGULATOR 0x77
-#define RADIO_2055_CORE1_RXBB_SPARE1 0x78
-#define RADIO_2055_CORE1_RXTXBB_RCAL 0x79
-#define RADIO_2055_CORE1_TXRF_SGM_PGA 0x7a
-#define RADIO_2055_CORE1_TXRF_SGM_PAD 0x7b
-#define RADIO_2055_CORE1_TXRF_CNTR_PGA1 0x7c
-#define RADIO_2055_CORE1_TXRF_CNTR_PAD1 0x7d
-#define RADIO_2055_CORE1_TX_RFPGA_IDAC 0x7e
-#define RADIO_2055_CORE1_TX_PGA_PAD_TN 0x7f
-#define RADIO_2055_CORE1_TX_PAD_IDAC1 0x80
-#define RADIO_2055_CORE1_TX_PAD_IDAC2 0x81
-#define RADIO_2055_CORE1_TX_MX_BGTRIM 0x82
-#define RADIO_2055_CORE1_TXRF_RCAL 0x83
-#define RADIO_2055_CORE1_TXRF_PAD_TSSI1 0x84
-#define RADIO_2055_CORE1_TXRF_PAD_TSSI2 0x85
-#define RADIO_2055_CORE1_TX_RF_SPARE 0x86
-#define RADIO_2055_CORE1_TXRF_IQCAL1 0x87
-#define RADIO_2055_CORE1_TXRF_IQCAL2 0x88
-#define RADIO_2055_CORE1_TXBB_RCCAL_CTRL 0x89
-#define RADIO_2055_CORE1_TXBB_LPF1 0x8a
-#define RADIO_2055_CORE1_TX_VOS_CNCL 0x8b
-#define RADIO_2055_CORE1_TX_LPF_MXGM_IDAC 0x8c
-#define RADIO_2055_CORE1_TX_BB_MXGM 0x8d
-#define RADIO_2055_CORE2_LGBUF_A_TUNE 0x8e
-#define RADIO_2055_CORE2_LGBUF_G_TUNE 0x8f
-#define RADIO_2055_CORE2_LGBUF_DIV 0x90
-#define RADIO_2055_CORE2_LGBUF_A_IDAC 0x91
-#define RADIO_2055_CORE2_LGBUF_G_IDAC 0x92
-#define RADIO_2055_CORE2_LGBUF_IDACFIL_OVR 0x93
-#define RADIO_2055_CORE2_LGBUF_SPARE 0x94
-#define RADIO_2055_CORE2_RXRF_SPC1 0x95
-#define RADIO_2055_CORE2_RXRF_REG1 0x96
-#define RADIO_2055_CORE2_RXRF_REG2 0x97
-#define RADIO_2055_CORE2_RXRF_RCAL 0x98
-#define RADIO_2055_CORE2_RXBB_BUFI_LPFCMP 0x99
-#define RADIO_2055_CORE2_RXBB_LPF 0x9a
-#define RADIO_2055_CORE2_RXBB_MIDAC_HIPAS 0x9b
-#define RADIO_2055_CORE2_RXBB_VGA1_IDAC 0x9c
-#define RADIO_2055_CORE2_RXBB_VGA2_IDAC 0x9d
-#define RADIO_2055_CORE2_RXBB_VGA3_IDAC 0x9e
-#define RADIO_2055_CORE2_RXBB_BUFO_CTRL 0x9f
-#define RADIO_2055_CORE2_RXBB_RCCAL_CTRL 0xa0
-#define RADIO_2055_CORE2_RXBB_RSSI_CTRL1 0xa1
-#define RADIO_2055_CORE2_RXBB_RSSI_CTRL2 0xa2
-#define RADIO_2055_CORE2_RXBB_RSSI_CTRL3 0xa3
-#define RADIO_2055_CORE2_RXBB_RSSI_CTRL4 0xa4
-#define RADIO_2055_CORE2_RXBB_RSSI_CTRL5 0xa5
-#define RADIO_2055_CORE2_RXBB_REGULATOR 0xa6
-#define RADIO_2055_CORE2_RXBB_SPARE1 0xa7
-#define RADIO_2055_CORE2_RXTXBB_RCAL 0xa8
-#define RADIO_2055_CORE2_TXRF_SGM_PGA 0xa9
-#define RADIO_2055_CORE2_TXRF_SGM_PAD 0xaa
-#define RADIO_2055_CORE2_TXRF_CNTR_PGA1 0xab
-#define RADIO_2055_CORE2_TXRF_CNTR_PAD1 0xac
-#define RADIO_2055_CORE2_TX_RFPGA_IDAC 0xad
-#define RADIO_2055_CORE2_TX_PGA_PAD_TN 0xae
-#define RADIO_2055_CORE2_TX_PAD_IDAC1 0xaf
-#define RADIO_2055_CORE2_TX_PAD_IDAC2 0xb0
-#define RADIO_2055_CORE2_TX_MX_BGTRIM 0xb1
-#define RADIO_2055_CORE2_TXRF_RCAL 0xb2
-#define RADIO_2055_CORE2_TXRF_PAD_TSSI1 0xb3
-#define RADIO_2055_CORE2_TXRF_PAD_TSSI2 0xb4
-#define RADIO_2055_CORE2_TX_RF_SPARE 0xb5
-#define RADIO_2055_CORE2_TXRF_IQCAL1 0xb6
-#define RADIO_2055_CORE2_TXRF_IQCAL2 0xb7
-#define RADIO_2055_CORE2_TXBB_RCCAL_CTRL 0xb8
-#define RADIO_2055_CORE2_TXBB_LPF1 0xb9
-#define RADIO_2055_CORE2_TX_VOS_CNCL 0xba
-#define RADIO_2055_CORE2_TX_LPF_MXGM_IDAC 0xbb
-#define RADIO_2055_CORE2_TX_BB_MXGM 0xbc
-#define RADIO_2055_PRG_GC_HPVGA23_21 0xbd
-#define RADIO_2055_PRG_GC_HPVGA23_22 0xbe
-#define RADIO_2055_PRG_GC_HPVGA23_23 0xbf
-#define RADIO_2055_PRG_GC_HPVGA23_24 0xc0
-#define RADIO_2055_PRG_GC_HPVGA23_25 0xc1
-#define RADIO_2055_PRG_GC_HPVGA23_26 0xc2
-#define RADIO_2055_PRG_GC_HPVGA23_27 0xc3
-#define RADIO_2055_PRG_GC_HPVGA23_28 0xc4
-#define RADIO_2055_PRG_GC_HPVGA23_29 0xc5
-#define RADIO_2055_PRG_GC_HPVGA23_30 0xc6
-#define RADIO_2055_CORE1_LNA_GAINBST 0xcd
-#define RADIO_2055_CORE1_B0_NBRSSI_VCM 0xd2
-#define RADIO_2055_CORE1_GEN_SPARE2 0xd6
-#define RADIO_2055_CORE2_LNA_GAINBST 0xd9
-#define RADIO_2055_CORE2_B0_NBRSSI_VCM 0xde
-#define RADIO_2055_CORE2_GEN_SPARE2 0xe2
-
-#define RADIO_2055_GAINBST_GAIN_DB 6
-#define RADIO_2055_GAINBST_CODE 0x6
-
-#define RADIO_2055_JTAGCTRL_MASK 0x04
-#define RADIO_2055_JTAGSYNC_MASK 0x08
-#define RADIO_2055_RRCAL_START 0x40
-#define RADIO_2055_RRCAL_RST_N 0x01
-#define RADIO_2055_CAL_LPO_ENABLE 0x80
-#define RADIO_2055_RCAL_DONE 0x80
-#define RADIO_2055_NBRSSI_VCM_I_MASK 0x03
-#define RADIO_2055_NBRSSI_VCM_I_SHIFT 0x00
-#define RADIO_2055_NBRSSI_VCM_Q_MASK 0x03
-#define RADIO_2055_NBRSSI_VCM_Q_SHIFT 0x00
-#define RADIO_2055_WBRSSI_VCM_IQ_MASK 0x0c
-#define RADIO_2055_WBRSSI_VCM_IQ_SHIFT 0x02
-#define RADIO_2055_NBRSSI_PD 0x01
-#define RADIO_2055_WBRSSI_G1_PD 0x04
-#define RADIO_2055_WBRSSI_G2_PD 0x02
-#define RADIO_2055_NBRSSI_SEL 0x01
-#define RADIO_2055_WBRSSI_G1_SEL 0x04
-#define RADIO_2055_WBRSSI_G2_SEL 0x02
-#define RADIO_2055_COUPLE_RX_MASK 0x01
-#define RADIO_2055_COUPLE_TX_MASK 0x02
-#define RADIO_2055_GAINBST_DISABLE 0x02
-#define RADIO_2055_GAINBST_VAL_MASK 0x07
-#define RADIO_2055_RXMX_GC_MASK 0x0c
-
-#define RADIO_MIMO_CORESEL_OFF 0x0
-#define RADIO_MIMO_CORESEL_CORE1 0x1
-#define RADIO_MIMO_CORESEL_CORE2 0x2
-#define RADIO_MIMO_CORESEL_CORE3 0x3
-#define RADIO_MIMO_CORESEL_CORE4 0x4
-#define RADIO_MIMO_CORESEL_ALLRX 0x5
-#define RADIO_MIMO_CORESEL_ALLTX 0x6
-#define RADIO_MIMO_CORESEL_ALLRXTX 0x7
-
-#define RADIO_2064_READ_OFF 0x200
-
-#define RADIO_2064_REG000 0x0
-#define RADIO_2064_REG001 0x1
-#define RADIO_2064_REG002 0x2
-#define RADIO_2064_REG003 0x3
-#define RADIO_2064_REG004 0x4
-#define RADIO_2064_REG005 0x5
-#define RADIO_2064_REG006 0x6
-#define RADIO_2064_REG007 0x7
-#define RADIO_2064_REG008 0x8
-#define RADIO_2064_REG009 0x9
-#define RADIO_2064_REG00A 0xa
-#define RADIO_2064_REG00B 0xb
-#define RADIO_2064_REG00C 0xc
-#define RADIO_2064_REG00D 0xd
-#define RADIO_2064_REG00E 0xe
-#define RADIO_2064_REG00F 0xf
-#define RADIO_2064_REG010 0x10
-#define RADIO_2064_REG011 0x11
-#define RADIO_2064_REG012 0x12
-#define RADIO_2064_REG013 0x13
-#define RADIO_2064_REG014 0x14
-#define RADIO_2064_REG015 0x15
-#define RADIO_2064_REG016 0x16
-#define RADIO_2064_REG017 0x17
-#define RADIO_2064_REG018 0x18
-#define RADIO_2064_REG019 0x19
-#define RADIO_2064_REG01A 0x1a
-#define RADIO_2064_REG01B 0x1b
-#define RADIO_2064_REG01C 0x1c
-#define RADIO_2064_REG01D 0x1d
-#define RADIO_2064_REG01E 0x1e
-#define RADIO_2064_REG01F 0x1f
-#define RADIO_2064_REG020 0x20
-#define RADIO_2064_REG021 0x21
-#define RADIO_2064_REG022 0x22
-#define RADIO_2064_REG023 0x23
-#define RADIO_2064_REG024 0x24
-#define RADIO_2064_REG025 0x25
-#define RADIO_2064_REG026 0x26
-#define RADIO_2064_REG027 0x27
-#define RADIO_2064_REG028 0x28
-#define RADIO_2064_REG029 0x29
-#define RADIO_2064_REG02A 0x2a
-#define RADIO_2064_REG02B 0x2b
-#define RADIO_2064_REG02C 0x2c
-#define RADIO_2064_REG02D 0x2d
-#define RADIO_2064_REG02E 0x2e
-#define RADIO_2064_REG02F 0x2f
-#define RADIO_2064_REG030 0x30
-#define RADIO_2064_REG031 0x31
-#define RADIO_2064_REG032 0x32
-#define RADIO_2064_REG033 0x33
-#define RADIO_2064_REG034 0x34
-#define RADIO_2064_REG035 0x35
-#define RADIO_2064_REG036 0x36
-#define RADIO_2064_REG037 0x37
-#define RADIO_2064_REG038 0x38
-#define RADIO_2064_REG039 0x39
-#define RADIO_2064_REG03A 0x3a
-#define RADIO_2064_REG03B 0x3b
-#define RADIO_2064_REG03C 0x3c
-#define RADIO_2064_REG03D 0x3d
-#define RADIO_2064_REG03E 0x3e
-#define RADIO_2064_REG03F 0x3f
-#define RADIO_2064_REG040 0x40
-#define RADIO_2064_REG041 0x41
-#define RADIO_2064_REG042 0x42
-#define RADIO_2064_REG043 0x43
-#define RADIO_2064_REG044 0x44
-#define RADIO_2064_REG045 0x45
-#define RADIO_2064_REG046 0x46
-#define RADIO_2064_REG047 0x47
-#define RADIO_2064_REG048 0x48
-#define RADIO_2064_REG049 0x49
-#define RADIO_2064_REG04A 0x4a
-#define RADIO_2064_REG04B 0x4b
-#define RADIO_2064_REG04C 0x4c
-#define RADIO_2064_REG04D 0x4d
-#define RADIO_2064_REG04E 0x4e
-#define RADIO_2064_REG04F 0x4f
-#define RADIO_2064_REG050 0x50
-#define RADIO_2064_REG051 0x51
-#define RADIO_2064_REG052 0x52
-#define RADIO_2064_REG053 0x53
-#define RADIO_2064_REG054 0x54
-#define RADIO_2064_REG055 0x55
-#define RADIO_2064_REG056 0x56
-#define RADIO_2064_REG057 0x57
-#define RADIO_2064_REG058 0x58
-#define RADIO_2064_REG059 0x59
-#define RADIO_2064_REG05A 0x5a
-#define RADIO_2064_REG05B 0x5b
-#define RADIO_2064_REG05C 0x5c
-#define RADIO_2064_REG05D 0x5d
-#define RADIO_2064_REG05E 0x5e
-#define RADIO_2064_REG05F 0x5f
-#define RADIO_2064_REG060 0x60
-#define RADIO_2064_REG061 0x61
-#define RADIO_2064_REG062 0x62
-#define RADIO_2064_REG063 0x63
-#define RADIO_2064_REG064 0x64
-#define RADIO_2064_REG065 0x65
-#define RADIO_2064_REG066 0x66
-#define RADIO_2064_REG067 0x67
-#define RADIO_2064_REG068 0x68
-#define RADIO_2064_REG069 0x69
-#define RADIO_2064_REG06A 0x6a
-#define RADIO_2064_REG06B 0x6b
-#define RADIO_2064_REG06C 0x6c
-#define RADIO_2064_REG06D 0x6d
-#define RADIO_2064_REG06E 0x6e
-#define RADIO_2064_REG06F 0x6f
-#define RADIO_2064_REG070 0x70
-#define RADIO_2064_REG071 0x71
-#define RADIO_2064_REG072 0x72
-#define RADIO_2064_REG073 0x73
-#define RADIO_2064_REG074 0x74
-#define RADIO_2064_REG075 0x75
-#define RADIO_2064_REG076 0x76
-#define RADIO_2064_REG077 0x77
-#define RADIO_2064_REG078 0x78
-#define RADIO_2064_REG079 0x79
-#define RADIO_2064_REG07A 0x7a
-#define RADIO_2064_REG07B 0x7b
-#define RADIO_2064_REG07C 0x7c
-#define RADIO_2064_REG07D 0x7d
-#define RADIO_2064_REG07E 0x7e
-#define RADIO_2064_REG07F 0x7f
-#define RADIO_2064_REG080 0x80
-#define RADIO_2064_REG081 0x81
-#define RADIO_2064_REG082 0x82
-#define RADIO_2064_REG083 0x83
-#define RADIO_2064_REG084 0x84
-#define RADIO_2064_REG085 0x85
-#define RADIO_2064_REG086 0x86
-#define RADIO_2064_REG087 0x87
-#define RADIO_2064_REG088 0x88
-#define RADIO_2064_REG089 0x89
-#define RADIO_2064_REG08A 0x8a
-#define RADIO_2064_REG08B 0x8b
-#define RADIO_2064_REG08C 0x8c
-#define RADIO_2064_REG08D 0x8d
-#define RADIO_2064_REG08E 0x8e
-#define RADIO_2064_REG08F 0x8f
-#define RADIO_2064_REG090 0x90
-#define RADIO_2064_REG091 0x91
-#define RADIO_2064_REG092 0x92
-#define RADIO_2064_REG093 0x93
-#define RADIO_2064_REG094 0x94
-#define RADIO_2064_REG095 0x95
-#define RADIO_2064_REG096 0x96
-#define RADIO_2064_REG097 0x97
-#define RADIO_2064_REG098 0x98
-#define RADIO_2064_REG099 0x99
-#define RADIO_2064_REG09A 0x9a
-#define RADIO_2064_REG09B 0x9b
-#define RADIO_2064_REG09C 0x9c
-#define RADIO_2064_REG09D 0x9d
-#define RADIO_2064_REG09E 0x9e
-#define RADIO_2064_REG09F 0x9f
-#define RADIO_2064_REG0A0 0xa0
-#define RADIO_2064_REG0A1 0xa1
-#define RADIO_2064_REG0A2 0xa2
-#define RADIO_2064_REG0A3 0xa3
-#define RADIO_2064_REG0A4 0xa4
-#define RADIO_2064_REG0A5 0xa5
-#define RADIO_2064_REG0A6 0xa6
-#define RADIO_2064_REG0A7 0xa7
-#define RADIO_2064_REG0A8 0xa8
-#define RADIO_2064_REG0A9 0xa9
-#define RADIO_2064_REG0AA 0xaa
-#define RADIO_2064_REG0AB 0xab
-#define RADIO_2064_REG0AC 0xac
-#define RADIO_2064_REG0AD 0xad
-#define RADIO_2064_REG0AE 0xae
-#define RADIO_2064_REG0AF 0xaf
-#define RADIO_2064_REG0B0 0xb0
-#define RADIO_2064_REG0B1 0xb1
-#define RADIO_2064_REG0B2 0xb2
-#define RADIO_2064_REG0B3 0xb3
-#define RADIO_2064_REG0B4 0xb4
-#define RADIO_2064_REG0B5 0xb5
-#define RADIO_2064_REG0B6 0xb6
-#define RADIO_2064_REG0B7 0xb7
-#define RADIO_2064_REG0B8 0xb8
-#define RADIO_2064_REG0B9 0xb9
-#define RADIO_2064_REG0BA 0xba
-#define RADIO_2064_REG0BB 0xbb
-#define RADIO_2064_REG0BC 0xbc
-#define RADIO_2064_REG0BD 0xbd
-#define RADIO_2064_REG0BE 0xbe
-#define RADIO_2064_REG0BF 0xbf
-#define RADIO_2064_REG0C0 0xc0
-#define RADIO_2064_REG0C1 0xc1
-#define RADIO_2064_REG0C2 0xc2
-#define RADIO_2064_REG0C3 0xc3
-#define RADIO_2064_REG0C4 0xc4
-#define RADIO_2064_REG0C5 0xc5
-#define RADIO_2064_REG0C6 0xc6
-#define RADIO_2064_REG0C7 0xc7
-#define RADIO_2064_REG0C8 0xc8
-#define RADIO_2064_REG0C9 0xc9
-#define RADIO_2064_REG0CA 0xca
-#define RADIO_2064_REG0CB 0xcb
-#define RADIO_2064_REG0CC 0xcc
-#define RADIO_2064_REG0CD 0xcd
-#define RADIO_2064_REG0CE 0xce
-#define RADIO_2064_REG0CF 0xcf
-#define RADIO_2064_REG0D0 0xd0
-#define RADIO_2064_REG0D1 0xd1
-#define RADIO_2064_REG0D2 0xd2
-#define RADIO_2064_REG0D3 0xd3
-#define RADIO_2064_REG0D4 0xd4
-#define RADIO_2064_REG0D5 0xd5
-#define RADIO_2064_REG0D6 0xd6
-#define RADIO_2064_REG0D7 0xd7
-#define RADIO_2064_REG0D8 0xd8
-#define RADIO_2064_REG0D9 0xd9
-#define RADIO_2064_REG0DA 0xda
-#define RADIO_2064_REG0DB 0xdb
-#define RADIO_2064_REG0DC 0xdc
-#define RADIO_2064_REG0DD 0xdd
-#define RADIO_2064_REG0DE 0xde
-#define RADIO_2064_REG0DF 0xdf
-#define RADIO_2064_REG0E0 0xe0
-#define RADIO_2064_REG0E1 0xe1
-#define RADIO_2064_REG0E2 0xe2
-#define RADIO_2064_REG0E3 0xe3
-#define RADIO_2064_REG0E4 0xe4
-#define RADIO_2064_REG0E5 0xe5
-#define RADIO_2064_REG0E6 0xe6
-#define RADIO_2064_REG0E7 0xe7
-#define RADIO_2064_REG0E8 0xe8
-#define RADIO_2064_REG0E9 0xe9
-#define RADIO_2064_REG0EA 0xea
-#define RADIO_2064_REG0EB 0xeb
-#define RADIO_2064_REG0EC 0xec
-#define RADIO_2064_REG0ED 0xed
-#define RADIO_2064_REG0EE 0xee
-#define RADIO_2064_REG0EF 0xef
-#define RADIO_2064_REG0F0 0xf0
-#define RADIO_2064_REG0F1 0xf1
-#define RADIO_2064_REG0F2 0xf2
-#define RADIO_2064_REG0F3 0xf3
-#define RADIO_2064_REG0F4 0xf4
-#define RADIO_2064_REG0F5 0xf5
-#define RADIO_2064_REG0F6 0xf6
-#define RADIO_2064_REG0F7 0xf7
-#define RADIO_2064_REG0F8 0xf8
-#define RADIO_2064_REG0F9 0xf9
-#define RADIO_2064_REG0FA 0xfa
-#define RADIO_2064_REG0FB 0xfb
-#define RADIO_2064_REG0FC 0xfc
-#define RADIO_2064_REG0FD 0xfd
-#define RADIO_2064_REG0FE 0xfe
-#define RADIO_2064_REG0FF 0xff
-#define RADIO_2064_REG100 0x100
-#define RADIO_2064_REG101 0x101
-#define RADIO_2064_REG102 0x102
-#define RADIO_2064_REG103 0x103
-#define RADIO_2064_REG104 0x104
-#define RADIO_2064_REG105 0x105
-#define RADIO_2064_REG106 0x106
-#define RADIO_2064_REG107 0x107
-#define RADIO_2064_REG108 0x108
-#define RADIO_2064_REG109 0x109
-#define RADIO_2064_REG10A 0x10a
-#define RADIO_2064_REG10B 0x10b
-#define RADIO_2064_REG10C 0x10c
-#define RADIO_2064_REG10D 0x10d
-#define RADIO_2064_REG10E 0x10e
-#define RADIO_2064_REG10F 0x10f
-#define RADIO_2064_REG110 0x110
-#define RADIO_2064_REG111 0x111
-#define RADIO_2064_REG112 0x112
-#define RADIO_2064_REG113 0x113
-#define RADIO_2064_REG114 0x114
-#define RADIO_2064_REG115 0x115
-#define RADIO_2064_REG116 0x116
-#define RADIO_2064_REG117 0x117
-#define RADIO_2064_REG118 0x118
-#define RADIO_2064_REG119 0x119
-#define RADIO_2064_REG11A 0x11a
-#define RADIO_2064_REG11B 0x11b
-#define RADIO_2064_REG11C 0x11c
-#define RADIO_2064_REG11D 0x11d
-#define RADIO_2064_REG11E 0x11e
-#define RADIO_2064_REG11F 0x11f
-#define RADIO_2064_REG120 0x120
-#define RADIO_2064_REG121 0x121
-#define RADIO_2064_REG122 0x122
-#define RADIO_2064_REG123 0x123
-#define RADIO_2064_REG124 0x124
-#define RADIO_2064_REG125 0x125
-#define RADIO_2064_REG126 0x126
-#define RADIO_2064_REG127 0x127
-#define RADIO_2064_REG128 0x128
-#define RADIO_2064_REG129 0x129
-#define RADIO_2064_REG12A 0x12a
-#define RADIO_2064_REG12B 0x12b
-#define RADIO_2064_REG12C 0x12c
-#define RADIO_2064_REG12D 0x12d
-#define RADIO_2064_REG12E 0x12e
-#define RADIO_2064_REG12F 0x12f
-#define RADIO_2064_REG130 0x130
-
-#define RADIO_2056_SYN (0x0 << 12)
-#define RADIO_2056_TX0 (0x2 << 12)
-#define RADIO_2056_TX1 (0x3 << 12)
-#define RADIO_2056_RX0 (0x6 << 12)
-#define RADIO_2056_RX1 (0x7 << 12)
-#define RADIO_2056_ALLTX (0xe << 12)
-#define RADIO_2056_ALLRX (0xf << 12)
-
-#define RADIO_2056_SYN_RESERVED_ADDR0 0x0
-#define RADIO_2056_SYN_IDCODE 0x1
-#define RADIO_2056_SYN_RESERVED_ADDR2 0x2
-#define RADIO_2056_SYN_RESERVED_ADDR3 0x3
-#define RADIO_2056_SYN_RESERVED_ADDR4 0x4
-#define RADIO_2056_SYN_RESERVED_ADDR5 0x5
-#define RADIO_2056_SYN_RESERVED_ADDR6 0x6
-#define RADIO_2056_SYN_RESERVED_ADDR7 0x7
-#define RADIO_2056_SYN_COM_CTRL 0x8
-#define RADIO_2056_SYN_COM_PU 0x9
-#define RADIO_2056_SYN_COM_OVR 0xa
-#define RADIO_2056_SYN_COM_RESET 0xb
-#define RADIO_2056_SYN_COM_RCAL 0xc
-#define RADIO_2056_SYN_COM_RC_RXLPF 0xd
-#define RADIO_2056_SYN_COM_RC_TXLPF 0xe
-#define RADIO_2056_SYN_COM_RC_RXHPF 0xf
-#define RADIO_2056_SYN_RESERVED_ADDR16 0x10
-#define RADIO_2056_SYN_RESERVED_ADDR17 0x11
-#define RADIO_2056_SYN_RESERVED_ADDR18 0x12
-#define RADIO_2056_SYN_RESERVED_ADDR19 0x13
-#define RADIO_2056_SYN_RESERVED_ADDR20 0x14
-#define RADIO_2056_SYN_RESERVED_ADDR21 0x15
-#define RADIO_2056_SYN_RESERVED_ADDR22 0x16
-#define RADIO_2056_SYN_RESERVED_ADDR23 0x17
-#define RADIO_2056_SYN_RESERVED_ADDR24 0x18
-#define RADIO_2056_SYN_RESERVED_ADDR25 0x19
-#define RADIO_2056_SYN_RESERVED_ADDR26 0x1a
-#define RADIO_2056_SYN_RESERVED_ADDR27 0x1b
-#define RADIO_2056_SYN_RESERVED_ADDR28 0x1c
-#define RADIO_2056_SYN_RESERVED_ADDR29 0x1d
-#define RADIO_2056_SYN_RESERVED_ADDR30 0x1e
-#define RADIO_2056_SYN_RESERVED_ADDR31 0x1f
-#define RADIO_2056_SYN_GPIO_MASTER1 0x20
-#define RADIO_2056_SYN_GPIO_MASTER2 0x21
-#define RADIO_2056_SYN_TOPBIAS_MASTER 0x22
-#define RADIO_2056_SYN_TOPBIAS_RCAL 0x23
-#define RADIO_2056_SYN_AFEREG 0x24
-#define RADIO_2056_SYN_TEMPPROCSENSE 0x25
-#define RADIO_2056_SYN_TEMPPROCSENSEIDAC 0x26
-#define RADIO_2056_SYN_TEMPPROCSENSERCAL 0x27
-#define RADIO_2056_SYN_LPO 0x28
-#define RADIO_2056_SYN_VDDCAL_MASTER 0x29
-#define RADIO_2056_SYN_VDDCAL_IDAC 0x2a
-#define RADIO_2056_SYN_VDDCAL_STATUS 0x2b
-#define RADIO_2056_SYN_RCAL_MASTER 0x2c
-#define RADIO_2056_SYN_RCAL_CODE_OUT 0x2d
-#define RADIO_2056_SYN_RCCAL_CTRL0 0x2e
-#define RADIO_2056_SYN_RCCAL_CTRL1 0x2f
-#define RADIO_2056_SYN_RCCAL_CTRL2 0x30
-#define RADIO_2056_SYN_RCCAL_CTRL3 0x31
-#define RADIO_2056_SYN_RCCAL_CTRL4 0x32
-#define RADIO_2056_SYN_RCCAL_CTRL5 0x33
-#define RADIO_2056_SYN_RCCAL_CTRL6 0x34
-#define RADIO_2056_SYN_RCCAL_CTRL7 0x35
-#define RADIO_2056_SYN_RCCAL_CTRL8 0x36
-#define RADIO_2056_SYN_RCCAL_CTRL9 0x37
-#define RADIO_2056_SYN_RCCAL_CTRL10 0x38
-#define RADIO_2056_SYN_RCCAL_CTRL11 0x39
-#define RADIO_2056_SYN_ZCAL_SPARE1 0x3a
-#define RADIO_2056_SYN_ZCAL_SPARE2 0x3b
-#define RADIO_2056_SYN_PLL_MAST1 0x3c
-#define RADIO_2056_SYN_PLL_MAST2 0x3d
-#define RADIO_2056_SYN_PLL_MAST3 0x3e
-#define RADIO_2056_SYN_PLL_BIAS_RESET 0x3f
-#define RADIO_2056_SYN_PLL_XTAL0 0x40
-#define RADIO_2056_SYN_PLL_XTAL1 0x41
-#define RADIO_2056_SYN_PLL_XTAL3 0x42
-#define RADIO_2056_SYN_PLL_XTAL4 0x43
-#define RADIO_2056_SYN_PLL_XTAL5 0x44
-#define RADIO_2056_SYN_PLL_XTAL6 0x45
-#define RADIO_2056_SYN_PLL_REFDIV 0x46
-#define RADIO_2056_SYN_PLL_PFD 0x47
-#define RADIO_2056_SYN_PLL_CP1 0x48
-#define RADIO_2056_SYN_PLL_CP2 0x49
-#define RADIO_2056_SYN_PLL_CP3 0x4a
-#define RADIO_2056_SYN_PLL_LOOPFILTER1 0x4b
-#define RADIO_2056_SYN_PLL_LOOPFILTER2 0x4c
-#define RADIO_2056_SYN_PLL_LOOPFILTER3 0x4d
-#define RADIO_2056_SYN_PLL_LOOPFILTER4 0x4e
-#define RADIO_2056_SYN_PLL_LOOPFILTER5 0x4f
-#define RADIO_2056_SYN_PLL_MMD1 0x50
-#define RADIO_2056_SYN_PLL_MMD2 0x51
-#define RADIO_2056_SYN_PLL_VCO1 0x52
-#define RADIO_2056_SYN_PLL_VCO2 0x53
-#define RADIO_2056_SYN_PLL_MONITOR1 0x54
-#define RADIO_2056_SYN_PLL_MONITOR2 0x55
-#define RADIO_2056_SYN_PLL_VCOCAL1 0x56
-#define RADIO_2056_SYN_PLL_VCOCAL2 0x57
-#define RADIO_2056_SYN_PLL_VCOCAL4 0x58
-#define RADIO_2056_SYN_PLL_VCOCAL5 0x59
-#define RADIO_2056_SYN_PLL_VCOCAL6 0x5a
-#define RADIO_2056_SYN_PLL_VCOCAL7 0x5b
-#define RADIO_2056_SYN_PLL_VCOCAL8 0x5c
-#define RADIO_2056_SYN_PLL_VCOCAL9 0x5d
-#define RADIO_2056_SYN_PLL_VCOCAL10 0x5e
-#define RADIO_2056_SYN_PLL_VCOCAL11 0x5f
-#define RADIO_2056_SYN_PLL_VCOCAL12 0x60
-#define RADIO_2056_SYN_PLL_VCOCAL13 0x61
-#define RADIO_2056_SYN_PLL_VREG 0x62
-#define RADIO_2056_SYN_PLL_STATUS1 0x63
-#define RADIO_2056_SYN_PLL_STATUS2 0x64
-#define RADIO_2056_SYN_PLL_STATUS3 0x65
-#define RADIO_2056_SYN_LOGEN_PU0 0x66
-#define RADIO_2056_SYN_LOGEN_PU1 0x67
-#define RADIO_2056_SYN_LOGEN_PU2 0x68
-#define RADIO_2056_SYN_LOGEN_PU3 0x69
-#define RADIO_2056_SYN_LOGEN_PU5 0x6a
-#define RADIO_2056_SYN_LOGEN_PU6 0x6b
-#define RADIO_2056_SYN_LOGEN_PU7 0x6c
-#define RADIO_2056_SYN_LOGEN_PU8 0x6d
-#define RADIO_2056_SYN_LOGEN_BIAS_RESET 0x6e
-#define RADIO_2056_SYN_LOGEN_RCCR1 0x6f
-#define RADIO_2056_SYN_LOGEN_VCOBUF1 0x70
-#define RADIO_2056_SYN_LOGEN_MIXER1 0x71
-#define RADIO_2056_SYN_LOGEN_MIXER2 0x72
-#define RADIO_2056_SYN_LOGEN_BUF1 0x73
-#define RADIO_2056_SYN_LOGENBUF2 0x74
-#define RADIO_2056_SYN_LOGEN_BUF3 0x75
-#define RADIO_2056_SYN_LOGEN_BUF4 0x76
-#define RADIO_2056_SYN_LOGEN_DIV1 0x77
-#define RADIO_2056_SYN_LOGEN_DIV2 0x78
-#define RADIO_2056_SYN_LOGEN_DIV3 0x79
-#define RADIO_2056_SYN_LOGEN_ACL1 0x7a
-#define RADIO_2056_SYN_LOGEN_ACL2 0x7b
-#define RADIO_2056_SYN_LOGEN_ACL3 0x7c
-#define RADIO_2056_SYN_LOGEN_ACL4 0x7d
-#define RADIO_2056_SYN_LOGEN_ACL5 0x7e
-#define RADIO_2056_SYN_LOGEN_ACL6 0x7f
-#define RADIO_2056_SYN_LOGEN_ACLOUT 0x80
-#define RADIO_2056_SYN_LOGEN_ACLCAL1 0x81
-#define RADIO_2056_SYN_LOGEN_ACLCAL2 0x82
-#define RADIO_2056_SYN_LOGEN_ACLCAL3 0x83
-#define RADIO_2056_SYN_CALEN 0x84
-#define RADIO_2056_SYN_LOGEN_PEAKDET1 0x85
-#define RADIO_2056_SYN_LOGEN_CORE_ACL_OVR 0x86
-#define RADIO_2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87
-#define RADIO_2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88
-#define RADIO_2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89
-#define RADIO_2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8a
-#define RADIO_2056_SYN_LOGEN_VCOBUF2 0x8b
-#define RADIO_2056_SYN_LOGEN_MIXER3 0x8c
-#define RADIO_2056_SYN_LOGEN_BUF5 0x8d
-#define RADIO_2056_SYN_LOGEN_BUF6 0x8e
-#define RADIO_2056_SYN_LOGEN_CBUFRX1 0x8f
-#define RADIO_2056_SYN_LOGEN_CBUFRX2 0x90
-#define RADIO_2056_SYN_LOGEN_CBUFRX3 0x91
-#define RADIO_2056_SYN_LOGEN_CBUFRX4 0x92
-#define RADIO_2056_SYN_LOGEN_CBUFTX1 0x93
-#define RADIO_2056_SYN_LOGEN_CBUFTX2 0x94
-#define RADIO_2056_SYN_LOGEN_CBUFTX3 0x95
-#define RADIO_2056_SYN_LOGEN_CBUFTX4 0x96
-#define RADIO_2056_SYN_LOGEN_CMOSRX1 0x97
-#define RADIO_2056_SYN_LOGEN_CMOSRX2 0x98
-#define RADIO_2056_SYN_LOGEN_CMOSRX3 0x99
-#define RADIO_2056_SYN_LOGEN_CMOSRX4 0x9a
-#define RADIO_2056_SYN_LOGEN_CMOSTX1 0x9b
-#define RADIO_2056_SYN_LOGEN_CMOSTX2 0x9c
-#define RADIO_2056_SYN_LOGEN_CMOSTX3 0x9d
-#define RADIO_2056_SYN_LOGEN_CMOSTX4 0x9e
-#define RADIO_2056_SYN_LOGEN_VCOBUF2_OVRVAL 0x9f
-#define RADIO_2056_SYN_LOGEN_MIXER3_OVRVAL 0xa0
-#define RADIO_2056_SYN_LOGEN_BUF5_OVRVAL 0xa1
-#define RADIO_2056_SYN_LOGEN_BUF6_OVRVAL 0xa2
-#define RADIO_2056_SYN_LOGEN_CBUFRX1_OVRVAL 0xa3
-#define RADIO_2056_SYN_LOGEN_CBUFRX2_OVRVAL 0xa4
-#define RADIO_2056_SYN_LOGEN_CBUFRX3_OVRVAL 0xa5
-#define RADIO_2056_SYN_LOGEN_CBUFRX4_OVRVAL 0xa6
-#define RADIO_2056_SYN_LOGEN_CBUFTX1_OVRVAL 0xa7
-#define RADIO_2056_SYN_LOGEN_CBUFTX2_OVRVAL 0xa8
-#define RADIO_2056_SYN_LOGEN_CBUFTX3_OVRVAL 0xa9
-#define RADIO_2056_SYN_LOGEN_CBUFTX4_OVRVAL 0xaa
-#define RADIO_2056_SYN_LOGEN_CMOSRX1_OVRVAL 0xab
-#define RADIO_2056_SYN_LOGEN_CMOSRX2_OVRVAL 0xac
-#define RADIO_2056_SYN_LOGEN_CMOSRX3_OVRVAL 0xad
-#define RADIO_2056_SYN_LOGEN_CMOSRX4_OVRVAL 0xae
-#define RADIO_2056_SYN_LOGEN_CMOSTX1_OVRVAL 0xaf
-#define RADIO_2056_SYN_LOGEN_CMOSTX2_OVRVAL 0xb0
-#define RADIO_2056_SYN_LOGEN_CMOSTX3_OVRVAL 0xb1
-#define RADIO_2056_SYN_LOGEN_CMOSTX4_OVRVAL 0xb2
-#define RADIO_2056_SYN_LOGEN_ACL_WAITCNT 0xb3
-#define RADIO_2056_SYN_LOGEN_CORE_CALVALID 0xb4
-#define RADIO_2056_SYN_LOGEN_RX_CMOS_CALVALID 0xb5
-#define RADIO_2056_SYN_LOGEN_TX_CMOS_VALID 0xb6
-
-#define RADIO_2056_TX_RESERVED_ADDR0 0x0
-#define RADIO_2056_TX_IDCODE 0x1
-#define RADIO_2056_TX_RESERVED_ADDR2 0x2
-#define RADIO_2056_TX_RESERVED_ADDR3 0x3
-#define RADIO_2056_TX_RESERVED_ADDR4 0x4
-#define RADIO_2056_TX_RESERVED_ADDR5 0x5
-#define RADIO_2056_TX_RESERVED_ADDR6 0x6
-#define RADIO_2056_TX_RESERVED_ADDR7 0x7
-#define RADIO_2056_TX_COM_CTRL 0x8
-#define RADIO_2056_TX_COM_PU 0x9
-#define RADIO_2056_TX_COM_OVR 0xa
-#define RADIO_2056_TX_COM_RESET 0xb
-#define RADIO_2056_TX_COM_RCAL 0xc
-#define RADIO_2056_TX_COM_RC_RXLPF 0xd
-#define RADIO_2056_TX_COM_RC_TXLPF 0xe
-#define RADIO_2056_TX_COM_RC_RXHPF 0xf
-#define RADIO_2056_TX_RESERVED_ADDR16 0x10
-#define RADIO_2056_TX_RESERVED_ADDR17 0x11
-#define RADIO_2056_TX_RESERVED_ADDR18 0x12
-#define RADIO_2056_TX_RESERVED_ADDR19 0x13
-#define RADIO_2056_TX_RESERVED_ADDR20 0x14
-#define RADIO_2056_TX_RESERVED_ADDR21 0x15
-#define RADIO_2056_TX_RESERVED_ADDR22 0x16
-#define RADIO_2056_TX_RESERVED_ADDR23 0x17
-#define RADIO_2056_TX_RESERVED_ADDR24 0x18
-#define RADIO_2056_TX_RESERVED_ADDR25 0x19
-#define RADIO_2056_TX_RESERVED_ADDR26 0x1a
-#define RADIO_2056_TX_RESERVED_ADDR27 0x1b
-#define RADIO_2056_TX_RESERVED_ADDR28 0x1c
-#define RADIO_2056_TX_RESERVED_ADDR29 0x1d
-#define RADIO_2056_TX_RESERVED_ADDR30 0x1e
-#define RADIO_2056_TX_RESERVED_ADDR31 0x1f
-#define RADIO_2056_TX_IQCAL_GAIN_BW 0x20
-#define RADIO_2056_TX_LOFT_FINE_I 0x21
-#define RADIO_2056_TX_LOFT_FINE_Q 0x22
-#define RADIO_2056_TX_LOFT_COARSE_I 0x23
-#define RADIO_2056_TX_LOFT_COARSE_Q 0x24
-#define RADIO_2056_TX_TX_COM_MASTER1 0x25
-#define RADIO_2056_TX_TX_COM_MASTER2 0x26
-#define RADIO_2056_TX_RXIQCAL_TXMUX 0x27
-#define RADIO_2056_TX_TX_SSI_MASTER 0x28
-#define RADIO_2056_TX_IQCAL_VCM_HG 0x29
-#define RADIO_2056_TX_IQCAL_IDAC 0x2a
-#define RADIO_2056_TX_TSSI_VCM 0x2b
-#define RADIO_2056_TX_TX_AMP_DET 0x2c
-#define RADIO_2056_TX_TX_SSI_MUX 0x2d
-#define RADIO_2056_TX_TSSIA 0x2e
-#define RADIO_2056_TX_TSSIG 0x2f
-#define RADIO_2056_TX_TSSI_MISC1 0x30
-#define RADIO_2056_TX_TSSI_MISC2 0x31
-#define RADIO_2056_TX_TSSI_MISC3 0x32
-#define RADIO_2056_TX_PA_SPARE1 0x33
-#define RADIO_2056_TX_PA_SPARE2 0x34
-#define RADIO_2056_TX_INTPAA_MASTER 0x35
-#define RADIO_2056_TX_INTPAA_GAIN 0x36
-#define RADIO_2056_TX_INTPAA_BOOST_TUNE 0x37
-#define RADIO_2056_TX_INTPAA_IAUX_STAT 0x38
-#define RADIO_2056_TX_INTPAA_IAUX_DYN 0x39
-#define RADIO_2056_TX_INTPAA_IMAIN_STAT 0x3a
-#define RADIO_2056_TX_INTPAA_IMAIN_DYN 0x3b
-#define RADIO_2056_TX_INTPAA_CASCBIAS 0x3c
-#define RADIO_2056_TX_INTPAA_PASLOPE 0x3d
-#define RADIO_2056_TX_INTPAA_PA_MISC 0x3e
-#define RADIO_2056_TX_INTPAG_MASTER 0x3f
-#define RADIO_2056_TX_INTPAG_GAIN 0x40
-#define RADIO_2056_TX_INTPAG_BOOST_TUNE 0x41
-#define RADIO_2056_TX_INTPAG_IAUX_STAT 0x42
-#define RADIO_2056_TX_INTPAG_IAUX_DYN 0x43
-#define RADIO_2056_TX_INTPAG_IMAIN_STAT 0x44
-#define RADIO_2056_TX_INTPAG_IMAIN_DYN 0x45
-#define RADIO_2056_TX_INTPAG_CASCBIAS 0x46
-#define RADIO_2056_TX_INTPAG_PASLOPE 0x47
-#define RADIO_2056_TX_INTPAG_PA_MISC 0x48
-#define RADIO_2056_TX_PADA_MASTER 0x49
-#define RADIO_2056_TX_PADA_IDAC 0x4a
-#define RADIO_2056_TX_PADA_CASCBIAS 0x4b
-#define RADIO_2056_TX_PADA_GAIN 0x4c
-#define RADIO_2056_TX_PADA_BOOST_TUNE 0x4d
-#define RADIO_2056_TX_PADA_SLOPE 0x4e
-#define RADIO_2056_TX_PADG_MASTER 0x4f
-#define RADIO_2056_TX_PADG_IDAC 0x50
-#define RADIO_2056_TX_PADG_CASCBIAS 0x51
-#define RADIO_2056_TX_PADG_GAIN 0x52
-#define RADIO_2056_TX_PADG_BOOST_TUNE 0x53
-#define RADIO_2056_TX_PADG_SLOPE 0x54
-#define RADIO_2056_TX_PGAA_MASTER 0x55
-#define RADIO_2056_TX_PGAA_IDAC 0x56
-#define RADIO_2056_TX_PGAA_GAIN 0x57
-#define RADIO_2056_TX_PGAA_BOOST_TUNE 0x58
-#define RADIO_2056_TX_PGAA_SLOPE 0x59
-#define RADIO_2056_TX_PGAA_MISC 0x5a
-#define RADIO_2056_TX_PGAG_MASTER 0x5b
-#define RADIO_2056_TX_PGAG_IDAC 0x5c
-#define RADIO_2056_TX_PGAG_GAIN 0x5d
-#define RADIO_2056_TX_PGAG_BOOST_TUNE 0x5e
-#define RADIO_2056_TX_PGAG_SLOPE 0x5f
-#define RADIO_2056_TX_PGAG_MISC 0x60
-#define RADIO_2056_TX_MIXA_MASTER 0x61
-#define RADIO_2056_TX_MIXA_BOOST_TUNE 0x62
-#define RADIO_2056_TX_MIXG 0x63
-#define RADIO_2056_TX_MIXG_BOOST_TUNE 0x64
-#define RADIO_2056_TX_BB_GM_MASTER 0x65
-#define RADIO_2056_TX_GMBB_GM 0x66
-#define RADIO_2056_TX_GMBB_IDAC 0x67
-#define RADIO_2056_TX_TXLPF_MASTER 0x68
-#define RADIO_2056_TX_TXLPF_RCCAL 0x69
-#define RADIO_2056_TX_TXLPF_RCCAL_OFF0 0x6a
-#define RADIO_2056_TX_TXLPF_RCCAL_OFF1 0x6b
-#define RADIO_2056_TX_TXLPF_RCCAL_OFF2 0x6c
-#define RADIO_2056_TX_TXLPF_RCCAL_OFF3 0x6d
-#define RADIO_2056_TX_TXLPF_RCCAL_OFF4 0x6e
-#define RADIO_2056_TX_TXLPF_RCCAL_OFF5 0x6f
-#define RADIO_2056_TX_TXLPF_RCCAL_OFF6 0x70
-#define RADIO_2056_TX_TXLPF_BW 0x71
-#define RADIO_2056_TX_TXLPF_GAIN 0x72
-#define RADIO_2056_TX_TXLPF_IDAC 0x73
-#define RADIO_2056_TX_TXLPF_IDAC_0 0x74
-#define RADIO_2056_TX_TXLPF_IDAC_1 0x75
-#define RADIO_2056_TX_TXLPF_IDAC_2 0x76
-#define RADIO_2056_TX_TXLPF_IDAC_3 0x77
-#define RADIO_2056_TX_TXLPF_IDAC_4 0x78
-#define RADIO_2056_TX_TXLPF_IDAC_5 0x79
-#define RADIO_2056_TX_TXLPF_IDAC_6 0x7a
-#define RADIO_2056_TX_TXLPF_OPAMP_IDAC 0x7b
-#define RADIO_2056_TX_TXLPF_MISC 0x7c
-#define RADIO_2056_TX_TXSPARE1 0x7d
-#define RADIO_2056_TX_TXSPARE2 0x7e
-#define RADIO_2056_TX_TXSPARE3 0x7f
-#define RADIO_2056_TX_TXSPARE4 0x80
-#define RADIO_2056_TX_TXSPARE5 0x81
-#define RADIO_2056_TX_TXSPARE6 0x82
-#define RADIO_2056_TX_TXSPARE7 0x83
-#define RADIO_2056_TX_TXSPARE8 0x84
-#define RADIO_2056_TX_TXSPARE9 0x85
-#define RADIO_2056_TX_TXSPARE10 0x86
-#define RADIO_2056_TX_TXSPARE11 0x87
-#define RADIO_2056_TX_TXSPARE12 0x88
-#define RADIO_2056_TX_TXSPARE13 0x89
-#define RADIO_2056_TX_TXSPARE14 0x8a
-#define RADIO_2056_TX_TXSPARE15 0x8b
-#define RADIO_2056_TX_TXSPARE16 0x8c
-#define RADIO_2056_TX_STATUS_INTPA_GAIN 0x8d
-#define RADIO_2056_TX_STATUS_PAD_GAIN 0x8e
-#define RADIO_2056_TX_STATUS_PGA_GAIN 0x8f
-#define RADIO_2056_TX_STATUS_GM_TXLPF_GAIN 0x90
-#define RADIO_2056_TX_STATUS_TXLPF_BW 0x91
-#define RADIO_2056_TX_STATUS_TXLPF_RC 0x92
-#define RADIO_2056_TX_GMBB_IDAC0 0x93
-#define RADIO_2056_TX_GMBB_IDAC1 0x94
-#define RADIO_2056_TX_GMBB_IDAC2 0x95
-#define RADIO_2056_TX_GMBB_IDAC3 0x96
-#define RADIO_2056_TX_GMBB_IDAC4 0x97
-#define RADIO_2056_TX_GMBB_IDAC5 0x98
-#define RADIO_2056_TX_GMBB_IDAC6 0x99
-#define RADIO_2056_TX_GMBB_IDAC7 0x9a
-
-#define RADIO_2056_RX_RESERVED_ADDR0 0x0
-#define RADIO_2056_RX_IDCODE 0x1
-#define RADIO_2056_RX_RESERVED_ADDR2 0x2
-#define RADIO_2056_RX_RESERVED_ADDR3 0x3
-#define RADIO_2056_RX_RESERVED_ADDR4 0x4
-#define RADIO_2056_RX_RESERVED_ADDR5 0x5
-#define RADIO_2056_RX_RESERVED_ADDR6 0x6
-#define RADIO_2056_RX_RESERVED_ADDR7 0x7
-#define RADIO_2056_RX_COM_CTRL 0x8
-#define RADIO_2056_RX_COM_PU 0x9
-#define RADIO_2056_RX_COM_OVR 0xa
-#define RADIO_2056_RX_COM_RESET 0xb
-#define RADIO_2056_RX_COM_RCAL 0xc
-#define RADIO_2056_RX_COM_RC_RXLPF 0xd
-#define RADIO_2056_RX_COM_RC_TXLPF 0xe
-#define RADIO_2056_RX_COM_RC_RXHPF 0xf
-#define RADIO_2056_RX_RESERVED_ADDR16 0x10
-#define RADIO_2056_RX_RESERVED_ADDR17 0x11
-#define RADIO_2056_RX_RESERVED_ADDR18 0x12
-#define RADIO_2056_RX_RESERVED_ADDR19 0x13
-#define RADIO_2056_RX_RESERVED_ADDR20 0x14
-#define RADIO_2056_RX_RESERVED_ADDR21 0x15
-#define RADIO_2056_RX_RESERVED_ADDR22 0x16
-#define RADIO_2056_RX_RESERVED_ADDR23 0x17
-#define RADIO_2056_RX_RESERVED_ADDR24 0x18
-#define RADIO_2056_RX_RESERVED_ADDR25 0x19
-#define RADIO_2056_RX_RESERVED_ADDR26 0x1a
-#define RADIO_2056_RX_RESERVED_ADDR27 0x1b
-#define RADIO_2056_RX_RESERVED_ADDR28 0x1c
-#define RADIO_2056_RX_RESERVED_ADDR29 0x1d
-#define RADIO_2056_RX_RESERVED_ADDR30 0x1e
-#define RADIO_2056_RX_RESERVED_ADDR31 0x1f
-#define RADIO_2056_RX_RXIQCAL_RXMUX 0x20
-#define RADIO_2056_RX_RSSI_PU 0x21
-#define RADIO_2056_RX_RSSI_SEL 0x22
-#define RADIO_2056_RX_RSSI_GAIN 0x23
-#define RADIO_2056_RX_RSSI_NB_IDAC 0x24
-#define RADIO_2056_RX_RSSI_WB2I_IDAC_1 0x25
-#define RADIO_2056_RX_RSSI_WB2I_IDAC_2 0x26
-#define RADIO_2056_RX_RSSI_WB2Q_IDAC_1 0x27
-#define RADIO_2056_RX_RSSI_WB2Q_IDAC_2 0x28
-#define RADIO_2056_RX_RSSI_POLE 0x29
-#define RADIO_2056_RX_RSSI_WB1_IDAC 0x2a
-#define RADIO_2056_RX_RSSI_MISC 0x2b
-#define RADIO_2056_RX_LNAA_MASTER 0x2c
-#define RADIO_2056_RX_LNAA_TUNE 0x2d
-#define RADIO_2056_RX_LNAA_GAIN 0x2e
-#define RADIO_2056_RX_LNA_A_SLOPE 0x2f
-#define RADIO_2056_RX_BIASPOLE_LNAA1_IDAC 0x30
-#define RADIO_2056_RX_LNAA2_IDAC 0x31
-#define RADIO_2056_RX_LNA1A_MISC 0x32
-#define RADIO_2056_RX_LNAG_MASTER 0x33
-#define RADIO_2056_RX_LNAG_TUNE 0x34
-#define RADIO_2056_RX_LNAG_GAIN 0x35
-#define RADIO_2056_RX_LNA_G_SLOPE 0x36
-#define RADIO_2056_RX_BIASPOLE_LNAG1_IDAC 0x37
-#define RADIO_2056_RX_LNAG2_IDAC 0x38
-#define RADIO_2056_RX_LNA1G_MISC 0x39
-#define RADIO_2056_RX_MIXA_MASTER 0x3a
-#define RADIO_2056_RX_MIXA_VCM 0x3b
-#define RADIO_2056_RX_MIXA_CTRLPTAT 0x3c
-#define RADIO_2056_RX_MIXA_LOB_BIAS 0x3d
-#define RADIO_2056_RX_MIXA_CORE_IDAC 0x3e
-#define RADIO_2056_RX_MIXA_CMFB_IDAC 0x3f
-#define RADIO_2056_RX_MIXA_BIAS_AUX 0x40
-#define RADIO_2056_RX_MIXA_BIAS_MAIN 0x41
-#define RADIO_2056_RX_MIXA_BIAS_MISC 0x42
-#define RADIO_2056_RX_MIXA_MAST_BIAS 0x43
-#define RADIO_2056_RX_MIXG_MASTER 0x44
-#define RADIO_2056_RX_MIXG_VCM 0x45
-#define RADIO_2056_RX_MIXG_CTRLPTAT 0x46
-#define RADIO_2056_RX_MIXG_LOB_BIAS 0x47
-#define RADIO_2056_RX_MIXG_CORE_IDAC 0x48
-#define RADIO_2056_RX_MIXG_CMFB_IDAC 0x49
-#define RADIO_2056_RX_MIXG_BIAS_AUX 0x4a
-#define RADIO_2056_RX_MIXG_BIAS_MAIN 0x4b
-#define RADIO_2056_RX_MIXG_BIAS_MISC 0x4c
-#define RADIO_2056_RX_MIXG_MAST_BIAS 0x4d
-#define RADIO_2056_RX_TIA_MASTER 0x4e
-#define RADIO_2056_RX_TIA_IOPAMP 0x4f
-#define RADIO_2056_RX_TIA_QOPAMP 0x50
-#define RADIO_2056_RX_TIA_IMISC 0x51
-#define RADIO_2056_RX_TIA_QMISC 0x52
-#define RADIO_2056_RX_TIA_GAIN 0x53
-#define RADIO_2056_RX_TIA_SPARE1 0x54
-#define RADIO_2056_RX_TIA_SPARE2 0x55
-#define RADIO_2056_RX_BB_LPF_MASTER 0x56
-#define RADIO_2056_RX_AACI_MASTER 0x57
-#define RADIO_2056_RX_RXLPF_IDAC 0x58
-#define RADIO_2056_RX_RXLPF_OPAMPBIAS_LOWQ 0x59
-#define RADIO_2056_RX_RXLPF_OPAMPBIAS_HIGHQ 0x5a
-#define RADIO_2056_RX_RXLPF_BIAS_DCCANCEL 0x5b
-#define RADIO_2056_RX_RXLPF_OUTVCM 0x5c
-#define RADIO_2056_RX_RXLPF_INVCM_BODY 0x5d
-#define RADIO_2056_RX_RXLPF_CC_OP 0x5e
-#define RADIO_2056_RX_RXLPF_GAIN 0x5f
-#define RADIO_2056_RX_RXLPF_Q_BW 0x60
-#define RADIO_2056_RX_RXLPF_HP_CORNER_BW 0x61
-#define RADIO_2056_RX_RXLPF_RCCAL_HPC 0x62
-#define RADIO_2056_RX_RXHPF_OFF0 0x63
-#define RADIO_2056_RX_RXHPF_OFF1 0x64
-#define RADIO_2056_RX_RXHPF_OFF2 0x65
-#define RADIO_2056_RX_RXHPF_OFF3 0x66
-#define RADIO_2056_RX_RXHPF_OFF4 0x67
-#define RADIO_2056_RX_RXHPF_OFF5 0x68
-#define RADIO_2056_RX_RXHPF_OFF6 0x69
-#define RADIO_2056_RX_RXHPF_OFF7 0x6a
-#define RADIO_2056_RX_RXLPF_RCCAL_LPC 0x6b
-#define RADIO_2056_RX_RXLPF_OFF_0 0x6c
-#define RADIO_2056_RX_RXLPF_OFF_1 0x6d
-#define RADIO_2056_RX_RXLPF_OFF_2 0x6e
-#define RADIO_2056_RX_RXLPF_OFF_3 0x6f
-#define RADIO_2056_RX_RXLPF_OFF_4 0x70
-#define RADIO_2056_RX_UNUSED 0x71
-#define RADIO_2056_RX_VGA_MASTER 0x72
-#define RADIO_2056_RX_VGA_BIAS 0x73
-#define RADIO_2056_RX_VGA_BIAS_DCCANCEL 0x74
-#define RADIO_2056_RX_VGA_GAIN 0x75
-#define RADIO_2056_RX_VGA_HP_CORNER_BW 0x76
-#define RADIO_2056_RX_VGABUF_BIAS 0x77
-#define RADIO_2056_RX_VGABUF_GAIN_BW 0x78
-#define RADIO_2056_RX_TXFBMIX_A 0x79
-#define RADIO_2056_RX_TXFBMIX_G 0x7a
-#define RADIO_2056_RX_RXSPARE1 0x7b
-#define RADIO_2056_RX_RXSPARE2 0x7c
-#define RADIO_2056_RX_RXSPARE3 0x7d
-#define RADIO_2056_RX_RXSPARE4 0x7e
-#define RADIO_2056_RX_RXSPARE5 0x7f
-#define RADIO_2056_RX_RXSPARE6 0x80
-#define RADIO_2056_RX_RXSPARE7 0x81
-#define RADIO_2056_RX_RXSPARE8 0x82
-#define RADIO_2056_RX_RXSPARE9 0x83
-#define RADIO_2056_RX_RXSPARE10 0x84
-#define RADIO_2056_RX_RXSPARE11 0x85
-#define RADIO_2056_RX_RXSPARE12 0x86
-#define RADIO_2056_RX_RXSPARE13 0x87
-#define RADIO_2056_RX_RXSPARE14 0x88
-#define RADIO_2056_RX_RXSPARE15 0x89
-#define RADIO_2056_RX_RXSPARE16 0x8a
-#define RADIO_2056_RX_STATUS_LNAA_GAIN 0x8b
-#define RADIO_2056_RX_STATUS_LNAG_GAIN 0x8c
-#define RADIO_2056_RX_STATUS_MIXTIA_GAIN 0x8d
-#define RADIO_2056_RX_STATUS_RXLPF_GAIN 0x8e
-#define RADIO_2056_RX_STATUS_VGA_BUF_GAIN 0x8f
-#define RADIO_2056_RX_STATUS_RXLPF_Q 0x90
-#define RADIO_2056_RX_STATUS_RXLPF_BUF_BW 0x91
-#define RADIO_2056_RX_STATUS_RXLPF_VGA_HPC 0x92
-#define RADIO_2056_RX_STATUS_RXLPF_RC 0x93
-#define RADIO_2056_RX_STATUS_HPC_RC 0x94
-
-#define RADIO_2056_LNA1_A_PU 0x01
-#define RADIO_2056_LNA2_A_PU 0x02
-#define RADIO_2056_LNA1_G_PU 0x01
-#define RADIO_2056_LNA2_G_PU 0x02
-#define RADIO_2056_MIXA_PU_I 0x01
-#define RADIO_2056_MIXA_PU_Q 0x02
-#define RADIO_2056_MIXA_PU_GM 0x10
-#define RADIO_2056_MIXG_PU_I 0x01
-#define RADIO_2056_MIXG_PU_Q 0x02
-#define RADIO_2056_MIXG_PU_GM 0x10
-#define RADIO_2056_TIA_PU 0x01
-#define RADIO_2056_BB_LPF_PU 0x20
-#define RADIO_2056_W1_PU 0x02
-#define RADIO_2056_W2_PU 0x04
-#define RADIO_2056_NB_PU 0x08
-#define RADIO_2056_RSSI_W1_SEL 0x02
-#define RADIO_2056_RSSI_W2_SEL 0x04
-#define RADIO_2056_RSSI_NB_SEL 0x08
-#define RADIO_2056_VCM_MASK 0x1c
-#define RADIO_2056_RSSI_VCM_SHIFT 0x02
-
-#define RADIO_2057_DACBUF_VINCM_CORE0 0x0
-#define RADIO_2057_IDCODE 0x1
-#define RADIO_2057_RCCAL_MASTER 0x2
-#define RADIO_2057_RCCAL_CAP_SIZE 0x3
-#define RADIO_2057_RCAL_CONFIG 0x4
-#define RADIO_2057_GPAIO_CONFIG 0x5
-#define RADIO_2057_GPAIO_SEL1 0x6
-#define RADIO_2057_GPAIO_SEL0 0x7
-#define RADIO_2057_CLPO_CONFIG 0x8
-#define RADIO_2057_BANDGAP_CONFIG 0x9
-#define RADIO_2057_BANDGAP_RCAL_TRIM 0xa
-#define RADIO_2057_AFEREG_CONFIG 0xb
-#define RADIO_2057_TEMPSENSE_CONFIG 0xc
-#define RADIO_2057_XTAL_CONFIG1 0xd
-#define RADIO_2057_XTAL_ICORE_SIZE 0xe
-#define RADIO_2057_XTAL_BUF_SIZE 0xf
-#define RADIO_2057_XTAL_PULLCAP_SIZE 0x10
-#define RADIO_2057_RFPLL_MASTER 0x11
-#define RADIO_2057_VCOMONITOR_VTH_L 0x12
-#define RADIO_2057_VCOMONITOR_VTH_H 0x13
-#define RADIO_2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x14
-#define RADIO_2057_VCO_VARCSIZE_IDAC 0x15
-#define RADIO_2057_VCOCAL_COUNTVAL0 0x16
-#define RADIO_2057_VCOCAL_COUNTVAL1 0x17
-#define RADIO_2057_VCOCAL_INTCLK_COUNT 0x18
-#define RADIO_2057_VCOCAL_MASTER 0x19
-#define RADIO_2057_VCOCAL_NUMCAPCHANGE 0x1a
-#define RADIO_2057_VCOCAL_WINSIZE 0x1b
-#define RADIO_2057_VCOCAL_DELAY_AFTER_REFRESH 0x1c
-#define RADIO_2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x1d
-#define RADIO_2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x1e
-#define RADIO_2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x1f
-#define RADIO_2057_VCO_FORCECAPEN_FORCECAP1 0x20
-#define RADIO_2057_VCO_FORCECAP0 0x21
-#define RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x22
-#define RADIO_2057_RFPLL_PFD_RESET_PW 0x23
-#define RADIO_2057_RFPLL_LOOPFILTER_R2 0x24
-#define RADIO_2057_RFPLL_LOOPFILTER_R1 0x25
-#define RADIO_2057_RFPLL_LOOPFILTER_C3 0x26
-#define RADIO_2057_RFPLL_LOOPFILTER_C2 0x27
-#define RADIO_2057_RFPLL_LOOPFILTER_C1 0x28
-#define RADIO_2057_CP_KPD_IDAC 0x29
-#define RADIO_2057_RFPLL_IDACS 0x2a
-#define RADIO_2057_RFPLL_MISC_EN 0x2b
-#define RADIO_2057_RFPLL_MMD0 0x2c
-#define RADIO_2057_RFPLL_MMD1 0x2d
-#define RADIO_2057_RFPLL_MISC_CAL_RESETN 0x2e
-#define RADIO_2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x2f
-#define RADIO_2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x30
-#define RADIO_2057_VCOCAL_READCAP0 0x31
-#define RADIO_2057_VCOCAL_READCAP1 0x32
-#define RADIO_2057_VCOCAL_STATUS 0x33
-#define RADIO_2057_LOGEN_PUS 0x34
-#define RADIO_2057_LOGEN_PTAT_RESETS 0x35
-#define RADIO_2057_VCOBUF_IDACS 0x36
-#define RADIO_2057_VCOBUF_TUNE 0x37
-#define RADIO_2057_CMOSBUF_TX2GQ_IDACS 0x38
-#define RADIO_2057_CMOSBUF_TX2GI_IDACS 0x39
-#define RADIO_2057_CMOSBUF_TX5GQ_IDACS 0x3a
-#define RADIO_2057_CMOSBUF_TX5GI_IDACS 0x3b
-#define RADIO_2057_CMOSBUF_RX2GQ_IDACS 0x3c
-#define RADIO_2057_CMOSBUF_RX2GI_IDACS 0x3d
-#define RADIO_2057_CMOSBUF_RX5GQ_IDACS 0x3e
-#define RADIO_2057_CMOSBUF_RX5GI_IDACS 0x3f
-#define RADIO_2057_LOGEN_MX2G_IDACS 0x40
-#define RADIO_2057_LOGEN_MX2G_TUNE 0x41
-#define RADIO_2057_LOGEN_MX5G_IDACS 0x42
-#define RADIO_2057_LOGEN_MX5G_TUNE 0x43
-#define RADIO_2057_LOGEN_MX5G_RCCR 0x44
-#define RADIO_2057_LOGEN_INDBUF2G_IDAC 0x45
-#define RADIO_2057_LOGEN_INDBUF2G_IBOOST 0x46
-#define RADIO_2057_LOGEN_INDBUF2G_TUNE 0x47
-#define RADIO_2057_LOGEN_INDBUF5G_IDAC 0x48
-#define RADIO_2057_LOGEN_INDBUF5G_IBOOST 0x49
-#define RADIO_2057_LOGEN_INDBUF5G_TUNE 0x4a
-#define RADIO_2057_CMOSBUF_TX_RCCR 0x4b
-#define RADIO_2057_CMOSBUF_RX_RCCR 0x4c
-#define RADIO_2057_LOGEN_SEL_PKDET 0x4d
-#define RADIO_2057_CMOSBUF_SHAREIQ_PTAT 0x4e
-#define RADIO_2057_RXTXBIAS_CONFIG_CORE0 0x4f
-#define RADIO_2057_TXGM_TXRF_PUS_CORE0 0x50
-#define RADIO_2057_TXGM_IDAC_BLEED_CORE0 0x51
-#define RADIO_2057_TXGM_GAIN_CORE0 0x56
-#define RADIO_2057_TXGM2G_PKDET_PUS_CORE0 0x57
-#define RADIO_2057_PAD2G_PTATS_CORE0 0x58
-#define RADIO_2057_PAD2G_IDACS_CORE0 0x59
-#define RADIO_2057_PAD2G_BOOST_PU_CORE0 0x5a
-#define RADIO_2057_PAD2G_CASCV_GAIN_CORE0 0x5b
-#define RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x5c
-#define RADIO_2057_TXMIX2G_LODC_CORE0 0x5d
-#define RADIO_2057_PAD2G_TUNE_PUS_CORE0 0x5e
-#define RADIO_2057_IPA2G_GAIN_CORE0 0x5f
-#define RADIO_2057_TSSI2G_SPARE1_CORE0 0x60
-#define RADIO_2057_TSSI2G_SPARE2_CORE0 0x61
-#define RADIO_2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x62
-#define RADIO_2057_IPA2G_IMAIN_CORE0 0x63
-#define RADIO_2057_IPA2G_CASCONV_CORE0 0x64
-#define RADIO_2057_IPA2G_CASCOFFV_CORE0 0x65
-#define RADIO_2057_IPA2G_BIAS_FILTER_CORE0 0x66
-#define RADIO_2057_TX5G_PKDET_CORE0 0x69
-#define RADIO_2057_PGA_PTAT_TXGM5G_PU_CORE0 0x6a
-#define RADIO_2057_PAD5G_PTATS1_CORE0 0x6b
-#define RADIO_2057_PAD5G_CLASS_PTATS2_CORE0 0x6c
-#define RADIO_2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x6d
-#define RADIO_2057_PAD5G_CASCV_IMAIN_CORE0 0x6e
-#define RADIO_2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x6f
-#define RADIO_2057_PGA_BOOST_TUNE_CORE0 0x70
-#define RADIO_2057_PGA_GAIN_CORE0 0x71
-#define RADIO_2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x72
-#define RADIO_2057_TXMIX5G_BOOST_TUNE_CORE0 0x73
-#define RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE0 0x74
-#define RADIO_2057_IPA5G_IAUX_CORE0 0x75
-#define RADIO_2057_IPA5G_GAIN_CORE0 0x76
-#define RADIO_2057_TSSI5G_SPARE1_CORE0 0x77
-#define RADIO_2057_TSSI5G_SPARE2_CORE0 0x78
-#define RADIO_2057_IPA5G_CASCOFFV_PU_CORE0 0x79
-#define RADIO_2057_IPA5G_PTAT_CORE0 0x7a
-#define RADIO_2057_IPA5G_IMAIN_CORE0 0x7b
-#define RADIO_2057_IPA5G_CASCONV_CORE0 0x7c
-#define RADIO_2057_IPA5G_BIAS_FILTER_CORE0 0x7d
-#define RADIO_2057_PAD_BIAS_FILTER_BWS_CORE0 0x80
-#define RADIO_2057_TR2G_CONFIG1_CORE0_NU 0x81
-#define RADIO_2057_TR2G_CONFIG2_CORE0_NU 0x82
-#define RADIO_2057_LNA5G_RFEN_CORE0 0x83
-#define RADIO_2057_TR5G_CONFIG2_CORE0_NU 0x84
-#define RADIO_2057_RXRFBIAS_IBOOST_PU_CORE0 0x85
-#define RADIO_2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x86
-#define RADIO_2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x87
-#define RADIO_2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x88
-#define RADIO_2057_RXMIX_CMFBITAIL_PU_CORE0 0x89
-#define RADIO_2057_LNA2_IMAIN_PTAT_PU_CORE0 0x8a
-#define RADIO_2057_LNA2_IAUX_PTAT_CORE0 0x8b
-#define RADIO_2057_LNA1_IMAIN_PTAT_PU_CORE0 0x8c
-#define RADIO_2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x8d
-#define RADIO_2057_RXRFBIAS_BANDSEL_CORE0 0x8e
-#define RADIO_2057_TIA_CONFIG_CORE0 0x8f
-#define RADIO_2057_TIA_IQGAIN_CORE0 0x90
-#define RADIO_2057_TIA_IBIAS2_CORE0 0x91
-#define RADIO_2057_TIA_IBIAS1_CORE0 0x92
-#define RADIO_2057_TIA_SPARE_Q_CORE0 0x93
-#define RADIO_2057_TIA_SPARE_I_CORE0 0x94
-#define RADIO_2057_RXMIX2G_PUS_CORE0 0x95
-#define RADIO_2057_RXMIX2G_VCMREFS_CORE0 0x96
-#define RADIO_2057_RXMIX2G_LODC_QI_CORE0 0x97
-#define RADIO_2057_W12G_BW_LNA2G_PUS_CORE0 0x98
-#define RADIO_2057_LNA2G_GAIN_CORE0 0x99
-#define RADIO_2057_LNA2G_TUNE_CORE0 0x9a
-#define RADIO_2057_RXMIX5G_PUS_CORE0 0x9b
-#define RADIO_2057_RXMIX5G_VCMREFS_CORE0 0x9c
-#define RADIO_2057_RXMIX5G_LODC_QI_CORE0 0x9d
-#define RADIO_2057_W15G_BW_LNA5G_PUS_CORE0 0x9e
-#define RADIO_2057_LNA5G_GAIN_CORE0 0x9f
-#define RADIO_2057_LNA5G_TUNE_CORE0 0xa0
-#define RADIO_2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0xa1
-#define RADIO_2057_RXBB_BIAS_MASTER_CORE0 0xa2
-#define RADIO_2057_RXBB_VGABUF_IDACS_CORE0 0xa3
-#define RADIO_2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0xa4
-#define RADIO_2057_TXBUF_VINCM_CORE0 0xa5
-#define RADIO_2057_TXBUF_IDACS_CORE0 0xa6
-#define RADIO_2057_LPF_RESP_RXBUF_BW_CORE0 0xa7
-#define RADIO_2057_RXBB_CC_CORE0 0xa8
-#define RADIO_2057_RXBB_SPARE3_CORE0 0xa9
-#define RADIO_2057_RXBB_RCCAL_HPC_CORE0 0xaa
-#define RADIO_2057_LPF_IDACS_CORE0 0xab
-#define RADIO_2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0xac
-#define RADIO_2057_TXBUF_GAIN_CORE0 0xad
-#define RADIO_2057_AFELOOPBACK_AACI_RESP_CORE0 0xae
-#define RADIO_2057_RXBUF_DEGEN_CORE0 0xaf
-#define RADIO_2057_RXBB_SPARE2_CORE0 0xb0
-#define RADIO_2057_RXBB_SPARE1_CORE0 0xb1
-#define RADIO_2057_RSSI_MASTER_CORE0 0xb2
-#define RADIO_2057_W2_MASTER_CORE0 0xb3
-#define RADIO_2057_NB_MASTER_CORE0 0xb4
-#define RADIO_2057_W2_IDACS0_Q_CORE0 0xb5
-#define RADIO_2057_W2_IDACS1_Q_CORE0 0xb6
-#define RADIO_2057_W2_IDACS0_I_CORE0 0xb7
-#define RADIO_2057_W2_IDACS1_I_CORE0 0xb8
-#define RADIO_2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0xb9
-#define RADIO_2057_NB_IDACS_Q_CORE0 0xba
-#define RADIO_2057_NB_IDACS_I_CORE0 0xbb
-#define RADIO_2057_BACKUP4_CORE0 0xc1
-#define RADIO_2057_BACKUP3_CORE0 0xc2
-#define RADIO_2057_BACKUP2_CORE0 0xc3
-#define RADIO_2057_BACKUP1_CORE0 0xc4
-#define RADIO_2057_SPARE16_CORE0 0xc5
-#define RADIO_2057_SPARE15_CORE0 0xc6
-#define RADIO_2057_SPARE14_CORE0 0xc7
-#define RADIO_2057_SPARE13_CORE0 0xc8
-#define RADIO_2057_SPARE12_CORE0 0xc9
-#define RADIO_2057_SPARE11_CORE0 0xca
-#define RADIO_2057_TX2G_BIAS_RESETS_CORE0 0xcb
-#define RADIO_2057_TX5G_BIAS_RESETS_CORE0 0xcc
-#define RADIO_2057_IQTEST_SEL_PU 0xcd
-#define RADIO_2057_XTAL_CONFIG2 0xce
-#define RADIO_2057_BUFS_MISC_LPFBW_CORE0 0xcf
-#define RADIO_2057_TXLPF_RCCAL_CORE0 0xd0
-#define RADIO_2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0xd1
-#define RADIO_2057_LPF_GAIN_CORE0 0xd2
-#define RADIO_2057_DACBUF_IDACS_BW_CORE0 0xd3
-#define RADIO_2057_RXTXBIAS_CONFIG_CORE1 0xd4
-#define RADIO_2057_TXGM_TXRF_PUS_CORE1 0xd5
-#define RADIO_2057_TXGM_IDAC_BLEED_CORE1 0xd6
-#define RADIO_2057_TXGM_GAIN_CORE1 0xdb
-#define RADIO_2057_TXGM2G_PKDET_PUS_CORE1 0xdc
-#define RADIO_2057_PAD2G_PTATS_CORE1 0xdd
-#define RADIO_2057_PAD2G_IDACS_CORE1 0xde
-#define RADIO_2057_PAD2G_BOOST_PU_CORE1 0xdf
-#define RADIO_2057_PAD2G_CASCV_GAIN_CORE1 0xe0
-#define RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0xe1
-#define RADIO_2057_TXMIX2G_LODC_CORE1 0xe2
-#define RADIO_2057_PAD2G_TUNE_PUS_CORE1 0xe3
-#define RADIO_2057_IPA2G_GAIN_CORE1 0xe4
-#define RADIO_2057_TSSI2G_SPARE1_CORE1 0xe5
-#define RADIO_2057_TSSI2G_SPARE2_CORE1 0xe6
-#define RADIO_2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0xe7
-#define RADIO_2057_IPA2G_IMAIN_CORE1 0xe8
-#define RADIO_2057_IPA2G_CASCONV_CORE1 0xe9
-#define RADIO_2057_IPA2G_CASCOFFV_CORE1 0xea
-#define RADIO_2057_IPA2G_BIAS_FILTER_CORE1 0xeb
-#define RADIO_2057_TX5G_PKDET_CORE1 0xee
-#define RADIO_2057_PGA_PTAT_TXGM5G_PU_CORE1 0xef
-#define RADIO_2057_PAD5G_PTATS1_CORE1 0xf0
-#define RADIO_2057_PAD5G_CLASS_PTATS2_CORE1 0xf1
-#define RADIO_2057_PGA_BOOSTPTAT_IMAIN_CORE1 0xf2
-#define RADIO_2057_PAD5G_CASCV_IMAIN_CORE1 0xf3
-#define RADIO_2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0xf4
-#define RADIO_2057_PGA_BOOST_TUNE_CORE1 0xf5
-#define RADIO_2057_PGA_GAIN_CORE1 0xf6
-#define RADIO_2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0xf7
-#define RADIO_2057_TXMIX5G_BOOST_TUNE_CORE1 0xf8
-#define RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE1 0xf9
-#define RADIO_2057_IPA5G_IAUX_CORE1 0xfa
-#define RADIO_2057_IPA5G_GAIN_CORE1 0xfb
-#define RADIO_2057_TSSI5G_SPARE1_CORE1 0xfc
-#define RADIO_2057_TSSI5G_SPARE2_CORE1 0xfd
-#define RADIO_2057_IPA5G_CASCOFFV_PU_CORE1 0xfe
-#define RADIO_2057_IPA5G_PTAT_CORE1 0xff
-#define RADIO_2057_IPA5G_IMAIN_CORE1 0x100
-#define RADIO_2057_IPA5G_CASCONV_CORE1 0x101
-#define RADIO_2057_IPA5G_BIAS_FILTER_CORE1 0x102
-#define RADIO_2057_PAD_BIAS_FILTER_BWS_CORE1 0x105
-#define RADIO_2057_TR2G_CONFIG1_CORE1_NU 0x106
-#define RADIO_2057_TR2G_CONFIG2_CORE1_NU 0x107
-#define RADIO_2057_LNA5G_RFEN_CORE1 0x108
-#define RADIO_2057_TR5G_CONFIG2_CORE1_NU 0x109
-#define RADIO_2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a
-#define RADIO_2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b
-#define RADIO_2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c
-#define RADIO_2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d
-#define RADIO_2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e
-#define RADIO_2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f
-#define RADIO_2057_LNA2_IAUX_PTAT_CORE1 0x110
-#define RADIO_2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111
-#define RADIO_2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112
-#define RADIO_2057_RXRFBIAS_BANDSEL_CORE1 0x113
-#define RADIO_2057_TIA_CONFIG_CORE1 0x114
-#define RADIO_2057_TIA_IQGAIN_CORE1 0x115
-#define RADIO_2057_TIA_IBIAS2_CORE1 0x116
-#define RADIO_2057_TIA_IBIAS1_CORE1 0x117
-#define RADIO_2057_TIA_SPARE_Q_CORE1 0x118
-#define RADIO_2057_TIA_SPARE_I_CORE1 0x119
-#define RADIO_2057_RXMIX2G_PUS_CORE1 0x11a
-#define RADIO_2057_RXMIX2G_VCMREFS_CORE1 0x11b
-#define RADIO_2057_RXMIX2G_LODC_QI_CORE1 0x11c
-#define RADIO_2057_W12G_BW_LNA2G_PUS_CORE1 0x11d
-#define RADIO_2057_LNA2G_GAIN_CORE1 0x11e
-#define RADIO_2057_LNA2G_TUNE_CORE1 0x11f
-#define RADIO_2057_RXMIX5G_PUS_CORE1 0x120
-#define RADIO_2057_RXMIX5G_VCMREFS_CORE1 0x121
-#define RADIO_2057_RXMIX5G_LODC_QI_CORE1 0x122
-#define RADIO_2057_W15G_BW_LNA5G_PUS_CORE1 0x123
-#define RADIO_2057_LNA5G_GAIN_CORE1 0x124
-#define RADIO_2057_LNA5G_TUNE_CORE1 0x125
-#define RADIO_2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126
-#define RADIO_2057_RXBB_BIAS_MASTER_CORE1 0x127
-#define RADIO_2057_RXBB_VGABUF_IDACS_CORE1 0x128
-#define RADIO_2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129
-#define RADIO_2057_TXBUF_VINCM_CORE1 0x12a
-#define RADIO_2057_TXBUF_IDACS_CORE1 0x12b
-#define RADIO_2057_LPF_RESP_RXBUF_BW_CORE1 0x12c
-#define RADIO_2057_RXBB_CC_CORE1 0x12d
-#define RADIO_2057_RXBB_SPARE3_CORE1 0x12e
-#define RADIO_2057_RXBB_RCCAL_HPC_CORE1 0x12f
-#define RADIO_2057_LPF_IDACS_CORE1 0x130
-#define RADIO_2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131
-#define RADIO_2057_TXBUF_GAIN_CORE1 0x132
-#define RADIO_2057_AFELOOPBACK_AACI_RESP_CORE1 0x133
-#define RADIO_2057_RXBUF_DEGEN_CORE1 0x134
-#define RADIO_2057_RXBB_SPARE2_CORE1 0x135
-#define RADIO_2057_RXBB_SPARE1_CORE1 0x136
-#define RADIO_2057_RSSI_MASTER_CORE1 0x137
-#define RADIO_2057_W2_MASTER_CORE1 0x138
-#define RADIO_2057_NB_MASTER_CORE1 0x139
-#define RADIO_2057_W2_IDACS0_Q_CORE1 0x13a
-#define RADIO_2057_W2_IDACS1_Q_CORE1 0x13b
-#define RADIO_2057_W2_IDACS0_I_CORE1 0x13c
-#define RADIO_2057_W2_IDACS1_I_CORE1 0x13d
-#define RADIO_2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e
-#define RADIO_2057_NB_IDACS_Q_CORE1 0x13f
-#define RADIO_2057_NB_IDACS_I_CORE1 0x140
-#define RADIO_2057_BACKUP4_CORE1 0x146
-#define RADIO_2057_BACKUP3_CORE1 0x147
-#define RADIO_2057_BACKUP2_CORE1 0x148
-#define RADIO_2057_BACKUP1_CORE1 0x149
-#define RADIO_2057_SPARE16_CORE1 0x14a
-#define RADIO_2057_SPARE15_CORE1 0x14b
-#define RADIO_2057_SPARE14_CORE1 0x14c
-#define RADIO_2057_SPARE13_CORE1 0x14d
-#define RADIO_2057_SPARE12_CORE1 0x14e
-#define RADIO_2057_SPARE11_CORE1 0x14f
-#define RADIO_2057_TX2G_BIAS_RESETS_CORE1 0x150
-#define RADIO_2057_TX5G_BIAS_RESETS_CORE1 0x151
-#define RADIO_2057_SPARE8_CORE1 0x152
-#define RADIO_2057_SPARE7_CORE1 0x153
-#define RADIO_2057_BUFS_MISC_LPFBW_CORE1 0x154
-#define RADIO_2057_TXLPF_RCCAL_CORE1 0x155
-#define RADIO_2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156
-#define RADIO_2057_LPF_GAIN_CORE1 0x157
-#define RADIO_2057_DACBUF_IDACS_BW_CORE1 0x158
-#define RADIO_2057_DACBUF_VINCM_CORE1 0x159
-#define RADIO_2057_RCCAL_START_R1_Q1_P1 0x15a
-#define RADIO_2057_RCCAL_X1 0x15b
-#define RADIO_2057_RCCAL_TRC0 0x15c
-#define RADIO_2057_RCCAL_TRC1 0x15d
-#define RADIO_2057_RCCAL_DONE_OSCCAP 0x15e
-#define RADIO_2057_RCCAL_N0_0 0x15f
-#define RADIO_2057_RCCAL_N0_1 0x160
-#define RADIO_2057_RCCAL_N1_0 0x161
-#define RADIO_2057_RCCAL_N1_1 0x162
-#define RADIO_2057_RCAL_STATUS 0x163
-#define RADIO_2057_XTALPUOVR_PINCTRL 0x164
-#define RADIO_2057_OVR_REG0 0x165
-#define RADIO_2057_OVR_REG1 0x166
-#define RADIO_2057_OVR_REG2 0x167
-#define RADIO_2057_OVR_REG3 0x168
-#define RADIO_2057_OVR_REG4 0x169
-#define RADIO_2057_RCCAL_SCAP_VAL 0x16a
-#define RADIO_2057_RCCAL_BCAP_VAL 0x16b
-#define RADIO_2057_RCCAL_HPC_VAL 0x16c
-#define RADIO_2057_RCCAL_OVERRIDES 0x16d
-#define RADIO_2057_TX0_IQCAL_GAIN_BW 0x170
-#define RADIO_2057_TX0_LOFT_FINE_I 0x171
-#define RADIO_2057_TX0_LOFT_FINE_Q 0x172
-#define RADIO_2057_TX0_LOFT_COARSE_I 0x173
-#define RADIO_2057_TX0_LOFT_COARSE_Q 0x174
-#define RADIO_2057_TX0_TX_SSI_MASTER 0x175
-#define RADIO_2057_TX0_IQCAL_VCM_HG 0x176
-#define RADIO_2057_TX0_IQCAL_IDAC 0x177
-#define RADIO_2057_TX0_TSSI_VCM 0x178
-#define RADIO_2057_TX0_TX_SSI_MUX 0x179
-#define RADIO_2057_TX0_TSSIA 0x17a
-#define RADIO_2057_TX0_TSSIG 0x17b
-#define RADIO_2057_TX0_TSSI_MISC1 0x17c
-#define RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d
-#define RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e
-#define RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f
-#define RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180
-#define RADIO_2057_TX1_IQCAL_GAIN_BW 0x190
-#define RADIO_2057_TX1_LOFT_FINE_I 0x191
-#define RADIO_2057_TX1_LOFT_FINE_Q 0x192
-#define RADIO_2057_TX1_LOFT_COARSE_I 0x193
-#define RADIO_2057_TX1_LOFT_COARSE_Q 0x194
-#define RADIO_2057_TX1_TX_SSI_MASTER 0x195
-#define RADIO_2057_TX1_IQCAL_VCM_HG 0x196
-#define RADIO_2057_TX1_IQCAL_IDAC 0x197
-#define RADIO_2057_TX1_TSSI_VCM 0x198
-#define RADIO_2057_TX1_TX_SSI_MUX 0x199
-#define RADIO_2057_TX1_TSSIA 0x19a
-#define RADIO_2057_TX1_TSSIG 0x19b
-#define RADIO_2057_TX1_TSSI_MISC1 0x19c
-#define RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d
-#define RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e
-#define RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f
-#define RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0
-#define RADIO_2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1
-#define RADIO_2057_AFE_SET_VCM_I_CORE0 0x1a2
-#define RADIO_2057_AFE_SET_VCM_Q_CORE0 0x1a3
-#define RADIO_2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4
-#define RADIO_2057_AFE_STATUS_VCM_I_CORE0 0x1a5
-#define RADIO_2057_AFE_STATUS_VCM_Q_CORE0 0x1a6
-#define RADIO_2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7
-#define RADIO_2057_AFE_SET_VCM_I_CORE1 0x1a8
-#define RADIO_2057_AFE_SET_VCM_Q_CORE1 0x1a9
-#define RADIO_2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa
-#define RADIO_2057_AFE_STATUS_VCM_I_CORE1 0x1ab
-#define RADIO_2057_AFE_STATUS_VCM_Q_CORE1 0x1ac
-
-#define RADIO_2057v7_DACBUF_VINCM_CORE0 0x1ad
-#define RADIO_2057v7_RCCAL_MASTER 0x1ae
-#define RADIO_2057v7_TR2G_CONFIG3_CORE0_NU 0x1af
-#define RADIO_2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0
-#define RADIO_2057v7_LOGEN_PUS1 0x1b1
-#define RADIO_2057v7_OVR_REG5 0x1b2
-#define RADIO_2057v7_OVR_REG6 0x1b3
-#define RADIO_2057v7_OVR_REG7 0x1b4
-#define RADIO_2057v7_OVR_REG8 0x1b5
-#define RADIO_2057v7_OVR_REG9 0x1b6
-#define RADIO_2057v7_OVR_REG10 0x1b7
-#define RADIO_2057v7_OVR_REG11 0x1b8
-#define RADIO_2057v7_OVR_REG12 0x1b9
-#define RADIO_2057v7_OVR_REG13 0x1ba
-#define RADIO_2057v7_OVR_REG14 0x1bb
-#define RADIO_2057v7_OVR_REG15 0x1bc
-#define RADIO_2057v7_OVR_REG16 0x1bd
-#define RADIO_2057v7_OVR_REG1 0x1be
-#define RADIO_2057v7_OVR_REG18 0x1bf
-#define RADIO_2057v7_OVR_REG19 0x1c0
-#define RADIO_2057v7_OVR_REG20 0x1c1
-#define RADIO_2057v7_OVR_REG21 0x1c2
-#define RADIO_2057v7_OVR_REG2 0x1c3
-#define RADIO_2057v7_OVR_REG23 0x1c4
-#define RADIO_2057v7_OVR_REG24 0x1c5
-#define RADIO_2057v7_OVR_REG25 0x1c6
-#define RADIO_2057v7_OVR_REG26 0x1c7
-#define RADIO_2057v7_OVR_REG27 0x1c8
-#define RADIO_2057v7_OVR_REG28 0x1c9
-#define RADIO_2057v7_IQTEST_SEL_PU2 0x1ca
-
-#define RADIO_2057_VCM_MASK 0x7
-
-#endif /* _BRCM_PHY_RADIO_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#define NPHY_TBL_ID_GAIN1 0
-#define NPHY_TBL_ID_GAIN2 1
-#define NPHY_TBL_ID_GAINBITS1 2
-#define NPHY_TBL_ID_GAINBITS2 3
-#define NPHY_TBL_ID_GAINLIMIT 4
-#define NPHY_TBL_ID_WRSSIGainLimit 5
-#define NPHY_TBL_ID_RFSEQ 7
-#define NPHY_TBL_ID_AFECTRL 8
-#define NPHY_TBL_ID_ANTSWCTRLLUT 9
-#define NPHY_TBL_ID_IQLOCAL 15
-#define NPHY_TBL_ID_NOISEVAR 16
-#define NPHY_TBL_ID_SAMPLEPLAY 17
-#define NPHY_TBL_ID_CORE1TXPWRCTL 26
-#define NPHY_TBL_ID_CORE2TXPWRCTL 27
-#define NPHY_TBL_ID_CMPMETRICDATAWEIGHTTBL 30
-
-#define NPHY_TBL_ID_EPSILONTBL0 31
-#define NPHY_TBL_ID_SCALARTBL0 32
-#define NPHY_TBL_ID_EPSILONTBL1 33
-#define NPHY_TBL_ID_SCALARTBL1 34
-
-#define NPHY_TO_BPHY_OFF 0xc00
-
-#define NPHY_BandControl_currentBand 0x0001
-#define RFCC_CHIP0_PU 0x0400
-#define RFCC_POR_FORCE 0x0040
-#define RFCC_OE_POR_FORCE 0x0080
-#define NPHY_RfctrlIntc_override_OFF 0
-#define NPHY_RfctrlIntc_override_TRSW 1
-#define NPHY_RfctrlIntc_override_PA 2
-#define NPHY_RfctrlIntc_override_EXT_LNA_PU 3
-#define NPHY_RfctrlIntc_override_EXT_LNA_GAIN 4
-#define RIFS_ENABLE 0x80
-#define BPHY_BAND_SEL_UP20 0x10
-#define NPHY_MLenable 0x02
-
-#define NPHY_RfseqMode_CoreActv_override 0x0001
-#define NPHY_RfseqMode_Trigger_override 0x0002
-#define NPHY_RfseqCoreActv_TxRxChain0 (0x11)
-#define NPHY_RfseqCoreActv_TxRxChain1 (0x22)
-
-#define NPHY_RfseqTrigger_rx2tx 0x0001
-#define NPHY_RfseqTrigger_tx2rx 0x0002
-#define NPHY_RfseqTrigger_updategainh 0x0004
-#define NPHY_RfseqTrigger_updategainl 0x0008
-#define NPHY_RfseqTrigger_updategainu 0x0010
-#define NPHY_RfseqTrigger_reset2rx 0x0020
-#define NPHY_RfseqStatus_rx2tx 0x0001
-#define NPHY_RfseqStatus_tx2rx 0x0002
-#define NPHY_RfseqStatus_updategainh 0x0004
-#define NPHY_RfseqStatus_updategainl 0x0008
-#define NPHY_RfseqStatus_updategainu 0x0010
-#define NPHY_RfseqStatus_reset2rx 0x0020
-#define NPHY_ClassifierCtrl_cck_en 0x1
-#define NPHY_ClassifierCtrl_ofdm_en 0x2
-#define NPHY_ClassifierCtrl_waited_en 0x4
-#define NPHY_IQFlip_ADC1 0x0001
-#define NPHY_IQFlip_ADC2 0x0010
-#define NPHY_sampleCmd_STOP 0x0002
-
-#define RX_GF_OR_MM 0x0004
-#define RX_GF_MM_AUTO 0x0100
-
-#define NPHY_iqloCalCmdGctl_IQLO_CAL_EN 0x8000
-
-#define NPHY_IqestCmd_iqstart 0x1
-#define NPHY_IqestCmd_iqMode 0x2
-
-#define NPHY_TxPwrCtrlCmd_pwrIndex_init 0x40
-#define NPHY_TxPwrCtrlCmd_pwrIndex_init_rev7 0x19
-
-#define PRIM_SEL_UP20 0x8000
-
-#define NPHY_RFSEQ_RX2TX 0x0
-#define NPHY_RFSEQ_TX2RX 0x1
-#define NPHY_RFSEQ_RESET2RX 0x2
-#define NPHY_RFSEQ_UPDATEGAINH 0x3
-#define NPHY_RFSEQ_UPDATEGAINL 0x4
-#define NPHY_RFSEQ_UPDATEGAINU 0x5
-
-#define NPHY_RFSEQ_CMD_NOP 0x0
-#define NPHY_RFSEQ_CMD_RXG_FBW 0x1
-#define NPHY_RFSEQ_CMD_TR_SWITCH 0x2
-#define NPHY_RFSEQ_CMD_EXT_PA 0x3
-#define NPHY_RFSEQ_CMD_RXPD_TXPD 0x4
-#define NPHY_RFSEQ_CMD_TX_GAIN 0x5
-#define NPHY_RFSEQ_CMD_RX_GAIN 0x6
-#define NPHY_RFSEQ_CMD_SET_HPF_BW 0x7
-#define NPHY_RFSEQ_CMD_CLR_HIQ_DIS 0x8
-#define NPHY_RFSEQ_CMD_END 0xf
-
-#define NPHY_REV3_RFSEQ_CMD_NOP 0x0
-#define NPHY_REV3_RFSEQ_CMD_RXG_FBW 0x1
-#define NPHY_REV3_RFSEQ_CMD_TR_SWITCH 0x2
-#define NPHY_REV3_RFSEQ_CMD_INT_PA_PU 0x3
-#define NPHY_REV3_RFSEQ_CMD_EXT_PA 0x4
-#define NPHY_REV3_RFSEQ_CMD_RXPD_TXPD 0x5
-#define NPHY_REV3_RFSEQ_CMD_TX_GAIN 0x6
-#define NPHY_REV3_RFSEQ_CMD_RX_GAIN 0x7
-#define NPHY_REV3_RFSEQ_CMD_CLR_HIQ_DIS 0x8
-#define NPHY_REV3_RFSEQ_CMD_SET_HPF_H_HPC 0x9
-#define NPHY_REV3_RFSEQ_CMD_SET_LPF_H_HPC 0xa
-#define NPHY_REV3_RFSEQ_CMD_SET_HPF_M_HPC 0xb
-#define NPHY_REV3_RFSEQ_CMD_SET_LPF_M_HPC 0xc
-#define NPHY_REV3_RFSEQ_CMD_SET_HPF_L_HPC 0xd
-#define NPHY_REV3_RFSEQ_CMD_SET_LPF_L_HPC 0xe
-#define NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS 0xf
-#define NPHY_REV3_RFSEQ_CMD_END 0x1f
-
-#define NPHY_RSSI_SEL_W1 0x0
-#define NPHY_RSSI_SEL_W2 0x1
-#define NPHY_RSSI_SEL_NB 0x2
-#define NPHY_RSSI_SEL_IQ 0x3
-#define NPHY_RSSI_SEL_TSSI_2G 0x4
-#define NPHY_RSSI_SEL_TSSI_5G 0x5
-#define NPHY_RSSI_SEL_TBD 0x6
-
-#define NPHY_RAIL_I 0x0
-#define NPHY_RAIL_Q 0x1
-
-#define NPHY_FORCESIG_DECODEGATEDCLKS 0x8
-
-#define NPHY_REV7_RfctrlOverride_cmd_rxrf_pu 0x0
-#define NPHY_REV7_RfctrlOverride_cmd_rx_pu 0x1
-#define NPHY_REV7_RfctrlOverride_cmd_tx_pu 0x2
-#define NPHY_REV7_RfctrlOverride_cmd_rxgain 0x3
-#define NPHY_REV7_RfctrlOverride_cmd_txgain 0x4
-
-#define NPHY_REV7_RXGAINCODE_RFMXGAIN_MASK 0x000ff
-#define NPHY_REV7_RXGAINCODE_LPFGAIN_MASK 0x0ff00
-#define NPHY_REV7_RXGAINCODE_DVGAGAIN_MASK 0xf0000
-
-#define NPHY_REV7_TXGAINCODE_TGAIN_MASK 0x7fff
-#define NPHY_REV7_TXGAINCODE_LPFGAIN_MASK 0x8000
-#define NPHY_REV7_TXGAINCODE_BIQ0GAIN_SHIFT 14
-
-#define NPHY_REV7_RFCTRLOVERRIDE_ID0 0x0
-#define NPHY_REV7_RFCTRLOVERRIDE_ID1 0x1
-#define NPHY_REV7_RFCTRLOVERRIDE_ID2 0x2
-
-#define NPHY_IqestIqAccLo(core) ((core == 0) ? 0x12c : 0x134)
-
-#define NPHY_IqestIqAccHi(core) ((core == 0) ? 0x12d : 0x135)
-
-#define NPHY_IqestipwrAccLo(core) ((core == 0) ? 0x12e : 0x136)
-
-#define NPHY_IqestipwrAccHi(core) ((core == 0) ? 0x12f : 0x137)
-
-#define NPHY_IqestqpwrAccLo(core) ((core == 0) ? 0x130 : 0x138)
-
-#define NPHY_IqestqpwrAccHi(core) ((core == 0) ? 0x131 : 0x139)
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/types.h>
-#include "bcmdma.h"
-#include <wlc_phy_int.h>
-#include <wlc_phytbl_lcn.h>
-
-const u32 dot11lcn_gain_tbl_rev0[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000004,
- 0x00000000,
- 0x00000004,
- 0x00000008,
- 0x00000001,
- 0x00000005,
- 0x00000009,
- 0x0000000d,
- 0x0000004d,
- 0x0000008d,
- 0x0000000d,
- 0x0000004d,
- 0x0000008d,
- 0x000000cd,
- 0x0000004f,
- 0x0000008f,
- 0x000000cf,
- 0x000000d3,
- 0x00000113,
- 0x00000513,
- 0x00000913,
- 0x00000953,
- 0x00000d53,
- 0x00001153,
- 0x00001193,
- 0x00005193,
- 0x00009193,
- 0x0000d193,
- 0x00011193,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000004,
- 0x00000000,
- 0x00000004,
- 0x00000008,
- 0x00000001,
- 0x00000005,
- 0x00000009,
- 0x0000000d,
- 0x0000004d,
- 0x0000008d,
- 0x0000000d,
- 0x0000004d,
- 0x0000008d,
- 0x000000cd,
- 0x0000004f,
- 0x0000008f,
- 0x000000cf,
- 0x000000d3,
- 0x00000113,
- 0x00000513,
- 0x00000913,
- 0x00000953,
- 0x00000d53,
- 0x00001153,
- 0x00005153,
- 0x00009153,
- 0x0000d153,
- 0x00011153,
- 0x00015153,
- 0x00019153,
- 0x0001d153,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 dot11lcn_gain_tbl_rev1[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000008,
- 0x00000004,
- 0x00000008,
- 0x00000001,
- 0x00000005,
- 0x00000009,
- 0x0000000D,
- 0x00000011,
- 0x00000051,
- 0x00000091,
- 0x00000011,
- 0x00000051,
- 0x00000091,
- 0x000000d1,
- 0x00000053,
- 0x00000093,
- 0x000000d3,
- 0x000000d7,
- 0x00000117,
- 0x00000517,
- 0x00000917,
- 0x00000957,
- 0x00000d57,
- 0x00001157,
- 0x00001197,
- 0x00005197,
- 0x00009197,
- 0x0000d197,
- 0x00011197,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000008,
- 0x00000004,
- 0x00000008,
- 0x00000001,
- 0x00000005,
- 0x00000009,
- 0x0000000D,
- 0x00000011,
- 0x00000051,
- 0x00000091,
- 0x00000011,
- 0x00000051,
- 0x00000091,
- 0x000000d1,
- 0x00000053,
- 0x00000093,
- 0x000000d3,
- 0x000000d7,
- 0x00000117,
- 0x00000517,
- 0x00000917,
- 0x00000957,
- 0x00000d57,
- 0x00001157,
- 0x00005157,
- 0x00009157,
- 0x0000d157,
- 0x00011157,
- 0x00015157,
- 0x00019157,
- 0x0001d157,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u16 dot11lcn_aux_gain_idx_tbl_rev0[] = {
- 0x0401,
- 0x0402,
- 0x0403,
- 0x0404,
- 0x0405,
- 0x0406,
- 0x0407,
- 0x0408,
- 0x0409,
- 0x040a,
- 0x058b,
- 0x058c,
- 0x058d,
- 0x058e,
- 0x058f,
- 0x0090,
- 0x0091,
- 0x0092,
- 0x0193,
- 0x0194,
- 0x0195,
- 0x0196,
- 0x0197,
- 0x0198,
- 0x0199,
- 0x019a,
- 0x019b,
- 0x019c,
- 0x019d,
- 0x019e,
- 0x019f,
- 0x01a0,
- 0x01a1,
- 0x01a2,
- 0x01a3,
- 0x01a4,
- 0x01a5,
- 0x0000,
-};
-
-const u32 dot11lcn_gain_idx_tbl_rev0[] = {
- 0x00000000,
- 0x00000000,
- 0x10000000,
- 0x00000000,
- 0x20000000,
- 0x00000000,
- 0x30000000,
- 0x00000000,
- 0x40000000,
- 0x00000000,
- 0x50000000,
- 0x00000000,
- 0x60000000,
- 0x00000000,
- 0x70000000,
- 0x00000000,
- 0x80000000,
- 0x00000000,
- 0x90000000,
- 0x00000008,
- 0xa0000000,
- 0x00000008,
- 0xb0000000,
- 0x00000008,
- 0xc0000000,
- 0x00000008,
- 0xd0000000,
- 0x00000008,
- 0xe0000000,
- 0x00000008,
- 0xf0000000,
- 0x00000008,
- 0x00000000,
- 0x00000009,
- 0x10000000,
- 0x00000009,
- 0x20000000,
- 0x00000019,
- 0x30000000,
- 0x00000019,
- 0x40000000,
- 0x00000019,
- 0x50000000,
- 0x00000019,
- 0x60000000,
- 0x00000019,
- 0x70000000,
- 0x00000019,
- 0x80000000,
- 0x00000019,
- 0x90000000,
- 0x00000019,
- 0xa0000000,
- 0x00000019,
- 0xb0000000,
- 0x00000019,
- 0xc0000000,
- 0x00000019,
- 0xd0000000,
- 0x00000019,
- 0xe0000000,
- 0x00000019,
- 0xf0000000,
- 0x00000019,
- 0x00000000,
- 0x0000001a,
- 0x10000000,
- 0x0000001a,
- 0x20000000,
- 0x0000001a,
- 0x30000000,
- 0x0000001a,
- 0x40000000,
- 0x0000001a,
- 0x50000000,
- 0x00000002,
- 0x60000000,
- 0x00000002,
- 0x70000000,
- 0x00000002,
- 0x80000000,
- 0x00000002,
- 0x90000000,
- 0x00000002,
- 0xa0000000,
- 0x00000002,
- 0xb0000000,
- 0x00000002,
- 0xc0000000,
- 0x0000000a,
- 0xd0000000,
- 0x0000000a,
- 0xe0000000,
- 0x0000000a,
- 0xf0000000,
- 0x0000000a,
- 0x00000000,
- 0x0000000b,
- 0x10000000,
- 0x0000000b,
- 0x20000000,
- 0x0000000b,
- 0x30000000,
- 0x0000000b,
- 0x40000000,
- 0x0000000b,
- 0x50000000,
- 0x0000001b,
- 0x60000000,
- 0x0000001b,
- 0x70000000,
- 0x0000001b,
- 0x80000000,
- 0x0000001b,
- 0x90000000,
- 0x0000001b,
- 0xa0000000,
- 0x0000001b,
- 0xb0000000,
- 0x0000001b,
- 0xc0000000,
- 0x0000001b,
- 0xd0000000,
- 0x0000001b,
- 0xe0000000,
- 0x0000001b,
- 0xf0000000,
- 0x0000001b,
- 0x00000000,
- 0x0000001c,
- 0x10000000,
- 0x0000001c,
- 0x20000000,
- 0x0000001c,
- 0x30000000,
- 0x0000001c,
- 0x40000000,
- 0x0000001c,
- 0x50000000,
- 0x0000001c,
- 0x60000000,
- 0x0000001c,
- 0x70000000,
- 0x0000001c,
- 0x80000000,
- 0x0000001c,
- 0x90000000,
- 0x0000001c,
-};
-
-const u16 dot11lcn_aux_gain_idx_tbl_2G[] = {
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0001,
- 0x0080,
- 0x0081,
- 0x0100,
- 0x0101,
- 0x0180,
- 0x0181,
- 0x0182,
- 0x0183,
- 0x0184,
- 0x0185,
- 0x0186,
- 0x0187,
- 0x0188,
- 0x0285,
- 0x0289,
- 0x028a,
- 0x028b,
- 0x028c,
- 0x028d,
- 0x028e,
- 0x028f,
- 0x0290,
- 0x0291,
- 0x0292,
- 0x0293,
- 0x0294,
- 0x0295,
- 0x0296,
- 0x0297,
- 0x0298,
- 0x0299,
- 0x029a,
- 0x0000
-};
-
-const u8 dot11lcn_gain_val_tbl_2G[] = {
- 0xfc,
- 0x02,
- 0x08,
- 0x0e,
- 0x13,
- 0x1b,
- 0xfc,
- 0x02,
- 0x08,
- 0x0e,
- 0x13,
- 0x1b,
- 0xfc,
- 0x00,
- 0x0c,
- 0x03,
- 0xeb,
- 0xfe,
- 0x07,
- 0x0b,
- 0x0f,
- 0xfb,
- 0xfe,
- 0x01,
- 0x05,
- 0x08,
- 0x0b,
- 0x0e,
- 0x11,
- 0x14,
- 0x17,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x15,
- 0x18,
- 0x1b,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-
-const u32 dot11lcn_gain_idx_tbl_2G[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x10000000,
- 0x00000000,
- 0x00000000,
- 0x00000008,
- 0x10000000,
- 0x00000008,
- 0x00000000,
- 0x00000010,
- 0x10000000,
- 0x00000010,
- 0x00000000,
- 0x00000018,
- 0x10000000,
- 0x00000018,
- 0x20000000,
- 0x00000018,
- 0x30000000,
- 0x00000018,
- 0x40000000,
- 0x00000018,
- 0x50000000,
- 0x00000018,
- 0x60000000,
- 0x00000018,
- 0x70000000,
- 0x00000018,
- 0x80000000,
- 0x00000018,
- 0x50000000,
- 0x00000028,
- 0x90000000,
- 0x00000028,
- 0xa0000000,
- 0x00000028,
- 0xb0000000,
- 0x00000028,
- 0xc0000000,
- 0x00000028,
- 0xd0000000,
- 0x00000028,
- 0xe0000000,
- 0x00000028,
- 0xf0000000,
- 0x00000028,
- 0x00000000,
- 0x00000029,
- 0x10000000,
- 0x00000029,
- 0x20000000,
- 0x00000029,
- 0x30000000,
- 0x00000029,
- 0x40000000,
- 0x00000029,
- 0x50000000,
- 0x00000029,
- 0x60000000,
- 0x00000029,
- 0x70000000,
- 0x00000029,
- 0x80000000,
- 0x00000029,
- 0x90000000,
- 0x00000029,
- 0xa0000000,
- 0x00000029,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x10000000,
- 0x00000000,
- 0x00000000,
- 0x00000008,
- 0x10000000,
- 0x00000008,
- 0x00000000,
- 0x00000010,
- 0x10000000,
- 0x00000010,
- 0x00000000,
- 0x00000018,
- 0x10000000,
- 0x00000018,
- 0x20000000,
- 0x00000018,
- 0x30000000,
- 0x00000018,
- 0x40000000,
- 0x00000018,
- 0x50000000,
- 0x00000018,
- 0x60000000,
- 0x00000018,
- 0x70000000,
- 0x00000018,
- 0x80000000,
- 0x00000018,
- 0x50000000,
- 0x00000028,
- 0x90000000,
- 0x00000028,
- 0xa0000000,
- 0x00000028,
- 0xb0000000,
- 0x00000028,
- 0xc0000000,
- 0x00000028,
- 0xd0000000,
- 0x00000028,
- 0xe0000000,
- 0x00000028,
- 0xf0000000,
- 0x00000028,
- 0x00000000,
- 0x00000029,
- 0x10000000,
- 0x00000029,
- 0x20000000,
- 0x00000029,
- 0x30000000,
- 0x00000029,
- 0x40000000,
- 0x00000029,
- 0x50000000,
- 0x00000029,
- 0x60000000,
- 0x00000029,
- 0x70000000,
- 0x00000029,
- 0x80000000,
- 0x00000029,
- 0x90000000,
- 0x00000029,
- 0xa0000000,
- 0x00000029,
- 0xb0000000,
- 0x00000029,
- 0xc0000000,
- 0x00000029,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000
-};
-
-const u32 dot11lcn_gain_tbl_2G[] = {
- 0x00000000,
- 0x00000004,
- 0x00000008,
- 0x00000001,
- 0x00000005,
- 0x00000009,
- 0x0000000d,
- 0x0000004d,
- 0x0000008d,
- 0x00000049,
- 0x00000089,
- 0x000000c9,
- 0x0000004b,
- 0x0000008b,
- 0x000000cb,
- 0x000000cf,
- 0x0000010f,
- 0x0000050f,
- 0x0000090f,
- 0x0000094f,
- 0x00000d4f,
- 0x0000114f,
- 0x0000118f,
- 0x0000518f,
- 0x0000918f,
- 0x0000d18f,
- 0x0001118f,
- 0x0001518f,
- 0x0001918f,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000
-};
-
-const u32 dot11lcn_gain_tbl_extlna_2G[] = {
- 0x00000000,
- 0x00000004,
- 0x00000008,
- 0x00000001,
- 0x00000005,
- 0x00000009,
- 0x0000000d,
- 0x00000003,
- 0x00000007,
- 0x0000000b,
- 0x0000000f,
- 0x0000004f,
- 0x0000008f,
- 0x000000cf,
- 0x0000010f,
- 0x0000014f,
- 0x0000018f,
- 0x0000058f,
- 0x0000098f,
- 0x00000d8f,
- 0x00008000,
- 0x00008004,
- 0x00008008,
- 0x00008001,
- 0x00008005,
- 0x00008009,
- 0x0000800d,
- 0x00008003,
- 0x00008007,
- 0x0000800b,
- 0x0000800f,
- 0x0000804f,
- 0x0000808f,
- 0x000080cf,
- 0x0000810f,
- 0x0000814f,
- 0x0000818f,
- 0x0000858f,
- 0x0000898f,
- 0x00008d8f,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000
-};
-
-const u16 dot11lcn_aux_gain_idx_tbl_extlna_2G[] = {
- 0x0400,
- 0x0400,
- 0x0400,
- 0x0400,
- 0x0400,
- 0x0400,
- 0x0400,
- 0x0400,
- 0x0400,
- 0x0401,
- 0x0402,
- 0x0403,
- 0x0404,
- 0x0483,
- 0x0484,
- 0x0485,
- 0x0486,
- 0x0583,
- 0x0584,
- 0x0585,
- 0x0587,
- 0x0588,
- 0x0589,
- 0x058a,
- 0x0687,
- 0x0688,
- 0x0689,
- 0x068a,
- 0x068b,
- 0x068c,
- 0x068d,
- 0x068e,
- 0x068f,
- 0x0690,
- 0x0691,
- 0x0692,
- 0x0693,
- 0x0000
-};
-
-const u8 dot11lcn_gain_val_tbl_extlna_2G[] = {
- 0xfc,
- 0x02,
- 0x08,
- 0x0e,
- 0x13,
- 0x1b,
- 0xfc,
- 0x02,
- 0x08,
- 0x0e,
- 0x13,
- 0x1b,
- 0xfc,
- 0x00,
- 0x0f,
- 0x03,
- 0xeb,
- 0xfe,
- 0x07,
- 0x0b,
- 0x0f,
- 0xfb,
- 0xfe,
- 0x01,
- 0x05,
- 0x08,
- 0x0b,
- 0x0e,
- 0x11,
- 0x14,
- 0x17,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x15,
- 0x18,
- 0x1b,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-
-const u32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
- 0x00000000,
- 0x00000040,
- 0x00000000,
- 0x00000040,
- 0x00000000,
- 0x00000040,
- 0x00000000,
- 0x00000040,
- 0x00000000,
- 0x00000040,
- 0x00000000,
- 0x00000040,
- 0x00000000,
- 0x00000040,
- 0x00000000,
- 0x00000040,
- 0x00000000,
- 0x00000040,
- 0x10000000,
- 0x00000040,
- 0x20000000,
- 0x00000040,
- 0x30000000,
- 0x00000040,
- 0x40000000,
- 0x00000040,
- 0x30000000,
- 0x00000048,
- 0x40000000,
- 0x00000048,
- 0x50000000,
- 0x00000048,
- 0x60000000,
- 0x00000048,
- 0x30000000,
- 0x00000058,
- 0x40000000,
- 0x00000058,
- 0x50000000,
- 0x00000058,
- 0x70000000,
- 0x00000058,
- 0x80000000,
- 0x00000058,
- 0x90000000,
- 0x00000058,
- 0xa0000000,
- 0x00000058,
- 0x70000000,
- 0x00000068,
- 0x80000000,
- 0x00000068,
- 0x90000000,
- 0x00000068,
- 0xa0000000,
- 0x00000068,
- 0xb0000000,
- 0x00000068,
- 0xc0000000,
- 0x00000068,
- 0xd0000000,
- 0x00000068,
- 0xe0000000,
- 0x00000068,
- 0xf0000000,
- 0x00000068,
- 0x00000000,
- 0x00000069,
- 0x10000000,
- 0x00000069,
- 0x20000000,
- 0x00000069,
- 0x30000000,
- 0x00000069,
- 0x40000000,
- 0x00000041,
- 0x40000000,
- 0x00000041,
- 0x40000000,
- 0x00000041,
- 0x40000000,
- 0x00000041,
- 0x40000000,
- 0x00000041,
- 0x40000000,
- 0x00000041,
- 0x40000000,
- 0x00000041,
- 0x40000000,
- 0x00000041,
- 0x40000000,
- 0x00000041,
- 0x50000000,
- 0x00000041,
- 0x60000000,
- 0x00000041,
- 0x70000000,
- 0x00000041,
- 0x80000000,
- 0x00000041,
- 0x70000000,
- 0x00000049,
- 0x80000000,
- 0x00000049,
- 0x90000000,
- 0x00000049,
- 0xa0000000,
- 0x00000049,
- 0x70000000,
- 0x00000059,
- 0x80000000,
- 0x00000059,
- 0x90000000,
- 0x00000059,
- 0xb0000000,
- 0x00000059,
- 0xc0000000,
- 0x00000059,
- 0xd0000000,
- 0x00000059,
- 0xe0000000,
- 0x00000059,
- 0xb0000000,
- 0x00000069,
- 0xc0000000,
- 0x00000069,
- 0xd0000000,
- 0x00000069,
- 0xe0000000,
- 0x00000069,
- 0xf0000000,
- 0x00000069,
- 0x00000000,
- 0x0000006a,
- 0x10000000,
- 0x0000006a,
- 0x20000000,
- 0x0000006a,
- 0x30000000,
- 0x0000006a,
- 0x40000000,
- 0x0000006a,
- 0x50000000,
- 0x0000006a,
- 0x60000000,
- 0x0000006a,
- 0x70000000,
- 0x0000006a,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000
-};
-
-const u32 dot11lcn_aux_gain_idx_tbl_5G[] = {
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0001,
- 0x0002,
- 0x0003,
- 0x0004,
- 0x0083,
- 0x0084,
- 0x0085,
- 0x0086,
- 0x0087,
- 0x0186,
- 0x0187,
- 0x0188,
- 0x0189,
- 0x018a,
- 0x018b,
- 0x018c,
- 0x018d,
- 0x018e,
- 0x018f,
- 0x0190,
- 0x0191,
- 0x0192,
- 0x0193,
- 0x0194,
- 0x0195,
- 0x0196,
- 0x0197,
- 0x0198,
- 0x0199,
- 0x019a,
- 0x019b,
- 0x019c,
- 0x019d,
- 0x0000
-};
-
-const u32 dot11lcn_gain_val_tbl_5G[] = {
- 0xf7,
- 0xfd,
- 0x00,
- 0x04,
- 0x04,
- 0x04,
- 0xf7,
- 0xfd,
- 0x00,
- 0x04,
- 0x04,
- 0x04,
- 0xf6,
- 0x00,
- 0x0c,
- 0x03,
- 0xeb,
- 0xfe,
- 0x06,
- 0x0a,
- 0x10,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x15,
- 0x18,
- 0x1b,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x15,
- 0x18,
- 0x1b,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-
-const u32 dot11lcn_gain_idx_tbl_5G[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x10000000,
- 0x00000000,
- 0x20000000,
- 0x00000000,
- 0x30000000,
- 0x00000000,
- 0x40000000,
- 0x00000000,
- 0x30000000,
- 0x00000008,
- 0x40000000,
- 0x00000008,
- 0x50000000,
- 0x00000008,
- 0x60000000,
- 0x00000008,
- 0x70000000,
- 0x00000008,
- 0x60000000,
- 0x00000018,
- 0x70000000,
- 0x00000018,
- 0x80000000,
- 0x00000018,
- 0x90000000,
- 0x00000018,
- 0xa0000000,
- 0x00000018,
- 0xb0000000,
- 0x00000018,
- 0xc0000000,
- 0x00000018,
- 0xd0000000,
- 0x00000018,
- 0xe0000000,
- 0x00000018,
- 0xf0000000,
- 0x00000018,
- 0x00000000,
- 0x00000019,
- 0x10000000,
- 0x00000019,
- 0x20000000,
- 0x00000019,
- 0x30000000,
- 0x00000019,
- 0x40000000,
- 0x00000019,
- 0x50000000,
- 0x00000019,
- 0x60000000,
- 0x00000019,
- 0x70000000,
- 0x00000019,
- 0x80000000,
- 0x00000019,
- 0x90000000,
- 0x00000019,
- 0xa0000000,
- 0x00000019,
- 0xb0000000,
- 0x00000019,
- 0xc0000000,
- 0x00000019,
- 0xd0000000,
- 0x00000019,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000
-};
-
-const u32 dot11lcn_gain_tbl_5G[] = {
- 0x00000000,
- 0x00000040,
- 0x00000080,
- 0x00000001,
- 0x00000005,
- 0x00000009,
- 0x0000000d,
- 0x00000011,
- 0x00000015,
- 0x00000055,
- 0x00000095,
- 0x00000017,
- 0x0000001b,
- 0x0000005b,
- 0x0000009b,
- 0x000000db,
- 0x0000011b,
- 0x0000015b,
- 0x0000019b,
- 0x0000059b,
- 0x0000099b,
- 0x00000d9b,
- 0x0000119b,
- 0x0000519b,
- 0x0000919b,
- 0x0000d19b,
- 0x0001119b,
- 0x0001519b,
- 0x0001919b,
- 0x0001d19b,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000
-};
-
-const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[] = {
- {&dot11lcn_gain_tbl_rev0,
- sizeof(dot11lcn_gain_tbl_rev0) / sizeof(dot11lcn_gain_tbl_rev0[0]), 18,
- 0, 32}
- ,
- {&dot11lcn_aux_gain_idx_tbl_rev0,
- sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
- sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
- ,
- {&dot11lcn_gain_idx_tbl_rev0,
- sizeof(dot11lcn_gain_idx_tbl_rev0) /
- sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
- ,
-};
-
-const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev1[] = {
- {&dot11lcn_gain_tbl_rev1,
- sizeof(dot11lcn_gain_tbl_rev1) / sizeof(dot11lcn_gain_tbl_rev1[0]), 18,
- 0, 32}
- ,
- {&dot11lcn_aux_gain_idx_tbl_rev0,
- sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
- sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
- ,
- {&dot11lcn_gain_idx_tbl_rev0,
- sizeof(dot11lcn_gain_idx_tbl_rev0) /
- sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
- ,
-};
-
-const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[] = {
- {&dot11lcn_gain_tbl_2G,
- sizeof(dot11lcn_gain_tbl_2G) / sizeof(dot11lcn_gain_tbl_2G[0]), 18, 0,
- 32}
- ,
- {&dot11lcn_aux_gain_idx_tbl_2G,
- sizeof(dot11lcn_aux_gain_idx_tbl_2G) /
- sizeof(dot11lcn_aux_gain_idx_tbl_2G[0]), 14, 0, 16}
- ,
- {&dot11lcn_gain_idx_tbl_2G,
- sizeof(dot11lcn_gain_idx_tbl_2G) / sizeof(dot11lcn_gain_idx_tbl_2G[0]),
- 13, 0, 32}
- ,
- {&dot11lcn_gain_val_tbl_2G,
- sizeof(dot11lcn_gain_val_tbl_2G) / sizeof(dot11lcn_gain_val_tbl_2G[0]),
- 17, 0, 8}
-};
-
-const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[] = {
- {&dot11lcn_gain_tbl_5G,
- sizeof(dot11lcn_gain_tbl_5G) / sizeof(dot11lcn_gain_tbl_5G[0]), 18, 0,
- 32}
- ,
- {&dot11lcn_aux_gain_idx_tbl_5G,
- sizeof(dot11lcn_aux_gain_idx_tbl_5G) /
- sizeof(dot11lcn_aux_gain_idx_tbl_5G[0]), 14, 0, 16}
- ,
- {&dot11lcn_gain_idx_tbl_5G,
- sizeof(dot11lcn_gain_idx_tbl_5G) / sizeof(dot11lcn_gain_idx_tbl_5G[0]),
- 13, 0, 32}
- ,
- {&dot11lcn_gain_val_tbl_5G,
- sizeof(dot11lcn_gain_val_tbl_5G) / sizeof(dot11lcn_gain_val_tbl_5G[0]),
- 17, 0, 8}
-};
-
-const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[] = {
- {&dot11lcn_gain_tbl_extlna_2G,
- sizeof(dot11lcn_gain_tbl_extlna_2G) /
- sizeof(dot11lcn_gain_tbl_extlna_2G[0]), 18, 0, 32}
- ,
- {&dot11lcn_aux_gain_idx_tbl_extlna_2G,
- sizeof(dot11lcn_aux_gain_idx_tbl_extlna_2G) /
- sizeof(dot11lcn_aux_gain_idx_tbl_extlna_2G[0]), 14, 0, 16}
- ,
- {&dot11lcn_gain_idx_tbl_extlna_2G,
- sizeof(dot11lcn_gain_idx_tbl_extlna_2G) /
- sizeof(dot11lcn_gain_idx_tbl_extlna_2G[0]), 13, 0, 32}
- ,
- {&dot11lcn_gain_val_tbl_extlna_2G,
- sizeof(dot11lcn_gain_val_tbl_extlna_2G) /
- sizeof(dot11lcn_gain_val_tbl_extlna_2G[0]), 17, 0, 8}
-};
-
-const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[] = {
- {&dot11lcn_gain_tbl_5G,
- sizeof(dot11lcn_gain_tbl_5G) / sizeof(dot11lcn_gain_tbl_5G[0]), 18, 0,
- 32}
- ,
- {&dot11lcn_aux_gain_idx_tbl_5G,
- sizeof(dot11lcn_aux_gain_idx_tbl_5G) /
- sizeof(dot11lcn_aux_gain_idx_tbl_5G[0]), 14, 0, 16}
- ,
- {&dot11lcn_gain_idx_tbl_5G,
- sizeof(dot11lcn_gain_idx_tbl_5G) / sizeof(dot11lcn_gain_idx_tbl_5G[0]),
- 13, 0, 32}
- ,
- {&dot11lcn_gain_val_tbl_5G,
- sizeof(dot11lcn_gain_val_tbl_5G) / sizeof(dot11lcn_gain_val_tbl_5G[0]),
- 17, 0, 8}
-};
-
-const u32 dot11lcnphytbl_rx_gain_info_sz_rev0 =
- sizeof(dot11lcnphytbl_rx_gain_info_rev0) /
- sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]);
-
-const u32 dot11lcnphytbl_rx_gain_info_sz_rev1 =
- sizeof(dot11lcnphytbl_rx_gain_info_rev1) /
- sizeof(dot11lcnphytbl_rx_gain_info_rev1[0]);
-
-const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz =
- sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) /
- sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]);
-
-const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz =
- sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) /
- sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]);
-
-const u16 dot11lcn_min_sig_sq_tbl_rev0[] = {
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
- 0x014d,
-};
-
-const u16 dot11lcn_noise_scale_tbl_rev0[] = {
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
-};
-
-const u32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
- 0x000141f8,
- 0x000021f8,
- 0x000021fb,
- 0x000041fb,
- 0x0001fe4b,
- 0x0000217b,
- 0x00002133,
- 0x000040eb,
- 0x0001fea3,
- 0x0000024b,
-};
-
-const u32 dot11lcn_ps_ctrl_tbl_rev0[] = {
- 0x00100001,
- 0x00200010,
- 0x00300001,
- 0x00400010,
- 0x00500022,
- 0x00600122,
- 0x00700222,
- 0x00800322,
- 0x00900422,
- 0x00a00522,
- 0x00b00622,
- 0x00c00722,
- 0x00d00822,
- 0x00f00922,
- 0x00100a22,
- 0x00200b22,
- 0x00300c22,
- 0x00400d22,
- 0x00500e22,
- 0x00600f22,
-};
-
-const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[] = {
- 0x0007,
- 0x0005,
- 0x0006,
- 0x0004,
- 0x0007,
- 0x0005,
- 0x0006,
- 0x0004,
- 0x0007,
- 0x0005,
- 0x0006,
- 0x0004,
- 0x0007,
- 0x0005,
- 0x0006,
- 0x0004,
- 0x000b,
- 0x000b,
- 0x000a,
- 0x000a,
- 0x000b,
- 0x000b,
- 0x000a,
- 0x000a,
- 0x000b,
- 0x000b,
- 0x000a,
- 0x000a,
- 0x000b,
- 0x000b,
- 0x000a,
- 0x000a,
- 0x0007,
- 0x0005,
- 0x0006,
- 0x0004,
- 0x0007,
- 0x0005,
- 0x0006,
- 0x0004,
- 0x0007,
- 0x0005,
- 0x0006,
- 0x0004,
- 0x0007,
- 0x0005,
- 0x0006,
- 0x0004,
- 0x000b,
- 0x000b,
- 0x000a,
- 0x000a,
- 0x000b,
- 0x000b,
- 0x000a,
- 0x000a,
- 0x000b,
- 0x000b,
- 0x000a,
- 0x000a,
- 0x000b,
- 0x000b,
- 0x000a,
- 0x000a,
-
-};
-
-const u16 dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[] = {
- 0x0007,
- 0x0005,
- 0x0002,
- 0x0000,
- 0x0007,
- 0x0005,
- 0x0002,
- 0x0000,
- 0x0007,
- 0x0005,
- 0x0002,
- 0x0000,
- 0x0007,
- 0x0005,
- 0x0002,
- 0x0000,
- 0x0007,
- 0x0007,
- 0x0002,
- 0x0002,
- 0x0007,
- 0x0007,
- 0x0002,
- 0x0002,
- 0x0007,
- 0x0007,
- 0x0002,
- 0x0002,
- 0x0007,
- 0x0007,
- 0x0002,
- 0x0002,
- 0x0007,
- 0x0005,
- 0x0002,
- 0x0000,
- 0x0007,
- 0x0005,
- 0x0002,
- 0x0000,
- 0x0007,
- 0x0005,
- 0x0002,
- 0x0000,
- 0x0007,
- 0x0005,
- 0x0002,
- 0x0000,
- 0x0007,
- 0x0007,
- 0x0002,
- 0x0002,
- 0x0007,
- 0x0007,
- 0x0002,
- 0x0002,
- 0x0007,
- 0x0007,
- 0x0002,
- 0x0002,
- 0x0007,
- 0x0007,
- 0x0002,
- 0x0002,
-};
-
-const u16 dot11lcn_sw_ctrl_tbl_4313_epa_rev0[] = {
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
- 0x0002,
- 0x0008,
- 0x0004,
- 0x0001,
-};
-
-const u16 dot11lcn_sw_ctrl_tbl_4313_rev0[] = {
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
- 0x000a,
- 0x0009,
- 0x0006,
- 0x0005,
-};
-
-const u16 dot11lcn_sw_ctrl_tbl_rev0[] = {
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
- 0x0004,
- 0x0004,
- 0x0002,
- 0x0002,
-};
-
-const u8 dot11lcn_nf_table_rev0[] = {
- 0x5f,
- 0x36,
- 0x29,
- 0x1f,
- 0x5f,
- 0x36,
- 0x29,
- 0x1f,
- 0x5f,
- 0x36,
- 0x29,
- 0x1f,
- 0x5f,
- 0x36,
- 0x29,
- 0x1f,
-};
-
-const u8 dot11lcn_gain_val_tbl_rev0[] = {
- 0x09,
- 0x0f,
- 0x14,
- 0x18,
- 0xfe,
- 0x07,
- 0x0b,
- 0x0f,
- 0xfb,
- 0xfe,
- 0x01,
- 0x05,
- 0x08,
- 0x0b,
- 0x0e,
- 0x11,
- 0x14,
- 0x17,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x06,
- 0x09,
- 0x0c,
- 0x0f,
- 0x12,
- 0x15,
- 0x18,
- 0x1b,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0xeb,
- 0x00,
- 0x00,
-};
-
-const u8 dot11lcn_spur_tbl_rev0[] = {
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x02,
- 0x03,
- 0x01,
- 0x03,
- 0x02,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x02,
- 0x03,
- 0x01,
- 0x03,
- 0x02,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
- 0x01,
-};
-
-const u16 dot11lcn_unsup_mcs_tbl_rev0[] = {
- 0x001a,
- 0x0034,
- 0x004e,
- 0x0068,
- 0x009c,
- 0x00d0,
- 0x00ea,
- 0x0104,
- 0x0034,
- 0x0068,
- 0x009c,
- 0x00d0,
- 0x0138,
- 0x01a0,
- 0x01d4,
- 0x0208,
- 0x004e,
- 0x009c,
- 0x00ea,
- 0x0138,
- 0x01d4,
- 0x0270,
- 0x02be,
- 0x030c,
- 0x0068,
- 0x00d0,
- 0x0138,
- 0x01a0,
- 0x0270,
- 0x0340,
- 0x03a8,
- 0x0410,
- 0x0018,
- 0x009c,
- 0x00d0,
- 0x0104,
- 0x00ea,
- 0x0138,
- 0x0186,
- 0x00d0,
- 0x0104,
- 0x0104,
- 0x0138,
- 0x016c,
- 0x016c,
- 0x01a0,
- 0x0138,
- 0x0186,
- 0x0186,
- 0x01d4,
- 0x0222,
- 0x0222,
- 0x0270,
- 0x0104,
- 0x0138,
- 0x016c,
- 0x0138,
- 0x016c,
- 0x01a0,
- 0x01d4,
- 0x01a0,
- 0x01d4,
- 0x0208,
- 0x0208,
- 0x023c,
- 0x0186,
- 0x01d4,
- 0x0222,
- 0x01d4,
- 0x0222,
- 0x0270,
- 0x02be,
- 0x0270,
- 0x02be,
- 0x030c,
- 0x030c,
- 0x035a,
- 0x0036,
- 0x006c,
- 0x00a2,
- 0x00d8,
- 0x0144,
- 0x01b0,
- 0x01e6,
- 0x021c,
- 0x006c,
- 0x00d8,
- 0x0144,
- 0x01b0,
- 0x0288,
- 0x0360,
- 0x03cc,
- 0x0438,
- 0x00a2,
- 0x0144,
- 0x01e6,
- 0x0288,
- 0x03cc,
- 0x0510,
- 0x05b2,
- 0x0654,
- 0x00d8,
- 0x01b0,
- 0x0288,
- 0x0360,
- 0x0510,
- 0x06c0,
- 0x0798,
- 0x0870,
- 0x0018,
- 0x0144,
- 0x01b0,
- 0x021c,
- 0x01e6,
- 0x0288,
- 0x032a,
- 0x01b0,
- 0x021c,
- 0x021c,
- 0x0288,
- 0x02f4,
- 0x02f4,
- 0x0360,
- 0x0288,
- 0x032a,
- 0x032a,
- 0x03cc,
- 0x046e,
- 0x046e,
- 0x0510,
- 0x021c,
- 0x0288,
- 0x02f4,
- 0x0288,
- 0x02f4,
- 0x0360,
- 0x03cc,
- 0x0360,
- 0x03cc,
- 0x0438,
- 0x0438,
- 0x04a4,
- 0x032a,
- 0x03cc,
- 0x046e,
- 0x03cc,
- 0x046e,
- 0x0510,
- 0x05b2,
- 0x0510,
- 0x05b2,
- 0x0654,
- 0x0654,
- 0x06f6,
-};
-
-const u16 dot11lcn_iq_local_tbl_rev0[] = {
- 0x0200,
- 0x0300,
- 0x0400,
- 0x0600,
- 0x0800,
- 0x0b00,
- 0x1000,
- 0x1001,
- 0x1002,
- 0x1003,
- 0x1004,
- 0x1005,
- 0x1006,
- 0x1007,
- 0x1707,
- 0x2007,
- 0x2d07,
- 0x4007,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0200,
- 0x0300,
- 0x0400,
- 0x0600,
- 0x0800,
- 0x0b00,
- 0x1000,
- 0x1001,
- 0x1002,
- 0x1003,
- 0x1004,
- 0x1005,
- 0x1006,
- 0x1007,
- 0x1707,
- 0x2007,
- 0x2d07,
- 0x4007,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x4000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
-};
-
-const u32 dot11lcn_papd_compdelta_tbl_rev0[] = {
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
- 0x00080000,
-};
-
-const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[] = {
- {&dot11lcn_min_sig_sq_tbl_rev0,
- sizeof(dot11lcn_min_sig_sq_tbl_rev0) /
- sizeof(dot11lcn_min_sig_sq_tbl_rev0[0]), 2, 0, 16}
- ,
- {&dot11lcn_noise_scale_tbl_rev0,
- sizeof(dot11lcn_noise_scale_tbl_rev0) /
- sizeof(dot11lcn_noise_scale_tbl_rev0[0]), 1, 0, 16}
- ,
- {&dot11lcn_fltr_ctrl_tbl_rev0,
- sizeof(dot11lcn_fltr_ctrl_tbl_rev0) /
- sizeof(dot11lcn_fltr_ctrl_tbl_rev0[0]), 11, 0, 32}
- ,
- {&dot11lcn_ps_ctrl_tbl_rev0,
- sizeof(dot11lcn_ps_ctrl_tbl_rev0) /
- sizeof(dot11lcn_ps_ctrl_tbl_rev0[0]), 12, 0, 32}
- ,
- {&dot11lcn_gain_idx_tbl_rev0,
- sizeof(dot11lcn_gain_idx_tbl_rev0) /
- sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
- ,
- {&dot11lcn_aux_gain_idx_tbl_rev0,
- sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
- sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
- ,
- {&dot11lcn_sw_ctrl_tbl_rev0,
- sizeof(dot11lcn_sw_ctrl_tbl_rev0) /
- sizeof(dot11lcn_sw_ctrl_tbl_rev0[0]), 15, 0, 16}
- ,
- {&dot11lcn_nf_table_rev0,
- sizeof(dot11lcn_nf_table_rev0) / sizeof(dot11lcn_nf_table_rev0[0]), 16,
- 0, 8}
- ,
- {&dot11lcn_gain_val_tbl_rev0,
- sizeof(dot11lcn_gain_val_tbl_rev0) /
- sizeof(dot11lcn_gain_val_tbl_rev0[0]), 17, 0, 8}
- ,
- {&dot11lcn_gain_tbl_rev0,
- sizeof(dot11lcn_gain_tbl_rev0) / sizeof(dot11lcn_gain_tbl_rev0[0]), 18,
- 0, 32}
- ,
- {&dot11lcn_spur_tbl_rev0,
- sizeof(dot11lcn_spur_tbl_rev0) / sizeof(dot11lcn_spur_tbl_rev0[0]), 20,
- 0, 8}
- ,
- {&dot11lcn_unsup_mcs_tbl_rev0,
- sizeof(dot11lcn_unsup_mcs_tbl_rev0) /
- sizeof(dot11lcn_unsup_mcs_tbl_rev0[0]), 23, 0, 16}
- ,
- {&dot11lcn_iq_local_tbl_rev0,
- sizeof(dot11lcn_iq_local_tbl_rev0) /
- sizeof(dot11lcn_iq_local_tbl_rev0[0]), 0, 0, 16}
- ,
- {&dot11lcn_papd_compdelta_tbl_rev0,
- sizeof(dot11lcn_papd_compdelta_tbl_rev0) /
- sizeof(dot11lcn_papd_compdelta_tbl_rev0[0]), 24, 0, 32}
- ,
-};
-
-const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313 = {
- &dot11lcn_sw_ctrl_tbl_4313_rev0,
- sizeof(dot11lcn_sw_ctrl_tbl_4313_rev0) /
- sizeof(dot11lcn_sw_ctrl_tbl_4313_rev0[0]), 15, 0, 16
-};
-
-const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa = {
- &dot11lcn_sw_ctrl_tbl_4313_epa_rev0,
- sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0) /
- sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0[0]), 15, 0, 16
-};
-
-const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa = {
- &dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo,
- sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo) /
- sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[0]), 15, 0, 16
-};
-
-const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = {
- &dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0,
- sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0) /
- sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16
-};
-
-const u32 dot11lcnphytbl_info_sz_rev0 =
- sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]);
-
-const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = {
- {3, 0, 31, 0, 72,}
- ,
- {3, 0, 31, 0, 70,}
- ,
- {3, 0, 31, 0, 68,}
- ,
- {3, 0, 30, 0, 67,}
- ,
- {3, 0, 29, 0, 68,}
- ,
- {3, 0, 28, 0, 68,}
- ,
- {3, 0, 27, 0, 69,}
- ,
- {3, 0, 26, 0, 70,}
- ,
- {3, 0, 25, 0, 70,}
- ,
- {3, 0, 24, 0, 71,}
- ,
- {3, 0, 23, 0, 72,}
- ,
- {3, 0, 23, 0, 70,}
- ,
- {3, 0, 22, 0, 71,}
- ,
- {3, 0, 21, 0, 72,}
- ,
- {3, 0, 21, 0, 70,}
- ,
- {3, 0, 21, 0, 68,}
- ,
- {3, 0, 21, 0, 66,}
- ,
- {3, 0, 21, 0, 64,}
- ,
- {3, 0, 21, 0, 63,}
- ,
- {3, 0, 20, 0, 64,}
- ,
- {3, 0, 19, 0, 65,}
- ,
- {3, 0, 19, 0, 64,}
- ,
- {3, 0, 18, 0, 65,}
- ,
- {3, 0, 18, 0, 64,}
- ,
- {3, 0, 17, 0, 65,}
- ,
- {3, 0, 17, 0, 64,}
- ,
- {3, 0, 16, 0, 65,}
- ,
- {3, 0, 16, 0, 64,}
- ,
- {3, 0, 16, 0, 62,}
- ,
- {3, 0, 16, 0, 60,}
- ,
- {3, 0, 16, 0, 58,}
- ,
- {3, 0, 15, 0, 61,}
- ,
- {3, 0, 15, 0, 59,}
- ,
- {3, 0, 14, 0, 61,}
- ,
- {3, 0, 14, 0, 60,}
- ,
- {3, 0, 14, 0, 58,}
- ,
- {3, 0, 13, 0, 60,}
- ,
- {3, 0, 13, 0, 59,}
- ,
- {3, 0, 12, 0, 62,}
- ,
- {3, 0, 12, 0, 60,}
- ,
- {3, 0, 12, 0, 58,}
- ,
- {3, 0, 11, 0, 62,}
- ,
- {3, 0, 11, 0, 60,}
- ,
- {3, 0, 11, 0, 59,}
- ,
- {3, 0, 11, 0, 57,}
- ,
- {3, 0, 10, 0, 61,}
- ,
- {3, 0, 10, 0, 59,}
- ,
- {3, 0, 10, 0, 57,}
- ,
- {3, 0, 9, 0, 62,}
- ,
- {3, 0, 9, 0, 60,}
- ,
- {3, 0, 9, 0, 58,}
- ,
- {3, 0, 9, 0, 57,}
- ,
- {3, 0, 8, 0, 62,}
- ,
- {3, 0, 8, 0, 60,}
- ,
- {3, 0, 8, 0, 58,}
- ,
- {3, 0, 8, 0, 57,}
- ,
- {3, 0, 8, 0, 55,}
- ,
- {3, 0, 7, 0, 61,}
- ,
- {3, 0, 7, 0, 60,}
- ,
- {3, 0, 7, 0, 58,}
- ,
- {3, 0, 7, 0, 56,}
- ,
- {3, 0, 7, 0, 55,}
- ,
- {3, 0, 6, 0, 62,}
- ,
- {3, 0, 6, 0, 60,}
- ,
- {3, 0, 6, 0, 58,}
- ,
- {3, 0, 6, 0, 57,}
- ,
- {3, 0, 6, 0, 55,}
- ,
- {3, 0, 6, 0, 54,}
- ,
- {3, 0, 6, 0, 52,}
- ,
- {3, 0, 5, 0, 61,}
- ,
- {3, 0, 5, 0, 59,}
- ,
- {3, 0, 5, 0, 57,}
- ,
- {3, 0, 5, 0, 56,}
- ,
- {3, 0, 5, 0, 54,}
- ,
- {3, 0, 5, 0, 53,}
- ,
- {3, 0, 5, 0, 51,}
- ,
- {3, 0, 4, 0, 62,}
- ,
- {3, 0, 4, 0, 60,}
- ,
- {3, 0, 4, 0, 58,}
- ,
- {3, 0, 4, 0, 57,}
- ,
- {3, 0, 4, 0, 55,}
- ,
- {3, 0, 4, 0, 54,}
- ,
- {3, 0, 4, 0, 52,}
- ,
- {3, 0, 4, 0, 51,}
- ,
- {3, 0, 4, 0, 49,}
- ,
- {3, 0, 4, 0, 48,}
- ,
- {3, 0, 4, 0, 46,}
- ,
- {3, 0, 3, 0, 60,}
- ,
- {3, 0, 3, 0, 58,}
- ,
- {3, 0, 3, 0, 57,}
- ,
- {3, 0, 3, 0, 55,}
- ,
- {3, 0, 3, 0, 54,}
- ,
- {3, 0, 3, 0, 52,}
- ,
- {3, 0, 3, 0, 51,}
- ,
- {3, 0, 3, 0, 49,}
- ,
- {3, 0, 3, 0, 48,}
- ,
- {3, 0, 3, 0, 46,}
- ,
- {3, 0, 3, 0, 45,}
- ,
- {3, 0, 3, 0, 44,}
- ,
- {3, 0, 3, 0, 43,}
- ,
- {3, 0, 3, 0, 41,}
- ,
- {3, 0, 2, 0, 61,}
- ,
- {3, 0, 2, 0, 59,}
- ,
- {3, 0, 2, 0, 57,}
- ,
- {3, 0, 2, 0, 56,}
- ,
- {3, 0, 2, 0, 54,}
- ,
- {3, 0, 2, 0, 53,}
- ,
- {3, 0, 2, 0, 51,}
- ,
- {3, 0, 2, 0, 50,}
- ,
- {3, 0, 2, 0, 48,}
- ,
- {3, 0, 2, 0, 47,}
- ,
- {3, 0, 2, 0, 46,}
- ,
- {3, 0, 2, 0, 44,}
- ,
- {3, 0, 2, 0, 43,}
- ,
- {3, 0, 2, 0, 42,}
- ,
- {3, 0, 2, 0, 41,}
- ,
- {3, 0, 2, 0, 39,}
- ,
- {3, 0, 2, 0, 38,}
- ,
- {3, 0, 2, 0, 37,}
- ,
- {3, 0, 2, 0, 36,}
- ,
- {3, 0, 2, 0, 35,}
- ,
- {3, 0, 2, 0, 34,}
- ,
- {3, 0, 2, 0, 33,}
- ,
- {3, 0, 2, 0, 32,}
- ,
- {3, 0, 1, 0, 63,}
- ,
- {3, 0, 1, 0, 61,}
- ,
- {3, 0, 1, 0, 59,}
- ,
- {3, 0, 1, 0, 57,}
- ,
-};
-
-const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_gaintable_rev0[128] = {
- {7, 0, 31, 0, 72,}
- ,
- {7, 0, 31, 0, 70,}
- ,
- {7, 0, 31, 0, 68,}
- ,
- {7, 0, 30, 0, 67,}
- ,
- {7, 0, 29, 0, 68,}
- ,
- {7, 0, 28, 0, 68,}
- ,
- {7, 0, 27, 0, 69,}
- ,
- {7, 0, 26, 0, 70,}
- ,
- {7, 0, 25, 0, 70,}
- ,
- {7, 0, 24, 0, 71,}
- ,
- {7, 0, 23, 0, 72,}
- ,
- {7, 0, 23, 0, 70,}
- ,
- {7, 0, 22, 0, 71,}
- ,
- {7, 0, 21, 0, 72,}
- ,
- {7, 0, 21, 0, 70,}
- ,
- {7, 0, 21, 0, 68,}
- ,
- {7, 0, 21, 0, 66,}
- ,
- {7, 0, 21, 0, 64,}
- ,
- {7, 0, 21, 0, 63,}
- ,
- {7, 0, 20, 0, 64,}
- ,
- {7, 0, 19, 0, 65,}
- ,
- {7, 0, 19, 0, 64,}
- ,
- {7, 0, 18, 0, 65,}
- ,
- {7, 0, 18, 0, 64,}
- ,
- {7, 0, 17, 0, 65,}
- ,
- {7, 0, 17, 0, 64,}
- ,
- {7, 0, 16, 0, 65,}
- ,
- {7, 0, 16, 0, 64,}
- ,
- {7, 0, 16, 0, 62,}
- ,
- {7, 0, 16, 0, 60,}
- ,
- {7, 0, 16, 0, 58,}
- ,
- {7, 0, 15, 0, 61,}
- ,
- {7, 0, 15, 0, 59,}
- ,
- {7, 0, 14, 0, 61,}
- ,
- {7, 0, 14, 0, 60,}
- ,
- {7, 0, 14, 0, 58,}
- ,
- {7, 0, 13, 0, 60,}
- ,
- {7, 0, 13, 0, 59,}
- ,
- {7, 0, 12, 0, 62,}
- ,
- {7, 0, 12, 0, 60,}
- ,
- {7, 0, 12, 0, 58,}
- ,
- {7, 0, 11, 0, 62,}
- ,
- {7, 0, 11, 0, 60,}
- ,
- {7, 0, 11, 0, 59,}
- ,
- {7, 0, 11, 0, 57,}
- ,
- {7, 0, 10, 0, 61,}
- ,
- {7, 0, 10, 0, 59,}
- ,
- {7, 0, 10, 0, 57,}
- ,
- {7, 0, 9, 0, 62,}
- ,
- {7, 0, 9, 0, 60,}
- ,
- {7, 0, 9, 0, 58,}
- ,
- {7, 0, 9, 0, 57,}
- ,
- {7, 0, 8, 0, 62,}
- ,
- {7, 0, 8, 0, 60,}
- ,
- {7, 0, 8, 0, 58,}
- ,
- {7, 0, 8, 0, 57,}
- ,
- {7, 0, 8, 0, 55,}
- ,
- {7, 0, 7, 0, 61,}
- ,
- {7, 0, 7, 0, 60,}
- ,
- {7, 0, 7, 0, 58,}
- ,
- {7, 0, 7, 0, 56,}
- ,
- {7, 0, 7, 0, 55,}
- ,
- {7, 0, 6, 0, 62,}
- ,
- {7, 0, 6, 0, 60,}
- ,
- {7, 0, 6, 0, 58,}
- ,
- {7, 0, 6, 0, 57,}
- ,
- {7, 0, 6, 0, 55,}
- ,
- {7, 0, 6, 0, 54,}
- ,
- {7, 0, 6, 0, 52,}
- ,
- {7, 0, 5, 0, 61,}
- ,
- {7, 0, 5, 0, 59,}
- ,
- {7, 0, 5, 0, 57,}
- ,
- {7, 0, 5, 0, 56,}
- ,
- {7, 0, 5, 0, 54,}
- ,
- {7, 0, 5, 0, 53,}
- ,
- {7, 0, 5, 0, 51,}
- ,
- {7, 0, 4, 0, 62,}
- ,
- {7, 0, 4, 0, 60,}
- ,
- {7, 0, 4, 0, 58,}
- ,
- {7, 0, 4, 0, 57,}
- ,
- {7, 0, 4, 0, 55,}
- ,
- {7, 0, 4, 0, 54,}
- ,
- {7, 0, 4, 0, 52,}
- ,
- {7, 0, 4, 0, 51,}
- ,
- {7, 0, 4, 0, 49,}
- ,
- {7, 0, 4, 0, 48,}
- ,
- {7, 0, 4, 0, 46,}
- ,
- {7, 0, 3, 0, 60,}
- ,
- {7, 0, 3, 0, 58,}
- ,
- {7, 0, 3, 0, 57,}
- ,
- {7, 0, 3, 0, 55,}
- ,
- {7, 0, 3, 0, 54,}
- ,
- {7, 0, 3, 0, 52,}
- ,
- {7, 0, 3, 0, 51,}
- ,
- {7, 0, 3, 0, 49,}
- ,
- {7, 0, 3, 0, 48,}
- ,
- {7, 0, 3, 0, 46,}
- ,
- {7, 0, 3, 0, 45,}
- ,
- {7, 0, 3, 0, 44,}
- ,
- {7, 0, 3, 0, 43,}
- ,
- {7, 0, 3, 0, 41,}
- ,
- {7, 0, 2, 0, 61,}
- ,
- {7, 0, 2, 0, 59,}
- ,
- {7, 0, 2, 0, 57,}
- ,
- {7, 0, 2, 0, 56,}
- ,
- {7, 0, 2, 0, 54,}
- ,
- {7, 0, 2, 0, 53,}
- ,
- {7, 0, 2, 0, 51,}
- ,
- {7, 0, 2, 0, 50,}
- ,
- {7, 0, 2, 0, 48,}
- ,
- {7, 0, 2, 0, 47,}
- ,
- {7, 0, 2, 0, 46,}
- ,
- {7, 0, 2, 0, 44,}
- ,
- {7, 0, 2, 0, 43,}
- ,
- {7, 0, 2, 0, 42,}
- ,
- {7, 0, 2, 0, 41,}
- ,
- {7, 0, 2, 0, 39,}
- ,
- {7, 0, 2, 0, 38,}
- ,
- {7, 0, 2, 0, 37,}
- ,
- {7, 0, 2, 0, 36,}
- ,
- {7, 0, 2, 0, 35,}
- ,
- {7, 0, 2, 0, 34,}
- ,
- {7, 0, 2, 0, 33,}
- ,
- {7, 0, 2, 0, 32,}
- ,
- {7, 0, 1, 0, 63,}
- ,
- {7, 0, 1, 0, 61,}
- ,
- {7, 0, 1, 0, 59,}
- ,
- {7, 0, 1, 0, 57,}
- ,
-};
-
-const lcnphy_tx_gain_tbl_entry dot11lcnphy_5GHz_gaintable_rev0[128] = {
- {255, 255, 0xf0, 0, 152,}
- ,
- {255, 255, 0xf0, 0, 147,}
- ,
- {255, 255, 0xf0, 0, 143,}
- ,
- {255, 255, 0xf0, 0, 139,}
- ,
- {255, 255, 0xf0, 0, 135,}
- ,
- {255, 255, 0xf0, 0, 131,}
- ,
- {255, 255, 0xf0, 0, 128,}
- ,
- {255, 255, 0xf0, 0, 124,}
- ,
- {255, 255, 0xf0, 0, 121,}
- ,
- {255, 255, 0xf0, 0, 117,}
- ,
- {255, 255, 0xf0, 0, 114,}
- ,
- {255, 255, 0xf0, 0, 111,}
- ,
- {255, 255, 0xf0, 0, 107,}
- ,
- {255, 255, 0xf0, 0, 104,}
- ,
- {255, 255, 0xf0, 0, 101,}
- ,
- {255, 255, 0xf0, 0, 99,}
- ,
- {255, 255, 0xf0, 0, 96,}
- ,
- {255, 255, 0xf0, 0, 93,}
- ,
- {255, 255, 0xf0, 0, 90,}
- ,
- {255, 255, 0xf0, 0, 88,}
- ,
- {255, 255, 0xf0, 0, 85,}
- ,
- {255, 255, 0xf0, 0, 83,}
- ,
- {255, 255, 0xf0, 0, 81,}
- ,
- {255, 255, 0xf0, 0, 78,}
- ,
- {255, 255, 0xf0, 0, 76,}
- ,
- {255, 255, 0xf0, 0, 74,}
- ,
- {255, 255, 0xf0, 0, 72,}
- ,
- {255, 255, 0xf0, 0, 70,}
- ,
- {255, 255, 0xf0, 0, 68,}
- ,
- {255, 255, 0xf0, 0, 66,}
- ,
- {255, 255, 0xf0, 0, 64,}
- ,
- {255, 248, 0xf0, 0, 64,}
- ,
- {255, 241, 0xf0, 0, 64,}
- ,
- {255, 251, 0xe0, 0, 64,}
- ,
- {255, 244, 0xe0, 0, 64,}
- ,
- {255, 254, 0xd0, 0, 64,}
- ,
- {255, 246, 0xd0, 0, 64,}
- ,
- {255, 239, 0xd0, 0, 64,}
- ,
- {255, 249, 0xc0, 0, 64,}
- ,
- {255, 242, 0xc0, 0, 64,}
- ,
- {255, 255, 0xb0, 0, 64,}
- ,
- {255, 248, 0xb0, 0, 64,}
- ,
- {255, 241, 0xb0, 0, 64,}
- ,
- {255, 254, 0xa0, 0, 64,}
- ,
- {255, 246, 0xa0, 0, 64,}
- ,
- {255, 239, 0xa0, 0, 64,}
- ,
- {255, 255, 0x90, 0, 64,}
- ,
- {255, 248, 0x90, 0, 64,}
- ,
- {255, 241, 0x90, 0, 64,}
- ,
- {255, 234, 0x90, 0, 64,}
- ,
- {255, 255, 0x80, 0, 64,}
- ,
- {255, 248, 0x80, 0, 64,}
- ,
- {255, 241, 0x80, 0, 64,}
- ,
- {255, 234, 0x80, 0, 64,}
- ,
- {255, 255, 0x70, 0, 64,}
- ,
- {255, 248, 0x70, 0, 64,}
- ,
- {255, 241, 0x70, 0, 64,}
- ,
- {255, 234, 0x70, 0, 64,}
- ,
- {255, 227, 0x70, 0, 64,}
- ,
- {255, 221, 0x70, 0, 64,}
- ,
- {255, 215, 0x70, 0, 64,}
- ,
- {255, 208, 0x70, 0, 64,}
- ,
- {255, 203, 0x70, 0, 64,}
- ,
- {255, 197, 0x70, 0, 64,}
- ,
- {255, 255, 0x60, 0, 64,}
- ,
- {255, 248, 0x60, 0, 64,}
- ,
- {255, 241, 0x60, 0, 64,}
- ,
- {255, 234, 0x60, 0, 64,}
- ,
- {255, 227, 0x60, 0, 64,}
- ,
- {255, 221, 0x60, 0, 64,}
- ,
- {255, 255, 0x50, 0, 64,}
- ,
- {255, 248, 0x50, 0, 64,}
- ,
- {255, 241, 0x50, 0, 64,}
- ,
- {255, 234, 0x50, 0, 64,}
- ,
- {255, 227, 0x50, 0, 64,}
- ,
- {255, 221, 0x50, 0, 64,}
- ,
- {255, 215, 0x50, 0, 64,}
- ,
- {255, 208, 0x50, 0, 64,}
- ,
- {255, 255, 0x40, 0, 64,}
- ,
- {255, 248, 0x40, 0, 64,}
- ,
- {255, 241, 0x40, 0, 64,}
- ,
- {255, 234, 0x40, 0, 64,}
- ,
- {255, 227, 0x40, 0, 64,}
- ,
- {255, 221, 0x40, 0, 64,}
- ,
- {255, 215, 0x40, 0, 64,}
- ,
- {255, 208, 0x40, 0, 64,}
- ,
- {255, 203, 0x40, 0, 64,}
- ,
- {255, 197, 0x40, 0, 64,}
- ,
- {255, 255, 0x30, 0, 64,}
- ,
- {255, 248, 0x30, 0, 64,}
- ,
- {255, 241, 0x30, 0, 64,}
- ,
- {255, 234, 0x30, 0, 64,}
- ,
- {255, 227, 0x30, 0, 64,}
- ,
- {255, 221, 0x30, 0, 64,}
- ,
- {255, 215, 0x30, 0, 64,}
- ,
- {255, 208, 0x30, 0, 64,}
- ,
- {255, 203, 0x30, 0, 64,}
- ,
- {255, 197, 0x30, 0, 64,}
- ,
- {255, 191, 0x30, 0, 64,}
- ,
- {255, 186, 0x30, 0, 64,}
- ,
- {255, 181, 0x30, 0, 64,}
- ,
- {255, 175, 0x30, 0, 64,}
- ,
- {255, 255, 0x20, 0, 64,}
- ,
- {255, 248, 0x20, 0, 64,}
- ,
- {255, 241, 0x20, 0, 64,}
- ,
- {255, 234, 0x20, 0, 64,}
- ,
- {255, 227, 0x20, 0, 64,}
- ,
- {255, 221, 0x20, 0, 64,}
- ,
- {255, 215, 0x20, 0, 64,}
- ,
- {255, 208, 0x20, 0, 64,}
- ,
- {255, 203, 0x20, 0, 64,}
- ,
- {255, 197, 0x20, 0, 64,}
- ,
- {255, 191, 0x20, 0, 64,}
- ,
- {255, 186, 0x20, 0, 64,}
- ,
- {255, 181, 0x20, 0, 64,}
- ,
- {255, 175, 0x20, 0, 64,}
- ,
- {255, 170, 0x20, 0, 64,}
- ,
- {255, 166, 0x20, 0, 64,}
- ,
- {255, 161, 0x20, 0, 64,}
- ,
- {255, 156, 0x20, 0, 64,}
- ,
- {255, 152, 0x20, 0, 64,}
- ,
- {255, 148, 0x20, 0, 64,}
- ,
- {255, 143, 0x20, 0, 64,}
- ,
- {255, 139, 0x20, 0, 64,}
- ,
- {255, 135, 0x20, 0, 64,}
- ,
- {255, 132, 0x20, 0, 64,}
- ,
- {255, 255, 0x10, 0, 64,}
- ,
- {255, 248, 0x10, 0, 64,}
- ,
-};
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-typedef phytbl_info_t dot11lcnphytbl_info_t;
-
-extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[];
-extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev0;
-extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313;
-extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa;
-extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa_combo;
-
-extern const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[];
-extern const u32 dot11lcnphytbl_info_sz_rev0;
-
-extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[];
-extern const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
-
-extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[];
-extern const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
-
-extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[];
-
-extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[];
-
-typedef struct {
- unsigned char gm;
- unsigned char pga;
- unsigned char pad;
- unsigned char dac;
- unsigned char bb_mult;
-} lcnphy_tx_gain_tbl_entry;
-
-extern const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_gaintable_rev0[];
-extern const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[];
-
-extern const lcnphy_tx_gain_tbl_entry dot11lcnphy_5GHz_gaintable_rev0[];
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/kernel.h>
-
-#include "bcmdma.h"
-#include <wlc_phy_int.h>
-#include <wlc_phytbl_n.h>
-
-const u32 frame_struct_rev0[] = {
- 0x08004a04,
- 0x00100000,
- 0x01000a05,
- 0x00100020,
- 0x09804506,
- 0x00100030,
- 0x09804507,
- 0x00100030,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x08004a0c,
- 0x00100004,
- 0x01000a0d,
- 0x00100024,
- 0x0980450e,
- 0x00100034,
- 0x0980450f,
- 0x00100034,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000a04,
- 0x00100000,
- 0x11008a05,
- 0x00100020,
- 0x1980c506,
- 0x00100030,
- 0x21810506,
- 0x00100030,
- 0x21810506,
- 0x00100030,
- 0x01800504,
- 0x00100030,
- 0x11808505,
- 0x00100030,
- 0x29814507,
- 0x01100030,
- 0x00000a04,
- 0x00100000,
- 0x11008a05,
- 0x00100020,
- 0x21810506,
- 0x00100030,
- 0x21810506,
- 0x00100030,
- 0x29814507,
- 0x01100030,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000a0c,
- 0x00100008,
- 0x11008a0d,
- 0x00100028,
- 0x1980c50e,
- 0x00100038,
- 0x2181050e,
- 0x00100038,
- 0x2181050e,
- 0x00100038,
- 0x0180050c,
- 0x00100038,
- 0x1180850d,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000a0c,
- 0x00100008,
- 0x11008a0d,
- 0x00100028,
- 0x2181050e,
- 0x00100038,
- 0x2181050e,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x08004a04,
- 0x00100000,
- 0x01000a05,
- 0x00100020,
- 0x1980c506,
- 0x00100030,
- 0x1980c506,
- 0x00100030,
- 0x11808504,
- 0x00100030,
- 0x3981ca05,
- 0x00100030,
- 0x29814507,
- 0x01100030,
- 0x00000000,
- 0x00000000,
- 0x10008a04,
- 0x00100000,
- 0x3981ca05,
- 0x00100030,
- 0x1980c506,
- 0x00100030,
- 0x29814507,
- 0x01100030,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x08004a0c,
- 0x00100008,
- 0x01000a0d,
- 0x00100028,
- 0x1980c50e,
- 0x00100038,
- 0x1980c50e,
- 0x00100038,
- 0x1180850c,
- 0x00100038,
- 0x3981ca0d,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x10008a0c,
- 0x00100008,
- 0x3981ca0d,
- 0x00100038,
- 0x1980c50e,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40021404,
- 0x00100000,
- 0x02001405,
- 0x00100040,
- 0x0b004a06,
- 0x01900060,
- 0x13008a06,
- 0x01900060,
- 0x13008a06,
- 0x01900060,
- 0x43020a04,
- 0x00100060,
- 0x1b00ca05,
- 0x00100060,
- 0x23010a07,
- 0x01500060,
- 0x40021404,
- 0x00100000,
- 0x1a00d405,
- 0x00100040,
- 0x13008a06,
- 0x01900060,
- 0x13008a06,
- 0x01900060,
- 0x23010a07,
- 0x01500060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x4002140c,
- 0x00100010,
- 0x0200140d,
- 0x00100050,
- 0x0b004a0e,
- 0x01900070,
- 0x13008a0e,
- 0x01900070,
- 0x13008a0e,
- 0x01900070,
- 0x43020a0c,
- 0x00100070,
- 0x1b00ca0d,
- 0x00100070,
- 0x23010a0f,
- 0x01500070,
- 0x4002140c,
- 0x00100010,
- 0x1a00d40d,
- 0x00100050,
- 0x13008a0e,
- 0x01900070,
- 0x13008a0e,
- 0x01900070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x50029404,
- 0x00100000,
- 0x32019405,
- 0x00100040,
- 0x0b004a06,
- 0x01900060,
- 0x0b004a06,
- 0x01900060,
- 0x5b02ca04,
- 0x00100060,
- 0x3b01d405,
- 0x00100060,
- 0x23010a07,
- 0x01500060,
- 0x00000000,
- 0x00000000,
- 0x5802d404,
- 0x00100000,
- 0x3b01d405,
- 0x00100060,
- 0x0b004a06,
- 0x01900060,
- 0x23010a07,
- 0x01500060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x5002940c,
- 0x00100010,
- 0x3201940d,
- 0x00100050,
- 0x0b004a0e,
- 0x01900070,
- 0x0b004a0e,
- 0x01900070,
- 0x5b02ca0c,
- 0x00100070,
- 0x3b01d40d,
- 0x00100070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
- 0x5802d40c,
- 0x00100010,
- 0x3b01d40d,
- 0x00100070,
- 0x0b004a0e,
- 0x01900070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40021404,
- 0x000f4800,
- 0x62031405,
- 0x00100040,
- 0x53028a06,
- 0x01900060,
- 0x53028a07,
- 0x01900060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x4002140c,
- 0x000f4808,
- 0x6203140d,
- 0x00100048,
- 0x53028a0e,
- 0x01900068,
- 0x53028a0f,
- 0x01900068,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000a0c,
- 0x00100004,
- 0x11008a0d,
- 0x00100024,
- 0x1980c50e,
- 0x00100034,
- 0x2181050e,
- 0x00100034,
- 0x2181050e,
- 0x00100034,
- 0x0180050c,
- 0x00100038,
- 0x1180850d,
- 0x00100038,
- 0x1181850d,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000a0c,
- 0x00100008,
- 0x11008a0d,
- 0x00100028,
- 0x2181050e,
- 0x00100038,
- 0x2181050e,
- 0x00100038,
- 0x1181850d,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x08004a04,
- 0x00100000,
- 0x01000a05,
- 0x00100020,
- 0x0180c506,
- 0x00100030,
- 0x0180c506,
- 0x00100030,
- 0x2180c50c,
- 0x00100030,
- 0x49820a0d,
- 0x0016a130,
- 0x41824a0d,
- 0x0016a130,
- 0x2981450f,
- 0x01100030,
- 0x00000000,
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- 0x00000000,
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- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x2000ca0c,
- 0x00100000,
- 0x49820a0d,
- 0x0016a130,
- 0x1980c50e,
- 0x00100030,
- 0x41824a0d,
- 0x0016a130,
- 0x2981450f,
- 0x01100030,
- 0x00000000,
- 0x00000000,
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- 0x00000000,
- 0x00000000,
- 0x00000000,
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- 0x0b004a0e,
- 0x01900068,
- 0x13008a0e,
- 0x01900068,
- 0x13008a0e,
- 0x01900068,
- 0x43020a0c,
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- 0x1b00ca0d,
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- 0x1b014a0d,
- 0x00100070,
- 0x23010a0f,
- 0x01500070,
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- 0x4002140c,
- 0x00100010,
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- 0x00100050,
- 0x13008a0e,
- 0x01900070,
- 0x13008a0e,
- 0x01900070,
- 0x1b014a0d,
- 0x00100070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
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- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x50029404,
- 0x00100000,
- 0x32019405,
- 0x00100040,
- 0x03004a06,
- 0x01900060,
- 0x03004a06,
- 0x01900060,
- 0x6b030a0c,
- 0x00100060,
- 0x4b02140d,
- 0x0016a160,
- 0x4302540d,
- 0x0016a160,
- 0x23010a0f,
- 0x01500060,
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- 0x01900060,
- 0x4302540d,
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- 0x00100000,
- 0x1a00d405,
- 0x00100040,
- 0x53028a06,
- 0x01900060,
- 0x5b02ca06,
- 0x01900060,
- 0x5b02ca06,
- 0x01900060,
- 0x43020a04,
- 0x00100060,
- 0x1b00ca05,
- 0x00100060,
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- 0x1a00d40d,
- 0x00100050,
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- 0x01900070,
- 0x5b02ca0e,
- 0x01900070,
- 0x5b02ca0e,
- 0x01900070,
- 0x43020a0c,
- 0x00100070,
- 0x1b00ca0d,
- 0x00100070,
- 0x53028a0f,
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- 0x00100040,
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- 0x01900060,
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- 0x00000000,
- 0x00000000,
-};
-
-const u8 frame_lut_rev0[] = {
- 0x02,
- 0x04,
- 0x14,
- 0x14,
- 0x03,
- 0x05,
- 0x16,
- 0x16,
- 0x0a,
- 0x0c,
- 0x1c,
- 0x1c,
- 0x0b,
- 0x0d,
- 0x1e,
- 0x1e,
- 0x06,
- 0x08,
- 0x18,
- 0x18,
- 0x07,
- 0x09,
- 0x1a,
- 0x1a,
- 0x0e,
- 0x10,
- 0x20,
- 0x28,
- 0x0f,
- 0x11,
- 0x22,
- 0x2a,
-};
-
-const u32 tmap_tbl_rev0[] = {
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00000111,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x000aa888,
- 0x88880000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa2222220,
- 0x22222222,
- 0x22c22222,
- 0x00000222,
- 0x22000000,
- 0x2222a222,
- 0x22222222,
- 0x222222a2,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00011111,
- 0x11110000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0xa8aa88a0,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x00088aaa,
- 0xaaaa0000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xaaa8aaa0,
- 0x8aaa8aaa,
- 0xaa8a8a8a,
- 0x000aaa88,
- 0x8aaa0000,
- 0xaaa8a888,
- 0x8aa88a8a,
- 0x8a88a888,
- 0x08080a00,
- 0x0a08080a,
- 0x080a0a08,
- 0x00080808,
- 0x080a0000,
- 0x080a0808,
- 0x080a0808,
- 0x0a0a0a08,
- 0xa0a0a0a0,
- 0x80a0a080,
- 0x8080a0a0,
- 0x00008080,
- 0x80a00000,
- 0x80a080a0,
- 0xa080a0a0,
- 0x8080a0a0,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x99999000,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb90,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00aaa888,
- 0x22000000,
- 0x2222b222,
- 0x22222222,
- 0x222222b2,
- 0xb2222220,
- 0x22222222,
- 0x22d22222,
- 0x00000222,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x33000000,
- 0x3333b333,
- 0x33333333,
- 0x333333b3,
- 0xb3333330,
- 0x33333333,
- 0x33d33333,
- 0x00000333,
- 0x22000000,
- 0x2222a222,
- 0x22222222,
- 0x222222a2,
- 0xa2222220,
- 0x22222222,
- 0x22c22222,
- 0x00000222,
- 0x99b99b00,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb99,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x08aaa888,
- 0x22222200,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0x22222222,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x11111111,
- 0xf1111111,
- 0x11111111,
- 0x11f11111,
- 0x01111111,
- 0xbb9bb900,
- 0xb9b9bb99,
- 0xb99bbbbb,
- 0xbbbb9b9b,
- 0xb9bb99bb,
- 0xb99999b9,
- 0xb9b9b99b,
- 0x00000bbb,
- 0xaa000000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xa8aa88aa,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x0a888aaa,
- 0xaa000000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xa8aa88a0,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x00000aaa,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0xbbbbbb00,
- 0x999bbbbb,
- 0x9bb99b9b,
- 0xb9b9b9bb,
- 0xb9b99bbb,
- 0xb9b9b9bb,
- 0xb9bb9b99,
- 0x00000999,
- 0x8a000000,
- 0xaa88a888,
- 0xa88888aa,
- 0xa88a8a88,
- 0xa88aa88a,
- 0x88a8aaaa,
- 0xa8aa8aaa,
- 0x0888a88a,
- 0x0b0b0b00,
- 0x090b0b0b,
- 0x0b090b0b,
- 0x0909090b,
- 0x09090b0b,
- 0x09090b0b,
- 0x09090b09,
- 0x00000909,
- 0x0a000000,
- 0x0a080808,
- 0x080a080a,
- 0x080a0a08,
- 0x080a080a,
- 0x0808080a,
- 0x0a0a0a08,
- 0x0808080a,
- 0xb0b0b000,
- 0x9090b0b0,
- 0x90b09090,
- 0xb0b0b090,
- 0xb0b090b0,
- 0x90b0b0b0,
- 0xb0b09090,
- 0x00000090,
- 0x80000000,
- 0xa080a080,
- 0xa08080a0,
- 0xa0808080,
- 0xa080a080,
- 0x80a0a0a0,
- 0xa0a080a0,
- 0x00a0a0a0,
- 0x22000000,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0xf2222220,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00000111,
- 0x33000000,
- 0x3333f333,
- 0x33333333,
- 0x333333f3,
- 0xf3333330,
- 0x33333333,
- 0x33f33333,
- 0x00000333,
- 0x22000000,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0xf2222220,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x99000000,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb90,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88888000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00aaa888,
- 0x88a88a00,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x08aaa888,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 tdtrn_tbl_rev0[] = {
- 0x061c061c,
- 0x0050ee68,
- 0xf592fe36,
- 0xfe5212f6,
- 0x00000c38,
- 0xfe5212f6,
- 0xf592fe36,
- 0x0050ee68,
- 0x061c061c,
- 0xee680050,
- 0xfe36f592,
- 0x12f6fe52,
- 0x0c380000,
- 0x12f6fe52,
- 0xfe36f592,
- 0xee680050,
- 0x061c061c,
- 0x0050ee68,
- 0xf592fe36,
- 0xfe5212f6,
- 0x00000c38,
- 0xfe5212f6,
- 0xf592fe36,
- 0x0050ee68,
- 0x061c061c,
- 0xee680050,
- 0xfe36f592,
- 0x12f6fe52,
- 0x0c380000,
- 0x12f6fe52,
- 0xfe36f592,
- 0xee680050,
- 0x05e305e3,
- 0x004def0c,
- 0xf5f3fe47,
- 0xfe611246,
- 0x00000bc7,
- 0xfe611246,
- 0xf5f3fe47,
- 0x004def0c,
- 0x05e305e3,
- 0xef0c004d,
- 0xfe47f5f3,
- 0x1246fe61,
- 0x0bc70000,
- 0x1246fe61,
- 0xfe47f5f3,
- 0xef0c004d,
- 0x05e305e3,
- 0x004def0c,
- 0xf5f3fe47,
- 0xfe611246,
- 0x00000bc7,
- 0xfe611246,
- 0xf5f3fe47,
- 0x004def0c,
- 0x05e305e3,
- 0xef0c004d,
- 0xfe47f5f3,
- 0x1246fe61,
- 0x0bc70000,
- 0x1246fe61,
- 0xfe47f5f3,
- 0xef0c004d,
- 0xfa58fa58,
- 0xf895043b,
- 0xff4c09c0,
- 0xfbc6ffa8,
- 0xfb84f384,
- 0x0798f6f9,
- 0x05760122,
- 0x058409f6,
- 0x0b500000,
- 0x05b7f542,
- 0x08860432,
- 0x06ddfee7,
- 0xfb84f384,
- 0xf9d90664,
- 0xf7e8025c,
- 0x00fff7bd,
- 0x05a805a8,
- 0xf7bd00ff,
- 0x025cf7e8,
- 0x0664f9d9,
- 0xf384fb84,
- 0xfee706dd,
- 0x04320886,
- 0xf54205b7,
- 0x00000b50,
- 0x09f60584,
- 0x01220576,
- 0xf6f90798,
- 0xf384fb84,
- 0xffa8fbc6,
- 0x09c0ff4c,
- 0x043bf895,
- 0x02d402d4,
- 0x07de0270,
- 0xfc96079c,
- 0xf90afe94,
- 0xfe00ff2c,
- 0x02d4065d,
- 0x092a0096,
- 0x0014fbb8,
- 0xfd2cfd2c,
- 0x076afb3c,
- 0x0096f752,
- 0xf991fd87,
- 0xfb2c0200,
- 0xfeb8f960,
- 0x08e0fc96,
- 0x049802a8,
- 0xfd2cfd2c,
- 0x02a80498,
- 0xfc9608e0,
- 0xf960feb8,
- 0x0200fb2c,
- 0xfd87f991,
- 0xf7520096,
- 0xfb3c076a,
- 0xfd2cfd2c,
- 0xfbb80014,
- 0x0096092a,
- 0x065d02d4,
- 0xff2cfe00,
- 0xfe94f90a,
- 0x079cfc96,
- 0x027007de,
- 0x02d402d4,
- 0x027007de,
- 0x079cfc96,
- 0xfe94f90a,
- 0xff2cfe00,
- 0x065d02d4,
- 0x0096092a,
- 0xfbb80014,
- 0xfd2cfd2c,
- 0xfb3c076a,
- 0xf7520096,
- 0xfd87f991,
- 0x0200fb2c,
- 0xf960feb8,
- 0xfc9608e0,
- 0x02a80498,
- 0xfd2cfd2c,
- 0x049802a8,
- 0x08e0fc96,
- 0xfeb8f960,
- 0xfb2c0200,
- 0xf991fd87,
- 0x0096f752,
- 0x076afb3c,
- 0xfd2cfd2c,
- 0x0014fbb8,
- 0x092a0096,
- 0x02d4065d,
- 0xfe00ff2c,
- 0xf90afe94,
- 0xfc96079c,
- 0x07de0270,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x062a0000,
- 0xfefa0759,
- 0x08b80908,
- 0xf396fc2d,
- 0xf9d6045c,
- 0xfc4ef608,
- 0xf748f596,
- 0x07b207bf,
- 0x062a062a,
- 0xf84ef841,
- 0xf748f596,
- 0x03b209f8,
- 0xf9d6045c,
- 0x0c6a03d3,
- 0x08b80908,
- 0x0106f8a7,
- 0x062a0000,
- 0xfefaf8a7,
- 0x08b8f6f8,
- 0xf39603d3,
- 0xf9d6fba4,
- 0xfc4e09f8,
- 0xf7480a6a,
- 0x07b2f841,
- 0x062af9d6,
- 0xf84e07bf,
- 0xf7480a6a,
- 0x03b2f608,
- 0xf9d6fba4,
- 0x0c6afc2d,
- 0x08b8f6f8,
- 0x01060759,
- 0x062a0000,
- 0xfefa0759,
- 0x08b80908,
- 0xf396fc2d,
- 0xf9d6045c,
- 0xfc4ef608,
- 0xf748f596,
- 0x07b207bf,
- 0x062a062a,
- 0xf84ef841,
- 0xf748f596,
- 0x03b209f8,
- 0xf9d6045c,
- 0x0c6a03d3,
- 0x08b80908,
- 0x0106f8a7,
- 0x062a0000,
- 0xfefaf8a7,
- 0x08b8f6f8,
- 0xf39603d3,
- 0xf9d6fba4,
- 0xfc4e09f8,
- 0xf7480a6a,
- 0x07b2f841,
- 0x062af9d6,
- 0xf84e07bf,
- 0xf7480a6a,
- 0x03b2f608,
- 0xf9d6fba4,
- 0x0c6afc2d,
- 0x08b8f6f8,
- 0x01060759,
- 0x061c061c,
- 0xff30009d,
- 0xffb21141,
- 0xfd87fb54,
- 0xf65dfe59,
- 0x02eef99e,
- 0x0166f03c,
- 0xfff809b6,
- 0x000008a4,
- 0x000af42b,
- 0x00eff577,
- 0xfa840bf2,
- 0xfc02ff51,
- 0x08260f67,
- 0xfff0036f,
- 0x0842f9c3,
- 0x00000000,
- 0x063df7be,
- 0xfc910010,
- 0xf099f7da,
- 0x00af03fe,
- 0xf40e057c,
- 0x0a89ff11,
- 0x0bd5fff6,
- 0xf75c0000,
- 0xf64a0008,
- 0x0fc4fe9a,
- 0x0662fd12,
- 0x01a709a3,
- 0x04ac0279,
- 0xeebf004e,
- 0xff6300d0,
- 0xf9e4f9e4,
- 0x00d0ff63,
- 0x004eeebf,
- 0x027904ac,
- 0x09a301a7,
- 0xfd120662,
- 0xfe9a0fc4,
- 0x0008f64a,
- 0x0000f75c,
- 0xfff60bd5,
- 0xff110a89,
- 0x057cf40e,
- 0x03fe00af,
- 0xf7daf099,
- 0x0010fc91,
- 0xf7be063d,
- 0x00000000,
- 0xf9c30842,
- 0x036ffff0,
- 0x0f670826,
- 0xff51fc02,
- 0x0bf2fa84,
- 0xf57700ef,
- 0xf42b000a,
- 0x08a40000,
- 0x09b6fff8,
- 0xf03c0166,
- 0xf99e02ee,
- 0xfe59f65d,
- 0xfb54fd87,
- 0x1141ffb2,
- 0x009dff30,
- 0x05e30000,
- 0xff060705,
- 0x085408a0,
- 0xf425fc59,
- 0xfa1d042a,
- 0xfc78f67a,
- 0xf7acf60e,
- 0x075a0766,
- 0x05e305e3,
- 0xf8a6f89a,
- 0xf7acf60e,
- 0x03880986,
- 0xfa1d042a,
- 0x0bdb03a7,
- 0x085408a0,
- 0x00faf8fb,
- 0x05e30000,
- 0xff06f8fb,
- 0x0854f760,
- 0xf42503a7,
- 0xfa1dfbd6,
- 0xfc780986,
- 0xf7ac09f2,
- 0x075af89a,
- 0x05e3fa1d,
- 0xf8a60766,
- 0xf7ac09f2,
- 0x0388f67a,
- 0xfa1dfbd6,
- 0x0bdbfc59,
- 0x0854f760,
- 0x00fa0705,
- 0x05e30000,
- 0xff060705,
- 0x085408a0,
- 0xf425fc59,
- 0xfa1d042a,
- 0xfc78f67a,
- 0xf7acf60e,
- 0x075a0766,
- 0x05e305e3,
- 0xf8a6f89a,
- 0xf7acf60e,
- 0x03880986,
- 0xfa1d042a,
- 0x0bdb03a7,
- 0x085408a0,
- 0x00faf8fb,
- 0x05e30000,
- 0xff06f8fb,
- 0x0854f760,
- 0xf42503a7,
- 0xfa1dfbd6,
- 0xfc780986,
- 0xf7ac09f2,
- 0x075af89a,
- 0x05e3fa1d,
- 0xf8a60766,
- 0xf7ac09f2,
- 0x0388f67a,
- 0xfa1dfbd6,
- 0x0bdbfc59,
- 0x0854f760,
- 0x00fa0705,
- 0xfa58fa58,
- 0xf8f0fe00,
- 0x0448073d,
- 0xfdc9fe46,
- 0xf9910258,
- 0x089d0407,
- 0xfd5cf71a,
- 0x02affde0,
- 0x083e0496,
- 0xff5a0740,
- 0xff7afd97,
- 0x00fe01f1,
- 0x0009082e,
- 0xfa94ff75,
- 0xfecdf8ea,
- 0xffb0f693,
- 0xfd2cfa58,
- 0x0433ff16,
- 0xfba405dd,
- 0xfa610341,
- 0x06a606cb,
- 0x0039fd2d,
- 0x0677fa97,
- 0x01fa05e0,
- 0xf896003e,
- 0x075a068b,
- 0x012cfc3e,
- 0xfa23f98d,
- 0xfc7cfd43,
- 0xff90fc0d,
- 0x01c10982,
- 0x00c601d6,
- 0xfd2cfd2c,
- 0x01d600c6,
- 0x098201c1,
- 0xfc0dff90,
- 0xfd43fc7c,
- 0xf98dfa23,
- 0xfc3e012c,
- 0x068b075a,
- 0x003ef896,
- 0x05e001fa,
- 0xfa970677,
- 0xfd2d0039,
- 0x06cb06a6,
- 0x0341fa61,
- 0x05ddfba4,
- 0xff160433,
- 0xfa58fd2c,
- 0xf693ffb0,
- 0xf8eafecd,
- 0xff75fa94,
- 0x082e0009,
- 0x01f100fe,
- 0xfd97ff7a,
- 0x0740ff5a,
- 0x0496083e,
- 0xfde002af,
- 0xf71afd5c,
- 0x0407089d,
- 0x0258f991,
- 0xfe46fdc9,
- 0x073d0448,
- 0xfe00f8f0,
- 0xfd2cfd2c,
- 0xfce00500,
- 0xfc09fddc,
- 0xfe680157,
- 0x04c70571,
- 0xfc3aff21,
- 0xfcd70228,
- 0x056d0277,
- 0x0200fe00,
- 0x0022f927,
- 0xfe3c032b,
- 0xfc44ff3c,
- 0x03e9fbdb,
- 0x04570313,
- 0x04c9ff5c,
- 0x000d03b8,
- 0xfa580000,
- 0xfbe900d2,
- 0xf9d0fe0b,
- 0x0125fdf9,
- 0x042501bf,
- 0x0328fa2b,
- 0xffa902f0,
- 0xfa250157,
- 0x0200fe00,
- 0x03740438,
- 0xff0405fd,
- 0x030cfe52,
- 0x0037fb39,
- 0xff6904c5,
- 0x04f8fd23,
- 0xfd31fc1b,
- 0xfd2cfd2c,
- 0xfc1bfd31,
- 0xfd2304f8,
- 0x04c5ff69,
- 0xfb390037,
- 0xfe52030c,
- 0x05fdff04,
- 0x04380374,
- 0xfe000200,
- 0x0157fa25,
- 0x02f0ffa9,
- 0xfa2b0328,
- 0x01bf0425,
- 0xfdf90125,
- 0xfe0bf9d0,
- 0x00d2fbe9,
- 0x0000fa58,
- 0x03b8000d,
- 0xff5c04c9,
- 0x03130457,
- 0xfbdb03e9,
- 0xff3cfc44,
- 0x032bfe3c,
- 0xf9270022,
- 0xfe000200,
- 0x0277056d,
- 0x0228fcd7,
- 0xff21fc3a,
- 0x057104c7,
- 0x0157fe68,
- 0xfddcfc09,
- 0x0500fce0,
- 0xfd2cfd2c,
- 0x0500fce0,
- 0xfddcfc09,
- 0x0157fe68,
- 0x057104c7,
- 0xff21fc3a,
- 0x0228fcd7,
- 0x0277056d,
- 0xfe000200,
- 0xf9270022,
- 0x032bfe3c,
- 0xff3cfc44,
- 0xfbdb03e9,
- 0x03130457,
- 0xff5c04c9,
- 0x03b8000d,
- 0x0000fa58,
- 0x00d2fbe9,
- 0xfe0bf9d0,
- 0xfdf90125,
- 0x01bf0425,
- 0xfa2b0328,
- 0x02f0ffa9,
- 0x0157fa25,
- 0xfe000200,
- 0x04380374,
- 0x05fdff04,
- 0xfe52030c,
- 0xfb390037,
- 0x04c5ff69,
- 0xfd2304f8,
- 0xfc1bfd31,
- 0xfd2cfd2c,
- 0xfd31fc1b,
- 0x04f8fd23,
- 0xff6904c5,
- 0x0037fb39,
- 0x030cfe52,
- 0xff0405fd,
- 0x03740438,
- 0x0200fe00,
- 0xfa250157,
- 0xffa902f0,
- 0x0328fa2b,
- 0x042501bf,
- 0x0125fdf9,
- 0xf9d0fe0b,
- 0xfbe900d2,
- 0xfa580000,
- 0x000d03b8,
- 0x04c9ff5c,
- 0x04570313,
- 0x03e9fbdb,
- 0xfc44ff3c,
- 0xfe3c032b,
- 0x0022f927,
- 0x0200fe00,
- 0x056d0277,
- 0xfcd70228,
- 0xfc3aff21,
- 0x04c70571,
- 0xfe680157,
- 0xfc09fddc,
- 0xfce00500,
- 0x05a80000,
- 0xff1006be,
- 0x0800084a,
- 0xf49cfc7e,
- 0xfa580400,
- 0xfc9cf6da,
- 0xf800f672,
- 0x0710071c,
- 0x05a805a8,
- 0xf8f0f8e4,
- 0xf800f672,
- 0x03640926,
- 0xfa580400,
- 0x0b640382,
- 0x0800084a,
- 0x00f0f942,
- 0x05a80000,
- 0xff10f942,
- 0x0800f7b6,
- 0xf49c0382,
- 0xfa58fc00,
- 0xfc9c0926,
- 0xf800098e,
- 0x0710f8e4,
- 0x05a8fa58,
- 0xf8f0071c,
- 0xf800098e,
- 0x0364f6da,
- 0xfa58fc00,
- 0x0b64fc7e,
- 0x0800f7b6,
- 0x00f006be,
- 0x05a80000,
- 0xff1006be,
- 0x0800084a,
- 0xf49cfc7e,
- 0xfa580400,
- 0xfc9cf6da,
- 0xf800f672,
- 0x0710071c,
- 0x05a805a8,
- 0xf8f0f8e4,
- 0xf800f672,
- 0x03640926,
- 0xfa580400,
- 0x0b640382,
- 0x0800084a,
- 0x00f0f942,
- 0x05a80000,
- 0xff10f942,
- 0x0800f7b6,
- 0xf49c0382,
- 0xfa58fc00,
- 0xfc9c0926,
- 0xf800098e,
- 0x0710f8e4,
- 0x05a8fa58,
- 0xf8f0071c,
- 0xf800098e,
- 0x0364f6da,
- 0xfa58fc00,
- 0x0b64fc7e,
- 0x0800f7b6,
- 0x00f006be,
-};
-
-const u32 intlv_tbl_rev0[] = {
- 0x00802070,
- 0x0671188d,
- 0x0a60192c,
- 0x0a300e46,
- 0x00c1188d,
- 0x080024d2,
- 0x00000070,
-};
-
-const u16 pilot_tbl_rev0[] = {
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0xff0a,
- 0xff82,
- 0xffa0,
- 0xff28,
- 0xffff,
- 0xffff,
- 0xffff,
- 0xffff,
- 0xff82,
- 0xffa0,
- 0xff28,
- 0xff0a,
- 0xffff,
- 0xffff,
- 0xffff,
- 0xffff,
- 0xf83f,
- 0xfa1f,
- 0xfa97,
- 0xfab5,
- 0xf2bd,
- 0xf0bf,
- 0xffff,
- 0xffff,
- 0xf017,
- 0xf815,
- 0xf215,
- 0xf095,
- 0xf035,
- 0xf01d,
- 0xffff,
- 0xffff,
- 0xff08,
- 0xff02,
- 0xff80,
- 0xff20,
- 0xff08,
- 0xff02,
- 0xff80,
- 0xff20,
- 0xf01f,
- 0xf817,
- 0xfa15,
- 0xf295,
- 0xf0b5,
- 0xf03d,
- 0xffff,
- 0xffff,
- 0xf82a,
- 0xfa0a,
- 0xfa82,
- 0xfaa0,
- 0xf2a8,
- 0xf0aa,
- 0xffff,
- 0xffff,
- 0xf002,
- 0xf800,
- 0xf200,
- 0xf080,
- 0xf020,
- 0xf008,
- 0xffff,
- 0xffff,
- 0xf00a,
- 0xf802,
- 0xfa00,
- 0xf280,
- 0xf0a0,
- 0xf028,
- 0xffff,
- 0xffff,
-};
-
-const u32 pltlut_tbl_rev0[] = {
- 0x76540123,
- 0x62407351,
- 0x76543201,
- 0x76540213,
- 0x76540123,
- 0x76430521,
-};
-
-const u32 tdi_tbl20_ant0_rev0[] = {
- 0x00091226,
- 0x000a1429,
- 0x000b56ad,
- 0x000c58b0,
- 0x000d5ab3,
- 0x000e9cb6,
- 0x000f9eba,
- 0x0000c13d,
- 0x00020301,
- 0x00030504,
- 0x00040708,
- 0x0005090b,
- 0x00064b8e,
- 0x00095291,
- 0x000a5494,
- 0x000b9718,
- 0x000c9927,
- 0x000d9b2a,
- 0x000edd2e,
- 0x000fdf31,
- 0x000101b4,
- 0x000243b7,
- 0x000345bb,
- 0x000447be,
- 0x00058982,
- 0x00068c05,
- 0x00099309,
- 0x000a950c,
- 0x000bd78f,
- 0x000cd992,
- 0x000ddb96,
- 0x000f1d99,
- 0x00005fa8,
- 0x0001422c,
- 0x0002842f,
- 0x00038632,
- 0x00048835,
- 0x0005ca38,
- 0x0006ccbc,
- 0x0009d3bf,
- 0x000b1603,
- 0x000c1806,
- 0x000d1a0a,
- 0x000e1c0d,
- 0x000f5e10,
- 0x00008093,
- 0x00018297,
- 0x0002c49a,
- 0x0003c680,
- 0x0004c880,
- 0x00060b00,
- 0x00070d00,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 tdi_tbl20_ant1_rev0[] = {
- 0x00014b26,
- 0x00028d29,
- 0x000393ad,
- 0x00049630,
- 0x0005d833,
- 0x0006da36,
- 0x00099c3a,
- 0x000a9e3d,
- 0x000bc081,
- 0x000cc284,
- 0x000dc488,
- 0x000f068b,
- 0x0000488e,
- 0x00018b91,
- 0x0002d214,
- 0x0003d418,
- 0x0004d6a7,
- 0x000618aa,
- 0x00071aae,
- 0x0009dcb1,
- 0x000b1eb4,
- 0x000c0137,
- 0x000d033b,
- 0x000e053e,
- 0x000f4702,
- 0x00008905,
- 0x00020c09,
- 0x0003128c,
- 0x0004148f,
- 0x00051712,
- 0x00065916,
- 0x00091b19,
- 0x000a1d28,
- 0x000b5f2c,
- 0x000c41af,
- 0x000d43b2,
- 0x000e85b5,
- 0x000f87b8,
- 0x0000c9bc,
- 0x00024cbf,
- 0x00035303,
- 0x00045506,
- 0x0005978a,
- 0x0006998d,
- 0x00095b90,
- 0x000a5d93,
- 0x000b9f97,
- 0x000c821a,
- 0x000d8400,
- 0x000ec600,
- 0x000fc800,
- 0x00010a00,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 tdi_tbl40_ant0_rev0[] = {
- 0x0011a346,
- 0x00136ccf,
- 0x0014f5d9,
- 0x001641e2,
- 0x0017cb6b,
- 0x00195475,
- 0x001b2383,
- 0x001cad0c,
- 0x001e7616,
- 0x0000821f,
- 0x00020ba8,
- 0x0003d4b2,
- 0x00056447,
- 0x00072dd0,
- 0x0008b6da,
- 0x000a02e3,
- 0x000b8c6c,
- 0x000d15f6,
- 0x0011e484,
- 0x0013ae0d,
- 0x00153717,
- 0x00168320,
- 0x00180ca9,
- 0x00199633,
- 0x001b6548,
- 0x001ceed1,
- 0x001eb7db,
- 0x0000c3e4,
- 0x00024d6d,
- 0x000416f7,
- 0x0005a585,
- 0x00076f0f,
- 0x0008f818,
- 0x000a4421,
- 0x000bcdab,
- 0x000d9734,
- 0x00122649,
- 0x0013efd2,
- 0x001578dc,
- 0x0016c4e5,
- 0x00184e6e,
- 0x001a17f8,
- 0x001ba686,
- 0x001d3010,
- 0x001ef999,
- 0x00010522,
- 0x00028eac,
- 0x00045835,
- 0x0005e74a,
- 0x0007b0d3,
- 0x00093a5d,
- 0x000a85e6,
- 0x000c0f6f,
- 0x000dd8f9,
- 0x00126787,
- 0x00143111,
- 0x0015ba9a,
- 0x00170623,
- 0x00188fad,
- 0x001a5936,
- 0x001be84b,
- 0x001db1d4,
- 0x001f3b5e,
- 0x000146e7,
- 0x00031070,
- 0x000499fa,
- 0x00062888,
- 0x0007f212,
- 0x00097b9b,
- 0x000ac7a4,
- 0x000c50ae,
- 0x000e1a37,
- 0x0012a94c,
- 0x001472d5,
- 0x0015fc5f,
- 0x00174868,
- 0x0018d171,
- 0x001a9afb,
- 0x001c2989,
- 0x001df313,
- 0x001f7c9c,
- 0x000188a5,
- 0x000351af,
- 0x0004db38,
- 0x0006aa4d,
- 0x000833d7,
- 0x0009bd60,
- 0x000b0969,
- 0x000c9273,
- 0x000e5bfc,
- 0x00132a8a,
- 0x0014b414,
- 0x00163d9d,
- 0x001789a6,
- 0x001912b0,
- 0x001adc39,
- 0x001c6bce,
- 0x001e34d8,
- 0x001fbe61,
- 0x0001ca6a,
- 0x00039374,
- 0x00051cfd,
- 0x0006ec0b,
- 0x00087515,
- 0x0009fe9e,
- 0x000b4aa7,
- 0x000cd3b1,
- 0x000e9d3a,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 tdi_tbl40_ant1_rev0[] = {
- 0x001edb36,
- 0x000129ca,
- 0x0002b353,
- 0x00047cdd,
- 0x0005c8e6,
- 0x000791ef,
- 0x00091bf9,
- 0x000aaa07,
- 0x000c3391,
- 0x000dfd1a,
- 0x00120923,
- 0x0013d22d,
- 0x00155c37,
- 0x0016eacb,
- 0x00187454,
- 0x001a3dde,
- 0x001b89e7,
- 0x001d12f0,
- 0x001f1cfa,
- 0x00016b88,
- 0x00033492,
- 0x0004be1b,
- 0x00060a24,
- 0x0007d32e,
- 0x00095d38,
- 0x000aec4c,
- 0x000c7555,
- 0x000e3edf,
- 0x00124ae8,
- 0x001413f1,
- 0x0015a37b,
- 0x00172c89,
- 0x0018b593,
- 0x001a419c,
- 0x001bcb25,
- 0x001d942f,
- 0x001f63b9,
- 0x0001ad4d,
- 0x00037657,
- 0x0004c260,
- 0x00068be9,
- 0x000814f3,
- 0x0009a47c,
- 0x000b2d8a,
- 0x000cb694,
- 0x000e429d,
- 0x00128c26,
- 0x001455b0,
- 0x0015e4ba,
- 0x00176e4e,
- 0x0018f758,
- 0x001a8361,
- 0x001c0cea,
- 0x001dd674,
- 0x001fa57d,
- 0x0001ee8b,
- 0x0003b795,
- 0x0005039e,
- 0x0006cd27,
- 0x000856b1,
- 0x0009e5c6,
- 0x000b6f4f,
- 0x000cf859,
- 0x000e8462,
- 0x00130deb,
- 0x00149775,
- 0x00162603,
- 0x0017af8c,
- 0x00193896,
- 0x001ac49f,
- 0x001c4e28,
- 0x001e17b2,
- 0x0000a6c7,
- 0x00023050,
- 0x0003f9da,
- 0x00054563,
- 0x00070eec,
- 0x00089876,
- 0x000a2704,
- 0x000bb08d,
- 0x000d3a17,
- 0x001185a0,
- 0x00134f29,
- 0x0014d8b3,
- 0x001667c8,
- 0x0017f151,
- 0x00197adb,
- 0x001b0664,
- 0x001c8fed,
- 0x001e5977,
- 0x0000e805,
- 0x0002718f,
- 0x00043b18,
- 0x000586a1,
- 0x0007502b,
- 0x0008d9b4,
- 0x000a68c9,
- 0x000bf252,
- 0x000dbbdc,
- 0x0011c7e5,
- 0x001390ee,
- 0x00151a78,
- 0x0016a906,
- 0x00183290,
- 0x0019bc19,
- 0x001b4822,
- 0x001cd12c,
- 0x001e9ab5,
- 0x00000000,
- 0x00000000,
-};
-
-const u16 bdi_tbl_rev0[] = {
- 0x0070,
- 0x0126,
- 0x012c,
- 0x0246,
- 0x048d,
- 0x04d2,
-};
-
-const u32 chanest_tbl_rev0[] = {
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
-};
-
-const u8 mcs_tbl_rev0[] = {
- 0x00,
- 0x08,
- 0x0a,
- 0x10,
- 0x12,
- 0x19,
- 0x1a,
- 0x1c,
- 0x40,
- 0x48,
- 0x4a,
- 0x50,
- 0x52,
- 0x59,
- 0x5a,
- 0x5c,
- 0x80,
- 0x88,
- 0x8a,
- 0x90,
- 0x92,
- 0x99,
- 0x9a,
- 0x9c,
- 0xc0,
- 0xc8,
- 0xca,
- 0xd0,
- 0xd2,
- 0xd9,
- 0xda,
- 0xdc,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x02,
- 0x04,
- 0x08,
- 0x09,
- 0x0a,
- 0x0c,
- 0x10,
- 0x11,
- 0x12,
- 0x14,
- 0x18,
- 0x19,
- 0x1a,
- 0x1c,
- 0x20,
- 0x21,
- 0x22,
- 0x24,
- 0x40,
- 0x41,
- 0x42,
- 0x44,
- 0x48,
- 0x49,
- 0x4a,
- 0x4c,
- 0x50,
- 0x51,
- 0x52,
- 0x54,
- 0x58,
- 0x59,
- 0x5a,
- 0x5c,
- 0x60,
- 0x61,
- 0x62,
- 0x64,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
-};
-
-const u32 noise_var_tbl0_rev0[] = {
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
-};
-
-const u32 noise_var_tbl1_rev0[] = {
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
-};
-
-const u8 est_pwr_lut_core0_rev0[] = {
- 0x50,
- 0x4f,
- 0x4e,
- 0x4d,
- 0x4c,
- 0x4b,
- 0x4a,
- 0x49,
- 0x48,
- 0x47,
- 0x46,
- 0x45,
- 0x44,
- 0x43,
- 0x42,
- 0x41,
- 0x40,
- 0x3f,
- 0x3e,
- 0x3d,
- 0x3c,
- 0x3b,
- 0x3a,
- 0x39,
- 0x38,
- 0x37,
- 0x36,
- 0x35,
- 0x34,
- 0x33,
- 0x32,
- 0x31,
- 0x30,
- 0x2f,
- 0x2e,
- 0x2d,
- 0x2c,
- 0x2b,
- 0x2a,
- 0x29,
- 0x28,
- 0x27,
- 0x26,
- 0x25,
- 0x24,
- 0x23,
- 0x22,
- 0x21,
- 0x20,
- 0x1f,
- 0x1e,
- 0x1d,
- 0x1c,
- 0x1b,
- 0x1a,
- 0x19,
- 0x18,
- 0x17,
- 0x16,
- 0x15,
- 0x14,
- 0x13,
- 0x12,
- 0x11,
-};
-
-const u8 est_pwr_lut_core1_rev0[] = {
- 0x50,
- 0x4f,
- 0x4e,
- 0x4d,
- 0x4c,
- 0x4b,
- 0x4a,
- 0x49,
- 0x48,
- 0x47,
- 0x46,
- 0x45,
- 0x44,
- 0x43,
- 0x42,
- 0x41,
- 0x40,
- 0x3f,
- 0x3e,
- 0x3d,
- 0x3c,
- 0x3b,
- 0x3a,
- 0x39,
- 0x38,
- 0x37,
- 0x36,
- 0x35,
- 0x34,
- 0x33,
- 0x32,
- 0x31,
- 0x30,
- 0x2f,
- 0x2e,
- 0x2d,
- 0x2c,
- 0x2b,
- 0x2a,
- 0x29,
- 0x28,
- 0x27,
- 0x26,
- 0x25,
- 0x24,
- 0x23,
- 0x22,
- 0x21,
- 0x20,
- 0x1f,
- 0x1e,
- 0x1d,
- 0x1c,
- 0x1b,
- 0x1a,
- 0x19,
- 0x18,
- 0x17,
- 0x16,
- 0x15,
- 0x14,
- 0x13,
- 0x12,
- 0x11,
-};
-
-const u8 adj_pwr_lut_core0_rev0[] = {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
-};
-
-const u8 adj_pwr_lut_core1_rev0[] = {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
-};
-
-const u32 gainctrl_lut_core0_rev0[] = {
- 0x03cc2b44,
- 0x03cc2b42,
- 0x03cc2b40,
- 0x03cc2b3e,
- 0x03cc2b3d,
- 0x03cc2b3b,
- 0x03c82b44,
- 0x03c82b42,
- 0x03c82b40,
- 0x03c82b3e,
- 0x03c82b3d,
- 0x03c82b3b,
- 0x03c82b39,
- 0x03c82b38,
- 0x03c82b36,
- 0x03c82b34,
- 0x03c42b44,
- 0x03c42b42,
- 0x03c42b40,
- 0x03c42b3e,
- 0x03c42b3d,
- 0x03c42b3b,
- 0x03c42b39,
- 0x03c42b38,
- 0x03c42b36,
- 0x03c42b34,
- 0x03c42b33,
- 0x03c42b32,
- 0x03c42b30,
- 0x03c42b2f,
- 0x03c42b2d,
- 0x03c02b44,
- 0x03c02b42,
- 0x03c02b40,
- 0x03c02b3e,
- 0x03c02b3d,
- 0x03c02b3b,
- 0x03c02b39,
- 0x03c02b38,
- 0x03c02b36,
- 0x03c02b34,
- 0x03b02b44,
- 0x03b02b42,
- 0x03b02b40,
- 0x03b02b3e,
- 0x03b02b3d,
- 0x03b02b3b,
- 0x03b02b39,
- 0x03b02b38,
- 0x03b02b36,
- 0x03b02b34,
- 0x03b02b33,
- 0x03b02b32,
- 0x03b02b30,
- 0x03b02b2f,
- 0x03b02b2d,
- 0x03a02b44,
- 0x03a02b42,
- 0x03a02b40,
- 0x03a02b3e,
- 0x03a02b3d,
- 0x03a02b3b,
- 0x03a02b39,
- 0x03a02b38,
- 0x03a02b36,
- 0x03a02b34,
- 0x03902b44,
- 0x03902b42,
- 0x03902b40,
- 0x03902b3e,
- 0x03902b3d,
- 0x03902b3b,
- 0x03902b39,
- 0x03902b38,
- 0x03902b36,
- 0x03902b34,
- 0x03902b33,
- 0x03902b32,
- 0x03902b30,
- 0x03802b44,
- 0x03802b42,
- 0x03802b40,
- 0x03802b3e,
- 0x03802b3d,
- 0x03802b3b,
- 0x03802b39,
- 0x03802b38,
- 0x03802b36,
- 0x03802b34,
- 0x03802b33,
- 0x03802b32,
- 0x03802b30,
- 0x03802b2f,
- 0x03802b2d,
- 0x03802b2c,
- 0x03802b2b,
- 0x03802b2a,
- 0x03802b29,
- 0x03802b27,
- 0x03802b26,
- 0x03802b25,
- 0x03802b24,
- 0x03802b23,
- 0x03802b22,
- 0x03802b21,
- 0x03802b20,
- 0x03802b1f,
- 0x03802b1e,
- 0x03802b1e,
- 0x03802b1d,
- 0x03802b1c,
- 0x03802b1b,
- 0x03802b1a,
- 0x03802b1a,
- 0x03802b19,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x00002b00,
-};
-
-const u32 gainctrl_lut_core1_rev0[] = {
- 0x03cc2b44,
- 0x03cc2b42,
- 0x03cc2b40,
- 0x03cc2b3e,
- 0x03cc2b3d,
- 0x03cc2b3b,
- 0x03c82b44,
- 0x03c82b42,
- 0x03c82b40,
- 0x03c82b3e,
- 0x03c82b3d,
- 0x03c82b3b,
- 0x03c82b39,
- 0x03c82b38,
- 0x03c82b36,
- 0x03c82b34,
- 0x03c42b44,
- 0x03c42b42,
- 0x03c42b40,
- 0x03c42b3e,
- 0x03c42b3d,
- 0x03c42b3b,
- 0x03c42b39,
- 0x03c42b38,
- 0x03c42b36,
- 0x03c42b34,
- 0x03c42b33,
- 0x03c42b32,
- 0x03c42b30,
- 0x03c42b2f,
- 0x03c42b2d,
- 0x03c02b44,
- 0x03c02b42,
- 0x03c02b40,
- 0x03c02b3e,
- 0x03c02b3d,
- 0x03c02b3b,
- 0x03c02b39,
- 0x03c02b38,
- 0x03c02b36,
- 0x03c02b34,
- 0x03b02b44,
- 0x03b02b42,
- 0x03b02b40,
- 0x03b02b3e,
- 0x03b02b3d,
- 0x03b02b3b,
- 0x03b02b39,
- 0x03b02b38,
- 0x03b02b36,
- 0x03b02b34,
- 0x03b02b33,
- 0x03b02b32,
- 0x03b02b30,
- 0x03b02b2f,
- 0x03b02b2d,
- 0x03a02b44,
- 0x03a02b42,
- 0x03a02b40,
- 0x03a02b3e,
- 0x03a02b3d,
- 0x03a02b3b,
- 0x03a02b39,
- 0x03a02b38,
- 0x03a02b36,
- 0x03a02b34,
- 0x03902b44,
- 0x03902b42,
- 0x03902b40,
- 0x03902b3e,
- 0x03902b3d,
- 0x03902b3b,
- 0x03902b39,
- 0x03902b38,
- 0x03902b36,
- 0x03902b34,
- 0x03902b33,
- 0x03902b32,
- 0x03902b30,
- 0x03802b44,
- 0x03802b42,
- 0x03802b40,
- 0x03802b3e,
- 0x03802b3d,
- 0x03802b3b,
- 0x03802b39,
- 0x03802b38,
- 0x03802b36,
- 0x03802b34,
- 0x03802b33,
- 0x03802b32,
- 0x03802b30,
- 0x03802b2f,
- 0x03802b2d,
- 0x03802b2c,
- 0x03802b2b,
- 0x03802b2a,
- 0x03802b29,
- 0x03802b27,
- 0x03802b26,
- 0x03802b25,
- 0x03802b24,
- 0x03802b23,
- 0x03802b22,
- 0x03802b21,
- 0x03802b20,
- 0x03802b1f,
- 0x03802b1e,
- 0x03802b1e,
- 0x03802b1d,
- 0x03802b1c,
- 0x03802b1b,
- 0x03802b1a,
- 0x03802b1a,
- 0x03802b19,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x03802b18,
- 0x00002b00,
-};
-
-const u32 iq_lut_core0_rev0[] = {
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
-};
-
-const u32 iq_lut_core1_rev0[] = {
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
- 0x0000007f,
-};
-
-const u16 loft_lut_core0_rev0[] = {
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
-};
-
-const u16 loft_lut_core1_rev0[] = {
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
- 0x0000,
- 0x0101,
- 0x0002,
- 0x0103,
-};
-
-const mimophytbl_info_t mimophytbl_info_rev0_volatile[] = {
- {&bdi_tbl_rev0, sizeof(bdi_tbl_rev0) / sizeof(bdi_tbl_rev0[0]), 21, 0,
- 16}
- ,
- {&pltlut_tbl_rev0, sizeof(pltlut_tbl_rev0) / sizeof(pltlut_tbl_rev0[0]),
- 20, 0, 32}
- ,
- {&gainctrl_lut_core0_rev0,
- sizeof(gainctrl_lut_core0_rev0) / sizeof(gainctrl_lut_core0_rev0[0]),
- 26, 192, 32}
- ,
- {&gainctrl_lut_core1_rev0,
- sizeof(gainctrl_lut_core1_rev0) / sizeof(gainctrl_lut_core1_rev0[0]),
- 27, 192, 32}
- ,
-
- {&est_pwr_lut_core0_rev0,
- sizeof(est_pwr_lut_core0_rev0) / sizeof(est_pwr_lut_core0_rev0[0]), 26,
- 0, 8}
- ,
- {&est_pwr_lut_core1_rev0,
- sizeof(est_pwr_lut_core1_rev0) / sizeof(est_pwr_lut_core1_rev0[0]), 27,
- 0, 8}
- ,
- {&adj_pwr_lut_core0_rev0,
- sizeof(adj_pwr_lut_core0_rev0) / sizeof(adj_pwr_lut_core0_rev0[0]), 26,
- 64, 8}
- ,
- {&adj_pwr_lut_core1_rev0,
- sizeof(adj_pwr_lut_core1_rev0) / sizeof(adj_pwr_lut_core1_rev0[0]), 27,
- 64, 8}
- ,
- {&iq_lut_core0_rev0,
- sizeof(iq_lut_core0_rev0) / sizeof(iq_lut_core0_rev0[0]), 26, 320, 32}
- ,
- {&iq_lut_core1_rev0,
- sizeof(iq_lut_core1_rev0) / sizeof(iq_lut_core1_rev0[0]), 27, 320, 32}
- ,
- {&loft_lut_core0_rev0,
- sizeof(loft_lut_core0_rev0) / sizeof(loft_lut_core0_rev0[0]), 26, 448,
- 16}
- ,
- {&loft_lut_core1_rev0,
- sizeof(loft_lut_core1_rev0) / sizeof(loft_lut_core1_rev0[0]), 27, 448,
- 16}
- ,
-};
-
-const mimophytbl_info_t mimophytbl_info_rev0[] = {
- {&frame_struct_rev0,
- sizeof(frame_struct_rev0) / sizeof(frame_struct_rev0[0]), 10, 0, 32}
- ,
- {&frame_lut_rev0, sizeof(frame_lut_rev0) / sizeof(frame_lut_rev0[0]),
- 24, 0, 8}
- ,
- {&tmap_tbl_rev0, sizeof(tmap_tbl_rev0) / sizeof(tmap_tbl_rev0[0]), 12,
- 0, 32}
- ,
- {&tdtrn_tbl_rev0, sizeof(tdtrn_tbl_rev0) / sizeof(tdtrn_tbl_rev0[0]),
- 14, 0, 32}
- ,
- {&intlv_tbl_rev0, sizeof(intlv_tbl_rev0) / sizeof(intlv_tbl_rev0[0]),
- 13, 0, 32}
- ,
- {&pilot_tbl_rev0, sizeof(pilot_tbl_rev0) / sizeof(pilot_tbl_rev0[0]),
- 11, 0, 16}
- ,
- {&tdi_tbl20_ant0_rev0,
- sizeof(tdi_tbl20_ant0_rev0) / sizeof(tdi_tbl20_ant0_rev0[0]), 19, 128,
- 32}
- ,
- {&tdi_tbl20_ant1_rev0,
- sizeof(tdi_tbl20_ant1_rev0) / sizeof(tdi_tbl20_ant1_rev0[0]), 19, 256,
- 32}
- ,
- {&tdi_tbl40_ant0_rev0,
- sizeof(tdi_tbl40_ant0_rev0) / sizeof(tdi_tbl40_ant0_rev0[0]), 19, 640,
- 32}
- ,
- {&tdi_tbl40_ant1_rev0,
- sizeof(tdi_tbl40_ant1_rev0) / sizeof(tdi_tbl40_ant1_rev0[0]), 19, 768,
- 32}
- ,
- {&chanest_tbl_rev0,
- sizeof(chanest_tbl_rev0) / sizeof(chanest_tbl_rev0[0]), 22, 0, 32}
- ,
- {&mcs_tbl_rev0, sizeof(mcs_tbl_rev0) / sizeof(mcs_tbl_rev0[0]), 18, 0, 8}
- ,
- {&noise_var_tbl0_rev0,
- sizeof(noise_var_tbl0_rev0) / sizeof(noise_var_tbl0_rev0[0]), 16, 0,
- 32}
- ,
- {&noise_var_tbl1_rev0,
- sizeof(noise_var_tbl1_rev0) / sizeof(noise_var_tbl1_rev0[0]), 16, 128,
- 32}
- ,
-};
-
-const u32 mimophytbl_info_sz_rev0 =
- sizeof(mimophytbl_info_rev0) / sizeof(mimophytbl_info_rev0[0]);
-const u32 mimophytbl_info_sz_rev0_volatile =
- sizeof(mimophytbl_info_rev0_volatile) /
- sizeof(mimophytbl_info_rev0_volatile[0]);
-
-const u16 ant_swctrl_tbl_rev3[] = {
- 0x0082,
- 0x0082,
- 0x0211,
- 0x0222,
- 0x0328,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0144,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0188,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0082,
- 0x0082,
- 0x0211,
- 0x0222,
- 0x0328,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0144,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0188,
- 0x0000,
- 0x0000,
- 0x0000,
-};
-
-const u16 ant_swctrl_tbl_rev3_1[] = {
- 0x0022,
- 0x0022,
- 0x0011,
- 0x0022,
- 0x0022,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0011,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0022,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0022,
- 0x0022,
- 0x0011,
- 0x0022,
- 0x0022,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0011,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0022,
- 0x0000,
- 0x0000,
- 0x0000,
-};
-
-const u16 ant_swctrl_tbl_rev3_2[] = {
- 0x0088,
- 0x0088,
- 0x0044,
- 0x0088,
- 0x0088,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0044,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0088,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0088,
- 0x0088,
- 0x0044,
- 0x0088,
- 0x0088,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0044,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0088,
- 0x0000,
- 0x0000,
- 0x0000,
-};
-
-const u16 ant_swctrl_tbl_rev3_3[] = {
- 0x022,
- 0x022,
- 0x011,
- 0x022,
- 0x000,
- 0x000,
- 0x000,
- 0x000,
- 0x011,
- 0x000,
- 0x000,
- 0x000,
- 0x022,
- 0x000,
- 0x000,
- 0x3cc,
- 0x022,
- 0x022,
- 0x011,
- 0x022,
- 0x000,
- 0x000,
- 0x000,
- 0x000,
- 0x011,
- 0x000,
- 0x000,
- 0x000,
- 0x022,
- 0x000,
- 0x000,
- 0x3cc
-};
-
-const u32 frame_struct_rev3[] = {
- 0x08004a04,
- 0x00100000,
- 0x01000a05,
- 0x00100020,
- 0x09804506,
- 0x00100030,
- 0x09804507,
- 0x00100030,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x08004a0c,
- 0x00100004,
- 0x01000a0d,
- 0x00100024,
- 0x0980450e,
- 0x00100034,
- 0x0980450f,
- 0x00100034,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000a04,
- 0x00100000,
- 0x11008a05,
- 0x00100020,
- 0x1980c506,
- 0x00100030,
- 0x21810506,
- 0x00100030,
- 0x21810506,
- 0x00100030,
- 0x01800504,
- 0x00100030,
- 0x11808505,
- 0x00100030,
- 0x29814507,
- 0x01100030,
- 0x00000a04,
- 0x00100000,
- 0x11008a05,
- 0x00100020,
- 0x21810506,
- 0x00100030,
- 0x21810506,
- 0x00100030,
- 0x29814507,
- 0x01100030,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000a0c,
- 0x00100008,
- 0x11008a0d,
- 0x00100028,
- 0x1980c50e,
- 0x00100038,
- 0x2181050e,
- 0x00100038,
- 0x2181050e,
- 0x00100038,
- 0x0180050c,
- 0x00100038,
- 0x1180850d,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000a0c,
- 0x00100008,
- 0x11008a0d,
- 0x00100028,
- 0x2181050e,
- 0x00100038,
- 0x2181050e,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x08004a04,
- 0x00100000,
- 0x01000a05,
- 0x00100020,
- 0x1980c506,
- 0x00100030,
- 0x1980c506,
- 0x00100030,
- 0x11808504,
- 0x00100030,
- 0x3981ca05,
- 0x00100030,
- 0x29814507,
- 0x01100030,
- 0x00000000,
- 0x00000000,
- 0x10008a04,
- 0x00100000,
- 0x3981ca05,
- 0x00100030,
- 0x1980c506,
- 0x00100030,
- 0x29814507,
- 0x01100030,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x08004a0c,
- 0x00100008,
- 0x01000a0d,
- 0x00100028,
- 0x1980c50e,
- 0x00100038,
- 0x1980c50e,
- 0x00100038,
- 0x1180850c,
- 0x00100038,
- 0x3981ca0d,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x10008a0c,
- 0x00100008,
- 0x3981ca0d,
- 0x00100038,
- 0x1980c50e,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40021404,
- 0x00100000,
- 0x02001405,
- 0x00100040,
- 0x0b004a06,
- 0x01900060,
- 0x13008a06,
- 0x01900060,
- 0x13008a06,
- 0x01900060,
- 0x43020a04,
- 0x00100060,
- 0x1b00ca05,
- 0x00100060,
- 0x23010a07,
- 0x01500060,
- 0x40021404,
- 0x00100000,
- 0x1a00d405,
- 0x00100040,
- 0x13008a06,
- 0x01900060,
- 0x13008a06,
- 0x01900060,
- 0x23010a07,
- 0x01500060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x4002140c,
- 0x00100010,
- 0x0200140d,
- 0x00100050,
- 0x0b004a0e,
- 0x01900070,
- 0x13008a0e,
- 0x01900070,
- 0x13008a0e,
- 0x01900070,
- 0x43020a0c,
- 0x00100070,
- 0x1b00ca0d,
- 0x00100070,
- 0x23010a0f,
- 0x01500070,
- 0x4002140c,
- 0x00100010,
- 0x1a00d40d,
- 0x00100050,
- 0x13008a0e,
- 0x01900070,
- 0x13008a0e,
- 0x01900070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x50029404,
- 0x00100000,
- 0x32019405,
- 0x00100040,
- 0x0b004a06,
- 0x01900060,
- 0x0b004a06,
- 0x01900060,
- 0x5b02ca04,
- 0x00100060,
- 0x3b01d405,
- 0x00100060,
- 0x23010a07,
- 0x01500060,
- 0x00000000,
- 0x00000000,
- 0x5802d404,
- 0x00100000,
- 0x3b01d405,
- 0x00100060,
- 0x0b004a06,
- 0x01900060,
- 0x23010a07,
- 0x01500060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x5002940c,
- 0x00100010,
- 0x3201940d,
- 0x00100050,
- 0x0b004a0e,
- 0x01900070,
- 0x0b004a0e,
- 0x01900070,
- 0x5b02ca0c,
- 0x00100070,
- 0x3b01d40d,
- 0x00100070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
- 0x5802d40c,
- 0x00100010,
- 0x3b01d40d,
- 0x00100070,
- 0x0b004a0e,
- 0x01900070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40021404,
- 0x000f4800,
- 0x62031405,
- 0x00100040,
- 0x53028a06,
- 0x01900060,
- 0x53028a07,
- 0x01900060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x4002140c,
- 0x000f4808,
- 0x6203140d,
- 0x00100048,
- 0x53028a0e,
- 0x01900068,
- 0x53028a0f,
- 0x01900068,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000a0c,
- 0x00100004,
- 0x11008a0d,
- 0x00100024,
- 0x1980c50e,
- 0x00100034,
- 0x2181050e,
- 0x00100034,
- 0x2181050e,
- 0x00100034,
- 0x0180050c,
- 0x00100038,
- 0x1180850d,
- 0x00100038,
- 0x1181850d,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000a0c,
- 0x00100008,
- 0x11008a0d,
- 0x00100028,
- 0x2181050e,
- 0x00100038,
- 0x2181050e,
- 0x00100038,
- 0x1181850d,
- 0x00100038,
- 0x2981450f,
- 0x01100038,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x08004a04,
- 0x00100000,
- 0x01000a05,
- 0x00100020,
- 0x0180c506,
- 0x00100030,
- 0x0180c506,
- 0x00100030,
- 0x2180c50c,
- 0x00100030,
- 0x49820a0d,
- 0x0016a130,
- 0x41824a0d,
- 0x0016a130,
- 0x2981450f,
- 0x01100030,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x2000ca0c,
- 0x00100000,
- 0x49820a0d,
- 0x0016a130,
- 0x1980c50e,
- 0x00100030,
- 0x41824a0d,
- 0x0016a130,
- 0x2981450f,
- 0x01100030,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x4002140c,
- 0x00100008,
- 0x0200140d,
- 0x00100048,
- 0x0b004a0e,
- 0x01900068,
- 0x13008a0e,
- 0x01900068,
- 0x13008a0e,
- 0x01900068,
- 0x43020a0c,
- 0x00100070,
- 0x1b00ca0d,
- 0x00100070,
- 0x1b014a0d,
- 0x00100070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x4002140c,
- 0x00100010,
- 0x1a00d40d,
- 0x00100050,
- 0x13008a0e,
- 0x01900070,
- 0x13008a0e,
- 0x01900070,
- 0x1b014a0d,
- 0x00100070,
- 0x23010a0f,
- 0x01500070,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x50029404,
- 0x00100000,
- 0x32019405,
- 0x00100040,
- 0x03004a06,
- 0x01900060,
- 0x03004a06,
- 0x01900060,
- 0x6b030a0c,
- 0x00100060,
- 0x4b02140d,
- 0x0016a160,
- 0x4302540d,
- 0x0016a160,
- 0x23010a0f,
- 0x01500060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x6b03140c,
- 0x00100060,
- 0x4b02140d,
- 0x0016a160,
- 0x0b004a0e,
- 0x01900060,
- 0x4302540d,
- 0x0016a160,
- 0x23010a0f,
- 0x01500060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40021404,
- 0x00100000,
- 0x1a00d405,
- 0x00100040,
- 0x53028a06,
- 0x01900060,
- 0x5b02ca06,
- 0x01900060,
- 0x5b02ca06,
- 0x01900060,
- 0x43020a04,
- 0x00100060,
- 0x1b00ca05,
- 0x00100060,
- 0x53028a07,
- 0x0190c060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x4002140c,
- 0x00100010,
- 0x1a00d40d,
- 0x00100050,
- 0x53028a0e,
- 0x01900070,
- 0x5b02ca0e,
- 0x01900070,
- 0x5b02ca0e,
- 0x01900070,
- 0x43020a0c,
- 0x00100070,
- 0x1b00ca0d,
- 0x00100070,
- 0x53028a0f,
- 0x0190c070,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x40021404,
- 0x00100000,
- 0x1a00d405,
- 0x00100040,
- 0x5b02ca06,
- 0x01900060,
- 0x5b02ca06,
- 0x01900060,
- 0x53028a07,
- 0x0190c060,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x4002140c,
- 0x00100010,
- 0x1a00d40d,
- 0x00100050,
- 0x5b02ca0e,
- 0x01900070,
- 0x5b02ca0e,
- 0x01900070,
- 0x53028a0f,
- 0x0190c070,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u16 pilot_tbl_rev3[] = {
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0xff08,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0x80d5,
- 0xff0a,
- 0xff82,
- 0xffa0,
- 0xff28,
- 0xffff,
- 0xffff,
- 0xffff,
- 0xffff,
- 0xff82,
- 0xffa0,
- 0xff28,
- 0xff0a,
- 0xffff,
- 0xffff,
- 0xffff,
- 0xffff,
- 0xf83f,
- 0xfa1f,
- 0xfa97,
- 0xfab5,
- 0xf2bd,
- 0xf0bf,
- 0xffff,
- 0xffff,
- 0xf017,
- 0xf815,
- 0xf215,
- 0xf095,
- 0xf035,
- 0xf01d,
- 0xffff,
- 0xffff,
- 0xff08,
- 0xff02,
- 0xff80,
- 0xff20,
- 0xff08,
- 0xff02,
- 0xff80,
- 0xff20,
- 0xf01f,
- 0xf817,
- 0xfa15,
- 0xf295,
- 0xf0b5,
- 0xf03d,
- 0xffff,
- 0xffff,
- 0xf82a,
- 0xfa0a,
- 0xfa82,
- 0xfaa0,
- 0xf2a8,
- 0xf0aa,
- 0xffff,
- 0xffff,
- 0xf002,
- 0xf800,
- 0xf200,
- 0xf080,
- 0xf020,
- 0xf008,
- 0xffff,
- 0xffff,
- 0xf00a,
- 0xf802,
- 0xfa00,
- 0xf280,
- 0xf0a0,
- 0xf028,
- 0xffff,
- 0xffff,
-};
-
-const u32 tmap_tbl_rev3[] = {
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00000111,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x000aa888,
- 0x88880000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa2222220,
- 0x22222222,
- 0x22c22222,
- 0x00000222,
- 0x22000000,
- 0x2222a222,
- 0x22222222,
- 0x222222a2,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00011111,
- 0x11110000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0xa8aa88a0,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x00088aaa,
- 0xaaaa0000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xaaa8aaa0,
- 0x8aaa8aaa,
- 0xaa8a8a8a,
- 0x000aaa88,
- 0x8aaa0000,
- 0xaaa8a888,
- 0x8aa88a8a,
- 0x8a88a888,
- 0x08080a00,
- 0x0a08080a,
- 0x080a0a08,
- 0x00080808,
- 0x080a0000,
- 0x080a0808,
- 0x080a0808,
- 0x0a0a0a08,
- 0xa0a0a0a0,
- 0x80a0a080,
- 0x8080a0a0,
- 0x00008080,
- 0x80a00000,
- 0x80a080a0,
- 0xa080a0a0,
- 0x8080a0a0,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x99999000,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb90,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00aaa888,
- 0x22000000,
- 0x2222b222,
- 0x22222222,
- 0x222222b2,
- 0xb2222220,
- 0x22222222,
- 0x22d22222,
- 0x00000222,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x33000000,
- 0x3333b333,
- 0x33333333,
- 0x333333b3,
- 0xb3333330,
- 0x33333333,
- 0x33d33333,
- 0x00000333,
- 0x22000000,
- 0x2222a222,
- 0x22222222,
- 0x222222a2,
- 0xa2222220,
- 0x22222222,
- 0x22c22222,
- 0x00000222,
- 0x99b99b00,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb99,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x08aaa888,
- 0x22222200,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0x22222222,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x11111111,
- 0xf1111111,
- 0x11111111,
- 0x11f11111,
- 0x01111111,
- 0xbb9bb900,
- 0xb9b9bb99,
- 0xb99bbbbb,
- 0xbbbb9b9b,
- 0xb9bb99bb,
- 0xb99999b9,
- 0xb9b9b99b,
- 0x00000bbb,
- 0xaa000000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xa8aa88aa,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x0a888aaa,
- 0xaa000000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xa8aa88a0,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x00000aaa,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0xbbbbbb00,
- 0x999bbbbb,
- 0x9bb99b9b,
- 0xb9b9b9bb,
- 0xb9b99bbb,
- 0xb9b9b9bb,
- 0xb9bb9b99,
- 0x00000999,
- 0x8a000000,
- 0xaa88a888,
- 0xa88888aa,
- 0xa88a8a88,
- 0xa88aa88a,
- 0x88a8aaaa,
- 0xa8aa8aaa,
- 0x0888a88a,
- 0x0b0b0b00,
- 0x090b0b0b,
- 0x0b090b0b,
- 0x0909090b,
- 0x09090b0b,
- 0x09090b0b,
- 0x09090b09,
- 0x00000909,
- 0x0a000000,
- 0x0a080808,
- 0x080a080a,
- 0x080a0a08,
- 0x080a080a,
- 0x0808080a,
- 0x0a0a0a08,
- 0x0808080a,
- 0xb0b0b000,
- 0x9090b0b0,
- 0x90b09090,
- 0xb0b0b090,
- 0xb0b090b0,
- 0x90b0b0b0,
- 0xb0b09090,
- 0x00000090,
- 0x80000000,
- 0xa080a080,
- 0xa08080a0,
- 0xa0808080,
- 0xa080a080,
- 0x80a0a0a0,
- 0xa0a080a0,
- 0x00a0a0a0,
- 0x22000000,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0xf2222220,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00000111,
- 0x33000000,
- 0x3333f333,
- 0x33333333,
- 0x333333f3,
- 0xf3333330,
- 0x33333333,
- 0x33f33333,
- 0x00000333,
- 0x22000000,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0xf2222220,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x99000000,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb90,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88888000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00aaa888,
- 0x88a88a00,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x08aaa888,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 intlv_tbl_rev3[] = {
- 0x00802070,
- 0x0671188d,
- 0x0a60192c,
- 0x0a300e46,
- 0x00c1188d,
- 0x080024d2,
- 0x00000070,
-};
-
-const u32 tdtrn_tbl_rev3[] = {
- 0x061c061c,
- 0x0050ee68,
- 0xf592fe36,
- 0xfe5212f6,
- 0x00000c38,
- 0xfe5212f6,
- 0xf592fe36,
- 0x0050ee68,
- 0x061c061c,
- 0xee680050,
- 0xfe36f592,
- 0x12f6fe52,
- 0x0c380000,
- 0x12f6fe52,
- 0xfe36f592,
- 0xee680050,
- 0x061c061c,
- 0x0050ee68,
- 0xf592fe36,
- 0xfe5212f6,
- 0x00000c38,
- 0xfe5212f6,
- 0xf592fe36,
- 0x0050ee68,
- 0x061c061c,
- 0xee680050,
- 0xfe36f592,
- 0x12f6fe52,
- 0x0c380000,
- 0x12f6fe52,
- 0xfe36f592,
- 0xee680050,
- 0x05e305e3,
- 0x004def0c,
- 0xf5f3fe47,
- 0xfe611246,
- 0x00000bc7,
- 0xfe611246,
- 0xf5f3fe47,
- 0x004def0c,
- 0x05e305e3,
- 0xef0c004d,
- 0xfe47f5f3,
- 0x1246fe61,
- 0x0bc70000,
- 0x1246fe61,
- 0xfe47f5f3,
- 0xef0c004d,
- 0x05e305e3,
- 0x004def0c,
- 0xf5f3fe47,
- 0xfe611246,
- 0x00000bc7,
- 0xfe611246,
- 0xf5f3fe47,
- 0x004def0c,
- 0x05e305e3,
- 0xef0c004d,
- 0xfe47f5f3,
- 0x1246fe61,
- 0x0bc70000,
- 0x1246fe61,
- 0xfe47f5f3,
- 0xef0c004d,
- 0xfa58fa58,
- 0xf895043b,
- 0xff4c09c0,
- 0xfbc6ffa8,
- 0xfb84f384,
- 0x0798f6f9,
- 0x05760122,
- 0x058409f6,
- 0x0b500000,
- 0x05b7f542,
- 0x08860432,
- 0x06ddfee7,
- 0xfb84f384,
- 0xf9d90664,
- 0xf7e8025c,
- 0x00fff7bd,
- 0x05a805a8,
- 0xf7bd00ff,
- 0x025cf7e8,
- 0x0664f9d9,
- 0xf384fb84,
- 0xfee706dd,
- 0x04320886,
- 0xf54205b7,
- 0x00000b50,
- 0x09f60584,
- 0x01220576,
- 0xf6f90798,
- 0xf384fb84,
- 0xffa8fbc6,
- 0x09c0ff4c,
- 0x043bf895,
- 0x02d402d4,
- 0x07de0270,
- 0xfc96079c,
- 0xf90afe94,
- 0xfe00ff2c,
- 0x02d4065d,
- 0x092a0096,
- 0x0014fbb8,
- 0xfd2cfd2c,
- 0x076afb3c,
- 0x0096f752,
- 0xf991fd87,
- 0xfb2c0200,
- 0xfeb8f960,
- 0x08e0fc96,
- 0x049802a8,
- 0xfd2cfd2c,
- 0x02a80498,
- 0xfc9608e0,
- 0xf960feb8,
- 0x0200fb2c,
- 0xfd87f991,
- 0xf7520096,
- 0xfb3c076a,
- 0xfd2cfd2c,
- 0xfbb80014,
- 0x0096092a,
- 0x065d02d4,
- 0xff2cfe00,
- 0xfe94f90a,
- 0x079cfc96,
- 0x027007de,
- 0x02d402d4,
- 0x027007de,
- 0x079cfc96,
- 0xfe94f90a,
- 0xff2cfe00,
- 0x065d02d4,
- 0x0096092a,
- 0xfbb80014,
- 0xfd2cfd2c,
- 0xfb3c076a,
- 0xf7520096,
- 0xfd87f991,
- 0x0200fb2c,
- 0xf960feb8,
- 0xfc9608e0,
- 0x02a80498,
- 0xfd2cfd2c,
- 0x049802a8,
- 0x08e0fc96,
- 0xfeb8f960,
- 0xfb2c0200,
- 0xf991fd87,
- 0x0096f752,
- 0x076afb3c,
- 0xfd2cfd2c,
- 0x0014fbb8,
- 0x092a0096,
- 0x02d4065d,
- 0xfe00ff2c,
- 0xf90afe94,
- 0xfc96079c,
- 0x07de0270,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x062a0000,
- 0xfefa0759,
- 0x08b80908,
- 0xf396fc2d,
- 0xf9d6045c,
- 0xfc4ef608,
- 0xf748f596,
- 0x07b207bf,
- 0x062a062a,
- 0xf84ef841,
- 0xf748f596,
- 0x03b209f8,
- 0xf9d6045c,
- 0x0c6a03d3,
- 0x08b80908,
- 0x0106f8a7,
- 0x062a0000,
- 0xfefaf8a7,
- 0x08b8f6f8,
- 0xf39603d3,
- 0xf9d6fba4,
- 0xfc4e09f8,
- 0xf7480a6a,
- 0x07b2f841,
- 0x062af9d6,
- 0xf84e07bf,
- 0xf7480a6a,
- 0x03b2f608,
- 0xf9d6fba4,
- 0x0c6afc2d,
- 0x08b8f6f8,
- 0x01060759,
- 0x062a0000,
- 0xfefa0759,
- 0x08b80908,
- 0xf396fc2d,
- 0xf9d6045c,
- 0xfc4ef608,
- 0xf748f596,
- 0x07b207bf,
- 0x062a062a,
- 0xf84ef841,
- 0xf748f596,
- 0x03b209f8,
- 0xf9d6045c,
- 0x0c6a03d3,
- 0x08b80908,
- 0x0106f8a7,
- 0x062a0000,
- 0xfefaf8a7,
- 0x08b8f6f8,
- 0xf39603d3,
- 0xf9d6fba4,
- 0xfc4e09f8,
- 0xf7480a6a,
- 0x07b2f841,
- 0x062af9d6,
- 0xf84e07bf,
- 0xf7480a6a,
- 0x03b2f608,
- 0xf9d6fba4,
- 0x0c6afc2d,
- 0x08b8f6f8,
- 0x01060759,
- 0x061c061c,
- 0xff30009d,
- 0xffb21141,
- 0xfd87fb54,
- 0xf65dfe59,
- 0x02eef99e,
- 0x0166f03c,
- 0xfff809b6,
- 0x000008a4,
- 0x000af42b,
- 0x00eff577,
- 0xfa840bf2,
- 0xfc02ff51,
- 0x08260f67,
- 0xfff0036f,
- 0x0842f9c3,
- 0x00000000,
- 0x063df7be,
- 0xfc910010,
- 0xf099f7da,
- 0x00af03fe,
- 0xf40e057c,
- 0x0a89ff11,
- 0x0bd5fff6,
- 0xf75c0000,
- 0xf64a0008,
- 0x0fc4fe9a,
- 0x0662fd12,
- 0x01a709a3,
- 0x04ac0279,
- 0xeebf004e,
- 0xff6300d0,
- 0xf9e4f9e4,
- 0x00d0ff63,
- 0x004eeebf,
- 0x027904ac,
- 0x09a301a7,
- 0xfd120662,
- 0xfe9a0fc4,
- 0x0008f64a,
- 0x0000f75c,
- 0xfff60bd5,
- 0xff110a89,
- 0x057cf40e,
- 0x03fe00af,
- 0xf7daf099,
- 0x0010fc91,
- 0xf7be063d,
- 0x00000000,
- 0xf9c30842,
- 0x036ffff0,
- 0x0f670826,
- 0xff51fc02,
- 0x0bf2fa84,
- 0xf57700ef,
- 0xf42b000a,
- 0x08a40000,
- 0x09b6fff8,
- 0xf03c0166,
- 0xf99e02ee,
- 0xfe59f65d,
- 0xfb54fd87,
- 0x1141ffb2,
- 0x009dff30,
- 0x05e30000,
- 0xff060705,
- 0x085408a0,
- 0xf425fc59,
- 0xfa1d042a,
- 0xfc78f67a,
- 0xf7acf60e,
- 0x075a0766,
- 0x05e305e3,
- 0xf8a6f89a,
- 0xf7acf60e,
- 0x03880986,
- 0xfa1d042a,
- 0x0bdb03a7,
- 0x085408a0,
- 0x00faf8fb,
- 0x05e30000,
- 0xff06f8fb,
- 0x0854f760,
- 0xf42503a7,
- 0xfa1dfbd6,
- 0xfc780986,
- 0xf7ac09f2,
- 0x075af89a,
- 0x05e3fa1d,
- 0xf8a60766,
- 0xf7ac09f2,
- 0x0388f67a,
- 0xfa1dfbd6,
- 0x0bdbfc59,
- 0x0854f760,
- 0x00fa0705,
- 0x05e30000,
- 0xff060705,
- 0x085408a0,
- 0xf425fc59,
- 0xfa1d042a,
- 0xfc78f67a,
- 0xf7acf60e,
- 0x075a0766,
- 0x05e305e3,
- 0xf8a6f89a,
- 0xf7acf60e,
- 0x03880986,
- 0xfa1d042a,
- 0x0bdb03a7,
- 0x085408a0,
- 0x00faf8fb,
- 0x05e30000,
- 0xff06f8fb,
- 0x0854f760,
- 0xf42503a7,
- 0xfa1dfbd6,
- 0xfc780986,
- 0xf7ac09f2,
- 0x075af89a,
- 0x05e3fa1d,
- 0xf8a60766,
- 0xf7ac09f2,
- 0x0388f67a,
- 0xfa1dfbd6,
- 0x0bdbfc59,
- 0x0854f760,
- 0x00fa0705,
- 0xfa58fa58,
- 0xf8f0fe00,
- 0x0448073d,
- 0xfdc9fe46,
- 0xf9910258,
- 0x089d0407,
- 0xfd5cf71a,
- 0x02affde0,
- 0x083e0496,
- 0xff5a0740,
- 0xff7afd97,
- 0x00fe01f1,
- 0x0009082e,
- 0xfa94ff75,
- 0xfecdf8ea,
- 0xffb0f693,
- 0xfd2cfa58,
- 0x0433ff16,
- 0xfba405dd,
- 0xfa610341,
- 0x06a606cb,
- 0x0039fd2d,
- 0x0677fa97,
- 0x01fa05e0,
- 0xf896003e,
- 0x075a068b,
- 0x012cfc3e,
- 0xfa23f98d,
- 0xfc7cfd43,
- 0xff90fc0d,
- 0x01c10982,
- 0x00c601d6,
- 0xfd2cfd2c,
- 0x01d600c6,
- 0x098201c1,
- 0xfc0dff90,
- 0xfd43fc7c,
- 0xf98dfa23,
- 0xfc3e012c,
- 0x068b075a,
- 0x003ef896,
- 0x05e001fa,
- 0xfa970677,
- 0xfd2d0039,
- 0x06cb06a6,
- 0x0341fa61,
- 0x05ddfba4,
- 0xff160433,
- 0xfa58fd2c,
- 0xf693ffb0,
- 0xf8eafecd,
- 0xff75fa94,
- 0x082e0009,
- 0x01f100fe,
- 0xfd97ff7a,
- 0x0740ff5a,
- 0x0496083e,
- 0xfde002af,
- 0xf71afd5c,
- 0x0407089d,
- 0x0258f991,
- 0xfe46fdc9,
- 0x073d0448,
- 0xfe00f8f0,
- 0xfd2cfd2c,
- 0xfce00500,
- 0xfc09fddc,
- 0xfe680157,
- 0x04c70571,
- 0xfc3aff21,
- 0xfcd70228,
- 0x056d0277,
- 0x0200fe00,
- 0x0022f927,
- 0xfe3c032b,
- 0xfc44ff3c,
- 0x03e9fbdb,
- 0x04570313,
- 0x04c9ff5c,
- 0x000d03b8,
- 0xfa580000,
- 0xfbe900d2,
- 0xf9d0fe0b,
- 0x0125fdf9,
- 0x042501bf,
- 0x0328fa2b,
- 0xffa902f0,
- 0xfa250157,
- 0x0200fe00,
- 0x03740438,
- 0xff0405fd,
- 0x030cfe52,
- 0x0037fb39,
- 0xff6904c5,
- 0x04f8fd23,
- 0xfd31fc1b,
- 0xfd2cfd2c,
- 0xfc1bfd31,
- 0xfd2304f8,
- 0x04c5ff69,
- 0xfb390037,
- 0xfe52030c,
- 0x05fdff04,
- 0x04380374,
- 0xfe000200,
- 0x0157fa25,
- 0x02f0ffa9,
- 0xfa2b0328,
- 0x01bf0425,
- 0xfdf90125,
- 0xfe0bf9d0,
- 0x00d2fbe9,
- 0x0000fa58,
- 0x03b8000d,
- 0xff5c04c9,
- 0x03130457,
- 0xfbdb03e9,
- 0xff3cfc44,
- 0x032bfe3c,
- 0xf9270022,
- 0xfe000200,
- 0x0277056d,
- 0x0228fcd7,
- 0xff21fc3a,
- 0x057104c7,
- 0x0157fe68,
- 0xfddcfc09,
- 0x0500fce0,
- 0xfd2cfd2c,
- 0x0500fce0,
- 0xfddcfc09,
- 0x0157fe68,
- 0x057104c7,
- 0xff21fc3a,
- 0x0228fcd7,
- 0x0277056d,
- 0xfe000200,
- 0xf9270022,
- 0x032bfe3c,
- 0xff3cfc44,
- 0xfbdb03e9,
- 0x03130457,
- 0xff5c04c9,
- 0x03b8000d,
- 0x0000fa58,
- 0x00d2fbe9,
- 0xfe0bf9d0,
- 0xfdf90125,
- 0x01bf0425,
- 0xfa2b0328,
- 0x02f0ffa9,
- 0x0157fa25,
- 0xfe000200,
- 0x04380374,
- 0x05fdff04,
- 0xfe52030c,
- 0xfb390037,
- 0x04c5ff69,
- 0xfd2304f8,
- 0xfc1bfd31,
- 0xfd2cfd2c,
- 0xfd31fc1b,
- 0x04f8fd23,
- 0xff6904c5,
- 0x0037fb39,
- 0x030cfe52,
- 0xff0405fd,
- 0x03740438,
- 0x0200fe00,
- 0xfa250157,
- 0xffa902f0,
- 0x0328fa2b,
- 0x042501bf,
- 0x0125fdf9,
- 0xf9d0fe0b,
- 0xfbe900d2,
- 0xfa580000,
- 0x000d03b8,
- 0x04c9ff5c,
- 0x04570313,
- 0x03e9fbdb,
- 0xfc44ff3c,
- 0xfe3c032b,
- 0x0022f927,
- 0x0200fe00,
- 0x056d0277,
- 0xfcd70228,
- 0xfc3aff21,
- 0x04c70571,
- 0xfe680157,
- 0xfc09fddc,
- 0xfce00500,
- 0x05a80000,
- 0xff1006be,
- 0x0800084a,
- 0xf49cfc7e,
- 0xfa580400,
- 0xfc9cf6da,
- 0xf800f672,
- 0x0710071c,
- 0x05a805a8,
- 0xf8f0f8e4,
- 0xf800f672,
- 0x03640926,
- 0xfa580400,
- 0x0b640382,
- 0x0800084a,
- 0x00f0f942,
- 0x05a80000,
- 0xff10f942,
- 0x0800f7b6,
- 0xf49c0382,
- 0xfa58fc00,
- 0xfc9c0926,
- 0xf800098e,
- 0x0710f8e4,
- 0x05a8fa58,
- 0xf8f0071c,
- 0xf800098e,
- 0x0364f6da,
- 0xfa58fc00,
- 0x0b64fc7e,
- 0x0800f7b6,
- 0x00f006be,
- 0x05a80000,
- 0xff1006be,
- 0x0800084a,
- 0xf49cfc7e,
- 0xfa580400,
- 0xfc9cf6da,
- 0xf800f672,
- 0x0710071c,
- 0x05a805a8,
- 0xf8f0f8e4,
- 0xf800f672,
- 0x03640926,
- 0xfa580400,
- 0x0b640382,
- 0x0800084a,
- 0x00f0f942,
- 0x05a80000,
- 0xff10f942,
- 0x0800f7b6,
- 0xf49c0382,
- 0xfa58fc00,
- 0xfc9c0926,
- 0xf800098e,
- 0x0710f8e4,
- 0x05a8fa58,
- 0xf8f0071c,
- 0xf800098e,
- 0x0364f6da,
- 0xfa58fc00,
- 0x0b64fc7e,
- 0x0800f7b6,
- 0x00f006be,
-};
-
-const u32 noise_var_tbl_rev3[] = {
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
- 0x02110211,
- 0x0000014d,
-};
-
-const u16 mcs_tbl_rev3[] = {
- 0x0000,
- 0x0008,
- 0x000a,
- 0x0010,
- 0x0012,
- 0x0019,
- 0x001a,
- 0x001c,
- 0x0080,
- 0x0088,
- 0x008a,
- 0x0090,
- 0x0092,
- 0x0099,
- 0x009a,
- 0x009c,
- 0x0100,
- 0x0108,
- 0x010a,
- 0x0110,
- 0x0112,
- 0x0119,
- 0x011a,
- 0x011c,
- 0x0180,
- 0x0188,
- 0x018a,
- 0x0190,
- 0x0192,
- 0x0199,
- 0x019a,
- 0x019c,
- 0x0000,
- 0x0098,
- 0x00a0,
- 0x00a8,
- 0x009a,
- 0x00a2,
- 0x00aa,
- 0x0120,
- 0x0128,
- 0x0128,
- 0x0130,
- 0x0138,
- 0x0138,
- 0x0140,
- 0x0122,
- 0x012a,
- 0x012a,
- 0x0132,
- 0x013a,
- 0x013a,
- 0x0142,
- 0x01a8,
- 0x01b0,
- 0x01b8,
- 0x01b0,
- 0x01b8,
- 0x01c0,
- 0x01c8,
- 0x01c0,
- 0x01c8,
- 0x01d0,
- 0x01d0,
- 0x01d8,
- 0x01aa,
- 0x01b2,
- 0x01ba,
- 0x01b2,
- 0x01ba,
- 0x01c2,
- 0x01ca,
- 0x01c2,
- 0x01ca,
- 0x01d2,
- 0x01d2,
- 0x01da,
- 0x0001,
- 0x0002,
- 0x0004,
- 0x0009,
- 0x000c,
- 0x0011,
- 0x0014,
- 0x0018,
- 0x0020,
- 0x0021,
- 0x0022,
- 0x0024,
- 0x0081,
- 0x0082,
- 0x0084,
- 0x0089,
- 0x008c,
- 0x0091,
- 0x0094,
- 0x0098,
- 0x00a0,
- 0x00a1,
- 0x00a2,
- 0x00a4,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
- 0x0007,
-};
-
-const u32 tdi_tbl20_ant0_rev3[] = {
- 0x00091226,
- 0x000a1429,
- 0x000b56ad,
- 0x000c58b0,
- 0x000d5ab3,
- 0x000e9cb6,
- 0x000f9eba,
- 0x0000c13d,
- 0x00020301,
- 0x00030504,
- 0x00040708,
- 0x0005090b,
- 0x00064b8e,
- 0x00095291,
- 0x000a5494,
- 0x000b9718,
- 0x000c9927,
- 0x000d9b2a,
- 0x000edd2e,
- 0x000fdf31,
- 0x000101b4,
- 0x000243b7,
- 0x000345bb,
- 0x000447be,
- 0x00058982,
- 0x00068c05,
- 0x00099309,
- 0x000a950c,
- 0x000bd78f,
- 0x000cd992,
- 0x000ddb96,
- 0x000f1d99,
- 0x00005fa8,
- 0x0001422c,
- 0x0002842f,
- 0x00038632,
- 0x00048835,
- 0x0005ca38,
- 0x0006ccbc,
- 0x0009d3bf,
- 0x000b1603,
- 0x000c1806,
- 0x000d1a0a,
- 0x000e1c0d,
- 0x000f5e10,
- 0x00008093,
- 0x00018297,
- 0x0002c49a,
- 0x0003c680,
- 0x0004c880,
- 0x00060b00,
- 0x00070d00,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 tdi_tbl20_ant1_rev3[] = {
- 0x00014b26,
- 0x00028d29,
- 0x000393ad,
- 0x00049630,
- 0x0005d833,
- 0x0006da36,
- 0x00099c3a,
- 0x000a9e3d,
- 0x000bc081,
- 0x000cc284,
- 0x000dc488,
- 0x000f068b,
- 0x0000488e,
- 0x00018b91,
- 0x0002d214,
- 0x0003d418,
- 0x0004d6a7,
- 0x000618aa,
- 0x00071aae,
- 0x0009dcb1,
- 0x000b1eb4,
- 0x000c0137,
- 0x000d033b,
- 0x000e053e,
- 0x000f4702,
- 0x00008905,
- 0x00020c09,
- 0x0003128c,
- 0x0004148f,
- 0x00051712,
- 0x00065916,
- 0x00091b19,
- 0x000a1d28,
- 0x000b5f2c,
- 0x000c41af,
- 0x000d43b2,
- 0x000e85b5,
- 0x000f87b8,
- 0x0000c9bc,
- 0x00024cbf,
- 0x00035303,
- 0x00045506,
- 0x0005978a,
- 0x0006998d,
- 0x00095b90,
- 0x000a5d93,
- 0x000b9f97,
- 0x000c821a,
- 0x000d8400,
- 0x000ec600,
- 0x000fc800,
- 0x00010a00,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 tdi_tbl40_ant0_rev3[] = {
- 0x0011a346,
- 0x00136ccf,
- 0x0014f5d9,
- 0x001641e2,
- 0x0017cb6b,
- 0x00195475,
- 0x001b2383,
- 0x001cad0c,
- 0x001e7616,
- 0x0000821f,
- 0x00020ba8,
- 0x0003d4b2,
- 0x00056447,
- 0x00072dd0,
- 0x0008b6da,
- 0x000a02e3,
- 0x000b8c6c,
- 0x000d15f6,
- 0x0011e484,
- 0x0013ae0d,
- 0x00153717,
- 0x00168320,
- 0x00180ca9,
- 0x00199633,
- 0x001b6548,
- 0x001ceed1,
- 0x001eb7db,
- 0x0000c3e4,
- 0x00024d6d,
- 0x000416f7,
- 0x0005a585,
- 0x00076f0f,
- 0x0008f818,
- 0x000a4421,
- 0x000bcdab,
- 0x000d9734,
- 0x00122649,
- 0x0013efd2,
- 0x001578dc,
- 0x0016c4e5,
- 0x00184e6e,
- 0x001a17f8,
- 0x001ba686,
- 0x001d3010,
- 0x001ef999,
- 0x00010522,
- 0x00028eac,
- 0x00045835,
- 0x0005e74a,
- 0x0007b0d3,
- 0x00093a5d,
- 0x000a85e6,
- 0x000c0f6f,
- 0x000dd8f9,
- 0x00126787,
- 0x00143111,
- 0x0015ba9a,
- 0x00170623,
- 0x00188fad,
- 0x001a5936,
- 0x001be84b,
- 0x001db1d4,
- 0x001f3b5e,
- 0x000146e7,
- 0x00031070,
- 0x000499fa,
- 0x00062888,
- 0x0007f212,
- 0x00097b9b,
- 0x000ac7a4,
- 0x000c50ae,
- 0x000e1a37,
- 0x0012a94c,
- 0x001472d5,
- 0x0015fc5f,
- 0x00174868,
- 0x0018d171,
- 0x001a9afb,
- 0x001c2989,
- 0x001df313,
- 0x001f7c9c,
- 0x000188a5,
- 0x000351af,
- 0x0004db38,
- 0x0006aa4d,
- 0x000833d7,
- 0x0009bd60,
- 0x000b0969,
- 0x000c9273,
- 0x000e5bfc,
- 0x00132a8a,
- 0x0014b414,
- 0x00163d9d,
- 0x001789a6,
- 0x001912b0,
- 0x001adc39,
- 0x001c6bce,
- 0x001e34d8,
- 0x001fbe61,
- 0x0001ca6a,
- 0x00039374,
- 0x00051cfd,
- 0x0006ec0b,
- 0x00087515,
- 0x0009fe9e,
- 0x000b4aa7,
- 0x000cd3b1,
- 0x000e9d3a,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 tdi_tbl40_ant1_rev3[] = {
- 0x001edb36,
- 0x000129ca,
- 0x0002b353,
- 0x00047cdd,
- 0x0005c8e6,
- 0x000791ef,
- 0x00091bf9,
- 0x000aaa07,
- 0x000c3391,
- 0x000dfd1a,
- 0x00120923,
- 0x0013d22d,
- 0x00155c37,
- 0x0016eacb,
- 0x00187454,
- 0x001a3dde,
- 0x001b89e7,
- 0x001d12f0,
- 0x001f1cfa,
- 0x00016b88,
- 0x00033492,
- 0x0004be1b,
- 0x00060a24,
- 0x0007d32e,
- 0x00095d38,
- 0x000aec4c,
- 0x000c7555,
- 0x000e3edf,
- 0x00124ae8,
- 0x001413f1,
- 0x0015a37b,
- 0x00172c89,
- 0x0018b593,
- 0x001a419c,
- 0x001bcb25,
- 0x001d942f,
- 0x001f63b9,
- 0x0001ad4d,
- 0x00037657,
- 0x0004c260,
- 0x00068be9,
- 0x000814f3,
- 0x0009a47c,
- 0x000b2d8a,
- 0x000cb694,
- 0x000e429d,
- 0x00128c26,
- 0x001455b0,
- 0x0015e4ba,
- 0x00176e4e,
- 0x0018f758,
- 0x001a8361,
- 0x001c0cea,
- 0x001dd674,
- 0x001fa57d,
- 0x0001ee8b,
- 0x0003b795,
- 0x0005039e,
- 0x0006cd27,
- 0x000856b1,
- 0x0009e5c6,
- 0x000b6f4f,
- 0x000cf859,
- 0x000e8462,
- 0x00130deb,
- 0x00149775,
- 0x00162603,
- 0x0017af8c,
- 0x00193896,
- 0x001ac49f,
- 0x001c4e28,
- 0x001e17b2,
- 0x0000a6c7,
- 0x00023050,
- 0x0003f9da,
- 0x00054563,
- 0x00070eec,
- 0x00089876,
- 0x000a2704,
- 0x000bb08d,
- 0x000d3a17,
- 0x001185a0,
- 0x00134f29,
- 0x0014d8b3,
- 0x001667c8,
- 0x0017f151,
- 0x00197adb,
- 0x001b0664,
- 0x001c8fed,
- 0x001e5977,
- 0x0000e805,
- 0x0002718f,
- 0x00043b18,
- 0x000586a1,
- 0x0007502b,
- 0x0008d9b4,
- 0x000a68c9,
- 0x000bf252,
- 0x000dbbdc,
- 0x0011c7e5,
- 0x001390ee,
- 0x00151a78,
- 0x0016a906,
- 0x00183290,
- 0x0019bc19,
- 0x001b4822,
- 0x001cd12c,
- 0x001e9ab5,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 pltlut_tbl_rev3[] = {
- 0x76540213,
- 0x62407351,
- 0x76543210,
- 0x76540213,
- 0x76540213,
- 0x76430521,
-};
-
-const u32 chanest_tbl_rev3[] = {
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x44444444,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
- 0x10101010,
-};
-
-const u8 frame_lut_rev3[] = {
- 0x02,
- 0x04,
- 0x14,
- 0x14,
- 0x03,
- 0x05,
- 0x16,
- 0x16,
- 0x0a,
- 0x0c,
- 0x1c,
- 0x1c,
- 0x0b,
- 0x0d,
- 0x1e,
- 0x1e,
- 0x06,
- 0x08,
- 0x18,
- 0x18,
- 0x07,
- 0x09,
- 0x1a,
- 0x1a,
- 0x0e,
- 0x10,
- 0x20,
- 0x28,
- 0x0f,
- 0x11,
- 0x22,
- 0x2a,
-};
-
-const u8 est_pwr_lut_core0_rev3[] = {
- 0x55,
- 0x54,
- 0x54,
- 0x53,
- 0x52,
- 0x52,
- 0x51,
- 0x51,
- 0x50,
- 0x4f,
- 0x4f,
- 0x4e,
- 0x4e,
- 0x4d,
- 0x4c,
- 0x4c,
- 0x4b,
- 0x4a,
- 0x49,
- 0x49,
- 0x48,
- 0x47,
- 0x46,
- 0x46,
- 0x45,
- 0x44,
- 0x43,
- 0x42,
- 0x41,
- 0x40,
- 0x40,
- 0x3f,
- 0x3e,
- 0x3d,
- 0x3c,
- 0x3a,
- 0x39,
- 0x38,
- 0x37,
- 0x36,
- 0x35,
- 0x33,
- 0x32,
- 0x31,
- 0x2f,
- 0x2e,
- 0x2c,
- 0x2b,
- 0x29,
- 0x27,
- 0x25,
- 0x23,
- 0x21,
- 0x1f,
- 0x1d,
- 0x1a,
- 0x18,
- 0x15,
- 0x12,
- 0x0e,
- 0x0b,
- 0x07,
- 0x02,
- 0xfd,
-};
-
-const u8 est_pwr_lut_core1_rev3[] = {
- 0x55,
- 0x54,
- 0x54,
- 0x53,
- 0x52,
- 0x52,
- 0x51,
- 0x51,
- 0x50,
- 0x4f,
- 0x4f,
- 0x4e,
- 0x4e,
- 0x4d,
- 0x4c,
- 0x4c,
- 0x4b,
- 0x4a,
- 0x49,
- 0x49,
- 0x48,
- 0x47,
- 0x46,
- 0x46,
- 0x45,
- 0x44,
- 0x43,
- 0x42,
- 0x41,
- 0x40,
- 0x40,
- 0x3f,
- 0x3e,
- 0x3d,
- 0x3c,
- 0x3a,
- 0x39,
- 0x38,
- 0x37,
- 0x36,
- 0x35,
- 0x33,
- 0x32,
- 0x31,
- 0x2f,
- 0x2e,
- 0x2c,
- 0x2b,
- 0x29,
- 0x27,
- 0x25,
- 0x23,
- 0x21,
- 0x1f,
- 0x1d,
- 0x1a,
- 0x18,
- 0x15,
- 0x12,
- 0x0e,
- 0x0b,
- 0x07,
- 0x02,
- 0xfd,
-};
-
-const u8 adj_pwr_lut_core0_rev3[] = {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
-};
-
-const u8 adj_pwr_lut_core1_rev3[] = {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
-};
-
-const u32 gainctrl_lut_core0_rev3[] = {
- 0x5bf70044,
- 0x5bf70042,
- 0x5bf70040,
- 0x5bf7003e,
- 0x5bf7003c,
- 0x5bf7003b,
- 0x5bf70039,
- 0x5bf70037,
- 0x5bf70036,
- 0x5bf70034,
- 0x5bf70033,
- 0x5bf70031,
- 0x5bf70030,
- 0x5ba70044,
- 0x5ba70042,
- 0x5ba70040,
- 0x5ba7003e,
- 0x5ba7003c,
- 0x5ba7003b,
- 0x5ba70039,
- 0x5ba70037,
- 0x5ba70036,
- 0x5ba70034,
- 0x5ba70033,
- 0x5b770044,
- 0x5b770042,
- 0x5b770040,
- 0x5b77003e,
- 0x5b77003c,
- 0x5b77003b,
- 0x5b770039,
- 0x5b770037,
- 0x5b770036,
- 0x5b770034,
- 0x5b770033,
- 0x5b770031,
- 0x5b770030,
- 0x5b77002f,
- 0x5b77002d,
- 0x5b77002c,
- 0x5b470044,
- 0x5b470042,
- 0x5b470040,
- 0x5b47003e,
- 0x5b47003c,
- 0x5b47003b,
- 0x5b470039,
- 0x5b470037,
- 0x5b470036,
- 0x5b470034,
- 0x5b470033,
- 0x5b470031,
- 0x5b470030,
- 0x5b47002f,
- 0x5b47002d,
- 0x5b47002c,
- 0x5b47002b,
- 0x5b47002a,
- 0x5b270044,
- 0x5b270042,
- 0x5b270040,
- 0x5b27003e,
- 0x5b27003c,
- 0x5b27003b,
- 0x5b270039,
- 0x5b270037,
- 0x5b270036,
- 0x5b270034,
- 0x5b270033,
- 0x5b270031,
- 0x5b270030,
- 0x5b27002f,
- 0x5b170044,
- 0x5b170042,
- 0x5b170040,
- 0x5b17003e,
- 0x5b17003c,
- 0x5b17003b,
- 0x5b170039,
- 0x5b170037,
- 0x5b170036,
- 0x5b170034,
- 0x5b170033,
- 0x5b170031,
- 0x5b170030,
- 0x5b17002f,
- 0x5b17002d,
- 0x5b17002c,
- 0x5b17002b,
- 0x5b17002a,
- 0x5b170028,
- 0x5b170027,
- 0x5b170026,
- 0x5b170025,
- 0x5b170024,
- 0x5b170023,
- 0x5b070044,
- 0x5b070042,
- 0x5b070040,
- 0x5b07003e,
- 0x5b07003c,
- 0x5b07003b,
- 0x5b070039,
- 0x5b070037,
- 0x5b070036,
- 0x5b070034,
- 0x5b070033,
- 0x5b070031,
- 0x5b070030,
- 0x5b07002f,
- 0x5b07002d,
- 0x5b07002c,
- 0x5b07002b,
- 0x5b07002a,
- 0x5b070028,
- 0x5b070027,
- 0x5b070026,
- 0x5b070025,
- 0x5b070024,
- 0x5b070023,
- 0x5b070022,
- 0x5b070021,
- 0x5b070020,
- 0x5b07001f,
- 0x5b07001e,
- 0x5b07001d,
- 0x5b07001d,
- 0x5b07001c,
-};
-
-const u32 gainctrl_lut_core1_rev3[] = {
- 0x5bf70044,
- 0x5bf70042,
- 0x5bf70040,
- 0x5bf7003e,
- 0x5bf7003c,
- 0x5bf7003b,
- 0x5bf70039,
- 0x5bf70037,
- 0x5bf70036,
- 0x5bf70034,
- 0x5bf70033,
- 0x5bf70031,
- 0x5bf70030,
- 0x5ba70044,
- 0x5ba70042,
- 0x5ba70040,
- 0x5ba7003e,
- 0x5ba7003c,
- 0x5ba7003b,
- 0x5ba70039,
- 0x5ba70037,
- 0x5ba70036,
- 0x5ba70034,
- 0x5ba70033,
- 0x5b770044,
- 0x5b770042,
- 0x5b770040,
- 0x5b77003e,
- 0x5b77003c,
- 0x5b77003b,
- 0x5b770039,
- 0x5b770037,
- 0x5b770036,
- 0x5b770034,
- 0x5b770033,
- 0x5b770031,
- 0x5b770030,
- 0x5b77002f,
- 0x5b77002d,
- 0x5b77002c,
- 0x5b470044,
- 0x5b470042,
- 0x5b470040,
- 0x5b47003e,
- 0x5b47003c,
- 0x5b47003b,
- 0x5b470039,
- 0x5b470037,
- 0x5b470036,
- 0x5b470034,
- 0x5b470033,
- 0x5b470031,
- 0x5b470030,
- 0x5b47002f,
- 0x5b47002d,
- 0x5b47002c,
- 0x5b47002b,
- 0x5b47002a,
- 0x5b270044,
- 0x5b270042,
- 0x5b270040,
- 0x5b27003e,
- 0x5b27003c,
- 0x5b27003b,
- 0x5b270039,
- 0x5b270037,
- 0x5b270036,
- 0x5b270034,
- 0x5b270033,
- 0x5b270031,
- 0x5b270030,
- 0x5b27002f,
- 0x5b170044,
- 0x5b170042,
- 0x5b170040,
- 0x5b17003e,
- 0x5b17003c,
- 0x5b17003b,
- 0x5b170039,
- 0x5b170037,
- 0x5b170036,
- 0x5b170034,
- 0x5b170033,
- 0x5b170031,
- 0x5b170030,
- 0x5b17002f,
- 0x5b17002d,
- 0x5b17002c,
- 0x5b17002b,
- 0x5b17002a,
- 0x5b170028,
- 0x5b170027,
- 0x5b170026,
- 0x5b170025,
- 0x5b170024,
- 0x5b170023,
- 0x5b070044,
- 0x5b070042,
- 0x5b070040,
- 0x5b07003e,
- 0x5b07003c,
- 0x5b07003b,
- 0x5b070039,
- 0x5b070037,
- 0x5b070036,
- 0x5b070034,
- 0x5b070033,
- 0x5b070031,
- 0x5b070030,
- 0x5b07002f,
- 0x5b07002d,
- 0x5b07002c,
- 0x5b07002b,
- 0x5b07002a,
- 0x5b070028,
- 0x5b070027,
- 0x5b070026,
- 0x5b070025,
- 0x5b070024,
- 0x5b070023,
- 0x5b070022,
- 0x5b070021,
- 0x5b070020,
- 0x5b07001f,
- 0x5b07001e,
- 0x5b07001d,
- 0x5b07001d,
- 0x5b07001c,
-};
-
-const u32 iq_lut_core0_rev3[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 iq_lut_core1_rev3[] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u16 loft_lut_core0_rev3[] = {
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
-};
-
-const u16 loft_lut_core1_rev3[] = {
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
-};
-
-const u16 papd_comp_rfpwr_tbl_core0_rev3[] = {
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
-};
-
-const u16 papd_comp_rfpwr_tbl_core1_rev3[] = {
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x0036,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x002a,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x001e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x000e,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01fc,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01ee,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
- 0x01d6,
-};
-
-const u32 papd_comp_epsilon_tbl_core0_rev3[] = {
- 0x00000000,
- 0x00001fa0,
- 0x00019f78,
- 0x0001df7e,
- 0x03fa9f86,
- 0x03fd1f90,
- 0x03fe5f8a,
- 0x03fb1f94,
- 0x03fd9fa0,
- 0x00009f98,
- 0x03fd1fac,
- 0x03ff9fa2,
- 0x03fe9fae,
- 0x00001fae,
- 0x03fddfb4,
- 0x03ff1fb8,
- 0x03ff9fbc,
- 0x03ffdfbe,
- 0x03fe9fc2,
- 0x03fedfc6,
- 0x03fedfc6,
- 0x03ff9fc8,
- 0x03ff5fc6,
- 0x03fedfc2,
- 0x03ff9fc0,
- 0x03ff5fac,
- 0x03ff5fac,
- 0x03ff9fa2,
- 0x03ff9fa6,
- 0x03ff9faa,
- 0x03ff5fb0,
- 0x03ff5fb4,
- 0x03ff1fca,
- 0x03ff5fce,
- 0x03fcdfdc,
- 0x03fb4006,
- 0x00000030,
- 0x03ff808a,
- 0x03ff80da,
- 0x0000016c,
- 0x03ff8318,
- 0x03ff063a,
- 0x03fd8bd6,
- 0x00014ffe,
- 0x00034ffe,
- 0x00034ffe,
- 0x0003cffe,
- 0x00040ffe,
- 0x00040ffe,
- 0x0003cffe,
- 0x0003cffe,
- 0x00020ffe,
- 0x03fe0ffe,
- 0x03fdcffe,
- 0x03f94ffe,
- 0x03f54ffe,
- 0x03f44ffe,
- 0x03ef8ffe,
- 0x03ee0ffe,
- 0x03ebcffe,
- 0x03e8cffe,
- 0x03e74ffe,
- 0x03e4cffe,
- 0x03e38ffe,
-};
-
-const u32 papd_cal_scalars_tbl_core0_rev3[] = {
- 0x05af005a,
- 0x0571005e,
- 0x05040066,
- 0x04bd006c,
- 0x047d0072,
- 0x04430078,
- 0x03f70081,
- 0x03cb0087,
- 0x03870091,
- 0x035e0098,
- 0x032e00a1,
- 0x030300aa,
- 0x02d800b4,
- 0x02ae00bf,
- 0x028900ca,
- 0x026400d6,
- 0x024100e3,
- 0x022200f0,
- 0x020200ff,
- 0x01e5010e,
- 0x01ca011e,
- 0x01b0012f,
- 0x01990140,
- 0x01830153,
- 0x016c0168,
- 0x0158017d,
- 0x01450193,
- 0x013301ab,
- 0x012101c5,
- 0x011101e0,
- 0x010201fc,
- 0x00f4021a,
- 0x00e6011d,
- 0x00d9012e,
- 0x00cd0140,
- 0x00c20153,
- 0x00b70167,
- 0x00ac017c,
- 0x00a30193,
- 0x009a01ab,
- 0x009101c4,
- 0x008901df,
- 0x008101fb,
- 0x007a0219,
- 0x00730239,
- 0x006d025b,
- 0x0067027e,
- 0x006102a4,
- 0x005c02cc,
- 0x005602f6,
- 0x00520323,
- 0x004d0353,
- 0x00490385,
- 0x004503bb,
- 0x004103f3,
- 0x003d042f,
- 0x003a046f,
- 0x003704b2,
- 0x003404f9,
- 0x00310545,
- 0x002e0596,
- 0x002b05f5,
- 0x00290640,
- 0x002606a4,
-};
-
-const u32 papd_comp_epsilon_tbl_core1_rev3[] = {
- 0x00000000,
- 0x00001fa0,
- 0x00019f78,
- 0x0001df7e,
- 0x03fa9f86,
- 0x03fd1f90,
- 0x03fe5f8a,
- 0x03fb1f94,
- 0x03fd9fa0,
- 0x00009f98,
- 0x03fd1fac,
- 0x03ff9fa2,
- 0x03fe9fae,
- 0x00001fae,
- 0x03fddfb4,
- 0x03ff1fb8,
- 0x03ff9fbc,
- 0x03ffdfbe,
- 0x03fe9fc2,
- 0x03fedfc6,
- 0x03fedfc6,
- 0x03ff9fc8,
- 0x03ff5fc6,
- 0x03fedfc2,
- 0x03ff9fc0,
- 0x03ff5fac,
- 0x03ff5fac,
- 0x03ff9fa2,
- 0x03ff9fa6,
- 0x03ff9faa,
- 0x03ff5fb0,
- 0x03ff5fb4,
- 0x03ff1fca,
- 0x03ff5fce,
- 0x03fcdfdc,
- 0x03fb4006,
- 0x00000030,
- 0x03ff808a,
- 0x03ff80da,
- 0x0000016c,
- 0x03ff8318,
- 0x03ff063a,
- 0x03fd8bd6,
- 0x00014ffe,
- 0x00034ffe,
- 0x00034ffe,
- 0x0003cffe,
- 0x00040ffe,
- 0x00040ffe,
- 0x0003cffe,
- 0x0003cffe,
- 0x00020ffe,
- 0x03fe0ffe,
- 0x03fdcffe,
- 0x03f94ffe,
- 0x03f54ffe,
- 0x03f44ffe,
- 0x03ef8ffe,
- 0x03ee0ffe,
- 0x03ebcffe,
- 0x03e8cffe,
- 0x03e74ffe,
- 0x03e4cffe,
- 0x03e38ffe,
-};
-
-const u32 papd_cal_scalars_tbl_core1_rev3[] = {
- 0x05af005a,
- 0x0571005e,
- 0x05040066,
- 0x04bd006c,
- 0x047d0072,
- 0x04430078,
- 0x03f70081,
- 0x03cb0087,
- 0x03870091,
- 0x035e0098,
- 0x032e00a1,
- 0x030300aa,
- 0x02d800b4,
- 0x02ae00bf,
- 0x028900ca,
- 0x026400d6,
- 0x024100e3,
- 0x022200f0,
- 0x020200ff,
- 0x01e5010e,
- 0x01ca011e,
- 0x01b0012f,
- 0x01990140,
- 0x01830153,
- 0x016c0168,
- 0x0158017d,
- 0x01450193,
- 0x013301ab,
- 0x012101c5,
- 0x011101e0,
- 0x010201fc,
- 0x00f4021a,
- 0x00e6011d,
- 0x00d9012e,
- 0x00cd0140,
- 0x00c20153,
- 0x00b70167,
- 0x00ac017c,
- 0x00a30193,
- 0x009a01ab,
- 0x009101c4,
- 0x008901df,
- 0x008101fb,
- 0x007a0219,
- 0x00730239,
- 0x006d025b,
- 0x0067027e,
- 0x006102a4,
- 0x005c02cc,
- 0x005602f6,
- 0x00520323,
- 0x004d0353,
- 0x00490385,
- 0x004503bb,
- 0x004103f3,
- 0x003d042f,
- 0x003a046f,
- 0x003704b2,
- 0x003404f9,
- 0x00310545,
- 0x002e0596,
- 0x002b05f5,
- 0x00290640,
- 0x002606a4,
-};
-
-const mimophytbl_info_t mimophytbl_info_rev3_volatile[] = {
- {&ant_swctrl_tbl_rev3,
- sizeof(ant_swctrl_tbl_rev3) / sizeof(ant_swctrl_tbl_rev3[0]), 9, 0, 16}
- ,
-};
-
-const mimophytbl_info_t mimophytbl_info_rev3_volatile1[] = {
- {&ant_swctrl_tbl_rev3_1,
- sizeof(ant_swctrl_tbl_rev3_1) / sizeof(ant_swctrl_tbl_rev3_1[0]), 9, 0,
- 16}
- ,
-};
-
-const mimophytbl_info_t mimophytbl_info_rev3_volatile2[] = {
- {&ant_swctrl_tbl_rev3_2,
- sizeof(ant_swctrl_tbl_rev3_2) / sizeof(ant_swctrl_tbl_rev3_2[0]), 9, 0,
- 16}
- ,
-};
-
-const mimophytbl_info_t mimophytbl_info_rev3_volatile3[] = {
- {&ant_swctrl_tbl_rev3_3,
- sizeof(ant_swctrl_tbl_rev3_3) / sizeof(ant_swctrl_tbl_rev3_3[0]), 9, 0,
- 16}
- ,
-};
-
-const mimophytbl_info_t mimophytbl_info_rev3[] = {
- {&frame_struct_rev3,
- sizeof(frame_struct_rev3) / sizeof(frame_struct_rev3[0]), 10, 0, 32}
- ,
- {&pilot_tbl_rev3, sizeof(pilot_tbl_rev3) / sizeof(pilot_tbl_rev3[0]),
- 11, 0, 16}
- ,
- {&tmap_tbl_rev3, sizeof(tmap_tbl_rev3) / sizeof(tmap_tbl_rev3[0]), 12,
- 0, 32}
- ,
- {&intlv_tbl_rev3, sizeof(intlv_tbl_rev3) / sizeof(intlv_tbl_rev3[0]),
- 13, 0, 32}
- ,
- {&tdtrn_tbl_rev3, sizeof(tdtrn_tbl_rev3) / sizeof(tdtrn_tbl_rev3[0]),
- 14, 0, 32}
- ,
- {&noise_var_tbl_rev3,
- sizeof(noise_var_tbl_rev3) / sizeof(noise_var_tbl_rev3[0]), 16, 0, 32}
- ,
- {&mcs_tbl_rev3, sizeof(mcs_tbl_rev3) / sizeof(mcs_tbl_rev3[0]), 18, 0,
- 16}
- ,
- {&tdi_tbl20_ant0_rev3,
- sizeof(tdi_tbl20_ant0_rev3) / sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
- 32}
- ,
- {&tdi_tbl20_ant1_rev3,
- sizeof(tdi_tbl20_ant1_rev3) / sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
- 32}
- ,
- {&tdi_tbl40_ant0_rev3,
- sizeof(tdi_tbl40_ant0_rev3) / sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
- 32}
- ,
- {&tdi_tbl40_ant1_rev3,
- sizeof(tdi_tbl40_ant1_rev3) / sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
- 32}
- ,
- {&pltlut_tbl_rev3, sizeof(pltlut_tbl_rev3) / sizeof(pltlut_tbl_rev3[0]),
- 20, 0, 32}
- ,
- {&chanest_tbl_rev3,
- sizeof(chanest_tbl_rev3) / sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
- ,
- {&frame_lut_rev3, sizeof(frame_lut_rev3) / sizeof(frame_lut_rev3[0]),
- 24, 0, 8}
- ,
- {&est_pwr_lut_core0_rev3,
- sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
- 0, 8}
- ,
- {&est_pwr_lut_core1_rev3,
- sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
- 0, 8}
- ,
- {&adj_pwr_lut_core0_rev3,
- sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
- 64, 8}
- ,
- {&adj_pwr_lut_core1_rev3,
- sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
- 64, 8}
- ,
- {&gainctrl_lut_core0_rev3,
- sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
- 26, 192, 32}
- ,
- {&gainctrl_lut_core1_rev3,
- sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
- 27, 192, 32}
- ,
- {&iq_lut_core0_rev3,
- sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
- ,
- {&iq_lut_core1_rev3,
- sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
- ,
- {&loft_lut_core0_rev3,
- sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
- 16}
- ,
- {&loft_lut_core1_rev3,
- sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
- 16}
-};
-
-const u32 mimophytbl_info_sz_rev3 =
- sizeof(mimophytbl_info_rev3) / sizeof(mimophytbl_info_rev3[0]);
-const u32 mimophytbl_info_sz_rev3_volatile =
- sizeof(mimophytbl_info_rev3_volatile) /
- sizeof(mimophytbl_info_rev3_volatile[0]);
-const u32 mimophytbl_info_sz_rev3_volatile1 =
- sizeof(mimophytbl_info_rev3_volatile1) /
- sizeof(mimophytbl_info_rev3_volatile1[0]);
-const u32 mimophytbl_info_sz_rev3_volatile2 =
- sizeof(mimophytbl_info_rev3_volatile2) /
- sizeof(mimophytbl_info_rev3_volatile2[0]);
-const u32 mimophytbl_info_sz_rev3_volatile3 =
- sizeof(mimophytbl_info_rev3_volatile3) /
- sizeof(mimophytbl_info_rev3_volatile3[0]);
-
-const u32 tmap_tbl_rev7[] = {
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00000111,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x000aa888,
- 0x88880000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa2222220,
- 0x22222222,
- 0x22c22222,
- 0x00000222,
- 0x22000000,
- 0x2222a222,
- 0x22222222,
- 0x222222a2,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00011111,
- 0x11110000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0xa8aa88a0,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x00088aaa,
- 0xaaaa0000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xaaa8aaa0,
- 0x8aaa8aaa,
- 0xaa8a8a8a,
- 0x000aaa88,
- 0x8aaa0000,
- 0xaaa8a888,
- 0x8aa88a8a,
- 0x8a88a888,
- 0x08080a00,
- 0x0a08080a,
- 0x080a0a08,
- 0x00080808,
- 0x080a0000,
- 0x080a0808,
- 0x080a0808,
- 0x0a0a0a08,
- 0xa0a0a0a0,
- 0x80a0a080,
- 0x8080a0a0,
- 0x00008080,
- 0x80a00000,
- 0x80a080a0,
- 0xa080a0a0,
- 0x8080a0a0,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x99999000,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb90,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00aaa888,
- 0x22000000,
- 0x2222b222,
- 0x22222222,
- 0x222222b2,
- 0xb2222220,
- 0x22222222,
- 0x22d22222,
- 0x00000222,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x33000000,
- 0x3333b333,
- 0x33333333,
- 0x333333b3,
- 0xb3333330,
- 0x33333333,
- 0x33d33333,
- 0x00000333,
- 0x22000000,
- 0x2222a222,
- 0x22222222,
- 0x222222a2,
- 0xa2222220,
- 0x22222222,
- 0x22c22222,
- 0x00000222,
- 0x99b99b00,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb99,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x08aaa888,
- 0x22222200,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0x22222222,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x11111111,
- 0xf1111111,
- 0x11111111,
- 0x11f11111,
- 0x01111111,
- 0xbb9bb900,
- 0xb9b9bb99,
- 0xb99bbbbb,
- 0xbbbb9b9b,
- 0xb9bb99bb,
- 0xb99999b9,
- 0xb9b9b99b,
- 0x00000bbb,
- 0xaa000000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xa8aa88aa,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x0a888aaa,
- 0xaa000000,
- 0xa8a8aa88,
- 0xa88aaaaa,
- 0xaaaa8a8a,
- 0xa8aa88a0,
- 0xa88888a8,
- 0xa8a8a88a,
- 0x00000aaa,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0xbbbbbb00,
- 0x999bbbbb,
- 0x9bb99b9b,
- 0xb9b9b9bb,
- 0xb9b99bbb,
- 0xb9b9b9bb,
- 0xb9bb9b99,
- 0x00000999,
- 0x8a000000,
- 0xaa88a888,
- 0xa88888aa,
- 0xa88a8a88,
- 0xa88aa88a,
- 0x88a8aaaa,
- 0xa8aa8aaa,
- 0x0888a88a,
- 0x0b0b0b00,
- 0x090b0b0b,
- 0x0b090b0b,
- 0x0909090b,
- 0x09090b0b,
- 0x09090b0b,
- 0x09090b09,
- 0x00000909,
- 0x0a000000,
- 0x0a080808,
- 0x080a080a,
- 0x080a0a08,
- 0x080a080a,
- 0x0808080a,
- 0x0a0a0a08,
- 0x0808080a,
- 0xb0b0b000,
- 0x9090b0b0,
- 0x90b09090,
- 0xb0b0b090,
- 0xb0b090b0,
- 0x90b0b0b0,
- 0xb0b09090,
- 0x00000090,
- 0x80000000,
- 0xa080a080,
- 0xa08080a0,
- 0xa0808080,
- 0xa080a080,
- 0x80a0a0a0,
- 0xa0a080a0,
- 0x00a0a0a0,
- 0x22000000,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0xf2222220,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x11000000,
- 0x1111f111,
- 0x11111111,
- 0x111111f1,
- 0xf1111110,
- 0x11111111,
- 0x11f11111,
- 0x00000111,
- 0x33000000,
- 0x3333f333,
- 0x33333333,
- 0x333333f3,
- 0xf3333330,
- 0x33333333,
- 0x33f33333,
- 0x00000333,
- 0x22000000,
- 0x2222f222,
- 0x22222222,
- 0x222222f2,
- 0xf2222220,
- 0x22222222,
- 0x22f22222,
- 0x00000222,
- 0x99000000,
- 0x9b9b99bb,
- 0x9bb99999,
- 0x9999b9b9,
- 0x9b99bb90,
- 0x9bbbbb9b,
- 0x9b9b9bb9,
- 0x00000999,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88888000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00aaa888,
- 0x88a88a00,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x000aa888,
- 0x88880000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa88,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x08aaa888,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x11000000,
- 0x1111a111,
- 0x11111111,
- 0x111111a1,
- 0xa1111110,
- 0x11111111,
- 0x11c11111,
- 0x00000111,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x88000000,
- 0x8a8a88aa,
- 0x8aa88888,
- 0x8888a8a8,
- 0x8a88aa80,
- 0x8aaaaa8a,
- 0x8a8a8aa8,
- 0x00000888,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-const u32 noise_var_tbl_rev7[] = {
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
- 0x020c020c,
- 0x0000014d,
-};
-
-const u32 papd_comp_epsilon_tbl_core0_rev7[] = {
- 0x00000000,
- 0x00000000,
- 0x00016023,
- 0x00006028,
- 0x00034036,
- 0x0003402e,
- 0x0007203c,
- 0x0006e037,
- 0x00070030,
- 0x0009401f,
- 0x0009a00f,
- 0x000b600d,
- 0x000c8007,
- 0x000ce007,
- 0x00101fff,
- 0x00121ff9,
- 0x0012e004,
- 0x0014dffc,
- 0x0016dff6,
- 0x0018dfe9,
- 0x001b3fe5,
- 0x001c5fd0,
- 0x001ddfc2,
- 0x001f1fb6,
- 0x00207fa4,
- 0x00219f8f,
- 0x0022ff7d,
- 0x00247f6c,
- 0x0024df5b,
- 0x00267f4b,
- 0x0027df3b,
- 0x0029bf3b,
- 0x002b5f2f,
- 0x002d3f2e,
- 0x002f5f2a,
- 0x002fff15,
- 0x00315f0b,
- 0x0032defa,
- 0x0033beeb,
- 0x0034fed9,
- 0x00353ec5,
- 0x00361eb0,
- 0x00363e9b,
- 0x0036be87,
- 0x0036be70,
- 0x0038fe67,
- 0x0044beb2,
- 0x00513ef3,
- 0x00595f11,
- 0x00669f3d,
- 0x0078dfdf,
- 0x00a143aa,
- 0x01642fff,
- 0x0162afff,
- 0x01620fff,
- 0x0160cfff,
- 0x015f0fff,
- 0x015dafff,
- 0x015bcfff,
- 0x015bcfff,
- 0x015b4fff,
- 0x015acfff,
- 0x01590fff,
- 0x0156cfff,
-};
-
-const u32 papd_cal_scalars_tbl_core0_rev7[] = {
- 0x0b5e002d,
- 0x0ae2002f,
- 0x0a3b0032,
- 0x09a70035,
- 0x09220038,
- 0x08ab003b,
- 0x081f003f,
- 0x07a20043,
- 0x07340047,
- 0x06d2004b,
- 0x067a004f,
- 0x06170054,
- 0x05bf0059,
- 0x0571005e,
- 0x051e0064,
- 0x04d3006a,
- 0x04910070,
- 0x044c0077,
- 0x040f007e,
- 0x03d90085,
- 0x03a1008d,
- 0x036f0095,
- 0x033d009e,
- 0x030b00a8,
- 0x02e000b2,
- 0x02b900bc,
- 0x029200c7,
- 0x026d00d3,
- 0x024900e0,
- 0x022900ed,
- 0x020a00fb,
- 0x01ec010a,
- 0x01d20119,
- 0x01b7012a,
- 0x019e013c,
- 0x0188014e,
- 0x01720162,
- 0x015d0177,
- 0x0149018e,
- 0x013701a5,
- 0x012601be,
- 0x011501d8,
- 0x010601f4,
- 0x00f70212,
- 0x00e90231,
- 0x00dc0253,
- 0x00d00276,
- 0x00c4029b,
- 0x00b902c3,
- 0x00af02ed,
- 0x00a50319,
- 0x009c0348,
- 0x0093037a,
- 0x008b03af,
- 0x008303e6,
- 0x007c0422,
- 0x00750460,
- 0x006e04a3,
- 0x006804e9,
- 0x00620533,
- 0x005d0582,
- 0x005805d6,
- 0x0053062e,
- 0x004e068c,
-};
-
-const u32 papd_comp_epsilon_tbl_core1_rev7[] = {
- 0x00000000,
- 0x00000000,
- 0x00016023,
- 0x00006028,
- 0x00034036,
- 0x0003402e,
- 0x0007203c,
- 0x0006e037,
- 0x00070030,
- 0x0009401f,
- 0x0009a00f,
- 0x000b600d,
- 0x000c8007,
- 0x000ce007,
- 0x00101fff,
- 0x00121ff9,
- 0x0012e004,
- 0x0014dffc,
- 0x0016dff6,
- 0x0018dfe9,
- 0x001b3fe5,
- 0x001c5fd0,
- 0x001ddfc2,
- 0x001f1fb6,
- 0x00207fa4,
- 0x00219f8f,
- 0x0022ff7d,
- 0x00247f6c,
- 0x0024df5b,
- 0x00267f4b,
- 0x0027df3b,
- 0x0029bf3b,
- 0x002b5f2f,
- 0x002d3f2e,
- 0x002f5f2a,
- 0x002fff15,
- 0x00315f0b,
- 0x0032defa,
- 0x0033beeb,
- 0x0034fed9,
- 0x00353ec5,
- 0x00361eb0,
- 0x00363e9b,
- 0x0036be87,
- 0x0036be70,
- 0x0038fe67,
- 0x0044beb2,
- 0x00513ef3,
- 0x00595f11,
- 0x00669f3d,
- 0x0078dfdf,
- 0x00a143aa,
- 0x01642fff,
- 0x0162afff,
- 0x01620fff,
- 0x0160cfff,
- 0x015f0fff,
- 0x015dafff,
- 0x015bcfff,
- 0x015bcfff,
- 0x015b4fff,
- 0x015acfff,
- 0x01590fff,
- 0x0156cfff,
-};
-
-const u32 papd_cal_scalars_tbl_core1_rev7[] = {
- 0x0b5e002d,
- 0x0ae2002f,
- 0x0a3b0032,
- 0x09a70035,
- 0x09220038,
- 0x08ab003b,
- 0x081f003f,
- 0x07a20043,
- 0x07340047,
- 0x06d2004b,
- 0x067a004f,
- 0x06170054,
- 0x05bf0059,
- 0x0571005e,
- 0x051e0064,
- 0x04d3006a,
- 0x04910070,
- 0x044c0077,
- 0x040f007e,
- 0x03d90085,
- 0x03a1008d,
- 0x036f0095,
- 0x033d009e,
- 0x030b00a8,
- 0x02e000b2,
- 0x02b900bc,
- 0x029200c7,
- 0x026d00d3,
- 0x024900e0,
- 0x022900ed,
- 0x020a00fb,
- 0x01ec010a,
- 0x01d20119,
- 0x01b7012a,
- 0x019e013c,
- 0x0188014e,
- 0x01720162,
- 0x015d0177,
- 0x0149018e,
- 0x013701a5,
- 0x012601be,
- 0x011501d8,
- 0x010601f4,
- 0x00f70212,
- 0x00e90231,
- 0x00dc0253,
- 0x00d00276,
- 0x00c4029b,
- 0x00b902c3,
- 0x00af02ed,
- 0x00a50319,
- 0x009c0348,
- 0x0093037a,
- 0x008b03af,
- 0x008303e6,
- 0x007c0422,
- 0x00750460,
- 0x006e04a3,
- 0x006804e9,
- 0x00620533,
- 0x005d0582,
- 0x005805d6,
- 0x0053062e,
- 0x004e068c,
-};
-
-const mimophytbl_info_t mimophytbl_info_rev7[] = {
- {&frame_struct_rev3,
- sizeof(frame_struct_rev3) / sizeof(frame_struct_rev3[0]), 10, 0, 32}
- ,
- {&pilot_tbl_rev3, sizeof(pilot_tbl_rev3) / sizeof(pilot_tbl_rev3[0]),
- 11, 0, 16}
- ,
- {&tmap_tbl_rev7, sizeof(tmap_tbl_rev7) / sizeof(tmap_tbl_rev7[0]), 12,
- 0, 32}
- ,
- {&intlv_tbl_rev3, sizeof(intlv_tbl_rev3) / sizeof(intlv_tbl_rev3[0]),
- 13, 0, 32}
- ,
- {&tdtrn_tbl_rev3, sizeof(tdtrn_tbl_rev3) / sizeof(tdtrn_tbl_rev3[0]),
- 14, 0, 32}
- ,
- {&noise_var_tbl_rev7,
- sizeof(noise_var_tbl_rev7) / sizeof(noise_var_tbl_rev7[0]), 16, 0, 32}
- ,
- {&mcs_tbl_rev3, sizeof(mcs_tbl_rev3) / sizeof(mcs_tbl_rev3[0]), 18, 0,
- 16}
- ,
- {&tdi_tbl20_ant0_rev3,
- sizeof(tdi_tbl20_ant0_rev3) / sizeof(tdi_tbl20_ant0_rev3[0]), 19, 128,
- 32}
- ,
- {&tdi_tbl20_ant1_rev3,
- sizeof(tdi_tbl20_ant1_rev3) / sizeof(tdi_tbl20_ant1_rev3[0]), 19, 256,
- 32}
- ,
- {&tdi_tbl40_ant0_rev3,
- sizeof(tdi_tbl40_ant0_rev3) / sizeof(tdi_tbl40_ant0_rev3[0]), 19, 640,
- 32}
- ,
- {&tdi_tbl40_ant1_rev3,
- sizeof(tdi_tbl40_ant1_rev3) / sizeof(tdi_tbl40_ant1_rev3[0]), 19, 768,
- 32}
- ,
- {&pltlut_tbl_rev3, sizeof(pltlut_tbl_rev3) / sizeof(pltlut_tbl_rev3[0]),
- 20, 0, 32}
- ,
- {&chanest_tbl_rev3,
- sizeof(chanest_tbl_rev3) / sizeof(chanest_tbl_rev3[0]), 22, 0, 32}
- ,
- {&frame_lut_rev3, sizeof(frame_lut_rev3) / sizeof(frame_lut_rev3[0]),
- 24, 0, 8}
- ,
- {&est_pwr_lut_core0_rev3,
- sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
- 0, 8}
- ,
- {&est_pwr_lut_core1_rev3,
- sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
- 0, 8}
- ,
- {&adj_pwr_lut_core0_rev3,
- sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
- 64, 8}
- ,
- {&adj_pwr_lut_core1_rev3,
- sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
- 64, 8}
- ,
- {&gainctrl_lut_core0_rev3,
- sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
- 26, 192, 32}
- ,
- {&gainctrl_lut_core1_rev3,
- sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
- 27, 192, 32}
- ,
- {&iq_lut_core0_rev3,
- sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
- ,
- {&iq_lut_core1_rev3,
- sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
- ,
- {&loft_lut_core0_rev3,
- sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
- 16}
- ,
- {&loft_lut_core1_rev3,
- sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
- 16}
- ,
- {&papd_comp_rfpwr_tbl_core0_rev3,
- sizeof(papd_comp_rfpwr_tbl_core0_rev3) /
- sizeof(papd_comp_rfpwr_tbl_core0_rev3[0]), 26, 576, 16}
- ,
- {&papd_comp_rfpwr_tbl_core1_rev3,
- sizeof(papd_comp_rfpwr_tbl_core1_rev3) /
- sizeof(papd_comp_rfpwr_tbl_core1_rev3[0]), 27, 576, 16}
- ,
- {&papd_comp_epsilon_tbl_core0_rev7,
- sizeof(papd_comp_epsilon_tbl_core0_rev7) /
- sizeof(papd_comp_epsilon_tbl_core0_rev7[0]), 31, 0, 32}
- ,
- {&papd_cal_scalars_tbl_core0_rev7,
- sizeof(papd_cal_scalars_tbl_core0_rev7) /
- sizeof(papd_cal_scalars_tbl_core0_rev7[0]), 32, 0, 32}
- ,
- {&papd_comp_epsilon_tbl_core1_rev7,
- sizeof(papd_comp_epsilon_tbl_core1_rev7) /
- sizeof(papd_comp_epsilon_tbl_core1_rev7[0]), 33, 0, 32}
- ,
- {&papd_cal_scalars_tbl_core1_rev7,
- sizeof(papd_cal_scalars_tbl_core1_rev7) /
- sizeof(papd_cal_scalars_tbl_core1_rev7[0]), 34, 0, 32}
- ,
-};
-
-const u32 mimophytbl_info_sz_rev7 =
- sizeof(mimophytbl_info_rev7) / sizeof(mimophytbl_info_rev7[0]);
-
-const mimophytbl_info_t mimophytbl_info_rev16[] = {
- {&noise_var_tbl_rev7,
- sizeof(noise_var_tbl_rev7) / sizeof(noise_var_tbl_rev7[0]), 16, 0, 32}
- ,
- {&est_pwr_lut_core0_rev3,
- sizeof(est_pwr_lut_core0_rev3) / sizeof(est_pwr_lut_core0_rev3[0]), 26,
- 0, 8}
- ,
- {&est_pwr_lut_core1_rev3,
- sizeof(est_pwr_lut_core1_rev3) / sizeof(est_pwr_lut_core1_rev3[0]), 27,
- 0, 8}
- ,
- {&adj_pwr_lut_core0_rev3,
- sizeof(adj_pwr_lut_core0_rev3) / sizeof(adj_pwr_lut_core0_rev3[0]), 26,
- 64, 8}
- ,
- {&adj_pwr_lut_core1_rev3,
- sizeof(adj_pwr_lut_core1_rev3) / sizeof(adj_pwr_lut_core1_rev3[0]), 27,
- 64, 8}
- ,
- {&gainctrl_lut_core0_rev3,
- sizeof(gainctrl_lut_core0_rev3) / sizeof(gainctrl_lut_core0_rev3[0]),
- 26, 192, 32}
- ,
- {&gainctrl_lut_core1_rev3,
- sizeof(gainctrl_lut_core1_rev3) / sizeof(gainctrl_lut_core1_rev3[0]),
- 27, 192, 32}
- ,
- {&iq_lut_core0_rev3,
- sizeof(iq_lut_core0_rev3) / sizeof(iq_lut_core0_rev3[0]), 26, 320, 32}
- ,
- {&iq_lut_core1_rev3,
- sizeof(iq_lut_core1_rev3) / sizeof(iq_lut_core1_rev3[0]), 27, 320, 32}
- ,
- {&loft_lut_core0_rev3,
- sizeof(loft_lut_core0_rev3) / sizeof(loft_lut_core0_rev3[0]), 26, 448,
- 16}
- ,
- {&loft_lut_core1_rev3,
- sizeof(loft_lut_core1_rev3) / sizeof(loft_lut_core1_rev3[0]), 27, 448,
- 16}
- ,
-};
-
-const u32 mimophytbl_info_sz_rev16 =
- sizeof(mimophytbl_info_rev16) / sizeof(mimophytbl_info_rev16[0]);
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#define ANT_SWCTRL_TBL_REV3_IDX (0)
-
-typedef phytbl_info_t mimophytbl_info_t;
-
-extern const mimophytbl_info_t mimophytbl_info_rev0[],
- mimophytbl_info_rev0_volatile[];
-extern const u32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile;
-
-extern const mimophytbl_info_t mimophytbl_info_rev3[],
- mimophytbl_info_rev3_volatile[], mimophytbl_info_rev3_volatile1[],
- mimophytbl_info_rev3_volatile2[], mimophytbl_info_rev3_volatile3[];
-extern const u32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile,
- mimophytbl_info_sz_rev3_volatile1, mimophytbl_info_sz_rev3_volatile2,
- mimophytbl_info_sz_rev3_volatile3;
-
-extern const u32 noise_var_tbl_rev3[];
-
-extern const mimophytbl_info_t mimophytbl_info_rev7[];
-extern const u32 mimophytbl_info_sz_rev7;
-extern const u32 noise_var_tbl_rev7[];
-
-extern const mimophytbl_info_t mimophytbl_info_rev16[];
-extern const u32 mimophytbl_info_sz_rev16;
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This is "two-way" interface, acting as the SHIM layer between WL and PHY layer.
+ * WL driver can optinally call this translation layer to do some preprocessing, then reach PHY.
+ * On the PHY->WL driver direction, all calls go through this layer since PHY doesn't have the
+ * access to wlc_hw pointer.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <defs.h>
+#include <brcmu_utils.h>
+#include <brcmu_wifi.h>
+#include <aiutils.h>
+#include <chipcommon.h>
+#include "dma.h"
+#include <pmu.h>
+
+#include "types.h"
+#include "cfg.h"
+#include "d11.h"
+#include "rate.h"
+#include "scb.h"
+#include "pub.h"
+#include "phy/phy_hal.h"
+#include "channel.h"
+#include <srom.h>
+#include "key.h"
+#include "bottom_mac.h"
+#include "phy_hal.h"
+#include "main.h"
+#include "phy_shim.h"
+#include "mac80211_if.h"
+
+/* PHY SHIM module specific state */
+struct wlc_phy_shim_info {
+ struct wlc_hw_info *wlc_hw; /* pointer to main wlc_hw structure */
+ void *wlc; /* pointer to main wlc structure */
+ void *wl; /* pointer to os-specific private state */
+};
+
+wlc_phy_shim_info_t *wlc_phy_shim_attach(struct wlc_hw_info *wlc_hw,
+ void *wl, void *wlc) {
+ wlc_phy_shim_info_t *physhim = NULL;
+
+ physhim = kzalloc(sizeof(wlc_phy_shim_info_t), GFP_ATOMIC);
+ if (!physhim) {
+ wiphy_err(wlc_hw->wlc->wiphy,
+ "wl%d: wlc_phy_shim_attach: out of mem\n",
+ wlc_hw->unit);
+ return NULL;
+ }
+ physhim->wlc_hw = wlc_hw;
+ physhim->wlc = wlc;
+ physhim->wl = wl;
+
+ return physhim;
+}
+
+void wlc_phy_shim_detach(wlc_phy_shim_info_t *physhim)
+{
+ kfree(physhim);
+}
+
+struct wlapi_timer *wlapi_init_timer(wlc_phy_shim_info_t *physhim,
+ void (*fn) (void *arg), void *arg,
+ const char *name)
+{
+ return (struct wlapi_timer *)
+ brcms_init_timer(physhim->wl, fn, arg, name);
+}
+
+void wlapi_free_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t)
+{
+ brcms_free_timer(physhim->wl, (struct brcms_timer *)t);
+}
+
+void
+wlapi_add_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t, uint ms,
+ int periodic)
+{
+ brcms_add_timer(physhim->wl, (struct brcms_timer *)t, ms, periodic);
+}
+
+bool wlapi_del_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t)
+{
+ return brcms_del_timer(physhim->wl, (struct brcms_timer *)t);
+}
+
+void wlapi_intrson(wlc_phy_shim_info_t *physhim)
+{
+ brcms_intrson(physhim->wl);
+}
+
+u32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim)
+{
+ return brcms_intrsoff(physhim->wl);
+}
+
+void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim, u32 macintmask)
+{
+ brcms_intrsrestore(physhim->wl, macintmask);
+}
+
+void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, u16 v)
+{
+ wlc_bmac_write_shm(physhim->wlc_hw, offset, v);
+}
+
+u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset)
+{
+ return wlc_bmac_read_shm(physhim->wlc_hw, offset);
+}
+
+void
+wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, u16 mask,
+ u16 val, int bands)
+{
+ wlc_bmac_mhf(physhim->wlc_hw, idx, mask, val, bands);
+}
+
+void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, u32 flags)
+{
+ wlc_bmac_corereset(physhim->wlc_hw, flags);
+}
+
+void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim)
+{
+ wlc_suspend_mac_and_wait(physhim->wlc);
+}
+
+void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode)
+{
+ wlc_bmac_switch_macfreq(physhim->wlc_hw, spurmode);
+}
+
+void wlapi_enable_mac(wlc_phy_shim_info_t *physhim)
+{
+ wlc_enable_mac(physhim->wlc);
+}
+
+void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, u32 mask, u32 val)
+{
+ wlc_bmac_mctrl(physhim->wlc_hw, mask, val);
+}
+
+void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim)
+{
+ wlc_bmac_phy_reset(physhim->wlc_hw);
+}
+
+void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw)
+{
+ wlc_bmac_bw_set(physhim->wlc_hw, bw);
+}
+
+u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim)
+{
+ return wlc_bmac_get_txant(physhim->wlc_hw);
+}
+
+void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk)
+{
+ wlc_bmac_phyclk_fgc(physhim->wlc_hw, clk);
+}
+
+void wlapi_bmac_macphyclk_set(wlc_phy_shim_info_t *physhim, bool clk)
+{
+ wlc_bmac_macphyclk_set(physhim->wlc_hw, clk);
+}
+
+void wlapi_bmac_core_phypll_ctl(wlc_phy_shim_info_t *physhim, bool on)
+{
+ wlc_bmac_core_phypll_ctl(physhim->wlc_hw, on);
+}
+
+void wlapi_bmac_core_phypll_reset(wlc_phy_shim_info_t *physhim)
+{
+ wlc_bmac_core_phypll_reset(physhim->wlc_hw);
+}
+
+void wlapi_bmac_ucode_wake_override_phyreg_set(wlc_phy_shim_info_t *physhim)
+{
+ wlc_ucode_wake_override_set(physhim->wlc_hw, WLC_WAKE_OVERRIDE_PHYREG);
+}
+
+void wlapi_bmac_ucode_wake_override_phyreg_clear(wlc_phy_shim_info_t *physhim)
+{
+ wlc_ucode_wake_override_clear(physhim->wlc_hw,
+ WLC_WAKE_OVERRIDE_PHYREG);
+}
+
+void
+wlapi_bmac_write_template_ram(wlc_phy_shim_info_t *physhim, int offset,
+ int len, void *buf)
+{
+ wlc_bmac_write_template_ram(physhim->wlc_hw, offset, len, buf);
+}
+
+u16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim, u8 rate)
+{
+ return wlc_bmac_rate_shm_offset(physhim->wlc_hw, rate);
+}
+
+void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim)
+{
+}
+
+void
+wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint offset, void *buf,
+ int len, u32 sel)
+{
+ wlc_bmac_copyfrom_objmem(physhim->wlc_hw, offset, buf, len, sel);
+}
+
+void
+wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint offset, const void *buf,
+ int l, u32 sel)
+{
+ wlc_bmac_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * phy_shim.h: stuff defined in phy_shim.c and included only by the phy
+ */
+
+#ifndef _BRCM_PHY_SHIM_H_
+#define _BRCM_PHY_SHIM_H_
+
+#define RADAR_TYPE_NONE 0 /* Radar type None */
+#define RADAR_TYPE_ETSI_1 1 /* ETSI 1 Radar type */
+#define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */
+#define RADAR_TYPE_ETSI_3 3 /* ETSI 3 Radar type */
+#define RADAR_TYPE_ITU_E 4 /* ITU E Radar type */
+#define RADAR_TYPE_ITU_K 5 /* ITU K Radar type */
+#define RADAR_TYPE_UNCLASSIFIED 6 /* Unclassified Radar type */
+#define RADAR_TYPE_BIN5 7 /* long pulse radar type */
+#define RADAR_TYPE_STG2 8 /* staggered-2 radar */
+#define RADAR_TYPE_STG3 9 /* staggered-3 radar */
+#define RADAR_TYPE_FRA 10 /* French radar */
+
+/* French radar pulse widths */
+#define FRA_T1_20MHZ 52770
+#define FRA_T2_20MHZ 61538
+#define FRA_T3_20MHZ 66002
+#define FRA_T1_40MHZ 105541
+#define FRA_T2_40MHZ 123077
+#define FRA_T3_40MHZ 132004
+#define FRA_ERR_20MHZ 60
+#define FRA_ERR_40MHZ 120
+
+#define ANTSEL_NA 0 /* No boardlevel selection available */
+#define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
+#define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */
+
+/* Rx Antenna diversity control values */
+#define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
+#define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
+#define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
+#define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */
+#define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
+#define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */
+
+#define WL_ANT_RX_MAX 2 /* max 2 receive antennas */
+#define WL_ANT_HT_RX_MAX 3 /* max 3 receive antennas/cores */
+#define WL_ANT_IDX_1 0 /* antenna index 1 */
+#define WL_ANT_IDX_2 1 /* antenna index 2 */
+
+/* values for n_preamble_type */
+#define WLC_N_PREAMBLE_MIXEDMODE 0
+#define WLC_N_PREAMBLE_GF 1
+#define WLC_N_PREAMBLE_GF_BRCM 2
+
+#define WL_TX_POWER_RATES_LEGACY 45
+#define WL_TX_POWER_MCS20_FIRST 12
+#define WL_TX_POWER_MCS20_NUM 16
+#define WL_TX_POWER_MCS40_FIRST 28
+#define WL_TX_POWER_MCS40_NUM 17
+
+
+#define WL_TX_POWER_RATES 101
+#define WL_TX_POWER_CCK_FIRST 0
+#define WL_TX_POWER_CCK_NUM 4
+#define WL_TX_POWER_OFDM_FIRST 4 /* Index for first 20MHz OFDM SISO rate */
+#define WL_TX_POWER_OFDM20_CDD_FIRST 12 /* Index for first 20MHz OFDM CDD rate */
+#define WL_TX_POWER_OFDM40_SISO_FIRST 52 /* Index for first 40MHz OFDM SISO rate */
+#define WL_TX_POWER_OFDM40_CDD_FIRST 60 /* Index for first 40MHz OFDM CDD rate */
+#define WL_TX_POWER_OFDM_NUM 8
+#define WL_TX_POWER_MCS20_SISO_FIRST 20 /* Index for first 20MHz MCS SISO rate */
+#define WL_TX_POWER_MCS20_CDD_FIRST 28 /* Index for first 20MHz MCS CDD rate */
+#define WL_TX_POWER_MCS20_STBC_FIRST 36 /* Index for first 20MHz MCS STBC rate */
+#define WL_TX_POWER_MCS20_SDM_FIRST 44 /* Index for first 20MHz MCS SDM rate */
+#define WL_TX_POWER_MCS40_SISO_FIRST 68 /* Index for first 40MHz MCS SISO rate */
+#define WL_TX_POWER_MCS40_CDD_FIRST 76 /* Index for first 40MHz MCS CDD rate */
+#define WL_TX_POWER_MCS40_STBC_FIRST 84 /* Index for first 40MHz MCS STBC rate */
+#define WL_TX_POWER_MCS40_SDM_FIRST 92 /* Index for first 40MHz MCS SDM rate */
+#define WL_TX_POWER_MCS_1_STREAM_NUM 8
+#define WL_TX_POWER_MCS_2_STREAM_NUM 8
+#define WL_TX_POWER_MCS_32 100 /* Index for 40MHz rate MCS 32 */
+#define WL_TX_POWER_MCS_32_NUM 1
+
+/* sslpnphy specifics */
+#define WL_TX_POWER_MCS20_SISO_FIRST_SSN 12 /* Index for first 20MHz MCS SISO rate */
+
+/* tx_power_t.flags bits */
+#define WL_TX_POWER_F_ENABLED 1
+#define WL_TX_POWER_F_HW 2
+#define WL_TX_POWER_F_MIMO 4
+#define WL_TX_POWER_F_SISO 8
+
+/* values to force tx/rx chain */
+#define WLC_N_TXRX_CHAIN0 0
+#define WLC_N_TXRX_CHAIN1 1
+
+/* Forward declarations */
+struct wlc_hw_info;
+typedef struct wlc_phy_shim_info wlc_phy_shim_info_t;
+
+extern wlc_phy_shim_info_t *wlc_phy_shim_attach(struct wlc_hw_info *wlc_hw,
+ void *wl, void *wlc);
+extern void wlc_phy_shim_detach(wlc_phy_shim_info_t *physhim);
+
+/* PHY to WL utility functions */
+struct wlapi_timer;
+extern struct wlapi_timer *wlapi_init_timer(wlc_phy_shim_info_t *physhim,
+ void (*fn) (void *arg), void *arg,
+ const char *name);
+extern void wlapi_free_timer(wlc_phy_shim_info_t *physhim,
+ struct wlapi_timer *t);
+extern void wlapi_add_timer(wlc_phy_shim_info_t *physhim,
+ struct wlapi_timer *t, uint ms, int periodic);
+extern bool wlapi_del_timer(wlc_phy_shim_info_t *physhim,
+ struct wlapi_timer *t);
+extern void wlapi_intrson(wlc_phy_shim_info_t *physhim);
+extern u32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim);
+extern void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim,
+ u32 macintmask);
+
+extern void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset,
+ u16 v);
+extern u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset);
+extern void wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx,
+ u16 mask, u16 val, int bands);
+extern void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, u32 flags);
+extern void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim);
+extern void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode);
+extern void wlapi_enable_mac(wlc_phy_shim_info_t *physhim);
+extern void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, u32 mask,
+ u32 val);
+extern void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim);
+extern void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw);
+extern void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk);
+extern void wlapi_bmac_macphyclk_set(wlc_phy_shim_info_t *physhim, bool clk);
+extern void wlapi_bmac_core_phypll_ctl(wlc_phy_shim_info_t *physhim, bool on);
+extern void wlapi_bmac_core_phypll_reset(wlc_phy_shim_info_t *physhim);
+extern void wlapi_bmac_ucode_wake_override_phyreg_set(wlc_phy_shim_info_t *
+ physhim);
+extern void wlapi_bmac_ucode_wake_override_phyreg_clear(wlc_phy_shim_info_t *
+ physhim);
+extern void wlapi_bmac_write_template_ram(wlc_phy_shim_info_t *physhim, int o,
+ int len, void *buf);
+extern u16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim,
+ u8 rate);
+extern void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim);
+extern void wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint,
+ void *buf, int, u32 sel);
+extern void wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint,
+ const void *buf, int, u32);
+
+extern void wlapi_high_update_phy_mode(wlc_phy_shim_info_t *physhim,
+ u32 phy_mode);
+extern u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim);
+#endif /* _BRCM_PHY_SHIM_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2011 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <brcm_hw_ids.h>
+#include "types.h"
+#include <chipcommon.h>
+#include <brcmu_utils.h>
+#include "scb.h"
+#include "pub.h"
+#include "pmu.h"
+
+/*
+ * d11 slow to fast clock transition time in slow clock cycles
+ */
+#define D11SCC_SLOW2FAST_TRANSITION 2
+
+/*
+ * external LPO crystal frequency
+ */
+#define EXT_ILP_HZ 32768
+
+/*
+ * Duration for ILP clock frequency measurment in milliseconds
+ *
+ * remark: 1000 must be an integer multiple of this duration
+ */
+#define ILP_CALC_DUR 10
+
+/*
+ * FVCO frequency
+ */
+#define FVCO_880 880000 /* 880MHz */
+#define FVCO_1760 1760000 /* 1760MHz */
+#define FVCO_1440 1440000 /* 1440MHz */
+#define FVCO_960 960000 /* 960MHz */
+
+/*
+ * PMU crystal table indices for 1440MHz fvco
+ */
+#define PMU1_XTALTAB0_1440_12000K 0
+#define PMU1_XTALTAB0_1440_13000K 1
+#define PMU1_XTALTAB0_1440_14400K 2
+#define PMU1_XTALTAB0_1440_15360K 3
+#define PMU1_XTALTAB0_1440_16200K 4
+#define PMU1_XTALTAB0_1440_16800K 5
+#define PMU1_XTALTAB0_1440_19200K 6
+#define PMU1_XTALTAB0_1440_19800K 7
+#define PMU1_XTALTAB0_1440_20000K 8
+#define PMU1_XTALTAB0_1440_25000K 9
+#define PMU1_XTALTAB0_1440_26000K 10
+#define PMU1_XTALTAB0_1440_30000K 11
+#define PMU1_XTALTAB0_1440_37400K 12
+#define PMU1_XTALTAB0_1440_38400K 13
+#define PMU1_XTALTAB0_1440_40000K 14
+#define PMU1_XTALTAB0_1440_48000K 15
+
+/*
+ * PMU crystal table indices for 960MHz fvco
+ */
+#define PMU1_XTALTAB0_960_12000K 0
+#define PMU1_XTALTAB0_960_13000K 1
+#define PMU1_XTALTAB0_960_14400K 2
+#define PMU1_XTALTAB0_960_15360K 3
+#define PMU1_XTALTAB0_960_16200K 4
+#define PMU1_XTALTAB0_960_16800K 5
+#define PMU1_XTALTAB0_960_19200K 6
+#define PMU1_XTALTAB0_960_19800K 7
+#define PMU1_XTALTAB0_960_20000K 8
+#define PMU1_XTALTAB0_960_25000K 9
+#define PMU1_XTALTAB0_960_26000K 10
+#define PMU1_XTALTAB0_960_30000K 11
+#define PMU1_XTALTAB0_960_37400K 12
+#define PMU1_XTALTAB0_960_38400K 13
+#define PMU1_XTALTAB0_960_40000K 14
+#define PMU1_XTALTAB0_960_48000K 15
+
+/*
+ * PMU crystal table indices for 880MHz fvco
+ */
+#define PMU1_XTALTAB0_880_12000K 0
+#define PMU1_XTALTAB0_880_13000K 1
+#define PMU1_XTALTAB0_880_14400K 2
+#define PMU1_XTALTAB0_880_15360K 3
+#define PMU1_XTALTAB0_880_16200K 4
+#define PMU1_XTALTAB0_880_16800K 5
+#define PMU1_XTALTAB0_880_19200K 6
+#define PMU1_XTALTAB0_880_19800K 7
+#define PMU1_XTALTAB0_880_20000K 8
+#define PMU1_XTALTAB0_880_24000K 9
+#define PMU1_XTALTAB0_880_25000K 10
+#define PMU1_XTALTAB0_880_26000K 11
+#define PMU1_XTALTAB0_880_30000K 12
+#define PMU1_XTALTAB0_880_37400K 13
+#define PMU1_XTALTAB0_880_38400K 14
+#define PMU1_XTALTAB0_880_40000K 15
+
+/*
+ * crystal frequency values
+ */
+#define XTAL_FREQ_24000MHZ 24000
+#define XTAL_FREQ_30000MHZ 30000
+#define XTAL_FREQ_37400MHZ 37400
+#define XTAL_FREQ_48000MHZ 48000
+
+/*
+ * Resource dependancies mask change action
+ *
+ * @RES_DEPEND_SET: Override the dependancies mask
+ * @RES_DEPEND_ADD: Add to the dependancies mask
+ * @RES_DEPEND_REMOVE: Remove from the dependancies mask
+ */
+#define RES_DEPEND_SET 0
+#define RES_DEPEND_ADD 1
+#define RES_DEPEND_REMOVE -1
+
+/* Fields in pmucontrol */
+#define PCTL_ILP_DIV_MASK 0xffff0000
+#define PCTL_ILP_DIV_SHIFT 16
+#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
+#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
+#define PCTL_HT_REQ_EN 0x00000100
+#define PCTL_ALP_REQ_EN 0x00000080
+#define PCTL_XTALFREQ_MASK 0x0000007c
+#define PCTL_XTALFREQ_SHIFT 2
+#define PCTL_ILP_DIV_EN 0x00000002
+#define PCTL_LPO_SEL 0x00000001
+
+/* Fields in clkstretch */
+#define CSTRETCH_HT 0xffff0000
+#define CSTRETCH_ALP 0x0000ffff
+
+/* d11 slow to fast clock transition time in slow clock cycles */
+#define D11SCC_SLOW2FAST_TRANSITION 2
+
+/* ILP clock */
+#define ILP_CLOCK 32000
+
+/* ALP clock on pre-PMU chips */
+#define ALP_CLOCK 20000000
+
+/* HT clock */
+#define HT_CLOCK 80000000
+
+#define OTPS_READY 0x00001000
+
+/* pmustatus */
+#define PST_EXTLPOAVAIL 0x0100
+#define PST_WDRESET 0x0080
+#define PST_INTPEND 0x0040
+#define PST_SBCLKST 0x0030
+#define PST_SBCLKST_ILP 0x0010
+#define PST_SBCLKST_ALP 0x0020
+#define PST_SBCLKST_HT 0x0030
+#define PST_ALPAVAIL 0x0008
+#define PST_HTAVAIL 0x0004
+#define PST_RESINIT 0x0003
+
+/* PMU Resource Request Timer registers */
+/* This is based on PmuRev0 */
+#define PRRT_TIME_MASK 0x03ff
+#define PRRT_INTEN 0x0400
+#define PRRT_REQ_ACTIVE 0x0800
+#define PRRT_ALP_REQ 0x1000
+#define PRRT_HT_REQ 0x2000
+
+/* PMU resource bit position */
+#define PMURES_BIT(bit) (1 << (bit))
+
+/* PMU resource number limit */
+#define PMURES_MAX_RESNUM 30
+
+/* PMU chip control0 register */
+#define PMU_CHIPCTL0 0
+
+/* PMU chip control1 register */
+#define PMU_CHIPCTL1 1
+#define PMU_CC1_RXC_DLL_BYPASS 0x00010000
+
+#define PMU_CC1_IF_TYPE_MASK 0x00000030
+#define PMU_CC1_IF_TYPE_RMII 0x00000000
+#define PMU_CC1_IF_TYPE_MII 0x00000010
+#define PMU_CC1_IF_TYPE_RGMII 0x00000020
+
+#define PMU_CC1_SW_TYPE_MASK 0x000000c0
+#define PMU_CC1_SW_TYPE_EPHY 0x00000000
+#define PMU_CC1_SW_TYPE_EPHYMII 0x00000040
+#define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080
+#define PMU_CC1_SW_TYPE_RGMII 0x000000c0
+
+/* PMU corerev and chip specific PLL controls.
+ * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
+ * to differentiate different PLLs controlled by the same PMU rev.
+ */
+/* pllcontrol registers */
+/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
+#define PMU0_PLL0_PLLCTL0 0
+#define PMU0_PLL0_PC0_PDIV_MASK 1
+#define PMU0_PLL0_PC0_PDIV_FREQ 25000
+#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
+#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
+#define PMU0_PLL0_PC0_DIV_ARM_BASE 8
+
+/* PC0_DIV_ARM for PLLOUT_ARM */
+#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
+#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
+#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
+#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
+#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
+#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
+#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
+#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
+
+/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
+#define PMU0_PLL0_PLLCTL1 1
+#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
+#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
+#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
+#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
+#define PMU0_PLL0_PC1_STOP_MOD 0x00000040
+
+/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
+#define PMU0_PLL0_PLLCTL2 2
+#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
+#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
+
+/* pllcontrol registers */
+/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
+#define PMU1_PLL0_PLLCTL0 0
+#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
+#define PMU1_PLL0_PC0_P1DIV_SHIFT 20
+#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
+#define PMU1_PLL0_PC0_P2DIV_SHIFT 24
+
+/* m<x>div */
+#define PMU1_PLL0_PLLCTL1 1
+#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
+#define PMU1_PLL0_PC1_M1DIV_SHIFT 0
+#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
+#define PMU1_PLL0_PC1_M2DIV_SHIFT 8
+#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
+#define PMU1_PLL0_PC1_M3DIV_SHIFT 16
+#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
+#define PMU1_PLL0_PC1_M4DIV_SHIFT 24
+
+#define PMU1_PLL0_CHIPCTL0 0
+#define PMU1_PLL0_CHIPCTL1 1
+#define PMU1_PLL0_CHIPCTL2 2
+
+#define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
+#define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
+#define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
+
+/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
+#define PMU1_PLL0_PLLCTL2 2
+#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
+#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
+#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
+#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
+#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
+#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
+#define PMU1_PLL0_PC2_NDIV_MODE_MASH 1
+#define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */
+#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
+#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
+
+/* ndiv_frac */
+#define PMU1_PLL0_PLLCTL3 3
+#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
+#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
+
+/* pll_ctrl */
+#define PMU1_PLL0_PLLCTL4 4
+
+/* pll_ctrl, vco_rng, clkdrive_ch<x> */
+#define PMU1_PLL0_PLLCTL5 5
+#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
+#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
+
+/* PMU rev 2 control words */
+#define PMU2_PHY_PLL_PLLCTL 4
+#define PMU2_SI_PLL_PLLCTL 10
+
+/* PMU rev 2 */
+/* pllcontrol registers */
+/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
+#define PMU2_PLL_PLLCTL0 0
+#define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000
+#define PMU2_PLL_PC0_P1DIV_SHIFT 20
+#define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000
+#define PMU2_PLL_PC0_P2DIV_SHIFT 24
+
+/* m<x>div */
+#define PMU2_PLL_PLLCTL1 1
+#define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff
+#define PMU2_PLL_PC1_M1DIV_SHIFT 0
+#define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00
+#define PMU2_PLL_PC1_M2DIV_SHIFT 8
+#define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000
+#define PMU2_PLL_PC1_M3DIV_SHIFT 16
+#define PMU2_PLL_PC1_M4DIV_MASK 0xff000000
+#define PMU2_PLL_PC1_M4DIV_SHIFT 24
+
+/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
+#define PMU2_PLL_PLLCTL2 2
+#define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff
+#define PMU2_PLL_PC2_M5DIV_SHIFT 0
+#define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00
+#define PMU2_PLL_PC2_M6DIV_SHIFT 8
+#define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000
+#define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17
+#define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000
+#define PMU2_PLL_PC2_NDIV_INT_SHIFT 20
+
+/* ndiv_frac */
+#define PMU2_PLL_PLLCTL3 3
+#define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff
+#define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0
+
+/* pll_ctrl */
+#define PMU2_PLL_PLLCTL4 4
+
+/* pll_ctrl, vco_rng, clkdrive_ch<x> */
+#define PMU2_PLL_PLLCTL5 5
+#define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00
+#define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8
+#define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000
+#define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12
+#define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000
+#define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16
+#define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000
+#define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20
+#define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000
+#define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24
+#define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000
+#define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28
+
+/* PMU rev 5 (& 6) */
+#define PMU5_PLL_P1P2_OFF 0
+#define PMU5_PLL_P1_MASK 0x0f000000
+#define PMU5_PLL_P1_SHIFT 24
+#define PMU5_PLL_P2_MASK 0x00f00000
+#define PMU5_PLL_P2_SHIFT 20
+#define PMU5_PLL_M14_OFF 1
+#define PMU5_PLL_MDIV_MASK 0x000000ff
+#define PMU5_PLL_MDIV_WIDTH 8
+#define PMU5_PLL_NM5_OFF 2
+#define PMU5_PLL_NDIV_MASK 0xfff00000
+#define PMU5_PLL_NDIV_SHIFT 20
+#define PMU5_PLL_NDIV_MODE_MASK 0x000e0000
+#define PMU5_PLL_NDIV_MODE_SHIFT 17
+#define PMU5_PLL_FMAB_OFF 3
+#define PMU5_PLL_MRAT_MASK 0xf0000000
+#define PMU5_PLL_MRAT_SHIFT 28
+#define PMU5_PLL_ABRAT_MASK 0x08000000
+#define PMU5_PLL_ABRAT_SHIFT 27
+#define PMU5_PLL_FDIV_MASK 0x07ffffff
+#define PMU5_PLL_PLLCTL_OFF 4
+#define PMU5_PLL_PCHI_OFF 5
+#define PMU5_PLL_PCHI_MASK 0x0000003f
+
+/* pmu XtalFreqRatio */
+#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
+#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
+#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
+
+/* Divider allocation in 4716/47162/5356/5357 */
+#define PMU5_MAINPLL_CPU 1
+#define PMU5_MAINPLL_MEM 2
+#define PMU5_MAINPLL_SI 3
+
+#define PMU7_PLL_PLLCTL7 7
+#define PMU7_PLL_PLLCTL8 8
+#define PMU7_PLL_PLLCTL11 11
+
+/* PLL usage in 4716/47162 */
+#define PMU4716_MAINPLL_PLL0 12
+
+/* PLL usage in 5356/5357 */
+#define PMU5356_MAINPLL_PLL0 0
+#define PMU5357_MAINPLL_PLL0 0
+
+/* 4328 resources */
+#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
+#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
+#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
+#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
+#define RES4328_ILP_REQUEST 4 /* 0x00010 */
+#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
+#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
+#define RES4328_ROM_SWITCH 7 /* 0x00080 */
+#define RES4328_PA_REF_LDO 8 /* 0x00100 */
+#define RES4328_RADIO_LDO 9 /* 0x00200 */
+#define RES4328_AFE_LDO 10 /* 0x00400 */
+#define RES4328_PLL_LDO 11 /* 0x00800 */
+#define RES4328_BG_FILTBYP 12 /* 0x01000 */
+#define RES4328_TX_FILTBYP 13 /* 0x02000 */
+#define RES4328_RX_FILTBYP 14 /* 0x04000 */
+#define RES4328_XTAL_PU 15 /* 0x08000 */
+#define RES4328_XTAL_EN 16 /* 0x10000 */
+#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
+#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
+#define RES4328_BB_PLL_PU 19 /* 0x80000 */
+
+/* 4325 A0/A1 resources */
+#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
+#define RES4325_CBUCK_BURST 1 /* 0x00000002 */
+#define RES4325_CBUCK_PWM 2 /* 0x00000004 */
+#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
+#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
+#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
+#define RES4325_ILP_REQUEST 6 /* 0x00000040 */
+#define RES4325_ABUCK_BURST 7 /* 0x00000080 */
+#define RES4325_ABUCK_PWM 8 /* 0x00000100 */
+#define RES4325_LNLDO1_PU 9 /* 0x00000200 */
+#define RES4325_OTP_PU 10 /* 0x00000400 */
+#define RES4325_LNLDO3_PU 11 /* 0x00000800 */
+#define RES4325_LNLDO4_PU 12 /* 0x00001000 */
+#define RES4325_XTAL_PU 13 /* 0x00002000 */
+#define RES4325_ALP_AVAIL 14 /* 0x00004000 */
+#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
+#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
+#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
+#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
+#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
+#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
+#define RES4325_HT_AVAIL 21 /* 0x00200000 */
+
+/* 4325 B0/C0 resources */
+#define RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */
+#define RES4325B0_CBUCK_BURST 2 /* 0x00000004 */
+#define RES4325B0_CBUCK_PWM 3 /* 0x00000008 */
+#define RES4325B0_CLDO_PU 4 /* 0x00000010 */
+
+/* 4325 C1 resources */
+#define RES4325C1_LNLDO2_PU 12 /* 0x00001000 */
+
+#define RES4329_RESERVED0 0 /* 0x00000001 */
+#define RES4329_CBUCK_LPOM 1 /* 0x00000002 */
+#define RES4329_CBUCK_BURST 2 /* 0x00000004 */
+#define RES4329_CBUCK_PWM 3 /* 0x00000008 */
+#define RES4329_CLDO_PU 4 /* 0x00000010 */
+#define RES4329_PALDO_PU 5 /* 0x00000020 */
+#define RES4329_ILP_REQUEST 6 /* 0x00000040 */
+#define RES4329_RESERVED7 7 /* 0x00000080 */
+#define RES4329_RESERVED8 8 /* 0x00000100 */
+#define RES4329_LNLDO1_PU 9 /* 0x00000200 */
+#define RES4329_OTP_PU 10 /* 0x00000400 */
+#define RES4329_RESERVED11 11 /* 0x00000800 */
+#define RES4329_LNLDO2_PU 12 /* 0x00001000 */
+#define RES4329_XTAL_PU 13 /* 0x00002000 */
+#define RES4329_ALP_AVAIL 14 /* 0x00004000 */
+#define RES4329_RX_PWRSW_PU 15 /* 0x00008000 */
+#define RES4329_TX_PWRSW_PU 16 /* 0x00010000 */
+#define RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */
+#define RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */
+#define RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */
+#define RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */
+#define RES4329_HT_AVAIL 21 /* 0x00200000 */
+
+/* 4315 resources */
+#define RES4315_CBUCK_LPOM 1 /* 0x00000002 */
+#define RES4315_CBUCK_BURST 2 /* 0x00000004 */
+#define RES4315_CBUCK_PWM 3 /* 0x00000008 */
+#define RES4315_CLDO_PU 4 /* 0x00000010 */
+#define RES4315_PALDO_PU 5 /* 0x00000020 */
+#define RES4315_ILP_REQUEST 6 /* 0x00000040 */
+#define RES4315_LNLDO1_PU 9 /* 0x00000200 */
+#define RES4315_OTP_PU 10 /* 0x00000400 */
+#define RES4315_LNLDO2_PU 12 /* 0x00001000 */
+#define RES4315_XTAL_PU 13 /* 0x00002000 */
+#define RES4315_ALP_AVAIL 14 /* 0x00004000 */
+#define RES4315_RX_PWRSW_PU 15 /* 0x00008000 */
+#define RES4315_TX_PWRSW_PU 16 /* 0x00010000 */
+#define RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */
+#define RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */
+#define RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */
+#define RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */
+#define RES4315_HT_AVAIL 21 /* 0x00200000 */
+
+/* 4319 resources */
+#define RES4319_CBUCK_LPOM 1 /* 0x00000002 */
+#define RES4319_CBUCK_BURST 2 /* 0x00000004 */
+#define RES4319_CBUCK_PWM 3 /* 0x00000008 */
+#define RES4319_CLDO_PU 4 /* 0x00000010 */
+#define RES4319_PALDO_PU 5 /* 0x00000020 */
+#define RES4319_ILP_REQUEST 6 /* 0x00000040 */
+#define RES4319_LNLDO1_PU 9 /* 0x00000200 */
+#define RES4319_OTP_PU 10 /* 0x00000400 */
+#define RES4319_LNLDO2_PU 12 /* 0x00001000 */
+#define RES4319_XTAL_PU 13 /* 0x00002000 */
+#define RES4319_ALP_AVAIL 14 /* 0x00004000 */
+#define RES4319_RX_PWRSW_PU 15 /* 0x00008000 */
+#define RES4319_TX_PWRSW_PU 16 /* 0x00010000 */
+#define RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */
+#define RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */
+#define RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */
+#define RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */
+#define RES4319_HT_AVAIL 21 /* 0x00200000 */
+
+#define CCTL_4319USB_XTAL_SEL_MASK 0x00180000
+#define CCTL_4319USB_XTAL_SEL_SHIFT 19
+#define CCTL_4319USB_48MHZ_PLL_SEL 1
+#define CCTL_4319USB_24MHZ_PLL_SEL 2
+
+/* PMU resources for 4336 */
+#define RES4336_CBUCK_LPOM 0
+#define RES4336_CBUCK_BURST 1
+#define RES4336_CBUCK_LP_PWM 2
+#define RES4336_CBUCK_PWM 3
+#define RES4336_CLDO_PU 4
+#define RES4336_DIS_INT_RESET_PD 5
+#define RES4336_ILP_REQUEST 6
+#define RES4336_LNLDO_PU 7
+#define RES4336_LDO3P3_PU 8
+#define RES4336_OTP_PU 9
+#define RES4336_XTAL_PU 10
+#define RES4336_ALP_AVAIL 11
+#define RES4336_RADIO_PU 12
+#define RES4336_BG_PU 13
+#define RES4336_VREG1p4_PU_PU 14
+#define RES4336_AFE_PWRSW_PU 15
+#define RES4336_RX_PWRSW_PU 16
+#define RES4336_TX_PWRSW_PU 17
+#define RES4336_BB_PWRSW_PU 18
+#define RES4336_SYNTH_PWRSW_PU 19
+#define RES4336_MISC_PWRSW_PU 20
+#define RES4336_LOGEN_PWRSW_PU 21
+#define RES4336_BBPLL_PWRSW_PU 22
+#define RES4336_MACPHY_CLKAVAIL 23
+#define RES4336_HT_AVAIL 24
+#define RES4336_RSVD 25
+
+/* 4330 resources */
+#define RES4330_CBUCK_LPOM 0
+#define RES4330_CBUCK_BURST 1
+#define RES4330_CBUCK_LP_PWM 2
+#define RES4330_CBUCK_PWM 3
+#define RES4330_CLDO_PU 4
+#define RES4330_DIS_INT_RESET_PD 5
+#define RES4330_ILP_REQUEST 6
+#define RES4330_LNLDO_PU 7
+#define RES4330_LDO3P3_PU 8
+#define RES4330_OTP_PU 9
+#define RES4330_XTAL_PU 10
+#define RES4330_ALP_AVAIL 11
+#define RES4330_RADIO_PU 12
+#define RES4330_BG_PU 13
+#define RES4330_VREG1p4_PU_PU 14
+#define RES4330_AFE_PWRSW_PU 15
+#define RES4330_RX_PWRSW_PU 16
+#define RES4330_TX_PWRSW_PU 17
+#define RES4330_BB_PWRSW_PU 18
+#define RES4330_SYNTH_PWRSW_PU 19
+#define RES4330_MISC_PWRSW_PU 20
+#define RES4330_LOGEN_PWRSW_PU 21
+#define RES4330_BBPLL_PWRSW_PU 22
+#define RES4330_MACPHY_CLKAVAIL 23
+#define RES4330_HT_AVAIL 24
+#define RES4330_5gRX_PWRSW_PU 25
+#define RES4330_5gTX_PWRSW_PU 26
+#define RES4330_5g_LOGEN_PWRSW_PU 27
+
+/* 4313 resources */
+#define RES4313_BB_PU_RSRC 0
+#define RES4313_ILP_REQ_RSRC 1
+#define RES4313_XTAL_PU_RSRC 2
+#define RES4313_ALP_AVAIL_RSRC 3
+#define RES4313_RADIO_PU_RSRC 4
+#define RES4313_BG_PU_RSRC 5
+#define RES4313_VREG1P4_PU_RSRC 6
+#define RES4313_AFE_PWRSW_RSRC 7
+#define RES4313_RX_PWRSW_RSRC 8
+#define RES4313_TX_PWRSW_RSRC 9
+#define RES4313_BB_PWRSW_RSRC 10
+#define RES4313_SYNTH_PWRSW_RSRC 11
+#define RES4313_MISC_PWRSW_RSRC 12
+#define RES4313_BB_PLL_PWRSW_RSRC 13
+#define RES4313_HT_AVAIL_RSRC 14
+#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
+
+/* PMU resource up transition time in ILP cycles */
+#define PMURES_UP_TRANSITION 2
+
+/* Setup resource up/down timers */
+typedef struct {
+ u8 resnum;
+ u16 updown;
+} pmu_res_updown_t;
+
+/* Change resource dependancies masks */
+typedef struct {
+ u32 res_mask; /* resources (chip specific) */
+ s8 action; /* action */
+ u32 depend_mask; /* changes to the dependancies mask */
+ /* action is taken when filter is NULL or return true: */
+ bool(*filter) (struct si_pub *sih);
+} pmu_res_depend_t;
+
+/* setup pll and query clock speed */
+typedef struct {
+ u16 fref;
+ u8 xf;
+ u8 p1div;
+ u8 p2div;
+ u8 ndiv_int;
+ u32 ndiv_frac;
+} pmu1_xtaltab0_t;
+
+/*
+ * prototypes used in resource tables
+ */
+static bool si_pmu_res_depfltr_bb(struct si_pub *sih);
+static bool si_pmu_res_depfltr_ncb(struct si_pub *sih);
+static bool si_pmu_res_depfltr_paldo(struct si_pub *sih);
+static bool si_pmu_res_depfltr_npaldo(struct si_pub *sih);
+
+static const pmu_res_updown_t bcm4328a0_res_updown[] = {
+ {
+ RES4328_EXT_SWITCHER_PWM, 0x0101}, {
+ RES4328_BB_SWITCHER_PWM, 0x1f01}, {
+ RES4328_BB_SWITCHER_BURST, 0x010f}, {
+ RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, {
+ RES4328_ILP_REQUEST, 0x0202}, {
+ RES4328_RADIO_SWITCHER_PWM, 0x0f01}, {
+ RES4328_RADIO_SWITCHER_BURST, 0x0f01}, {
+ RES4328_ROM_SWITCH, 0x0101}, {
+ RES4328_PA_REF_LDO, 0x0f01}, {
+ RES4328_RADIO_LDO, 0x0f01}, {
+ RES4328_AFE_LDO, 0x0f01}, {
+ RES4328_PLL_LDO, 0x0f01}, {
+ RES4328_BG_FILTBYP, 0x0101}, {
+ RES4328_TX_FILTBYP, 0x0101}, {
+ RES4328_RX_FILTBYP, 0x0101}, {
+ RES4328_XTAL_PU, 0x0101}, {
+ RES4328_XTAL_EN, 0xa001}, {
+ RES4328_BB_PLL_FILTBYP, 0x0101}, {
+ RES4328_RF_PLL_FILTBYP, 0x0101}, {
+ RES4328_BB_PLL_PU, 0x0701}
+};
+
+static const pmu_res_depend_t bcm4328a0_res_depend[] = {
+ /* Adjust ILP request resource not to force ext/BB switchers into burst mode */
+ {
+ PMURES_BIT(RES4328_ILP_REQUEST),
+ RES_DEPEND_SET,
+ PMURES_BIT(RES4328_EXT_SWITCHER_PWM) |
+ PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL}
+};
+
+static const pmu_res_updown_t bcm4325a0_res_updown_qt[] = {
+ {
+ RES4325_HT_AVAIL, 0x0300}, {
+ RES4325_BBPLL_PWRSW_PU, 0x0101}, {
+ RES4325_RFPLL_PWRSW_PU, 0x0101}, {
+ RES4325_ALP_AVAIL, 0x0100}, {
+ RES4325_XTAL_PU, 0x1000}, {
+ RES4325_LNLDO1_PU, 0x0800}, {
+ RES4325_CLDO_CBUCK_PWM, 0x0101}, {
+ RES4325_CBUCK_PWM, 0x0803}
+};
+
+static const pmu_res_updown_t bcm4325a0_res_updown[] = {
+ {
+ RES4325_XTAL_PU, 0x1501}
+};
+
+static const pmu_res_depend_t bcm4325a0_res_depend[] = {
+ /* Adjust OTP PU resource dependencies - remove BB BURST */
+ {
+ PMURES_BIT(RES4325_OTP_PU),
+ RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL},
+ /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */
+ {
+ PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4325_BUCK_BOOST_BURST) |
+ PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb},
+ /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
+ {
+ PMURES_BIT(RES4325_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4325_RX_PWRSW_PU) |
+ PMURES_BIT(RES4325_TX_PWRSW_PU) |
+ PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL},
+ /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
+ {
+ PMURES_BIT(RES4325_ILP_REQUEST) |
+ PMURES_BIT(RES4325_ABUCK_BURST) |
+ PMURES_BIT(RES4325_ABUCK_PWM) |
+ PMURES_BIT(RES4325_LNLDO1_PU) |
+ PMURES_BIT(RES4325C1_LNLDO2_PU) |
+ PMURES_BIT(RES4325_XTAL_PU) |
+ PMURES_BIT(RES4325_ALP_AVAIL) |
+ PMURES_BIT(RES4325_RX_PWRSW_PU) |
+ PMURES_BIT(RES4325_TX_PWRSW_PU) |
+ PMURES_BIT(RES4325_RFPLL_PWRSW_PU) |
+ PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4325_AFE_PWRSW_PU) |
+ PMURES_BIT(RES4325_BBPLL_PWRSW_PU) |
+ PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4325B0_CBUCK_LPOM) |
+ PMURES_BIT(RES4325B0_CBUCK_BURST) |
+ PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb}
+};
+
+static const pmu_res_updown_t bcm4315a0_res_updown_qt[] = {
+ {
+ RES4315_HT_AVAIL, 0x0101}, {
+ RES4315_XTAL_PU, 0x0100}, {
+ RES4315_LNLDO1_PU, 0x0100}, {
+ RES4315_PALDO_PU, 0x0100}, {
+ RES4315_CLDO_PU, 0x0100}, {
+ RES4315_CBUCK_PWM, 0x0100}, {
+ RES4315_CBUCK_BURST, 0x0100}, {
+ RES4315_CBUCK_LPOM, 0x0100}
+};
+
+static const pmu_res_updown_t bcm4315a0_res_updown[] = {
+ {
+ RES4315_XTAL_PU, 0x2501}
+};
+
+static const pmu_res_depend_t bcm4315a0_res_depend[] = {
+ /* Adjust OTP PU resource dependencies - not need PALDO unless write */
+ {
+ PMURES_BIT(RES4315_OTP_PU),
+ RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo},
+ /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */
+ {
+ PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo},
+ /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
+ {
+ PMURES_BIT(RES4315_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4315_RX_PWRSW_PU) |
+ PMURES_BIT(RES4315_TX_PWRSW_PU) |
+ PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL},
+ /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
+ {
+ PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) |
+ PMURES_BIT(RES4315_LNLDO1_PU) |
+ PMURES_BIT(RES4315_OTP_PU) |
+ PMURES_BIT(RES4315_LNLDO2_PU) |
+ PMURES_BIT(RES4315_XTAL_PU) |
+ PMURES_BIT(RES4315_ALP_AVAIL) |
+ PMURES_BIT(RES4315_RX_PWRSW_PU) |
+ PMURES_BIT(RES4315_TX_PWRSW_PU) |
+ PMURES_BIT(RES4315_RFPLL_PWRSW_PU) |
+ PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4315_AFE_PWRSW_PU) |
+ PMURES_BIT(RES4315_BBPLL_PWRSW_PU) |
+ PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4315_CBUCK_LPOM) |
+ PMURES_BIT(RES4315_CBUCK_BURST) |
+ PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb}
+};
+
+ /* 4329 specific. needs to come back this issue later */
+static const pmu_res_updown_t bcm4329_res_updown[] = {
+ {
+ RES4329_XTAL_PU, 0x1501}
+};
+
+static const pmu_res_depend_t bcm4329_res_depend[] = {
+ /* Adjust HT Avail resource dependencies */
+ {
+ PMURES_BIT(RES4329_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4329_CBUCK_LPOM) |
+ PMURES_BIT(RES4329_CBUCK_BURST) |
+ PMURES_BIT(RES4329_CBUCK_PWM) |
+ PMURES_BIT(RES4329_CLDO_PU) |
+ PMURES_BIT(RES4329_PALDO_PU) |
+ PMURES_BIT(RES4329_LNLDO1_PU) |
+ PMURES_BIT(RES4329_XTAL_PU) |
+ PMURES_BIT(RES4329_ALP_AVAIL) |
+ PMURES_BIT(RES4329_RX_PWRSW_PU) |
+ PMURES_BIT(RES4329_TX_PWRSW_PU) |
+ PMURES_BIT(RES4329_RFPLL_PWRSW_PU) |
+ PMURES_BIT(RES4329_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4329_AFE_PWRSW_PU) |
+ PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL}
+};
+
+static const pmu_res_updown_t bcm4319a0_res_updown_qt[] = {
+ {
+ RES4319_HT_AVAIL, 0x0101}, {
+ RES4319_XTAL_PU, 0x0100}, {
+ RES4319_LNLDO1_PU, 0x0100}, {
+ RES4319_PALDO_PU, 0x0100}, {
+ RES4319_CLDO_PU, 0x0100}, {
+ RES4319_CBUCK_PWM, 0x0100}, {
+ RES4319_CBUCK_BURST, 0x0100}, {
+ RES4319_CBUCK_LPOM, 0x0100}
+};
+
+static const pmu_res_updown_t bcm4319a0_res_updown[] = {
+ {
+ RES4319_XTAL_PU, 0x3f01}
+};
+
+static const pmu_res_depend_t bcm4319a0_res_depend[] = {
+ /* Adjust OTP PU resource dependencies - not need PALDO unless write */
+ {
+ PMURES_BIT(RES4319_OTP_PU),
+ RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo},
+ /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */
+ {
+ PMURES_BIT(RES4319_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo},
+ /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
+ {
+ PMURES_BIT(RES4319_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4319_RX_PWRSW_PU) |
+ PMURES_BIT(RES4319_TX_PWRSW_PU) |
+ PMURES_BIT(RES4319_RFPLL_PWRSW_PU) |
+ PMURES_BIT(RES4319_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL}
+};
+
+static const pmu_res_updown_t bcm4336a0_res_updown_qt[] = {
+ {
+ RES4336_HT_AVAIL, 0x0101}, {
+ RES4336_XTAL_PU, 0x0100}, {
+ RES4336_CLDO_PU, 0x0100}, {
+ RES4336_CBUCK_PWM, 0x0100}, {
+ RES4336_CBUCK_BURST, 0x0100}, {
+ RES4336_CBUCK_LPOM, 0x0100}
+};
+
+static const pmu_res_updown_t bcm4336a0_res_updown[] = {
+ {
+ RES4336_HT_AVAIL, 0x0D01}
+};
+
+static const pmu_res_depend_t bcm4336a0_res_depend[] = {
+ /* Just a dummy entry for now */
+ {
+ PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL}
+};
+
+static const pmu_res_updown_t bcm4330a0_res_updown_qt[] = {
+ {
+ RES4330_HT_AVAIL, 0x0101}, {
+ RES4330_XTAL_PU, 0x0100}, {
+ RES4330_CLDO_PU, 0x0100}, {
+ RES4330_CBUCK_PWM, 0x0100}, {
+ RES4330_CBUCK_BURST, 0x0100}, {
+ RES4330_CBUCK_LPOM, 0x0100}
+};
+
+static const pmu_res_updown_t bcm4330a0_res_updown[] = {
+ {
+ RES4330_HT_AVAIL, 0x0e02}
+};
+
+static const pmu_res_depend_t bcm4330a0_res_depend[] = {
+ /* Just a dummy entry for now */
+ {
+ PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL}
+};
+
+/* the following table is based on 1440Mhz fvco */
+static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = {
+ {
+ 12000, 1, 1, 1, 0x78, 0x0}, {
+ 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, {
+ 14400, 3, 1, 1, 0x64, 0x0}, {
+ 15360, 4, 1, 1, 0x5D, 0xC00000}, {
+ 16200, 5, 1, 1, 0x58, 0xE38E38}, {
+ 16800, 6, 1, 1, 0x55, 0xB6DB6D}, {
+ 19200, 7, 1, 1, 0x4B, 0}, {
+ 19800, 8, 1, 1, 0x48, 0xBA2E8B}, {
+ 20000, 9, 1, 1, 0x48, 0x0}, {
+ 25000, 10, 1, 1, 0x39, 0x999999}, {
+ 26000, 11, 1, 1, 0x37, 0x627627}, {
+ 30000, 12, 1, 1, 0x30, 0x0}, {
+ 37400, 13, 2, 1, 0x4D, 0x15E76}, {
+ 38400, 13, 2, 1, 0x4B, 0x0}, {
+ 40000, 14, 2, 1, 0x48, 0x0}, {
+ 48000, 15, 2, 1, 0x3c, 0x0}, {
+ 0, 0, 0, 0, 0, 0}
+};
+
+static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = {
+ {
+ 12000, 1, 1, 1, 0x50, 0x0}, {
+ 13000, 2, 1, 1, 0x49, 0xD89D89}, {
+ 14400, 3, 1, 1, 0x42, 0xAAAAAA}, {
+ 15360, 4, 1, 1, 0x3E, 0x800000}, {
+ 16200, 5, 1, 1, 0x39, 0x425ED0}, {
+ 16800, 6, 1, 1, 0x39, 0x249249}, {
+ 19200, 7, 1, 1, 0x32, 0x0}, {
+ 19800, 8, 1, 1, 0x30, 0x7C1F07}, {
+ 20000, 9, 1, 1, 0x30, 0x0}, {
+ 25000, 10, 1, 1, 0x26, 0x666666}, {
+ 26000, 11, 1, 1, 0x24, 0xEC4EC4}, {
+ 30000, 12, 1, 1, 0x20, 0x0}, {
+ 37400, 13, 2, 1, 0x33, 0x563EF9}, {
+ 38400, 14, 2, 1, 0x32, 0x0}, {
+ 40000, 15, 2, 1, 0x30, 0x0}, {
+ 48000, 16, 2, 1, 0x28, 0x0}, {
+ 0, 0, 0, 0, 0, 0}
+};
+
+static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = {
+ {
+ 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
+ 13000, 2, 1, 6, 0xb, 0x483483}, {
+ 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
+ 15360, 4, 1, 5, 0xb, 0x755555}, {
+ 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
+ 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
+ 19200, 7, 1, 4, 0xb, 0x755555}, {
+ 19800, 8, 1, 11, 0x4, 0xA57EB}, {
+ 20000, 9, 1, 11, 0x4, 0x0}, {
+ 24000, 10, 3, 11, 0xa, 0x0}, {
+ 25000, 11, 5, 16, 0xb, 0x0}, {
+ 26000, 12, 1, 1, 0x21, 0xD89D89}, {
+ 30000, 13, 3, 8, 0xb, 0x0}, {
+ 37400, 14, 3, 1, 0x46, 0x969696}, {
+ 38400, 15, 1, 1, 0x16, 0xEAAAAA}, {
+ 40000, 16, 1, 2, 0xb, 0}, {
+ 0, 0, 0, 0, 0, 0}
+};
+
+/* the following table is based on 880Mhz fvco */
+static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = {
+ {
+ 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
+ 13000, 2, 1, 6, 0xb, 0x483483}, {
+ 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
+ 15360, 4, 1, 5, 0xb, 0x755555}, {
+ 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
+ 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
+ 19200, 7, 1, 4, 0xb, 0x755555}, {
+ 19800, 8, 1, 11, 0x4, 0xA57EB}, {
+ 20000, 9, 1, 11, 0x4, 0x0}, {
+ 24000, 10, 3, 11, 0xa, 0x0}, {
+ 25000, 11, 5, 16, 0xb, 0x0}, {
+ 26000, 12, 1, 2, 0x10, 0xEC4EC4}, {
+ 30000, 13, 3, 8, 0xb, 0x0}, {
+ 33600, 14, 1, 2, 0xd, 0x186186}, {
+ 38400, 15, 1, 2, 0xb, 0x755555}, {
+ 40000, 16, 1, 2, 0xb, 0}, {
+ 0, 0, 0, 0, 0, 0}
+};
+
+/* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
+static bool si_pmu_res_depfltr_bb(struct si_pub *sih)
+{
+ return (sih->boardflags & BFL_BUCKBOOST) != 0;
+}
+
+/* true if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
+static bool si_pmu_res_depfltr_ncb(struct si_pub *sih)
+{
+
+ return (sih->boardflags & BFL_NOCBUCK) != 0;
+}
+
+/* true if the power topology uses the PALDO */
+static bool si_pmu_res_depfltr_paldo(struct si_pub *sih)
+{
+ return (sih->boardflags & BFL_PALDO) != 0;
+}
+
+/* true if the power topology doesn't use the PALDO */
+static bool si_pmu_res_depfltr_npaldo(struct si_pub *sih)
+{
+ return (sih->boardflags & BFL_PALDO) == 0;
+}
+
+/* Return dependancies (direct or all/indirect) for the given resources */
+static u32
+si_pmu_res_deps(struct si_pub *sih, chipcregs_t *cc, u32 rsrcs,
+ bool all)
+{
+ u32 deps = 0;
+ u32 i;
+
+ for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
+ if (!(rsrcs & PMURES_BIT(i)))
+ continue;
+ W_REG(&cc->res_table_sel, i);
+ deps |= R_REG(&cc->res_dep_mask);
+ }
+
+ return !all ? deps : (deps
+ ? (deps |
+ si_pmu_res_deps(sih, cc, deps,
+ true)) : 0);
+}
+
+/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
+static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
+{
+ u32 min_mask = 0, max_mask = 0;
+ uint rsrcs;
+ char *val;
+
+ /* # resources */
+ rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
+
+ /* determine min/max rsrc masks */
+ switch (sih->chip) {
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ /* ??? */
+ break;
+
+ case BCM4329_CHIP_ID:
+ /* 4329 spedific issue. Needs to come back this issue later */
+ /* Down to save the power. */
+ min_mask =
+ PMURES_BIT(RES4329_CBUCK_LPOM) |
+ PMURES_BIT(RES4329_CLDO_PU);
+ /* Allow (but don't require) PLL to turn on */
+ max_mask = 0x3ff63e;
+ break;
+ case BCM4319_CHIP_ID:
+ /* We only need a few resources to be kept on all the time */
+ min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
+ PMURES_BIT(RES4319_CLDO_PU);
+
+ /* Allow everything else to be turned on upon requests */
+ max_mask = ~(~0 << rsrcs);
+ break;
+ case BCM4336_CHIP_ID:
+ /* Down to save the power. */
+ min_mask =
+ PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU)
+ | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU)
+ | PMURES_BIT(RES4336_DIS_INT_RESET_PD);
+ /* Allow (but don't require) PLL to turn on */
+ max_mask = 0x1ffffff;
+ break;
+
+ case BCM4330_CHIP_ID:
+ /* Down to save the power. */
+ min_mask =
+ PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU)
+ | PMURES_BIT(RES4330_DIS_INT_RESET_PD) |
+ PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU);
+ /* Allow (but don't require) PLL to turn on */
+ max_mask = 0xfffffff;
+ break;
+
+ case BCM4313_CHIP_ID:
+ min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
+ PMURES_BIT(RES4313_XTAL_PU_RSRC) |
+ PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
+ PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
+ max_mask = 0xffff;
+ break;
+ default:
+ break;
+ }
+
+ /* Apply nvram override to min mask */
+ val = getvar(NULL, "rmin");
+ if (val != NULL) {
+ min_mask = (u32) simple_strtoul(val, NULL, 0);
+ }
+ /* Apply nvram override to max mask */
+ val = getvar(NULL, "rmax");
+ if (val != NULL) {
+ max_mask = (u32) simple_strtoul(val, NULL, 0);
+ }
+
+ *pmin = min_mask;
+ *pmax = max_mask;
+}
+
+/* Return up time in ILP cycles for the given resource. */
+static uint
+si_pmu_res_uptime(struct si_pub *sih, chipcregs_t *cc, u8 rsrc) {
+ u32 deps;
+ uint up, i, dup, dmax;
+ u32 min_mask = 0, max_mask = 0;
+
+ /* uptime of resource 'rsrc' */
+ W_REG(&cc->res_table_sel, rsrc);
+ up = (R_REG(&cc->res_updn_timer) >> 8) & 0xff;
+
+ /* direct dependancies of resource 'rsrc' */
+ deps = si_pmu_res_deps(sih, cc, PMURES_BIT(rsrc), false);
+ for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
+ if (!(deps & PMURES_BIT(i)))
+ continue;
+ deps &= ~si_pmu_res_deps(sih, cc, PMURES_BIT(i), true);
+ }
+ si_pmu_res_masks(sih, &min_mask, &max_mask);
+ deps &= ~min_mask;
+
+ /* max uptime of direct dependancies */
+ dmax = 0;
+ for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
+ if (!(deps & PMURES_BIT(i)))
+ continue;
+ dup = si_pmu_res_uptime(sih, cc, (u8) i);
+ if (dmax < dup)
+ dmax = dup;
+ }
+
+ return up + dmax + PMURES_UP_TRANSITION;
+}
+
+static void
+si_pmu_spuravoid_pllupdate(struct si_pub *sih, chipcregs_t *cc, u8 spuravoid)
+{
+ u32 tmp = 0;
+ u8 phypll_offset = 0;
+ u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
+ u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
+
+ switch (sih->chip) {
+ case BCM5357_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+
+ /*
+ * BCM5357 needs to touch PLL1_PLLCTL[02],
+ * so offset PLL0_PLLCTL[02] by 6
+ */
+ phypll_offset = (sih->chip == BCM5357_CHIP_ID) ? 6 : 0;
+
+ /* RMW only the P1 divider */
+ W_REG(&cc->pllcontrol_addr,
+ PMU1_PLL0_PLLCTL0 + phypll_offset);
+ tmp = R_REG(&cc->pllcontrol_data);
+ tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK));
+ tmp |=
+ (bcm5357_bcm43236_p1div[spuravoid] <<
+ PMU1_PLL0_PC0_P1DIV_SHIFT);
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ /* RMW only the int feedback divider */
+ W_REG(&cc->pllcontrol_addr,
+ PMU1_PLL0_PLLCTL2 + phypll_offset);
+ tmp = R_REG(&cc->pllcontrol_data);
+ tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK);
+ tmp |=
+ (bcm5357_bcm43236_ndiv[spuravoid]) <<
+ PMU1_PLL0_PC2_NDIV_INT_SHIFT;
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ tmp = 1 << 10;
+ break;
+
+ case BCM4331_CHIP_ID:
+ if (spuravoid == 2) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11500014);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x0FC00a08);
+ } else if (spuravoid == 1) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11500014);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x0F600a08);
+ } else {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100014);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x03000a08);
+ }
+ tmp = 1 << 10;
+ break;
+
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ if (spuravoid == 1) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11500010);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x000C0C06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x0F600a08);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x2001E920);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888815);
+ } else {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100010);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x000c0c06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x03000a08);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x200005c0);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888815);
+ }
+ tmp = 1 << 10;
+ break;
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100008);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x0c000c06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x03000a08);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x200005c0);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888855);
+
+ tmp = 1 << 10;
+ break;
+
+ case BCM4716_CHIP_ID:
+ case BCM4748_CHIP_ID:
+ case BCM47162_CHIP_ID:
+ if (spuravoid == 1) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11500060);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x080C0C06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x0F600000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x2001E924);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888815);
+ } else {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100060);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x080c0c06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x03000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x200005c0);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888815);
+ }
+
+ tmp = 3 << 9;
+ break;
+
+ case BCM4319_CHIP_ID:
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100070);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x1014140a);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888854);
+
+ if (spuravoid == 1) {
+ /* spur_avoid ON, so enable 41/82/164Mhz clock mode */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x05201828);
+ } else {
+ /* enable 40/80/160Mhz clock mode */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x05001828);
+ }
+ break;
+ case BCM4336_CHIP_ID:
+ /* Looks like these are only for default xtal freq 26MHz */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x02100020);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x0C0C0C0C);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x01240C0C);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x202C2820);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888825);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ if (spuravoid == 1)
+ W_REG(&cc->pllcontrol_data, 0x00EC4EC4);
+ else
+ W_REG(&cc->pllcontrol_data, 0x00762762);
+
+ tmp = PCTL_PLL_PLLCTL_UPD;
+ break;
+
+ default:
+ /* bail out */
+ return;
+ }
+
+ tmp |= R_REG(&cc->pmucontrol);
+ W_REG(&cc->pmucontrol, tmp);
+}
+
+/* select default xtal frequency for each chip */
+static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(struct si_pub *sih)
+{
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ /* Default to 38400Khz */
+ return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K];
+ case BCM4319_CHIP_ID:
+ /* Default to 30000Khz */
+ return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K];
+ case BCM4336_CHIP_ID:
+ /* Default to 26000Khz */
+ return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K];
+ case BCM4330_CHIP_ID:
+ /* Default to 37400Khz */
+ if (CST4330_CHIPMODE_SDIOD(sih->chipst))
+ return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K];
+ else
+ return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K];
+ default:
+ break;
+ }
+ return NULL;
+}
+
+/* select xtal table for each chip */
+static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(struct si_pub *sih)
+{
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ return pmu1_xtaltab0_880_4329;
+ case BCM4319_CHIP_ID:
+ return pmu1_xtaltab0_1440;
+ case BCM4336_CHIP_ID:
+ return pmu1_xtaltab0_960;
+ case BCM4330_CHIP_ID:
+ if (CST4330_CHIPMODE_SDIOD(sih->chipst))
+ return pmu1_xtaltab0_960;
+ else
+ return pmu1_xtaltab0_1440;
+ default:
+ break;
+ }
+ return NULL;
+}
+
+/* query alp/xtal clock frequency */
+static u32
+si_pmu1_alpclk0(struct si_pub *sih, chipcregs_t *cc)
+{
+ const pmu1_xtaltab0_t *xt;
+ u32 xf;
+
+ /* Find the frequency in the table */
+ xf = (R_REG(&cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
+ PCTL_XTALFREQ_SHIFT;
+ for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
+ if (xt->xf == xf)
+ break;
+ /* Could not find it so assign a default value */
+ if (xt == NULL || xt->fref == 0)
+ xt = si_pmu1_xtaldef0(sih);
+ return xt->fref * 1000;
+}
+
+/* select default pll fvco for each chip */
+static u32 si_pmu1_pllfvco0(struct si_pub *sih)
+{
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ return FVCO_880;
+ case BCM4319_CHIP_ID:
+ return FVCO_1440;
+ case BCM4336_CHIP_ID:
+ return FVCO_960;
+ case BCM4330_CHIP_ID:
+ if (CST4330_CHIPMODE_SDIOD(sih->chipst))
+ return FVCO_960;
+ else
+ return FVCO_1440;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void si_pmu_set_4330_plldivs(struct si_pub *sih)
+{
+ u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
+ u32 m1div, m2div, m3div, m4div, m5div, m6div;
+ u32 pllc1, pllc2;
+
+ m2div = m3div = m4div = m6div = FVCO / 80;
+ m5div = FVCO / 160;
+
+ if (CST4330_CHIPMODE_SDIOD(sih->chipst))
+ m1div = FVCO / 80;
+ else
+ m1div = FVCO / 90;
+ pllc1 =
+ (m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div <<
+ PMU1_PLL0_PC1_M2DIV_SHIFT) |
+ (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div <<
+ PMU1_PLL0_PC1_M4DIV_SHIFT);
+ si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1);
+
+ pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
+ pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK);
+ pllc2 |=
+ ((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) |
+ (m6div << PMU1_PLL0_PC2_M6DIV_SHIFT));
+ si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2);
+}
+
+/* Set up PLL registers in the PMU as per the crystal speed.
+ * XtalFreq field in pmucontrol register being 0 indicates the PLL
+ * is not programmed and the h/w default is assumed to work, in which
+ * case the xtal frequency is unknown to the s/w so we need to call
+ * si_pmu1_xtaldef0() wherever it is needed to return a default value.
+ */
+static void si_pmu1_pllinit0(struct si_pub *sih, chipcregs_t *cc, u32 xtal)
+{
+ const pmu1_xtaltab0_t *xt;
+ u32 tmp;
+ u32 buf_strength = 0;
+ u8 ndiv_mode = 1;
+
+ /* Use h/w default PLL config */
+ if (xtal == 0) {
+ return;
+ }
+
+ /* Find the frequency in the table */
+ for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
+ if (xt->fref == xtal)
+ break;
+
+ /* Check current PLL state, bail out if it has been programmed or
+ * we don't know how to program it.
+ */
+ if (xt == NULL || xt->fref == 0) {
+ return;
+ }
+ /* for 4319 bootloader already programs the PLL but bootloader does not
+ * program the PLL4 and PLL5. So Skip this check for 4319
+ */
+ if ((((R_REG(&cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
+ PCTL_XTALFREQ_SHIFT) == xt->xf) &&
+ !((sih->chip == BCM4319_CHIP_ID)
+ || (sih->chip == BCM4330_CHIP_ID)))
+ return;
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ /* Change the BBPLL drive strength to 8 for all channels */
+ buf_strength = 0x888888;
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
+ PMURES_BIT(RES4329_HT_AVAIL)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
+ PMURES_BIT(RES4329_HT_AVAIL)));
+ SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
+ PMU_MAX_TRANSITION_DLY);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ if (xt->fref == 38400)
+ tmp = 0x200024C0;
+ else if (xt->fref == 37400)
+ tmp = 0x20004500;
+ else if (xt->fref == 26000)
+ tmp = 0x200024C0;
+ else
+ tmp = 0x200005C0; /* Chip Dflt Settings */
+ W_REG(&cc->pllcontrol_data, tmp);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ tmp =
+ R_REG(&cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK;
+ if ((xt->fref == 38400) || (xt->fref == 37400)
+ || (xt->fref == 26000))
+ tmp |= 0x15;
+ else
+ tmp |= 0x25; /* Chip Dflt Settings */
+ W_REG(&cc->pllcontrol_data, tmp);
+ break;
+
+ case BCM4319_CHIP_ID:
+ /* Change the BBPLL drive strength to 2 for all channels */
+ buf_strength = 0x222222;
+
+ /* Make sure the PLL is off */
+ /* WAR65104: Disable the HT_AVAIL resource first and then
+ * after a delay (more than downtime for HT_AVAIL) remove the
+ * BBPLL resource; backplane clock moves to ALP from HT.
+ */
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4319_HT_AVAIL)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4319_HT_AVAIL)));
+
+ udelay(100);
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
+
+ udelay(100);
+ SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
+ PMU_MAX_TRANSITION_DLY);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ tmp = 0x200005c0;
+ W_REG(&cc->pllcontrol_data, tmp);
+ break;
+
+ case BCM4336_CHIP_ID:
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4336_HT_AVAIL) |
+ PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4336_HT_AVAIL) |
+ PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
+ udelay(100);
+ SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
+ PMU_MAX_TRANSITION_DLY);
+ break;
+
+ case BCM4330_CHIP_ID:
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4330_HT_AVAIL) |
+ PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4330_HT_AVAIL) |
+ PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
+ udelay(100);
+ SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
+ PMU_MAX_TRANSITION_DLY);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Write p1div and p2div to pllcontrol[0] */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ tmp = R_REG(&cc->pllcontrol_data) &
+ ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK);
+ tmp |=
+ ((xt->
+ p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
+ ((xt->
+ p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK);
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ if ((sih->chip == BCM4330_CHIP_ID))
+ si_pmu_set_4330_plldivs(sih);
+
+ if ((sih->chip == BCM4329_CHIP_ID)
+ && (sih->chiprev == 0)) {
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ tmp = R_REG(&cc->pllcontrol_data);
+ tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK);
+ tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL;
+ W_REG(&cc->pllcontrol_data, tmp);
+ }
+ if ((sih->chip == BCM4319_CHIP_ID) ||
+ (sih->chip == BCM4336_CHIP_ID) ||
+ (sih->chip == BCM4330_CHIP_ID))
+ ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB;
+ else
+ ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH;
+
+ /* Write ndiv_int and ndiv_mode to pllcontrol[2] */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ tmp = R_REG(&cc->pllcontrol_data) &
+ ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK);
+ tmp |=
+ ((xt->
+ ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) &
+ PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode <<
+ PMU1_PLL0_PC2_NDIV_MODE_SHIFT) &
+ PMU1_PLL0_PC2_NDIV_MODE_MASK);
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ /* Write ndiv_frac to pllcontrol[3] */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ tmp = R_REG(&cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
+ tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) &
+ PMU1_PLL0_PC3_NDIV_FRAC_MASK);
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ /* Write clock driving strength to pllcontrol[5] */
+ if (buf_strength) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ tmp =
+ R_REG(&cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
+ tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT);
+ W_REG(&cc->pllcontrol_data, tmp);
+ }
+
+ /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs
+ * to be updated.
+ */
+ if ((sih->chip == BCM4319_CHIP_ID)
+ && (xt->fref != XTAL_FREQ_30000MHZ)) {
+ W_REG(&cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
+ tmp =
+ R_REG(&cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK;
+ if (xt->fref == XTAL_FREQ_24000MHZ) {
+ tmp |=
+ (CCTL_4319USB_24MHZ_PLL_SEL <<
+ CCTL_4319USB_XTAL_SEL_SHIFT);
+ } else if (xt->fref == XTAL_FREQ_48000MHZ) {
+ tmp |=
+ (CCTL_4319USB_48MHZ_PLL_SEL <<
+ CCTL_4319USB_XTAL_SEL_SHIFT);
+ }
+ W_REG(&cc->chipcontrol_data, tmp);
+ }
+
+ /* Flush deferred pll control registers writes */
+ if (sih->pmurev >= 2)
+ OR_REG(&cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
+
+ /* Write XtalFreq. Set the divisor also. */
+ tmp = R_REG(&cc->pmucontrol) &
+ ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK);
+ tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) &
+ PCTL_ILP_DIV_MASK) |
+ ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
+
+ if ((sih->chip == BCM4329_CHIP_ID)
+ && sih->chiprev == 0) {
+ /* clear the htstretch before clearing HTReqEn */
+ AND_REG(&cc->clkstretch, ~CSTRETCH_HT);
+ tmp &= ~PCTL_HT_REQ_EN;
+ }
+
+ W_REG(&cc->pmucontrol, tmp);
+}
+
+u32 si_pmu_ilp_clock(struct si_pub *sih)
+{
+ static u32 ilpcycles_per_sec;
+
+ if (ISSIM_ENAB(sih) || !PMUCTL_ENAB(sih))
+ return ILP_CLOCK;
+
+ if (ilpcycles_per_sec == 0) {
+ u32 start, end, delta;
+ u32 origidx = ai_coreidx(sih);
+ chipcregs_t *cc = ai_setcoreidx(sih, SI_CC_IDX);
+ start = R_REG(&cc->pmutimer);
+ mdelay(ILP_CALC_DUR);
+ end = R_REG(&cc->pmutimer);
+ delta = end - start;
+ ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
+ ai_setcoreidx(sih, origidx);
+ }
+
+ return ilpcycles_per_sec;
+}
+
+void si_pmu_set_ldo_voltage(struct si_pub *sih, u8 ldo, u8 voltage)
+{
+ u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
+ u8 addr = 0;
+
+ switch (sih->chip) {
+ case BCM4336_CHIP_ID:
+ switch (ldo) {
+ case SET_LDO_VOLTAGE_CLDO_PWM:
+ addr = 4;
+ rc_shift = 1;
+ mask = 0xf;
+ break;
+ case SET_LDO_VOLTAGE_CLDO_BURST:
+ addr = 4;
+ rc_shift = 5;
+ mask = 0xf;
+ break;
+ case SET_LDO_VOLTAGE_LNLDO1:
+ addr = 4;
+ rc_shift = 17;
+ mask = 0xf;
+ break;
+ default:
+ return;
+ }
+ break;
+ case BCM4330_CHIP_ID:
+ switch (ldo) {
+ case SET_LDO_VOLTAGE_CBUCK_PWM:
+ addr = 3;
+ rc_shift = 0;
+ mask = 0x1f;
+ break;
+ default:
+ return;
+ }
+ break;
+ default:
+ return;
+ }
+
+ shift = sr_cntl_shift + rc_shift;
+
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
+ ~0, addr);
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
+ mask << shift, (voltage & mask) << shift);
+}
+
+u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
+{
+ uint delay = PMU_MAX_TRANSITION_DLY;
+ chipcregs_t *cc;
+ uint origidx;
+#ifdef BCMDBG
+ char chn[8];
+ chn[0] = 0; /* to suppress compile error */
+#endif
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ case BCM4313_CHIP_ID:
+ delay = ISSIM_ENAB(sih) ? 70 : 3700;
+ break;
+ case BCM4329_CHIP_ID:
+ if (ISSIM_ENAB(sih))
+ delay = 70;
+ else {
+ u32 ilp = si_pmu_ilp_clock(sih);
+ delay =
+ (si_pmu_res_uptime(sih, cc, RES4329_HT_AVAIL) +
+ D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
+ 1) / ilp);
+ delay = (11 * delay) / 10;
+ }
+ break;
+ case BCM4319_CHIP_ID:
+ delay = ISSIM_ENAB(sih) ? 70 : 3700;
+ break;
+ case BCM4336_CHIP_ID:
+ if (ISSIM_ENAB(sih))
+ delay = 70;
+ else {
+ u32 ilp = si_pmu_ilp_clock(sih);
+ delay =
+ (si_pmu_res_uptime(sih, cc, RES4336_HT_AVAIL) +
+ D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
+ 1) / ilp);
+ delay = (11 * delay) / 10;
+ }
+ break;
+ case BCM4330_CHIP_ID:
+ if (ISSIM_ENAB(sih))
+ delay = 70;
+ else {
+ u32 ilp = si_pmu_ilp_clock(sih);
+ delay =
+ (si_pmu_res_uptime(sih, cc, RES4330_HT_AVAIL) +
+ D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
+ 1) / ilp);
+ delay = (11 * delay) / 10;
+ }
+ break;
+ default:
+ break;
+ }
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+
+ return (u16) delay;
+}
+
+void si_pmu_sprom_enable(struct si_pub *sih, bool enable)
+{
+ chipcregs_t *cc;
+ uint origidx;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+/* Read/write a chipcontrol reg */
+u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
+{
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
+ reg);
+ return ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_data), mask, val);
+}
+
+/* Read/write a regcontrol reg */
+u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
+{
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
+ reg);
+ return ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, regcontrol_data), mask, val);
+}
+
+/* Read/write a pllcontrol reg */
+u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
+{
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
+ reg);
+ return ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, pllcontrol_data), mask, val);
+}
+
+/* PMU PLL update */
+void si_pmu_pllupd(struct si_pub *sih)
+{
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
+ PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
+}
+
+/* query alp/xtal clock frequency */
+u32 si_pmu_alp_clock(struct si_pub *sih)
+{
+ chipcregs_t *cc;
+ uint origidx;
+ u32 clock = ALP_CLOCK;
+
+ /* bail out with default */
+ if (!PMUCTL_ENAB(sih))
+ return clock;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ case BCM4716_CHIP_ID:
+ case BCM4748_CHIP_ID:
+ case BCM47162_CHIP_ID:
+ case BCM4313_CHIP_ID:
+ case BCM5357_CHIP_ID:
+ /* always 20Mhz */
+ clock = 20000 * 1000;
+ break;
+ case BCM4329_CHIP_ID:
+ case BCM4319_CHIP_ID:
+ case BCM4336_CHIP_ID:
+ case BCM4330_CHIP_ID:
+
+ clock = si_pmu1_alpclk0(sih, cc);
+ break;
+ case BCM5356_CHIP_ID:
+ /* always 25Mhz */
+ clock = 25000 * 1000;
+ break;
+ default:
+ break;
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+ return clock;
+}
+
+void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
+{
+ chipcregs_t *cc;
+ uint origidx, intr_val;
+ u32 tmp = 0;
+
+ /* Remember original core before switch to chipc */
+ cc = (chipcregs_t *) ai_switch_core(sih, CC_CORE_ID, &origidx,
+ &intr_val);
+
+ /* force the HT off */
+ if (sih->chip == BCM4336_CHIP_ID) {
+ tmp = R_REG(&cc->max_res_mask);
+ tmp &= ~RES4336_HT_AVAIL;
+ W_REG(&cc->max_res_mask, tmp);
+ /* wait for the ht to really go away */
+ SPINWAIT(((R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL) == 0),
+ 10000);
+ }
+
+ /* update the pll changes */
+ si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
+
+ /* enable HT back on */
+ if (sih->chip == BCM4336_CHIP_ID) {
+ tmp = R_REG(&cc->max_res_mask);
+ tmp |= RES4336_HT_AVAIL;
+ W_REG(&cc->max_res_mask, tmp);
+ }
+
+ /* Return to original core */
+ ai_restore_core(sih, origidx, intr_val);
+}
+
+/* initialize PMU */
+void si_pmu_init(struct si_pub *sih)
+{
+ chipcregs_t *cc;
+ uint origidx;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ if (sih->pmurev == 1)
+ AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
+ else if (sih->pmurev >= 2)
+ OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT);
+
+ if ((sih->chip == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
+ /* Fix for 4329b0 bad LPOM state. */
+ W_REG(&cc->regcontrol_addr, 2);
+ OR_REG(&cc->regcontrol_data, 0x100);
+
+ W_REG(&cc->regcontrol_addr, 3);
+ OR_REG(&cc->regcontrol_data, 0x4);
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+/* initialize PMU chip controls and other chip level stuff */
+void si_pmu_chip_init(struct si_pub *sih)
+{
+ uint origidx;
+
+ /* Gate off SPROM clock and chip select signals */
+ si_pmu_sprom_enable(sih, false);
+
+ /* Remember original core */
+ origidx = ai_coreidx(sih);
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+/* initialize PMU switch/regulators */
+void si_pmu_swreg_init(struct si_pub *sih)
+{
+ switch (sih->chip) {
+ case BCM4336_CHIP_ID:
+ /* Reduce CLDO PWM output voltage to 1.2V */
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
+ /* Reduce CLDO BURST output voltage to 1.2V */
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_BURST,
+ 0xe);
+ /* Reduce LNLDO1 output voltage to 1.2V */
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_LNLDO1, 0xe);
+ if (sih->chiprev == 0)
+ si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
+ break;
+
+ case BCM4330_CHIP_ID:
+ /* CBUCK Voltage is 1.8 by default and set that to 1.5 */
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+/* initialize PLL */
+void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
+{
+ chipcregs_t *cc;
+ uint origidx;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ if (xtalfreq == 0)
+ xtalfreq = 38400;
+ si_pmu1_pllinit0(sih, cc, xtalfreq);
+ break;
+ case BCM4313_CHIP_ID:
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ /* ??? */
+ break;
+ case BCM4319_CHIP_ID:
+ case BCM4336_CHIP_ID:
+ case BCM4330_CHIP_ID:
+ si_pmu1_pllinit0(sih, cc, xtalfreq);
+ break;
+ default:
+ break;
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+/* initialize PMU resources */
+void si_pmu_res_init(struct si_pub *sih)
+{
+ chipcregs_t *cc;
+ uint origidx;
+ const pmu_res_updown_t *pmu_res_updown_table = NULL;
+ uint pmu_res_updown_table_sz = 0;
+ const pmu_res_depend_t *pmu_res_depend_table = NULL;
+ uint pmu_res_depend_table_sz = 0;
+ u32 min_mask = 0, max_mask = 0;
+ char name[8], *val;
+ uint i, rsrcs;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ /* Optimize resources up/down timers */
+ if (ISSIM_ENAB(sih)) {
+ pmu_res_updown_table = NULL;
+ pmu_res_updown_table_sz = 0;
+ } else {
+ pmu_res_updown_table = bcm4329_res_updown;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4329_res_updown);
+ }
+ /* Optimize resources dependencies */
+ pmu_res_depend_table = bcm4329_res_depend;
+ pmu_res_depend_table_sz = ARRAY_SIZE(bcm4329_res_depend);
+ break;
+
+ case BCM4319_CHIP_ID:
+ /* Optimize resources up/down timers */
+ if (ISSIM_ENAB(sih)) {
+ pmu_res_updown_table = bcm4319a0_res_updown_qt;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4319a0_res_updown_qt);
+ } else {
+ pmu_res_updown_table = bcm4319a0_res_updown;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4319a0_res_updown);
+ }
+ /* Optimize resources dependancies masks */
+ pmu_res_depend_table = bcm4319a0_res_depend;
+ pmu_res_depend_table_sz = ARRAY_SIZE(bcm4319a0_res_depend);
+ break;
+
+ case BCM4336_CHIP_ID:
+ /* Optimize resources up/down timers */
+ if (ISSIM_ENAB(sih)) {
+ pmu_res_updown_table = bcm4336a0_res_updown_qt;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4336a0_res_updown_qt);
+ } else {
+ pmu_res_updown_table = bcm4336a0_res_updown;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4336a0_res_updown);
+ }
+ /* Optimize resources dependancies masks */
+ pmu_res_depend_table = bcm4336a0_res_depend;
+ pmu_res_depend_table_sz = ARRAY_SIZE(bcm4336a0_res_depend);
+ break;
+
+ case BCM4330_CHIP_ID:
+ /* Optimize resources up/down timers */
+ if (ISSIM_ENAB(sih)) {
+ pmu_res_updown_table = bcm4330a0_res_updown_qt;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4330a0_res_updown_qt);
+ } else {
+ pmu_res_updown_table = bcm4330a0_res_updown;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4330a0_res_updown);
+ }
+ /* Optimize resources dependancies masks */
+ pmu_res_depend_table = bcm4330a0_res_depend;
+ pmu_res_depend_table_sz = ARRAY_SIZE(bcm4330a0_res_depend);
+ break;
+
+ default:
+ break;
+ }
+
+ /* # resources */
+ rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
+
+ /* Program up/down timers */
+ while (pmu_res_updown_table_sz--) {
+ W_REG(&cc->res_table_sel,
+ pmu_res_updown_table[pmu_res_updown_table_sz].resnum);
+ W_REG(&cc->res_updn_timer,
+ pmu_res_updown_table[pmu_res_updown_table_sz].updown);
+ }
+ /* Apply nvram overrides to up/down timers */
+ for (i = 0; i < rsrcs; i++) {
+ snprintf(name, sizeof(name), "r%dt", i);
+ val = getvar(NULL, name);
+ if (val == NULL)
+ continue;
+ W_REG(&cc->res_table_sel, (u32) i);
+ W_REG(&cc->res_updn_timer,
+ (u32) simple_strtoul(val, NULL, 0));
+ }
+
+ /* Program resource dependencies table */
+ while (pmu_res_depend_table_sz--) {
+ if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL
+ && !(pmu_res_depend_table[pmu_res_depend_table_sz].
+ filter) (sih))
+ continue;
+ for (i = 0; i < rsrcs; i++) {
+ if ((pmu_res_depend_table[pmu_res_depend_table_sz].
+ res_mask & PMURES_BIT(i)) == 0)
+ continue;
+ W_REG(&cc->res_table_sel, i);
+ switch (pmu_res_depend_table[pmu_res_depend_table_sz].
+ action) {
+ case RES_DEPEND_SET:
+ W_REG(&cc->res_dep_mask,
+ pmu_res_depend_table
+ [pmu_res_depend_table_sz].depend_mask);
+ break;
+ case RES_DEPEND_ADD:
+ OR_REG(&cc->res_dep_mask,
+ pmu_res_depend_table
+ [pmu_res_depend_table_sz].depend_mask);
+ break;
+ case RES_DEPEND_REMOVE:
+ AND_REG(&cc->res_dep_mask,
+ ~pmu_res_depend_table
+ [pmu_res_depend_table_sz].depend_mask);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ /* Apply nvram overrides to dependancies masks */
+ for (i = 0; i < rsrcs; i++) {
+ snprintf(name, sizeof(name), "r%dd", i);
+ val = getvar(NULL, name);
+ if (val == NULL)
+ continue;
+ W_REG(&cc->res_table_sel, (u32) i);
+ W_REG(&cc->res_dep_mask,
+ (u32) simple_strtoul(val, NULL, 0));
+ }
+
+ /* Determine min/max rsrc masks */
+ si_pmu_res_masks(sih, &min_mask, &max_mask);
+
+ /* It is required to program max_mask first and then min_mask */
+
+ /* Program max resource mask */
+
+ if (max_mask)
+ W_REG(&cc->max_res_mask, max_mask);
+
+ /* Program min resource mask */
+
+ if (min_mask)
+ W_REG(&cc->min_res_mask, min_mask);
+
+ /* Add some delay; allow resources to come up and settle. */
+ mdelay(2);
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+u32 si_pmu_measure_alpclk(struct si_pub *sih)
+{
+ chipcregs_t *cc;
+ uint origidx;
+ u32 alp_khz;
+
+ if (sih->pmurev < 10)
+ return 0;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) {
+ u32 ilp_ctr, alp_hz;
+
+ /*
+ * Enable the reg to measure the freq,
+ * in case it was disabled before
+ */
+ W_REG(&cc->pmu_xtalfreq,
+ 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
+
+ /* Delay for well over 4 ILP clocks */
+ udelay(1000);
+
+ /* Read the latched number of ALP ticks per 4 ILP ticks */
+ ilp_ctr =
+ R_REG(&cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
+
+ /*
+ * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
+ * bit to save power
+ */
+ W_REG(&cc->pmu_xtalfreq, 0);
+
+ /* Calculate ALP frequency */
+ alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
+
+ /*
+ * Round to nearest 100KHz, and at
+ * the same time convert to KHz
+ */
+ alp_khz = (alp_hz + 50000) / 100000 * 100;
+ } else
+ alp_khz = 0;
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+
+ return alp_khz;
+}
+
+bool si_pmu_is_otp_powered(struct si_pub *sih)
+{
+ uint idx;
+ chipcregs_t *cc;
+ bool st;
+
+ /* Remember original core before switch to chipc */
+ idx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ st = (R_REG(&cc->res_state) & PMURES_BIT(RES4329_OTP_PU))
+ != 0;
+ break;
+ case BCM4319_CHIP_ID:
+ st = (R_REG(&cc->res_state) & PMURES_BIT(RES4319_OTP_PU))
+ != 0;
+ break;
+ case BCM4336_CHIP_ID:
+ st = (R_REG(&cc->res_state) & PMURES_BIT(RES4336_OTP_PU))
+ != 0;
+ break;
+ case BCM4330_CHIP_ID:
+ st = (R_REG(&cc->res_state) & PMURES_BIT(RES4330_OTP_PU))
+ != 0;
+ break;
+
+ /* These chip doesn't use PMU bit to power up/down OTP. OTP always on.
+ * Use OTP_INIT command to reset/refresh state.
+ */
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ st = true;
+ break;
+ default:
+ st = true;
+ break;
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, idx);
+ return st;
+}
+
+/* power up/down OTP through PMU resources */
+void si_pmu_otp_power(struct si_pub *sih, bool on)
+{
+ chipcregs_t *cc;
+ uint origidx;
+ u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
+
+ /* Don't do anything if OTP is disabled */
+ if (ai_is_otp_disabled(sih))
+ return;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ rsrcs = PMURES_BIT(RES4329_OTP_PU);
+ break;
+ case BCM4319_CHIP_ID:
+ rsrcs = PMURES_BIT(RES4319_OTP_PU);
+ break;
+ case BCM4336_CHIP_ID:
+ rsrcs = PMURES_BIT(RES4336_OTP_PU);
+ break;
+ case BCM4330_CHIP_ID:
+ rsrcs = PMURES_BIT(RES4330_OTP_PU);
+ break;
+ default:
+ break;
+ }
+
+ if (rsrcs != 0) {
+ u32 otps;
+
+ /* Figure out the dependancies (exclude min_res_mask) */
+ u32 deps = si_pmu_res_deps(sih, cc, rsrcs, true);
+ u32 min_mask = 0, max_mask = 0;
+ si_pmu_res_masks(sih, &min_mask, &max_mask);
+ deps &= ~min_mask;
+ /* Turn on/off the power */
+ if (on) {
+ OR_REG(&cc->min_res_mask, (rsrcs | deps));
+ SPINWAIT(!(R_REG(&cc->res_state) & rsrcs),
+ PMU_MAX_TRANSITION_DLY);
+ } else {
+ AND_REG(&cc->min_res_mask, ~(rsrcs | deps));
+ }
+
+ SPINWAIT((((otps = R_REG(&cc->otpstatus)) & OTPS_READY) !=
+ (on ? OTPS_READY : 0)), 100);
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _BRCM_PMU_H_
+#define _BRCM_PMU_H_
+
+#include <linux/types.h>
+
+#include <aiutils.h>
+
+/*
+ * LDO selections used in si_pmu_set_ldo_voltage
+ */
+#define SET_LDO_VOLTAGE_LDO1 1
+#define SET_LDO_VOLTAGE_LDO2 2
+#define SET_LDO_VOLTAGE_LDO3 3
+#define SET_LDO_VOLTAGE_PAREF 4
+#define SET_LDO_VOLTAGE_CLDO_PWM 5
+#define SET_LDO_VOLTAGE_CLDO_BURST 6
+#define SET_LDO_VOLTAGE_CBUCK_PWM 7
+#define SET_LDO_VOLTAGE_CBUCK_BURST 8
+#define SET_LDO_VOLTAGE_LNLDO1 9
+#define SET_LDO_VOLTAGE_LNLDO2_SEL 10
+
+extern void si_pmu_set_ldo_voltage(struct si_pub *sih, u8 ldo, u8 voltage);
+extern u16 si_pmu_fast_pwrup_delay(struct si_pub *sih);
+extern void si_pmu_sprom_enable(struct si_pub *sih, bool enable);
+extern u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
+extern u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
+extern u32 si_pmu_ilp_clock(struct si_pub *sih);
+extern u32 si_pmu_alp_clock(struct si_pub *sih);
+extern void si_pmu_pllupd(struct si_pub *sih);
+extern void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid);
+extern u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
+extern void si_pmu_init(struct si_pub *sih);
+extern void si_pmu_chip_init(struct si_pub *sih);
+extern void si_pmu_pll_init(struct si_pub *sih, u32 xtalfreq);
+extern void si_pmu_res_init(struct si_pub *sih);
+extern void si_pmu_swreg_init(struct si_pub *sih);
+extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
+extern bool si_pmu_is_otp_powered(struct si_pub *sih);
+extern void si_pmu_otp_power(struct si_pub *sih, bool on);
+
+#endif /* _BRCM_PMU_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_PUB_H_
+#define _BRCM_PUB_H_
+
+#include "types.h" /* forward structure declarations */
+#include "brcmu_wifi.h" /* for chanspec_t */
+
+#define WLC_NUMRATES 16 /* max # of rates in a rateset */
+#define MAXMULTILIST 32 /* max # multicast addresses */
+#define D11_PHY_HDR_LEN 6 /* Phy header length - 6 bytes */
+
+/* phy types */
+#define PHY_TYPE_A 0 /* Phy type A */
+#define PHY_TYPE_G 2 /* Phy type G */
+#define PHY_TYPE_N 4 /* Phy type N */
+#define PHY_TYPE_LP 5 /* Phy type Low Power A/B/G */
+#define PHY_TYPE_SSN 6 /* Phy type Single Stream N */
+#define PHY_TYPE_LCN 8 /* Phy type Single Stream N */
+#define PHY_TYPE_LCNXN 9 /* Phy type 2-stream N */
+#define PHY_TYPE_HT 7 /* Phy type 3-Stream N */
+
+/* bw */
+#define WLC_10_MHZ 10 /* 10Mhz nphy channel bandwidth */
+#define WLC_20_MHZ 20 /* 20Mhz nphy channel bandwidth */
+#define WLC_40_MHZ 40 /* 40Mhz nphy channel bandwidth */
+
+#define CHSPEC_WLC_BW(chanspec) (CHSPEC_IS40(chanspec) ? WLC_40_MHZ : \
+ CHSPEC_IS20(chanspec) ? WLC_20_MHZ : \
+ WLC_10_MHZ)
+
+#define WLC_RSSI_MINVAL -200 /* Low value, e.g. for forcing roam */
+#define WLC_RSSI_NO_SIGNAL -91 /* NDIS RSSI link quality cutoffs */
+#define WLC_RSSI_VERY_LOW -80 /* Very low quality cutoffs */
+#define WLC_RSSI_LOW -70 /* Low quality cutoffs */
+#define WLC_RSSI_GOOD -68 /* Good quality cutoffs */
+#define WLC_RSSI_VERY_GOOD -58 /* Very good quality cutoffs */
+#define WLC_RSSI_EXCELLENT -57 /* Excellent quality cutoffs */
+
+#define WLC_PHYTYPE(_x) (_x) /* macro to perform WLC PHY -> D11 PHY TYPE, currently 1:1 */
+
+#define MA_WINDOW_SZ 8 /* moving average window size */
+
+#define WLC_SNR_INVALID 0 /* invalid SNR value */
+
+/* a large TX Power as an init value to factor out of min() calculations,
+ * keep low enough to fit in an s8, units are .25 dBm
+ */
+#define WLC_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
+
+/* rate related definitions */
+#define WLC_RATE_FLAG 0x80 /* Flag to indicate it is a basic rate */
+#define WLC_RATE_MASK 0x7f /* Rate value mask w/o basic rate flag */
+
+/* legacy rx Antenna diversity for SISO rates */
+#define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
+#define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
+#define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
+#define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */
+#define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
+#define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */
+
+/* legacy rx Antenna diversity for SISO rates */
+#define ANT_TX_FORCE_0 0 /* Tx on antenna 0, "legacy term Main" */
+#define ANT_TX_FORCE_1 1 /* Tx on antenna 1, "legacy term Aux" */
+#define ANT_TX_LAST_RX 3 /* Tx on phy's last good Rx antenna */
+#define ANT_TX_DEF 3 /* driver's default tx antenna setting */
+
+#define TXCORE_POLICY_ALL 0x1 /* use all available core for transmit */
+
+/* Tx Chain values */
+#define TXCHAIN_DEF 0x1 /* def bitmap of txchain */
+#define TXCHAIN_DEF_NPHY 0x3 /* default bitmap of tx chains for nphy */
+#define TXCHAIN_DEF_HTPHY 0x7 /* default bitmap of tx chains for nphy */
+#define RXCHAIN_DEF 0x1 /* def bitmap of rxchain */
+#define RXCHAIN_DEF_NPHY 0x3 /* default bitmap of rx chains for nphy */
+#define RXCHAIN_DEF_HTPHY 0x7 /* default bitmap of rx chains for nphy */
+#define ANTSWITCH_NONE 0 /* no antenna switch */
+#define ANTSWITCH_TYPE_1 1 /* antenna switch on 4321CB2, 2of3 */
+#define ANTSWITCH_TYPE_2 2 /* antenna switch on 4321MPCI, 2of3 */
+#define ANTSWITCH_TYPE_3 3 /* antenna switch on 4322, 2of3 */
+
+#define RXBUFSZ PKTBUFSZ
+#ifndef AIDMAPSZ
+#define AIDMAPSZ (roundup(MAXSCB, NBBY)/NBBY) /* aid bitmap size in bytes */
+#endif /* AIDMAPSZ */
+
+#define MAX_STREAMS_SUPPORTED 4 /* max number of streams supported */
+
+#define WL_SPURAVOID_OFF 0
+#define WL_SPURAVOID_ON1 1
+#define WL_SPURAVOID_ON2 2
+
+struct ieee80211_tx_queue_params;
+
+typedef struct wlc_tunables {
+ int ntxd; /* size of tx descriptor table */
+ int nrxd; /* size of rx descriptor table */
+ int rxbufsz; /* size of rx buffers to post */
+ int nrxbufpost; /* # of rx buffers to post */
+ int maxscb; /* # of SCBs supported */
+ int ampdunummpdu; /* max number of mpdu in an ampdu */
+ int maxpktcb; /* max # of packet callbacks */
+ int maxucodebss; /* max # of BSS handled in ucode bcn/prb */
+ int maxucodebss4; /* max # of BSS handled in sw bcn/prb */
+ int maxbss; /* max # of bss info elements in scan list */
+ int datahiwat; /* data msg txq hiwat mark */
+ int ampdudatahiwat; /* AMPDU msg txq hiwat mark */
+ int rxbnd; /* max # of rx bufs to process before deferring to dpc */
+ int txsbnd; /* max # tx status to process in wlc_txstatus() */
+ int memreserved; /* memory reserved for BMAC's USB dma rx */
+} wlc_tunables_t;
+
+typedef struct wlc_rateset {
+ uint count; /* number of rates in rates[] */
+ u8 rates[WLC_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
+ u8 htphy_membership; /* HT PHY Membership */
+ u8 mcs[MCSSET_LEN]; /* supported mcs index bit map */
+} wlc_rateset_t;
+
+struct rsn_parms {
+ u8 flags; /* misc booleans (e.g., supported) */
+ u8 multicast; /* multicast cipher */
+ u8 ucount; /* count of unicast ciphers */
+ u8 unicast[4]; /* unicast ciphers */
+ u8 acount; /* count of auth modes */
+ u8 auth[4]; /* Authentication modes */
+ u8 PAD[4]; /* padding for future growth */
+};
+
+/*
+ * 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
+ */
+#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
+
+#define RSN_FLAGS_SUPPORTED 0x1 /* Flag for rsn_params */
+#define RSN_FLAGS_PREAUTH 0x2 /* Flag for WPA2 rsn_params */
+
+/* All the HT-specific default advertised capabilities (including AMPDU)
+ * should be grouped here at one place
+ */
+#define AMPDU_DEF_MPDU_DENSITY 6 /* default mpdu density (110 ==> 4us) */
+
+/* defaults for the HT (MIMO) bss */
+#define HT_CAP (IEEE80211_HT_CAP_SM_PS |\
+ IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_GRN_FLD |\
+ IEEE80211_HT_CAP_MAX_AMSDU | IEEE80211_HT_CAP_DSSSCCK40)
+
+/* wlc internal bss_info */
+typedef struct wlc_bss_info {
+ u8 BSSID[ETH_ALEN]; /* network BSSID */
+ u16 flags; /* flags for internal attributes */
+ u8 SSID_len; /* the length of SSID */
+ u8 SSID[32]; /* SSID string */
+ s16 RSSI; /* receive signal strength (in dBm) */
+ s16 SNR; /* receive signal SNR in dB */
+ u16 beacon_period; /* units are Kusec */
+ u16 atim_window; /* units are Kusec */
+ chanspec_t chanspec; /* Channel num, bw, ctrl_sb and band */
+ s8 infra; /* 0=IBSS, 1=infrastructure, 2=unknown */
+ wlc_rateset_t rateset; /* supported rates */
+ u8 dtim_period; /* DTIM period */
+ s8 phy_noise; /* noise right after tx (in dBm) */
+ u16 capability; /* Capability information */
+ u8 wme_qosinfo; /* QoS Info from WME IE; valid if WLC_BSS_WME flag set */
+ struct rsn_parms wpa;
+ struct rsn_parms wpa2;
+ u16 qbss_load_aac; /* qbss load available admission capacity */
+ /* qbss_load_chan_free <- (0xff - channel_utilization of qbss_load_ie_t) */
+ u8 qbss_load_chan_free; /* indicates how free the channel is */
+ u8 mcipher; /* multicast cipher */
+ u8 wpacfg; /* wpa config index */
+} wlc_bss_info_t;
+
+/* forward declarations */
+struct wlc_if;
+
+/* wlc_ioctl error codes */
+#define WLC_ENOIOCTL 1 /* No such Ioctl */
+#define WLC_EINVAL 2 /* Invalid value */
+#define WLC_ETOOSMALL 3 /* Value too small */
+#define WLC_ETOOBIG 4 /* Value too big */
+#define WLC_ERANGE 5 /* Out of range */
+#define WLC_EDOWN 6 /* Down */
+#define WLC_EUP 7 /* Up */
+#define WLC_ENOMEM 8 /* No Memory */
+#define WLC_EBUSY 9 /* Busy */
+
+/* IOVar flags for common error checks */
+#define IOVF_MFG (1<<3) /* flag for mfgtest iovars */
+#define IOVF_WHL (1<<4) /* value must be whole (0-max) */
+#define IOVF_NTRL (1<<5) /* value must be natural (1-max) */
+
+#define IOVF_SET_UP (1<<6) /* set requires driver be up */
+#define IOVF_SET_DOWN (1<<7) /* set requires driver be down */
+#define IOVF_SET_CLK (1<<8) /* set requires core clock */
+#define IOVF_SET_BAND (1<<9) /* set requires fixed band */
+
+#define IOVF_GET_UP (1<<10) /* get requires driver be up */
+#define IOVF_GET_DOWN (1<<11) /* get requires driver be down */
+#define IOVF_GET_CLK (1<<12) /* get requires core clock */
+#define IOVF_GET_BAND (1<<13) /* get requires fixed band */
+#define IOVF_OPEN_ALLOW (1<<14) /* set allowed iovar for opensrc */
+
+/* watchdog down and dump callback function proto's */
+typedef int (*watchdog_fn_t) (void *handle);
+typedef int (*down_fn_t) (void *handle);
+typedef int (*dump_fn_t) (void *handle, struct brcmu_strbuf *b);
+
+/* IOVar handler
+ *
+ * handle - a pointer value registered with the function
+ * vi - iovar_info that was looked up
+ * actionid - action ID, calculated by IOV_GVAL() and IOV_SVAL() based on varid.
+ * name - the actual iovar name
+ * params/plen - parameters and length for a get, input only.
+ * arg/len - buffer and length for value to be set or retrieved, input or output.
+ * vsize - value size, valid for integer type only.
+ * wlcif - interface context (wlc_if pointer)
+ *
+ * All pointers may point into the same buffer.
+ */
+typedef int (*iovar_fn_t) (void *handle, const struct brcmu_iovar *vi,
+ u32 actionid, const char *name, void *params,
+ uint plen, void *arg, int alen, int vsize,
+ struct wlc_if *wlcif);
+
+#define MAC80211_PROMISC_BCNS (1 << 0)
+#define MAC80211_SCAN (1 << 1)
+
+/*
+ * Public portion of "common" os-independent state structure.
+ * The wlc handle points at this.
+ */
+struct wlc_pub {
+ void *wlc;
+
+ struct ieee80211_hw *ieee_hw;
+ struct scb *global_scb;
+ scb_ampdu_t *global_ampdu;
+ uint mac80211_state;
+ uint unit; /* device instance number */
+ uint corerev; /* core revision */
+ struct si_pub *sih; /* SI handle (cookie for siutils calls) */
+ char *vars; /* "environment" name=value */
+ bool up; /* interface up and running */
+ bool hw_off; /* HW is off */
+ wlc_tunables_t *tunables; /* tunables: ntxd, nrxd, maxscb, etc. */
+ bool hw_up; /* one time hw up/down(from boot or hibernation) */
+ bool _piomode; /* true if pio mode *//* BMAC_NOTE: NEED In both */
+ uint _nbands; /* # bands supported */
+ uint now; /* # elapsed seconds */
+
+ bool promisc; /* promiscuous destination address */
+ bool delayed_down; /* down delayed */
+ bool _ap; /* AP mode enabled */
+ bool _apsta; /* simultaneous AP/STA mode enabled */
+ bool _assoc_recreate; /* association recreation on up transitions */
+ int _wme; /* WME QoS mode */
+ u8 _mbss; /* MBSS mode on */
+ bool allmulti; /* enable all multicasts */
+ bool associated; /* true:part of [I]BSS, false: not */
+ /* (union of stas_associated, aps_associated) */
+ bool phytest_on; /* whether a PHY test is running */
+ bool bf_preempt_4306; /* True to enable 'darwin' mode */
+ bool _ampdu; /* ampdu enabled or not */
+ bool _cac; /* 802.11e CAC enabled */
+ u8 _n_enab; /* bitmap of 11N + HT support */
+ bool _n_reqd; /* N support required for clients */
+
+ s8 _coex; /* 20/40 MHz BSS Management AUTO, ENAB, DISABLE */
+ bool _priofc; /* Priority-based flowcontrol */
+
+ u8 cur_etheraddr[ETH_ALEN]; /* our local ethernet address */
+
+ u8 *multicast; /* ptr to list of multicast addresses */
+ uint nmulticast; /* # enabled multicast addresses */
+
+ u32 wlfeatureflag; /* Flags to control sw features from registry */
+ int psq_pkts_total; /* total num of ps pkts */
+
+ u16 txmaxpkts; /* max number of large pkts allowed to be pending */
+
+ /* s/w decryption counters */
+ u32 swdecrypt; /* s/w decrypt attempts */
+
+ int bcmerror; /* last bcm error */
+
+ mbool radio_disabled; /* bit vector for radio disabled reasons */
+ bool radio_active; /* radio on/off state */
+ u16 roam_time_thresh; /* Max. # secs. of not hearing beacons
+ * before roaming.
+ */
+ bool align_wd_tbtt; /* Align watchdog with tbtt indication
+ * handling. This flag is cleared by default
+ * and is set by per port code explicitly and
+ * you need to make sure the OSL_SYSUPTIME()
+ * is implemented properly in osl of that port
+ * when it enables this Power Save feature.
+ */
+
+ u16 boardrev; /* version # of particular board */
+ u8 sromrev; /* version # of the srom */
+ char srom_ccode[WLC_CNTRY_BUF_SZ]; /* Country Code in SROM */
+ u32 boardflags; /* Board specific flags from srom */
+ u32 boardflags2; /* More board flags if sromrev >= 4 */
+ bool tempsense_disable; /* disable periodic tempsense check */
+ bool phy_11ncapable; /* the PHY/HW is capable of 802.11N */
+ bool _ampdumac; /* mac assist ampdu enabled or not */
+
+ struct wl_cnt *_cnt; /* low-level counters in driver */
+};
+
+/* wl_monitor rx status per packet */
+typedef struct wl_rxsts {
+ uint pkterror; /* error flags per pkt */
+ uint phytype; /* 802.11 A/B/G ... */
+ uint channel; /* channel */
+ uint datarate; /* rate in 500kbps */
+ uint antenna; /* antenna pkts received on */
+ uint pktlength; /* pkt length minus bcm phy hdr */
+ u32 mactime; /* time stamp from mac, count per 1us */
+ uint sq; /* signal quality */
+ s32 signal; /* in dbm */
+ s32 noise; /* in dbm */
+ uint preamble; /* Unknown, short, long */
+ uint encoding; /* Unknown, CCK, PBCC, OFDM */
+ uint nfrmtype; /* special 802.11n frames(AMPDU, AMSDU) */
+ struct brcms_if *wlif; /* wl interface */
+} wl_rxsts_t;
+
+/* status per error RX pkt */
+#define WL_RXS_CRC_ERROR 0x00000001 /* CRC Error in packet */
+#define WL_RXS_RUNT_ERROR 0x00000002 /* Runt packet */
+#define WL_RXS_ALIGN_ERROR 0x00000004 /* Misaligned packet */
+#define WL_RXS_OVERSIZE_ERROR 0x00000008 /* packet bigger than RX_LENGTH (usually 1518) */
+#define WL_RXS_WEP_ICV_ERROR 0x00000010 /* Integrity Check Value error */
+#define WL_RXS_WEP_ENCRYPTED 0x00000020 /* Encrypted with WEP */
+#define WL_RXS_PLCP_SHORT 0x00000040 /* Short PLCP error */
+#define WL_RXS_DECRYPT_ERR 0x00000080 /* Decryption error */
+#define WL_RXS_OTHER_ERR 0x80000000 /* Other errors */
+
+/* phy type */
+#define WL_RXS_PHY_A 0x00000000 /* A phy type */
+#define WL_RXS_PHY_B 0x00000001 /* B phy type */
+#define WL_RXS_PHY_G 0x00000002 /* G phy type */
+#define WL_RXS_PHY_N 0x00000004 /* N phy type */
+
+/* encoding */
+#define WL_RXS_ENCODING_CCK 0x00000000 /* CCK encoding */
+#define WL_RXS_ENCODING_OFDM 0x00000001 /* OFDM encoding */
+
+/* preamble */
+#define WL_RXS_UNUSED_STUB 0x0 /* stub to match with wlc_ethereal.h */
+#define WL_RXS_PREAMBLE_SHORT 0x00000001 /* Short preamble */
+#define WL_RXS_PREAMBLE_LONG 0x00000002 /* Long preamble */
+#define WL_RXS_PREAMBLE_MIMO_MM 0x00000003 /* MIMO mixed mode preamble */
+#define WL_RXS_PREAMBLE_MIMO_GF 0x00000004 /* MIMO green field preamble */
+
+#define WL_RXS_NFRM_AMPDU_FIRST 0x00000001 /* first MPDU in A-MPDU */
+#define WL_RXS_NFRM_AMPDU_SUB 0x00000002 /* subsequent MPDU(s) in A-MPDU */
+#define WL_RXS_NFRM_AMSDU_FIRST 0x00000004 /* first MSDU in A-MSDU */
+#define WL_RXS_NFRM_AMSDU_SUB 0x00000008 /* subsequent MSDU(s) in A-MSDU */
+
+enum wlc_par_id {
+ IOV_MPC = 1,
+ IOV_RTSTHRESH,
+ IOV_QTXPOWER,
+ IOV_BCN_LI_BCN /* Beacon listen interval in # of beacons */
+};
+
+/* forward declare and use the struct notation so we don't have to
+ * have it defined if not necessary.
+ */
+struct wlc_info;
+struct wlc_hw_info;
+struct wlc_bsscfg;
+struct wlc_if;
+
+/***********************************************
+ * Feature-related macros to optimize out code *
+ * *********************************************
+ */
+
+/* AP Support (versus STA) */
+#define AP_ENAB(pub) (0)
+
+/* Macro to check if APSTA mode enabled */
+#define APSTA_ENAB(pub) (0)
+
+/* Some useful combinations */
+#define STA_ONLY(pub) (!AP_ENAB(pub))
+#define AP_ONLY(pub) (AP_ENAB(pub) && !APSTA_ENAB(pub))
+
+#define ENAB_1x1 0x01
+#define ENAB_2x2 0x02
+#define ENAB_3x3 0x04
+#define ENAB_4x4 0x08
+#define SUPPORT_11N (ENAB_1x1|ENAB_2x2)
+#define SUPPORT_HT (ENAB_1x1|ENAB_2x2|ENAB_3x3)
+/* WL11N Support */
+#if ((defined(NCONF) && (NCONF != 0)) || (defined(LCNCONF) && (LCNCONF != 0)) || \
+ (defined(HTCONF) && (HTCONF != 0)) || (defined(SSLPNCONF) && (SSLPNCONF != 0)))
+#define N_ENAB(pub) ((pub)->_n_enab & SUPPORT_11N)
+#define N_REQD(pub) ((pub)->_n_reqd)
+#else
+#define N_ENAB(pub) 0
+#define N_REQD(pub) 0
+#endif
+
+#if (defined(HTCONF) && (HTCONF != 0))
+#define HT_ENAB(pub) (((pub)->_n_enab & SUPPORT_HT) == SUPPORT_HT)
+#else
+#define HT_ENAB(pub) 0
+#endif
+
+#define AMPDU_AGG_HOST 1
+#define AMPDU_ENAB(pub) ((pub)->_ampdu)
+
+#define EDCF_ENAB(pub) (WME_ENAB(pub))
+#define QOS_ENAB(pub) (WME_ENAB(pub) || N_ENAB(pub))
+
+#define MONITOR_ENAB(wlc) ((wlc)->monitor)
+
+#define PROMISC_ENAB(wlc) ((wlc)->promisc)
+
+#define WLC_PREC_COUNT 16 /* Max precedence level implemented */
+
+/* pri is priority encoded in the packet. This maps the Packet priority to
+ * enqueue precedence as defined in wlc_prec_map
+ */
+extern const u8 wlc_prio2prec_map[];
+#define WLC_PRIO_TO_PREC(pri) wlc_prio2prec_map[(pri) & 7]
+
+/* This maps priority to one precedence higher - Used by PS-Poll response packets to
+ * simulate enqueue-at-head operation, but still maintain the order on the queue
+ */
+#define WLC_PRIO_TO_HI_PREC(pri) min(WLC_PRIO_TO_PREC(pri) + 1, WLC_PREC_COUNT - 1)
+
+extern const u8 wme_fifo2ac[];
+#define WME_PRIO2AC(prio) wme_fifo2ac[prio2fifo[(prio)]]
+
+/* Mask to describe all precedence levels */
+#define WLC_PREC_BMP_ALL MAXBITVAL(WLC_PREC_COUNT)
+
+/* Define a bitmap of precedences comprised by each AC */
+#define WLC_PREC_BMP_AC_BE (NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_BE)) | \
+ NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_BE)) | \
+ NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_EE)) | \
+ NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_EE)))
+#define WLC_PREC_BMP_AC_BK (NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_BK)) | \
+ NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_BK)) | \
+ NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_NONE)) | \
+ NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_NONE)))
+#define WLC_PREC_BMP_AC_VI (NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_CL)) | \
+ NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_CL)) | \
+ NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_VI)) | \
+ NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_VI)))
+#define WLC_PREC_BMP_AC_VO (NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_VO)) | \
+ NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_VO)) | \
+ NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_NC)) | \
+ NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_NC)))
+
+/* WME Support */
+#define WME_ENAB(pub) ((pub)->_wme != OFF)
+#define WME_AUTO(wlc) ((wlc)->pub->_wme == AUTO)
+
+#define WLC_USE_COREFLAGS 0xffffffff /* invalid core flags, use the saved coreflags */
+
+
+/* network protection config */
+#define WLC_PROT_G_SPEC 1 /* SPEC g protection */
+#define WLC_PROT_G_OVR 2 /* SPEC g prot override */
+#define WLC_PROT_G_USER 3 /* gmode specified by user */
+#define WLC_PROT_OVERLAP 4 /* overlap */
+#define WLC_PROT_N_USER 10 /* nmode specified by user */
+#define WLC_PROT_N_CFG 11 /* n protection */
+#define WLC_PROT_N_CFG_OVR 12 /* n protection override */
+#define WLC_PROT_N_NONGF 13 /* non-GF protection */
+#define WLC_PROT_N_NONGF_OVR 14 /* non-GF protection override */
+#define WLC_PROT_N_PAM_OVR 15 /* n preamble override */
+#define WLC_PROT_N_OBSS 16 /* non-HT OBSS present */
+
+/*
+ * 54g modes (basic bits may still be overridden)
+ *
+ * GMODE_LEGACY_B Rateset: 1b, 2b, 5.5, 11
+ * Preamble: Long
+ * Shortslot: Off
+ * GMODE_AUTO Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
+ * Extended Rateset: 6, 9, 12, 48
+ * Preamble: Long
+ * Shortslot: Auto
+ * GMODE_ONLY Rateset: 1b, 2b, 5.5b, 11b, 18, 24b, 36, 54
+ * Extended Rateset: 6b, 9, 12b, 48
+ * Preamble: Short required
+ * Shortslot: Auto
+ * GMODE_B_DEFERRED Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
+ * Extended Rateset: 6, 9, 12, 48
+ * Preamble: Long
+ * Shortslot: On
+ * GMODE_PERFORMANCE Rateset: 1b, 2b, 5.5b, 6b, 9, 11b, 12b, 18, 24b, 36, 48, 54
+ * Preamble: Short required
+ * Shortslot: On and required
+ * GMODE_LRS Rateset: 1b, 2b, 5.5b, 11b
+ * Extended Rateset: 6, 9, 12, 18, 24, 36, 48, 54
+ * Preamble: Long
+ * Shortslot: Auto
+ */
+#define GMODE_LEGACY_B 0
+#define GMODE_AUTO 1
+#define GMODE_ONLY 2
+#define GMODE_B_DEFERRED 3
+#define GMODE_PERFORMANCE 4
+#define GMODE_LRS 5
+#define GMODE_MAX 6
+
+/* values for PLCPHdr_override */
+#define WLC_PLCP_AUTO -1
+#define WLC_PLCP_SHORT 0
+#define WLC_PLCP_LONG 1
+
+/* values for g_protection_override and n_protection_override */
+#define WLC_PROTECTION_AUTO -1
+#define WLC_PROTECTION_OFF 0
+#define WLC_PROTECTION_ON 1
+#define WLC_PROTECTION_MMHDR_ONLY 2
+#define WLC_PROTECTION_CTS_ONLY 3
+
+/* values for g_protection_control and n_protection_control */
+#define WLC_PROTECTION_CTL_OFF 0
+#define WLC_PROTECTION_CTL_LOCAL 1
+#define WLC_PROTECTION_CTL_OVERLAP 2
+
+/* values for n_protection */
+#define WLC_N_PROTECTION_OFF 0
+#define WLC_N_PROTECTION_OPTIONAL 1
+#define WLC_N_PROTECTION_20IN40 2
+#define WLC_N_PROTECTION_MIXEDMODE 3
+
+/* values for band specific 40MHz capabilities */
+#define WLC_N_BW_20ALL 0
+#define WLC_N_BW_40ALL 1
+#define WLC_N_BW_20IN2G_40IN5G 2
+
+/* bitflags for SGI support (sgi_rx iovar) */
+#define WLC_N_SGI_20 0x01
+#define WLC_N_SGI_40 0x02
+
+/* defines used by the nrate iovar */
+#define NRATE_MCS_INUSE 0x00000080 /* MSC in use,indicates b0-6 holds an mcs */
+#define NRATE_RATE_MASK 0x0000007f /* rate/mcs value */
+#define NRATE_STF_MASK 0x0000ff00 /* stf mode mask: siso, cdd, stbc, sdm */
+#define NRATE_STF_SHIFT 8 /* stf mode shift */
+#define NRATE_OVERRIDE 0x80000000 /* bit indicates override both rate & mode */
+#define NRATE_OVERRIDE_MCS_ONLY 0x40000000 /* bit indicate to override mcs only */
+#define NRATE_SGI_MASK 0x00800000 /* sgi mode */
+#define NRATE_SGI_SHIFT 23 /* sgi mode */
+#define NRATE_LDPC_CODING 0x00400000 /* bit indicates adv coding in use */
+#define NRATE_LDPC_SHIFT 22 /* ldpc shift */
+
+#define NRATE_STF_SISO 0 /* stf mode SISO */
+#define NRATE_STF_CDD 1 /* stf mode CDD */
+#define NRATE_STF_STBC 2 /* stf mode STBC */
+#define NRATE_STF_SDM 3 /* stf mode SDM */
+
+#define ANT_SELCFG_MAX 4 /* max number of antenna configurations */
+
+#define HIGHEST_SINGLE_STREAM_MCS 7 /* MCS values greater than this enable multiple streams */
+
+typedef struct {
+ u8 ant_config[ANT_SELCFG_MAX]; /* antenna configuration */
+ u8 num_antcfg; /* number of available antenna configurations */
+} wlc_antselcfg_t;
+
+/* common functions for every port */
+extern void *wlc_attach(struct brcms_info *wl, u16 vendor, u16 device,
+ uint unit, bool piomode, void *regsva, uint bustype,
+ void *btparam, uint *perr);
+extern uint wlc_detach(struct wlc_info *wlc);
+extern int wlc_up(struct wlc_info *wlc);
+extern uint wlc_down(struct wlc_info *wlc);
+
+extern int wlc_set(struct wlc_info *wlc, int cmd, int arg);
+extern int wlc_get(struct wlc_info *wlc, int cmd, int *arg);
+extern bool wlc_chipmatch(u16 vendor, u16 device);
+extern void wlc_init(struct wlc_info *wlc);
+extern void wlc_reset(struct wlc_info *wlc);
+
+extern void wlc_intrson(struct wlc_info *wlc);
+extern u32 wlc_intrsoff(struct wlc_info *wlc);
+extern void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask);
+extern bool wlc_intrsupd(struct wlc_info *wlc);
+extern bool wlc_isr(struct wlc_info *wlc, bool *wantdpc);
+extern bool wlc_dpc(struct wlc_info *wlc, bool bounded);
+extern bool wlc_sendpkt_mac80211(struct wlc_info *wlc, struct sk_buff *sdu,
+ struct ieee80211_hw *hw);
+extern int wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
+ struct wlc_if *wlcif);
+extern bool wlc_aggregatable(struct wlc_info *wlc, u8 tid);
+
+/* helper functions */
+extern void wlc_statsupd(struct wlc_info *wlc);
+extern void wlc_protection_upd(struct wlc_info *wlc, uint idx, int val);
+extern int wlc_get_header_len(void);
+extern void wlc_mac_bcn_promisc_change(struct wlc_info *wlc, bool promisc);
+extern void wlc_set_addrmatch(struct wlc_info *wlc, int match_reg_offset,
+ const u8 *addr);
+extern void wlc_wme_setparams(struct wlc_info *wlc, u16 aci,
+ const struct ieee80211_tx_queue_params *arg,
+ bool suspend);
+extern struct wlc_pub *wlc_pub(void *wlc);
+
+/* common functions for every port */
+extern void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val,
+ int bands);
+extern void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset);
+extern void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs);
+
+struct ieee80211_sta;
+extern void wlc_ampdu_flush(struct wlc_info *wlc, struct ieee80211_sta *sta,
+ u16 tid);
+extern int wlc_set_par(struct wlc_info *wlc, enum wlc_par_id par_id, int val);
+extern int wlc_get_par(struct wlc_info *wlc, enum wlc_par_id par_id, int *ret_int_ptr);
+extern char *getvar(char *vars, const char *name);
+extern int getintvar(char *vars, const char *name);
+
+/* wlc_phy.c helper functions */
+extern void wlc_set_ps_ctrl(struct wlc_info *wlc);
+extern void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val);
+
+extern int wlc_module_register(struct wlc_pub *pub,
+ const char *name, void *hdl,
+ watchdog_fn_t watchdog_fn, down_fn_t down_fn);
+extern int wlc_module_unregister(struct wlc_pub *pub, const char *name,
+ void *hdl);
+extern void wlc_suspend_mac_and_wait(struct wlc_info *wlc);
+extern void wlc_enable_mac(struct wlc_info *wlc);
+extern void wlc_associate_upd(struct wlc_info *wlc, bool state);
+extern void wlc_scan_start(struct wlc_info *wlc);
+extern void wlc_scan_stop(struct wlc_info *wlc);
+extern int wlc_get_curband(struct wlc_info *wlc);
+extern void wlc_wait_for_tx_completion(struct wlc_info *wlc, bool drop);
+
+/* helper functions */
+extern bool wlc_check_radio_disabled(struct wlc_info *wlc);
+extern bool wlc_radio_monitor_stop(struct wlc_info *wlc);
+
+#define MAXBANDS 2 /* Maximum #of bands */
+/* bandstate array indices */
+#define BAND_2G_INDEX 0 /* wlc->bandstate[x] index */
+#define BAND_5G_INDEX 1 /* wlc->bandstate[x] index */
+
+#define BAND_2G_NAME "2.4G"
+#define BAND_5G_NAME "5G"
+
+/* BMAC RPC: 7 u32 params: pkttotlen, fifo, commit, fid, txpktpend, pktflag, rpc_id */
+#define WLC_RPCTX_PARAMS 32
+
+#endif /* _BRCM_PUB_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <defs.h>
+#include <brcmu_utils.h>
+#include <aiutils.h>
+#include "dma.h"
+
+#include "types.h"
+#include "d11.h"
+#include "cfg.h"
+#include "scb.h"
+#include "pub.h"
+#include "rate.h"
+
+/* Rate info per rate: It tells whether a rate is ofdm or not and its phy_rate value */
+const u8 rate_info[WLC_MAXRATE + 1] = {
+ /* 0 1 2 3 4 5 6 7 8 9 */
+/* 0 */ 0x00, 0x00, 0x0a, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 10 */ 0x00, 0x37, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x00,
+/* 20 */ 0x00, 0x00, 0x6e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, 0x00, 0x00,
+/* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00,
+/* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 70 */ 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00,
+/* 100 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8c
+};
+
+/* rates are in units of Kbps */
+const mcs_info_t mcs_table[MCS_TABLE_SIZE] = {
+ /* MCS 0: SS 1, MOD: BPSK, CR 1/2 */
+ {6500, 13500, CEIL(6500 * 10, 9), CEIL(13500 * 10, 9), 0x00,
+ WLC_RATE_6M},
+ /* MCS 1: SS 1, MOD: QPSK, CR 1/2 */
+ {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x08,
+ WLC_RATE_12M},
+ /* MCS 2: SS 1, MOD: QPSK, CR 3/4 */
+ {19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x0A,
+ WLC_RATE_18M},
+ /* MCS 3: SS 1, MOD: 16QAM, CR 1/2 */
+ {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x10,
+ WLC_RATE_24M},
+ /* MCS 4: SS 1, MOD: 16QAM, CR 3/4 */
+ {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x12,
+ WLC_RATE_36M},
+ /* MCS 5: SS 1, MOD: 64QAM, CR 2/3 */
+ {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x19,
+ WLC_RATE_48M},
+ /* MCS 6: SS 1, MOD: 64QAM, CR 3/4 */
+ {58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x1A,
+ WLC_RATE_54M},
+ /* MCS 7: SS 1, MOD: 64QAM, CR 5/6 */
+ {65000, 135000, CEIL(65000 * 10, 9), CEIL(135000 * 10, 9), 0x1C,
+ WLC_RATE_54M},
+ /* MCS 8: SS 2, MOD: BPSK, CR 1/2 */
+ {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x40,
+ WLC_RATE_6M},
+ /* MCS 9: SS 2, MOD: QPSK, CR 1/2 */
+ {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x48,
+ WLC_RATE_12M},
+ /* MCS 10: SS 2, MOD: QPSK, CR 3/4 */
+ {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x4A,
+ WLC_RATE_18M},
+ /* MCS 11: SS 2, MOD: 16QAM, CR 1/2 */
+ {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x50,
+ WLC_RATE_24M},
+ /* MCS 12: SS 2, MOD: 16QAM, CR 3/4 */
+ {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0x52,
+ WLC_RATE_36M},
+ /* MCS 13: SS 2, MOD: 64QAM, CR 2/3 */
+ {104000, 216000, CEIL(104000 * 10, 9), CEIL(216000 * 10, 9), 0x59,
+ WLC_RATE_48M},
+ /* MCS 14: SS 2, MOD: 64QAM, CR 3/4 */
+ {117000, 243000, CEIL(117000 * 10, 9), CEIL(243000 * 10, 9), 0x5A,
+ WLC_RATE_54M},
+ /* MCS 15: SS 2, MOD: 64QAM, CR 5/6 */
+ {130000, 270000, CEIL(130000 * 10, 9), CEIL(270000 * 10, 9), 0x5C,
+ WLC_RATE_54M},
+ /* MCS 16: SS 3, MOD: BPSK, CR 1/2 */
+ {19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x80,
+ WLC_RATE_6M},
+ /* MCS 17: SS 3, MOD: QPSK, CR 1/2 */
+ {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x88,
+ WLC_RATE_12M},
+ /* MCS 18: SS 3, MOD: QPSK, CR 3/4 */
+ {58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x8A,
+ WLC_RATE_18M},
+ /* MCS 19: SS 3, MOD: 16QAM, CR 1/2 */
+ {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0x90,
+ WLC_RATE_24M},
+ /* MCS 20: SS 3, MOD: 16QAM, CR 3/4 */
+ {117000, 243000, CEIL(117000 * 10, 9), CEIL(243000 * 10, 9), 0x92,
+ WLC_RATE_36M},
+ /* MCS 21: SS 3, MOD: 64QAM, CR 2/3 */
+ {156000, 324000, CEIL(156000 * 10, 9), CEIL(324000 * 10, 9), 0x99,
+ WLC_RATE_48M},
+ /* MCS 22: SS 3, MOD: 64QAM, CR 3/4 */
+ {175500, 364500, CEIL(175500 * 10, 9), CEIL(364500 * 10, 9), 0x9A,
+ WLC_RATE_54M},
+ /* MCS 23: SS 3, MOD: 64QAM, CR 5/6 */
+ {195000, 405000, CEIL(195000 * 10, 9), CEIL(405000 * 10, 9), 0x9B,
+ WLC_RATE_54M},
+ /* MCS 24: SS 4, MOD: BPSK, CR 1/2 */
+ {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0xC0,
+ WLC_RATE_6M},
+ /* MCS 25: SS 4, MOD: QPSK, CR 1/2 */
+ {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0xC8,
+ WLC_RATE_12M},
+ /* MCS 26: SS 4, MOD: QPSK, CR 3/4 */
+ {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0xCA,
+ WLC_RATE_18M},
+ /* MCS 27: SS 4, MOD: 16QAM, CR 1/2 */
+ {104000, 216000, CEIL(104000 * 10, 9), CEIL(216000 * 10, 9), 0xD0,
+ WLC_RATE_24M},
+ /* MCS 28: SS 4, MOD: 16QAM, CR 3/4 */
+ {156000, 324000, CEIL(156000 * 10, 9), CEIL(324000 * 10, 9), 0xD2,
+ WLC_RATE_36M},
+ /* MCS 29: SS 4, MOD: 64QAM, CR 2/3 */
+ {208000, 432000, CEIL(208000 * 10, 9), CEIL(432000 * 10, 9), 0xD9,
+ WLC_RATE_48M},
+ /* MCS 30: SS 4, MOD: 64QAM, CR 3/4 */
+ {234000, 486000, CEIL(234000 * 10, 9), CEIL(486000 * 10, 9), 0xDA,
+ WLC_RATE_54M},
+ /* MCS 31: SS 4, MOD: 64QAM, CR 5/6 */
+ {260000, 540000, CEIL(260000 * 10, 9), CEIL(540000 * 10, 9), 0xDB,
+ WLC_RATE_54M},
+ /* MCS 32: SS 1, MOD: BPSK, CR 1/2 */
+ {0, 6000, 0, CEIL(6000 * 10, 9), 0x00, WLC_RATE_6M},
+};
+
+/* phycfg for legacy OFDM frames: code rate, modulation scheme, spatial streams
+ * Number of spatial streams: always 1
+ * other fields: refer to table 78 of section 17.3.2.2 of the original .11a standard
+ */
+typedef struct legacy_phycfg {
+ u32 rate_ofdm; /* ofdm mac rate */
+ u8 tx_phy_ctl3; /* phy ctl byte 3, code rate, modulation type, # of streams */
+} legacy_phycfg_t;
+
+#define LEGACY_PHYCFG_TABLE_SIZE 12 /* Number of legacy_rate_cfg entries in the table */
+
+/* In CCK mode LPPHY overloads OFDM Modulation bits with CCK Data Rate */
+/* Eventually MIMOPHY would also be converted to this format */
+/* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
+static const legacy_phycfg_t legacy_phycfg_table[LEGACY_PHYCFG_TABLE_SIZE] = {
+ {WLC_RATE_1M, 0x00}, /* CCK 1Mbps, data rate 0 */
+ {WLC_RATE_2M, 0x08}, /* CCK 2Mbps, data rate 1 */
+ {WLC_RATE_5M5, 0x10}, /* CCK 5.5Mbps, data rate 2 */
+ {WLC_RATE_11M, 0x18}, /* CCK 11Mbps, data rate 3 */
+ {WLC_RATE_6M, 0x00}, /* OFDM 6Mbps, code rate 1/2, BPSK, 1 spatial stream */
+ {WLC_RATE_9M, 0x02}, /* OFDM 9Mbps, code rate 3/4, BPSK, 1 spatial stream */
+ {WLC_RATE_12M, 0x08}, /* OFDM 12Mbps, code rate 1/2, QPSK, 1 spatial stream */
+ {WLC_RATE_18M, 0x0A}, /* OFDM 18Mbps, code rate 3/4, QPSK, 1 spatial stream */
+ {WLC_RATE_24M, 0x10}, /* OFDM 24Mbps, code rate 1/2, 16-QAM, 1 spatial stream */
+ {WLC_RATE_36M, 0x12}, /* OFDM 36Mbps, code rate 3/4, 16-QAM, 1 spatial stream */
+ {WLC_RATE_48M, 0x19}, /* OFDM 48Mbps, code rate 2/3, 64-QAM, 1 spatial stream */
+ {WLC_RATE_54M, 0x1A}, /* OFDM 54Mbps, code rate 3/4, 64-QAM, 1 spatial stream */
+};
+
+/* Hardware rates (also encodes default basic rates) */
+
+const wlc_rateset_t cck_ofdm_mimo_rates = {
+ 12,
+ { /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48, 54 Mbps */
+ 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
+ 0x6c},
+ 0x00,
+ {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+const wlc_rateset_t ofdm_mimo_rates = {
+ 8,
+ { /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
+ 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
+ 0x00,
+ {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+/* Default ratesets that include MCS32 for 40BW channels */
+const wlc_rateset_t cck_ofdm_40bw_mimo_rates = {
+ 12,
+ { /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48, 54 Mbps */
+ 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
+ 0x6c},
+ 0x00,
+ {0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+const wlc_rateset_t ofdm_40bw_mimo_rates = {
+ 8,
+ { /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
+ 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
+ 0x00,
+ {0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+const wlc_rateset_t cck_ofdm_rates = {
+ 12,
+ { /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48, 54 Mbps */
+ 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
+ 0x6c},
+ 0x00,
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+const wlc_rateset_t gphy_legacy_rates = {
+ 4,
+ { /* 1b, 2b, 5.5b, 11b Mbps */
+ 0x82, 0x84, 0x8b, 0x96},
+ 0x00,
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+const wlc_rateset_t ofdm_rates = {
+ 8,
+ { /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
+ 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
+ 0x00,
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+const wlc_rateset_t cck_rates = {
+ 4,
+ { /* 1b, 2b, 5.5, 11 Mbps */
+ 0x82, 0x84, 0x0b, 0x16},
+ 0x00,
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00}
+};
+
+static bool wlc_rateset_valid(wlc_rateset_t *rs, bool check_brate);
+
+/* check if rateset is valid.
+ * if check_brate is true, rateset without a basic rate is considered NOT valid.
+ */
+static bool wlc_rateset_valid(wlc_rateset_t *rs, bool check_brate)
+{
+ uint idx;
+
+ if (!rs->count)
+ return false;
+
+ if (!check_brate)
+ return true;
+
+ /* error if no basic rates */
+ for (idx = 0; idx < rs->count; idx++) {
+ if (rs->rates[idx] & WLC_RATE_FLAG)
+ return true;
+ }
+ return false;
+}
+
+void wlc_rateset_mcs_upd(wlc_rateset_t *rs, u8 txstreams)
+{
+ int i;
+ for (i = txstreams; i < MAX_STREAMS_SUPPORTED; i++)
+ rs->mcs[i] = 0;
+}
+
+/* filter based on hardware rateset, and sort filtered rateset with basic bit(s) preserved,
+ * and check if resulting rateset is valid.
+*/
+bool
+wlc_rate_hwrs_filter_sort_validate(wlc_rateset_t *rs,
+ const wlc_rateset_t *hw_rs,
+ bool check_brate, u8 txstreams)
+{
+ u8 rateset[WLC_MAXRATE + 1];
+ u8 r;
+ uint count;
+ uint i;
+
+ memset(rateset, 0, sizeof(rateset));
+ count = rs->count;
+
+ for (i = 0; i < count; i++) {
+ /* mask off "basic rate" bit, WLC_RATE_FLAG */
+ r = (int)rs->rates[i] & WLC_RATE_MASK;
+ if ((r > WLC_MAXRATE) || (rate_info[r] == 0)) {
+ continue;
+ }
+ rateset[r] = rs->rates[i]; /* preserve basic bit! */
+ }
+
+ /* fill out the rates in order, looking at only supported rates */
+ count = 0;
+ for (i = 0; i < hw_rs->count; i++) {
+ r = hw_rs->rates[i] & WLC_RATE_MASK;
+ if (rateset[r])
+ rs->rates[count++] = rateset[r];
+ }
+
+ rs->count = count;
+
+ /* only set the mcs rate bit if the equivalent hw mcs bit is set */
+ for (i = 0; i < MCSSET_LEN; i++)
+ rs->mcs[i] = (rs->mcs[i] & hw_rs->mcs[i]);
+
+ if (wlc_rateset_valid(rs, check_brate))
+ return true;
+ else
+ return false;
+}
+
+/* calculate the rate of a rx'd frame and return it as a ratespec */
+ratespec_t wlc_compute_rspec(d11rxhdr_t *rxh, u8 *plcp)
+{
+ int phy_type;
+ ratespec_t rspec = PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT;
+
+ phy_type =
+ ((rxh->RxChan & RXS_CHAN_PHYTYPE_MASK) >> RXS_CHAN_PHYTYPE_SHIFT);
+
+ if ((phy_type == PHY_TYPE_N) || (phy_type == PHY_TYPE_SSN) ||
+ (phy_type == PHY_TYPE_LCN) || (phy_type == PHY_TYPE_HT)) {
+ switch (rxh->PhyRxStatus_0 & PRXS0_FT_MASK) {
+ case PRXS0_CCK:
+ rspec =
+ CCK_PHY2MAC_RATE(((cck_phy_hdr_t *) plcp)->signal);
+ break;
+ case PRXS0_OFDM:
+ rspec =
+ OFDM_PHY2MAC_RATE(((ofdm_phy_hdr_t *) plcp)->
+ rlpt[0]);
+ break;
+ case PRXS0_PREN:
+ rspec = (plcp[0] & MIMO_PLCP_MCS_MASK) | RSPEC_MIMORATE;
+ if (plcp[0] & MIMO_PLCP_40MHZ) {
+ /* indicate rspec is for 40 MHz mode */
+ rspec &= ~RSPEC_BW_MASK;
+ rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
+ }
+ break;
+ case PRXS0_STDN:
+ /* fallthru */
+ default:
+ /* not supported, error condition */
+ break;
+ }
+ if (PLCP3_ISSGI(plcp[3]))
+ rspec |= RSPEC_SHORT_GI;
+ } else
+ if ((phy_type == PHY_TYPE_A) || (rxh->PhyRxStatus_0 & PRXS0_OFDM))
+ rspec = OFDM_PHY2MAC_RATE(((ofdm_phy_hdr_t *) plcp)->rlpt[0]);
+ else
+ rspec = CCK_PHY2MAC_RATE(((cck_phy_hdr_t *) plcp)->signal);
+
+ return rspec;
+}
+
+/* copy rateset src to dst as-is (no masking or sorting) */
+void wlc_rateset_copy(const wlc_rateset_t *src, wlc_rateset_t *dst)
+{
+ memcpy(dst, src, sizeof(wlc_rateset_t));
+}
+
+/*
+ * Copy and selectively filter one rateset to another.
+ * 'basic_only' means only copy basic rates.
+ * 'rates' indicates cck (11b) and ofdm rates combinations.
+ * - 0: cck and ofdm
+ * - 1: cck only
+ * - 2: ofdm only
+ * 'xmask' is the copy mask (typically 0x7f or 0xff).
+ */
+void
+wlc_rateset_filter(wlc_rateset_t *src, wlc_rateset_t *dst, bool basic_only,
+ u8 rates, uint xmask, bool mcsallow)
+{
+ uint i;
+ uint r;
+ uint count;
+
+ count = 0;
+ for (i = 0; i < src->count; i++) {
+ r = src->rates[i];
+ if (basic_only && !(r & WLC_RATE_FLAG))
+ continue;
+ if ((rates == WLC_RATES_CCK) && IS_OFDM((r & WLC_RATE_MASK)))
+ continue;
+ if ((rates == WLC_RATES_OFDM) && IS_CCK((r & WLC_RATE_MASK)))
+ continue;
+ dst->rates[count++] = r & xmask;
+ }
+ dst->count = count;
+ dst->htphy_membership = src->htphy_membership;
+
+ if (mcsallow && rates != WLC_RATES_CCK)
+ memcpy(&dst->mcs[0], &src->mcs[0], MCSSET_LEN);
+ else
+ wlc_rateset_mcs_clear(dst);
+}
+
+/* select rateset for a given phy_type and bandtype and filter it, sort it
+ * and fill rs_tgt with result
+ */
+void
+wlc_rateset_default(wlc_rateset_t *rs_tgt, const wlc_rateset_t *rs_hw,
+ uint phy_type, int bandtype, bool cck_only, uint rate_mask,
+ bool mcsallow, u8 bw, u8 txstreams)
+{
+ const wlc_rateset_t *rs_dflt;
+ wlc_rateset_t rs_sel;
+ if ((PHYTYPE_IS(phy_type, PHY_TYPE_HT)) ||
+ (PHYTYPE_IS(phy_type, PHY_TYPE_N)) ||
+ (PHYTYPE_IS(phy_type, PHY_TYPE_LCN)) ||
+ (PHYTYPE_IS(phy_type, PHY_TYPE_SSN))) {
+ if (BAND_5G(bandtype)) {
+ rs_dflt = (bw == WLC_20_MHZ ?
+ &ofdm_mimo_rates : &ofdm_40bw_mimo_rates);
+ } else {
+ rs_dflt = (bw == WLC_20_MHZ ?
+ &cck_ofdm_mimo_rates :
+ &cck_ofdm_40bw_mimo_rates);
+ }
+ } else if (PHYTYPE_IS(phy_type, PHY_TYPE_LP)) {
+ rs_dflt = (BAND_5G(bandtype)) ? &ofdm_rates : &cck_ofdm_rates;
+ } else if (PHYTYPE_IS(phy_type, PHY_TYPE_A)) {
+ rs_dflt = &ofdm_rates;
+ } else if (PHYTYPE_IS(phy_type, PHY_TYPE_G)) {
+ rs_dflt = &cck_ofdm_rates;
+ } else {
+ /* should not happen, error condition */
+ rs_dflt = &cck_rates; /* force cck */
+ }
+
+ /* if hw rateset is not supplied, assign selected rateset to it */
+ if (!rs_hw)
+ rs_hw = rs_dflt;
+
+ wlc_rateset_copy(rs_dflt, &rs_sel);
+ wlc_rateset_mcs_upd(&rs_sel, txstreams);
+ wlc_rateset_filter(&rs_sel, rs_tgt, false,
+ cck_only ? WLC_RATES_CCK : WLC_RATES_CCK_OFDM,
+ rate_mask, mcsallow);
+ wlc_rate_hwrs_filter_sort_validate(rs_tgt, rs_hw, false,
+ mcsallow ? txstreams : 1);
+}
+
+s16 wlc_rate_legacy_phyctl(uint rate)
+{
+ uint i;
+ for (i = 0; i < LEGACY_PHYCFG_TABLE_SIZE; i++)
+ if (rate == legacy_phycfg_table[i].rate_ofdm)
+ return legacy_phycfg_table[i].tx_phy_ctl3;
+
+ return -1;
+}
+
+void wlc_rateset_mcs_clear(wlc_rateset_t *rateset)
+{
+ uint i;
+ for (i = 0; i < MCSSET_LEN; i++)
+ rateset->mcs[i] = 0;
+}
+
+void wlc_rateset_mcs_build(wlc_rateset_t *rateset, u8 txstreams)
+{
+ memcpy(&rateset->mcs[0], &cck_ofdm_mimo_rates.mcs[0], MCSSET_LEN);
+ wlc_rateset_mcs_upd(rateset, txstreams);
+}
+
+/* Based on bandwidth passed, allow/disallow MCS 32 in the rateset */
+void wlc_rateset_bw_mcs_filter(wlc_rateset_t *rateset, u8 bw)
+{
+ if (bw == WLC_40_MHZ)
+ setbit(rateset->mcs, 32);
+ else
+ clrbit(rateset->mcs, 32);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _WLC_RATE_H_
+#define _WLC_RATE_H_
+
+extern const u8 rate_info[];
+extern const struct wlc_rateset cck_ofdm_mimo_rates;
+extern const struct wlc_rateset ofdm_mimo_rates;
+extern const struct wlc_rateset cck_ofdm_rates;
+extern const struct wlc_rateset ofdm_rates;
+extern const struct wlc_rateset cck_rates;
+extern const struct wlc_rateset gphy_legacy_rates;
+extern const struct wlc_rateset wlc_lrs_rates;
+extern const struct wlc_rateset rate_limit_1_2;
+
+typedef struct mcs_info {
+ u32 phy_rate_20; /* phy rate in kbps [20Mhz] */
+ u32 phy_rate_40; /* phy rate in kbps [40Mhz] */
+ u32 phy_rate_20_sgi; /* phy rate in kbps [20Mhz] with SGI */
+ u32 phy_rate_40_sgi; /* phy rate in kbps [40Mhz] with SGI */
+ u8 tx_phy_ctl3; /* phy ctl byte 3, code rate, modulation type, # of streams */
+ u8 leg_ofdm; /* matching legacy ofdm rate in 500bkps */
+} mcs_info_t;
+
+#define WLC_MAXMCS 32 /* max valid mcs index */
+#define MCS_TABLE_SIZE 33 /* Number of mcs entries in the table */
+extern const mcs_info_t mcs_table[];
+
+#define MCS_INVALID 0xFF
+#define MCS_CR_MASK 0x07 /* Code Rate bit mask */
+#define MCS_MOD_MASK 0x38 /* Modulation bit shift */
+#define MCS_MOD_SHIFT 3 /* MOdulation bit shift */
+#define MCS_TXS_MASK 0xc0 /* num tx streams - 1 bit mask */
+#define MCS_TXS_SHIFT 6 /* num tx streams - 1 bit shift */
+#define MCS_CR(_mcs) (mcs_table[_mcs].tx_phy_ctl3 & MCS_CR_MASK)
+#define MCS_MOD(_mcs) ((mcs_table[_mcs].tx_phy_ctl3 & MCS_MOD_MASK) >> MCS_MOD_SHIFT)
+#define MCS_TXS(_mcs) ((mcs_table[_mcs].tx_phy_ctl3 & MCS_TXS_MASK) >> MCS_TXS_SHIFT)
+#define MCS_RATE(_mcs, _is40, _sgi) (_sgi ? \
+ (_is40 ? mcs_table[_mcs].phy_rate_40_sgi : mcs_table[_mcs].phy_rate_20_sgi) : \
+ (_is40 ? mcs_table[_mcs].phy_rate_40 : mcs_table[_mcs].phy_rate_20))
+#define VALID_MCS(_mcs) ((_mcs < MCS_TABLE_SIZE))
+
+/* Macro to use the rate_info table */
+#define WLC_RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */
+
+#define WLC_RATE_500K_TO_BPS(rate) ((rate) * 500000) /* convert 500kbps to bps */
+
+/* rate spec : holds rate and mode specific information required to generate a tx frame. */
+/* Legacy CCK and OFDM information is held in the same manner as was done in the past */
+/* (in the lower byte) the upper 3 bytes primarily hold MIMO specific information */
+typedef u32 ratespec_t;
+
+/* rate spec bit fields */
+#define RSPEC_RATE_MASK 0x0000007F /* Either 500Kbps units or MIMO MCS idx */
+#define RSPEC_MIMORATE 0x08000000 /* mimo MCS is stored in RSPEC_RATE_MASK */
+#define RSPEC_BW_MASK 0x00000700 /* mimo bw mask */
+#define RSPEC_BW_SHIFT 8 /* mimo bw shift */
+#define RSPEC_STF_MASK 0x00003800 /* mimo Space/Time/Frequency mode mask */
+#define RSPEC_STF_SHIFT 11 /* mimo Space/Time/Frequency mode shift */
+#define RSPEC_CT_MASK 0x0000C000 /* mimo coding type mask */
+#define RSPEC_CT_SHIFT 14 /* mimo coding type shift */
+#define RSPEC_STC_MASK 0x00300000 /* mimo num STC streams per PLCP defn. */
+#define RSPEC_STC_SHIFT 20 /* mimo num STC streams per PLCP defn. */
+#define RSPEC_LDPC_CODING 0x00400000 /* mimo bit indicates adv coding in use */
+#define RSPEC_SHORT_GI 0x00800000 /* mimo bit indicates short GI in use */
+#define RSPEC_OVERRIDE 0x80000000 /* bit indicates override both rate & mode */
+#define RSPEC_OVERRIDE_MCS_ONLY 0x40000000 /* bit indicates override rate only */
+
+#define WLC_HTPHY 127 /* HT PHY Membership */
+
+#define RSPEC_ACTIVE(rspec) (rspec & (RSPEC_RATE_MASK | RSPEC_MIMORATE))
+#define RSPEC2RATE(rspec) ((rspec & RSPEC_MIMORATE) ? \
+ MCS_RATE((rspec & RSPEC_RATE_MASK), RSPEC_IS40MHZ(rspec), RSPEC_ISSGI(rspec)) : \
+ (rspec & RSPEC_RATE_MASK))
+/* return rate in unit of 500Kbps -- for internal use in wlc_rate_sel.c */
+#define RSPEC2RATE500K(rspec) ((rspec & RSPEC_MIMORATE) ? \
+ MCS_RATE((rspec & RSPEC_RATE_MASK), state->is40bw, RSPEC_ISSGI(rspec))/500 : \
+ (rspec & RSPEC_RATE_MASK))
+#define CRSPEC2RATE500K(rspec) ((rspec & RSPEC_MIMORATE) ? \
+ MCS_RATE((rspec & RSPEC_RATE_MASK), RSPEC_IS40MHZ(rspec), RSPEC_ISSGI(rspec))/500 :\
+ (rspec & RSPEC_RATE_MASK))
+
+#define RSPEC2KBPS(rspec) (IS_MCS(rspec) ? RSPEC2RATE(rspec) : RSPEC2RATE(rspec)*500)
+#define RSPEC_PHYTXBYTE2(rspec) ((rspec & 0xff00) >> 8)
+#define RSPEC_GET_BW(rspec) ((rspec & RSPEC_BW_MASK) >> RSPEC_BW_SHIFT)
+#define RSPEC_IS40MHZ(rspec) ((((rspec & RSPEC_BW_MASK) >> RSPEC_BW_SHIFT) == \
+ PHY_TXC1_BW_40MHZ) || (((rspec & RSPEC_BW_MASK) >> \
+ RSPEC_BW_SHIFT) == PHY_TXC1_BW_40MHZ_DUP))
+#define RSPEC_ISSGI(rspec) ((rspec & RSPEC_SHORT_GI) == RSPEC_SHORT_GI)
+#define RSPEC_MIMOPLCP3(rspec) ((rspec & 0xf00000) >> 16)
+#define PLCP3_ISSGI(plcp) (plcp & (RSPEC_SHORT_GI >> 16))
+#define RSPEC_STC(rspec) ((rspec & RSPEC_STC_MASK) >> RSPEC_STC_SHIFT)
+#define RSPEC_STF(rspec) ((rspec & RSPEC_STF_MASK) >> RSPEC_STF_SHIFT)
+#define PLCP3_ISSTBC(plcp) ((plcp & (RSPEC_STC_MASK) >> 16) == 0x10)
+#define PLCP3_STC_MASK 0x30
+#define PLCP3_STC_SHIFT 4
+
+/* Rate info table; takes a legacy rate or ratespec_t */
+#define IS_MCS(r) (r & RSPEC_MIMORATE)
+#define IS_OFDM(r) (!IS_MCS(r) && (rate_info[(r) & RSPEC_RATE_MASK] & WLC_RATE_FLAG))
+#define IS_CCK(r) (!IS_MCS(r) && ( \
+ ((r) & WLC_RATE_MASK) == WLC_RATE_1M || \
+ ((r) & WLC_RATE_MASK) == WLC_RATE_2M || \
+ ((r) & WLC_RATE_MASK) == WLC_RATE_5M5 || \
+ ((r) & WLC_RATE_MASK) == WLC_RATE_11M))
+#define IS_SINGLE_STREAM(mcs) (((mcs) <= HIGHEST_SINGLE_STREAM_MCS) || ((mcs) == 32))
+#define CCK_RSPEC(cck) ((cck) & RSPEC_RATE_MASK)
+#define OFDM_RSPEC(ofdm) (((ofdm) & RSPEC_RATE_MASK) |\
+ (PHY_TXC1_MODE_CDD << RSPEC_STF_SHIFT))
+#define LEGACY_RSPEC(rate) (IS_CCK(rate) ? CCK_RSPEC(rate) : OFDM_RSPEC(rate))
+
+#define MCS_RSPEC(mcs) (((mcs) & RSPEC_RATE_MASK) | RSPEC_MIMORATE | \
+ (IS_SINGLE_STREAM(mcs) ? (PHY_TXC1_MODE_CDD << RSPEC_STF_SHIFT) : \
+ (PHY_TXC1_MODE_SDM << RSPEC_STF_SHIFT)))
+
+/* Convert encoded rate value in plcp header to numerical rates in 500 KHz increments */
+extern const u8 ofdm_rate_lookup[];
+#define OFDM_PHY2MAC_RATE(rlpt) (ofdm_rate_lookup[rlpt & 0x7])
+#define CCK_PHY2MAC_RATE(signal) (signal/5)
+
+/* Rates specified in wlc_rateset_filter() */
+#define WLC_RATES_CCK_OFDM 0
+#define WLC_RATES_CCK 1
+#define WLC_RATES_OFDM 2
+
+/* use the stuct form instead of typedef to fix dependency problems */
+struct wlc_rateset;
+
+/* sanitize, and sort a rateset with the basic bit(s) preserved, validate rateset */
+extern bool wlc_rate_hwrs_filter_sort_validate(struct wlc_rateset *rs,
+ const struct wlc_rateset *hw_rs,
+ bool check_brate,
+ u8 txstreams);
+/* copy rateset src to dst as-is (no masking or sorting) */
+extern void wlc_rateset_copy(const struct wlc_rateset *src,
+ struct wlc_rateset *dst);
+
+/* would be nice to have these documented ... */
+extern ratespec_t wlc_compute_rspec(d11rxhdr_t *rxh, u8 *plcp);
+
+extern void wlc_rateset_filter(struct wlc_rateset *src, struct wlc_rateset *dst,
+ bool basic_only, u8 rates, uint xmask,
+ bool mcsallow);
+extern void wlc_rateset_default(struct wlc_rateset *rs_tgt,
+ const struct wlc_rateset *rs_hw, uint phy_type,
+ int bandtype, bool cck_only, uint rate_mask,
+ bool mcsallow, u8 bw, u8 txstreams);
+extern s16 wlc_rate_legacy_phyctl(uint rate);
+
+extern void wlc_rateset_mcs_upd(struct wlc_rateset *rs, u8 txstreams);
+extern void wlc_rateset_mcs_clear(struct wlc_rateset *rateset);
+extern void wlc_rateset_mcs_build(struct wlc_rateset *rateset, u8 txstreams);
+extern void wlc_rateset_bw_mcs_filter(struct wlc_rateset *rateset, u8 bw);
+
+#endif /* _WLC_RATE_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_SCB_H_
+#define _BRCM_SCB_H_
+
+#include <linux/if_ether.h> /* for ETH_ALEN */
+
+#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
+/* structure to store per-tid state for the ampdu initiator */
+typedef struct scb_ampdu_tid_ini {
+ u32 magic;
+ u8 tx_in_transit; /* number of pending mpdus in transit in driver */
+ u8 tid; /* initiator tid for easy lookup */
+ u8 txretry[AMPDU_TX_BA_MAX_WSIZE]; /* tx retry count; indexed by seq modulo */
+ struct scb *scb; /* backptr for easy lookup */
+} scb_ampdu_tid_ini_t;
+
+#define AMPDU_MAX_SCB_TID NUMPRIO
+
+typedef struct scb_ampdu {
+ struct scb *scb; /* back pointer for easy reference */
+ u8 mpdu_density; /* mpdu density */
+ u8 max_pdu; /* max pdus allowed in ampdu */
+ u8 release; /* # of mpdus released at a time */
+ u16 min_len; /* min mpdu len to support the density */
+ u32 max_rxlen; /* max ampdu rcv length; 8k, 16k, 32k, 64k */
+ struct pktq txq; /* sdu transmit queue pending aggregation */
+
+ /* This could easily be a ini[] pointer and we keep this info in wl itself instead
+ * of having mac80211 hold it for us. Also could be made dynamic per tid instead of
+ * static.
+ */
+ scb_ampdu_tid_ini_t ini[AMPDU_MAX_SCB_TID]; /* initiator info - per tid (NUMPRIO) */
+} scb_ampdu_t;
+
+#define SCB_MAGIC 0xbeefcafe
+#define INI_MAGIC 0xabcd1234
+
+/* station control block - one per remote MAC address */
+struct scb {
+ u32 magic;
+ u32 flags; /* various bit flags as defined below */
+ u32 flags2; /* various bit flags2 as defined below */
+ u8 state; /* current state bitfield of auth/assoc process */
+ u8 ea[ETH_ALEN]; /* station address */
+ void *fragbuf[NUMPRIO]; /* defragmentation buffer per prio */
+ uint fragresid[NUMPRIO]; /* #bytes unused in frag buffer per prio */
+
+ u16 seqctl[NUMPRIO]; /* seqctl of last received frame (for dups) */
+ u16 seqctl_nonqos; /* seqctl of last received frame (for dups) for
+ * non-QoS data and management
+ */
+ u16 seqnum[NUMPRIO]; /* WME: driver maintained sw seqnum per priority */
+
+ scb_ampdu_t scb_ampdu; /* AMPDU state including per tid info */
+};
+
+/* scb flags */
+#define SCB_WMECAP 0x0040 /* may ONLY be set if WME_ENAB(wlc) */
+#define SCB_HTCAP 0x10000 /* HT (MIMO) capable device */
+#define SCB_IS40 0x80000 /* 40MHz capable */
+#define SCB_STBCCAP 0x40000000 /* STBC Capable */
+#define SCB_WME(a) ((a)->flags & SCB_WMECAP)/* implies WME_ENAB */
+#define SCB_SEQNUM(scb, prio) ((scb)->seqnum[(prio)])
+#define SCB_PS(a) NULL
+#define SCB_STBC_CAP(a) ((a)->flags & SCB_STBCCAP)
+#define SCB_AMPDU(a) true
+#endif /* _BRCM_SCB_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/etherdevice.h>
+#include <defs.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <stdarg.h>
+#include "types.h"
+#include <brcmu_utils.h>
+#include <soc.h>
+#include <chipcommon.h>
+#include <brcm_hw_ids.h>
+#include <nicpci.h>
+#include <aiutils.h>
+#include <srom.h>
+#include "otp.h"
+
+#define SROM_OFFSET(sih) ((sih->ccrev > 31) ? \
+ (((sih->cccaps & CC_CAP_SROM) == 0) ? NULL : \
+ ((u8 *)curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP)) : \
+ ((u8 *)curmap + PCI_BAR0_SPROM_OFFSET))
+
+#if defined(BCMDBG)
+#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
+#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
+#endif
+
+/* Maximum srom: 6 Kilobits == 768 bytes */
+#define SROM_MAX 768
+
+/* PCI fields */
+#define PCI_F0DEVID 48
+
+#define SROM_WORDS 64
+
+#define SROM_SSID 2
+
+#define SROM_WL1LHMAXP 29
+
+#define SROM_WL1LPAB0 30
+#define SROM_WL1LPAB1 31
+#define SROM_WL1LPAB2 32
+
+#define SROM_WL1HPAB0 33
+#define SROM_WL1HPAB1 34
+#define SROM_WL1HPAB2 35
+
+#define SROM_MACHI_IL0 36
+#define SROM_MACMID_IL0 37
+#define SROM_MACLO_IL0 38
+#define SROM_MACHI_ET1 42
+#define SROM_MACMID_ET1 43
+#define SROM_MACLO_ET1 44
+#define SROM3_MACHI 37
+#define SROM3_MACMID 38
+#define SROM3_MACLO 39
+
+#define SROM_BXARSSI2G 40
+#define SROM_BXARSSI5G 41
+
+#define SROM_TRI52G 42
+#define SROM_TRI5GHL 43
+
+#define SROM_RXPO52G 45
+
+#define SROM_AABREV 46
+/* Fields in AABREV */
+#define SROM_BR_MASK 0x00ff
+#define SROM_CC_MASK 0x0f00
+#define SROM_CC_SHIFT 8
+#define SROM_AA0_MASK 0x3000
+#define SROM_AA0_SHIFT 12
+#define SROM_AA1_MASK 0xc000
+#define SROM_AA1_SHIFT 14
+
+#define SROM_WL0PAB0 47
+#define SROM_WL0PAB1 48
+#define SROM_WL0PAB2 49
+
+#define SROM_LEDBH10 50
+#define SROM_LEDBH32 51
+
+#define SROM_WL10MAXP 52
+
+#define SROM_WL1PAB0 53
+#define SROM_WL1PAB1 54
+#define SROM_WL1PAB2 55
+
+#define SROM_ITT 56
+
+#define SROM_BFL 57
+#define SROM_BFL2 28
+#define SROM3_BFL2 61
+
+#define SROM_AG10 58
+
+#define SROM_CCODE 59
+
+#define SROM_OPO 60
+
+#define SROM3_LEDDC 62
+
+#define SROM_CRCREV 63
+
+/* SROM Rev 4: Reallocate the software part of the srom to accommodate
+ * MIMO features. It assumes up to two PCIE functions and 440 bytes
+ * of usable srom i.e. the usable storage in chips with OTP that
+ * implements hardware redundancy.
+ */
+
+#define SROM4_WORDS 220
+
+#define SROM4_SIGN 32
+#define SROM4_SIGNATURE 0x5372
+
+#define SROM4_BREV 33
+
+#define SROM4_BFL0 34
+#define SROM4_BFL1 35
+#define SROM4_BFL2 36
+#define SROM4_BFL3 37
+#define SROM5_BFL0 37
+#define SROM5_BFL1 38
+#define SROM5_BFL2 39
+#define SROM5_BFL3 40
+
+#define SROM4_MACHI 38
+#define SROM4_MACMID 39
+#define SROM4_MACLO 40
+#define SROM5_MACHI 41
+#define SROM5_MACMID 42
+#define SROM5_MACLO 43
+
+#define SROM4_CCODE 41
+#define SROM4_REGREV 42
+#define SROM5_CCODE 34
+#define SROM5_REGREV 35
+
+#define SROM4_LEDBH10 43
+#define SROM4_LEDBH32 44
+#define SROM5_LEDBH10 59
+#define SROM5_LEDBH32 60
+
+#define SROM4_LEDDC 45
+#define SROM5_LEDDC 45
+
+#define SROM4_AA 46
+
+#define SROM4_AG10 47
+#define SROM4_AG32 48
+
+#define SROM4_TXPID2G 49
+#define SROM4_TXPID5G 51
+#define SROM4_TXPID5GL 53
+#define SROM4_TXPID5GH 55
+
+#define SROM4_TXRXC 61
+#define SROM4_TXCHAIN_MASK 0x000f
+#define SROM4_TXCHAIN_SHIFT 0
+#define SROM4_RXCHAIN_MASK 0x00f0
+#define SROM4_RXCHAIN_SHIFT 4
+#define SROM4_SWITCH_MASK 0xff00
+#define SROM4_SWITCH_SHIFT 8
+
+/* Per-path fields */
+#define MAX_PATH_SROM 4
+#define SROM4_PATH0 64
+#define SROM4_PATH1 87
+#define SROM4_PATH2 110
+#define SROM4_PATH3 133
+
+#define SROM4_2G_ITT_MAXP 0
+#define SROM4_2G_PA 1
+#define SROM4_5G_ITT_MAXP 5
+#define SROM4_5GLH_MAXP 6
+#define SROM4_5G_PA 7
+#define SROM4_5GL_PA 11
+#define SROM4_5GH_PA 15
+
+/* All the miriad power offsets */
+#define SROM4_2G_CCKPO 156
+#define SROM4_2G_OFDMPO 157
+#define SROM4_5G_OFDMPO 159
+#define SROM4_5GL_OFDMPO 161
+#define SROM4_5GH_OFDMPO 163
+#define SROM4_2G_MCSPO 165
+#define SROM4_5G_MCSPO 173
+#define SROM4_5GL_MCSPO 181
+#define SROM4_5GH_MCSPO 189
+#define SROM4_CDDPO 197
+#define SROM4_STBCPO 198
+#define SROM4_BW40PO 199
+#define SROM4_BWDUPPO 200
+
+#define SROM4_CRCREV 219
+
+/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
+ * This is acombined srom for both MIMO and SISO boards, usable in
+ * the .130 4Kilobit OTP with hardware redundancy.
+ */
+#define SROM8_BREV 65
+
+#define SROM8_BFL0 66
+#define SROM8_BFL1 67
+#define SROM8_BFL2 68
+#define SROM8_BFL3 69
+
+#define SROM8_MACHI 70
+#define SROM8_MACMID 71
+#define SROM8_MACLO 72
+
+#define SROM8_CCODE 73
+#define SROM8_REGREV 74
+
+#define SROM8_LEDBH10 75
+#define SROM8_LEDBH32 76
+
+#define SROM8_LEDDC 77
+
+#define SROM8_AA 78
+
+#define SROM8_AG10 79
+#define SROM8_AG32 80
+
+#define SROM8_TXRXC 81
+
+#define SROM8_BXARSSI2G 82
+#define SROM8_BXARSSI5G 83
+#define SROM8_TRI52G 84
+#define SROM8_TRI5GHL 85
+#define SROM8_RXPO52G 86
+
+#define SROM8_FEM2G 87
+#define SROM8_FEM5G 88
+#define SROM8_FEM_ANTSWLUT_MASK 0xf800
+#define SROM8_FEM_ANTSWLUT_SHIFT 11
+#define SROM8_FEM_TR_ISO_MASK 0x0700
+#define SROM8_FEM_TR_ISO_SHIFT 8
+#define SROM8_FEM_PDET_RANGE_MASK 0x00f8
+#define SROM8_FEM_PDET_RANGE_SHIFT 3
+#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
+#define SROM8_FEM_EXTPA_GAIN_SHIFT 1
+#define SROM8_FEM_TSSIPOS_MASK 0x0001
+#define SROM8_FEM_TSSIPOS_SHIFT 0
+
+#define SROM8_THERMAL 89
+
+/* Temp sense related entries */
+#define SROM8_MPWR_RAWTS 90
+#define SROM8_TS_SLP_OPT_CORRX 91
+/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
+#define SROM8_FOC_HWIQ_IQSWP 92
+
+/* Temperature delta for PHY calibration */
+#define SROM8_PHYCAL_TEMPDELTA 93
+
+/* Per-path offsets & fields */
+#define SROM8_PATH0 96
+#define SROM8_PATH1 112
+#define SROM8_PATH2 128
+#define SROM8_PATH3 144
+
+#define SROM8_2G_ITT_MAXP 0
+#define SROM8_2G_PA 1
+#define SROM8_5G_ITT_MAXP 4
+#define SROM8_5GLH_MAXP 5
+#define SROM8_5G_PA 6
+#define SROM8_5GL_PA 9
+#define SROM8_5GH_PA 12
+
+/* All the miriad power offsets */
+#define SROM8_2G_CCKPO 160
+
+#define SROM8_2G_OFDMPO 161
+#define SROM8_5G_OFDMPO 163
+#define SROM8_5GL_OFDMPO 165
+#define SROM8_5GH_OFDMPO 167
+
+#define SROM8_2G_MCSPO 169
+#define SROM8_5G_MCSPO 177
+#define SROM8_5GL_MCSPO 185
+#define SROM8_5GH_MCSPO 193
+
+#define SROM8_CDDPO 201
+#define SROM8_STBCPO 202
+#define SROM8_BW40PO 203
+#define SROM8_BWDUPPO 204
+
+/* SISO PA parameters are in the path0 spaces */
+#define SROM8_SISO 96
+
+/* Legacy names for SISO PA paramters */
+#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
+#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
+#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
+#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
+#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
+#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
+#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
+#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
+#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
+#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
+#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
+#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
+#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
+#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
+#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
+
+/* SROM REV 9 */
+#define SROM9_2GPO_CCKBW20 160
+#define SROM9_2GPO_CCKBW20UL 161
+#define SROM9_2GPO_LOFDMBW20 162
+#define SROM9_2GPO_LOFDMBW20UL 164
+
+#define SROM9_5GLPO_LOFDMBW20 166
+#define SROM9_5GLPO_LOFDMBW20UL 168
+#define SROM9_5GMPO_LOFDMBW20 170
+#define SROM9_5GMPO_LOFDMBW20UL 172
+#define SROM9_5GHPO_LOFDMBW20 174
+#define SROM9_5GHPO_LOFDMBW20UL 176
+
+#define SROM9_2GPO_MCSBW20 178
+#define SROM9_2GPO_MCSBW20UL 180
+#define SROM9_2GPO_MCSBW40 182
+
+#define SROM9_5GLPO_MCSBW20 184
+#define SROM9_5GLPO_MCSBW20UL 186
+#define SROM9_5GLPO_MCSBW40 188
+#define SROM9_5GMPO_MCSBW20 190
+#define SROM9_5GMPO_MCSBW20UL 192
+#define SROM9_5GMPO_MCSBW40 194
+#define SROM9_5GHPO_MCSBW20 196
+#define SROM9_5GHPO_MCSBW20UL 198
+#define SROM9_5GHPO_MCSBW40 200
+
+#define SROM9_PO_MCS32 202
+#define SROM9_PO_LOFDM40DUP 203
+
+/* SROM flags (see sromvar_t) */
+#define SRFL_MORE 1 /* value continues as described by the next entry */
+#define SRFL_NOFFS 2 /* value bits can't be all one's */
+#define SRFL_PRHEX 4 /* value is in hexdecimal format */
+#define SRFL_PRSIGN 8 /* value is in signed decimal format */
+#define SRFL_CCODE 0x10 /* value is in country code format */
+#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
+#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
+#define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
+
+/* Max. nvram variable table size */
+#define MAXSZ_NVRAM_VARS 4096
+
+typedef struct {
+ const char *name;
+ u32 revmask;
+ u32 flags;
+ u16 off;
+ u16 mask;
+} sromvar_t;
+
+typedef struct varbuf {
+ char *base; /* pointer to buffer base */
+ char *buf; /* pointer to current position */
+ unsigned int size; /* current (residual) size in bytes */
+} varbuf_t;
+
+/* Assumptions:
+ * - Ethernet address spans across 3 consective words
+ *
+ * Table rules:
+ * - Add multiple entries next to each other if a value spans across multiple words
+ * (even multiple fields in the same word) with each entry except the last having
+ * it's SRFL_MORE bit set.
+ * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
+ * bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
+ * - The last entry's name field must be NULL to indicate the end of the table. Other
+ * entries must have non-NULL name.
+ */
+static const sromvar_t pci_sromvars[] = {
+ {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
+ {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
+ {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
+ {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
+ {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
+ {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
+ {"", 0, 0, SROM_BFL2, 0xffff},
+ {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
+ {"", 0, 0, SROM3_BFL2, 0xffff},
+ {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
+ {"", 0, 0, SROM4_BFL1, 0xffff},
+ {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
+ {"", 0, 0, SROM5_BFL1, 0xffff},
+ {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
+ {"", 0, 0, SROM8_BFL1, 0xffff},
+ {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
+ {"", 0, 0, SROM4_BFL3, 0xffff},
+ {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
+ {"", 0, 0, SROM5_BFL3, 0xffff},
+ {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
+ {"", 0, 0, SROM8_BFL3, 0xffff},
+ {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
+ {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
+ {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
+ {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
+ {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
+ {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
+ {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
+ {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
+ {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
+ {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
+ {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
+ {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
+ {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
+ {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
+ {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
+ {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
+ {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
+ {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
+ {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
+ {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
+ {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
+ {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
+ {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
+ {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
+ {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
+ {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
+ {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
+ {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
+ {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
+ {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
+ {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
+ {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
+ {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
+ {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
+ {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
+ {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
+ {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
+ {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
+ {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
+ {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
+ {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
+ {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
+ {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
+ {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
+ {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
+ {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
+ {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
+ {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
+ {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
+ {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
+ {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
+ {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
+ {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
+ {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
+ {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
+ {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
+ {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
+ {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
+ {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
+ {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
+ {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
+ {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
+ {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
+ {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
+ {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
+ {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
+ {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
+ {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
+ {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
+ {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
+ {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
+ {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
+ {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
+ {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
+ {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
+ {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
+ {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
+ {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
+ {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
+ {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
+ {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
+ {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
+ {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
+ {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
+ {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
+ {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
+ {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
+ {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
+ {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
+ {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
+ {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
+ {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
+ {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
+ {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
+ {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
+ {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
+ {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
+ {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
+ {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
+ {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
+ {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
+ {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
+ {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
+ {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
+ {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
+ {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
+ {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
+ {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
+ {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
+ {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
+ {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
+ {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
+ {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
+ {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
+ {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
+ {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
+ {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
+ {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
+ {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
+ {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
+ {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
+ {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
+ {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
+ {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
+ {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
+ {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
+ {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
+ {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
+ {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
+ {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
+ {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
+ {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
+ {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
+ {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
+ {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
+ {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
+ {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
+ {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
+ {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
+ {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
+ {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
+ {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
+ {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
+
+ {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
+ {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
+ {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
+ {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
+ {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
+ {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
+ {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
+ {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
+ {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
+ {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
+ {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
+ {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
+ {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
+ {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
+ {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
+ {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
+ {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
+ 0x00ff},
+ {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
+ {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
+ 0x0300},
+ {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
+ 0x000f},
+ {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
+ {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
+ {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
+
+ {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
+ {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
+ {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
+ {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
+ {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
+ {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
+ {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
+ {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
+ {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
+ {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
+ {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
+ {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
+ {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
+ {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
+ {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
+ {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
+ {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
+ {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
+ {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
+ {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
+ {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
+ {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
+ {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
+ {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
+ {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
+ {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
+ {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
+ {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
+ {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
+ {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
+ {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
+ {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
+ {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
+ {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
+ {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
+ {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
+ {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
+ {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
+ {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
+ {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
+ {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
+ {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
+ {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
+ {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
+ {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
+ {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
+ {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
+ {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
+ {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
+ {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
+ {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
+ {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
+ {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
+ {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
+ {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
+ {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
+ {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
+ {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
+ {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
+ {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
+ {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
+ {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
+ {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
+ {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
+ {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
+ {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
+ {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
+ {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
+ {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
+ {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
+ {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
+ {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
+ {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
+ {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
+ {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
+ {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
+ {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
+ {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
+ {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
+ {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
+ {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
+ {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
+ {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
+ {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
+ {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
+ {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
+ {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
+ {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
+ {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
+ {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
+
+ /* power per rate from sromrev 9 */
+ {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
+ {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
+ {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
+ 0xffff},
+ {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
+ {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
+ {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
+ 0xffff},
+ {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
+ {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
+ {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
+ 0xffff},
+ {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
+ {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
+ {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
+ 0xffff},
+ {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
+ {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
+ {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
+ {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
+ {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
+ {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
+ {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
+ {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
+ {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
+ {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
+ {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
+ {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
+ {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
+ {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
+ {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
+ {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
+ {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
+ {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
+ {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
+ {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
+ {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
+ {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
+ {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
+ {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
+ {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
+
+ {NULL, 0, 0, 0, 0}
+};
+
+static const sromvar_t perpath_pci_sromvars[] = {
+ {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
+ {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
+ {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
+ {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
+ {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
+ {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
+ {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
+ {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
+ {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
+ {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
+ {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
+ {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
+ {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
+ {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
+ {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
+ {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
+ {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
+ {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
+ {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
+ {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
+ {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
+ {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
+ {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
+ {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
+ {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
+ {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
+ {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
+ {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
+ {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
+ {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
+ {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
+ {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
+ {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
+ {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
+ {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
+ {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
+ {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
+ {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
+ {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
+ {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
+ {NULL, 0, 0, 0, 0}
+};
+
+static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b);
+static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
+ uint *count);
+static int sprom_read_pci(struct si_pub *sih, u16 *sprom,
+ uint wordoff, u16 *buf, uint nwords, bool check_crc);
+#if defined(BCMNVRAMR)
+static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz);
+#endif
+static u16 srom_cc_cmd(struct si_pub *sih, void *ccregs, u32 cmd,
+ uint wordoff, u16 data);
+
+static int initvars_table(char *start, char *end,
+ char **vars, uint *count);
+
+/* Initialization of varbuf structure */
+static void varbuf_init(varbuf_t *b, char *buf, uint size)
+{
+ b->size = size;
+ b->base = b->buf = buf;
+}
+
+/* append a null terminated var=value string */
+static int varbuf_append(varbuf_t *b, const char *fmt, ...)
+{
+ va_list ap;
+ int r;
+ size_t len;
+ char *s;
+
+ if (b->size < 2)
+ return 0;
+
+ va_start(ap, fmt);
+ r = vsnprintf(b->buf, b->size, fmt, ap);
+ va_end(ap);
+
+ /* C99 snprintf behavior returns r >= size on overflow,
+ * others return -1 on overflow.
+ * All return -1 on format error.
+ * We need to leave room for 2 null terminations, one for the current var
+ * string, and one for final null of the var table. So check that the
+ * strlen written, r, leaves room for 2 chars.
+ */
+ if ((r == -1) || (r > (int)(b->size - 2))) {
+ b->size = 0;
+ return 0;
+ }
+
+ /* Remove any earlier occurrence of the same variable */
+ s = strchr(b->buf, '=');
+ if (s != NULL) {
+ len = (size_t) (s - b->buf);
+ for (s = b->base; s < b->buf;) {
+ if ((memcmp(s, b->buf, len) == 0) && s[len] == '=') {
+ len = strlen(s) + 1;
+ memmove(s, (s + len),
+ ((b->buf + r + 1) - (s + len)));
+ b->buf -= len;
+ b->size += (unsigned int)len;
+ break;
+ }
+
+ while (*s++)
+ ;
+ }
+ }
+
+ /* skip over this string's null termination */
+ r++;
+ b->size -= r;
+ b->buf += r;
+
+ return r;
+}
+
+/*
+ * Initialize local vars from the right source for this platform.
+ * Return 0 on success, nonzero on error.
+ */
+int srom_var_init(struct si_pub *sih, uint bustype, void *curmap,
+ char **vars, uint *count)
+{
+ uint len;
+
+ len = 0;
+
+ if (vars == NULL || count == NULL)
+ return 0;
+
+ *vars = NULL;
+ *count = 0;
+
+ if (curmap != NULL && bustype == PCI_BUS)
+ return initvars_srom_pci(sih, curmap, vars, count);
+
+ return -1;
+}
+
+/* In chips with chipcommon rev 32 and later, the srom is in chipcommon,
+ * not in the bus cores.
+ */
+static u16
+srom_cc_cmd(struct si_pub *sih, void *ccregs, u32 cmd,
+ uint wordoff, u16 data)
+{
+ chipcregs_t *cc = (chipcregs_t *) ccregs;
+ uint wait_cnt = 1000;
+
+ if ((cmd == SRC_OP_READ) || (cmd == SRC_OP_WRITE)) {
+ W_REG(&cc->sromaddress, wordoff * 2);
+ if (cmd == SRC_OP_WRITE)
+ W_REG(&cc->sromdata, data);
+ }
+
+ W_REG(&cc->sromcontrol, SRC_START | cmd);
+
+ while (wait_cnt--) {
+ if ((R_REG(&cc->sromcontrol) & SRC_BUSY) == 0)
+ break;
+ }
+
+ if (!wait_cnt) {
+ return 0xffff;
+ }
+ if (cmd == SRC_OP_READ)
+ return (u16) R_REG(&cc->sromdata);
+ else
+ return 0xffff;
+}
+
+static inline void ltoh16_buf(u16 *buf, unsigned int size)
+{
+ for (size /= 2; size; size--)
+ *(buf + size) = le16_to_cpu(*(buf + size));
+}
+
+static inline void htol16_buf(u16 *buf, unsigned int size)
+{
+ for (size /= 2; size; size--)
+ *(buf + size) = cpu_to_le16(*(buf + size));
+}
+
+/*
+ * Read in and validate sprom.
+ * Return 0 on success, nonzero on error.
+ */
+static int
+sprom_read_pci(struct si_pub *sih, u16 *sprom, uint wordoff,
+ u16 *buf, uint nwords, bool check_crc)
+{
+ int err = 0;
+ uint i;
+ void *ccregs = NULL;
+
+ /* read the sprom */
+ for (i = 0; i < nwords; i++) {
+
+ if (sih->ccrev > 31 && ISSIM_ENAB(sih)) {
+ /* use indirect since direct is too slow on QT */
+ if ((sih->cccaps & CC_CAP_SROM) == 0)
+ return 1;
+
+ ccregs = (void *)((u8 *) sprom - CC_SROM_OTP);
+ buf[i] =
+ srom_cc_cmd(sih, ccregs, SRC_OP_READ,
+ wordoff + i, 0);
+
+ } else {
+ if (ISSIM_ENAB(sih))
+ buf[i] = R_REG(&sprom[wordoff + i]);
+
+ buf[i] = R_REG(&sprom[wordoff + i]);
+ }
+
+ }
+
+ /* bypass crc checking for simulation to allow srom hack */
+ if (ISSIM_ENAB(sih))
+ return err;
+
+ if (check_crc) {
+
+ if (buf[0] == 0xffff) {
+ /* The hardware thinks that an srom that starts with 0xffff
+ * is blank, regardless of the rest of the content, so declare
+ * it bad.
+ */
+ return 1;
+ }
+
+ /* fixup the endianness so crc8 will pass */
+ htol16_buf(buf, nwords * 2);
+ if (brcmu_crc8((u8 *) buf, nwords * 2, CRC8_INIT_VALUE) !=
+ CRC8_GOOD_VALUE) {
+ /* DBG only pci always read srom4 first, then srom8/9 */
+ err = 1;
+ }
+ /* now correct the endianness of the byte array */
+ ltoh16_buf(buf, nwords * 2);
+ }
+ return err;
+}
+
+#if defined(BCMNVRAMR)
+static int otp_read_pci(struct si_pub *sih, u16 *buf, uint bufsz)
+{
+ u8 *otp;
+ uint sz = OTP_SZ_MAX / 2; /* size in words */
+ int err = 0;
+
+ otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
+ if (otp == NULL) {
+ return -EBADE;
+ }
+
+ err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
+
+ memcpy(buf, otp, bufsz);
+
+ kfree(otp);
+
+ /* Check CRC */
+ if (buf[0] == 0xffff) {
+ /* The hardware thinks that an srom that starts with 0xffff
+ * is blank, regardless of the rest of the content, so declare
+ * it bad.
+ */
+ return 1;
+ }
+
+ /* fixup the endianness so crc8 will pass */
+ htol16_buf(buf, bufsz);
+ if (brcmu_crc8((u8 *) buf, SROM4_WORDS * 2, CRC8_INIT_VALUE) !=
+ CRC8_GOOD_VALUE) {
+ err = 1;
+ }
+ /* now correct the endianness of the byte array */
+ ltoh16_buf(buf, bufsz);
+
+ return err;
+}
+#endif /* defined(BCMNVRAMR) */
+/*
+* Create variable table from memory.
+* Return 0 on success, nonzero on error.
+*/
+static int initvars_table(char *start, char *end,
+ char **vars, uint *count)
+{
+ int c = (int)(end - start);
+
+ /* do it only when there is more than just the null string */
+ if (c > 1) {
+ char *vp = kmalloc(c, GFP_ATOMIC);
+ if (!vp)
+ return -ENOMEM;
+ memcpy(vp, start, c);
+ *vars = vp;
+ *count = c;
+ } else {
+ *vars = NULL;
+ *count = 0;
+ }
+
+ return 0;
+}
+
+/* Parse SROM and create name=value pairs. 'srom' points to
+ * the SROM word array. 'off' specifies the offset of the
+ * first word 'srom' points to, which should be either 0 or
+ * SROM3_SWRG_OFF (full SROM or software region).
+ */
+
+static uint mask_shift(u16 mask)
+{
+ uint i;
+ for (i = 0; i < (sizeof(mask) << 3); i++) {
+ if (mask & (1 << i))
+ return i;
+ }
+ return 0;
+}
+
+static uint mask_width(u16 mask)
+{
+ int i;
+ for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
+ if (mask & (1 << i))
+ return (uint) (i - mask_shift(mask) + 1);
+ }
+ return 0;
+}
+
+static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b)
+{
+ u16 w;
+ u32 val;
+ const sromvar_t *srv;
+ uint width;
+ uint flags;
+ u32 sr = (1 << sromrev);
+
+ varbuf_append(b, "sromrev=%d", sromrev);
+
+ for (srv = pci_sromvars; srv->name != NULL; srv++) {
+ const char *name;
+
+ if ((srv->revmask & sr) == 0)
+ continue;
+
+ if (srv->off < off)
+ continue;
+
+ flags = srv->flags;
+ name = srv->name;
+
+ /* This entry is for mfgc only. Don't generate param for it, */
+ if (flags & SRFL_NOVAR)
+ continue;
+
+ if (flags & SRFL_ETHADDR) {
+ u8 ea[ETH_ALEN];
+
+ ea[0] = (srom[srv->off - off] >> 8) & 0xff;
+ ea[1] = srom[srv->off - off] & 0xff;
+ ea[2] = (srom[srv->off + 1 - off] >> 8) & 0xff;
+ ea[3] = srom[srv->off + 1 - off] & 0xff;
+ ea[4] = (srom[srv->off + 2 - off] >> 8) & 0xff;
+ ea[5] = srom[srv->off + 2 - off] & 0xff;
+
+ varbuf_append(b, "%s=%pM", name, ea);
+ } else {
+ w = srom[srv->off - off];
+ val = (w & srv->mask) >> mask_shift(srv->mask);
+ width = mask_width(srv->mask);
+
+ while (srv->flags & SRFL_MORE) {
+ srv++;
+ if (srv->off == 0 || srv->off < off)
+ continue;
+
+ w = srom[srv->off - off];
+ val +=
+ ((w & srv->mask) >> mask_shift(srv->
+ mask)) <<
+ width;
+ width += mask_width(srv->mask);
+ }
+
+ if ((flags & SRFL_NOFFS)
+ && ((int)val == (1 << width) - 1))
+ continue;
+
+ if (flags & SRFL_CCODE) {
+ if (val == 0)
+ varbuf_append(b, "ccode=");
+ else
+ varbuf_append(b, "ccode=%c%c",
+ (val >> 8), (val & 0xff));
+ }
+ /* LED Powersave duty cycle has to be scaled:
+ *(oncount >> 24) (offcount >> 8)
+ */
+ else if (flags & SRFL_LEDDC) {
+ u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
+ (((val & 0xff)) << 8); /* offcount */
+ varbuf_append(b, "leddc=%d", w32);
+ } else if (flags & SRFL_PRHEX)
+ varbuf_append(b, "%s=0x%x", name, val);
+ else if ((flags & SRFL_PRSIGN)
+ && (val & (1 << (width - 1))))
+ varbuf_append(b, "%s=%d", name,
+ (int)(val | (~0 << width)));
+ else
+ varbuf_append(b, "%s=%u", name, val);
+ }
+ }
+
+ if (sromrev >= 4) {
+ /* Do per-path variables */
+ uint p, pb, psz;
+
+ if (sromrev >= 8) {
+ pb = SROM8_PATH0;
+ psz = SROM8_PATH1 - SROM8_PATH0;
+ } else {
+ pb = SROM4_PATH0;
+ psz = SROM4_PATH1 - SROM4_PATH0;
+ }
+
+ for (p = 0; p < MAX_PATH_SROM; p++) {
+ for (srv = perpath_pci_sromvars; srv->name != NULL;
+ srv++) {
+ if ((srv->revmask & sr) == 0)
+ continue;
+
+ if (pb + srv->off < off)
+ continue;
+
+ /* This entry is for mfgc only. Don't generate param for it, */
+ if (srv->flags & SRFL_NOVAR)
+ continue;
+
+ w = srom[pb + srv->off - off];
+ val = (w & srv->mask) >> mask_shift(srv->mask);
+ width = mask_width(srv->mask);
+
+ /* Cheating: no per-path var is more than 1 word */
+
+ if ((srv->flags & SRFL_NOFFS)
+ && ((int)val == (1 << width) - 1))
+ continue;
+
+ if (srv->flags & SRFL_PRHEX)
+ varbuf_append(b, "%s%d=0x%x", srv->name,
+ p, val);
+ else
+ varbuf_append(b, "%s%d=%d", srv->name,
+ p, val);
+ }
+ pb += psz;
+ }
+ }
+}
+
+/*
+ * Initialize nonvolatile variable table from sprom.
+ * Return 0 on success, nonzero on error.
+ */
+static int initvars_srom_pci(struct si_pub *sih, void *curmap, char **vars,
+ uint *count)
+{
+ u16 *srom, *sromwindow;
+ u8 sromrev = 0;
+ u32 sr;
+ varbuf_t b;
+ char *vp, *base = NULL;
+ bool flash = false;
+ int err = 0;
+
+ /*
+ * Apply CRC over SROM content regardless SROM is present or not,
+ * and use variable <devpath>sromrev's existence in flash to decide
+ * if we should return an error when CRC fails or read SROM variables
+ * from flash.
+ */
+ srom = kmalloc(SROM_MAX, GFP_ATOMIC);
+ if (!srom)
+ return -2;
+
+ sromwindow = (u16 *) SROM_OFFSET(sih);
+ if (ai_is_sprom_available(sih)) {
+ err =
+ sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
+ true);
+
+ if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
+ (((sih->buscoretype == PCIE_CORE_ID)
+ && (sih->buscorerev >= 6))
+ || ((sih->buscoretype == PCI_CORE_ID)
+ && (sih->buscorerev >= 0xe)))) {
+ /* sromrev >= 4, read more */
+ err =
+ sprom_read_pci(sih, sromwindow, 0, srom,
+ SROM4_WORDS, true);
+ sromrev = srom[SROM4_CRCREV] & 0xff;
+ } else if (err == 0) {
+ /* srom is good and is rev < 4 */
+ /* top word of sprom contains version and crc8 */
+ sromrev = srom[SROM_CRCREV] & 0xff;
+ /* bcm4401 sroms misprogrammed */
+ if (sromrev == 0x10)
+ sromrev = 1;
+ }
+ }
+#if defined(BCMNVRAMR)
+ /* Use OTP if SPROM not available */
+ else {
+ err = otp_read_pci(sih, srom, SROM_MAX);
+ if (err == 0)
+ /* OTP only contain SROM rev8/rev9 for now */
+ sromrev = srom[SROM4_CRCREV] & 0xff;
+ else
+ err = 1;
+ }
+#else
+ else
+ err = 1;
+#endif
+
+ /*
+ * We want internal/wltest driver to come up with default
+ * sromvars so we can program a blank SPROM/OTP.
+ */
+ if (err) {
+ char *value;
+ u32 val;
+ val = 0;
+
+ value = ai_getdevpathvar(sih, "sromrev");
+ if (value) {
+ sromrev = (u8) simple_strtoul(value, NULL, 0);
+ flash = true;
+ goto varscont;
+ }
+
+ value = ai_getnvramflvar(sih, "sromrev");
+ if (value) {
+ err = 0;
+ goto errout;
+ }
+
+ {
+ err = -1;
+ goto errout;
+ }
+ }
+
+ varscont:
+ /* Bitmask for the sromrev */
+ sr = 1 << sromrev;
+
+ /* srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 9 */
+ if ((sr & 0x33e) == 0) {
+ err = -2;
+ goto errout;
+ }
+
+ base = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
+ if (!base) {
+ err = -2;
+ goto errout;
+ }
+
+ varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
+
+ /* parse SROM into name=value pairs. */
+ _initvars_srom_pci(sromrev, srom, 0, &b);
+
+ /* final nullbyte terminator */
+ vp = b.buf;
+ *vp++ = '\0';
+
+ err = initvars_table(base, vp, vars, count);
+
+ errout:
+ if (base)
+ kfree(base);
+
+ kfree(srom);
+ return err;
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <defs.h>
+#include <brcmu_utils.h>
+#include <aiutils.h>
+#include <brcmu_wifi.h>
+#include "dma.h"
+
+#include "types.h"
+#include "d11.h"
+#include "cfg.h"
+#include "rate.h"
+#include "scb.h"
+#include "pub.h"
+#include "key.h"
+#include "phy/phy_hal.h"
+#include "channel.h"
+#include "main.h"
+#include "bottom_mac.h"
+#include "stf.h"
+
+#define MIN_SPATIAL_EXPANSION 0
+#define MAX_SPATIAL_EXPANSION 1
+
+#define WLC_STF_SS_STBC_RX(wlc) (WLCISNPHY(wlc->band) && \
+ NREV_GT(wlc->band->phyrev, 3) && NREV_LE(wlc->band->phyrev, 6))
+
+static bool wlc_stf_stbc_tx_set(struct wlc_info *wlc, s32 int_val);
+static int wlc_stf_txcore_set(struct wlc_info *wlc, u8 Nsts, u8 val);
+static int wlc_stf_spatial_policy_set(struct wlc_info *wlc, int val);
+static void wlc_stf_stbc_rx_ht_update(struct wlc_info *wlc, int val);
+
+static void _wlc_stf_phy_txant_upd(struct wlc_info *wlc);
+static u16 _wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec);
+
+#define NSTS_1 1
+#define NSTS_2 2
+#define NSTS_3 3
+#define NSTS_4 4
+const u8 txcore_default[5] = {
+ (0), /* bitmap of the core enabled */
+ (0x01), /* For Nsts = 1, enable core 1 */
+ (0x03), /* For Nsts = 2, enable core 1 & 2 */
+ (0x07), /* For Nsts = 3, enable core 1, 2 & 3 */
+ (0x0f) /* For Nsts = 4, enable all cores */
+};
+
+static void wlc_stf_stbc_rx_ht_update(struct wlc_info *wlc, int val)
+{
+ /* MIMOPHYs rev3-6 cannot receive STBC with only one rx core active */
+ if (WLC_STF_SS_STBC_RX(wlc)) {
+ if ((wlc->stf->rxstreams == 1) && (val != HT_CAP_RX_STBC_NO))
+ return;
+ }
+
+ wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_RX_STBC;
+ wlc->ht_cap.cap_info |= (val << IEEE80211_HT_CAP_RX_STBC_SHIFT);
+
+ if (wlc->pub->up) {
+ wlc_update_beacon(wlc);
+ wlc_update_probe_resp(wlc, true);
+ }
+}
+
+/* every WLC_TEMPSENSE_PERIOD seconds temperature check to decide whether to turn on/off txchain */
+void wlc_tempsense_upd(struct wlc_info *wlc)
+{
+ wlc_phy_t *pi = wlc->band->pi;
+ uint active_chains, txchain;
+
+ /* Check if the chip is too hot. Disable one Tx chain, if it is */
+ /* high 4 bits are for Rx chain, low 4 bits are for Tx chain */
+ active_chains = wlc_phy_stf_chain_active_get(pi);
+ txchain = active_chains & 0xf;
+
+ if (wlc->stf->txchain == wlc->stf->hw_txchain) {
+ if (txchain && (txchain < wlc->stf->hw_txchain)) {
+ /* turn off 1 tx chain */
+ wlc_stf_txchain_set(wlc, txchain, true);
+ }
+ } else if (wlc->stf->txchain < wlc->stf->hw_txchain) {
+ if (txchain == wlc->stf->hw_txchain) {
+ /* turn back on txchain */
+ wlc_stf_txchain_set(wlc, txchain, true);
+ }
+ }
+}
+
+void
+wlc_stf_ss_algo_channel_get(struct wlc_info *wlc, u16 *ss_algo_channel,
+ chanspec_t chanspec)
+{
+ tx_power_t power;
+ u8 siso_mcs_id, cdd_mcs_id, stbc_mcs_id;
+
+ /* Clear previous settings */
+ *ss_algo_channel = 0;
+
+ if (!wlc->pub->up) {
+ *ss_algo_channel = (u16) -1;
+ return;
+ }
+
+ wlc_phy_txpower_get_current(wlc->band->pi, &power,
+ CHSPEC_CHANNEL(chanspec));
+
+ siso_mcs_id = (CHSPEC_IS40(chanspec)) ?
+ WL_TX_POWER_MCS40_SISO_FIRST : WL_TX_POWER_MCS20_SISO_FIRST;
+ cdd_mcs_id = (CHSPEC_IS40(chanspec)) ?
+ WL_TX_POWER_MCS40_CDD_FIRST : WL_TX_POWER_MCS20_CDD_FIRST;
+ stbc_mcs_id = (CHSPEC_IS40(chanspec)) ?
+ WL_TX_POWER_MCS40_STBC_FIRST : WL_TX_POWER_MCS20_STBC_FIRST;
+
+ /* criteria to choose stf mode */
+
+ /* the "+3dbm (12 0.25db units)" is to account for the fact that with CDD, tx occurs
+ * on both chains
+ */
+ if (power.target[siso_mcs_id] > (power.target[cdd_mcs_id] + 12))
+ setbit(ss_algo_channel, PHY_TXC1_MODE_SISO);
+ else
+ setbit(ss_algo_channel, PHY_TXC1_MODE_CDD);
+
+ /* STBC is ORed into to algo channel as STBC requires per-packet SCB capability check
+ * so cannot be default mode of operation. One of SISO, CDD have to be set
+ */
+ if (power.target[siso_mcs_id] <= (power.target[stbc_mcs_id] + 12))
+ setbit(ss_algo_channel, PHY_TXC1_MODE_STBC);
+}
+
+static bool wlc_stf_stbc_tx_set(struct wlc_info *wlc, s32 int_val)
+{
+ if ((int_val != AUTO) && (int_val != OFF) && (int_val != ON)) {
+ return false;
+ }
+
+ if ((int_val == ON) && (wlc->stf->txstreams == 1))
+ return false;
+
+ if ((int_val == OFF) || (wlc->stf->txstreams == 1)
+ || !WLC_STBC_CAP_PHY(wlc))
+ wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_TX_STBC;
+ else
+ wlc->ht_cap.cap_info |= IEEE80211_HT_CAP_TX_STBC;
+
+ wlc->bandstate[BAND_2G_INDEX]->band_stf_stbc_tx = (s8) int_val;
+ wlc->bandstate[BAND_5G_INDEX]->band_stf_stbc_tx = (s8) int_val;
+
+ return true;
+}
+
+bool wlc_stf_stbc_rx_set(struct wlc_info *wlc, s32 int_val)
+{
+ if ((int_val != HT_CAP_RX_STBC_NO)
+ && (int_val != HT_CAP_RX_STBC_ONE_STREAM)) {
+ return false;
+ }
+
+ if (WLC_STF_SS_STBC_RX(wlc)) {
+ if ((int_val != HT_CAP_RX_STBC_NO)
+ && (wlc->stf->rxstreams == 1))
+ return false;
+ }
+
+ wlc_stf_stbc_rx_ht_update(wlc, int_val);
+ return true;
+}
+
+static int wlc_stf_txcore_set(struct wlc_info *wlc, u8 Nsts, u8 core_mask)
+{
+ BCMMSG(wlc->wiphy, "wl%d: Nsts %d core_mask %x\n",
+ wlc->pub->unit, Nsts, core_mask);
+
+ if (WLC_BITSCNT(core_mask) > wlc->stf->txstreams) {
+ core_mask = 0;
+ }
+
+ if ((WLC_BITSCNT(core_mask) == wlc->stf->txstreams) &&
+ ((core_mask & ~wlc->stf->txchain)
+ || !(core_mask & wlc->stf->txchain))) {
+ core_mask = wlc->stf->txchain;
+ }
+
+ wlc->stf->txcore[Nsts] = core_mask;
+ /* Nsts = 1..4, txcore index = 1..4 */
+ if (Nsts == 1) {
+ /* Needs to update beacon and ucode generated response
+ * frames when 1 stream core map changed
+ */
+ wlc->stf->phytxant = core_mask << PHY_TXC_ANT_SHIFT;
+ wlc_bmac_txant_set(wlc->hw, wlc->stf->phytxant);
+ if (wlc->clk) {
+ wlc_suspend_mac_and_wait(wlc);
+ wlc_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec);
+ wlc_enable_mac(wlc);
+ }
+ }
+
+ return 0;
+}
+
+static int wlc_stf_spatial_policy_set(struct wlc_info *wlc, int val)
+{
+ int i;
+ u8 core_mask = 0;
+
+ BCMMSG(wlc->wiphy, "wl%d: val %x\n", wlc->pub->unit, val);
+
+ wlc->stf->spatial_policy = (s8) val;
+ for (i = 1; i <= MAX_STREAMS_SUPPORTED; i++) {
+ core_mask = (val == MAX_SPATIAL_EXPANSION) ?
+ wlc->stf->txchain : txcore_default[i];
+ wlc_stf_txcore_set(wlc, (u8) i, core_mask);
+ }
+ return 0;
+}
+
+int wlc_stf_txchain_set(struct wlc_info *wlc, s32 int_val, bool force)
+{
+ u8 txchain = (u8) int_val;
+ u8 txstreams;
+ uint i;
+
+ if (wlc->stf->txchain == txchain)
+ return 0;
+
+ if ((txchain & ~wlc->stf->hw_txchain)
+ || !(txchain & wlc->stf->hw_txchain))
+ return -EINVAL;
+
+ /* if nrate override is configured to be non-SISO STF mode, reject reducing txchain to 1 */
+ txstreams = (u8) WLC_BITSCNT(txchain);
+ if (txstreams > MAX_STREAMS_SUPPORTED)
+ return -EINVAL;
+
+ if (txstreams == 1) {
+ for (i = 0; i < NBANDS(wlc); i++)
+ if ((RSPEC_STF(wlc->bandstate[i]->rspec_override) !=
+ PHY_TXC1_MODE_SISO)
+ || (RSPEC_STF(wlc->bandstate[i]->mrspec_override) !=
+ PHY_TXC1_MODE_SISO)) {
+ if (!force)
+ return -EBADE;
+
+ /* over-write the override rspec */
+ if (RSPEC_STF(wlc->bandstate[i]->rspec_override)
+ != PHY_TXC1_MODE_SISO) {
+ wlc->bandstate[i]->rspec_override = 0;
+ wiphy_err(wlc->wiphy, "%s(): temp "
+ "sense override non-SISO "
+ "rspec_override\n",
+ __func__);
+ }
+ if (RSPEC_STF
+ (wlc->bandstate[i]->mrspec_override) !=
+ PHY_TXC1_MODE_SISO) {
+ wlc->bandstate[i]->mrspec_override = 0;
+ wiphy_err(wlc->wiphy, "%s(): temp "
+ "sense override non-SISO "
+ "mrspec_override\n",
+ __func__);
+ }
+ }
+ }
+
+ wlc->stf->txchain = txchain;
+ wlc->stf->txstreams = txstreams;
+ wlc_stf_stbc_tx_set(wlc, wlc->band->band_stf_stbc_tx);
+ wlc_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
+ wlc_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
+ wlc->stf->txant =
+ (wlc->stf->txstreams == 1) ? ANT_TX_FORCE_0 : ANT_TX_DEF;
+ _wlc_stf_phy_txant_upd(wlc);
+
+ wlc_phy_stf_chain_set(wlc->band->pi, wlc->stf->txchain,
+ wlc->stf->rxchain);
+
+ for (i = 1; i <= MAX_STREAMS_SUPPORTED; i++)
+ wlc_stf_txcore_set(wlc, (u8) i, txcore_default[i]);
+
+ return 0;
+}
+
+/* update wlc->stf->ss_opmode which represents the operational stf_ss mode we're using */
+int wlc_stf_ss_update(struct wlc_info *wlc, struct wlcband *band)
+{
+ int ret_code = 0;
+ u8 prev_stf_ss;
+ u8 upd_stf_ss;
+
+ prev_stf_ss = wlc->stf->ss_opmode;
+
+ /* NOTE: opmode can only be SISO or CDD as STBC is decided on a per-packet basis */
+ if (WLC_STBC_CAP_PHY(wlc) &&
+ wlc->stf->ss_algosel_auto
+ && (wlc->stf->ss_algo_channel != (u16) -1)) {
+ upd_stf_ss = (wlc->stf->no_cddstbc || (wlc->stf->txstreams == 1)
+ || isset(&wlc->stf->ss_algo_channel,
+ PHY_TXC1_MODE_SISO)) ? PHY_TXC1_MODE_SISO
+ : PHY_TXC1_MODE_CDD;
+ } else {
+ if (wlc->band != band)
+ return ret_code;
+ upd_stf_ss = (wlc->stf->no_cddstbc
+ || (wlc->stf->txstreams ==
+ 1)) ? PHY_TXC1_MODE_SISO : band->
+ band_stf_ss_mode;
+ }
+ if (prev_stf_ss != upd_stf_ss) {
+ wlc->stf->ss_opmode = upd_stf_ss;
+ wlc_bmac_band_stf_ss_set(wlc->hw, upd_stf_ss);
+ }
+
+ return ret_code;
+}
+
+int wlc_stf_attach(struct wlc_info *wlc)
+{
+ wlc->bandstate[BAND_2G_INDEX]->band_stf_ss_mode = PHY_TXC1_MODE_SISO;
+ wlc->bandstate[BAND_5G_INDEX]->band_stf_ss_mode = PHY_TXC1_MODE_CDD;
+
+ if (WLCISNPHY(wlc->band) &&
+ (wlc_phy_txpower_hw_ctrl_get(wlc->band->pi) != PHY_TPC_HW_ON))
+ wlc->bandstate[BAND_2G_INDEX]->band_stf_ss_mode =
+ PHY_TXC1_MODE_CDD;
+ wlc_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
+ wlc_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
+
+ wlc_stf_stbc_rx_ht_update(wlc, HT_CAP_RX_STBC_NO);
+ wlc->bandstate[BAND_2G_INDEX]->band_stf_stbc_tx = OFF;
+ wlc->bandstate[BAND_5G_INDEX]->band_stf_stbc_tx = OFF;
+
+ if (WLC_STBC_CAP_PHY(wlc)) {
+ wlc->stf->ss_algosel_auto = true;
+ wlc->stf->ss_algo_channel = (u16) -1; /* Init the default value */
+ }
+ return 0;
+}
+
+void wlc_stf_detach(struct wlc_info *wlc)
+{
+}
+
+/*
+ * Centralized txant update function. call it whenever wlc->stf->txant and/or wlc->stf->txchain
+ * change
+ *
+ * Antennas are controlled by ucode indirectly, which drives PHY or GPIO to
+ * achieve various tx/rx antenna selection schemes
+ *
+ * legacy phy, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7 means auto(last rx)
+ * for NREV<3, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7 means last rx and
+ * do tx-antenna selection for SISO transmissions
+ * for NREV=3, bit 6 and bit _8_ means antenna 0 and 1 respectively, bit6+bit7 means last rx and
+ * do tx-antenna selection for SISO transmissions
+ * for NREV>=7, bit 6 and bit 7 mean antenna 0 and 1 respectively, nit6+bit7 means both cores active
+*/
+static void _wlc_stf_phy_txant_upd(struct wlc_info *wlc)
+{
+ s8 txant;
+
+ txant = (s8) wlc->stf->txant;
+ if (WLC_PHY_11N_CAP(wlc->band)) {
+ if (txant == ANT_TX_FORCE_0) {
+ wlc->stf->phytxant = PHY_TXC_ANT_0;
+ } else if (txant == ANT_TX_FORCE_1) {
+ wlc->stf->phytxant = PHY_TXC_ANT_1;
+
+ if (WLCISNPHY(wlc->band) &&
+ NREV_GE(wlc->band->phyrev, 3)
+ && NREV_LT(wlc->band->phyrev, 7)) {
+ wlc->stf->phytxant = PHY_TXC_ANT_2;
+ }
+ } else {
+ if (WLCISLCNPHY(wlc->band) || WLCISSSLPNPHY(wlc->band))
+ wlc->stf->phytxant = PHY_TXC_LCNPHY_ANT_LAST;
+ else {
+ /* catch out of sync wlc->stf->txcore */
+ WARN_ON(wlc->stf->txchain <= 0);
+ wlc->stf->phytxant =
+ wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
+ }
+ }
+ } else {
+ if (txant == ANT_TX_FORCE_0)
+ wlc->stf->phytxant = PHY_TXC_OLD_ANT_0;
+ else if (txant == ANT_TX_FORCE_1)
+ wlc->stf->phytxant = PHY_TXC_OLD_ANT_1;
+ else
+ wlc->stf->phytxant = PHY_TXC_OLD_ANT_LAST;
+ }
+
+ wlc_bmac_txant_set(wlc->hw, wlc->stf->phytxant);
+}
+
+void wlc_stf_phy_txant_upd(struct wlc_info *wlc)
+{
+ _wlc_stf_phy_txant_upd(wlc);
+}
+
+void wlc_stf_phy_chain_calc(struct wlc_info *wlc)
+{
+ /* get available rx/tx chains */
+ wlc->stf->hw_txchain = (u8) getintvar(wlc->pub->vars, "txchain");
+ wlc->stf->hw_rxchain = (u8) getintvar(wlc->pub->vars, "rxchain");
+
+ /* these parameter are intended to be used for all PHY types */
+ if (wlc->stf->hw_txchain == 0 || wlc->stf->hw_txchain == 0xf) {
+ if (WLCISNPHY(wlc->band)) {
+ wlc->stf->hw_txchain = TXCHAIN_DEF_NPHY;
+ } else {
+ wlc->stf->hw_txchain = TXCHAIN_DEF;
+ }
+ }
+
+ wlc->stf->txchain = wlc->stf->hw_txchain;
+ wlc->stf->txstreams = (u8) WLC_BITSCNT(wlc->stf->hw_txchain);
+
+ if (wlc->stf->hw_rxchain == 0 || wlc->stf->hw_rxchain == 0xf) {
+ if (WLCISNPHY(wlc->band)) {
+ wlc->stf->hw_rxchain = RXCHAIN_DEF_NPHY;
+ } else {
+ wlc->stf->hw_rxchain = RXCHAIN_DEF;
+ }
+ }
+
+ wlc->stf->rxchain = wlc->stf->hw_rxchain;
+ wlc->stf->rxstreams = (u8) WLC_BITSCNT(wlc->stf->hw_rxchain);
+
+ /* initialize the txcore table */
+ memcpy(wlc->stf->txcore, txcore_default, sizeof(wlc->stf->txcore));
+
+ /* default spatial_policy */
+ wlc->stf->spatial_policy = MIN_SPATIAL_EXPANSION;
+ wlc_stf_spatial_policy_set(wlc, MIN_SPATIAL_EXPANSION);
+}
+
+static u16 _wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec)
+{
+ u16 phytxant = wlc->stf->phytxant;
+
+ if (RSPEC_STF(rspec) != PHY_TXC1_MODE_SISO) {
+ phytxant = wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
+ } else if (wlc->stf->txant == ANT_TX_DEF)
+ phytxant = wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
+ phytxant &= PHY_TXC_ANT_MASK;
+ return phytxant;
+}
+
+u16 wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec)
+{
+ return _wlc_stf_phytxchain_sel(wlc, rspec);
+}
+
+u16 wlc_stf_d11hdrs_phyctl_txant(struct wlc_info *wlc, ratespec_t rspec)
+{
+ u16 phytxant = wlc->stf->phytxant;
+ u16 mask = PHY_TXC_ANT_MASK;
+
+ /* for non-siso rates or default setting, use the available chains */
+ if (WLCISNPHY(wlc->band)) {
+ phytxant = _wlc_stf_phytxchain_sel(wlc, rspec);
+ mask = PHY_TXC_HTANT_MASK;
+ }
+ phytxant |= phytxant & mask;
+ return phytxant;
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_STF_H_
+#define _BRCM_STF_H_
+
+extern int wlc_stf_attach(struct wlc_info *wlc);
+extern void wlc_stf_detach(struct wlc_info *wlc);
+
+extern void wlc_tempsense_upd(struct wlc_info *wlc);
+extern void wlc_stf_ss_algo_channel_get(struct wlc_info *wlc,
+ u16 *ss_algo_channel,
+ chanspec_t chanspec);
+extern int wlc_stf_ss_update(struct wlc_info *wlc, struct wlcband *band);
+extern void wlc_stf_phy_txant_upd(struct wlc_info *wlc);
+extern int wlc_stf_txchain_set(struct wlc_info *wlc, s32 int_val, bool force);
+extern bool wlc_stf_stbc_rx_set(struct wlc_info *wlc, s32 int_val);
+extern void wlc_stf_phy_txant_upd(struct wlc_info *wlc);
+extern void wlc_stf_phy_chain_calc(struct wlc_info *wlc);
+extern u16 wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec);
+extern u16 wlc_stf_d11hdrs_phyctl_txant(struct wlc_info *wlc, ratespec_t rspec);
+
+#endif /* _BRCM_STF_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_TYPES_H_
+#define _BRCM_TYPES_H_
+
+/* Bus types */
+#define SI_BUS 0 /* SOC Interconnect */
+#define PCI_BUS 1 /* PCI target */
+#define SDIO_BUS 3 /* SDIO target */
+#define JTAG_BUS 4 /* JTAG */
+#define USB_BUS 5 /* USB (does not support R/W REG) */
+#define SPI_BUS 6 /* gSPI target */
+#define RPC_BUS 7 /* RPC target */
+
+#define WL_CHAN_FREQ_RANGE_2G 0
+#define WL_CHAN_FREQ_RANGE_5GL 1
+#define WL_CHAN_FREQ_RANGE_5GM 2
+#define WL_CHAN_FREQ_RANGE_5GH 3
+
+#define MAX_DMA_SEGS 4
+
+#define BCMMSG(dev, fmt, args...) \
+do { \
+ if (brcm_msg_level & LOG_TRACE_VAL) \
+ wiphy_err(dev, "%s: " fmt, __func__, ##args); \
+} while (0)
+
+#define WL_ERROR_ON() (brcm_msg_level & LOG_ERROR_VAL)
+
+/* register access macros */
+#ifndef __BIG_ENDIAN
+#ifndef __mips__
+#define R_REG(r) \
+ ({\
+ sizeof(*(r)) == sizeof(u8) ? \
+ readb((volatile u8*)(r)) : \
+ sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
+ readl((volatile u32*)(r)); \
+ })
+#else /* __mips__ */
+#define R_REG(r) \
+ ({ \
+ __typeof(*(r)) __osl_v; \
+ __asm__ __volatile__("sync"); \
+ switch (sizeof(*(r))) { \
+ case sizeof(u8): \
+ __osl_v = readb((volatile u8*)(r)); \
+ break; \
+ case sizeof(u16): \
+ __osl_v = readw((volatile u16*)(r)); \
+ break; \
+ case sizeof(u32): \
+ __osl_v = \
+ readl((volatile u32*)(r)); \
+ break; \
+ } \
+ __asm__ __volatile__("sync"); \
+ __osl_v; \
+ })
+#endif /* __mips__ */
+
+#define W_REG(r, v) do { \
+ switch (sizeof(*(r))) { \
+ case sizeof(u8): \
+ writeb((u8)(v), (volatile u8*)(r)); break; \
+ case sizeof(u16): \
+ writew((u16)(v), (volatile u16*)(r)); break; \
+ case sizeof(u32): \
+ writel((u32)(v), (volatile u32*)(r)); break; \
+ }; \
+ } while (0)
+#else /* __BIG_ENDIAN */
+#define R_REG(r) \
+ ({ \
+ __typeof(*(r)) __osl_v; \
+ switch (sizeof(*(r))) { \
+ case sizeof(u8): \
+ __osl_v = \
+ readb((volatile u8*)((r)^3)); \
+ break; \
+ case sizeof(u16): \
+ __osl_v = \
+ readw((volatile u16*)((r)^2)); \
+ break; \
+ case sizeof(u32): \
+ __osl_v = readl((volatile u32*)(r)); \
+ break; \
+ } \
+ __osl_v; \
+ })
+
+#define W_REG(r, v) do { \
+ switch (sizeof(*(r))) { \
+ case sizeof(u8): \
+ writeb((u8)(v), \
+ (volatile u8*)((r)^3)); break; \
+ case sizeof(u16): \
+ writew((u16)(v), \
+ (volatile u16*)((r)^2)); break; \
+ case sizeof(u32): \
+ writel((u32)(v), \
+ (volatile u32*)(r)); break; \
+ } \
+ } while (0)
+#endif /* __BIG_ENDIAN */
+
+#ifdef __mips__
+/*
+ * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
+ * transactions. As a fix, a read after write is performed on certain places
+ * in the code. Older chips and the newer 5357 family don't require this fix.
+ */
+#define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
+#else
+#define W_REG_FLUSH(r, v) W_REG((r), (v))
+#endif /* __mips__ */
+
+#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
+#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
+
+#define SET_REG(r, mask, val) \
+ W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
+
+/* forward declarations */
+struct sk_buff;
+struct brcms_info;
+struct wlc_info;
+struct wlc_hw_info;
+struct wlc_if;
+struct brcms_if;
+struct ampdu_info;
+struct antsel_info;
+struct bmac_pmq;
+struct d11init;
+struct dma_pub;
+struct wlc_bsscfg;
+struct brcmu_strbuf;
+struct si_pub;
+
+/* brcm_msg_level is a bit vector with defs in defs.h */
+extern u32 brcm_msg_level;
+
+#endif /* _BRCM_TYPES_H_ */
*/
#include <linux/types.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <ucode_loader.h>
enum {
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
-#include "wlc_types.h" /* forward structure declarations */
+#include "types.h" /* forward structure declarations */
#define MIN_FW_SIZE 40000 /* minimum firmware file size in bytes */
#define MAX_FW_SIZE 150000
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include <bcmdefs.h>
-#include <brcmu_utils.h>
-#include <aiutils.h>
-#include "bcmdma.h"
-
-#include "d11.h"
-#include "wlc_types.h"
-#include "wlc_cfg.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "wlc_key.h"
-#include "wlc_alloc.h"
-#include "wlc_rate.h"
-#include "wlc_bsscfg.h"
-#include "phy/wlc_phy_hal.h"
-#include "wlc_channel.h"
-#include "wlc_main.h"
-
-static struct wlc_bsscfg *wlc_bsscfg_malloc(uint unit);
-static void wlc_bsscfg_mfree(struct wlc_bsscfg *cfg);
-static struct wlc_pub *wlc_pub_malloc(uint unit,
- uint *err, uint devid);
-static void wlc_pub_mfree(struct wlc_pub *pub);
-static void wlc_tunables_init(wlc_tunables_t *tunables, uint devid);
-
-static void wlc_tunables_init(wlc_tunables_t *tunables, uint devid)
-{
- tunables->ntxd = NTXD;
- tunables->nrxd = NRXD;
- tunables->rxbufsz = RXBUFSZ;
- tunables->nrxbufpost = NRXBUFPOST;
- tunables->maxscb = MAXSCB;
- tunables->ampdunummpdu = AMPDU_NUM_MPDU;
- tunables->maxpktcb = MAXPKTCB;
- tunables->maxucodebss = WLC_MAX_UCODE_BSS;
- tunables->maxucodebss4 = WLC_MAX_UCODE_BSS4;
- tunables->maxbss = MAXBSS;
- tunables->datahiwat = WLC_DATAHIWAT;
- tunables->ampdudatahiwat = WLC_AMPDUDATAHIWAT;
- tunables->rxbnd = RXBND;
- tunables->txsbnd = TXSBND;
-}
-
-static struct wlc_pub *wlc_pub_malloc(uint unit, uint *err, uint devid)
-{
- struct wlc_pub *pub;
-
- pub = kzalloc(sizeof(struct wlc_pub), GFP_ATOMIC);
- if (pub == NULL) {
- *err = 1001;
- goto fail;
- }
-
- pub->tunables = kzalloc(sizeof(wlc_tunables_t), GFP_ATOMIC);
- if (pub->tunables == NULL) {
- *err = 1028;
- goto fail;
- }
-
- /* need to init the tunables now */
- wlc_tunables_init(pub->tunables, devid);
-
- pub->multicast = kzalloc(ETH_ALEN * MAXMULTILIST, GFP_ATOMIC);
- if (pub->multicast == NULL) {
- *err = 1003;
- goto fail;
- }
-
- return pub;
-
- fail:
- wlc_pub_mfree(pub);
- return NULL;
-}
-
-static void wlc_pub_mfree(struct wlc_pub *pub)
-{
- if (pub == NULL)
- return;
-
- kfree(pub->multicast);
- kfree(pub->tunables);
- kfree(pub);
-}
-
-static struct wlc_bsscfg *wlc_bsscfg_malloc(uint unit)
-{
- struct wlc_bsscfg *cfg;
-
- cfg = kzalloc(sizeof(struct wlc_bsscfg), GFP_ATOMIC);
- if (cfg == NULL)
- goto fail;
-
- cfg->current_bss = kzalloc(sizeof(wlc_bss_info_t), GFP_ATOMIC);
- if (cfg->current_bss == NULL)
- goto fail;
-
- return cfg;
-
- fail:
- wlc_bsscfg_mfree(cfg);
- return NULL;
-}
-
-static void wlc_bsscfg_mfree(struct wlc_bsscfg *cfg)
-{
- if (cfg == NULL)
- return;
-
- kfree(cfg->maclist);
- kfree(cfg->current_bss);
- kfree(cfg);
-}
-
-static void wlc_bsscfg_ID_assign(struct wlc_info *wlc,
- struct wlc_bsscfg *bsscfg)
-{
- bsscfg->ID = wlc->next_bsscfg_ID;
- wlc->next_bsscfg_ID++;
-}
-
-/*
- * The common driver entry routine. Error codes should be unique
- */
-struct wlc_info *wlc_attach_malloc(uint unit, uint *err, uint devid)
-{
- struct wlc_info *wlc;
-
- wlc = kzalloc(sizeof(struct wlc_info), GFP_ATOMIC);
- if (wlc == NULL) {
- *err = 1002;
- goto fail;
- }
-
- /* allocate struct wlc_pub state structure */
- wlc->pub = wlc_pub_malloc(unit, err, devid);
- if (wlc->pub == NULL) {
- *err = 1003;
- goto fail;
- }
- wlc->pub->wlc = wlc;
-
- /* allocate struct wlc_hw_info state structure */
-
- wlc->hw = kzalloc(sizeof(struct wlc_hw_info), GFP_ATOMIC);
- if (wlc->hw == NULL) {
- *err = 1005;
- goto fail;
- }
- wlc->hw->wlc = wlc;
-
- wlc->hw->bandstate[0] =
- kzalloc(sizeof(struct wlc_hwband) * MAXBANDS, GFP_ATOMIC);
- if (wlc->hw->bandstate[0] == NULL) {
- *err = 1006;
- goto fail;
- } else {
- int i;
-
- for (i = 1; i < MAXBANDS; i++) {
- wlc->hw->bandstate[i] = (struct wlc_hwband *)
- ((unsigned long)wlc->hw->bandstate[0] +
- (sizeof(struct wlc_hwband) * i));
- }
- }
-
- wlc->modulecb =
- kzalloc(sizeof(struct modulecb) * WLC_MAXMODULES, GFP_ATOMIC);
- if (wlc->modulecb == NULL) {
- *err = 1009;
- goto fail;
- }
-
- wlc->default_bss = kzalloc(sizeof(wlc_bss_info_t), GFP_ATOMIC);
- if (wlc->default_bss == NULL) {
- *err = 1010;
- goto fail;
- }
-
- wlc->cfg = wlc_bsscfg_malloc(unit);
- if (wlc->cfg == NULL) {
- *err = 1011;
- goto fail;
- }
- wlc_bsscfg_ID_assign(wlc, wlc->cfg);
-
- wlc->wsec_def_keys[0] =
- kzalloc(sizeof(wsec_key_t) * WLC_DEFAULT_KEYS, GFP_ATOMIC);
- if (wlc->wsec_def_keys[0] == NULL) {
- *err = 1015;
- goto fail;
- } else {
- int i;
- for (i = 1; i < WLC_DEFAULT_KEYS; i++) {
- wlc->wsec_def_keys[i] = (wsec_key_t *)
- ((unsigned long)wlc->wsec_def_keys[0] +
- (sizeof(wsec_key_t) * i));
- }
- }
-
- wlc->protection = kzalloc(sizeof(struct wlc_protection), GFP_ATOMIC);
- if (wlc->protection == NULL) {
- *err = 1016;
- goto fail;
- }
-
- wlc->stf = kzalloc(sizeof(struct wlc_stf), GFP_ATOMIC);
- if (wlc->stf == NULL) {
- *err = 1017;
- goto fail;
- }
-
- wlc->bandstate[0] =
- kzalloc(sizeof(struct wlcband)*MAXBANDS, GFP_ATOMIC);
- if (wlc->bandstate[0] == NULL) {
- *err = 1025;
- goto fail;
- } else {
- int i;
-
- for (i = 1; i < MAXBANDS; i++) {
- wlc->bandstate[i] =
- (struct wlcband *) ((unsigned long)wlc->bandstate[0]
- + (sizeof(struct wlcband)*i));
- }
- }
-
- wlc->corestate = kzalloc(sizeof(struct wlccore), GFP_ATOMIC);
- if (wlc->corestate == NULL) {
- *err = 1026;
- goto fail;
- }
-
- wlc->corestate->macstat_snapshot =
- kzalloc(sizeof(macstat_t), GFP_ATOMIC);
- if (wlc->corestate->macstat_snapshot == NULL) {
- *err = 1027;
- goto fail;
- }
-
- return wlc;
-
- fail:
- wlc_detach_mfree(wlc);
- return NULL;
-}
-
-void wlc_detach_mfree(struct wlc_info *wlc)
-{
- if (wlc == NULL)
- return;
-
- wlc_bsscfg_mfree(wlc->cfg);
- wlc_pub_mfree(wlc->pub);
- kfree(wlc->modulecb);
- kfree(wlc->default_bss);
- kfree(wlc->wsec_def_keys[0]);
- kfree(wlc->protection);
- kfree(wlc->stf);
- kfree(wlc->bandstate[0]);
- kfree(wlc->corestate->macstat_snapshot);
- kfree(wlc->corestate);
- kfree(wlc->hw->bandstate[0]);
- kfree(wlc->hw);
-
- /* free the wlc */
- kfree(wlc);
- wlc = NULL;
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-extern struct wlc_info *wlc_attach_malloc(uint unit, uint *err, uint devid);
-extern void wlc_detach_mfree(struct wlc_info *wlc);
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include <linux/kernel.h>
-#include <net/mac80211.h>
-
-#include <bcmdefs.h>
-#include <brcmu_utils.h>
-#include <aiutils.h>
-#include "bcmdma.h"
-#include <bcmdma.h>
-#include <d11.h>
-
-#include "wlc_types.h"
-#include "wlc_cfg.h"
-#include "wlc_rate.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "wlc_key.h"
-#include "phy/wlc_phy_hal.h"
-#include "wlc_antsel.h"
-#include "wlc_channel.h"
-#include "wlc_main.h"
-#include "wlc_ampdu.h"
-
-#define AMPDU_MAX_MPDU 32 /* max number of mpdus in an ampdu */
-#define AMPDU_NUM_MPDU_LEGACY 16 /* max number of mpdus in an ampdu to a legacy */
-#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
-#define AMPDU_TX_BA_DEF_WSIZE 64 /* default Tx ba window size (in pdu) */
-#define AMPDU_RX_BA_DEF_WSIZE 64 /* max Rx ba window size (in pdu) */
-#define AMPDU_RX_BA_MAX_WSIZE 64 /* default Rx ba window size (in pdu) */
-#define AMPDU_MAX_DUR 5 /* max dur of tx ampdu (in msec) */
-#define AMPDU_DEF_RETRY_LIMIT 5 /* default tx retry limit */
-#define AMPDU_DEF_RR_RETRY_LIMIT 2 /* default tx retry limit at reg rate */
-#define AMPDU_DEF_TXPKT_WEIGHT 2 /* default weight of ampdu in txfifo */
-#define AMPDU_DEF_FFPLD_RSVD 2048 /* default ffpld reserved bytes */
-#define AMPDU_INI_FREE 10 /* # of inis to be freed on detach */
-#define AMPDU_SCB_MAX_RELEASE 20 /* max # of mpdus released at a time */
-
-#define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
-#define FFPLD_TX_MAX_UNFL 200 /* default value of the average number of ampdu
- * without underflows
- */
-#define FFPLD_MPDU_SIZE 1800 /* estimate of maximum mpdu size */
-#define FFPLD_MAX_MCS 23 /* we don't deal with mcs 32 */
-#define FFPLD_PLD_INCR 1000 /* increments in bytes */
-#define FFPLD_MAX_AMPDU_CNT 5000 /* maximum number of ampdu we
- * accumulate between resets.
- */
-
-#define TX_SEQ_TO_INDEX(seq) ((seq) % AMPDU_TX_BA_MAX_WSIZE)
-
-/* max possible overhead per mpdu in the ampdu; 3 is for roundup if needed */
-#define AMPDU_MAX_MPDU_OVERHEAD (FCS_LEN + DOT11_ICV_AES_LEN +\
- AMPDU_DELIMITER_LEN + 3\
- + DOT11_A4_HDR_LEN + DOT11_QOS_LEN + DOT11_IV_MAX_LEN)
-
-/* structure to hold tx fifo information and pre-loading state
- * counters specific to tx underflows of ampdus
- * some counters might be redundant with the ones in wlc or ampdu structures.
- * This allows to maintain a specific state independently of
- * how often and/or when the wlc counters are updated.
- */
-typedef struct wlc_fifo_info {
- u16 ampdu_pld_size; /* number of bytes to be pre-loaded */
- u8 mcs2ampdu_table[FFPLD_MAX_MCS + 1]; /* per-mcs max # of mpdus in an ampdu */
- u16 prev_txfunfl; /* num of underflows last read from the HW macstats counter */
- u32 accum_txfunfl; /* num of underflows since we modified pld params */
- u32 accum_txampdu; /* num of tx ampdu since we modified pld params */
- u32 prev_txampdu; /* previous reading of tx ampdu */
- u32 dmaxferrate; /* estimated dma avg xfer rate in kbits/sec */
-} wlc_fifo_info_t;
-
-/* AMPDU module specific state */
-struct ampdu_info {
- struct wlc_info *wlc; /* pointer to main wlc structure */
- int scb_handle; /* scb cubby handle to retrieve data from scb */
- u8 ini_enable[AMPDU_MAX_SCB_TID]; /* per-tid initiator enable/disable of ampdu */
- u8 ba_tx_wsize; /* Tx ba window size (in pdu) */
- u8 ba_rx_wsize; /* Rx ba window size (in pdu) */
- u8 retry_limit; /* mpdu transmit retry limit */
- u8 rr_retry_limit; /* mpdu transmit retry limit at regular rate */
- u8 retry_limit_tid[AMPDU_MAX_SCB_TID]; /* per-tid mpdu transmit retry limit */
- /* per-tid mpdu transmit retry limit at regular rate */
- u8 rr_retry_limit_tid[AMPDU_MAX_SCB_TID];
- u8 mpdu_density; /* min mpdu spacing (0-7) ==> 2^(x-1)/8 usec */
- s8 max_pdu; /* max pdus allowed in ampdu */
- u8 dur; /* max duration of an ampdu (in msec) */
- u8 txpkt_weight; /* weight of ampdu in txfifo; reduces rate lag */
- u8 rx_factor; /* maximum rx ampdu factor (0-3) ==> 2^(13+x) bytes */
- u32 ffpld_rsvd; /* number of bytes to reserve for preload */
- u32 max_txlen[MCS_TABLE_SIZE][2][2]; /* max size of ampdu per mcs, bw and sgi */
- void *ini_free[AMPDU_INI_FREE]; /* array of ini's to be freed on detach */
- bool mfbr; /* enable multiple fallback rate */
- u32 tx_max_funl; /* underflows should be kept such that
- * (tx_max_funfl*underflows) < tx frames
- */
- wlc_fifo_info_t fifo_tb[NUM_FFPLD_FIFO]; /* table of fifo infos */
-
-};
-
-/* used for flushing ampdu packets */
-struct cb_del_ampdu_pars {
- struct ieee80211_sta *sta;
- u16 tid;
-};
-
-#define AMPDU_CLEANUPFLAG_RX (0x1)
-#define AMPDU_CLEANUPFLAG_TX (0x2)
-
-#define SCB_AMPDU_CUBBY(ampdu, scb) (&(scb->scb_ampdu))
-#define SCB_AMPDU_INI(scb_ampdu, tid) (&(scb_ampdu->ini[tid]))
-
-static void wlc_ffpld_init(struct ampdu_info *ampdu);
-static int wlc_ffpld_check_txfunfl(struct wlc_info *wlc, int f);
-static void wlc_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu, int f);
-
-static scb_ampdu_tid_ini_t *wlc_ampdu_init_tid_ini(struct ampdu_info *ampdu,
- scb_ampdu_t *scb_ampdu,
- u8 tid, bool override);
-static void ampdu_update_max_txlen(struct ampdu_info *ampdu, u8 dur);
-static void scb_ampdu_update_config(struct ampdu_info *ampdu, struct scb *scb);
-static void scb_ampdu_update_config_all(struct ampdu_info *ampdu);
-
-#define wlc_ampdu_txflowcontrol(a, b, c) do {} while (0)
-
-static void wlc_ampdu_dotxstatus_complete(struct ampdu_info *ampdu,
- struct scb *scb,
- struct sk_buff *p, tx_status_t *txs,
- u32 frmtxstatus, u32 frmtxstatus2);
-static bool wlc_ampdu_cap(struct ampdu_info *ampdu);
-static int wlc_ampdu_set(struct ampdu_info *ampdu, bool on);
-
-struct ampdu_info *wlc_ampdu_attach(struct wlc_info *wlc)
-{
- struct ampdu_info *ampdu;
- int i;
-
- ampdu = kzalloc(sizeof(struct ampdu_info), GFP_ATOMIC);
- if (!ampdu) {
- wiphy_err(wlc->wiphy, "wl%d: wlc_ampdu_attach: out of mem\n",
- wlc->pub->unit);
- return NULL;
- }
- ampdu->wlc = wlc;
-
- for (i = 0; i < AMPDU_MAX_SCB_TID; i++)
- ampdu->ini_enable[i] = true;
- /* Disable ampdu for VO by default */
- ampdu->ini_enable[PRIO_8021D_VO] = false;
- ampdu->ini_enable[PRIO_8021D_NC] = false;
-
- /* Disable ampdu for BK by default since not enough fifo space */
- ampdu->ini_enable[PRIO_8021D_NONE] = false;
- ampdu->ini_enable[PRIO_8021D_BK] = false;
-
- ampdu->ba_tx_wsize = AMPDU_TX_BA_DEF_WSIZE;
- ampdu->ba_rx_wsize = AMPDU_RX_BA_DEF_WSIZE;
- ampdu->mpdu_density = AMPDU_DEF_MPDU_DENSITY;
- ampdu->max_pdu = AUTO;
- ampdu->dur = AMPDU_MAX_DUR;
- ampdu->txpkt_weight = AMPDU_DEF_TXPKT_WEIGHT;
-
- ampdu->ffpld_rsvd = AMPDU_DEF_FFPLD_RSVD;
- /* bump max ampdu rcv size to 64k for all 11n devices except 4321A0 and 4321A1 */
- if (WLCISNPHY(wlc->band) && NREV_LT(wlc->band->phyrev, 2))
- ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_32K;
- else
- ampdu->rx_factor = IEEE80211_HT_MAX_AMPDU_64K;
- ampdu->retry_limit = AMPDU_DEF_RETRY_LIMIT;
- ampdu->rr_retry_limit = AMPDU_DEF_RR_RETRY_LIMIT;
-
- for (i = 0; i < AMPDU_MAX_SCB_TID; i++) {
- ampdu->retry_limit_tid[i] = ampdu->retry_limit;
- ampdu->rr_retry_limit_tid[i] = ampdu->rr_retry_limit;
- }
-
- ampdu_update_max_txlen(ampdu, ampdu->dur);
- ampdu->mfbr = false;
- /* try to set ampdu to the default value */
- wlc_ampdu_set(ampdu, wlc->pub->_ampdu);
-
- ampdu->tx_max_funl = FFPLD_TX_MAX_UNFL;
- wlc_ffpld_init(ampdu);
-
- return ampdu;
-}
-
-void wlc_ampdu_detach(struct ampdu_info *ampdu)
-{
- int i;
-
- if (!ampdu)
- return;
-
- /* free all ini's which were to be freed on callbacks which were never called */
- for (i = 0; i < AMPDU_INI_FREE; i++) {
- kfree(ampdu->ini_free[i]);
- }
-
- wlc_module_unregister(ampdu->wlc->pub, "ampdu", ampdu);
- kfree(ampdu);
-}
-
-static void scb_ampdu_update_config(struct ampdu_info *ampdu, struct scb *scb)
-{
- scb_ampdu_t *scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- int i;
-
- scb_ampdu->max_pdu = (u8) ampdu->wlc->pub->tunables->ampdunummpdu;
-
- /* go back to legacy size if some preloading is occurring */
- for (i = 0; i < NUM_FFPLD_FIFO; i++) {
- if (ampdu->fifo_tb[i].ampdu_pld_size > FFPLD_PLD_INCR)
- scb_ampdu->max_pdu = AMPDU_NUM_MPDU_LEGACY;
- }
-
- /* apply user override */
- if (ampdu->max_pdu != AUTO)
- scb_ampdu->max_pdu = (u8) ampdu->max_pdu;
-
- scb_ampdu->release = min_t(u8, scb_ampdu->max_pdu, AMPDU_SCB_MAX_RELEASE);
-
- if (scb_ampdu->max_rxlen)
- scb_ampdu->release =
- min_t(u8, scb_ampdu->release, scb_ampdu->max_rxlen / 1600);
-
- scb_ampdu->release = min(scb_ampdu->release,
- ampdu->fifo_tb[TX_AC_BE_FIFO].
- mcs2ampdu_table[FFPLD_MAX_MCS]);
-}
-
-static void scb_ampdu_update_config_all(struct ampdu_info *ampdu)
-{
- scb_ampdu_update_config(ampdu, ampdu->wlc->pub->global_scb);
-}
-
-static void wlc_ffpld_init(struct ampdu_info *ampdu)
-{
- int i, j;
- wlc_fifo_info_t *fifo;
-
- for (j = 0; j < NUM_FFPLD_FIFO; j++) {
- fifo = (ampdu->fifo_tb + j);
- fifo->ampdu_pld_size = 0;
- for (i = 0; i <= FFPLD_MAX_MCS; i++)
- fifo->mcs2ampdu_table[i] = 255;
- fifo->dmaxferrate = 0;
- fifo->accum_txampdu = 0;
- fifo->prev_txfunfl = 0;
- fifo->accum_txfunfl = 0;
-
- }
-}
-
-/* evaluate the dma transfer rate using the tx underflows as feedback.
- * If necessary, increase tx fifo preloading. If not enough,
- * decrease maximum ampdu size for each mcs till underflows stop
- * Return 1 if pre-loading not active, -1 if not an underflow event,
- * 0 if pre-loading module took care of the event.
- */
-static int wlc_ffpld_check_txfunfl(struct wlc_info *wlc, int fid)
-{
- struct ampdu_info *ampdu = wlc->ampdu;
- u32 phy_rate = MCS_RATE(FFPLD_MAX_MCS, true, false);
- u32 txunfl_ratio;
- u8 max_mpdu;
- u32 current_ampdu_cnt = 0;
- u16 max_pld_size;
- u32 new_txunfl;
- wlc_fifo_info_t *fifo = (ampdu->fifo_tb + fid);
- uint xmtfifo_sz;
- u16 cur_txunfl;
-
- /* return if we got here for a different reason than underflows */
- cur_txunfl =
- wlc_read_shm(wlc,
- M_UCODE_MACSTAT + offsetof(macstat_t, txfunfl[fid]));
- new_txunfl = (u16) (cur_txunfl - fifo->prev_txfunfl);
- if (new_txunfl == 0) {
- BCMMSG(wlc->wiphy, "TX status FRAG set but no tx underflows\n");
- return -1;
- }
- fifo->prev_txfunfl = cur_txunfl;
-
- if (!ampdu->tx_max_funl)
- return 1;
-
- /* check if fifo is big enough */
- if (wlc_xmtfifo_sz_get(wlc, fid, &xmtfifo_sz)) {
- return -1;
- }
-
- if ((TXFIFO_SIZE_UNIT * (u32) xmtfifo_sz) <= ampdu->ffpld_rsvd)
- return 1;
-
- max_pld_size = TXFIFO_SIZE_UNIT * xmtfifo_sz - ampdu->ffpld_rsvd;
- fifo->accum_txfunfl += new_txunfl;
-
- /* we need to wait for at least 10 underflows */
- if (fifo->accum_txfunfl < 10)
- return 0;
-
- BCMMSG(wlc->wiphy, "ampdu_count %d tx_underflows %d\n",
- current_ampdu_cnt, fifo->accum_txfunfl);
-
- /*
- compute the current ratio of tx unfl per ampdu.
- When the current ampdu count becomes too
- big while the ratio remains small, we reset
- the current count in order to not
- introduce too big of a latency in detecting a
- large amount of tx underflows later.
- */
-
- txunfl_ratio = current_ampdu_cnt / fifo->accum_txfunfl;
-
- if (txunfl_ratio > ampdu->tx_max_funl) {
- if (current_ampdu_cnt >= FFPLD_MAX_AMPDU_CNT) {
- fifo->accum_txfunfl = 0;
- }
- return 0;
- }
- max_mpdu =
- min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS], AMPDU_NUM_MPDU_LEGACY);
-
- /* In case max value max_pdu is already lower than
- the fifo depth, there is nothing more we can do.
- */
-
- if (fifo->ampdu_pld_size >= max_mpdu * FFPLD_MPDU_SIZE) {
- fifo->accum_txfunfl = 0;
- return 0;
- }
-
- if (fifo->ampdu_pld_size < max_pld_size) {
-
- /* increment by TX_FIFO_PLD_INC bytes */
- fifo->ampdu_pld_size += FFPLD_PLD_INCR;
- if (fifo->ampdu_pld_size > max_pld_size)
- fifo->ampdu_pld_size = max_pld_size;
-
- /* update scb release size */
- scb_ampdu_update_config_all(ampdu);
-
- /*
- compute a new dma xfer rate for max_mpdu @ max mcs.
- This is the minimum dma rate that
- can achieve no underflow condition for the current mpdu size.
- */
- /* note : we divide/multiply by 100 to avoid integer overflows */
- fifo->dmaxferrate =
- (((phy_rate / 100) *
- (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
- / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
-
- BCMMSG(wlc->wiphy, "DMA estimated transfer rate %d; "
- "pre-load size %d\n",
- fifo->dmaxferrate, fifo->ampdu_pld_size);
- } else {
-
- /* decrease ampdu size */
- if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] > 1) {
- if (fifo->mcs2ampdu_table[FFPLD_MAX_MCS] == 255)
- fifo->mcs2ampdu_table[FFPLD_MAX_MCS] =
- AMPDU_NUM_MPDU_LEGACY - 1;
- else
- fifo->mcs2ampdu_table[FFPLD_MAX_MCS] -= 1;
-
- /* recompute the table */
- wlc_ffpld_calc_mcs2ampdu_table(ampdu, fid);
-
- /* update scb release size */
- scb_ampdu_update_config_all(ampdu);
- }
- }
- fifo->accum_txfunfl = 0;
- return 0;
-}
-
-static void wlc_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu, int f)
-{
- int i;
- u32 phy_rate, dma_rate, tmp;
- u8 max_mpdu;
- wlc_fifo_info_t *fifo = (ampdu->fifo_tb + f);
-
- /* recompute the dma rate */
- /* note : we divide/multiply by 100 to avoid integer overflows */
- max_mpdu =
- min_t(u8, fifo->mcs2ampdu_table[FFPLD_MAX_MCS], AMPDU_NUM_MPDU_LEGACY);
- phy_rate = MCS_RATE(FFPLD_MAX_MCS, true, false);
- dma_rate =
- (((phy_rate / 100) *
- (max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
- / (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
- fifo->dmaxferrate = dma_rate;
-
- /* fill up the mcs2ampdu table; do not recalc the last mcs */
- dma_rate = dma_rate >> 7;
- for (i = 0; i < FFPLD_MAX_MCS; i++) {
- /* shifting to keep it within integer range */
- phy_rate = MCS_RATE(i, true, false) >> 7;
- if (phy_rate > dma_rate) {
- tmp = ((fifo->ampdu_pld_size * phy_rate) /
- ((phy_rate - dma_rate) * FFPLD_MPDU_SIZE)) + 1;
- tmp = min_t(u32, tmp, 255);
- fifo->mcs2ampdu_table[i] = (u8) tmp;
- }
- }
-}
-
-static void
-wlc_ampdu_agg(struct ampdu_info *ampdu, struct scb *scb, struct sk_buff *p,
- uint prec)
-{
- scb_ampdu_t *scb_ampdu;
- scb_ampdu_tid_ini_t *ini;
- u8 tid = (u8) (p->priority);
-
- scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
-
- /* initialize initiator on first packet; sends addba req */
- ini = SCB_AMPDU_INI(scb_ampdu, tid);
- if (ini->magic != INI_MAGIC) {
- ini = wlc_ampdu_init_tid_ini(ampdu, scb_ampdu, tid, false);
- }
- return;
-}
-
-int
-wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
- struct sk_buff **pdu, int prec)
-{
- struct wlc_info *wlc;
- struct sk_buff *p, *pkt[AMPDU_MAX_MPDU];
- u8 tid, ndelim;
- int err = 0;
- u8 preamble_type = WLC_GF_PREAMBLE;
- u8 fbr_preamble_type = WLC_GF_PREAMBLE;
- u8 rts_preamble_type = WLC_LONG_PREAMBLE;
- u8 rts_fbr_preamble_type = WLC_LONG_PREAMBLE;
-
- bool rr = true, fbr = false;
- uint i, count = 0, fifo, seg_cnt = 0;
- u16 plen, len, seq = 0, mcl, mch, index, frameid, dma_len = 0;
- u32 ampdu_len, maxlen = 0;
- d11txh_t *txh = NULL;
- u8 *plcp;
- struct ieee80211_hdr *h;
- struct scb *scb;
- scb_ampdu_t *scb_ampdu;
- scb_ampdu_tid_ini_t *ini;
- u8 mcs = 0;
- bool use_rts = false, use_cts = false;
- ratespec_t rspec = 0, rspec_fallback = 0;
- ratespec_t rts_rspec = 0, rts_rspec_fallback = 0;
- u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
- struct ieee80211_rts *rts;
- u8 rr_retry_limit;
- wlc_fifo_info_t *f;
- bool fbr_iscck;
- struct ieee80211_tx_info *tx_info;
- u16 qlen;
- struct wiphy *wiphy;
-
- wlc = ampdu->wlc;
- wiphy = wlc->wiphy;
- p = *pdu;
-
- tid = (u8) (p->priority);
-
- f = ampdu->fifo_tb + prio2fifo[tid];
-
- scb = wlc->pub->global_scb;
- scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- ini = &scb_ampdu->ini[tid];
-
- /* Let pressure continue to build ... */
- qlen = pktq_plen(&qi->q, prec);
- if (ini->tx_in_transit > 0 && qlen < scb_ampdu->max_pdu) {
- return -EBUSY;
- }
-
- wlc_ampdu_agg(ampdu, scb, p, tid);
-
- rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
- ampdu_len = 0;
- dma_len = 0;
- while (p) {
- struct ieee80211_tx_rate *txrate;
-
- tx_info = IEEE80211_SKB_CB(p);
- txrate = tx_info->status.rates;
-
- if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
- err = wlc_prep_pdu(wlc, p, &fifo);
- } else {
- wiphy_err(wiphy, "%s: AMPDU flag is off!\n", __func__);
- *pdu = NULL;
- err = 0;
- break;
- }
-
- if (err) {
- if (err == -EBUSY) {
- wiphy_err(wiphy, "wl%d: wlc_sendampdu: "
- "prep_xdu retry; seq 0x%x\n",
- wlc->pub->unit, seq);
- *pdu = p;
- break;
- }
-
- /* error in the packet; reject it */
- wiphy_err(wiphy, "wl%d: wlc_sendampdu: prep_xdu "
- "rejected; seq 0x%x\n", wlc->pub->unit, seq);
- *pdu = NULL;
- break;
- }
-
- /* pkt is good to be aggregated */
- txh = (d11txh_t *) p->data;
- plcp = (u8 *) (txh + 1);
- h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
- seq = le16_to_cpu(h->seq_ctrl) >> SEQNUM_SHIFT;
- index = TX_SEQ_TO_INDEX(seq);
-
- /* check mcl fields and test whether it can be agg'd */
- mcl = le16_to_cpu(txh->MacTxControlLow);
- mcl &= ~TXC_AMPDU_MASK;
- fbr_iscck = !(le16_to_cpu(txh->XtraFrameTypes) & 0x3);
- txh->PreloadSize = 0; /* always default to 0 */
-
- /* Handle retry limits */
- if (txrate[0].count <= rr_retry_limit) {
- txrate[0].count++;
- rr = true;
- fbr = false;
- } else {
- fbr = true;
- rr = false;
- txrate[1].count++;
- }
-
- /* extract the length info */
- len = fbr_iscck ? WLC_GET_CCK_PLCP_LEN(txh->FragPLCPFallback)
- : WLC_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
-
- /* retrieve null delimiter count */
- ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
- seg_cnt += 1;
-
- BCMMSG(wlc->wiphy, "wl%d: mpdu %d plcp_len %d\n",
- wlc->pub->unit, count, len);
-
- /*
- * aggregateable mpdu. For ucode/hw agg,
- * test whether need to break or change the epoch
- */
- if (count == 0) {
- mcl |= (TXC_AMPDU_FIRST << TXC_AMPDU_SHIFT);
- /* refill the bits since might be a retx mpdu */
- mcl |= TXC_STARTMSDU;
- rts = (struct ieee80211_rts *)&txh->rts_frame;
-
- if (ieee80211_is_rts(rts->frame_control)) {
- mcl |= TXC_SENDRTS;
- use_rts = true;
- }
- if (ieee80211_is_cts(rts->frame_control)) {
- mcl |= TXC_SENDCTS;
- use_cts = true;
- }
- } else {
- mcl |= (TXC_AMPDU_MIDDLE << TXC_AMPDU_SHIFT);
- mcl &= ~(TXC_STARTMSDU | TXC_SENDRTS | TXC_SENDCTS);
- }
-
- len = roundup(len, 4);
- ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN);
-
- dma_len += (u16) brcmu_pkttotlen(p);
-
- BCMMSG(wlc->wiphy, "wl%d: ampdu_len %d"
- " seg_cnt %d null delim %d\n",
- wlc->pub->unit, ampdu_len, seg_cnt, ndelim);
-
- txh->MacTxControlLow = cpu_to_le16(mcl);
-
- /* this packet is added */
- pkt[count++] = p;
-
- /* patch the first MPDU */
- if (count == 1) {
- u8 plcp0, plcp3, is40, sgi;
- struct ieee80211_sta *sta;
-
- sta = tx_info->control.sta;
-
- if (rr) {
- plcp0 = plcp[0];
- plcp3 = plcp[3];
- } else {
- plcp0 = txh->FragPLCPFallback[0];
- plcp3 = txh->FragPLCPFallback[3];
-
- }
- is40 = (plcp0 & MIMO_PLCP_40MHZ) ? 1 : 0;
- sgi = PLCP3_ISSGI(plcp3) ? 1 : 0;
- mcs = plcp0 & ~MIMO_PLCP_40MHZ;
- maxlen =
- min(scb_ampdu->max_rxlen,
- ampdu->max_txlen[mcs][is40][sgi]);
-
- /* XXX Fix me to honor real max_rxlen */
- /* can fix this as soon as ampdu_action() in mac80211.h
- * gets extra u8buf_size par */
- maxlen = 64 * 1024;
-
- if (is40)
- mimo_ctlchbw =
- CHSPEC_SB_UPPER(WLC_BAND_PI_RADIO_CHANSPEC)
- ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
-
- /* rebuild the rspec and rspec_fallback */
- rspec = RSPEC_MIMORATE;
- rspec |= plcp[0] & ~MIMO_PLCP_40MHZ;
- if (plcp[0] & MIMO_PLCP_40MHZ)
- rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
-
- if (fbr_iscck) /* CCK */
- rspec_fallback =
- CCK_RSPEC(CCK_PHY2MAC_RATE
- (txh->FragPLCPFallback[0]));
- else { /* MIMO */
- rspec_fallback = RSPEC_MIMORATE;
- rspec_fallback |=
- txh->FragPLCPFallback[0] & ~MIMO_PLCP_40MHZ;
- if (txh->FragPLCPFallback[0] & MIMO_PLCP_40MHZ)
- rspec_fallback |=
- (PHY_TXC1_BW_40MHZ <<
- RSPEC_BW_SHIFT);
- }
-
- if (use_rts || use_cts) {
- rts_rspec =
- wlc_rspec_to_rts_rspec(wlc, rspec, false,
- mimo_ctlchbw);
- rts_rspec_fallback =
- wlc_rspec_to_rts_rspec(wlc, rspec_fallback,
- false, mimo_ctlchbw);
- }
- }
-
- /* if (first mpdu for host agg) */
- /* test whether to add more */
- if ((MCS_RATE(mcs, true, false) >= f->dmaxferrate) &&
- (count == f->mcs2ampdu_table[mcs])) {
- BCMMSG(wlc->wiphy, "wl%d: PR 37644: stopping"
- " ampdu at %d for mcs %d\n",
- wlc->pub->unit, count, mcs);
- break;
- }
-
- if (count == scb_ampdu->max_pdu) {
- break;
- }
-
- /* check to see if the next pkt is a candidate for aggregation */
- p = pktq_ppeek(&qi->q, prec);
- tx_info = IEEE80211_SKB_CB(p); /* tx_info must be checked with current p */
-
- if (p) {
- if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
- ((u8) (p->priority) == tid)) {
-
- plen = brcmu_pkttotlen(p) +
- AMPDU_MAX_MPDU_OVERHEAD;
- plen = max(scb_ampdu->min_len, plen);
-
- if ((plen + ampdu_len) > maxlen) {
- p = NULL;
- wiphy_err(wiphy, "%s: Bogus plen #1\n",
- __func__);
- continue;
- }
-
- /* check if there are enough descriptors available */
- if (TXAVAIL(wlc, fifo) <= (seg_cnt + 1)) {
- wiphy_err(wiphy, "%s: No fifo space "
- "!!\n", __func__);
- p = NULL;
- continue;
- }
- p = brcmu_pktq_pdeq(&qi->q, prec);
- } else {
- p = NULL;
- }
- }
- } /* end while(p) */
-
- ini->tx_in_transit += count;
-
- if (count) {
- /* patch up the last txh */
- txh = (d11txh_t *) pkt[count - 1]->data;
- mcl = le16_to_cpu(txh->MacTxControlLow);
- mcl &= ~TXC_AMPDU_MASK;
- mcl |= (TXC_AMPDU_LAST << TXC_AMPDU_SHIFT);
- txh->MacTxControlLow = cpu_to_le16(mcl);
-
- /* remove the null delimiter after last mpdu */
- ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
- txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] = 0;
- ampdu_len -= ndelim * AMPDU_DELIMITER_LEN;
-
- /* remove the pad len from last mpdu */
- fbr_iscck = ((le16_to_cpu(txh->XtraFrameTypes) & 0x3) == 0);
- len = fbr_iscck ? WLC_GET_CCK_PLCP_LEN(txh->FragPLCPFallback)
- : WLC_GET_MIMO_PLCP_LEN(txh->FragPLCPFallback);
- ampdu_len -= roundup(len, 4) - len;
-
- /* patch up the first txh & plcp */
- txh = (d11txh_t *) pkt[0]->data;
- plcp = (u8 *) (txh + 1);
-
- WLC_SET_MIMO_PLCP_LEN(plcp, ampdu_len);
- /* mark plcp to indicate ampdu */
- WLC_SET_MIMO_PLCP_AMPDU(plcp);
-
- /* reset the mixed mode header durations */
- if (txh->MModeLen) {
- u16 mmodelen =
- wlc_calc_lsig_len(wlc, rspec, ampdu_len);
- txh->MModeLen = cpu_to_le16(mmodelen);
- preamble_type = WLC_MM_PREAMBLE;
- }
- if (txh->MModeFbrLen) {
- u16 mmfbrlen =
- wlc_calc_lsig_len(wlc, rspec_fallback, ampdu_len);
- txh->MModeFbrLen = cpu_to_le16(mmfbrlen);
- fbr_preamble_type = WLC_MM_PREAMBLE;
- }
-
- /* set the preload length */
- if (MCS_RATE(mcs, true, false) >= f->dmaxferrate) {
- dma_len = min(dma_len, f->ampdu_pld_size);
- txh->PreloadSize = cpu_to_le16(dma_len);
- } else
- txh->PreloadSize = 0;
-
- mch = le16_to_cpu(txh->MacTxControlHigh);
-
- /* update RTS dur fields */
- if (use_rts || use_cts) {
- u16 durid;
- rts = (struct ieee80211_rts *)&txh->rts_frame;
- if ((mch & TXC_PREAMBLE_RTS_MAIN_SHORT) ==
- TXC_PREAMBLE_RTS_MAIN_SHORT)
- rts_preamble_type = WLC_SHORT_PREAMBLE;
-
- if ((mch & TXC_PREAMBLE_RTS_FB_SHORT) ==
- TXC_PREAMBLE_RTS_FB_SHORT)
- rts_fbr_preamble_type = WLC_SHORT_PREAMBLE;
-
- durid =
- wlc_compute_rtscts_dur(wlc, use_cts, rts_rspec,
- rspec, rts_preamble_type,
- preamble_type, ampdu_len,
- true);
- rts->duration = cpu_to_le16(durid);
- durid = wlc_compute_rtscts_dur(wlc, use_cts,
- rts_rspec_fallback,
- rspec_fallback,
- rts_fbr_preamble_type,
- fbr_preamble_type,
- ampdu_len, true);
- txh->RTSDurFallback = cpu_to_le16(durid);
- /* set TxFesTimeNormal */
- txh->TxFesTimeNormal = rts->duration;
- /* set fallback rate version of TxFesTimeNormal */
- txh->TxFesTimeFallback = txh->RTSDurFallback;
- }
-
- /* set flag and plcp for fallback rate */
- if (fbr) {
- mch |= TXC_AMPDU_FBR;
- txh->MacTxControlHigh = cpu_to_le16(mch);
- WLC_SET_MIMO_PLCP_AMPDU(plcp);
- WLC_SET_MIMO_PLCP_AMPDU(txh->FragPLCPFallback);
- }
-
- BCMMSG(wlc->wiphy, "wl%d: count %d ampdu_len %d\n",
- wlc->pub->unit, count, ampdu_len);
-
- /* inform rate_sel if it this is a rate probe pkt */
- frameid = le16_to_cpu(txh->TxFrameID);
- if (frameid & TXFID_RATE_PROBE_MASK) {
- wiphy_err(wiphy, "%s: XXX what to do with "
- "TXFID_RATE_PROBE_MASK!?\n", __func__);
- }
- for (i = 0; i < count; i++)
- wlc_txfifo(wlc, fifo, pkt[i], i == (count - 1),
- ampdu->txpkt_weight);
-
- }
- /* endif (count) */
- return err;
-}
-
-void
-wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
- struct sk_buff *p, tx_status_t *txs)
-{
- scb_ampdu_t *scb_ampdu;
- struct wlc_info *wlc = ampdu->wlc;
- scb_ampdu_tid_ini_t *ini;
- u32 s1 = 0, s2 = 0;
- struct ieee80211_tx_info *tx_info;
-
- tx_info = IEEE80211_SKB_CB(p);
-
- /* BMAC_NOTE: For the split driver, second level txstatus comes later
- * So if the ACK was received then wait for the second level else just
- * call the first one
- */
- if (txs->status & TX_STATUS_ACK_RCV) {
- u8 status_delay = 0;
-
- /* wait till the next 8 bytes of txstatus is available */
- while (((s1 = R_REG(&wlc->regs->frmtxstatus)) & TXS_V) == 0) {
- udelay(1);
- status_delay++;
- if (status_delay > 10) {
- return; /* error condition */
- }
- }
-
- s2 = R_REG(&wlc->regs->frmtxstatus2);
- }
-
- if (likely(scb)) {
- scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- ini = SCB_AMPDU_INI(scb_ampdu, p->priority);
- wlc_ampdu_dotxstatus_complete(ampdu, scb, p, txs, s1, s2);
- } else {
- /* loop through all pkts and free */
- u8 queue = txs->frameid & TXFID_QUEUE_MASK;
- d11txh_t *txh;
- u16 mcl;
- while (p) {
- tx_info = IEEE80211_SKB_CB(p);
- txh = (d11txh_t *) p->data;
- mcl = le16_to_cpu(txh->MacTxControlLow);
- brcmu_pkt_buf_free_skb(p);
- /* break out if last packet of ampdu */
- if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
- TXC_AMPDU_LAST)
- break;
- p = GETNEXTTXP(wlc, queue);
- }
- wlc_txfifo_complete(wlc, queue, ampdu->txpkt_weight);
- }
- wlc_ampdu_txflowcontrol(wlc, scb_ampdu, ini);
-}
-
-static void
-rate_status(struct wlc_info *wlc, struct ieee80211_tx_info *tx_info,
- tx_status_t *txs, u8 mcs)
-{
- struct ieee80211_tx_rate *txrate = tx_info->status.rates;
- int i;
-
- /* clear the rest of the rates */
- for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
- txrate[i].idx = -1;
- txrate[i].count = 0;
- }
-}
-
-#define SHORTNAME "AMPDU status"
-
-static void
-wlc_ampdu_dotxstatus_complete(struct ampdu_info *ampdu, struct scb *scb,
- struct sk_buff *p, tx_status_t *txs,
- u32 s1, u32 s2)
-{
- scb_ampdu_t *scb_ampdu;
- struct wlc_info *wlc = ampdu->wlc;
- scb_ampdu_tid_ini_t *ini;
- u8 bitmap[8], queue, tid;
- d11txh_t *txh;
- u8 *plcp;
- struct ieee80211_hdr *h;
- u16 seq, start_seq = 0, bindex, index, mcl;
- u8 mcs = 0;
- bool ba_recd = false, ack_recd = false;
- u8 suc_mpdu = 0, tot_mpdu = 0;
- uint supr_status;
- bool update_rate = true, retry = true, tx_error = false;
- u16 mimoantsel = 0;
- u8 antselid = 0;
- u8 retry_limit, rr_retry_limit;
- struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
- struct wiphy *wiphy = wlc->wiphy;
-
-#ifdef BCMDBG
- u8 hole[AMPDU_MAX_MPDU];
- memset(hole, 0, sizeof(hole));
-#endif
-
- scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- tid = (u8) (p->priority);
-
- ini = SCB_AMPDU_INI(scb_ampdu, tid);
- retry_limit = ampdu->retry_limit_tid[tid];
- rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
- memset(bitmap, 0, sizeof(bitmap));
- queue = txs->frameid & TXFID_QUEUE_MASK;
- supr_status = txs->status & TX_STATUS_SUPR_MASK;
-
- if (txs->status & TX_STATUS_ACK_RCV) {
- if (TX_STATUS_SUPR_UF == supr_status) {
- update_rate = false;
- }
-
- WARN_ON(!(txs->status & TX_STATUS_INTERMEDIATE));
- start_seq = txs->sequence >> SEQNUM_SHIFT;
- bitmap[0] = (txs->status & TX_STATUS_BA_BMAP03_MASK) >>
- TX_STATUS_BA_BMAP03_SHIFT;
-
- WARN_ON(s1 & TX_STATUS_INTERMEDIATE);
- WARN_ON(!(s1 & TX_STATUS_AMPDU));
-
- bitmap[0] |=
- (s1 & TX_STATUS_BA_BMAP47_MASK) <<
- TX_STATUS_BA_BMAP47_SHIFT;
- bitmap[1] = (s1 >> 8) & 0xff;
- bitmap[2] = (s1 >> 16) & 0xff;
- bitmap[3] = (s1 >> 24) & 0xff;
-
- bitmap[4] = s2 & 0xff;
- bitmap[5] = (s2 >> 8) & 0xff;
- bitmap[6] = (s2 >> 16) & 0xff;
- bitmap[7] = (s2 >> 24) & 0xff;
-
- ba_recd = true;
- } else {
- if (supr_status) {
- update_rate = false;
- if (supr_status == TX_STATUS_SUPR_BADCH) {
- wiphy_err(wiphy, "%s: Pkt tx suppressed, "
- "illegal channel possibly %d\n",
- __func__, CHSPEC_CHANNEL(
- wlc->default_bss->chanspec));
- } else {
- if (supr_status != TX_STATUS_SUPR_FRAG)
- wiphy_err(wiphy, "%s: wlc_ampdu_dotx"
- "status:supr_status 0x%x\n",
- __func__, supr_status);
- }
- /* no need to retry for badch; will fail again */
- if (supr_status == TX_STATUS_SUPR_BADCH ||
- supr_status == TX_STATUS_SUPR_EXPTIME) {
- retry = false;
- } else if (supr_status == TX_STATUS_SUPR_EXPTIME) {
- /* TX underflow : try tuning pre-loading or ampdu size */
- } else if (supr_status == TX_STATUS_SUPR_FRAG) {
- /* if there were underflows, but pre-loading is not active,
- notify rate adaptation.
- */
- if (wlc_ffpld_check_txfunfl(wlc, prio2fifo[tid])
- > 0) {
- tx_error = true;
- }
- }
- } else if (txs->phyerr) {
- update_rate = false;
- wiphy_err(wiphy, "wl%d: wlc_ampdu_dotxstatus: tx phy "
- "error (0x%x)\n", wlc->pub->unit,
- txs->phyerr);
-
- if (WL_ERROR_ON()) {
- brcmu_prpkt("txpkt (AMPDU)", p);
- wlc_print_txdesc((d11txh_t *) p->data);
- }
- wlc_print_txstatus(txs);
- }
- }
-
- /* loop through all pkts and retry if not acked */
- while (p) {
- tx_info = IEEE80211_SKB_CB(p);
- txh = (d11txh_t *) p->data;
- mcl = le16_to_cpu(txh->MacTxControlLow);
- plcp = (u8 *) (txh + 1);
- h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
- seq = le16_to_cpu(h->seq_ctrl) >> SEQNUM_SHIFT;
-
- if (tot_mpdu == 0) {
- mcs = plcp[0] & MIMO_PLCP_MCS_MASK;
- mimoantsel = le16_to_cpu(txh->ABI_MimoAntSel);
- }
-
- index = TX_SEQ_TO_INDEX(seq);
- ack_recd = false;
- if (ba_recd) {
- bindex = MODSUB_POW2(seq, start_seq, SEQNUM_MAX);
- BCMMSG(wlc->wiphy, "tid %d seq %d,"
- " start_seq %d, bindex %d set %d, index %d\n",
- tid, seq, start_seq, bindex,
- isset(bitmap, bindex), index);
- /* if acked then clear bit and free packet */
- if ((bindex < AMPDU_TX_BA_MAX_WSIZE)
- && isset(bitmap, bindex)) {
- ini->tx_in_transit--;
- ini->txretry[index] = 0;
-
- /* ampdu_ack_len: number of acked aggregated frames */
- /* ampdu_len: number of aggregated frames */
- rate_status(wlc, tx_info, txs, mcs);
- tx_info->flags |= IEEE80211_TX_STAT_ACK;
- tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
- tx_info->status.ampdu_ack_len =
- tx_info->status.ampdu_len = 1;
-
- skb_pull(p, D11_PHY_HDR_LEN);
- skb_pull(p, D11_TXH_LEN);
-
- ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
- p);
- ack_recd = true;
- suc_mpdu++;
- }
- }
- /* either retransmit or send bar if ack not recd */
- if (!ack_recd) {
- struct ieee80211_tx_rate *txrate =
- tx_info->status.rates;
- if (retry && (txrate[0].count < (int)retry_limit)) {
- ini->txretry[index]++;
- ini->tx_in_transit--;
- /* Use high prededence for retransmit to give some punch */
- /* wlc_txq_enq(wlc, scb, p, WLC_PRIO_TO_PREC(tid)); */
- wlc_txq_enq(wlc, scb, p,
- WLC_PRIO_TO_HI_PREC(tid));
- } else {
- /* Retry timeout */
- ini->tx_in_transit--;
- ieee80211_tx_info_clear_status(tx_info);
- tx_info->status.ampdu_ack_len = 0;
- tx_info->status.ampdu_len = 1;
- tx_info->flags |=
- IEEE80211_TX_STAT_AMPDU_NO_BACK;
- skb_pull(p, D11_PHY_HDR_LEN);
- skb_pull(p, D11_TXH_LEN);
- wiphy_err(wiphy, "%s: BA Timeout, seq %d, in_"
- "transit %d\n", SHORTNAME, seq,
- ini->tx_in_transit);
- ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
- p);
- }
- }
- tot_mpdu++;
-
- /* break out if last packet of ampdu */
- if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
- TXC_AMPDU_LAST)
- break;
-
- p = GETNEXTTXP(wlc, queue);
- }
- wlc_send_q(wlc);
-
- /* update rate state */
- antselid = wlc_antsel_antsel2id(wlc->asi, mimoantsel);
-
- wlc_txfifo_complete(wlc, queue, ampdu->txpkt_weight);
-}
-
-/* initialize the initiator code for tid */
-static scb_ampdu_tid_ini_t *wlc_ampdu_init_tid_ini(struct ampdu_info *ampdu,
- scb_ampdu_t *scb_ampdu,
- u8 tid, bool override)
-{
- scb_ampdu_tid_ini_t *ini;
-
- /* check for per-tid control of ampdu */
- if (!ampdu->ini_enable[tid]) {
- wiphy_err(ampdu->wlc->wiphy, "%s: Rejecting tid %d\n",
- __func__, tid);
- return NULL;
- }
-
- ini = SCB_AMPDU_INI(scb_ampdu, tid);
- ini->tid = tid;
- ini->scb = scb_ampdu->scb;
- ini->magic = INI_MAGIC;
- return ini;
-}
-
-static int wlc_ampdu_set(struct ampdu_info *ampdu, bool on)
-{
- struct wlc_info *wlc = ampdu->wlc;
-
- wlc->pub->_ampdu = false;
-
- if (on) {
- if (!N_ENAB(wlc->pub)) {
- wiphy_err(ampdu->wlc->wiphy, "wl%d: driver not "
- "nmode enabled\n", wlc->pub->unit);
- return -ENOTSUPP;
- }
- if (!wlc_ampdu_cap(ampdu)) {
- wiphy_err(ampdu->wlc->wiphy, "wl%d: device not "
- "ampdu capable\n", wlc->pub->unit);
- return -ENOTSUPP;
- }
- wlc->pub->_ampdu = on;
- }
-
- return 0;
-}
-
-static bool wlc_ampdu_cap(struct ampdu_info *ampdu)
-{
- if (WLC_PHY_11N_CAP(ampdu->wlc->band))
- return true;
- else
- return false;
-}
-
-static void ampdu_update_max_txlen(struct ampdu_info *ampdu, u8 dur)
-{
- u32 rate, mcs;
-
- for (mcs = 0; mcs < MCS_TABLE_SIZE; mcs++) {
- /* rate is in Kbps; dur is in msec ==> len = (rate * dur) / 8 */
- /* 20MHz, No SGI */
- rate = MCS_RATE(mcs, false, false);
- ampdu->max_txlen[mcs][0][0] = (rate * dur) >> 3;
- /* 40 MHz, No SGI */
- rate = MCS_RATE(mcs, true, false);
- ampdu->max_txlen[mcs][1][0] = (rate * dur) >> 3;
- /* 20MHz, SGI */
- rate = MCS_RATE(mcs, false, true);
- ampdu->max_txlen[mcs][0][1] = (rate * dur) >> 3;
- /* 40 MHz, SGI */
- rate = MCS_RATE(mcs, true, true);
- ampdu->max_txlen[mcs][1][1] = (rate * dur) >> 3;
- }
-}
-
-void wlc_ampdu_macaddr_upd(struct wlc_info *wlc)
-{
- char template[T_RAM_ACCESS_SZ * 2];
-
- /* driver needs to write the ta in the template; ta is at offset 16 */
- memset(template, 0, sizeof(template));
- memcpy(template, wlc->pub->cur_etheraddr, ETH_ALEN);
- wlc_write_template_ram(wlc, (T_BA_TPL_BASE + 16), (T_RAM_ACCESS_SZ * 2),
- template);
-}
-
-bool wlc_aggregatable(struct wlc_info *wlc, u8 tid)
-{
- return wlc->ampdu->ini_enable[tid];
-}
-
-void wlc_ampdu_shm_upd(struct ampdu_info *ampdu)
-{
- struct wlc_info *wlc = ampdu->wlc;
-
- /* Extend ucode internal watchdog timer to match larger received frames */
- if ((ampdu->rx_factor & IEEE80211_HT_AMPDU_PARM_FACTOR) ==
- IEEE80211_HT_MAX_AMPDU_64K) {
- wlc_write_shm(wlc, M_MIMO_MAXSYM, MIMO_MAXSYM_MAX);
- wlc_write_shm(wlc, M_WATCHDOG_8TU, WATCHDOG_8TU_MAX);
- } else {
- wlc_write_shm(wlc, M_MIMO_MAXSYM, MIMO_MAXSYM_DEF);
- wlc_write_shm(wlc, M_WATCHDOG_8TU, WATCHDOG_8TU_DEF);
- }
-}
-
-/*
- * callback function that helps flushing ampdu packets from a priority queue
- */
-static bool cb_del_ampdu_pkt(struct sk_buff *mpdu, void *arg_a)
-{
- struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(mpdu);
- struct cb_del_ampdu_pars *ampdu_pars =
- (struct cb_del_ampdu_pars *)arg_a;
- bool rc;
-
- rc = tx_info->flags & IEEE80211_TX_CTL_AMPDU ? true : false;
- rc = rc && (tx_info->control.sta == NULL || ampdu_pars->sta == NULL ||
- tx_info->control.sta == ampdu_pars->sta);
- rc = rc && ((u8)(mpdu->priority) == ampdu_pars->tid);
- return rc;
-}
-
-/*
- * callback function that helps invalidating ampdu packets in a DMA queue
- */
-static void dma_cb_fn_ampdu(void *txi, void *arg_a)
-{
- struct ieee80211_sta *sta = arg_a;
- struct ieee80211_tx_info *tx_info = (struct ieee80211_tx_info *)txi;
-
- if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) &&
- (tx_info->control.sta == sta || sta == NULL))
- tx_info->control.sta = NULL;
-}
-
-/*
- * When a remote party is no longer available for ampdu communication, any
- * pending tx ampdu packets in the driver have to be flushed.
- */
-void wlc_ampdu_flush(struct wlc_info *wlc,
- struct ieee80211_sta *sta, u16 tid)
-{
- struct wlc_txq_info *qi = wlc->pkt_queue;
- struct pktq *pq = &qi->q;
- int prec;
- struct cb_del_ampdu_pars ampdu_pars;
-
- ampdu_pars.sta = sta;
- ampdu_pars.tid = tid;
- for (prec = 0; prec < pq->num_prec; prec++) {
- brcmu_pktq_pflush(pq, prec, true, cb_del_ampdu_pkt,
- (void *)&du_pars);
- }
- wlc_inval_dma_pkts(wlc->hw, sta, dma_cb_fn_ampdu);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_AMPDU_H_
-#define _BRCM_AMPDU_H_
-
-extern struct ampdu_info *wlc_ampdu_attach(struct wlc_info *wlc);
-extern void wlc_ampdu_detach(struct ampdu_info *ampdu);
-extern int wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
- struct sk_buff **aggp, int prec);
-extern void wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
- struct sk_buff *p, tx_status_t *txs);
-extern void wlc_ampdu_macaddr_upd(struct wlc_info *wlc);
-extern void wlc_ampdu_shm_upd(struct ampdu_info *ampdu);
-
-#endif /* _BRCM_AMPDU_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <wlc_cfg.h>
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-
-#include <bcmdefs.h>
-#include <brcmu_utils.h>
-#include <aiutils.h>
-#include <bcmdevs.h>
-#include "bcmdma.h"
-
-#include "d11.h"
-#include "wlc_rate.h"
-#include "wlc_key.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "phy/wlc_phy_hal.h"
-#include "wlc_bmac.h"
-#include "wlc_channel.h"
-#include "wlc_main.h"
-#include "wlc_antsel.h"
-
-#define ANT_SELCFG_AUTO 0x80 /* bit indicates antenna sel AUTO */
-#define ANT_SELCFG_MASK 0x33 /* antenna configuration mask */
-#define ANT_SELCFG_TX_UNICAST 0 /* unicast tx antenna configuration */
-#define ANT_SELCFG_RX_UNICAST 1 /* unicast rx antenna configuration */
-#define ANT_SELCFG_TX_DEF 2 /* default tx antenna configuration */
-#define ANT_SELCFG_RX_DEF 3 /* default rx antenna configuration */
-
-/* useful macros */
-#define WLC_ANTSEL_11N_0(ant) ((((ant) & ANT_SELCFG_MASK) >> 4) & 0xf)
-#define WLC_ANTSEL_11N_1(ant) (((ant) & ANT_SELCFG_MASK) & 0xf)
-#define WLC_ANTIDX_11N(ant) (((WLC_ANTSEL_11N_0(ant)) << 2) + (WLC_ANTSEL_11N_1(ant)))
-#define WLC_ANT_ISAUTO_11N(ant) (((ant) & ANT_SELCFG_AUTO) == ANT_SELCFG_AUTO)
-#define WLC_ANTSEL_11N(ant) ((ant) & ANT_SELCFG_MASK)
-
-/* antenna switch */
-/* defines for no boardlevel antenna diversity */
-#define ANT_SELCFG_DEF_2x2 0x01 /* default antenna configuration */
-
-/* 2x3 antdiv defines and tables for GPIO communication */
-#define ANT_SELCFG_NUM_2x3 3
-#define ANT_SELCFG_DEF_2x3 0x01 /* default antenna configuration */
-
-/* 2x4 antdiv rev4 defines and tables for GPIO communication */
-#define ANT_SELCFG_NUM_2x4 4
-#define ANT_SELCFG_DEF_2x4 0x02 /* default antenna configuration */
-
-/* static functions */
-static int wlc_antsel_cfgupd(struct antsel_info *asi, wlc_antselcfg_t *antsel);
-static u8 wlc_antsel_id2antcfg(struct antsel_info *asi, u8 id);
-static u16 wlc_antsel_antcfg2antsel(struct antsel_info *asi, u8 ant_cfg);
-static void wlc_antsel_init_cfg(struct antsel_info *asi,
- wlc_antselcfg_t *antsel,
- bool auto_sel);
-
-const u16 mimo_2x4_div_antselpat_tbl[] = {
- 0, 0, 0x9, 0xa, /* ant0: 0 ant1: 2,3 */
- 0, 0, 0x5, 0x6, /* ant0: 1 ant1: 2,3 */
- 0, 0, 0, 0, /* n.a. */
- 0, 0, 0, 0 /* n.a. */
-};
-
-const u8 mimo_2x4_div_antselid_tbl[16] = {
- 0, 0, 0, 0, 0, 2, 3, 0,
- 0, 0, 1, 0, 0, 0, 0, 0 /* pat to antselid */
-};
-
-const u16 mimo_2x3_div_antselpat_tbl[] = {
- 16, 0, 1, 16, /* ant0: 0 ant1: 1,2 */
- 16, 16, 16, 16, /* n.a. */
- 16, 2, 16, 16, /* ant0: 2 ant1: 1 */
- 16, 16, 16, 16 /* n.a. */
-};
-
-const u8 mimo_2x3_div_antselid_tbl[16] = {
- 0, 1, 2, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0 /* pat to antselid */
-};
-
-struct antsel_info *wlc_antsel_attach(struct wlc_info *wlc)
-{
- struct antsel_info *asi;
-
- asi = kzalloc(sizeof(struct antsel_info), GFP_ATOMIC);
- if (!asi) {
- wiphy_err(wlc->wiphy, "wl%d: wlc_antsel_attach: out of mem\n",
- wlc->pub->unit);
- return NULL;
- }
-
- asi->wlc = wlc;
- asi->pub = wlc->pub;
- asi->antsel_type = ANTSEL_NA;
- asi->antsel_avail = false;
- asi->antsel_antswitch = (u8) getintvar(asi->pub->vars, "antswitch");
-
- if ((asi->pub->sromrev >= 4) && (asi->antsel_antswitch != 0)) {
- switch (asi->antsel_antswitch) {
- case ANTSWITCH_TYPE_1:
- case ANTSWITCH_TYPE_2:
- case ANTSWITCH_TYPE_3:
- /* 4321/2 board with 2x3 switch logic */
- asi->antsel_type = ANTSEL_2x3;
- /* Antenna selection availability */
- if (((u16) getintvar(asi->pub->vars, "aa2g") == 7) ||
- ((u16) getintvar(asi->pub->vars, "aa5g") == 7)) {
- asi->antsel_avail = true;
- } else
- if (((u16) getintvar(asi->pub->vars, "aa2g") ==
- 3)
- || ((u16) getintvar(asi->pub->vars, "aa5g")
- == 3)) {
- asi->antsel_avail = false;
- } else {
- asi->antsel_avail = false;
- wiphy_err(wlc->wiphy, "wlc_antsel_attach: 2o3 "
- "board cfg invalid\n");
- }
- break;
- default:
- break;
- }
- } else if ((asi->pub->sromrev == 4) &&
- ((u16) getintvar(asi->pub->vars, "aa2g") == 7) &&
- ((u16) getintvar(asi->pub->vars, "aa5g") == 0)) {
- /* hack to match old 4321CB2 cards with 2of3 antenna switch */
- asi->antsel_type = ANTSEL_2x3;
- asi->antsel_avail = true;
- } else if (asi->pub->boardflags2 & BFL2_2X4_DIV) {
- asi->antsel_type = ANTSEL_2x4;
- asi->antsel_avail = true;
- }
-
- /* Set the antenna selection type for the low driver */
- wlc_bmac_antsel_type_set(wlc->hw, asi->antsel_type);
-
- /* Init (auto/manual) antenna selection */
- wlc_antsel_init_cfg(asi, &asi->antcfg_11n, true);
- wlc_antsel_init_cfg(asi, &asi->antcfg_cur, true);
-
- return asi;
-}
-
-void wlc_antsel_detach(struct antsel_info *asi)
-{
- kfree(asi);
-}
-
-void wlc_antsel_init(struct antsel_info *asi)
-{
- if ((asi->antsel_type == ANTSEL_2x3) ||
- (asi->antsel_type == ANTSEL_2x4))
- wlc_antsel_cfgupd(asi, &asi->antcfg_11n);
-}
-
-/* boardlevel antenna selection: init antenna selection structure */
-static void
-wlc_antsel_init_cfg(struct antsel_info *asi, wlc_antselcfg_t *antsel,
- bool auto_sel)
-{
- if (asi->antsel_type == ANTSEL_2x3) {
- u8 antcfg_def = ANT_SELCFG_DEF_2x3 |
- ((asi->antsel_avail && auto_sel) ? ANT_SELCFG_AUTO : 0);
- antsel->ant_config[ANT_SELCFG_TX_DEF] = antcfg_def;
- antsel->ant_config[ANT_SELCFG_TX_UNICAST] = antcfg_def;
- antsel->ant_config[ANT_SELCFG_RX_DEF] = antcfg_def;
- antsel->ant_config[ANT_SELCFG_RX_UNICAST] = antcfg_def;
- antsel->num_antcfg = ANT_SELCFG_NUM_2x3;
-
- } else if (asi->antsel_type == ANTSEL_2x4) {
-
- antsel->ant_config[ANT_SELCFG_TX_DEF] = ANT_SELCFG_DEF_2x4;
- antsel->ant_config[ANT_SELCFG_TX_UNICAST] = ANT_SELCFG_DEF_2x4;
- antsel->ant_config[ANT_SELCFG_RX_DEF] = ANT_SELCFG_DEF_2x4;
- antsel->ant_config[ANT_SELCFG_RX_UNICAST] = ANT_SELCFG_DEF_2x4;
- antsel->num_antcfg = ANT_SELCFG_NUM_2x4;
-
- } else { /* no antenna selection available */
-
- antsel->ant_config[ANT_SELCFG_TX_DEF] = ANT_SELCFG_DEF_2x2;
- antsel->ant_config[ANT_SELCFG_TX_UNICAST] = ANT_SELCFG_DEF_2x2;
- antsel->ant_config[ANT_SELCFG_RX_DEF] = ANT_SELCFG_DEF_2x2;
- antsel->ant_config[ANT_SELCFG_RX_UNICAST] = ANT_SELCFG_DEF_2x2;
- antsel->num_antcfg = 0;
- }
-}
-
-void
-wlc_antsel_antcfg_get(struct antsel_info *asi, bool usedef, bool sel,
- u8 antselid, u8 fbantselid, u8 *antcfg,
- u8 *fbantcfg)
-{
- u8 ant;
-
- /* if use default, assign it and return */
- if (usedef) {
- *antcfg = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_DEF];
- *fbantcfg = *antcfg;
- return;
- }
-
- if (!sel) {
- *antcfg = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
- *fbantcfg = *antcfg;
-
- } else {
- ant = asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
- if ((ant & ANT_SELCFG_AUTO) == ANT_SELCFG_AUTO) {
- *antcfg = wlc_antsel_id2antcfg(asi, antselid);
- *fbantcfg = wlc_antsel_id2antcfg(asi, fbantselid);
- } else {
- *antcfg =
- asi->antcfg_11n.ant_config[ANT_SELCFG_TX_UNICAST];
- *fbantcfg = *antcfg;
- }
- }
- return;
-}
-
-/* boardlevel antenna selection: convert mimo_antsel (ucode interface) to id */
-u8 wlc_antsel_antsel2id(struct antsel_info *asi, u16 antsel)
-{
- u8 antselid = 0;
-
- if (asi->antsel_type == ANTSEL_2x4) {
- /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
- antselid = mimo_2x4_div_antselid_tbl[(antsel & 0xf)];
- return antselid;
-
- } else if (asi->antsel_type == ANTSEL_2x3) {
- /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
- antselid = mimo_2x3_div_antselid_tbl[(antsel & 0xf)];
- return antselid;
- }
-
- return antselid;
-}
-
-/* boardlevel antenna selection: convert id to ant_cfg */
-static u8 wlc_antsel_id2antcfg(struct antsel_info *asi, u8 id)
-{
- u8 antcfg = ANT_SELCFG_DEF_2x2;
-
- if (asi->antsel_type == ANTSEL_2x4) {
- /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
- antcfg = (((id & 0x2) << 3) | ((id & 0x1) + 2));
- return antcfg;
-
- } else if (asi->antsel_type == ANTSEL_2x3) {
- /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
- antcfg = (((id & 0x02) << 4) | ((id & 0x1) + 1));
- return antcfg;
- }
-
- return antcfg;
-}
-
-/* boardlevel antenna selection: convert ant_cfg to mimo_antsel (ucode interface) */
-static u16 wlc_antsel_antcfg2antsel(struct antsel_info *asi, u8 ant_cfg)
-{
- u8 idx = WLC_ANTIDX_11N(WLC_ANTSEL_11N(ant_cfg));
- u16 mimo_antsel = 0;
-
- if (asi->antsel_type == ANTSEL_2x4) {
- /* 2x4 antenna diversity board, 4 cfgs: 0-2 0-3 1-2 1-3 */
- mimo_antsel = (mimo_2x4_div_antselpat_tbl[idx] & 0xf);
- return mimo_antsel;
-
- } else if (asi->antsel_type == ANTSEL_2x3) {
- /* 2x3 antenna selection, 3 cfgs: 0-1 0-2 2-1 */
- mimo_antsel = (mimo_2x3_div_antselpat_tbl[idx] & 0xf);
- return mimo_antsel;
- }
-
- return mimo_antsel;
-}
-
-/* boardlevel antenna selection: ucode interface control */
-static int wlc_antsel_cfgupd(struct antsel_info *asi, wlc_antselcfg_t *antsel)
-{
- struct wlc_info *wlc = asi->wlc;
- u8 ant_cfg;
- u16 mimo_antsel;
-
- /* 1) Update TX antconfig for all frames that are not unicast data
- * (aka default TX)
- */
- ant_cfg = antsel->ant_config[ANT_SELCFG_TX_DEF];
- mimo_antsel = wlc_antsel_antcfg2antsel(asi, ant_cfg);
- wlc_write_shm(wlc, M_MIMO_ANTSEL_TXDFLT, mimo_antsel);
- /* Update driver stats for currently selected default tx/rx antenna config */
- asi->antcfg_cur.ant_config[ANT_SELCFG_TX_DEF] = ant_cfg;
-
- /* 2) Update RX antconfig for all frames that are not unicast data
- * (aka default RX)
- */
- ant_cfg = antsel->ant_config[ANT_SELCFG_RX_DEF];
- mimo_antsel = wlc_antsel_antcfg2antsel(asi, ant_cfg);
- wlc_write_shm(wlc, M_MIMO_ANTSEL_RXDFLT, mimo_antsel);
- /* Update driver stats for currently selected default tx/rx antenna config */
- asi->antcfg_cur.ant_config[ANT_SELCFG_RX_DEF] = ant_cfg;
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_ANTSEL_H_
-#define _BRCM_ANTSEL_H_
-
-extern struct antsel_info *wlc_antsel_attach(struct wlc_info *wlc);
-extern void wlc_antsel_detach(struct antsel_info *asi);
-extern void wlc_antsel_init(struct antsel_info *asi);
-extern void wlc_antsel_antcfg_get(struct antsel_info *asi, bool usedef,
- bool sel,
- u8 id, u8 fbid, u8 *antcfg,
- u8 *fbantcfg);
-extern u8 wlc_antsel_antsel2id(struct antsel_info *asi, u16 antsel);
-
-#endif /* _BRCM_ANTSEL_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-
-#include <bcmdefs.h>
-#include <bcmdevs.h>
-#include <brcmu_wifi.h>
-#include <aiutils.h>
-#include <bcmsrom.h>
-#include <bcmotp.h>
-#include <brcmu_utils.h>
-#include <chipcommon.h>
-#include <nicpci.h>
-#include <bcmdma.h>
-
-#include "wlc_types.h"
-#include "wlc_pmu.h"
-#include "d11.h"
-#include "wlc_cfg.h"
-#include "wlc_rate.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "wlc_key.h"
-#include "phy/wlc_phy_hal.h"
-#include "wlc_channel.h"
-#include "wlc_main.h"
-#include "ucode_loader.h"
-#include "wlc_antsel.h"
-#include "wlc_alloc.h"
-#include "wlc_bmac.h"
-#include "brcms_mac80211.h"
-
-#define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
-
-#define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
-#define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
-#define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
-#define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
-
-#define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
-
-#ifndef BMAC_DUP_TO_REMOVE
-#define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
-
-#define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
-
-#endif /* BMAC_DUP_TO_REMOVE */
-
-#define DMAREG(wlc_hw, direction, fifonum) \
- ((direction == DMA_TX) ? \
- (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmaxmt) : \
- (void *)&(wlc_hw->regs->fifo64regs[fifonum].dmarcv))
-
-#define APHY_SLOT_TIME 9
-#define BPHY_SLOT_TIME 20
-
-/*
- * The following table lists the buffer memory allocated to xmt fifos in HW.
- * the size is in units of 256bytes(one block), total size is HW dependent
- * ucode has default fifo partition, sw can overwrite if necessary
- *
- * This is documented in twiki under the topic UcodeTxFifo. Please ensure
- * the twiki is updated before making changes.
- */
-
-#define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
-
-static u16 xmtfifo_sz[][NFIFO] = {
- {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
- {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
- {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
- {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
- {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
-};
-
-static void wlc_clkctl_clk(struct wlc_hw_info *wlc, uint mode);
-static void wlc_coreinit(struct wlc_info *wlc);
-
-/* used by wlc_wakeucode_init() */
-static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
- const struct d11init *inits);
-static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
- const uint nbytes);
-static void wlc_ucode_download(struct wlc_hw_info *wlc);
-static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw);
-
-/* used by wlc_dpc() */
-static bool wlc_bmac_dotxstatus(struct wlc_hw_info *wlc, tx_status_t *txs,
- u32 s2);
-static bool wlc_bmac_txstatus(struct wlc_hw_info *wlc, bool bound, bool *fatal);
-static bool wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound);
-
-/* used by wlc_down() */
-static void wlc_flushqueues(struct wlc_info *wlc);
-
-static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs);
-static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw);
-static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw);
-static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw,
- uint tx_fifo);
-static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo);
-static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo);
-
-/* Low Level Prototypes */
-static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw);
-static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw);
-static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want);
-static u16 wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset,
- u32 sel);
-static void wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset,
- u16 v, u32 sel);
-static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk);
-static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme);
-static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw);
-static void wlc_ucode_bsinit(struct wlc_hw_info *wlc_hw);
-static bool wlc_validboardtype(struct wlc_hw_info *wlc);
-static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw);
-static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw);
-static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw);
-static void wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init);
-static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw);
-static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool want, mbool flags);
-static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw);
-static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw);
-static u32 wlc_wlintrsoff(struct wlc_info *wlc);
-static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask);
-static void wlc_gpio_init(struct wlc_info *wlc);
-static void wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn,
- int len);
-static void wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn,
- int len);
-static void wlc_bmac_bsinit(struct wlc_info *wlc, chanspec_t chanspec);
-static u32 wlc_setband_inact(struct wlc_info *wlc, uint bandunit);
-static void wlc_bmac_setband(struct wlc_hw_info *wlc_hw, uint bandunit,
- chanspec_t chanspec);
-static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
- bool shortslot);
-static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw);
-static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw,
- u8 rate);
-
-/* === Low Level functions === */
-
-void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot)
-{
- wlc_hw->shortslot = shortslot;
-
- if (BAND_2G(wlc_bmac_bandtype(wlc_hw)) && wlc_hw->up) {
- wlc_suspend_mac_and_wait(wlc_hw->wlc);
- wlc_bmac_update_slot_timing(wlc_hw, shortslot);
- wlc_enable_mac(wlc_hw->wlc);
- }
-}
-
-/*
- * Update the slot timing for standard 11b/g (20us slots)
- * or shortslot 11g (9us slots)
- * The PSM needs to be suspended for this call.
- */
-static void wlc_bmac_update_slot_timing(struct wlc_hw_info *wlc_hw,
- bool shortslot)
-{
- d11regs_t *regs;
-
- regs = wlc_hw->regs;
-
- if (shortslot) {
- /* 11g short slot: 11a timing */
- W_REG(®s->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
- wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
- } else {
- /* 11g long slot: 11b timing */
- W_REG(®s->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
- wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
- }
-}
-
-static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
-{
- struct wiphy *wiphy = wlc_hw->wlc->wiphy;
-
- /* init microcode host flags */
- wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
-
- /* do band-specific ucode IHR, SHM, and SCR inits */
- if (D11REV_IS(wlc_hw->corerev, 23)) {
- if (WLCISNPHY(wlc_hw->band)) {
- wlc_write_inits(wlc_hw, d11n0bsinitvals16);
- } else {
- wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
- " %d\n", __func__, wlc_hw->unit,
- wlc_hw->corerev);
- }
- } else {
- if (D11REV_IS(wlc_hw->corerev, 24)) {
- if (WLCISLCNPHY(wlc_hw->band)) {
- wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
- } else
- wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
- " core rev %d\n", __func__,
- wlc_hw->unit, wlc_hw->corerev);
- } else {
- wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
- }
- }
-}
-
-/* switch to new band but leave it inactive */
-static u32 WLBANDINITFN(wlc_setband_inact) (struct wlc_info *wlc, uint bandunit)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- u32 macintmask;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
-
- /* disable interrupts */
- macintmask = brcms_intrsoff(wlc->wl);
-
- /* radio off */
- wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
-
- wlc_bmac_core_phy_clk(wlc_hw, OFF);
-
- wlc_setxband(wlc_hw, bandunit);
-
- return macintmask;
-}
-
-/* Process received frames */
-/*
- * Return true if more frames need to be processed. false otherwise.
- * Param 'bound' indicates max. # frames to process before break out.
- */
-static bool
-wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
-{
- struct sk_buff *p;
- struct sk_buff *head = NULL;
- struct sk_buff *tail = NULL;
- uint n = 0;
- uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
- wlc_d11rxhdr_t *wlc_rxhdr = NULL;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
- /* gather received frames */
- while ((p = dma_rx(wlc_hw->di[fifo]))) {
-
- if (!tail)
- head = tail = p;
- else {
- tail->prev = p;
- tail = p;
- }
-
- /* !give others some time to run! */
- if (++n >= bound_limit)
- break;
- }
-
- /* post more rbufs */
- dma_rxfill(wlc_hw->di[fifo]);
-
- /* process each frame */
- while ((p = head) != NULL) {
- head = head->prev;
- p->prev = NULL;
-
- wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
-
- /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
- wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
-
- wlc_recv(wlc_hw->wlc, p);
- }
-
- return n >= bound_limit;
-}
-
-/* second-level interrupt processing
- * Return true if another dpc needs to be re-scheduled. false otherwise.
- * Param 'bounded' indicates if applicable loops should be bounded.
- */
-bool wlc_dpc(struct wlc_info *wlc, bool bounded)
-{
- u32 macintstatus;
- struct wlc_hw_info *wlc_hw = wlc->hw;
- d11regs_t *regs = wlc_hw->regs;
- bool fatal = false;
- struct wiphy *wiphy = wlc->wiphy;
-
- if (DEVICEREMOVED(wlc)) {
- wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
- __func__);
- brcms_down(wlc->wl);
- return false;
- }
-
- /* grab and clear the saved software intstatus bits */
- macintstatus = wlc->macintstatus;
- wlc->macintstatus = 0;
-
- BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
- wlc_hw->unit, macintstatus);
-
- WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
-
- /* BCN template is available */
- /* ZZZ: Use AP_ACTIVE ? */
- if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub))
- && (macintstatus & MI_BCNTPL)) {
- wlc_update_beacon(wlc);
- }
-
- /* PMQ entry addition */
- if (macintstatus & MI_PMQ) {
- }
-
- /* tx status */
- if (macintstatus & MI_TFS) {
- if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
- wlc->macintstatus |= MI_TFS;
- if (fatal) {
- wiphy_err(wiphy, "MI_TFS: fatal\n");
- goto fatal;
- }
- }
-
- if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
- wlc_tbtt(wlc, regs);
-
- /* ATIM window end */
- if (macintstatus & MI_ATIMWINEND) {
- BCMMSG(wlc->wiphy, "end of ATIM window\n");
- OR_REG(®s->maccommand, wlc->qvalid);
- wlc->qvalid = 0;
- }
-
- /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
- if (macintstatus & MI_DMAINT) {
- if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
- wlc->macintstatus |= MI_DMAINT;
- }
- }
-
- /* TX FIFO suspend/flush completion */
- if (macintstatus & MI_TXSTOP) {
- if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
- /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
- }
- }
-
- /* noise sample collected */
- if (macintstatus & MI_BG_NOISE) {
- wlc_phy_noise_sample_intr(wlc_hw->band->pi);
- }
-
- if (macintstatus & MI_GP0) {
- wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
- "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
-
- printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
- __func__, wlc_hw->sih->chip,
- wlc_hw->sih->chiprev);
- /* big hammer */
- brcms_init(wlc->wl);
- }
-
- /* gptimer timeout */
- if (macintstatus & MI_TO) {
- W_REG(®s->gptimer, 0);
- }
-
- if (macintstatus & MI_RFDISABLE) {
- BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
- " RF Disable Input\n", wlc_hw->unit);
- brcms_rfkill_set_hw_state(wlc->wl);
- }
-
- /* send any enq'd tx packets. Just makes sure to jump start tx */
- if (!pktq_empty(&wlc->pkt_queue->q))
- wlc_send_q(wlc);
-
- /* it isn't done and needs to be resched if macintstatus is non-zero */
- return wlc->macintstatus != 0;
-
- fatal:
- brcms_init(wlc->wl);
- return wlc->macintstatus != 0;
-}
-
-/* common low-level watchdog code */
-void wlc_bmac_watchdog(void *arg)
-{
- struct wlc_info *wlc = (struct wlc_info *) arg;
- struct wlc_hw_info *wlc_hw = wlc->hw;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- if (!wlc_hw->up)
- return;
-
- /* increment second count */
- wlc_hw->now++;
-
- /* Check for FIFO error interrupts */
- wlc_bmac_fifoerrors(wlc_hw);
-
- /* make sure RX dma has buffers */
- dma_rxfill(wlc->hw->di[RX_FIFO]);
-
- wlc_phy_watchdog(wlc_hw->band->pi);
-}
-
-void
-wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
- bool mute, struct txpwr_limits *txpwr)
-{
- uint bandunit;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
-
- wlc_hw->chanspec = chanspec;
-
- /* Switch bands if necessary */
- if (NBANDS_HW(wlc_hw) > 1) {
- bandunit = CHSPEC_WLCBANDUNIT(chanspec);
- if (wlc_hw->band->bandunit != bandunit) {
- /* wlc_bmac_setband disables other bandunit,
- * use light band switch if not up yet
- */
- if (wlc_hw->up) {
- wlc_phy_chanspec_radio_set(wlc_hw->
- bandstate[bandunit]->
- pi, chanspec);
- wlc_bmac_setband(wlc_hw, bandunit, chanspec);
- } else {
- wlc_setxband(wlc_hw, bandunit);
- }
- }
- }
-
- wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
-
- if (!wlc_hw->up) {
- if (wlc_hw->clk)
- wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
- chanspec);
- wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
- } else {
- wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
- wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
-
- /* Update muting of the channel */
- wlc_bmac_mute(wlc_hw, mute, 0);
- }
-}
-
-int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw, wlc_bmac_state_t *state)
-{
- state->machwcap = wlc_hw->machwcap;
-
- return 0;
-}
-
-static bool wlc_bmac_attach_dmapio(struct wlc_info *wlc, uint j, bool wme)
-{
- uint i;
- char name[8];
- /* ucode host flag 2 needed for pio mode, independent of band and fifo */
- u16 pio_mhf2 = 0;
- struct wlc_hw_info *wlc_hw = wlc->hw;
- uint unit = wlc_hw->unit;
- wlc_tunables_t *tune = wlc->pub->tunables;
- struct wiphy *wiphy = wlc->wiphy;
-
- /* name and offsets for dma_attach */
- snprintf(name, sizeof(name), "wl%d", unit);
-
- if (wlc_hw->di[0] == 0) { /* Init FIFOs */
- uint addrwidth;
- int dma_attach_err = 0;
- /* Find out the DMA addressing capability and let OS know
- * All the channels within one DMA core have 'common-minimum' same
- * capability
- */
- addrwidth =
- dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
-
- if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
- wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
- "resources failed\n", unit);
- return false;
- }
-
- /*
- * FIFO 0
- * TX: TX_AC_BK_FIFO (TX AC Background data packets)
- * RX: RX_FIFO (RX data packets)
- */
- wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
- (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
- NULL), DMAREG(wlc_hw, DMA_RX, 0),
- (wme ? tune->ntxd : 0), tune->nrxd,
- tune->rxbufsz, -1, tune->nrxbufpost,
- WL_HWRXOFF, &brcm_msg_level);
- dma_attach_err |= (NULL == wlc_hw->di[0]);
-
- /*
- * FIFO 1
- * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
- * (legacy) TX_DATA_FIFO (TX data packets)
- * RX: UNUSED
- */
- wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
- DMAREG(wlc_hw, DMA_TX, 1), NULL,
- tune->ntxd, 0, 0, -1, 0, 0,
- &brcm_msg_level);
- dma_attach_err |= (NULL == wlc_hw->di[1]);
-
- /*
- * FIFO 2
- * TX: TX_AC_VI_FIFO (TX AC Video data packets)
- * RX: UNUSED
- */
- wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
- DMAREG(wlc_hw, DMA_TX, 2), NULL,
- tune->ntxd, 0, 0, -1, 0, 0,
- &brcm_msg_level);
- dma_attach_err |= (NULL == wlc_hw->di[2]);
- /*
- * FIFO 3
- * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
- * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
- */
- wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
- DMAREG(wlc_hw, DMA_TX, 3),
- NULL, tune->ntxd, 0, 0, -1,
- 0, 0, &brcm_msg_level);
- dma_attach_err |= (NULL == wlc_hw->di[3]);
-/* Cleaner to leave this as if with AP defined */
-
- if (dma_attach_err) {
- wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
- "\n", unit);
- return false;
- }
-
- /* get pointer to dma engine tx flow control variable */
- for (i = 0; i < NFIFO; i++)
- if (wlc_hw->di[i])
- wlc_hw->txavail[i] =
- (uint *) dma_getvar(wlc_hw->di[i],
- "&txavail");
- }
-
- /* initial ucode host flags */
- wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
-
- return true;
-}
-
-static void wlc_bmac_detach_dmapio(struct wlc_hw_info *wlc_hw)
-{
- uint j;
-
- for (j = 0; j < NFIFO; j++) {
- if (wlc_hw->di[j]) {
- dma_detach(wlc_hw->di[j]);
- wlc_hw->di[j] = NULL;
- }
- }
-}
-
-/* low level attach
- * run backplane attach, init nvram
- * run phy attach
- * initialize software state for each core and band
- * put the whole chip in reset(driver down state), no clock
- */
-int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device, uint unit,
- bool piomode, void *regsva, uint bustype, void *btparam)
-{
- struct wlc_hw_info *wlc_hw;
- d11regs_t *regs;
- char *macaddr = NULL;
- char *vars;
- uint err = 0;
- uint j;
- bool wme = false;
- shared_phy_params_t sha_params;
- struct wiphy *wiphy = wlc->wiphy;
-
- BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
- device);
-
- wme = true;
-
- wlc_hw = wlc->hw;
- wlc_hw->wlc = wlc;
- wlc_hw->unit = unit;
- wlc_hw->band = wlc_hw->bandstate[0];
- wlc_hw->_piomode = piomode;
-
- /* populate struct wlc_hw_info with default values */
- wlc_bmac_info_init(wlc_hw);
-
- /*
- * Do the hardware portion of the attach.
- * Also initialize software state that depends on the particular hardware
- * we are running.
- */
- wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
- &wlc_hw->vars, &wlc_hw->vars_size);
- if (wlc_hw->sih == NULL) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
- unit);
- err = 11;
- goto fail;
- }
- vars = wlc_hw->vars;
-
- /*
- * Get vendid/devid nvram overwrites, which could be different
- * than those the BIOS recognizes for devices on PCMCIA_BUS,
- * SDIO_BUS, and SROMless devices on PCI_BUS.
- */
-#ifdef BCMBUSTYPE
- bustype = BCMBUSTYPE;
-#endif
- if (bustype != SI_BUS) {
- char *var;
-
- var = getvar(vars, "vendid");
- if (var) {
- vendor = (u16) simple_strtoul(var, NULL, 0);
- wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
- vendor);
- }
- var = getvar(vars, "devid");
- if (var) {
- u16 devid = (u16) simple_strtoul(var, NULL, 0);
- if (devid != 0xffff) {
- device = devid;
- wiphy_err(wiphy, "Overriding device id = 0x%x"
- "\n", device);
- }
- }
-
- /* verify again the device is supported */
- if (!wlc_chipmatch(vendor, device)) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
- "vendor/device (0x%x/0x%x)\n",
- unit, vendor, device);
- err = 12;
- goto fail;
- }
- }
-
- wlc_hw->vendorid = vendor;
- wlc_hw->deviceid = device;
-
- /* set bar0 window to point at D11 core */
- wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
- wlc_hw->corerev = ai_corerev(wlc_hw->sih);
-
- regs = wlc_hw->regs;
-
- wlc->regs = wlc_hw->regs;
-
- /* validate chip, chiprev and corerev */
- if (!wlc_isgoodchip(wlc_hw)) {
- err = 13;
- goto fail;
- }
-
- /* initialize power control registers */
- ai_clkctl_init(wlc_hw->sih);
-
- /* request fastclock and force fastclock for the rest of attach
- * bring the d11 core out of reset.
- * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still false;
- * But it will be called again inside wlc_corereset, after d11 is out of reset.
- */
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
- wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
-
- if (!wlc_bmac_validate_chip_access(wlc_hw)) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
- "failed\n", unit);
- err = 14;
- goto fail;
- }
-
- /* get the board rev, used just below */
- j = getintvar(vars, "boardrev");
- /* promote srom boardrev of 0xFF to 1 */
- if (j == BOARDREV_PROMOTABLE)
- j = BOARDREV_PROMOTED;
- wlc_hw->boardrev = (u16) j;
- if (!wlc_validboardtype(wlc_hw)) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
- "board type (0x%x)" " or revision level (0x%x)\n",
- unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
- err = 15;
- goto fail;
- }
- wlc_hw->sromrev = (u8) getintvar(vars, "sromrev");
- wlc_hw->boardflags = (u32) getintvar(vars, "boardflags");
- wlc_hw->boardflags2 = (u32) getintvar(vars, "boardflags2");
-
- if (wlc_hw->boardflags & BFL_NOPLLDOWN)
- wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
-
- if ((wlc_hw->sih->bustype == PCI_BUS)
- && (ai_pci_war16165(wlc_hw->sih)))
- wlc->war16165 = true;
-
- /* check device id(srom, nvram etc.) to set bands */
- if (wlc_hw->deviceid == BCM43224_D11N_ID ||
- wlc_hw->deviceid == BCM43224_D11N_ID_VEN1) {
- /* Dualband boards */
- wlc_hw->_nbands = 2;
- } else
- wlc_hw->_nbands = 1;
-
- if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
- wlc_hw->_nbands = 1;
-
- /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
- * init of these values
- */
- wlc->vendorid = wlc_hw->vendorid;
- wlc->deviceid = wlc_hw->deviceid;
- wlc->pub->sih = wlc_hw->sih;
- wlc->pub->corerev = wlc_hw->corerev;
- wlc->pub->sromrev = wlc_hw->sromrev;
- wlc->pub->boardrev = wlc_hw->boardrev;
- wlc->pub->boardflags = wlc_hw->boardflags;
- wlc->pub->boardflags2 = wlc_hw->boardflags2;
- wlc->pub->_nbands = wlc_hw->_nbands;
-
- wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
-
- if (wlc_hw->physhim == NULL) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
- "failed\n", unit);
- err = 25;
- goto fail;
- }
-
- /* pass all the parameters to wlc_phy_shared_attach in one struct */
- sha_params.sih = wlc_hw->sih;
- sha_params.physhim = wlc_hw->physhim;
- sha_params.unit = unit;
- sha_params.corerev = wlc_hw->corerev;
- sha_params.vars = vars;
- sha_params.vid = wlc_hw->vendorid;
- sha_params.did = wlc_hw->deviceid;
- sha_params.chip = wlc_hw->sih->chip;
- sha_params.chiprev = wlc_hw->sih->chiprev;
- sha_params.chippkg = wlc_hw->sih->chippkg;
- sha_params.sromrev = wlc_hw->sromrev;
- sha_params.boardtype = wlc_hw->sih->boardtype;
- sha_params.boardrev = wlc_hw->boardrev;
- sha_params.boardvendor = wlc_hw->sih->boardvendor;
- sha_params.boardflags = wlc_hw->boardflags;
- sha_params.boardflags2 = wlc_hw->boardflags2;
- sha_params.bustype = wlc_hw->sih->bustype;
- sha_params.buscorerev = wlc_hw->sih->buscorerev;
-
- /* alloc and save pointer to shared phy state area */
- wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
- if (!wlc_hw->phy_sh) {
- err = 16;
- goto fail;
- }
-
- /* initialize software state for each core and band */
- for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
- /*
- * band0 is always 2.4Ghz
- * band1, if present, is 5Ghz
- */
-
- /* So if this is a single band 11a card, use band 1 */
- if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
- j = BAND_5G_INDEX;
-
- wlc_setxband(wlc_hw, j);
-
- wlc_hw->band->bandunit = j;
- wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
- wlc->band->bandunit = j;
- wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
- wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
-
- wlc_hw->machwcap = R_REG(®s->machwcap);
- wlc_hw->machwcap_backup = wlc_hw->machwcap;
-
- /* init tx fifo size */
- wlc_hw->xmtfifo_sz =
- xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
-
- /* Get a phy for this band */
- wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
- (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
- wlc->wiphy);
- if (wlc_hw->band->pi == NULL) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
- "attach failed\n", unit);
- err = 17;
- goto fail;
- }
-
- wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
-
- wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
- &wlc_hw->band->phyrev,
- &wlc_hw->band->radioid,
- &wlc_hw->band->radiorev);
- wlc_hw->band->abgphy_encore =
- wlc_phy_get_encore(wlc_hw->band->pi);
- wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
- wlc_hw->band->core_flags =
- wlc_phy_get_coreflags(wlc_hw->band->pi);
-
- /* verify good phy_type & supported phy revision */
- if (WLCISNPHY(wlc_hw->band)) {
- if (NCONF_HAS(wlc_hw->band->phyrev))
- goto good_phy;
- else
- goto bad_phy;
- } else if (WLCISLCNPHY(wlc_hw->band)) {
- if (LCNCONF_HAS(wlc_hw->band->phyrev))
- goto good_phy;
- else
- goto bad_phy;
- } else {
- bad_phy:
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
- "phy type/rev (%d/%d)\n", unit,
- wlc_hw->band->phytype, wlc_hw->band->phyrev);
- err = 18;
- goto fail;
- }
-
- good_phy:
- /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
- * high level attach. However we can not make that change until all low level access
- * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
- * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
- * low only init when all fns updated.
- */
- wlc->band->pi = wlc_hw->band->pi;
- wlc->band->phytype = wlc_hw->band->phytype;
- wlc->band->phyrev = wlc_hw->band->phyrev;
- wlc->band->radioid = wlc_hw->band->radioid;
- wlc->band->radiorev = wlc_hw->band->radiorev;
-
- /* default contention windows size limits */
- wlc_hw->band->CWmin = APHY_CWMIN;
- wlc_hw->band->CWmax = PHY_CWMAX;
-
- if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
- err = 19;
- goto fail;
- }
- }
-
- /* disable core to match driver "down" state */
- wlc_coredisable(wlc_hw);
-
- /* Match driver "down" state */
- if (wlc_hw->sih->bustype == PCI_BUS)
- ai_pci_down(wlc_hw->sih);
-
- /* register sb interrupt callback functions */
- ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
- (void *)wlc_wlintrsrestore, NULL, wlc);
-
- /* turn off pll and xtal to match driver "down" state */
- wlc_bmac_xtal(wlc_hw, OFF);
-
- /* *********************************************************************
- * The hardware is in the DOWN state at this point. D11 core
- * or cores are in reset with clocks off, and the board PLLs
- * are off if possible.
- *
- * Beyond this point, wlc->sbclk == false and chip registers
- * should not be touched.
- *********************************************************************
- */
-
- /* init etheraddr state variables */
- macaddr = wlc_get_macaddr(wlc_hw);
- if (macaddr == NULL) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
- unit);
- err = 21;
- goto fail;
- }
- brcmu_ether_atoe(macaddr, wlc_hw->etheraddr);
- if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
- is_zero_ether_addr(wlc_hw->etheraddr)) {
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
- unit, macaddr);
- err = 22;
- goto fail;
- }
-
- BCMMSG(wlc->wiphy,
- "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
- wlc_hw->deviceid, wlc_hw->_nbands,
- wlc_hw->sih->boardtype, macaddr);
-
- return err;
-
- fail:
- wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
- err);
- return err;
-}
-
-/*
- * Initialize wlc_info default values ...
- * may get overrides later in this function
- * BMAC_NOTES, move low out and resolve the dangling ones
- */
-static void wlc_bmac_info_init(struct wlc_hw_info *wlc_hw)
-{
- struct wlc_info *wlc = wlc_hw->wlc;
-
- /* set default sw macintmask value */
- wlc->defmacintmask = DEF_MACINTMASK;
-
- /* various 802.11g modes */
- wlc_hw->shortslot = false;
-
- wlc_hw->SFBL = RETRY_SHORT_FB;
- wlc_hw->LFBL = RETRY_LONG_FB;
-
- /* default mac retry limits */
- wlc_hw->SRL = RETRY_SHORT_DEF;
- wlc_hw->LRL = RETRY_LONG_DEF;
- wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
-}
-
-/*
- * low level detach
- */
-int wlc_bmac_detach(struct wlc_info *wlc)
-{
- uint i;
- struct wlc_hwband *band;
- struct wlc_hw_info *wlc_hw = wlc->hw;
- int callbacks;
-
- callbacks = 0;
-
- if (wlc_hw->sih) {
- /* detach interrupt sync mechanism since interrupt is disabled and per-port
- * interrupt object may has been freed. this must be done before sb core switch
- */
- ai_deregister_intr_callback(wlc_hw->sih);
-
- if (wlc_hw->sih->bustype == PCI_BUS)
- ai_pci_sleep(wlc_hw->sih);
- }
-
- wlc_bmac_detach_dmapio(wlc_hw);
-
- band = wlc_hw->band;
- for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
- if (band->pi) {
- /* Detach this band's phy */
- wlc_phy_detach(band->pi);
- band->pi = NULL;
- }
- band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
- }
-
- /* Free shared phy state */
- wlc_phy_shared_detach(wlc_hw->phy_sh);
-
- wlc_phy_shim_detach(wlc_hw->physhim);
-
- /* free vars */
- kfree(wlc_hw->vars);
- wlc_hw->vars = NULL;
-
- if (wlc_hw->sih) {
- ai_detach(wlc_hw->sih);
- wlc_hw->sih = NULL;
- }
-
- return callbacks;
-
-}
-
-void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
-{
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- /* reset the core */
- if (!DEVICEREMOVED(wlc_hw->wlc))
- wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
-
- /* purge the dma rings */
- wlc_flushqueues(wlc_hw->wlc);
-
- wlc_reset_bmac_done(wlc_hw->wlc);
-}
-
-void
-wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
- bool mute) {
- u32 macintmask;
- bool fastclk;
- struct wlc_info *wlc = wlc_hw->wlc;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- /* request FAST clock if not on */
- fastclk = wlc_hw->forcefastclk;
- if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
-
- /* disable interrupts */
- macintmask = brcms_intrsoff(wlc->wl);
-
- /* set up the specified band and chanspec */
- wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
- wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
-
- /* do one-time phy inits and calibration */
- wlc_phy_cal_init(wlc_hw->band->pi);
-
- /* core-specific initialization */
- wlc_coreinit(wlc);
-
- /* suspend the tx fifos and mute the phy for preism cac time */
- if (mute)
- wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
-
- /* band-specific inits */
- wlc_bmac_bsinit(wlc, chanspec);
-
- /* restore macintmask */
- brcms_intrsrestore(wlc->wl, macintmask);
-
- /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
- * and wlc_enable_mac() will clear this override bit.
- */
- mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
-
- /*
- * initialize mac_suspend_depth to 1 to match ucode initial suspended state
- */
- wlc_hw->mac_suspend_depth = 1;
-
- /* restore the clk */
- if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
-}
-
-int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw)
-{
- uint coremask;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- /*
- * Enable pll and xtal, initialize the power control registers,
- * and force fastclock for the remainder of wlc_up().
- */
- wlc_bmac_xtal(wlc_hw, ON);
- ai_clkctl_init(wlc_hw->sih);
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
-
- /*
- * Configure pci/pcmcia here instead of in wlc_attach()
- * to allow mfg hotswap: down, hotswap (chip power cycle), up.
- */
- coremask = (1 << wlc_hw->wlc->core->coreidx);
-
- if (wlc_hw->sih->bustype == PCI_BUS)
- ai_pci_setup(wlc_hw->sih, coremask);
-
- /*
- * Need to read the hwradio status here to cover the case where the system
- * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
- */
- if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
- /* put SB PCI in down state again */
- if (wlc_hw->sih->bustype == PCI_BUS)
- ai_pci_down(wlc_hw->sih);
- wlc_bmac_xtal(wlc_hw, OFF);
- return -ENOMEDIUM;
- }
-
- if (wlc_hw->sih->bustype == PCI_BUS)
- ai_pci_up(wlc_hw->sih);
-
- /* reset the d11 core */
- wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
-
- return 0;
-}
-
-int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
-{
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- wlc_hw->up = true;
- wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
-
- /* FULLY enable dynamic power control and d11 core interrupt */
- wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
- brcms_intrson(wlc_hw->wlc->wl);
- return 0;
-}
-
-int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw)
-{
- bool dev_gone;
- uint callbacks = 0;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- if (!wlc_hw->up)
- return callbacks;
-
- dev_gone = DEVICEREMOVED(wlc_hw->wlc);
-
- /* disable interrupts */
- if (dev_gone)
- wlc_hw->wlc->macintmask = 0;
- else {
- /* now disable interrupts */
- brcms_intrsoff(wlc_hw->wlc->wl);
-
- /* ensure we're running on the pll clock again */
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
- }
- /* down phy at the last of this stage */
- callbacks += wlc_phy_down(wlc_hw->band->pi);
-
- return callbacks;
-}
-
-int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw)
-{
- uint callbacks = 0;
- bool dev_gone;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- if (!wlc_hw->up)
- return callbacks;
-
- wlc_hw->up = false;
- wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
-
- dev_gone = DEVICEREMOVED(wlc_hw->wlc);
-
- if (dev_gone) {
- wlc_hw->sbclk = false;
- wlc_hw->clk = false;
- wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
-
- /* reclaim any posted packets */
- wlc_flushqueues(wlc_hw->wlc);
- } else {
-
- /* Reset and disable the core */
- if (ai_iscoreup(wlc_hw->sih)) {
- if (R_REG(&wlc_hw->regs->maccontrol) &
- MCTL_EN_MAC)
- wlc_suspend_mac_and_wait(wlc_hw->wlc);
- callbacks += brcms_reset(wlc_hw->wlc->wl);
- wlc_coredisable(wlc_hw);
- }
-
- /* turn off primary xtal and pll */
- if (!wlc_hw->noreset) {
- if (wlc_hw->sih->bustype == PCI_BUS)
- ai_pci_down(wlc_hw->sih);
- wlc_bmac_xtal(wlc_hw, OFF);
- }
- }
-
- return callbacks;
-}
-
-void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw)
-{
- /* delay before first read of ucode state */
- udelay(40);
-
- /* wait until ucode is no longer asleep */
- SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
- DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
-}
-
-void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
-{
- memcpy(ea, wlc_hw->etheraddr, ETH_ALEN);
-}
-
-static int wlc_bmac_bandtype(struct wlc_hw_info *wlc_hw)
-{
- return wlc_hw->band->bandtype;
-}
-
-/* control chip clock to save power, enable dynamic clock or force fast clock */
-static void wlc_clkctl_clk(struct wlc_hw_info *wlc_hw, uint mode)
-{
- if (PMUCTL_ENAB(wlc_hw->sih)) {
- /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
- * but mac core will still run on ALP(not HT) when it enters powersave mode,
- * which means the FCA bit may not be set.
- * should wakeup mac if driver wants it to run on HT.
- */
-
- if (wlc_hw->clk) {
- if (mode == CLK_FAST) {
- OR_REG(&wlc_hw->regs->clk_ctl_st,
- CCS_FORCEHT);
-
- udelay(64);
-
- SPINWAIT(((R_REG
- (&wlc_hw->regs->
- clk_ctl_st) & CCS_HTAVAIL) == 0),
- PMU_MAX_TRANSITION_DLY);
- WARN_ON(!(R_REG
- (&wlc_hw->regs->
- clk_ctl_st) & CCS_HTAVAIL));
- } else {
- if ((wlc_hw->sih->pmurev == 0) &&
- (R_REG
- (&wlc_hw->regs->
- clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
- SPINWAIT(((R_REG
- (&wlc_hw->regs->
- clk_ctl_st) & CCS_HTAVAIL)
- == 0),
- PMU_MAX_TRANSITION_DLY);
- AND_REG(&wlc_hw->regs->clk_ctl_st,
- ~CCS_FORCEHT);
- }
- }
- wlc_hw->forcefastclk = (mode == CLK_FAST);
- } else {
-
- /* old chips w/o PMU, force HT through cc,
- * then use FCA to verify mac is running fast clock
- */
-
- wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
-
- /* check fast clock is available (if core is not in reset) */
- if (wlc_hw->forcefastclk && wlc_hw->clk)
- WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
- SISF_FCLKA));
-
- /* keep the ucode wake bit on if forcefastclk is on
- * since we do not want ucode to put us back to slow clock
- * when it dozes for PM mode.
- * Code below matches the wake override bit with current forcefastclk state
- * Only setting bit in wake_override instead of waking ucode immediately
- * since old code (wlc.c 1.4499) had this behavior. Older code set
- * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
- * (protected by an up check) was executed just below.
- */
- if (wlc_hw->forcefastclk)
- mboolset(wlc_hw->wake_override,
- WLC_WAKE_OVERRIDE_FORCEFAST);
- else
- mboolclr(wlc_hw->wake_override,
- WLC_WAKE_OVERRIDE_FORCEFAST);
- }
-}
-
-/* set initial host flags value */
-static void
-wlc_mhfdef(struct wlc_info *wlc, u16 *mhfs, u16 mhf2_init)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
-
- memset(mhfs, 0, MHFMAX * sizeof(u16));
-
- mhfs[MHF2] |= mhf2_init;
-
- /* prohibit use of slowclock on multifunction boards */
- if (wlc_hw->boardflags & BFL_NOPLLDOWN)
- mhfs[MHF1] |= MHF1_FORCEFASTCLK;
-
- if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
- mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
- mhfs[MHF1] |= MHF1_IQSWAP_WAR;
- }
-}
-
-/* set or clear ucode host flag bits
- * it has an optimization for no-change write
- * it only writes through shared memory when the core has clock;
- * pre-CLK changes should use wlc_write_mhf to get around the optimization
- *
- *
- * bands values are: WLC_BAND_AUTO <--- Current band only
- * WLC_BAND_5G <--- 5G band only
- * WLC_BAND_2G <--- 2G band only
- * WLC_BAND_ALL <--- All bands
- */
-void
-wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask, u16 val,
- int bands)
-{
- u16 save;
- u16 addr[MHFMAX] = {
- M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
- M_HOST_FLAGS5
- };
- struct wlc_hwband *band;
-
- if ((val & ~mask) || idx >= MHFMAX)
- return; /* error condition */
-
- switch (bands) {
- /* Current band only or all bands,
- * then set the band to current band
- */
- case WLC_BAND_AUTO:
- case WLC_BAND_ALL:
- band = wlc_hw->band;
- break;
- case WLC_BAND_5G:
- band = wlc_hw->bandstate[BAND_5G_INDEX];
- break;
- case WLC_BAND_2G:
- band = wlc_hw->bandstate[BAND_2G_INDEX];
- break;
- default:
- band = NULL; /* error condition */
- }
-
- if (band) {
- save = band->mhfs[idx];
- band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
-
- /* optimization: only write through if changed, and
- * changed band is the current band
- */
- if (wlc_hw->clk && (band->mhfs[idx] != save)
- && (band == wlc_hw->band))
- wlc_bmac_write_shm(wlc_hw, addr[idx],
- (u16) band->mhfs[idx]);
- }
-
- if (bands == WLC_BAND_ALL) {
- wlc_hw->bandstate[0]->mhfs[idx] =
- (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
- wlc_hw->bandstate[1]->mhfs[idx] =
- (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
- }
-}
-
-u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
-{
- struct wlc_hwband *band;
-
- if (idx >= MHFMAX)
- return 0; /* error condition */
- switch (bands) {
- case WLC_BAND_AUTO:
- band = wlc_hw->band;
- break;
- case WLC_BAND_5G:
- band = wlc_hw->bandstate[BAND_5G_INDEX];
- break;
- case WLC_BAND_2G:
- band = wlc_hw->bandstate[BAND_2G_INDEX];
- break;
- default:
- band = NULL; /* error condition */
- }
-
- if (!band)
- return 0;
-
- return band->mhfs[idx];
-}
-
-static void wlc_write_mhf(struct wlc_hw_info *wlc_hw, u16 *mhfs)
-{
- u8 idx;
- u16 addr[] = {
- M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
- M_HOST_FLAGS5
- };
-
- for (idx = 0; idx < MHFMAX; idx++) {
- wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
- }
-}
-
-/* set the maccontrol register to desired reset state and
- * initialize the sw cache of the register
- */
-static void wlc_mctrl_reset(struct wlc_hw_info *wlc_hw)
-{
- /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
- wlc_hw->maccontrol = 0;
- wlc_hw->suspended_fifos = 0;
- wlc_hw->wake_override = 0;
- wlc_hw->mute_override = 0;
- wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
-}
-
-/* set or clear maccontrol bits */
-void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val)
-{
- u32 maccontrol;
- u32 new_maccontrol;
-
- if (val & ~mask)
- return; /* error condition */
- maccontrol = wlc_hw->maccontrol;
- new_maccontrol = (maccontrol & ~mask) | val;
-
- /* if the new maccontrol value is the same as the old, nothing to do */
- if (new_maccontrol == maccontrol)
- return;
-
- /* something changed, cache the new value */
- wlc_hw->maccontrol = new_maccontrol;
-
- /* write the new values with overrides applied */
- wlc_mctrl_write(wlc_hw);
-}
-
-/* write the software state of maccontrol and overrides to the maccontrol register */
-static void wlc_mctrl_write(struct wlc_hw_info *wlc_hw)
-{
- u32 maccontrol = wlc_hw->maccontrol;
-
- /* OR in the wake bit if overridden */
- if (wlc_hw->wake_override)
- maccontrol |= MCTL_WAKE;
-
- /* set AP and INFRA bits for mute if needed */
- if (wlc_hw->mute_override) {
- maccontrol &= ~(MCTL_AP);
- maccontrol |= MCTL_INFRA;
- }
-
- W_REG(&wlc_hw->regs->maccontrol, maccontrol);
-}
-
-void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
-{
- if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
- mboolset(wlc_hw->wake_override, override_bit);
- return;
- }
-
- mboolset(wlc_hw->wake_override, override_bit);
-
- wlc_mctrl_write(wlc_hw);
- wlc_bmac_wait_for_wake(wlc_hw);
-
- return;
-}
-
-void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
-{
- mboolclr(wlc_hw->wake_override, override_bit);
-
- if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
- return;
-
- wlc_mctrl_write(wlc_hw);
-
- return;
-}
-
-/* When driver needs ucode to stop beaconing, it has to make sure that
- * MCTL_AP is clear and MCTL_INFRA is set
- * Mode MCTL_AP MCTL_INFRA
- * AP 1 1
- * STA 0 1 <--- This will ensure no beacons
- * IBSS 0 0
- */
-static void wlc_ucode_mute_override_set(struct wlc_hw_info *wlc_hw)
-{
- wlc_hw->mute_override = 1;
-
- /* if maccontrol already has AP == 0 and INFRA == 1 without this
- * override, then there is no change to write
- */
- if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
- return;
-
- wlc_mctrl_write(wlc_hw);
-
- return;
-}
-
-/* Clear the override on AP and INFRA bits */
-static void wlc_ucode_mute_override_clear(struct wlc_hw_info *wlc_hw)
-{
- if (wlc_hw->mute_override == 0)
- return;
-
- wlc_hw->mute_override = 0;
-
- /* if maccontrol already has AP == 0 and INFRA == 1 without this
- * override, then there is no change to write
- */
- if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
- return;
-
- wlc_mctrl_write(wlc_hw);
-}
-
-/*
- * Write a MAC address to the given match reg offset in the RXE match engine.
- */
-void
-wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw, int match_reg_offset,
- const u8 *addr)
-{
- d11regs_t *regs;
- u16 mac_l;
- u16 mac_m;
- u16 mac_h;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
- wlc_hw->unit);
-
- regs = wlc_hw->regs;
- mac_l = addr[0] | (addr[1] << 8);
- mac_m = addr[2] | (addr[3] << 8);
- mac_h = addr[4] | (addr[5] << 8);
-
- /* enter the MAC addr into the RXE match registers */
- W_REG(®s->rcm_ctl, RCM_INC_DATA | match_reg_offset);
- W_REG(®s->rcm_mat_data, mac_l);
- W_REG(®s->rcm_mat_data, mac_m);
- W_REG(®s->rcm_mat_data, mac_h);
-
-}
-
-void
-wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset, int len,
- void *buf)
-{
- d11regs_t *regs;
- u32 word;
- bool be_bit;
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- regs = wlc_hw->regs;
- W_REG(®s->tplatewrptr, offset);
-
- /* if MCTL_BIGEND bit set in mac control register,
- * the chip swaps data in fifo, as well as data in
- * template ram
- */
- be_bit = (R_REG(®s->maccontrol) & MCTL_BIGEND) != 0;
-
- while (len > 0) {
- memcpy(&word, buf, sizeof(u32));
-
- if (be_bit)
- word = cpu_to_be32(word);
- else
- word = cpu_to_le32(word);
-
- W_REG(®s->tplatewrdata, word);
-
- buf = (u8 *) buf + sizeof(u32);
- len -= sizeof(u32);
- }
-}
-
-void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin)
-{
- wlc_hw->band->CWmin = newmin;
-
- W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
- (void)R_REG(&wlc_hw->regs->objaddr);
- W_REG(&wlc_hw->regs->objdata, newmin);
-}
-
-void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax)
-{
- wlc_hw->band->CWmax = newmax;
-
- W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
- (void)R_REG(&wlc_hw->regs->objaddr);
- W_REG(&wlc_hw->regs->objdata, newmax);
-}
-
-void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw)
-{
- bool fastclk;
-
- /* request FAST clock if not on */
- fastclk = wlc_hw->forcefastclk;
- if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
-
- wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
-
- wlc_bmac_phy_reset(wlc_hw);
- wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
-
- /* restore the clk */
- if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
-}
-
-static void
-wlc_write_hw_bcntemplate0(struct wlc_hw_info *wlc_hw, void *bcn, int len)
-{
- d11regs_t *regs = wlc_hw->regs;
-
- wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
- bcn);
- /* write beacon length to SCR */
- wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
- /* mark beacon0 valid */
- OR_REG(®s->maccommand, MCMD_BCN0VLD);
-}
-
-static void
-wlc_write_hw_bcntemplate1(struct wlc_hw_info *wlc_hw, void *bcn, int len)
-{
- d11regs_t *regs = wlc_hw->regs;
-
- wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
- bcn);
- /* write beacon length to SCR */
- wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
- /* mark beacon1 valid */
- OR_REG(®s->maccommand, MCMD_BCN1VLD);
-}
-
-/* mac is assumed to be suspended at this point */
-void
-wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw, void *bcn, int len,
- bool both)
-{
- d11regs_t *regs = wlc_hw->regs;
-
- if (both) {
- wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
- wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
- } else {
- /* bcn 0 */
- if (!(R_REG(®s->maccommand) & MCMD_BCN0VLD))
- wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
- /* bcn 1 */
- else if (!
- (R_REG(®s->maccommand) & MCMD_BCN1VLD))
- wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
- }
-}
-
-static void WLBANDINITFN(wlc_bmac_upd_synthpu) (struct wlc_hw_info *wlc_hw)
-{
- u16 v;
- struct wlc_info *wlc = wlc_hw->wlc;
- /* update SYNTHPU_DLY */
-
- if (WLCISLCNPHY(wlc->band)) {
- v = SYNTHPU_DLY_LPPHY_US;
- } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
- v = SYNTHPU_DLY_NPHY_US;
- } else {
- v = SYNTHPU_DLY_BPHY_US;
- }
-
- wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
-}
-
-/* band-specific init */
-static void
-WLBANDINITFN(wlc_bmac_bsinit) (struct wlc_info *wlc, chanspec_t chanspec)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
-
- BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
- wlc_hw->band->bandunit);
-
- wlc_ucode_bsinit(wlc_hw);
-
- wlc_phy_init(wlc_hw->band->pi, chanspec);
-
- wlc_ucode_txant_set(wlc_hw);
-
- /* cwmin is band-specific, update hardware with value for current band */
- wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
- wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
-
- wlc_bmac_update_slot_timing(wlc_hw,
- BAND_5G(wlc_hw->band->
- bandtype) ? true : wlc_hw->
- shortslot);
-
- /* write phytype and phyvers */
- wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
- wlc_bmac_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
-
- /* initialize the txphyctl1 rate table since shmem is shared between bands */
- wlc_upd_ofdm_pctl1_table(wlc_hw);
-
- wlc_bmac_upd_synthpu(wlc_hw);
-}
-
-static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
-{
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
-
- wlc_hw->phyclk = clk;
-
- if (OFF == clk) { /* clear gmode bit, put phy into reset */
-
- ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
- (SICF_PRST | SICF_FGC));
- udelay(1);
- ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
- udelay(1);
-
- } else { /* take phy out of reset */
-
- ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
- udelay(1);
- ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
- udelay(1);
-
- }
-}
-
-/* Perform a soft reset of the PHY PLL */
-void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
-{
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- ai_corereg(wlc_hw->sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
- udelay(1);
- ai_corereg(wlc_hw->sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
- udelay(1);
- ai_corereg(wlc_hw->sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
- udelay(1);
- ai_corereg(wlc_hw->sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
- udelay(1);
-}
-
-/* light way to turn on phy clock without reset for NPHY only
- * refer to wlc_bmac_core_phy_clk for full version
- */
-void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk)
-{
- /* support(necessary for NPHY and HYPHY) only */
- if (!WLCISNPHY(wlc_hw->band))
- return;
-
- if (ON == clk)
- ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
- else
- ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
-
-}
-
-void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
-{
- if (ON == clk)
- ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
- else
- ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
-}
-
-void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
-{
- wlc_phy_t *pih = wlc_hw->band->pi;
- u32 phy_bw_clkbits;
- bool phy_in_reset = false;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- if (pih == NULL)
- return;
-
- phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
-
- /* Specific reset sequence required for NPHY rev 3 and 4 */
- if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
- NREV_LE(wlc_hw->band->phyrev, 4)) {
- /* Set the PHY bandwidth */
- ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
-
- udelay(1);
-
- /* Perform a soft reset of the PHY PLL */
- wlc_bmac_core_phypll_reset(wlc_hw);
-
- /* reset the PHY */
- ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
- (SICF_PRST | SICF_PCLKE));
- phy_in_reset = true;
- } else {
-
- ai_core_cflags(wlc_hw->sih,
- (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
- (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
- }
-
- udelay(2);
- wlc_bmac_core_phy_clk(wlc_hw, ON);
-
- if (pih)
- wlc_phy_anacore(pih, ON);
-}
-
-/* switch to and initialize new band */
-static void
-WLBANDINITFN(wlc_bmac_setband) (struct wlc_hw_info *wlc_hw, uint bandunit,
- chanspec_t chanspec) {
- struct wlc_info *wlc = wlc_hw->wlc;
- u32 macintmask;
-
- /* Enable the d11 core before accessing it */
- if (!ai_iscoreup(wlc_hw->sih)) {
- ai_core_reset(wlc_hw->sih, 0, 0);
- wlc_mctrl_reset(wlc_hw);
- }
-
- macintmask = wlc_setband_inact(wlc, bandunit);
-
- if (!wlc_hw->up)
- return;
-
- wlc_bmac_core_phy_clk(wlc_hw, ON);
-
- /* band-specific initializations */
- wlc_bmac_bsinit(wlc, chanspec);
-
- /*
- * If there are any pending software interrupt bits,
- * then replace these with a harmless nonzero value
- * so wlc_dpc() will re-enable interrupts when done.
- */
- if (wlc->macintstatus)
- wlc->macintstatus = MI_DMAINT;
-
- /* restore macintmask */
- brcms_intrsrestore(wlc->wl, macintmask);
-
- /* ucode should still be suspended.. */
- WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
-}
-
-/* low-level band switch utility routine */
-void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
-{
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
- bandunit);
-
- wlc_hw->band = wlc_hw->bandstate[bandunit];
-
- /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
- wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
-
- /* set gmode core flag */
- if (wlc_hw->sbclk && !wlc_hw->noreset) {
- ai_core_cflags(wlc_hw->sih, SICF_GMODE,
- ((bandunit == 0) ? SICF_GMODE : 0));
- }
-}
-
-static bool wlc_isgoodchip(struct wlc_hw_info *wlc_hw)
-{
-
- /* reject unsupported corerev */
- if (!VALID_COREREV(wlc_hw->corerev)) {
- wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
- wlc_hw->corerev);
- return false;
- }
-
- return true;
-}
-
-static bool wlc_validboardtype(struct wlc_hw_info *wlc_hw)
-{
- bool goodboard = true;
- uint boardrev = wlc_hw->boardrev;
-
- if (boardrev == 0)
- goodboard = false;
- else if (boardrev > 0xff) {
- uint brt = (boardrev & 0xf000) >> 12;
- uint b0 = (boardrev & 0xf00) >> 8;
- uint b1 = (boardrev & 0xf0) >> 4;
- uint b2 = boardrev & 0xf;
-
- if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
- || (b2 > 9))
- goodboard = false;
- }
-
- if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
- return goodboard;
-
- return goodboard;
-}
-
-static char *wlc_get_macaddr(struct wlc_hw_info *wlc_hw)
-{
- const char *varname = "macaddr";
- char *macaddr;
-
- /* If macaddr exists, use it (Sromrev4, CIS, ...). */
- macaddr = getvar(wlc_hw->vars, varname);
- if (macaddr != NULL)
- return macaddr;
-
- if (NBANDS_HW(wlc_hw) > 1)
- varname = "et1macaddr";
- else
- varname = "il0macaddr";
-
- macaddr = getvar(wlc_hw->vars, varname);
- if (macaddr == NULL) {
- wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
- "getvar(%s) not found\n", wlc_hw->unit, varname);
- }
-
- return macaddr;
-}
-
-/*
- * Return true if radio is disabled, otherwise false.
- * hw radio disable signal is an external pin, users activate it asynchronously
- * this function could be called when driver is down and w/o clock
- * it operates on different registers depending on corerev and boardflag.
- */
-bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw)
-{
- bool v, clk, xtal;
- u32 resetbits = 0, flags = 0;
-
- xtal = wlc_hw->sbclk;
- if (!xtal)
- wlc_bmac_xtal(wlc_hw, ON);
-
- /* may need to take core out of reset first */
- clk = wlc_hw->clk;
- if (!clk) {
- /*
- * mac no longer enables phyclk automatically when driver
- * accesses phyreg throughput mac. This can be skipped since
- * only mac reg is accessed below
- */
- flags |= SICF_PCLKE;
-
- /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
- if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
- (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
- (wlc_hw->sih->chip == BCM43421_CHIP_ID))
- wlc_hw->regs =
- (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
- 0);
- ai_core_reset(wlc_hw->sih, flags, resetbits);
- wlc_mctrl_reset(wlc_hw);
- }
-
- v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
-
- /* put core back into reset */
- if (!clk)
- ai_core_disable(wlc_hw->sih, 0);
-
- if (!xtal)
- wlc_bmac_xtal(wlc_hw, OFF);
-
- return v;
-}
-
-/* Initialize just the hardware when coming out of POR or S3/S5 system states */
-void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw)
-{
- if (wlc_hw->wlc->pub->hw_up)
- return;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- /*
- * Enable pll and xtal, initialize the power control registers,
- * and force fastclock for the remainder of wlc_up().
- */
- wlc_bmac_xtal(wlc_hw, ON);
- ai_clkctl_init(wlc_hw->sih);
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
-
- if (wlc_hw->sih->bustype == PCI_BUS) {
- ai_pci_fixcfg(wlc_hw->sih);
-
- /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
- if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
- (wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
- (wlc_hw->sih->chip == BCM43421_CHIP_ID))
- wlc_hw->regs =
- (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
- 0);
- }
-
- /* Inform phy that a POR reset has occurred so it does a complete phy init */
- wlc_phy_por_inform(wlc_hw->band->pi);
-
- wlc_hw->ucode_loaded = false;
- wlc_hw->wlc->pub->hw_up = true;
-
- if ((wlc_hw->boardflags & BFL_FEM)
- && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
- if (!
- (wlc_hw->boardrev >= 0x1250
- && (wlc_hw->boardflags & BFL_FEM_BT)))
- ai_epa_4313war(wlc_hw->sih);
- }
-}
-
-static bool wlc_dma_rxreset(struct wlc_hw_info *wlc_hw, uint fifo)
-{
- struct dma_pub *di = wlc_hw->di[fifo];
- return dma_rxreset(di);
-}
-
-/* d11 core reset
- * ensure fask clock during reset
- * reset dma
- * reset d11(out of reset)
- * reset phy(out of reset)
- * clear software macintstatus for fresh new start
- * one testing hack wlc_hw->noreset will bypass the d11/phy reset
- */
-void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags)
-{
- d11regs_t *regs;
- uint i;
- bool fastclk;
- u32 resetbits = 0;
-
- if (flags == WLC_USE_COREFLAGS)
- flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- regs = wlc_hw->regs;
-
- /* request FAST clock if not on */
- fastclk = wlc_hw->forcefastclk;
- if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
-
- /* reset the dma engines except first time thru */
- if (ai_iscoreup(wlc_hw->sih)) {
- for (i = 0; i < NFIFO; i++)
- if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
- wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
- "dma_txreset[%d]: cannot stop dma\n",
- wlc_hw->unit, __func__, i);
- }
-
- if ((wlc_hw->di[RX_FIFO])
- && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
- wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
- "[%d]: cannot stop dma\n",
- wlc_hw->unit, __func__, RX_FIFO);
- }
- }
- /* if noreset, just stop the psm and return */
- if (wlc_hw->noreset) {
- wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
- wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
- return;
- }
-
- /*
- * mac no longer enables phyclk automatically when driver accesses
- * phyreg throughput mac, AND phy_reset is skipped at early stage when
- * band->pi is invalid. need to enable PHY CLK
- */
- flags |= SICF_PCLKE;
-
- /* reset the core
- * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
- * is cleared by the core_reset. have to re-request it.
- * This adds some delay and we can optimize it by also requesting fastclk through
- * chipcommon during this period if necessary. But that has to work coordinate
- * with other driver like mips/arm since they may touch chipcommon as well.
- */
- wlc_hw->clk = false;
- ai_core_reset(wlc_hw->sih, flags, resetbits);
- wlc_hw->clk = true;
- if (wlc_hw->band && wlc_hw->band->pi)
- wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
-
- wlc_mctrl_reset(wlc_hw);
-
- if (PMUCTL_ENAB(wlc_hw->sih))
- wlc_clkctl_clk(wlc_hw, CLK_FAST);
-
- wlc_bmac_phy_reset(wlc_hw);
-
- /* turn on PHY_PLL */
- wlc_bmac_core_phypll_ctl(wlc_hw, true);
-
- /* clear sw intstatus */
- wlc_hw->wlc->macintstatus = 0;
-
- /* restore the clk setting */
- if (!fastclk)
- wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
-}
-
-/* txfifo sizes needs to be modified(increased) since the newer cores
- * have more memory.
- */
-static void wlc_corerev_fifofixup(struct wlc_hw_info *wlc_hw)
-{
- d11regs_t *regs = wlc_hw->regs;
- u16 fifo_nu;
- u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
- u16 txfifo_def, txfifo_def1;
- u16 txfifo_cmd;
-
- /* tx fifos start at TXFIFO_START_BLK from the Base address */
- txfifo_startblk = TXFIFO_START_BLK;
-
- /* sequence of operations: reset fifo, set fifo size, reset fifo */
- for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
-
- txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
- txfifo_def = (txfifo_startblk & 0xff) |
- (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
- txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
- ((((txfifo_endblk -
- 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
- txfifo_cmd =
- TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
-
- W_REG(®s->xmtfifocmd, txfifo_cmd);
- W_REG(®s->xmtfifodef, txfifo_def);
- W_REG(®s->xmtfifodef1, txfifo_def1);
-
- W_REG(®s->xmtfifocmd, txfifo_cmd);
-
- txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
- }
- /*
- * need to propagate to shm location to be in sync since ucode/hw won't
- * do this
- */
- wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
- wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
- wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
- wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
- wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
- ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
- xmtfifo_sz[TX_AC_BK_FIFO]));
- wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
- ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
- xmtfifo_sz[TX_BCMC_FIFO]));
-}
-
-/* d11 core init
- * reset PSM
- * download ucode/PCM
- * let ucode run to suspended
- * download ucode inits
- * config other core registers
- * init dma
- */
-static void wlc_coreinit(struct wlc_info *wlc)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- d11regs_t *regs;
- u32 sflags;
- uint bcnint_us;
- uint i = 0;
- bool fifosz_fixup = false;
- int err = 0;
- u16 buf[NFIFO];
- struct wiphy *wiphy = wlc->wiphy;
-
- regs = wlc_hw->regs;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- /* reset PSM */
- wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
-
- wlc_ucode_download(wlc_hw);
- /*
- * FIFOSZ fixup. driver wants to controls the fifo allocation.
- */
- fifosz_fixup = true;
-
- /* let the PSM run to the suspended state, set mode to BSS STA */
- W_REG(®s->macintstatus, -1);
- wlc_bmac_mctrl(wlc_hw, ~0,
- (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
-
- /* wait for ucode to self-suspend after auto-init */
- SPINWAIT(((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0),
- 1000 * 1000);
- if ((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0)
- wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
- "suspend!\n", wlc_hw->unit);
-
- wlc_gpio_init(wlc);
-
- sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
-
- if (D11REV_IS(wlc_hw->corerev, 23)) {
- if (WLCISNPHY(wlc_hw->band))
- wlc_write_inits(wlc_hw, d11n0initvals16);
- else
- wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
- " %d\n", __func__, wlc_hw->unit,
- wlc_hw->corerev);
- } else if (D11REV_IS(wlc_hw->corerev, 24)) {
- if (WLCISLCNPHY(wlc_hw->band)) {
- wlc_write_inits(wlc_hw, d11lcn0initvals24);
- } else {
- wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
- " %d\n", __func__, wlc_hw->unit,
- wlc_hw->corerev);
- }
- } else {
- wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
- }
-
- /* For old ucode, txfifo sizes needs to be modified(increased) */
- if (fifosz_fixup == true) {
- wlc_corerev_fifofixup(wlc_hw);
- }
-
- /* check txfifo allocations match between ucode and driver */
- buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
- if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
- i = TX_AC_BE_FIFO;
- err = -1;
- }
- buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
- if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
- i = TX_AC_VI_FIFO;
- err = -1;
- }
- buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
- buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
- buf[TX_AC_BK_FIFO] &= 0xff;
- if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
- i = TX_AC_BK_FIFO;
- err = -1;
- }
- if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
- i = TX_AC_VO_FIFO;
- err = -1;
- }
- buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
- buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
- buf[TX_BCMC_FIFO] &= 0xff;
- if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
- i = TX_BCMC_FIFO;
- err = -1;
- }
- if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
- i = TX_ATIM_FIFO;
- err = -1;
- }
- if (err != 0) {
- wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
- " driver size %d index %d\n", buf[i],
- wlc_hw->xmtfifo_sz[i], i);
- }
-
- /* make sure we can still talk to the mac */
- WARN_ON(R_REG(®s->maccontrol) == 0xffffffff);
-
- /* band-specific inits done by wlc_bsinit() */
-
- /* Set up frame burst size and antenna swap threshold init values */
- wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
- wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
-
- /* enable one rx interrupt per received frame */
- W_REG(®s->intrcvlazy[0], (1 << IRL_FC_SHIFT));
-
- /* set the station mode (BSS STA) */
- wlc_bmac_mctrl(wlc_hw,
- (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
- (MCTL_INFRA | MCTL_DISCARD_PMQ));
-
- /* set up Beacon interval */
- bcnint_us = 0x8000 << 10;
- W_REG(®s->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
- W_REG(®s->tsf_cfpstart, bcnint_us);
- W_REG(®s->macintstatus, MI_GP1);
-
- /* write interrupt mask */
- W_REG(®s->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
-
- /* allow the MAC to control the PHY clock (dynamic on/off) */
- wlc_bmac_macphyclk_set(wlc_hw, ON);
-
- /* program dynamic clock control fast powerup delay register */
- wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
- W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
-
- /* tell the ucode the corerev */
- wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
-
- /* tell the ucode MAC capabilities */
- wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
- (u16) (wlc_hw->machwcap & 0xffff));
- wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
- (u16) ((wlc_hw->
- machwcap >> 16) & 0xffff));
-
- /* write retry limits to SCR, this done after PSM init */
- W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
- (void)R_REG(®s->objaddr);
- W_REG(®s->objdata, wlc_hw->SRL);
- W_REG(®s->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
- (void)R_REG(®s->objaddr);
- W_REG(®s->objdata, wlc_hw->LRL);
-
- /* write rate fallback retry limits */
- wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
- wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
-
- AND_REG(®s->ifs_ctl, 0x0FFF);
- W_REG(®s->ifs_aifsn, EDCF_AIFSN_MIN);
-
- /* dma initializations */
- wlc->txpend16165war = 0;
-
- /* init the tx dma engines */
- for (i = 0; i < NFIFO; i++) {
- if (wlc_hw->di[i])
- dma_txinit(wlc_hw->di[i]);
- }
-
- /* init the rx dma engine(s) and post receive buffers */
- dma_rxinit(wlc_hw->di[RX_FIFO]);
- dma_rxfill(wlc_hw->di[RX_FIFO]);
-}
-
-/* This function is used for changing the tsf frac register
- * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
- * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
- * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
- * HTPHY Formula is 2^26/freq(MHz) e.g.
- * For spuron2 - 126MHz -> 2^26/126 = 532610.0
- * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
- * For spuron: 123MHz -> 2^26/123 = 545600.5
- * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
- * For spur off: 120MHz -> 2^26/120 = 559240.5
- * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
- */
-
-void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode)
-{
- d11regs_t *regs;
- regs = wlc_hw->regs;
-
- if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
- (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
- if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
- W_REG(®s->tsf_clk_frac_l, 0x2082);
- W_REG(®s->tsf_clk_frac_h, 0x8);
- } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
- W_REG(®s->tsf_clk_frac_l, 0x5341);
- W_REG(®s->tsf_clk_frac_h, 0x8);
- } else { /* 120Mhz */
- W_REG(®s->tsf_clk_frac_l, 0x8889);
- W_REG(®s->tsf_clk_frac_h, 0x8);
- }
- } else if (WLCISLCNPHY(wlc_hw->band)) {
- if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
- W_REG(®s->tsf_clk_frac_l, 0x7CE0);
- W_REG(®s->tsf_clk_frac_h, 0xC);
- } else { /* 80Mhz */
- W_REG(®s->tsf_clk_frac_l, 0xCCCD);
- W_REG(®s->tsf_clk_frac_h, 0xC);
- }
- }
-}
-
-/* Initialize GPIOs that are controlled by D11 core */
-static void wlc_gpio_init(struct wlc_info *wlc)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- d11regs_t *regs;
- u32 gc, gm;
-
- regs = wlc_hw->regs;
-
- /* use GPIO select 0 to get all gpio signals from the gpio out reg */
- wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
-
- /*
- * Common GPIO setup:
- * G0 = LED 0 = WLAN Activity
- * G1 = LED 1 = WLAN 2.4 GHz Radio State
- * G2 = LED 2 = WLAN 5 GHz Radio State
- * G4 = radio disable input (HI enabled, LO disabled)
- */
-
- gc = gm = 0;
-
- /* Allocate GPIOs for mimo antenna diversity feature */
- if (wlc_hw->antsel_type == ANTSEL_2x3) {
- /* Enable antenna diversity, use 2x3 mode */
- wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
- MHF3_ANTSEL_EN, WLC_BAND_ALL);
- wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
- MHF3_ANTSEL_MODE, WLC_BAND_ALL);
-
- /* init superswitch control */
- wlc_phy_antsel_init(wlc_hw->band->pi, false);
-
- } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
- gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
- /*
- * The board itself is powered by these GPIOs
- * (when not sending pattern) so set them high
- */
- OR_REG(®s->psm_gpio_oe,
- (BOARD_GPIO_12 | BOARD_GPIO_13));
- OR_REG(®s->psm_gpio_out,
- (BOARD_GPIO_12 | BOARD_GPIO_13));
-
- /* Enable antenna diversity, use 2x4 mode */
- wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
- MHF3_ANTSEL_EN, WLC_BAND_ALL);
- wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
- WLC_BAND_ALL);
-
- /* Configure the desired clock to be 4Mhz */
- wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
- ANTSEL_CLKDIV_4MHZ);
- }
-
- /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
- if (wlc_hw->boardflags & BFL_PACTRL)
- gm |= gc |= BOARD_GPIO_PACTRL;
-
- /* apply to gpiocontrol register */
- ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
-}
-
-static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
-{
- struct wlc_info *wlc;
- wlc = wlc_hw->wlc;
-
- if (wlc_hw->ucode_loaded)
- return;
-
- if (D11REV_IS(wlc_hw->corerev, 23)) {
- if (WLCISNPHY(wlc_hw->band)) {
- wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
- bcm43xx_16_mimosz);
- wlc_hw->ucode_loaded = true;
- } else
- wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
- "corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
- } else if (D11REV_IS(wlc_hw->corerev, 24)) {
- if (WLCISLCNPHY(wlc_hw->band)) {
- wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
- bcm43xx_24_lcnsz);
- wlc_hw->ucode_loaded = true;
- } else {
- wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
- "corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
- }
- }
-}
-
-static void wlc_ucode_write(struct wlc_hw_info *wlc_hw, const u32 ucode[],
- const uint nbytes) {
- d11regs_t *regs = wlc_hw->regs;
- uint i;
- uint count;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- count = (nbytes / sizeof(u32));
-
- W_REG(®s->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
- (void)R_REG(®s->objaddr);
- for (i = 0; i < count; i++)
- W_REG(®s->objdata, ucode[i]);
-}
-
-static void wlc_write_inits(struct wlc_hw_info *wlc_hw,
- const struct d11init *inits)
-{
- int i;
- volatile u8 *base;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- base = (volatile u8 *)wlc_hw->regs;
-
- for (i = 0; inits[i].addr != 0xffff; i++) {
- if (inits[i].size == 2)
- W_REG((u16 *)(base + inits[i].addr),
- inits[i].value);
- else if (inits[i].size == 4)
- W_REG((u32 *)(base + inits[i].addr),
- inits[i].value);
- }
-}
-
-static void wlc_ucode_txant_set(struct wlc_hw_info *wlc_hw)
-{
- u16 phyctl;
- u16 phytxant = wlc_hw->bmac_phytxant;
- u16 mask = PHY_TXC_ANT_MASK;
-
- /* set the Probe Response frame phy control word */
- phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
- phyctl = (phyctl & ~mask) | phytxant;
- wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
-
- /* set the Response (ACK/CTS) frame phy control word */
- phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
- phyctl = (phyctl & ~mask) | phytxant;
- wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
-}
-
-void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant)
-{
- /* update sw state */
- wlc_hw->bmac_phytxant = phytxant;
-
- /* push to ucode if up */
- if (!wlc_hw->up)
- return;
- wlc_ucode_txant_set(wlc_hw);
-
-}
-
-u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw)
-{
- return (u16) wlc_hw->wlc->stf->txant;
-}
-
-void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw, u8 antsel_type)
-{
- wlc_hw->antsel_type = antsel_type;
-
- /* Update the antsel type for phy module to use */
- wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
-}
-
-void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw)
-{
- bool fatal = false;
- uint unit;
- uint intstatus, idx;
- d11regs_t *regs = wlc_hw->regs;
- struct wiphy *wiphy = wlc_hw->wlc->wiphy;
-
- unit = wlc_hw->unit;
-
- for (idx = 0; idx < NFIFO; idx++) {
- /* read intstatus register and ignore any non-error bits */
- intstatus =
- R_REG(®s->intctrlregs[idx].intstatus) & I_ERRORS;
- if (!intstatus)
- continue;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
- unit, idx, intstatus);
-
- if (intstatus & I_RO) {
- wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
- "overflow\n", unit, idx);
- fatal = true;
- }
-
- if (intstatus & I_PC) {
- wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
- unit, idx);
- fatal = true;
- }
-
- if (intstatus & I_PD) {
- wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
- idx);
- fatal = true;
- }
-
- if (intstatus & I_DE) {
- wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
- "error\n", unit, idx);
- fatal = true;
- }
-
- if (intstatus & I_RU) {
- wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
- "underflow\n", idx, unit);
- }
-
- if (intstatus & I_XU) {
- wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
- "underflow\n", idx, unit);
- fatal = true;
- }
-
- if (fatal) {
- wlc_fatal_error(wlc_hw->wlc); /* big hammer */
- break;
- } else
- W_REG(®s->intctrlregs[idx].intstatus,
- intstatus);
- }
-}
-
-void wlc_intrson(struct wlc_info *wlc)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- wlc->macintmask = wlc->defmacintmask;
- W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
-}
-
-/* callback for siutils.c, which has only wlc handler, no wl
- * they both check up, not only because there is no need to off/restore d11 interrupt
- * but also because per-port code may require sync with valid interrupt.
- */
-
-static u32 wlc_wlintrsoff(struct wlc_info *wlc)
-{
- if (!wlc->hw->up)
- return 0;
-
- return brcms_intrsoff(wlc->wl);
-}
-
-static void wlc_wlintrsrestore(struct wlc_info *wlc, u32 macintmask)
-{
- if (!wlc->hw->up)
- return;
-
- brcms_intrsrestore(wlc->wl, macintmask);
-}
-
-u32 wlc_intrsoff(struct wlc_info *wlc)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- u32 macintmask;
-
- if (!wlc_hw->clk)
- return 0;
-
- macintmask = wlc->macintmask; /* isr can still happen */
-
- W_REG(&wlc_hw->regs->macintmask, 0);
- (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
- udelay(1); /* ensure int line is no longer driven */
- wlc->macintmask = 0;
-
- /* return previous macintmask; resolve race between us and our isr */
- return wlc->macintstatus ? 0 : macintmask;
-}
-
-void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- if (!wlc_hw->clk)
- return;
-
- wlc->macintmask = macintmask;
- W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
-}
-
-static void wlc_bmac_mute(struct wlc_hw_info *wlc_hw, bool on, mbool flags)
-{
- u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
-
- if (on) {
- /* suspend tx fifos */
- wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
- wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
- wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
- wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
-
- /* zero the address match register so we do not send ACKs */
- wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
- null_ether_addr);
- } else {
- /* resume tx fifos */
- if (!wlc_hw->wlc->tx_suspended) {
- wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
- }
- wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
- wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
- wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
-
- /* Restore address */
- wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
- wlc_hw->etheraddr);
- }
-
- wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
-
- if (on)
- wlc_ucode_mute_override_set(wlc_hw);
- else
- wlc_ucode_mute_override_clear(wlc_hw);
-}
-
-int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
-{
- if (fifo >= NFIFO)
- return -EINVAL;
-
- *blocks = wlc_hw->xmtfifo_sz[fifo];
-
- return 0;
-}
-
-/* wlc_bmac_tx_fifo_suspended:
- * Check the MAC's tx suspend status for a tx fifo.
- *
- * When the MAC acknowledges a tx suspend, it indicates that no more
- * packets will be transmitted out the radio. This is independent of
- * DMA channel suspension---the DMA may have finished suspending, or may still
- * be pulling data into a tx fifo, by the time the MAC acks the suspend
- * request.
- */
-static bool wlc_bmac_tx_fifo_suspended(struct wlc_hw_info *wlc_hw, uint tx_fifo)
-{
- /* check that a suspend has been requested and is no longer pending */
-
- /*
- * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
- * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
- * chnstatus register.
- * The tx fifo suspend completion is independent of the DMA suspend completion and
- * may be acked before or after the DMA is suspended.
- */
- if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
- (R_REG(&wlc_hw->regs->chnstatus) &
- (1 << tx_fifo)) == 0)
- return true;
-
- return false;
-}
-
-static void wlc_bmac_tx_fifo_suspend(struct wlc_hw_info *wlc_hw, uint tx_fifo)
-{
- u8 fifo = 1 << tx_fifo;
-
- /* Two clients of this code, 11h Quiet period and scanning. */
-
- /* only suspend if not already suspended */
- if ((wlc_hw->suspended_fifos & fifo) == fifo)
- return;
-
- /* force the core awake only if not already */
- if (wlc_hw->suspended_fifos == 0)
- wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
-
- wlc_hw->suspended_fifos |= fifo;
-
- if (wlc_hw->di[tx_fifo]) {
- /* Suspending AMPDU transmissions in the middle can cause underflow
- * which may result in mismatch between ucode and driver
- * so suspend the mac before suspending the FIFO
- */
- if (WLC_PHY_11N_CAP(wlc_hw->band))
- wlc_suspend_mac_and_wait(wlc_hw->wlc);
-
- dma_txsuspend(wlc_hw->di[tx_fifo]);
-
- if (WLC_PHY_11N_CAP(wlc_hw->band))
- wlc_enable_mac(wlc_hw->wlc);
- }
-}
-
-static void wlc_bmac_tx_fifo_resume(struct wlc_hw_info *wlc_hw, uint tx_fifo)
-{
- /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
- * here for PIO otherwise the watchdog will catch the inconsistency and fire
- */
- /* Two clients of this code, 11h Quiet period and scanning. */
- if (wlc_hw->di[tx_fifo])
- dma_txresume(wlc_hw->di[tx_fifo]);
-
- /* allow core to sleep again */
- if (wlc_hw->suspended_fifos == 0)
- return;
- else {
- wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
- if (wlc_hw->suspended_fifos == 0)
- wlc_ucode_wake_override_clear(wlc_hw,
- WLC_WAKE_OVERRIDE_TXFIFO);
- }
-}
-
-/*
- * Read and clear macintmask and macintstatus and intstatus registers.
- * This routine should be called with interrupts off
- * Return:
- * -1 if DEVICEREMOVED(wlc) evaluates to true;
- * 0 if the interrupt is not for us, or we are in some special cases;
- * device interrupt status bits otherwise.
- */
-static inline u32 wlc_intstatus(struct wlc_info *wlc, bool in_isr)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- d11regs_t *regs = wlc_hw->regs;
- u32 macintstatus;
-
- /* macintstatus includes a DMA interrupt summary bit */
- macintstatus = R_REG(®s->macintstatus);
-
- BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
- macintstatus);
-
- /* detect cardbus removed, in power down(suspend) and in reset */
- if (DEVICEREMOVED(wlc))
- return -1;
-
- /* DEVICEREMOVED succeeds even when the core is still resetting,
- * handle that case here.
- */
- if (macintstatus == 0xffffffff)
- return 0;
-
- /* defer unsolicited interrupts */
- macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
-
- /* if not for us */
- if (macintstatus == 0)
- return 0;
-
- /* interrupts are already turned off for CFE build
- * Caution: For CFE Turning off the interrupts again has some undesired
- * consequences
- */
- /* turn off the interrupts */
- W_REG(®s->macintmask, 0);
- (void)R_REG(®s->macintmask); /* sync readback */
- wlc->macintmask = 0;
-
- /* clear device interrupts */
- W_REG(®s->macintstatus, macintstatus);
-
- /* MI_DMAINT is indication of non-zero intstatus */
- if (macintstatus & MI_DMAINT) {
- /*
- * only fifo interrupt enabled is I_RI in
- * RX_FIFO. If MI_DMAINT is set, assume it
- * is set and clear the interrupt.
- */
- W_REG(®s->intctrlregs[RX_FIFO].intstatus,
- DEF_RXINTMASK);
- }
-
- return macintstatus;
-}
-
-/* Update wlc->macintstatus and wlc->intstatus[]. */
-/* Return true if they are updated successfully. false otherwise */
-bool wlc_intrsupd(struct wlc_info *wlc)
-{
- u32 macintstatus;
-
- /* read and clear macintstatus and intstatus registers */
- macintstatus = wlc_intstatus(wlc, false);
-
- /* device is removed */
- if (macintstatus == 0xffffffff)
- return false;
-
- /* update interrupt status in software */
- wlc->macintstatus |= macintstatus;
-
- return true;
-}
-
-/*
- * First-level interrupt processing.
- * Return true if this was our interrupt, false otherwise.
- * *wantdpc will be set to true if further wlc_dpc() processing is required,
- * false otherwise.
- */
-bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- u32 macintstatus;
-
- *wantdpc = false;
-
- if (!wlc_hw->up || !wlc->macintmask)
- return false;
-
- /* read and clear macintstatus and intstatus registers */
- macintstatus = wlc_intstatus(wlc, true);
-
- if (macintstatus == 0xffffffff)
- wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
- " path\n");
-
- /* it is not for us */
- if (macintstatus == 0)
- return false;
-
- *wantdpc = true;
-
- /* save interrupt status bits */
- wlc->macintstatus = macintstatus;
-
- return true;
-
-}
-
-static bool
-wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
-{
- /* discard intermediate indications for ucode with one legitimate case:
- * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
- * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
- * transmission count)
- */
- if (!(txs->status & TX_STATUS_AMPDU)
- && (txs->status & TX_STATUS_INTERMEDIATE)) {
- return false;
- }
-
- return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
-}
-
-/* process tx completion events in BMAC
- * Return true if more tx status need to be processed. false otherwise.
- */
-static bool
-wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
-{
- bool morepending = false;
- struct wlc_info *wlc = wlc_hw->wlc;
- d11regs_t *regs;
- tx_status_t txstatus, *txs;
- u32 s1, s2;
- uint n = 0;
- /*
- * Param 'max_tx_num' indicates max. # tx status to process before
- * break out.
- */
- uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- txs = &txstatus;
- regs = wlc_hw->regs;
- while (!(*fatal)
- && (s1 = R_REG(®s->frmtxstatus)) & TXS_V) {
-
- if (s1 == 0xffffffff) {
- wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
- wlc_hw->unit, __func__);
- return morepending;
- }
-
- s2 = R_REG(®s->frmtxstatus2);
-
- txs->status = s1 & TXS_STATUS_MASK;
- txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
- txs->sequence = s2 & TXS_SEQ_MASK;
- txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
- txs->lasttxtime = 0;
-
- *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
-
- /* !give others some time to run! */
- if (++n >= max_tx_num)
- break;
- }
-
- if (*fatal)
- return 0;
-
- if (n >= max_tx_num)
- morepending = true;
-
- if (!pktq_empty(&wlc->pkt_queue->q))
- wlc_send_q(wlc);
-
- return morepending;
-}
-
-void wlc_suspend_mac_and_wait(struct wlc_info *wlc)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- d11regs_t *regs = wlc_hw->regs;
- u32 mc, mi;
- struct wiphy *wiphy = wlc->wiphy;
-
- BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
- wlc_hw->band->bandunit);
-
- /*
- * Track overlapping suspend requests
- */
- wlc_hw->mac_suspend_depth++;
- if (wlc_hw->mac_suspend_depth > 1)
- return;
-
- /* force the core awake */
- wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
-
- mc = R_REG(®s->maccontrol);
-
- if (mc == 0xffffffff) {
- wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
- __func__);
- brcms_down(wlc->wl);
- return;
- }
- WARN_ON(mc & MCTL_PSM_JMP_0);
- WARN_ON(!(mc & MCTL_PSM_RUN));
- WARN_ON(!(mc & MCTL_EN_MAC));
-
- mi = R_REG(®s->macintstatus);
- if (mi == 0xffffffff) {
- wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
- __func__);
- brcms_down(wlc->wl);
- return;
- }
- WARN_ON(mi & MI_MACSSPNDD);
-
- wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
-
- SPINWAIT(!(R_REG(®s->macintstatus) & MI_MACSSPNDD),
- WLC_MAX_MAC_SUSPEND);
-
- if (!(R_REG(®s->macintstatus) & MI_MACSSPNDD)) {
- wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
- " and MI_MACSSPNDD is still not on.\n",
- wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
- wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
- "psm_brc 0x%04x\n", wlc_hw->unit,
- R_REG(®s->psmdebug),
- R_REG(®s->phydebug),
- R_REG(®s->psm_brc));
- }
-
- mc = R_REG(®s->maccontrol);
- if (mc == 0xffffffff) {
- wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
- __func__);
- brcms_down(wlc->wl);
- return;
- }
- WARN_ON(mc & MCTL_PSM_JMP_0);
- WARN_ON(!(mc & MCTL_PSM_RUN));
- WARN_ON(mc & MCTL_EN_MAC);
-}
-
-void wlc_enable_mac(struct wlc_info *wlc)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- d11regs_t *regs = wlc_hw->regs;
- u32 mc, mi;
-
- BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
- wlc->band->bandunit);
-
- /*
- * Track overlapping suspend requests
- */
- wlc_hw->mac_suspend_depth--;
- if (wlc_hw->mac_suspend_depth > 0)
- return;
-
- mc = R_REG(®s->maccontrol);
- WARN_ON(mc & MCTL_PSM_JMP_0);
- WARN_ON(mc & MCTL_EN_MAC);
- WARN_ON(!(mc & MCTL_PSM_RUN));
-
- wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
- W_REG(®s->macintstatus, MI_MACSSPNDD);
-
- mc = R_REG(®s->maccontrol);
- WARN_ON(mc & MCTL_PSM_JMP_0);
- WARN_ON(!(mc & MCTL_EN_MAC));
- WARN_ON(!(mc & MCTL_PSM_RUN));
-
- mi = R_REG(®s->macintstatus);
- WARN_ON(mi & MI_MACSSPNDD);
-
- wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
-}
-
-static void wlc_upd_ofdm_pctl1_table(struct wlc_hw_info *wlc_hw)
-{
- u8 rate;
- u8 rates[8] = {
- WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
- WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
- };
- u16 entry_ptr;
- u16 pctl1;
- uint i;
-
- if (!WLC_PHY_11N_CAP(wlc_hw->band))
- return;
-
- /* walk the phy rate table and update the entries */
- for (i = 0; i < ARRAY_SIZE(rates); i++) {
- rate = rates[i];
-
- entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
-
- /* read the SHM Rate Table entry OFDM PCTL1 values */
- pctl1 =
- wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
-
- /* modify the value */
- pctl1 &= ~PHY_TXC1_MODE_MASK;
- pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
-
- /* Update the SHM Rate Table entry OFDM PCTL1 values */
- wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
- pctl1);
- }
-}
-
-static u16 wlc_bmac_ofdm_ratetable_offset(struct wlc_hw_info *wlc_hw, u8 rate)
-{
- uint i;
- u8 plcp_rate = 0;
- struct plcp_signal_rate_lookup {
- u8 rate;
- u8 signal_rate;
- };
- /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
- const struct plcp_signal_rate_lookup rate_lookup[] = {
- {WLC_RATE_6M, 0xB},
- {WLC_RATE_9M, 0xF},
- {WLC_RATE_12M, 0xA},
- {WLC_RATE_18M, 0xE},
- {WLC_RATE_24M, 0x9},
- {WLC_RATE_36M, 0xD},
- {WLC_RATE_48M, 0x8},
- {WLC_RATE_54M, 0xC}
- };
-
- for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
- if (rate == rate_lookup[i].rate) {
- plcp_rate = rate_lookup[i].signal_rate;
- break;
- }
- }
-
- /* Find the SHM pointer to the rate table entry by looking in the
- * Direct-map Table
- */
- return 2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
-}
-
-void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode)
-{
- wlc_hw->hw_stf_ss_opmode = stf_mode;
-
- if (wlc_hw->clk)
- wlc_upd_ofdm_pctl1_table(wlc_hw);
-}
-
-void
-wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
- u32 *tsf_h_ptr)
-{
- d11regs_t *regs = wlc_hw->regs;
-
- /* read the tsf timer low, then high to get an atomic read */
- *tsf_l_ptr = R_REG(®s->tsf_timerlow);
- *tsf_h_ptr = R_REG(®s->tsf_timerhigh);
-
- return;
-}
-
-static bool wlc_bmac_validate_chip_access(struct wlc_hw_info *wlc_hw)
-{
- d11regs_t *regs;
- u32 w, val;
- struct wiphy *wiphy = wlc_hw->wlc->wiphy;
-
- BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
-
- regs = wlc_hw->regs;
-
- /* Validate dchip register access */
-
- W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
- (void)R_REG(®s->objaddr);
- w = R_REG(®s->objdata);
-
- /* Can we write and read back a 32bit register? */
- W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
- (void)R_REG(®s->objaddr);
- W_REG(®s->objdata, (u32) 0xaa5555aa);
-
- W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
- (void)R_REG(®s->objaddr);
- val = R_REG(®s->objdata);
- if (val != (u32) 0xaa5555aa) {
- wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
- "expected 0xaa5555aa\n", wlc_hw->unit, val);
- return false;
- }
-
- W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
- (void)R_REG(®s->objaddr);
- W_REG(®s->objdata, (u32) 0x55aaaa55);
-
- W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
- (void)R_REG(®s->objaddr);
- val = R_REG(®s->objdata);
- if (val != (u32) 0x55aaaa55) {
- wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
- "expected 0x55aaaa55\n", wlc_hw->unit, val);
- return false;
- }
-
- W_REG(®s->objaddr, OBJADDR_SHM_SEL | 0);
- (void)R_REG(®s->objaddr);
- W_REG(®s->objdata, w);
-
- /* clear CFPStart */
- W_REG(®s->tsf_cfpstart, 0);
-
- w = R_REG(®s->maccontrol);
- if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
- (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
- wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
- "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
- (MCTL_IHR_EN | MCTL_WAKE),
- (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
- return false;
- }
-
- return true;
-}
-
-#define PHYPLL_WAIT_US 100000
-
-void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on)
-{
- d11regs_t *regs;
- u32 tmp;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- tmp = 0;
- regs = wlc_hw->regs;
-
- if (on) {
- if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
- OR_REG(®s->clk_ctl_st,
- (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
- CCS_ERSRC_REQ_PHYPLL));
- SPINWAIT((R_REG(®s->clk_ctl_st) &
- (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
- PHYPLL_WAIT_US);
-
- tmp = R_REG(®s->clk_ctl_st);
- if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
- (CCS_ERSRC_AVAIL_HT)) {
- wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
- " PLL failed\n", __func__);
- }
- } else {
- OR_REG(®s->clk_ctl_st,
- (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
- SPINWAIT((R_REG(®s->clk_ctl_st) &
- (CCS_ERSRC_AVAIL_D11PLL |
- CCS_ERSRC_AVAIL_PHYPLL)) !=
- (CCS_ERSRC_AVAIL_D11PLL |
- CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
-
- tmp = R_REG(®s->clk_ctl_st);
- if ((tmp &
- (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
- !=
- (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
- wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
- "PHY PLL failed\n", __func__);
- }
- }
- } else {
- /* Since the PLL may be shared, other cores can still be requesting it;
- * so we'll deassert the request but not wait for status to comply.
- */
- AND_REG(®s->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
- tmp = R_REG(®s->clk_ctl_st);
- }
-}
-
-void wlc_coredisable(struct wlc_hw_info *wlc_hw)
-{
- bool dev_gone;
-
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
-
- dev_gone = DEVICEREMOVED(wlc_hw->wlc);
-
- if (dev_gone)
- return;
-
- if (wlc_hw->noreset)
- return;
-
- /* radio off */
- wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
-
- /* turn off analog core */
- wlc_phy_anacore(wlc_hw->band->pi, OFF);
-
- /* turn off PHYPLL to save power */
- wlc_bmac_core_phypll_ctl(wlc_hw, false);
-
- /* No need to set wlc->pub->radio_active = OFF
- * because this function needs down capability and
- * radio_active is designed for BCMNODOWN.
- */
-
- /* remove gpio controls */
- if (wlc_hw->ucode_dbgsel)
- ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
-
- wlc_hw->clk = false;
- ai_core_disable(wlc_hw->sih, 0);
- wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
-}
-
-/* power both the pll and external oscillator on/off */
-static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
-{
- BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
-
- /* dont power down if plldown is false or we must poll hw radio disable */
- if (!want && wlc_hw->pllreq)
- return;
-
- if (wlc_hw->sih)
- ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
-
- wlc_hw->sbclk = want;
- if (!wlc_hw->sbclk) {
- wlc_hw->clk = false;
- if (wlc_hw->band && wlc_hw->band->pi)
- wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
- }
-}
-
-static void wlc_flushqueues(struct wlc_info *wlc)
-{
- struct wlc_hw_info *wlc_hw = wlc->hw;
- uint i;
-
- wlc->txpend16165war = 0;
-
- /* free any posted tx packets */
- for (i = 0; i < NFIFO; i++)
- if (wlc_hw->di[i]) {
- dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
- TXPKTPENDCLR(wlc, i);
- BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
- }
-
- /* free any posted rx packets */
- dma_rxreclaim(wlc_hw->di[RX_FIFO]);
-}
-
-u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset)
-{
- return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
-}
-
-void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v)
-{
- wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
-}
-
-static u16
-wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
-{
- d11regs_t *regs = wlc_hw->regs;
- volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
- volatile u16 *objdata_hi = objdata_lo + 1;
- u16 v;
-
- W_REG(®s->objaddr, sel | (offset >> 2));
- (void)R_REG(®s->objaddr);
- if (offset & 2) {
- v = R_REG(objdata_hi);
- } else {
- v = R_REG(objdata_lo);
- }
-
- return v;
-}
-
-static void
-wlc_bmac_write_objmem(struct wlc_hw_info *wlc_hw, uint offset, u16 v, u32 sel)
-{
- d11regs_t *regs = wlc_hw->regs;
- volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
- volatile u16 *objdata_hi = objdata_lo + 1;
-
- W_REG(®s->objaddr, sel | (offset >> 2));
- (void)R_REG(®s->objaddr);
- if (offset & 2) {
- W_REG(objdata_hi, v);
- } else {
- W_REG(objdata_lo, v);
- }
-}
-
-/* Copy a buffer to shared memory of specified type .
- * SHM 'offset' needs to be an even address and
- * Buffer length 'len' must be an even number of bytes
- * 'sel' selects the type of memory
- */
-void
-wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw, uint offset, const void *buf,
- int len, u32 sel)
-{
- u16 v;
- const u8 *p = (const u8 *)buf;
- int i;
-
- if (len <= 0 || (offset & 1) || (len & 1))
- return;
-
- for (i = 0; i < len; i += 2) {
- v = p[i] | (p[i + 1] << 8);
- wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
- }
-}
-
-/* Copy a piece of shared memory of specified type to a buffer .
- * SHM 'offset' needs to be an even address and
- * Buffer length 'len' must be an even number of bytes
- * 'sel' selects the type of memory
- */
-void
-wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset, void *buf,
- int len, u32 sel)
-{
- u16 v;
- u8 *p = (u8 *) buf;
- int i;
-
- if (len <= 0 || (offset & 1) || (len & 1))
- return;
-
- for (i = 0; i < len; i += 2) {
- v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
- p[i] = v & 0xFF;
- p[i + 1] = (v >> 8) & 0xFF;
- }
-}
-
-void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
-{
- BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
- wlc_hw->vars_size);
-
- *buf = wlc_hw->vars;
- *len = wlc_hw->vars_size;
-}
-
-void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL, u16 LRL)
-{
- wlc_hw->SRL = SRL;
- wlc_hw->LRL = LRL;
-
- /* write retry limit to SCR, shouldn't need to suspend */
- if (wlc_hw->up) {
- W_REG(&wlc_hw->regs->objaddr,
- OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
- (void)R_REG(&wlc_hw->regs->objaddr);
- W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
- W_REG(&wlc_hw->regs->objaddr,
- OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
- (void)R_REG(&wlc_hw->regs->objaddr);
- W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
- }
-}
-
-void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
-{
- if (set) {
- if (mboolisset(wlc_hw->pllreq, req_bit))
- return;
-
- mboolset(wlc_hw->pllreq, req_bit);
-
- if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
- if (!wlc_hw->sbclk) {
- wlc_bmac_xtal(wlc_hw, ON);
- }
- }
- } else {
- if (!mboolisset(wlc_hw->pllreq, req_bit))
- return;
-
- mboolclr(wlc_hw->pllreq, req_bit);
-
- if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
- if (wlc_hw->sbclk) {
- wlc_bmac_xtal(wlc_hw, OFF);
- }
- }
- }
-
- return;
-}
-
-u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
-{
- u16 table_ptr;
- u8 phy_rate, index;
-
- /* get the phy specific rate encoding for the PLCP SIGNAL field */
- /* XXX4321 fixup needed ? */
- if (IS_OFDM(rate))
- table_ptr = M_RT_DIRMAP_A;
- else
- table_ptr = M_RT_DIRMAP_B;
-
- /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
- * the index into the rate table.
- */
- phy_rate = rate_info[rate] & WLC_RATE_MASK;
- index = phy_rate & 0xf;
-
- /* Find the SHM pointer to the rate table entry by looking in the
- * Direct-map Table
- */
- return 2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2));
-}
-
-void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail)
-{
- wlc_hw->antsel_avail = antsel_avail;
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#ifndef _BRCM_BOTTOM_MAC_H_
-#define _BRCM_BOTTOM_MAC_H_
-
-/* XXXXX this interface is under wlc.c by design
- * http://hwnbu-twiki.broadcom.com/bin/view/Mwgroup/WlBmacDesign
- *
- * high driver files(e.g. wlc_ampdu.c etc)
- * wlc.h/wlc.c
- * wlc_bmac.h/wlc_bmac.c
- *
- * So don't include this in files other than wlc.c, wlc_bmac* wl_rte.c(dongle port) and wl_phy.c
- * create wrappers in wlc.c if needed
- */
-
-/* dup state between BMAC(struct wlc_hw_info) and HIGH(struct wlc_info)
- driver */
-typedef struct wlc_bmac_state {
- u32 machwcap; /* mac hw capibility */
- u32 preamble_ovr; /* preamble override */
-} wlc_bmac_state_t;
-
-enum {
- IOV_BMAC_DIAG,
- IOV_BMAC_SBGPIOTIMERVAL,
- IOV_BMAC_SBGPIOOUT,
- IOV_BMAC_CCGPIOCTRL, /* CC GPIOCTRL REG */
- IOV_BMAC_CCGPIOOUT, /* CC GPIOOUT REG */
- IOV_BMAC_CCGPIOOUTEN, /* CC GPIOOUTEN REG */
- IOV_BMAC_CCGPIOIN, /* CC GPIOIN REG */
- IOV_BMAC_WPSGPIO, /* WPS push button GPIO pin */
- IOV_BMAC_OTPDUMP,
- IOV_BMAC_OTPSTAT,
- IOV_BMAC_PCIEASPM, /* obfuscation clkreq/aspm control */
- IOV_BMAC_PCIEADVCORRMASK, /* advanced correctable error mask */
- IOV_BMAC_PCIECLKREQ, /* PCIE 1.1 clockreq enab support */
- IOV_BMAC_PCIELCREG, /* PCIE LCREG */
- IOV_BMAC_SBGPIOTIMERMASK,
- IOV_BMAC_RFDISABLEDLY,
- IOV_BMAC_PCIEREG, /* PCIE REG */
- IOV_BMAC_PCICFGREG, /* PCI Config register */
- IOV_BMAC_PCIESERDESREG, /* PCIE SERDES REG (dev, 0}offset) */
- IOV_BMAC_PCIEGPIOOUT, /* PCIEOUT REG */
- IOV_BMAC_PCIEGPIOOUTEN, /* PCIEOUTEN REG */
- IOV_BMAC_PCIECLKREQENCTRL, /* clkreqenctrl REG (PCIE REV > 6.0 */
- IOV_BMAC_DMALPBK,
- IOV_BMAC_CCREG,
- IOV_BMAC_COREREG,
- IOV_BMAC_SDCIS,
- IOV_BMAC_SDIO_DRIVE,
- IOV_BMAC_OTPW,
- IOV_BMAC_NVOTPW,
- IOV_BMAC_SROM,
- IOV_BMAC_SRCRC,
- IOV_BMAC_CIS_SOURCE,
- IOV_BMAC_CISVAR,
- IOV_BMAC_OTPLOCK,
- IOV_BMAC_OTP_CHIPID,
- IOV_BMAC_CUSTOMVAR1,
- IOV_BMAC_BOARDFLAGS,
- IOV_BMAC_BOARDFLAGS2,
- IOV_BMAC_WPSLED,
- IOV_BMAC_NVRAM_SOURCE,
- IOV_BMAC_OTP_RAW_READ,
- IOV_BMAC_LAST
-};
-
-extern int wlc_bmac_attach(struct wlc_info *wlc, u16 vendor, u16 device,
- uint unit, bool piomode, void *regsva, uint bustype,
- void *btparam);
-extern int wlc_bmac_detach(struct wlc_info *wlc);
-extern void wlc_bmac_watchdog(void *arg);
-
-/* up/down, reset, clk */
-extern void wlc_bmac_copyto_objmem(struct wlc_hw_info *wlc_hw,
- uint offset, const void *buf, int len,
- u32 sel);
-extern void wlc_bmac_copyfrom_objmem(struct wlc_hw_info *wlc_hw, uint offset,
- void *buf, int len, u32 sel);
-#define wlc_bmac_copyfrom_shm(wlc_hw, offset, buf, len) \
- wlc_bmac_copyfrom_objmem(wlc_hw, offset, buf, len, OBJADDR_SHM_SEL)
-#define wlc_bmac_copyto_shm(wlc_hw, offset, buf, len) \
- wlc_bmac_copyto_objmem(wlc_hw, offset, buf, len, OBJADDR_SHM_SEL)
-
-extern void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw);
-extern void wlc_bmac_core_phypll_ctl(struct wlc_hw_info *wlc_hw, bool on);
-extern void wlc_bmac_phyclk_fgc(struct wlc_hw_info *wlc_hw, bool clk);
-extern void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk);
-extern void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw);
-extern void wlc_bmac_corereset(struct wlc_hw_info *wlc_hw, u32 flags);
-extern void wlc_bmac_reset(struct wlc_hw_info *wlc_hw);
-extern void wlc_bmac_init(struct wlc_hw_info *wlc_hw, chanspec_t chanspec,
- bool mute);
-extern int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw);
-extern int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw);
-extern int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw);
-extern int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw);
-extern void wlc_bmac_switch_macfreq(struct wlc_hw_info *wlc_hw, u8 spurmode);
-
-/* chanspec, ucode interface */
-extern void wlc_bmac_set_chanspec(struct wlc_hw_info *wlc_hw,
- chanspec_t chanspec,
- bool mute, struct txpwr_limits *txpwr);
-
-extern int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo,
- uint *blocks);
-extern void wlc_bmac_mhf(struct wlc_hw_info *wlc_hw, u8 idx, u16 mask,
- u16 val, int bands);
-extern void wlc_bmac_mctrl(struct wlc_hw_info *wlc_hw, u32 mask, u32 val);
-extern u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands);
-extern void wlc_bmac_txant_set(struct wlc_hw_info *wlc_hw, u16 phytxant);
-extern u16 wlc_bmac_get_txant(struct wlc_hw_info *wlc_hw);
-extern void wlc_bmac_antsel_type_set(struct wlc_hw_info *wlc_hw,
- u8 antsel_type);
-extern int wlc_bmac_state_get(struct wlc_hw_info *wlc_hw,
- wlc_bmac_state_t *state);
-extern void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v);
-extern u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset);
-extern void wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset,
- int len, void *buf);
-extern void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf,
- uint *len);
-
-extern void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw,
- u8 *ea);
-
-extern bool wlc_bmac_radio_read_hwdisabled(struct wlc_hw_info *wlc_hw);
-extern void wlc_bmac_set_shortslot(struct wlc_hw_info *wlc_hw, bool shortslot);
-extern void wlc_bmac_band_stf_ss_set(struct wlc_hw_info *wlc_hw, u8 stf_mode);
-
-extern void wlc_bmac_wait_for_wake(struct wlc_hw_info *wlc_hw);
-
-extern void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw,
- u32 override_bit);
-extern void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw,
- u32 override_bit);
-
-extern void wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw,
- int match_reg_offset,
- const u8 *addr);
-extern void wlc_bmac_write_hw_bcntemplates(struct wlc_hw_info *wlc_hw,
- void *bcn, int len, bool both);
-
-extern void wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
- u32 *tsf_h_ptr);
-extern void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin);
-extern void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax);
-
-extern void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL,
- u16 LRL);
-
-extern void wlc_bmac_fifoerrors(struct wlc_hw_info *wlc_hw);
-
-
-/* API for BMAC driver (e.g. wlc_phy.c etc) */
-
-extern void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw);
-extern void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set,
- mbool req_bit);
-extern void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw);
-extern u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate);
-extern void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail);
-
-#endif /* _BRCM_BOTTOM_MAC_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_BSSCFG_H_
-#define _BRCM_BSSCFG_H_
-
-/* Check if a particular BSS config is AP or STA */
-#define BSSCFG_AP(cfg) (0)
-#define BSSCFG_STA(cfg) (1)
-
-#define BSSCFG_IBSS(cfg) (!(cfg)->BSS)
-
-#define NTXRATE 64 /* # tx MPDUs rate is reported for */
-#define MAXMACLIST 64 /* max # source MAC matches */
-#define BCN_TEMPLATE_COUNT 2
-
-/* Iterator for "associated" STA bss configs:
- (struct wlc_info *wlc, int idx, struct wlc_bsscfg *cfg) */
-#define FOREACH_AS_STA(wlc, idx, cfg) \
- for (idx = 0; (int) idx < WLC_MAXBSSCFG; idx++) \
- if ((cfg = (wlc)->bsscfg[idx]) && BSSCFG_STA(cfg) && cfg->associated)
-
-/* As above for all non-NULL BSS configs */
-#define FOREACH_BSS(wlc, idx, cfg) \
- for (idx = 0; (int) idx < WLC_MAXBSSCFG; idx++) \
- if ((cfg = (wlc)->bsscfg[idx]))
-
-/* BSS configuration state */
-struct wlc_bsscfg {
- struct wlc_info *wlc; /* wlc to which this bsscfg belongs to. */
- bool up; /* is this configuration up operational */
- bool enable; /* is this configuration enabled */
- bool associated; /* is BSS in ASSOCIATED state */
- bool BSS; /* infraustructure or adhac */
- bool dtim_programmed;
-
- u8 SSID_len; /* the length of SSID */
- u8 SSID[IEEE80211_MAX_SSID_LEN]; /* SSID string */
- struct scb *bcmc_scb[MAXBANDS]; /* one bcmc_scb per band */
- s8 _idx; /* the index of this bsscfg,
- * assigned at wlc_bsscfg_alloc()
- */
- /* MAC filter */
- uint nmac; /* # of entries on maclist array */
- int macmode; /* allow/deny stations on maclist array */
- struct ether_addr *maclist; /* list of source MAC addrs to match */
-
- /* security */
- u32 wsec; /* wireless security bitvec */
- s16 auth; /* 802.11 authentication: Open, Shared Key, WPA */
- s16 openshared; /* try Open auth first, then Shared Key */
- bool wsec_restrict; /* drop unencrypted packets if wsec is enabled */
- bool eap_restrict; /* restrict data until 802.1X auth succeeds */
- u16 WPA_auth; /* WPA: authenticated key management */
- bool wpa2_preauth; /* default is true, wpa_cap sets value */
- bool wsec_portopen; /* indicates keys are plumbed */
- wsec_iv_t wpa_none_txiv; /* global txiv for WPA_NONE, tkip and aes */
- int wsec_index; /* 0-3: default tx key, -1: not set */
- wsec_key_t *bss_def_keys[WLC_DEFAULT_KEYS]; /* default key storage */
-
- /* TKIP countermeasures */
- bool tkip_countermeasures; /* flags TKIP no-assoc period */
- u32 tk_cm_dt; /* detect timer */
- u32 tk_cm_bt; /* blocking timer */
- u32 tk_cm_bt_tmstmp; /* Timestamp when TKIP BT is activated */
- bool tk_cm_activate; /* activate countermeasures after EAPOL-Key sent */
-
- u8 BSSID[ETH_ALEN]; /* BSSID (associated) */
- u8 cur_etheraddr[ETH_ALEN]; /* h/w address */
- u16 bcmc_fid; /* the last BCMC FID queued to TX_BCMC_FIFO */
- u16 bcmc_fid_shm; /* the last BCMC FID written to shared mem */
-
- u32 flags; /* WLC_BSSCFG flags; see below */
-
- u8 *bcn; /* AP beacon */
- uint bcn_len; /* AP beacon length */
- bool ar_disassoc; /* disassociated in associated recreation */
-
- int auth_atmptd; /* auth type (open/shared) attempted */
-
- pmkid_cand_t pmkid_cand[MAXPMKID]; /* PMKID candidate list */
- uint npmkid_cand; /* num PMKID candidates */
- pmkid_t pmkid[MAXPMKID]; /* PMKID cache */
- uint npmkid; /* num cached PMKIDs */
-
- wlc_bss_info_t *current_bss; /* BSS parms in ASSOCIATED state */
-
- /* PM states */
- bool PMawakebcn; /* bcn recvd during current waking state */
- bool PMpending; /* waiting for tx status with PM indicated set */
- bool priorPMstate; /* Detecting PM state transitions */
- bool PSpoll; /* whether there is an outstanding PS-Poll frame */
-
- /* BSSID entry in RCMTA, use the wsec key management infrastructure to
- * manage the RCMTA entries.
- */
- wsec_key_t *rcmta;
-
- /* 'unique' ID of this bsscfg, assigned at bsscfg allocation */
- u16 ID;
-
- uint txrspecidx; /* index into tx rate circular buffer */
- ratespec_t txrspec[NTXRATE][2]; /* circular buffer of prev MPDUs tx rates */
-};
-
-#define WLC_BSSCFG_11N_DISABLE 0x1000 /* Do not advertise .11n IEs for this BSS */
-#define WLC_BSSCFG_HW_BCN 0x20 /* The BSS is generating beacons in HW */
-
-#define HWBCN_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_BCN) != 0)
-#define HWPRB_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_PRB) != 0)
-
-/* Extend N_ENAB to per-BSS */
-#define BSS_N_ENAB(wlc, cfg) \
- (N_ENAB((wlc)->pub) && !((cfg)->flags & WLC_BSSCFG_11N_DISABLE))
-
-#define MBSS_BCN_ENAB(cfg) 0
-#define MBSS_PRB_ENAB(cfg) 0
-#define SOFTBCN_ENAB(pub) (0)
-#define SOFTPRB_ENAB(pub) (0)
-#define wlc_bsscfg_tx_check(a) do { } while (0);
-
-#endif /* _BRCM_BSSCFG_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_CFG_H_
-#define _BRCM_CFG_H_
-
-#define NBANDS(wlc) ((wlc)->pub->_nbands)
-#define NBANDS_PUB(pub) ((pub)->_nbands)
-#define NBANDS_HW(hw) ((hw)->_nbands)
-
-#define IS_SINGLEBAND_5G(device) 0
-
-/* **** Core type/rev defaults **** */
-#define D11_DEFAULT 0x0fffffb0 /* Supported D11 revs: 4, 5, 7-27
- * also need to update wlc.h MAXCOREREV
- */
-
-#define NPHY_DEFAULT 0x000001ff /* Supported nphy revs:
- * 0 4321a0
- * 1 4321a1
- * 2 4321b0/b1/c0/c1
- * 3 4322a0
- * 4 4322a1
- * 5 4716a0
- * 6 43222a0, 43224a0
- * 7 43226a0
- * 8 5357a0, 43236a0
- */
-
-#define LCNPHY_DEFAULT 0x00000007 /* Supported lcnphy revs:
- * 0 4313a0, 4336a0, 4330a0
- * 1
- * 2 4330a0
- */
-
-#define SSLPNPHY_DEFAULT 0x0000000f /* Supported sslpnphy revs:
- * 0 4329a0/k0
- * 1 4329b0/4329C0
- * 2 4319a0
- * 3 5356a0
- */
-
-
-/* For undefined values, use defaults */
-#ifndef D11CONF
-#define D11CONF D11_DEFAULT
-#endif
-#ifndef NCONF
-#define NCONF NPHY_DEFAULT
-#endif
-#ifndef LCNCONF
-#define LCNCONF LCNPHY_DEFAULT
-#endif
-
-#ifndef SSLPNCONF
-#define SSLPNCONF SSLPNPHY_DEFAULT
-#endif
-
-/********************************************************************
- * Phy/Core Configuration. Defines macros to to check core phy/rev *
- * compile-time configuration. Defines default core support. *
- * ******************************************************************
- */
-
-/* Basic macros to check a configuration bitmask */
-
-#define CONF_HAS(config, val) ((config) & (1 << (val)))
-#define CONF_MSK(config, mask) ((config) & (mask))
-#define MSK_RANGE(low, hi) ((1 << ((hi)+1)) - (1 << (low)))
-#define CONF_RANGE(config, low, hi) (CONF_MSK(config, MSK_RANGE(low, high)))
-
-#define CONF_IS(config, val) ((config) == (1 << (val)))
-#define CONF_GE(config, val) ((config) & (0-(1 << (val))))
-#define CONF_GT(config, val) ((config) & (0-2*(1 << (val))))
-#define CONF_LT(config, val) ((config) & ((1 << (val))-1))
-#define CONF_LE(config, val) ((config) & (2*(1 << (val))-1))
-
-/* Wrappers for some of the above, specific to config constants */
-
-#define NCONF_HAS(val) CONF_HAS(NCONF, val)
-#define NCONF_MSK(mask) CONF_MSK(NCONF, mask)
-#define NCONF_IS(val) CONF_IS(NCONF, val)
-#define NCONF_GE(val) CONF_GE(NCONF, val)
-#define NCONF_GT(val) CONF_GT(NCONF, val)
-#define NCONF_LT(val) CONF_LT(NCONF, val)
-#define NCONF_LE(val) CONF_LE(NCONF, val)
-
-#define LCNCONF_HAS(val) CONF_HAS(LCNCONF, val)
-#define LCNCONF_MSK(mask) CONF_MSK(LCNCONF, mask)
-#define LCNCONF_IS(val) CONF_IS(LCNCONF, val)
-#define LCNCONF_GE(val) CONF_GE(LCNCONF, val)
-#define LCNCONF_GT(val) CONF_GT(LCNCONF, val)
-#define LCNCONF_LT(val) CONF_LT(LCNCONF, val)
-#define LCNCONF_LE(val) CONF_LE(LCNCONF, val)
-
-#define D11CONF_HAS(val) CONF_HAS(D11CONF, val)
-#define D11CONF_MSK(mask) CONF_MSK(D11CONF, mask)
-#define D11CONF_IS(val) CONF_IS(D11CONF, val)
-#define D11CONF_GE(val) CONF_GE(D11CONF, val)
-#define D11CONF_GT(val) CONF_GT(D11CONF, val)
-#define D11CONF_LT(val) CONF_LT(D11CONF, val)
-#define D11CONF_LE(val) CONF_LE(D11CONF, val)
-
-#define PHYCONF_HAS(val) CONF_HAS(PHYTYPE, val)
-#define PHYCONF_IS(val) CONF_IS(PHYTYPE, val)
-
-#define NREV_IS(var, val) (NCONF_HAS(val) && (NCONF_IS(val) || ((var) == (val))))
-#define NREV_GE(var, val) (NCONF_GE(val) && (!NCONF_LT(val) || ((var) >= (val))))
-#define NREV_GT(var, val) (NCONF_GT(val) && (!NCONF_LE(val) || ((var) > (val))))
-#define NREV_LT(var, val) (NCONF_LT(val) && (!NCONF_GE(val) || ((var) < (val))))
-#define NREV_LE(var, val) (NCONF_LE(val) && (!NCONF_GT(val) || ((var) <= (val))))
-
-#define LCNREV_IS(var, val) (LCNCONF_HAS(val) && (LCNCONF_IS(val) || ((var) == (val))))
-#define LCNREV_GE(var, val) (LCNCONF_GE(val) && (!LCNCONF_LT(val) || ((var) >= (val))))
-#define LCNREV_GT(var, val) (LCNCONF_GT(val) && (!LCNCONF_LE(val) || ((var) > (val))))
-#define LCNREV_LT(var, val) (LCNCONF_LT(val) && (!LCNCONF_GE(val) || ((var) < (val))))
-#define LCNREV_LE(var, val) (LCNCONF_LE(val) && (!LCNCONF_GT(val) || ((var) <= (val))))
-
-#define D11REV_IS(var, val) (D11CONF_HAS(val) && (D11CONF_IS(val) || ((var) == (val))))
-#define D11REV_GE(var, val) (D11CONF_GE(val) && (!D11CONF_LT(val) || ((var) >= (val))))
-#define D11REV_GT(var, val) (D11CONF_GT(val) && (!D11CONF_LE(val) || ((var) > (val))))
-#define D11REV_LT(var, val) (D11CONF_LT(val) && (!D11CONF_GE(val) || ((var) < (val))))
-#define D11REV_LE(var, val) (D11CONF_LE(val) && (!D11CONF_GT(val) || ((var) <= (val))))
-
-#define PHYTYPE_IS(var, val) (PHYCONF_HAS(val) && (PHYCONF_IS(val) || ((var) == (val))))
-
-/* Finally, early-exit from switch case if anyone wants it... */
-
-#define CASECHECK(config, val) if (!(CONF_HAS(config, val))) break
-#define CASEMSK(config, mask) if (!(CONF_MSK(config, mask))) break
-
-#if (D11CONF ^ (D11CONF & D11_DEFAULT))
-#error "Unsupported MAC revision configured"
-#endif
-#if (NCONF ^ (NCONF & NPHY_DEFAULT))
-#error "Unsupported NPHY revision configured"
-#endif
-#if (LCNCONF ^ (LCNCONF & LCNPHY_DEFAULT))
-#error "Unsupported LPPHY revision configured"
-#endif
-
-/* *** Consistency checks *** */
-#if !D11CONF
-#error "No MAC revisions configured!"
-#endif
-
-#if !NCONF && !LCNCONF && !SSLPNCONF
-#error "No PHY configured!"
-#endif
-
-/* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */
-
-#define _PHYCONF_N (1 << PHY_TYPE_N)
-
-#if LCNCONF
-#define _PHYCONF_LCN (1 << PHY_TYPE_LCN)
-#else
-#define _PHYCONF_LCN 0
-#endif /* LCNCONF */
-
-#if SSLPNCONF
-#define _PHYCONF_SSLPN (1 << PHY_TYPE_SSN)
-#else
-#define _PHYCONF_SSLPN 0
-#endif /* SSLPNCONF */
-
-#define PHYTYPE (_PHYCONF_N | _PHYCONF_LCN | _PHYCONF_SSLPN)
-
-/* Utility macro to identify 802.11n (HT) capable PHYs */
-#define PHYTYPE_11N_CAP(phytype) \
- (PHYTYPE_IS(phytype, PHY_TYPE_N) || \
- PHYTYPE_IS(phytype, PHY_TYPE_LCN) || \
- PHYTYPE_IS(phytype, PHY_TYPE_SSN))
-
-/* Last but not least: shorter wlc-specific var checks */
-#define WLCISNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_N)
-#define WLCISLCNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_LCN)
-#define WLCISSSLPNPHY(band) PHYTYPE_IS((band)->phytype, PHY_TYPE_SSN)
-
-#define WLC_PHY_11N_CAP(band) PHYTYPE_11N_CAP((band)->phytype)
-
-/**********************************************************************
- * ------------- End of Core phy/rev configuration. ----------------- *
- * ********************************************************************
- */
-
-/*************************************************
- * Defaults for tunables (e.g. sizing constants)
- *
- * For each new tunable, add a member to the end
- * of wlc_tunables_t in wlc_pub.h to enable
- * runtime checks of tunable values. (Directly
- * using the macros in code invalidates ROM code)
- *
- * ***********************************************
- */
-#ifndef NTXD
-#define NTXD 256 /* Max # of entries in Tx FIFO based on 4kb page size */
-#endif /* NTXD */
-#ifndef NRXD
-#define NRXD 256 /* Max # of entries in Rx FIFO based on 4kb page size */
-#endif /* NRXD */
-
-#ifndef NRXBUFPOST
-#define NRXBUFPOST 32 /* try to keep this # rbufs posted to the chip */
-#endif /* NRXBUFPOST */
-
-#ifndef MAXSCB /* station control blocks in cache */
-#define MAXSCB 32 /* Maximum SCBs in cache for STA */
-#endif /* MAXSCB */
-
-#ifndef AMPDU_NUM_MPDU
-#define AMPDU_NUM_MPDU 16 /* max allowed number of mpdus in an ampdu (2 streams) */
-#endif /* AMPDU_NUM_MPDU */
-
-#ifndef AMPDU_NUM_MPDU_3STREAMS
-#define AMPDU_NUM_MPDU_3STREAMS 32 /* max allowed number of mpdus in an ampdu for 3+ streams */
-#endif /* AMPDU_NUM_MPDU_3STREAMS */
-
-/* Count of packet callback structures. either of following
- * 1. Set to the number of SCBs since a STA
- * can queue up a rate callback for each IBSS STA it knows about, and an AP can
- * queue up an "are you there?" Null Data callback for each associated STA
- * 2. controlled by tunable config file
- */
-#ifndef MAXPKTCB
-#define MAXPKTCB MAXSCB /* Max number of packet callbacks */
-#endif /* MAXPKTCB */
-
-#ifndef CTFPOOLSZ
-#define CTFPOOLSZ 128
-#endif /* CTFPOOLSZ */
-
-/* NetBSD also needs to keep track of this */
-#define WLC_MAX_UCODE_BSS (16) /* Number of BSS handled in ucode bcn/prb */
-#define WLC_MAX_UCODE_BSS4 (4) /* Number of BSS handled in sw bcn/prb */
-#ifndef WLC_MAXBSSCFG
-#define WLC_MAXBSSCFG (1) /* max # BSS configs */
-#endif /* WLC_MAXBSSCFG */
-
-#ifndef MAXBSS
-#define MAXBSS 64 /* max # available networks */
-#endif /* MAXBSS */
-
-#ifndef WLC_DATAHIWAT
-#define WLC_DATAHIWAT 50 /* data msg txq hiwat mark */
-#endif /* WLC_DATAHIWAT */
-
-#ifndef WLC_AMPDUDATAHIWAT
-#define WLC_AMPDUDATAHIWAT 255
-#endif /* WLC_AMPDUDATAHIWAT */
-
-/* bounded rx loops */
-#ifndef RXBND
-#define RXBND 8 /* max # frames to process in wlc_recv() */
-#endif /* RXBND */
-#ifndef TXSBND
-#define TXSBND 8 /* max # tx status to process in wlc_txstatus() */
-#endif /* TXSBND */
-
-#define BAND_5G(bt) ((bt) == WLC_BAND_5G)
-#define BAND_2G(bt) ((bt) == WLC_BAND_2G)
-
-#define WLBANDINITDATA(_data) _data
-#define WLBANDINITFN(_fn) _fn
-
-#endif /* _BRCM_CFG_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-
-#include <bcmdefs.h>
-#include <brcmu_utils.h>
-#include <aiutils.h>
-#include "bcmdma.h"
-
-#include "wlc_types.h"
-#include "d11.h"
-#include "wlc_cfg.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "wlc_key.h"
-#include "phy/wlc_phy_hal.h"
-#include "wlc_bmac.h"
-#include "wlc_rate.h"
-#include "wlc_channel.h"
-#include "wlc_main.h"
-#include "wlc_stf.h"
-
-#define VALID_CHANNEL20_DB(wlc, val) wlc_valid_channel20_db((wlc)->cmi, val)
-#define VALID_CHANNEL20_IN_BAND(wlc, bandunit, val) \
- wlc_valid_channel20_in_band((wlc)->cmi, bandunit, val)
-#define VALID_CHANNEL20(wlc, val) wlc_valid_channel20((wlc)->cmi, val)
-
-typedef struct wlc_cm_band {
- u8 locale_flags; /* locale_info_t flags */
- chanvec_t valid_channels; /* List of valid channels in the country */
- const chanvec_t *restricted_channels; /* List of restricted use channels */
- const chanvec_t *radar_channels; /* List of radar sensitive channels */
- u8 PAD[8];
-} wlc_cm_band_t;
-
-struct wlc_cm_info {
- struct wlc_pub *pub;
- struct wlc_info *wlc;
- char srom_ccode[WLC_CNTRY_BUF_SZ]; /* Country Code in SROM */
- uint srom_regrev; /* Regulatory Rev for the SROM ccode */
- const country_info_t *country; /* current country def */
- char ccode[WLC_CNTRY_BUF_SZ]; /* current internal Country Code */
- uint regrev; /* current Regulatory Revision */
- char country_abbrev[WLC_CNTRY_BUF_SZ]; /* current advertised ccode */
- wlc_cm_band_t bandstate[MAXBANDS]; /* per-band state (one per phy/radio) */
- /* quiet channels currently for radar sensitivity or 11h support */
- chanvec_t quiet_channels; /* channels on which we cannot transmit */
-};
-
-static int wlc_channels_init(wlc_cm_info_t *wlc_cm,
- const country_info_t *country);
-static void wlc_set_country_common(wlc_cm_info_t *wlc_cm,
- const char *country_abbrev,
- const char *ccode, uint regrev,
- const country_info_t *country);
-static int wlc_set_countrycode(wlc_cm_info_t *wlc_cm, const char *ccode);
-static int wlc_set_countrycode_rev(wlc_cm_info_t *wlc_cm,
- const char *country_abbrev,
- const char *ccode, int regrev);
-static int wlc_country_aggregate_map(wlc_cm_info_t *wlc_cm, const char *ccode,
- char *mapped_ccode, uint *mapped_regrev);
-static const country_info_t *wlc_country_lookup_direct(const char *ccode,
- uint regrev);
-static const country_info_t *wlc_countrycode_map(wlc_cm_info_t *wlc_cm,
- const char *ccode,
- char *mapped_ccode,
- uint *mapped_regrev);
-static void wlc_channels_commit(wlc_cm_info_t *wlc_cm);
-static void wlc_quiet_channels_reset(wlc_cm_info_t *wlc_cm);
-static bool wlc_quiet_chanspec(wlc_cm_info_t *wlc_cm, chanspec_t chspec);
-static bool wlc_valid_channel20_db(wlc_cm_info_t *wlc_cm, uint val);
-static bool wlc_valid_channel20_in_band(wlc_cm_info_t *wlc_cm, uint bandunit,
- uint val);
-static bool wlc_valid_channel20(wlc_cm_info_t *wlc_cm, uint val);
-static const country_info_t *wlc_country_lookup(struct wlc_info *wlc,
- const char *ccode);
-static void wlc_locale_get_channels(const locale_info_t *locale,
- chanvec_t *valid_channels);
-static const locale_info_t *wlc_get_locale_2g(u8 locale_idx);
-static const locale_info_t *wlc_get_locale_5g(u8 locale_idx);
-static bool wlc_japan(struct wlc_info *wlc);
-static bool wlc_japan_ccode(const char *ccode);
-static void wlc_channel_min_txpower_limits_with_local_constraint(wlc_cm_info_t *
- wlc_cm,
- struct
- txpwr_limits
- *txpwr,
- u8
- local_constraint_qdbm);
-static void wlc_locale_add_channels(chanvec_t *target,
- const chanvec_t *channels);
-static const locale_mimo_info_t *wlc_get_mimo_2g(u8 locale_idx);
-static const locale_mimo_info_t *wlc_get_mimo_5g(u8 locale_idx);
-
-/* QDB() macro takes a dB value and converts to a quarter dB value */
-#ifdef QDB
-#undef QDB
-#endif
-#define QDB(n) ((n) * WLC_TXPWR_DB_FACTOR)
-
-/* Regulatory Matrix Spreadsheet (CLM) MIMO v3.7.9 */
-
-/*
- * Some common channel sets
- */
-
-/* No channels */
-static const chanvec_t chanvec_none = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-/* All 2.4 GHz HW channels */
-const chanvec_t chanvec_all_2G = {
- {0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-/* All 5 GHz HW channels */
-const chanvec_t chanvec_all_5G = {
- {0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x11, 0x11,
- 0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x20, 0x22, 0x22, 0x00, 0x00, 0x11,
- 0x11, 0x11, 0x11, 0x01}
-};
-
-/*
- * Radar channel sets
- */
-
-/* No radar */
-#define radar_set_none chanvec_none
-
-static const chanvec_t radar_set1 = { /* Channels 52 - 64, 100 - 140 */
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, /* 52 - 60 */
- 0x01, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x11, /* 64, 100 - 124 */
- 0x11, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 128 - 140 */
- 0x00, 0x00, 0x00, 0x00}
-};
-
-/*
- * Restricted channel sets
- */
-
-#define restricted_set_none chanvec_none
-
-/* Channels 34, 38, 42, 46 */
-static const chanvec_t restricted_set_japan_legacy = {
- {0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-/* Channels 12, 13 */
-static const chanvec_t restricted_set_2g_short = {
- {0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-/* Channel 165 */
-static const chanvec_t restricted_chan_165 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-/* Channels 36 - 48 & 149 - 165 */
-static const chanvec_t restricted_low_hi = {
- {0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x22, 0x22, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-/* Channels 12 - 14 */
-static const chanvec_t restricted_set_12_13_14 = {
- {0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-#define LOCALE_CHAN_01_11 (1<<0)
-#define LOCALE_CHAN_12_13 (1<<1)
-#define LOCALE_CHAN_14 (1<<2)
-#define LOCALE_SET_5G_LOW_JP1 (1<<3) /* 34-48, step 2 */
-#define LOCALE_SET_5G_LOW_JP2 (1<<4) /* 34-46, step 4 */
-#define LOCALE_SET_5G_LOW1 (1<<5) /* 36-48, step 4 */
-#define LOCALE_SET_5G_LOW2 (1<<6) /* 52 */
-#define LOCALE_SET_5G_LOW3 (1<<7) /* 56-64, step 4 */
-#define LOCALE_SET_5G_MID1 (1<<8) /* 100-116, step 4 */
-#define LOCALE_SET_5G_MID2 (1<<9) /* 120-124, step 4 */
-#define LOCALE_SET_5G_MID3 (1<<10) /* 128 */
-#define LOCALE_SET_5G_HIGH1 (1<<11) /* 132-140, step 4 */
-#define LOCALE_SET_5G_HIGH2 (1<<12) /* 149-161, step 4 */
-#define LOCALE_SET_5G_HIGH3 (1<<13) /* 165 */
-#define LOCALE_CHAN_52_140_ALL (1<<14)
-#define LOCALE_SET_5G_HIGH4 (1<<15) /* 184-216 */
-
-#define LOCALE_CHAN_36_64 (LOCALE_SET_5G_LOW1 | LOCALE_SET_5G_LOW2 | LOCALE_SET_5G_LOW3)
-#define LOCALE_CHAN_52_64 (LOCALE_SET_5G_LOW2 | LOCALE_SET_5G_LOW3)
-#define LOCALE_CHAN_100_124 (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2)
-#define LOCALE_CHAN_100_140 \
- (LOCALE_SET_5G_MID1 | LOCALE_SET_5G_MID2 | LOCALE_SET_5G_MID3 | LOCALE_SET_5G_HIGH1)
-#define LOCALE_CHAN_149_165 (LOCALE_SET_5G_HIGH2 | LOCALE_SET_5G_HIGH3)
-#define LOCALE_CHAN_184_216 LOCALE_SET_5G_HIGH4
-
-#define LOCALE_CHAN_01_14 (LOCALE_CHAN_01_11 | LOCALE_CHAN_12_13 | LOCALE_CHAN_14)
-
-#define LOCALE_RADAR_SET_NONE 0
-#define LOCALE_RADAR_SET_1 1
-
-#define LOCALE_RESTRICTED_NONE 0
-#define LOCALE_RESTRICTED_SET_2G_SHORT 1
-#define LOCALE_RESTRICTED_CHAN_165 2
-#define LOCALE_CHAN_ALL_5G 3
-#define LOCALE_RESTRICTED_JAPAN_LEGACY 4
-#define LOCALE_RESTRICTED_11D_2G 5
-#define LOCALE_RESTRICTED_11D_5G 6
-#define LOCALE_RESTRICTED_LOW_HI 7
-#define LOCALE_RESTRICTED_12_13_14 8
-
-/* global memory to provide working buffer for expanded locale */
-
-static const chanvec_t *g_table_radar_set[] = {
- &chanvec_none,
- &radar_set1
-};
-
-static const chanvec_t *g_table_restricted_chan[] = {
- &chanvec_none, /* restricted_set_none */
- &restricted_set_2g_short,
- &restricted_chan_165,
- &chanvec_all_5G,
- &restricted_set_japan_legacy,
- &chanvec_all_2G, /* restricted_set_11d_2G */
- &chanvec_all_5G, /* restricted_set_11d_5G */
- &restricted_low_hi,
- &restricted_set_12_13_14
-};
-
-static const chanvec_t locale_2g_01_11 = {
- {0xfe, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_2g_12_13 = {
- {0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_2g_14 = {
- {0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_LOW_JP1 = {
- {0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_LOW_JP2 = {
- {0x00, 0x00, 0x00, 0x00, 0x44, 0x44, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_LOW1 = {
- {0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x01, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_LOW2 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_LOW3 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
- 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_MID1 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x11, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_MID2 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_MID3 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_HIGH1 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_HIGH2 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x20, 0x22, 0x02, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_HIGH3 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_52_140_ALL = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11,
- 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11,
- 0x11, 0x11, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static const chanvec_t locale_5g_HIGH4 = {
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11,
- 0x11, 0x11, 0x11, 0x11}
-};
-
-static const chanvec_t *g_table_locale_base[] = {
- &locale_2g_01_11,
- &locale_2g_12_13,
- &locale_2g_14,
- &locale_5g_LOW_JP1,
- &locale_5g_LOW_JP2,
- &locale_5g_LOW1,
- &locale_5g_LOW2,
- &locale_5g_LOW3,
- &locale_5g_MID1,
- &locale_5g_MID2,
- &locale_5g_MID3,
- &locale_5g_HIGH1,
- &locale_5g_HIGH2,
- &locale_5g_HIGH3,
- &locale_5g_52_140_ALL,
- &locale_5g_HIGH4
-};
-
-static void wlc_locale_add_channels(chanvec_t *target,
- const chanvec_t *channels)
-{
- u8 i;
- for (i = 0; i < sizeof(chanvec_t); i++) {
- target->vec[i] |= channels->vec[i];
- }
-}
-
-static void wlc_locale_get_channels(const locale_info_t *locale,
- chanvec_t *channels)
-{
- u8 i;
-
- memset(channels, 0, sizeof(chanvec_t));
-
- for (i = 0; i < ARRAY_SIZE(g_table_locale_base); i++) {
- if (locale->valid_channels & (1 << i)) {
- wlc_locale_add_channels(channels,
- g_table_locale_base[i]);
- }
- }
-}
-
-/*
- * Locale Definitions - 2.4 GHz
- */
-static const locale_info_t locale_i = { /* locale i. channel 1 - 13 */
- LOCALE_CHAN_01_11 | LOCALE_CHAN_12_13,
- LOCALE_RADAR_SET_NONE,
- LOCALE_RESTRICTED_SET_2G_SHORT,
- {QDB(19), QDB(19), QDB(19),
- QDB(19), QDB(19), QDB(19)},
- {20, 20, 20, 0},
- WLC_EIRP
-};
-
-/*
- * Locale Definitions - 5 GHz
- */
-static const locale_info_t locale_11 = {
- /* locale 11. channel 36 - 48, 52 - 64, 100 - 140, 149 - 165 */
- LOCALE_CHAN_36_64 | LOCALE_CHAN_100_140 | LOCALE_CHAN_149_165,
- LOCALE_RADAR_SET_1,
- LOCALE_RESTRICTED_NONE,
- {QDB(21), QDB(21), QDB(21), QDB(21), QDB(21)},
- {23, 23, 23, 30, 30},
- WLC_EIRP | WLC_DFS_EU
-};
-
-#define LOCALE_2G_IDX_i 0
-static const locale_info_t *g_locale_2g_table[] = {
- &locale_i
-};
-
-#define LOCALE_5G_IDX_11 0
-static const locale_info_t *g_locale_5g_table[] = {
- &locale_11
-};
-
-/*
- * MIMO Locale Definitions - 2.4 GHz
- */
-static const locale_mimo_info_t locale_bn = {
- {QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
- QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
- QDB(13), QDB(13), QDB(13)},
- {0, 0, QDB(13), QDB(13), QDB(13),
- QDB(13), QDB(13), QDB(13), QDB(13), QDB(13),
- QDB(13), 0, 0},
- 0
-};
-
-/* locale mimo 2g indexes */
-#define LOCALE_MIMO_IDX_bn 0
-
-static const locale_mimo_info_t *g_mimo_2g_table[] = {
- &locale_bn
-};
-
-/*
- * MIMO Locale Definitions - 5 GHz
- */
-static const locale_mimo_info_t locale_11n = {
- { /* 12.5 dBm */ 50, 50, 50, QDB(15), QDB(15)},
- {QDB(14), QDB(15), QDB(15), QDB(15), QDB(15)},
- 0
-};
-
-#define LOCALE_MIMO_IDX_11n 0
-static const locale_mimo_info_t *g_mimo_5g_table[] = {
- &locale_11n
-};
-
-#ifdef LC
-#undef LC
-#endif
-#define LC(id) LOCALE_MIMO_IDX_ ## id
-
-#ifdef LC_2G
-#undef LC_2G
-#endif
-#define LC_2G(id) LOCALE_2G_IDX_ ## id
-
-#ifdef LC_5G
-#undef LC_5G
-#endif
-#define LC_5G(id) LOCALE_5G_IDX_ ## id
-
-#define LOCALES(band2, band5, mimo2, mimo5) {LC_2G(band2), LC_5G(band5), LC(mimo2), LC(mimo5)}
-
-static const struct {
- char abbrev[WLC_CNTRY_BUF_SZ]; /* country abbreviation */
- country_info_t country;
-} cntry_locales[] = {
- {
- "X2", LOCALES(i, 11, bn, 11n)}, /* Worldwide RoW 2 */
-};
-
-#ifdef SUPPORT_40MHZ
-/* 20MHz channel info for 40MHz pairing support */
-struct chan20_info {
- u8 sb;
- u8 adj_sbs;
-};
-
-/* indicates adjacent channels that are allowed for a 40 Mhz channel and
- * those that permitted by the HT
- */
-struct chan20_info chan20_info[] = {
- /* 11b/11g */
-/* 0 */ {1, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 1 */ {2, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 2 */ {3, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 3 */ {4, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 4 */ {5, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
-/* 5 */ {6, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
-/* 6 */ {7, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
-/* 7 */ {8, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
-/* 8 */ {9, (CH_UPPER_SB | CH_LOWER_SB | CH_EWA_VALID)},
-/* 9 */ {10, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 10 */ {11, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 11 */ {12, (CH_LOWER_SB)},
-/* 12 */ {13, (CH_LOWER_SB)},
-/* 13 */ {14, (CH_LOWER_SB)},
-
-/* 11a japan high */
-/* 14 */ {34, (CH_UPPER_SB)},
-/* 15 */ {38, (CH_LOWER_SB)},
-/* 16 */ {42, (CH_LOWER_SB)},
-/* 17 */ {46, (CH_LOWER_SB)},
-
-/* 11a usa low */
-/* 18 */ {36, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 19 */ {40, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 20 */ {44, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 21 */ {48, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 22 */ {52, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 23 */ {56, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 24 */ {60, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 25 */ {64, (CH_LOWER_SB | CH_EWA_VALID)},
-
-/* 11a Europe */
-/* 26 */ {100, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 27 */ {104, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 28 */ {108, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 29 */ {112, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 30 */ {116, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 31 */ {120, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 32 */ {124, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 33 */ {128, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 34 */ {132, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 35 */ {136, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 36 */ {140, (CH_LOWER_SB)},
-
-/* 11a usa high, ref5 only */
-/* The 0x80 bit in pdiv means these are REF5, other entries are REF20 */
-/* 37 */ {149, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 38 */ {153, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 39 */ {157, (CH_UPPER_SB | CH_EWA_VALID)},
-/* 40 */ {161, (CH_LOWER_SB | CH_EWA_VALID)},
-/* 41 */ {165, (CH_LOWER_SB)},
-
-/* 11a japan */
-/* 42 */ {184, (CH_UPPER_SB)},
-/* 43 */ {188, (CH_LOWER_SB)},
-/* 44 */ {192, (CH_UPPER_SB)},
-/* 45 */ {196, (CH_LOWER_SB)},
-/* 46 */ {200, (CH_UPPER_SB)},
-/* 47 */ {204, (CH_LOWER_SB)},
-/* 48 */ {208, (CH_UPPER_SB)},
-/* 49 */ {212, (CH_LOWER_SB)},
-/* 50 */ {216, (CH_LOWER_SB)}
-};
-#endif /* SUPPORT_40MHZ */
-
-static const locale_info_t *wlc_get_locale_2g(u8 locale_idx)
-{
- if (locale_idx >= ARRAY_SIZE(g_locale_2g_table)) {
- return NULL; /* error condition */
- }
- return g_locale_2g_table[locale_idx];
-}
-
-static const locale_info_t *wlc_get_locale_5g(u8 locale_idx)
-{
- if (locale_idx >= ARRAY_SIZE(g_locale_5g_table)) {
- return NULL; /* error condition */
- }
- return g_locale_5g_table[locale_idx];
-}
-
-static const locale_mimo_info_t *wlc_get_mimo_2g(u8 locale_idx)
-{
- if (locale_idx >= ARRAY_SIZE(g_mimo_2g_table)) {
- return NULL;
- }
- return g_mimo_2g_table[locale_idx];
-}
-
-static const locale_mimo_info_t *wlc_get_mimo_5g(u8 locale_idx)
-{
- if (locale_idx >= ARRAY_SIZE(g_mimo_5g_table)) {
- return NULL;
- }
- return g_mimo_5g_table[locale_idx];
-}
-
-wlc_cm_info_t *wlc_channel_mgr_attach(struct wlc_info *wlc)
-{
- wlc_cm_info_t *wlc_cm;
- char country_abbrev[WLC_CNTRY_BUF_SZ];
- const country_info_t *country;
- struct wlc_pub *pub = wlc->pub;
- char *ccode;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-
- wlc_cm = kzalloc(sizeof(wlc_cm_info_t), GFP_ATOMIC);
- if (wlc_cm == NULL) {
- wiphy_err(wlc->wiphy, "wl%d: %s: out of memory", pub->unit,
- __func__);
- return NULL;
- }
- wlc_cm->pub = pub;
- wlc_cm->wlc = wlc;
- wlc->cmi = wlc_cm;
-
- /* store the country code for passing up as a regulatory hint */
- ccode = getvar(wlc->pub->vars, "ccode");
- if (ccode) {
- strncpy(wlc->pub->srom_ccode, ccode, WLC_CNTRY_BUF_SZ - 1);
- }
-
- /* internal country information which must match regulatory constraints in firmware */
- memset(country_abbrev, 0, WLC_CNTRY_BUF_SZ);
- strncpy(country_abbrev, "X2", sizeof(country_abbrev) - 1);
- country = wlc_country_lookup(wlc, country_abbrev);
-
- /* save default country for exiting 11d regulatory mode */
- strncpy(wlc->country_default, country_abbrev, WLC_CNTRY_BUF_SZ - 1);
-
- /* initialize autocountry_default to driver default */
- strncpy(wlc->autocountry_default, "X2", WLC_CNTRY_BUF_SZ - 1);
-
- wlc_set_countrycode(wlc_cm, country_abbrev);
-
- return wlc_cm;
-}
-
-void wlc_channel_mgr_detach(wlc_cm_info_t *wlc_cm)
-{
- kfree(wlc_cm);
-}
-
-u8 wlc_channel_locale_flags_in_band(wlc_cm_info_t *wlc_cm, uint bandunit)
-{
- return wlc_cm->bandstate[bandunit].locale_flags;
-}
-
-/* set the driver's current country and regulatory information using a country code
- * as the source. Lookup built in country information found with the country code.
- */
-static int wlc_set_countrycode(wlc_cm_info_t *wlc_cm, const char *ccode)
-{
- char country_abbrev[WLC_CNTRY_BUF_SZ];
- strncpy(country_abbrev, ccode, WLC_CNTRY_BUF_SZ);
- return wlc_set_countrycode_rev(wlc_cm, country_abbrev, ccode, -1);
-}
-
-static int
-wlc_set_countrycode_rev(wlc_cm_info_t *wlc_cm,
- const char *country_abbrev,
- const char *ccode, int regrev)
-{
- const country_info_t *country;
- char mapped_ccode[WLC_CNTRY_BUF_SZ];
- uint mapped_regrev;
-
- /* if regrev is -1, lookup the mapped country code,
- * otherwise use the ccode and regrev directly
- */
- if (regrev == -1) {
- /* map the country code to a built-in country code, regrev, and country_info */
- country =
- wlc_countrycode_map(wlc_cm, ccode, mapped_ccode,
- &mapped_regrev);
- } else {
- /* find the matching built-in country definition */
- country = wlc_country_lookup_direct(ccode, regrev);
- strncpy(mapped_ccode, ccode, WLC_CNTRY_BUF_SZ);
- mapped_regrev = regrev;
- }
-
- if (country == NULL)
- return -EINVAL;
-
- /* set the driver state for the country */
- wlc_set_country_common(wlc_cm, country_abbrev, mapped_ccode,
- mapped_regrev, country);
-
- return 0;
-}
-
-/* set the driver's current country and regulatory information using a country code
- * as the source. Look up built in country information found with the country code.
- */
-static void
-wlc_set_country_common(wlc_cm_info_t *wlc_cm,
- const char *country_abbrev,
- const char *ccode, uint regrev,
- const country_info_t *country)
-{
- const locale_mimo_info_t *li_mimo;
- const locale_info_t *locale;
- struct wlc_info *wlc = wlc_cm->wlc;
- char prev_country_abbrev[WLC_CNTRY_BUF_SZ];
-
- /* save current country state */
- wlc_cm->country = country;
-
- memset(&prev_country_abbrev, 0, WLC_CNTRY_BUF_SZ);
- strncpy(prev_country_abbrev, wlc_cm->country_abbrev,
- WLC_CNTRY_BUF_SZ - 1);
-
- strncpy(wlc_cm->country_abbrev, country_abbrev, WLC_CNTRY_BUF_SZ - 1);
- strncpy(wlc_cm->ccode, ccode, WLC_CNTRY_BUF_SZ - 1);
- wlc_cm->regrev = regrev;
-
- /* disable/restore nmode based on country regulations */
- li_mimo = wlc_get_mimo_2g(country->locale_mimo_2G);
- if (li_mimo && (li_mimo->flags & WLC_NO_MIMO)) {
- wlc_set_nmode(wlc, OFF);
- wlc->stf->no_cddstbc = true;
- } else {
- wlc->stf->no_cddstbc = false;
- if (N_ENAB(wlc->pub) != wlc->protection->nmode_user)
- wlc_set_nmode(wlc, wlc->protection->nmode_user);
- }
-
- wlc_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
- wlc_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
- /* set or restore gmode as required by regulatory */
- locale = wlc_get_locale_2g(country->locale_2G);
- if (locale && (locale->flags & WLC_NO_OFDM)) {
- wlc_set_gmode(wlc, GMODE_LEGACY_B, false);
- } else {
- wlc_set_gmode(wlc, wlc->protection->gmode_user, false);
- }
-
- wlc_channels_init(wlc_cm, country);
-
- return;
-}
-
-/* Lookup a country info structure from a null terminated country code
- * The lookup is case sensitive.
- */
-static const country_info_t *wlc_country_lookup(struct wlc_info *wlc,
- const char *ccode)
-{
- const country_info_t *country;
- char mapped_ccode[WLC_CNTRY_BUF_SZ];
- uint mapped_regrev;
-
- /* map the country code to a built-in country code, regrev, and country_info struct */
- country =
- wlc_countrycode_map(wlc->cmi, ccode, mapped_ccode, &mapped_regrev);
-
- return country;
-}
-
-static const country_info_t *wlc_countrycode_map(wlc_cm_info_t *wlc_cm,
- const char *ccode,
- char *mapped_ccode,
- uint *mapped_regrev)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
- const country_info_t *country;
- uint srom_regrev = wlc_cm->srom_regrev;
- const char *srom_ccode = wlc_cm->srom_ccode;
- int mapped;
-
- /* check for currently supported ccode size */
- if (strlen(ccode) > (WLC_CNTRY_BUF_SZ - 1)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: ccode \"%s\" too long for "
- "match\n", wlc->pub->unit, __func__, ccode);
- return NULL;
- }
-
- /* default mapping is the given ccode and regrev 0 */
- strncpy(mapped_ccode, ccode, WLC_CNTRY_BUF_SZ);
- *mapped_regrev = 0;
-
- /* If the desired country code matches the srom country code,
- * then the mapped country is the srom regulatory rev.
- * Otherwise look for an aggregate mapping.
- */
- if (!strcmp(srom_ccode, ccode)) {
- *mapped_regrev = srom_regrev;
- mapped = 0;
- wiphy_err(wlc->wiphy, "srom_code == ccode %s\n", __func__);
- } else {
- mapped =
- wlc_country_aggregate_map(wlc_cm, ccode, mapped_ccode,
- mapped_regrev);
- }
-
- /* find the matching built-in country definition */
- country = wlc_country_lookup_direct(mapped_ccode, *mapped_regrev);
-
- /* if there is not an exact rev match, default to rev zero */
- if (country == NULL && *mapped_regrev != 0) {
- *mapped_regrev = 0;
- country =
- wlc_country_lookup_direct(mapped_ccode, *mapped_regrev);
- }
-
- return country;
-}
-
-static int
-wlc_country_aggregate_map(wlc_cm_info_t *wlc_cm, const char *ccode,
- char *mapped_ccode, uint *mapped_regrev)
-{
- return false;
-}
-
-/* Lookup a country info structure from a null terminated country
- * abbreviation and regrev directly with no translation.
- */
-static const country_info_t *wlc_country_lookup_direct(const char *ccode,
- uint regrev)
-{
- uint size, i;
-
- /* Should just return 0 for single locale driver. */
- /* Keep it this way in case we add more locales. (for now anyway) */
-
- /* all other country def arrays are for regrev == 0, so if regrev is non-zero, fail */
- if (regrev > 0)
- return NULL;
-
- /* find matched table entry from country code */
- size = ARRAY_SIZE(cntry_locales);
- for (i = 0; i < size; i++) {
- if (strcmp(ccode, cntry_locales[i].abbrev) == 0) {
- return &cntry_locales[i].country;
- }
- }
- return NULL;
-}
-
-static int
-wlc_channels_init(wlc_cm_info_t *wlc_cm, const country_info_t *country)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
- uint i, j;
- struct wlcband *band;
- const locale_info_t *li;
- chanvec_t sup_chan;
- const locale_mimo_info_t *li_mimo;
-
- band = wlc->band;
- for (i = 0; i < NBANDS(wlc);
- i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
-
- li = BAND_5G(band->bandtype) ?
- wlc_get_locale_5g(country->locale_5G) :
- wlc_get_locale_2g(country->locale_2G);
- wlc_cm->bandstate[band->bandunit].locale_flags = li->flags;
- li_mimo = BAND_5G(band->bandtype) ?
- wlc_get_mimo_5g(country->locale_mimo_5G) :
- wlc_get_mimo_2g(country->locale_mimo_2G);
-
- /* merge the mimo non-mimo locale flags */
- wlc_cm->bandstate[band->bandunit].locale_flags |=
- li_mimo->flags;
-
- wlc_cm->bandstate[band->bandunit].restricted_channels =
- g_table_restricted_chan[li->restricted_channels];
- wlc_cm->bandstate[band->bandunit].radar_channels =
- g_table_radar_set[li->radar_channels];
-
- /* set the channel availability,
- * masking out the channels that may not be supported on this phy
- */
- wlc_phy_chanspec_band_validch(band->pi, band->bandtype,
- &sup_chan);
- wlc_locale_get_channels(li,
- &wlc_cm->bandstate[band->bandunit].
- valid_channels);
- for (j = 0; j < sizeof(chanvec_t); j++)
- wlc_cm->bandstate[band->bandunit].valid_channels.
- vec[j] &= sup_chan.vec[j];
- }
-
- wlc_quiet_channels_reset(wlc_cm);
- wlc_channels_commit(wlc_cm);
-
- return 0;
-}
-
-/* Update the radio state (enable/disable) and tx power targets
- * based on a new set of channel/regulatory information
- */
-static void wlc_channels_commit(wlc_cm_info_t *wlc_cm)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
- uint chan;
- struct txpwr_limits txpwr;
-
- /* search for the existence of any valid channel */
- for (chan = 0; chan < MAXCHANNEL; chan++) {
- if (VALID_CHANNEL20_DB(wlc, chan)) {
- break;
- }
- }
- if (chan == MAXCHANNEL)
- chan = INVCHANNEL;
-
- /* based on the channel search above, set or clear WL_RADIO_COUNTRY_DISABLE */
- if (chan == INVCHANNEL) {
- /* country/locale with no valid channels, set the radio disable bit */
- mboolset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
- wiphy_err(wlc->wiphy, "wl%d: %s: no valid channel for \"%s\" "
- "nbands %d bandlocked %d\n", wlc->pub->unit,
- __func__, wlc_cm->country_abbrev, NBANDS(wlc),
- wlc->bandlocked);
- } else
- if (mboolisset(wlc->pub->radio_disabled,
- WL_RADIO_COUNTRY_DISABLE)) {
- /* country/locale with valid channel, clear the radio disable bit */
- mboolclr(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
- }
-
- /* Now that the country abbreviation is set, if the radio supports 2G, then
- * set channel 14 restrictions based on the new locale.
- */
- if (NBANDS(wlc) > 1 || BAND_2G(wlc->band->bandtype)) {
- wlc_phy_chanspec_ch14_widefilter_set(wlc->band->pi,
- wlc_japan(wlc) ? true :
- false);
- }
-
- if (wlc->pub->up && chan != INVCHANNEL) {
- wlc_channel_reg_limits(wlc_cm, wlc->chanspec, &txpwr);
- wlc_channel_min_txpower_limits_with_local_constraint(wlc_cm,
- &txpwr,
- WLC_TXPWR_MAX);
- wlc_phy_txpower_limit_set(wlc->band->pi, &txpwr, wlc->chanspec);
- }
-}
-
-/* reset the quiet channels vector to the union of the restricted and radar channel sets */
-static void wlc_quiet_channels_reset(wlc_cm_info_t *wlc_cm)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
- uint i, j;
- struct wlcband *band;
- const chanvec_t *chanvec;
-
- memset(&wlc_cm->quiet_channels, 0, sizeof(chanvec_t));
-
- band = wlc->band;
- for (i = 0; i < NBANDS(wlc);
- i++, band = wlc->bandstate[OTHERBANDUNIT(wlc)]) {
-
- /* initialize quiet channels for restricted channels */
- chanvec = wlc_cm->bandstate[band->bandunit].restricted_channels;
- for (j = 0; j < sizeof(chanvec_t); j++)
- wlc_cm->quiet_channels.vec[j] |= chanvec->vec[j];
-
- }
-}
-
-static bool wlc_quiet_chanspec(wlc_cm_info_t *wlc_cm, chanspec_t chspec)
-{
- return N_ENAB(wlc_cm->wlc->pub) && CHSPEC_IS40(chspec) ?
- (isset
- (wlc_cm->quiet_channels.vec,
- LOWER_20_SB(CHSPEC_CHANNEL(chspec)))
- || isset(wlc_cm->quiet_channels.vec,
- UPPER_20_SB(CHSPEC_CHANNEL(chspec)))) : isset(wlc_cm->
- quiet_channels.
- vec,
- CHSPEC_CHANNEL
- (chspec));
-}
-
-/* Is the channel valid for the current locale? (but don't consider channels not
- * available due to bandlocking)
- */
-static bool wlc_valid_channel20_db(wlc_cm_info_t *wlc_cm, uint val)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
-
- return VALID_CHANNEL20(wlc, val) ||
- (!wlc->bandlocked
- && VALID_CHANNEL20_IN_BAND(wlc, OTHERBANDUNIT(wlc), val));
-}
-
-/* Is the channel valid for the current locale and specified band? */
-static bool
-wlc_valid_channel20_in_band(wlc_cm_info_t *wlc_cm, uint bandunit, uint val)
-{
- return ((val < MAXCHANNEL)
- && isset(wlc_cm->bandstate[bandunit].valid_channels.vec, val));
-}
-
-/* Is the channel valid for the current locale and current band? */
-static bool wlc_valid_channel20(wlc_cm_info_t *wlc_cm, uint val)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
-
- return ((val < MAXCHANNEL) &&
- isset(wlc_cm->bandstate[wlc->band->bandunit].valid_channels.vec,
- val));
-}
-
-static void
-wlc_channel_min_txpower_limits_with_local_constraint(wlc_cm_info_t *wlc_cm,
- struct txpwr_limits *txpwr,
- u8
- local_constraint_qdbm)
-{
- int j;
-
- /* CCK Rates */
- for (j = 0; j < WL_TX_POWER_CCK_NUM; j++) {
- txpwr->cck[j] = min(txpwr->cck[j], local_constraint_qdbm);
- }
-
- /* 20 MHz Legacy OFDM SISO */
- for (j = 0; j < WL_TX_POWER_OFDM_NUM; j++) {
- txpwr->ofdm[j] = min(txpwr->ofdm[j], local_constraint_qdbm);
- }
-
- /* 20 MHz Legacy OFDM CDD */
- for (j = 0; j < WLC_NUM_RATES_OFDM; j++) {
- txpwr->ofdm_cdd[j] =
- min(txpwr->ofdm_cdd[j], local_constraint_qdbm);
- }
-
- /* 40 MHz Legacy OFDM SISO */
- for (j = 0; j < WLC_NUM_RATES_OFDM; j++) {
- txpwr->ofdm_40_siso[j] =
- min(txpwr->ofdm_40_siso[j], local_constraint_qdbm);
- }
-
- /* 40 MHz Legacy OFDM CDD */
- for (j = 0; j < WLC_NUM_RATES_OFDM; j++) {
- txpwr->ofdm_40_cdd[j] =
- min(txpwr->ofdm_40_cdd[j], local_constraint_qdbm);
- }
-
- /* 20MHz MCS 0-7 SISO */
- for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
- txpwr->mcs_20_siso[j] =
- min(txpwr->mcs_20_siso[j], local_constraint_qdbm);
- }
-
- /* 20MHz MCS 0-7 CDD */
- for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
- txpwr->mcs_20_cdd[j] =
- min(txpwr->mcs_20_cdd[j], local_constraint_qdbm);
- }
-
- /* 20MHz MCS 0-7 STBC */
- for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
- txpwr->mcs_20_stbc[j] =
- min(txpwr->mcs_20_stbc[j], local_constraint_qdbm);
- }
-
- /* 20MHz MCS 8-15 MIMO */
- for (j = 0; j < WLC_NUM_RATES_MCS_2_STREAM; j++)
- txpwr->mcs_20_mimo[j] =
- min(txpwr->mcs_20_mimo[j], local_constraint_qdbm);
-
- /* 40MHz MCS 0-7 SISO */
- for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
- txpwr->mcs_40_siso[j] =
- min(txpwr->mcs_40_siso[j], local_constraint_qdbm);
- }
-
- /* 40MHz MCS 0-7 CDD */
- for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
- txpwr->mcs_40_cdd[j] =
- min(txpwr->mcs_40_cdd[j], local_constraint_qdbm);
- }
-
- /* 40MHz MCS 0-7 STBC */
- for (j = 0; j < WLC_NUM_RATES_MCS_1_STREAM; j++) {
- txpwr->mcs_40_stbc[j] =
- min(txpwr->mcs_40_stbc[j], local_constraint_qdbm);
- }
-
- /* 40MHz MCS 8-15 MIMO */
- for (j = 0; j < WLC_NUM_RATES_MCS_2_STREAM; j++)
- txpwr->mcs_40_mimo[j] =
- min(txpwr->mcs_40_mimo[j], local_constraint_qdbm);
-
- /* 40MHz MCS 32 */
- txpwr->mcs32 = min(txpwr->mcs32, local_constraint_qdbm);
-
-}
-
-void
-wlc_channel_set_chanspec(wlc_cm_info_t *wlc_cm, chanspec_t chanspec,
- u8 local_constraint_qdbm)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
- struct txpwr_limits txpwr;
-
- wlc_channel_reg_limits(wlc_cm, chanspec, &txpwr);
-
- wlc_channel_min_txpower_limits_with_local_constraint(wlc_cm, &txpwr,
- local_constraint_qdbm);
-
- wlc_bmac_set_chanspec(wlc->hw, chanspec,
- (wlc_quiet_chanspec(wlc_cm, chanspec) != 0),
- &txpwr);
-}
-
-#ifdef POWER_DBG
-static void wlc_phy_txpower_limits_dump(txpwr_limits_t *txpwr)
-{
- int i;
- char buf[80];
- char fraction[4][4] = { " ", ".25", ".5 ", ".75" };
-
- sprintf(buf, "CCK ");
- for (i = 0; i < WLC_NUM_RATES_CCK; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->cck[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->cck[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "20 MHz OFDM SISO ");
- for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->ofdm[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->ofdm[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "20 MHz OFDM CDD ");
- for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->ofdm_cdd[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->ofdm_cdd[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "40 MHz OFDM SISO ");
- for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->ofdm_40_siso[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->ofdm_40_siso[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "40 MHz OFDM CDD ");
- for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->ofdm_40_cdd[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->ofdm_40_cdd[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "20 MHz MCS0-7 SISO ");
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->mcs_20_siso[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs_20_siso[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "20 MHz MCS0-7 CDD ");
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->mcs_20_cdd[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs_20_cdd[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "20 MHz MCS0-7 STBC ");
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->mcs_20_stbc[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs_20_stbc[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "20 MHz MCS8-15 SDM ");
- for (i = 0; i < WLC_NUM_RATES_MCS_2_STREAM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->mcs_20_mimo[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs_20_mimo[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "40 MHz MCS0-7 SISO ");
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->mcs_40_siso[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs_40_siso[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "40 MHz MCS0-7 CDD ");
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->mcs_40_cdd[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs_40_cdd[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "40 MHz MCS0-7 STBC ");
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->mcs_40_stbc[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs_40_stbc[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- sprintf(buf, "40 MHz MCS8-15 SDM ");
- for (i = 0; i < WLC_NUM_RATES_MCS_2_STREAM; i++) {
- sprintf(buf[strlen(buf)], " %2d%s",
- txpwr->mcs_40_mimo[i] / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs_40_mimo[i] % WLC_TXPWR_DB_FACTOR]);
- }
- printk(KERN_DEBUG "%s\n", buf);
-
- printk(KERN_DEBUG "MCS32 %2d%s\n",
- txpwr->mcs32 / WLC_TXPWR_DB_FACTOR,
- fraction[txpwr->mcs32 % WLC_TXPWR_DB_FACTOR]);
-}
-#endif /* POWER_DBG */
-
-void
-wlc_channel_reg_limits(wlc_cm_info_t *wlc_cm, chanspec_t chanspec,
- txpwr_limits_t *txpwr)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
- uint i;
- uint chan;
- int maxpwr;
- int delta;
- const country_info_t *country;
- struct wlcband *band;
- const locale_info_t *li;
- int conducted_max;
- int conducted_ofdm_max;
- const locale_mimo_info_t *li_mimo;
- int maxpwr20, maxpwr40;
- int maxpwr_idx;
- uint j;
-
- memset(txpwr, 0, sizeof(txpwr_limits_t));
-
- if (!wlc_valid_chanspec_db(wlc_cm, chanspec)) {
- country = wlc_country_lookup(wlc, wlc->autocountry_default);
- if (country == NULL)
- return;
- } else {
- country = wlc_cm->country;
- }
-
- chan = CHSPEC_CHANNEL(chanspec);
- band = wlc->bandstate[CHSPEC_WLCBANDUNIT(chanspec)];
- li = BAND_5G(band->bandtype) ?
- wlc_get_locale_5g(country->locale_5G) :
- wlc_get_locale_2g(country->locale_2G);
-
- li_mimo = BAND_5G(band->bandtype) ?
- wlc_get_mimo_5g(country->locale_mimo_5G) :
- wlc_get_mimo_2g(country->locale_mimo_2G);
-
- if (li->flags & WLC_EIRP) {
- delta = band->antgain;
- } else {
- delta = 0;
- if (band->antgain > QDB(6))
- delta = band->antgain - QDB(6); /* Excess over 6 dB */
- }
-
- if (li == &locale_i) {
- conducted_max = QDB(22);
- conducted_ofdm_max = QDB(22);
- }
-
- /* CCK txpwr limits for 2.4G band */
- if (BAND_2G(band->bandtype)) {
- maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_CCK(chan)];
-
- maxpwr = maxpwr - delta;
- maxpwr = max(maxpwr, 0);
- maxpwr = min(maxpwr, conducted_max);
-
- for (i = 0; i < WLC_NUM_RATES_CCK; i++)
- txpwr->cck[i] = (u8) maxpwr;
- }
-
- /* OFDM txpwr limits for 2.4G or 5G bands */
- if (BAND_2G(band->bandtype)) {
- maxpwr = li->maxpwr[CHANNEL_POWER_IDX_2G_OFDM(chan)];
-
- } else {
- maxpwr = li->maxpwr[CHANNEL_POWER_IDX_5G(chan)];
- }
-
- maxpwr = maxpwr - delta;
- maxpwr = max(maxpwr, 0);
- maxpwr = min(maxpwr, conducted_ofdm_max);
-
- /* Keep OFDM lmit below CCK limit */
- if (BAND_2G(band->bandtype))
- maxpwr = min_t(int, maxpwr, txpwr->cck[0]);
-
- for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
- txpwr->ofdm[i] = (u8) maxpwr;
- }
-
- for (i = 0; i < WLC_NUM_RATES_OFDM; i++) {
- /* OFDM 40 MHz SISO has the same power as the corresponding MCS0-7 rate unless
- * overriden by the locale specific code. We set this value to 0 as a
- * flag (presumably 0 dBm isn't a possibility) and then copy the MCS0-7 value
- * to the 40 MHz value if it wasn't explicitly set.
- */
- txpwr->ofdm_40_siso[i] = 0;
-
- txpwr->ofdm_cdd[i] = (u8) maxpwr;
-
- txpwr->ofdm_40_cdd[i] = 0;
- }
-
- /* MIMO/HT specific limits */
- if (li_mimo->flags & WLC_EIRP) {
- delta = band->antgain;
- } else {
- delta = 0;
- if (band->antgain > QDB(6))
- delta = band->antgain - QDB(6); /* Excess over 6 dB */
- }
-
- if (BAND_2G(band->bandtype))
- maxpwr_idx = (chan - 1);
- else
- maxpwr_idx = CHANNEL_POWER_IDX_5G(chan);
-
- maxpwr20 = li_mimo->maxpwr20[maxpwr_idx];
- maxpwr40 = li_mimo->maxpwr40[maxpwr_idx];
-
- maxpwr20 = maxpwr20 - delta;
- maxpwr20 = max(maxpwr20, 0);
- maxpwr40 = maxpwr40 - delta;
- maxpwr40 = max(maxpwr40, 0);
-
- /* Fill in the MCS 0-7 (SISO) rates */
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
-
- /* 20 MHz has the same power as the corresponding OFDM rate unless
- * overriden by the locale specific code.
- */
- txpwr->mcs_20_siso[i] = txpwr->ofdm[i];
- txpwr->mcs_40_siso[i] = 0;
- }
-
- /* Fill in the MCS 0-7 CDD rates */
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- txpwr->mcs_20_cdd[i] = (u8) maxpwr20;
- txpwr->mcs_40_cdd[i] = (u8) maxpwr40;
- }
-
- /* These locales have SISO expressed in the table and override CDD later */
- if (li_mimo == &locale_bn) {
- if (li_mimo == &locale_bn) {
- maxpwr20 = QDB(16);
- maxpwr40 = 0;
-
- if (chan >= 3 && chan <= 11) {
- maxpwr40 = QDB(16);
- }
- }
-
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- txpwr->mcs_20_siso[i] = (u8) maxpwr20;
- txpwr->mcs_40_siso[i] = (u8) maxpwr40;
- }
- }
-
- /* Fill in the MCS 0-7 STBC rates */
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- txpwr->mcs_20_stbc[i] = 0;
- txpwr->mcs_40_stbc[i] = 0;
- }
-
- /* Fill in the MCS 8-15 SDM rates */
- for (i = 0; i < WLC_NUM_RATES_MCS_2_STREAM; i++) {
- txpwr->mcs_20_mimo[i] = (u8) maxpwr20;
- txpwr->mcs_40_mimo[i] = (u8) maxpwr40;
- }
-
- /* Fill in MCS32 */
- txpwr->mcs32 = (u8) maxpwr40;
-
- for (i = 0, j = 0; i < WLC_NUM_RATES_OFDM; i++, j++) {
- if (txpwr->ofdm_40_cdd[i] == 0)
- txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j];
- if (i == 0) {
- i = i + 1;
- if (txpwr->ofdm_40_cdd[i] == 0)
- txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j];
- }
- }
-
- /* Copy the 40 MHZ MCS 0-7 CDD value to the 40 MHZ MCS 0-7 SISO value if it wasn't
- * provided explicitly.
- */
-
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- if (txpwr->mcs_40_siso[i] == 0)
- txpwr->mcs_40_siso[i] = txpwr->mcs_40_cdd[i];
- }
-
- for (i = 0, j = 0; i < WLC_NUM_RATES_OFDM; i++, j++) {
- if (txpwr->ofdm_40_siso[i] == 0)
- txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j];
- if (i == 0) {
- i = i + 1;
- if (txpwr->ofdm_40_siso[i] == 0)
- txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j];
- }
- }
-
- /* Copy the 20 and 40 MHz MCS0-7 CDD values to the corresponding STBC values if they weren't
- * provided explicitly.
- */
- for (i = 0; i < WLC_NUM_RATES_MCS_1_STREAM; i++) {
- if (txpwr->mcs_20_stbc[i] == 0)
- txpwr->mcs_20_stbc[i] = txpwr->mcs_20_cdd[i];
-
- if (txpwr->mcs_40_stbc[i] == 0)
- txpwr->mcs_40_stbc[i] = txpwr->mcs_40_cdd[i];
- }
-
-#ifdef POWER_DBG
- wlc_phy_txpower_limits_dump(txpwr);
-#endif
- return;
-}
-
-/* Returns true if currently set country is Japan or variant */
-static bool wlc_japan(struct wlc_info *wlc)
-{
- return wlc_japan_ccode(wlc->cmi->country_abbrev);
-}
-
-/* JP, J1 - J10 are Japan ccodes */
-static bool wlc_japan_ccode(const char *ccode)
-{
- return (ccode[0] == 'J' &&
- (ccode[1] == 'P' || (ccode[1] >= '1' && ccode[1] <= '9')));
-}
-
-/*
- * Validate the chanspec for this locale, for 40MHZ we need to also check that the sidebands
- * are valid 20MZH channels in this locale and they are also a legal HT combination
- */
-static bool
-wlc_valid_chanspec_ext(wlc_cm_info_t *wlc_cm, chanspec_t chspec, bool dualband)
-{
- struct wlc_info *wlc = wlc_cm->wlc;
- u8 channel = CHSPEC_CHANNEL(chspec);
-
- /* check the chanspec */
- if (brcmu_chspec_malformed(chspec)) {
- wiphy_err(wlc->wiphy, "wl%d: malformed chanspec 0x%x\n",
- wlc->pub->unit, chspec);
- return false;
- }
-
- if (CHANNEL_BANDUNIT(wlc_cm->wlc, channel) !=
- CHSPEC_WLCBANDUNIT(chspec))
- return false;
-
- /* Check a 20Mhz channel */
- if (CHSPEC_IS20(chspec)) {
- if (dualband)
- return VALID_CHANNEL20_DB(wlc_cm->wlc, channel);
- else
- return VALID_CHANNEL20(wlc_cm->wlc, channel);
- }
-#ifdef SUPPORT_40MHZ
- /* We know we are now checking a 40MHZ channel, so we should only be here
- * for NPHYS
- */
- if (WLCISNPHY(wlc->band) || WLCISSSLPNPHY(wlc->band)) {
- u8 upper_sideband = 0, idx;
- u8 num_ch20_entries =
- sizeof(chan20_info) / sizeof(struct chan20_info);
-
- if (!VALID_40CHANSPEC_IN_BAND(wlc, CHSPEC_WLCBANDUNIT(chspec)))
- return false;
-
- if (dualband) {
- if (!VALID_CHANNEL20_DB(wlc, LOWER_20_SB(channel)) ||
- !VALID_CHANNEL20_DB(wlc, UPPER_20_SB(channel)))
- return false;
- } else {
- if (!VALID_CHANNEL20(wlc, LOWER_20_SB(channel)) ||
- !VALID_CHANNEL20(wlc, UPPER_20_SB(channel)))
- return false;
- }
-
- /* find the lower sideband info in the sideband array */
- for (idx = 0; idx < num_ch20_entries; idx++) {
- if (chan20_info[idx].sb == LOWER_20_SB(channel))
- upper_sideband = chan20_info[idx].adj_sbs;
- }
- /* check that the lower sideband allows an upper sideband */
- if ((upper_sideband & (CH_UPPER_SB | CH_EWA_VALID)) ==
- (CH_UPPER_SB | CH_EWA_VALID))
- return true;
- return false;
- }
-#endif /* 40 MHZ */
-
- return false;
-}
-
-bool wlc_valid_chanspec_db(wlc_cm_info_t *wlc_cm, chanspec_t chspec)
-{
- return wlc_valid_chanspec_ext(wlc_cm, chspec, true);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_CHANNEL_H_
-#define _BRCM_CHANNEL_H_
-
-#define WLC_TXPWR_DB_FACTOR 4 /* conversion for phy txpwr cacluations that use .25 dB units */
-
-struct wlc_info;
-
-/* maxpwr mapping to 5GHz band channels:
- * maxpwr[0] - channels [34-48]
- * maxpwr[1] - channels [52-60]
- * maxpwr[2] - channels [62-64]
- * maxpwr[3] - channels [100-140]
- * maxpwr[4] - channels [149-165]
- */
-#define BAND_5G_PWR_LVLS 5 /* 5 power levels for 5G */
-
-/* power level in group of 2.4GHz band channels:
- * maxpwr[0] - CCK channels [1]
- * maxpwr[1] - CCK channels [2-10]
- * maxpwr[2] - CCK channels [11-14]
- * maxpwr[3] - OFDM channels [1]
- * maxpwr[4] - OFDM channels [2-10]
- * maxpwr[5] - OFDM channels [11-14]
- */
-
-/* macro to get 2.4 GHz channel group index for tx power */
-#define CHANNEL_POWER_IDX_2G_CCK(c) (((c) < 2) ? 0 : (((c) < 11) ? 1 : 2)) /* cck index */
-#define CHANNEL_POWER_IDX_2G_OFDM(c) (((c) < 2) ? 3 : (((c) < 11) ? 4 : 5)) /* ofdm index */
-
-/* macro to get 5 GHz channel group index for tx power */
-#define CHANNEL_POWER_IDX_5G(c) \
- (((c) < 52) ? 0 : (((c) < 62) ? 1 : (((c) < 100) ? 2 : (((c) < 149) ? 3 : 4))))
-
-#define WLC_MAXPWR_TBL_SIZE 6 /* max of BAND_5G_PWR_LVLS and 6 for 2.4 GHz */
-#define WLC_MAXPWR_MIMO_TBL_SIZE 14 /* max of BAND_5G_PWR_LVLS and 14 for 2.4 GHz */
-
-/* locale channel and power info. */
-typedef struct {
- u32 valid_channels;
- u8 radar_channels; /* List of radar sensitive channels */
- u8 restricted_channels; /* List of channels used only if APs are detected */
- s8 maxpwr[WLC_MAXPWR_TBL_SIZE]; /* Max tx pwr in qdBm for each sub-band */
- s8 pub_maxpwr[BAND_5G_PWR_LVLS]; /* Country IE advertised max tx pwr in dBm
- * per sub-band
- */
- u8 flags;
-} locale_info_t;
-
-/* bits for locale_info flags */
-#define WLC_PEAK_CONDUCTED 0x00 /* Peak for locals */
-#define WLC_EIRP 0x01 /* Flag for EIRP */
-#define WLC_DFS_TPC 0x02 /* Flag for DFS TPC */
-#define WLC_NO_OFDM 0x04 /* Flag for No OFDM */
-#define WLC_NO_40MHZ 0x08 /* Flag for No MIMO 40MHz */
-#define WLC_NO_MIMO 0x10 /* Flag for No MIMO, 20 or 40 MHz */
-#define WLC_RADAR_TYPE_EU 0x20 /* Flag for EU */
-#define WLC_DFS_FCC WLC_DFS_TPC /* Flag for DFS FCC */
-#define WLC_DFS_EU (WLC_DFS_TPC | WLC_RADAR_TYPE_EU) /* Flag for DFS EU */
-
-#define ISDFS_EU(fl) (((fl) & WLC_DFS_EU) == WLC_DFS_EU)
-
-/* locale per-channel tx power limits for MIMO frames
- * maxpwr arrays are index by channel for 2.4 GHz limits, and
- * by sub-band for 5 GHz limits using CHANNEL_POWER_IDX_5G(channel)
- */
-typedef struct {
- s8 maxpwr20[WLC_MAXPWR_MIMO_TBL_SIZE]; /* tx 20 MHz power limits, qdBm units */
- s8 maxpwr40[WLC_MAXPWR_MIMO_TBL_SIZE]; /* tx 40 MHz power limits, qdBm units */
- u8 flags;
-} locale_mimo_info_t;
-
-extern const chanvec_t chanvec_all_2G;
-extern const chanvec_t chanvec_all_5G;
-
-/*
- * Country names and abbreviations with locale defined from ISO 3166
- */
-struct country_info {
- const u8 locale_2G; /* 2.4G band locale */
- const u8 locale_5G; /* 5G band locale */
- const u8 locale_mimo_2G; /* 2.4G mimo info */
- const u8 locale_mimo_5G; /* 5G mimo info */
-};
-
-typedef struct country_info country_info_t;
-
-typedef struct wlc_cm_info wlc_cm_info_t;
-
-extern wlc_cm_info_t *wlc_channel_mgr_attach(struct wlc_info *wlc);
-extern void wlc_channel_mgr_detach(wlc_cm_info_t *wlc_cm);
-
-extern u8 wlc_channel_locale_flags_in_band(wlc_cm_info_t *wlc_cm,
- uint bandunit);
-
-extern bool wlc_valid_chanspec_db(wlc_cm_info_t *wlc_cm, chanspec_t chspec);
-
-extern void wlc_channel_reg_limits(wlc_cm_info_t *wlc_cm,
- chanspec_t chanspec,
- struct txpwr_limits *txpwr);
-extern void wlc_channel_set_chanspec(wlc_cm_info_t *wlc_cm,
- chanspec_t chanspec,
- u8 local_constraint_qdbm);
-
-#endif /* _WLC_CHANNEL_H */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_KEY_H_
-#define _BRCM_KEY_H_
-
-#include <linux/if_ether.h> /* for ETH_ALEN */
-
-struct scb;
-struct wlc_info;
-struct wlc_bsscfg;
-/* Maximum # of keys that wl driver supports in S/W.
- * Keys supported in H/W is less than or equal to WSEC_MAX_KEYS.
- */
-#define WSEC_MAX_KEYS 54 /* Max # of keys (50 + 4 default keys) */
-#define WLC_DEFAULT_KEYS 4 /* Default # of keys */
-
-#define WSEC_MAX_WOWL_KEYS 5 /* Max keys in WOWL mode (1 + 4 default keys) */
-
-#define WPA2_GTK_MAX 3
-
-/*
-* Max # of keys currently supported:
-*
-* s/w keys if WSEC_SW(wlc->wsec).
-* h/w keys otherwise.
-*/
-#define WLC_MAX_WSEC_KEYS(wlc) WSEC_MAX_KEYS
-
-/* number of 802.11 default (non-paired, group keys) */
-#define WSEC_MAX_DEFAULT_KEYS 4 /* # of default keys */
-
-/* Max # of hardware keys supported */
-#define WLC_MAX_WSEC_HW_KEYS(wlc) WSEC_MAX_RCMTA_KEYS
-
-/* Max # of hardware TKIP MIC keys supported */
-#define WLC_MAX_TKMIC_HW_KEYS(wlc) (WSEC_MAX_TKMIC_ENGINE_KEYS)
-
-#define WSEC_HW_TKMIC_KEY(wlc, key, bsscfg) \
- ((((wlc)->machwcap & MCAP_TKIPMIC)) && \
- (key) && ((key)->algo == CRYPTO_ALGO_TKIP) && \
- !WSEC_SOFTKEY(wlc, key, bsscfg) && \
- WSEC_KEY_INDEX(wlc, key) >= WLC_DEFAULT_KEYS && \
- (WSEC_KEY_INDEX(wlc, key) < WSEC_MAX_TKMIC_ENGINE_KEYS))
-
-/* index of key in key table */
-#define WSEC_KEY_INDEX(wlc, key) ((key)->idx)
-
-#define WSEC_SOFTKEY(wlc, key, bsscfg) (WLC_SW_KEYS(wlc, bsscfg) || \
- WSEC_KEY_INDEX(wlc, key) >= WLC_MAX_WSEC_HW_KEYS(wlc))
-
-/* get a key, non-NULL only if key allocated and not clear */
-#define WSEC_KEY(wlc, i) (((wlc)->wsec_keys[i] && (wlc)->wsec_keys[i]->len) ? \
- (wlc)->wsec_keys[i] : NULL)
-
-#define WSEC_SCB_KEY_VALID(scb) (((scb)->key && (scb)->key->len) ? true : false)
-
-/* default key */
-#define WSEC_BSS_DEFAULT_KEY(bsscfg) (((bsscfg)->wsec_index == -1) ? \
- (struct wsec_key *)NULL:(bsscfg)->bss_def_keys[(bsscfg)->wsec_index])
-
-/* Macros for key management in IBSS mode */
-#define WSEC_IBSS_MAX_PEERS 16 /* Max # of IBSS Peers */
-#define WSEC_IBSS_RCMTA_INDEX(idx) \
- (((idx - WSEC_MAX_DEFAULT_KEYS) % WSEC_IBSS_MAX_PEERS) + WSEC_MAX_DEFAULT_KEYS)
-
-/* contiguous # key slots for infrastructure mode STA */
-#define WSEC_BSS_STA_KEY_GROUP_SIZE 5
-
-typedef struct wsec_iv {
- u32 hi; /* upper 32 bits of IV */
- u16 lo; /* lower 16 bits of IV */
-} wsec_iv_t;
-
-#define WLC_NUMRXIVS 16 /* # rx IVs (one per 802.11e TID) */
-
-typedef struct wsec_key {
- u8 ea[ETH_ALEN]; /* per station */
- u8 idx; /* key index in wsec_keys array */
- u8 id; /* key ID [0-3] */
- u8 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
- u8 rcmta; /* rcmta entry index, same as idx by default */
- u16 flags; /* misc flags */
- u8 algo_hw; /* cache for hw register */
- u8 aes_mode; /* cache for hw register */
- s8 iv_len; /* IV length */
- s8 icv_len; /* ICV length */
- u32 len; /* key length..don't move this var */
- /* data is 4byte aligned */
- u8 data[WLAN_MAX_KEY_LEN]; /* key data */
- wsec_iv_t rxiv[WLC_NUMRXIVS]; /* Rx IV (one per TID) */
- wsec_iv_t txiv; /* Tx IV */
-
-} wsec_key_t;
-
-#define broken_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
-
-/* For use with wsec_key_t.flags */
-
-#define WSEC_BS_UPDATE (1 << 0) /* Indicates hw needs key update on BS switch */
-#define WSEC_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
-#define WSEC_TKIP_ERROR (1 << 2) /* Provoke deliberate MIC error */
-#define WSEC_REPLAY_ERROR (1 << 3) /* Provoke deliberate replay */
-#define WSEC_IBSS_PEER_GROUP_KEY (1 << 7) /* Flag: group key for a IBSS PEER */
-#define WSEC_ICV_ERROR (1 << 8) /* Provoke deliberate ICV error */
-
-#define wlc_key_insert(a, b, c, d, e, f, g, h, i, j) (-EBADE)
-#define wlc_key_update(a, b, c) do {} while (0)
-#define wlc_key_remove(a, b, c) do {} while (0)
-#define wlc_key_remove_all(a, b) do {} while (0)
-#define wlc_key_delete(a, b, c) do {} while (0)
-#define wlc_scb_key_delete(a, b) do {} while (0)
-#define wlc_key_lookup(a, b, c, d, e) (NULL)
-#define wlc_key_hw_init_all(a) do {} while (0)
-#define wlc_key_hw_init(a, b, c) do {} while (0)
-#define wlc_key_hw_wowl_init(a, b, c, d) do {} while (0)
-#define wlc_key_sw_wowl_update(a, b, c, d, e) do {} while (0)
-#define wlc_key_sw_wowl_create(a, b, c) (-EBADE)
-#define wlc_key_iv_update(a, b, c, d, e) do {(void)e; } while (0)
-#define wlc_key_iv_init(a, b, c) do {} while (0)
-#define wlc_key_set_error(a, b, c) (-EBADE)
-#define wlc_key_dump_hw(a, b) (-EBADE)
-#define wlc_key_dump_sw(a, b) (-EBADE)
-#define wlc_key_defkeyflag(a) (0)
-#define wlc_rcmta_add_bssid(a, b) do {} while (0)
-#define wlc_rcmta_del_bssid(a, b) do {} while (0)
-#define wlc_key_scb_delete(a, b) do {} while (0)
-
-#endif /* _BRCM_KEY_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include <linux/kernel.h>
-#include <linux/ctype.h>
-#include <linux/etherdevice.h>
-#include <linux/pci_ids.h>
-#include <net/mac80211.h>
-
-#include <bcmdefs.h>
-#include <bcmdevs.h>
-#include <brcmu_utils.h>
-#include <brcmu_wifi.h>
-#include <aiutils.h>
-#include <bcmsrom.h>
-#include "bcmdma.h"
-#include <bcmdma.h>
-
-#include "wlc_pmu.h"
-#include "d11.h"
-#include "wlc_types.h"
-#include "wlc_cfg.h"
-#include "wlc_rate.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "wlc_key.h"
-#include "wlc_bsscfg.h"
-#include "phy/wlc_phy_hal.h"
-#include "wlc_channel.h"
-#include "wlc_main.h"
-#include "wlc_bmac.h"
-#include "wlc_phy_hal.h"
-#include "wlc_antsel.h"
-#include "wlc_stf.h"
-#include "wlc_ampdu.h"
-#include "wlc_alloc.h"
-#include "brcms_mac80211.h"
-
-/*
- * WPA(2) definitions
- */
-#define RSN_CAP_4_REPLAY_CNTRS 2
-#define RSN_CAP_16_REPLAY_CNTRS 3
-
-#define WPA_CAP_4_REPLAY_CNTRS RSN_CAP_4_REPLAY_CNTRS
-#define WPA_CAP_16_REPLAY_CNTRS RSN_CAP_16_REPLAY_CNTRS
-
-/*
- * Indication for txflowcontrol that all priority bits in
- * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
- */
-#define ALLPRIO -1
-
-/*
- * 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
- */
-#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
-
-#define TIMER_INTERVAL_WATCHDOG 1000 /* watchdog timer, in unit of ms */
-#define TIMER_INTERVAL_RADIOCHK 800 /* radio monitor timer, in unit of ms */
-
-#ifndef WLC_MPC_MAX_DELAYCNT
-#define WLC_MPC_MAX_DELAYCNT 10 /* Max MPC timeout, in unit of watchdog */
-#endif
-#define WLC_MPC_MIN_DELAYCNT 1 /* Min MPC timeout, in unit of watchdog */
-#define WLC_MPC_THRESHOLD 3 /* MPC count threshold level */
-
-#define BEACON_INTERVAL_DEFAULT 100 /* beacon interval, in unit of 1024TU */
-#define DTIM_INTERVAL_DEFAULT 3 /* DTIM interval, in unit of beacon interval */
-
-/* Scale down delays to accommodate QT slow speed */
-#define BEACON_INTERVAL_DEF_QT 20 /* beacon interval, in unit of 1024TU */
-#define DTIM_INTERVAL_DEF_QT 1 /* DTIM interval, in unit of beacon interval */
-
-#define TBTT_ALIGN_LEEWAY_US 100 /* min leeway before first TBTT in us */
-
-/* Software feature flag defines used by wlfeatureflag */
-#define WL_SWFL_NOHWRADIO 0x0004
-#define WL_SWFL_FLOWCONTROL 0x0008 /* Enable backpressure to OS stack */
-#define WL_SWFL_WLBSSSORT 0x0010 /* Per-port supports sorting of BSS */
-
-/* n-mode support capability */
-/* 2x2 includes both 1x1 & 2x2 devices
- * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
- * control it independently
- */
-#define WL_11N_2x2 1
-#define WL_11N_3x3 3
-#define WL_11N_4x4 4
-
-/* define 11n feature disable flags */
-#define WLFEATURE_DISABLE_11N 0x00000001
-#define WLFEATURE_DISABLE_11N_STBC_TX 0x00000002
-#define WLFEATURE_DISABLE_11N_STBC_RX 0x00000004
-#define WLFEATURE_DISABLE_11N_SGI_TX 0x00000008
-#define WLFEATURE_DISABLE_11N_SGI_RX 0x00000010
-#define WLFEATURE_DISABLE_11N_AMPDU_TX 0x00000020
-#define WLFEATURE_DISABLE_11N_AMPDU_RX 0x00000040
-#define WLFEATURE_DISABLE_11N_GF 0x00000080
-
-#define EDCF_ACI_MASK 0x60
-#define EDCF_ACI_SHIFT 5
-#define EDCF_ECWMIN_MASK 0x0f
-#define EDCF_ECWMAX_SHIFT 4
-#define EDCF_AIFSN_MASK 0x0f
-#define EDCF_AIFSN_MAX 15
-#define EDCF_ECWMAX_MASK 0xf0
-
-#define EDCF_AC_BE_TXOP_STA 0x0000
-#define EDCF_AC_BK_TXOP_STA 0x0000
-#define EDCF_AC_VO_ACI_STA 0x62
-#define EDCF_AC_VO_ECW_STA 0x32
-#define EDCF_AC_VI_ACI_STA 0x42
-#define EDCF_AC_VI_ECW_STA 0x43
-#define EDCF_AC_BK_ECW_STA 0xA4
-#define EDCF_AC_VI_TXOP_STA 0x005e
-#define EDCF_AC_VO_TXOP_STA 0x002f
-#define EDCF_AC_BE_ACI_STA 0x03
-#define EDCF_AC_BE_ECW_STA 0xA4
-#define EDCF_AC_BK_ACI_STA 0x27
-#define EDCF_AC_VO_TXOP_AP 0x002f
-
-#define EDCF_TXOP2USEC(txop) ((txop) << 5)
-#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
-
-#define APHY_SYMBOL_TIME 4
-#define APHY_PREAMBLE_TIME 16
-#define APHY_SIGNAL_TIME 4
-#define APHY_SIFS_TIME 16
-#define APHY_SERVICE_NBITS 16
-#define APHY_TAIL_NBITS 6
-#define BPHY_SIFS_TIME 10
-#define BPHY_PLCP_SHORT_TIME 96
-
-#define PREN_PREAMBLE 24
-#define PREN_MM_EXT 12
-#define PREN_PREAMBLE_EXT 4
-
-#define DOT11_MAC_HDR_LEN 24
-#define DOT11_ACK_LEN 10
-#define DOT11_BA_LEN 4
-#define DOT11_OFDM_SIGNAL_EXTENSION 6
-#define DOT11_MIN_FRAG_LEN 256
-#define DOT11_RTS_LEN 16
-#define DOT11_CTS_LEN 10
-#define DOT11_BA_BITMAP_LEN 128
-#define DOT11_MIN_BEACON_PERIOD 1
-#define DOT11_MAX_BEACON_PERIOD 0xFFFF
-#define DOT11_MAXNUMFRAGS 16
-#define DOT11_MAX_FRAG_LEN 2346
-
-#define BPHY_PLCP_TIME 192
-#define RIFS_11N_TIME 2
-
-#define WME_VER 1
-#define WME_SUBTYPE_PARAM_IE 1
-#define WME_TYPE 2
-#define WME_OUI "\x00\x50\xf2"
-
-#define AC_BE 0
-#define AC_BK 1
-#define AC_VI 2
-#define AC_VO 3
-
-/*
- * driver maintains internal 'tick'(wlc->pub->now) which increments in 1s OS timer(soft
- * watchdog) it is not a wall clock and won't increment when driver is in "down" state
- * this low resolution driver tick can be used for maintenance tasks such as phy
- * calibration and scb update
- */
-
-/* To inform the ucode of the last mcast frame posted so that it can clear moredata bit */
-#define BCMCFID(wlc, fid) wlc_bmac_write_shm((wlc)->hw, M_BCMC_FID, (fid))
-
-#define WLC_WAR16165(wlc) (wlc->pub->sih->bustype == PCI_BUS && \
- (!AP_ENAB(wlc->pub)) && (wlc->war16165))
-
-/* debug/trace */
-uint brcm_msg_level =
-#if defined(BCMDBG)
- LOG_ERROR_VAL;
-#else
- 0;
-#endif /* BCMDBG */
-
-/* Find basic rate for a given rate */
-#define WLC_BASIC_RATE(wlc, rspec) (IS_MCS(rspec) ? \
- (wlc)->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK].leg_ofdm] : \
- (wlc)->band->basic_rate[rspec & RSPEC_RATE_MASK])
-
-#define FRAMETYPE(r, mimoframe) (IS_MCS(r) ? mimoframe : (IS_CCK(r) ? FT_CCK : FT_OFDM))
-
-#define RFDISABLE_DEFAULT 10000000 /* rfdisable delay timer 500 ms, runs of ALP clock */
-
-#define WLC_TEMPSENSE_PERIOD 10 /* 10 second timeout */
-
-#define SCAN_IN_PROGRESS(x) 0
-
-#define EPI_VERSION_NUM 0x054b0b00
-
-#ifdef BCMDBG
-/* pointer to most recently allocated wl/wlc */
-static struct wlc_info *wlc_info_dbg = (struct wlc_info *) (NULL);
-#endif
-
-const u8 prio2fifo[NUMPRIO] = {
- TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */
- TX_AC_BK_FIFO, /* 1 BK AC_BK Background */
- TX_AC_BK_FIFO, /* 2 -- AC_BK Background */
- TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */
- TX_AC_VI_FIFO, /* 4 CL AC_VI Video */
- TX_AC_VI_FIFO, /* 5 VI AC_VI Video */
- TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */
- TX_AC_VO_FIFO /* 7 NC AC_VO Voice */
-};
-
-/* precedences numbers for wlc queues. These are twice as may levels as
- * 802.1D priorities.
- * Odd numbers are used for HI priority traffic at same precedence levels
- * These constants are used ONLY by wlc_prio2prec_map. Do not use them elsewhere.
- */
-#define _WLC_PREC_NONE 0 /* None = - */
-#define _WLC_PREC_BK 2 /* BK - Background */
-#define _WLC_PREC_BE 4 /* BE - Best-effort */
-#define _WLC_PREC_EE 6 /* EE - Excellent-effort */
-#define _WLC_PREC_CL 8 /* CL - Controlled Load */
-#define _WLC_PREC_VI 10 /* Vi - Video */
-#define _WLC_PREC_VO 12 /* Vo - Voice */
-#define _WLC_PREC_NC 14 /* NC - Network Control */
-
-/* 802.1D Priority to precedence queue mapping */
-const u8 wlc_prio2prec_map[] = {
- _WLC_PREC_BE, /* 0 BE - Best-effort */
- _WLC_PREC_BK, /* 1 BK - Background */
- _WLC_PREC_NONE, /* 2 None = - */
- _WLC_PREC_EE, /* 3 EE - Excellent-effort */
- _WLC_PREC_CL, /* 4 CL - Controlled Load */
- _WLC_PREC_VI, /* 5 Vi - Video */
- _WLC_PREC_VO, /* 6 Vo - Voice */
- _WLC_PREC_NC, /* 7 NC - Network Control */
-};
-
-/* Sanity check for tx_prec_map and fifo synchup
- * Either there are some packets pending for the fifo, else if fifo is empty then
- * all the corresponding precmap bits should be set
- */
-#define WLC_TX_FIFO_CHECK(wlc, fifo) (TXPKTPENDGET((wlc), (fifo)) || \
- (TXPKTPENDGET((wlc), (fifo)) == 0 && \
- ((wlc)->tx_prec_map & (wlc)->fifo2prec_map[(fifo)]) == \
- (wlc)->fifo2prec_map[(fifo)]))
-
-/* TX FIFO number to WME/802.1E Access Category */
-const u8 wme_fifo2ac[] = { AC_BK, AC_BE, AC_VI, AC_VO, AC_BE, AC_BE };
-
-/* WME/802.1E Access Category to TX FIFO number */
-static const u8 wme_ac2fifo[] = { 1, 0, 2, 3 };
-
-static bool in_send_q = false;
-
-/* Shared memory location index for various AC params */
-#define wme_shmemacindex(ac) wme_ac2fifo[ac]
-
-#ifdef BCMDBG
-static const char *fifo_names[] = {
- "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
-#else
-static const char fifo_names[6][0];
-#endif
-
-static const u8 acbitmap2maxprio[] = {
- PRIO_8021D_BE, PRIO_8021D_BE, PRIO_8021D_BK, PRIO_8021D_BK,
- PRIO_8021D_VI, PRIO_8021D_VI, PRIO_8021D_VI, PRIO_8021D_VI,
- PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO,
- PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO, PRIO_8021D_VO
-};
-
-/* currently the best mechanism for determining SIFS is the band in use */
-#define SIFS(band) ((band)->bandtype == WLC_BAND_5G ? APHY_SIFS_TIME : BPHY_SIFS_TIME);
-
-/* value for # replay counters currently supported */
-#define WLC_REPLAY_CNTRS_VALUE WPA_CAP_16_REPLAY_CNTRS
-
-/* local prototypes */
-static u16 wlc_d11hdrs_mac80211(struct wlc_info *wlc,
- struct ieee80211_hw *hw,
- struct sk_buff *p,
- struct scb *scb, uint frag,
- uint nfrags, uint queue,
- uint next_frag_len,
- wsec_key_t *key,
- ratespec_t rspec_override);
-static void wlc_bss_default_init(struct wlc_info *wlc);
-static void wlc_ucode_mac_upd(struct wlc_info *wlc);
-static ratespec_t mac80211_wlc_set_nrate(struct wlc_info *wlc,
- struct wlcband *cur_band, u32 int_val);
-static void wlc_tx_prec_map_init(struct wlc_info *wlc);
-static void wlc_watchdog(void *arg);
-static void wlc_watchdog_by_timer(void *arg);
-static u16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate);
-static int wlc_set_rateset(struct wlc_info *wlc, wlc_rateset_t *rs_arg);
-static u8 wlc_local_constraint_qdbm(struct wlc_info *wlc);
-
-/* send and receive */
-static struct wlc_txq_info *wlc_txq_alloc(struct wlc_info *wlc);
-static void wlc_txq_free(struct wlc_info *wlc,
- struct wlc_txq_info *qi);
-static void wlc_txflowcontrol_signal(struct wlc_info *wlc,
- struct wlc_txq_info *qi,
- bool on, int prio);
-static void wlc_txflowcontrol_reset(struct wlc_info *wlc);
-static void wlc_compute_cck_plcp(struct wlc_info *wlc, ratespec_t rate,
- uint length, u8 *plcp);
-static void wlc_compute_ofdm_plcp(ratespec_t rate, uint length, u8 *plcp);
-static void wlc_compute_mimo_plcp(ratespec_t rate, uint length, u8 *plcp);
-static u16 wlc_compute_frame_dur(struct wlc_info *wlc, ratespec_t rate,
- u8 preamble_type, uint next_frag_len);
-static u64 wlc_recover_tsf64(struct wlc_info *wlc, struct wlc_d11rxhdr *rxh);
-static void wlc_recvctl(struct wlc_info *wlc,
- d11rxhdr_t *rxh, struct sk_buff *p);
-static uint wlc_calc_frame_len(struct wlc_info *wlc, ratespec_t rate,
- u8 preamble_type, uint dur);
-static uint wlc_calc_ack_time(struct wlc_info *wlc, ratespec_t rate,
- u8 preamble_type);
-static uint wlc_calc_cts_time(struct wlc_info *wlc, ratespec_t rate,
- u8 preamble_type);
-/* interrupt, up/down, band */
-static void wlc_setband(struct wlc_info *wlc, uint bandunit);
-static chanspec_t wlc_init_chanspec(struct wlc_info *wlc);
-static void wlc_bandinit_ordered(struct wlc_info *wlc, chanspec_t chanspec);
-static void wlc_bsinit(struct wlc_info *wlc);
-static int wlc_duty_cycle_set(struct wlc_info *wlc, int duty_cycle, bool isOFDM,
- bool writeToShm);
-static void wlc_radio_hwdisable_upd(struct wlc_info *wlc);
-static bool wlc_radio_monitor_start(struct wlc_info *wlc);
-static void wlc_radio_timer(void *arg);
-static void wlc_radio_enable(struct wlc_info *wlc);
-static void wlc_radio_upd(struct wlc_info *wlc);
-
-/* scan, association, BSS */
-static uint wlc_calc_ba_time(struct wlc_info *wlc, ratespec_t rate,
- u8 preamble_type);
-static void wlc_update_mimo_band_bwcap(struct wlc_info *wlc, u8 bwcap);
-static void wlc_ht_update_sgi_rx(struct wlc_info *wlc, int val);
-static void wlc_ht_update_ldpc(struct wlc_info *wlc, s8 val);
-static void wlc_war16165(struct wlc_info *wlc, bool tx);
-
-static void wlc_wme_retries_write(struct wlc_info *wlc);
-static bool wlc_attach_stf_ant_init(struct wlc_info *wlc);
-static uint wlc_attach_module(struct wlc_info *wlc);
-static void wlc_detach_module(struct wlc_info *wlc);
-static void wlc_timers_deinit(struct wlc_info *wlc);
-static void wlc_down_led_upd(struct wlc_info *wlc);
-static uint wlc_down_del_timer(struct wlc_info *wlc);
-static void wlc_ofdm_rateset_war(struct wlc_info *wlc);
-static int _wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
- struct wlc_if *wlcif);
-
-/* conditions under which the PM bit should be set in outgoing frames and STAY_AWAKE is meaningful
- */
-bool wlc_ps_allowed(struct wlc_info *wlc)
-{
- int idx;
- struct wlc_bsscfg *cfg;
-
- /* disallow PS when one of the following global conditions meets */
- if (!wlc->pub->associated)
- return false;
-
- /* disallow PS when one of these meets when not scanning */
- if (AP_ACTIVE(wlc) || wlc->monitor)
- return false;
-
- FOREACH_AS_STA(wlc, idx, cfg) {
- /* disallow PS when one of the following bsscfg specific conditions meets */
- if (!cfg->BSS || !WLC_PORTOPEN(cfg))
- return false;
-
- if (!cfg->dtim_programmed)
- return false;
- }
-
- return true;
-}
-
-void wlc_reset(struct wlc_info *wlc)
-{
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-
- /* slurp up hw mac counters before core reset */
- wlc_statsupd(wlc);
-
- /* reset our snapshot of macstat counters */
- memset((char *)wlc->core->macstat_snapshot, 0,
- sizeof(macstat_t));
-
- wlc_bmac_reset(wlc->hw);
-}
-
-void wlc_fatal_error(struct wlc_info *wlc)
-{
- wiphy_err(wlc->wiphy, "wl%d: fatal error, reinitializing\n",
- wlc->pub->unit);
- brcms_init(wlc->wl);
-}
-
-/* Return the channel the driver should initialize during wlc_init.
- * the channel may have to be changed from the currently configured channel
- * if other configurations are in conflict (bandlocked, 11n mode disabled,
- * invalid channel for current country, etc.)
- */
-static chanspec_t wlc_init_chanspec(struct wlc_info *wlc)
-{
- chanspec_t chanspec =
- 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
- WL_CHANSPEC_BAND_2G;
-
- return chanspec;
-}
-
-struct scb global_scb;
-
-static void wlc_init_scb(struct wlc_info *wlc, struct scb *scb)
-{
- int i;
- scb->flags = SCB_WMECAP | SCB_HTCAP;
- for (i = 0; i < NUMPRIO; i++)
- scb->seqnum[i] = 0;
-}
-
-void wlc_init(struct wlc_info *wlc)
-{
- d11regs_t *regs;
- chanspec_t chanspec;
- int i;
- struct wlc_bsscfg *bsscfg;
- bool mute = false;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-
- regs = wlc->regs;
-
- /* This will happen if a big-hammer was executed. In that case, we want to go back
- * to the channel that we were on and not new channel
- */
- if (wlc->pub->associated)
- chanspec = wlc->home_chanspec;
- else
- chanspec = wlc_init_chanspec(wlc);
-
- wlc_bmac_init(wlc->hw, chanspec, mute);
-
- /* update beacon listen interval */
- wlc_bcn_li_upd(wlc);
-
- /* the world is new again, so is our reported rate */
- wlc_reprate_init(wlc);
-
- /* write ethernet address to core */
- FOREACH_BSS(wlc, i, bsscfg) {
- wlc_set_mac(bsscfg);
- wlc_set_bssid(bsscfg);
- }
-
- /* Update tsf_cfprep if associated and up */
- if (wlc->pub->associated) {
- FOREACH_BSS(wlc, i, bsscfg) {
- if (bsscfg->up) {
- u32 bi;
-
- /* get beacon period and convert to uS */
- bi = bsscfg->current_bss->beacon_period << 10;
- /*
- * update since init path would reset
- * to default value
- */
- W_REG(®s->tsf_cfprep,
- (bi << CFPREP_CBI_SHIFT));
-
- /* Update maccontrol PM related bits */
- wlc_set_ps_ctrl(wlc);
-
- break;
- }
- }
- }
-
- wlc_key_hw_init_all(wlc);
-
- wlc_bandinit_ordered(wlc, chanspec);
-
- wlc_init_scb(wlc, &global_scb);
-
- /* init probe response timeout */
- wlc_write_shm(wlc, M_PRS_MAXTIME, wlc->prb_resp_timeout);
-
- /* init max burst txop (framebursting) */
- wlc_write_shm(wlc, M_MBURST_TXOP,
- (wlc->
- _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
-
- /* initialize maximum allowed duty cycle */
- wlc_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
- wlc_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
-
- /* Update some shared memory locations related to max AMPDU size allowed to received */
- wlc_ampdu_shm_upd(wlc->ampdu);
-
- /* band-specific inits */
- wlc_bsinit(wlc);
-
- /* Enable EDCF mode (while the MAC is suspended) */
- if (EDCF_ENAB(wlc->pub)) {
- OR_REG(®s->ifs_ctl, IFS_USEEDCF);
- wlc_edcf_setparams(wlc, false);
- }
-
- /* Init precedence maps for empty FIFOs */
- wlc_tx_prec_map_init(wlc);
-
- /* read the ucode version if we have not yet done so */
- if (wlc->ucode_rev == 0) {
- wlc->ucode_rev =
- wlc_read_shm(wlc, M_BOM_REV_MAJOR) << NBITS(u16);
- wlc->ucode_rev |= wlc_read_shm(wlc, M_BOM_REV_MINOR);
- }
-
- /* ..now really unleash hell (allow the MAC out of suspend) */
- wlc_enable_mac(wlc);
-
- /* clear tx flow control */
- wlc_txflowcontrol_reset(wlc);
-
- /* clear tx data fifo suspends */
- wlc->tx_suspended = false;
-
- /* enable the RF Disable Delay timer */
- W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
-
- /* initialize mpc delay */
- wlc->mpc_delay_off = wlc->mpc_dlycnt = WLC_MPC_MIN_DELAYCNT;
-
- /*
- * Initialize WME parameters; if they haven't been set by some other
- * mechanism (IOVar, etc) then read them from the hardware.
- */
- if (WLC_WME_RETRY_SHORT_GET(wlc, 0) == 0) { /* Uninitialized; read from HW */
- int ac;
-
- for (ac = 0; ac < AC_COUNT; ac++) {
- wlc->wme_retries[ac] =
- wlc_read_shm(wlc, M_AC_TXLMT_ADDR(ac));
- }
- }
-}
-
-void wlc_mac_bcn_promisc_change(struct wlc_info *wlc, bool promisc)
-{
- wlc->bcnmisc_monitor = promisc;
- wlc_mac_bcn_promisc(wlc);
-}
-
-void wlc_mac_bcn_promisc(struct wlc_info *wlc)
-{
- if ((AP_ENAB(wlc->pub) && (N_ENAB(wlc->pub) || wlc->band->gmode)) ||
- wlc->bcnmisc_ibss || wlc->bcnmisc_scan || wlc->bcnmisc_monitor)
- wlc_mctrl(wlc, MCTL_BCNS_PROMISC, MCTL_BCNS_PROMISC);
- else
- wlc_mctrl(wlc, MCTL_BCNS_PROMISC, 0);
-}
-
-/* set or clear maccontrol bits MCTL_PROMISC and MCTL_KEEPCONTROL */
-void wlc_mac_promisc(struct wlc_info *wlc)
-{
- u32 promisc_bits = 0;
-
- /* promiscuous mode just sets MCTL_PROMISC
- * Note: APs get all BSS traffic without the need to set the MCTL_PROMISC bit
- * since all BSS data traffic is directed at the AP
- */
- if (PROMISC_ENAB(wlc->pub) && !AP_ENAB(wlc->pub))
- promisc_bits |= MCTL_PROMISC;
-
- /* monitor mode needs both MCTL_PROMISC and MCTL_KEEPCONTROL
- * Note: monitor mode also needs MCTL_BCNS_PROMISC, but that is
- * handled in wlc_mac_bcn_promisc()
- */
- if (MONITOR_ENAB(wlc))
- promisc_bits |= MCTL_PROMISC | MCTL_KEEPCONTROL;
-
- wlc_mctrl(wlc, MCTL_PROMISC | MCTL_KEEPCONTROL, promisc_bits);
-}
-
-/* push sw hps and wake state through hardware */
-void wlc_set_ps_ctrl(struct wlc_info *wlc)
-{
- u32 v1, v2;
- bool hps;
- bool awake_before;
-
- hps = PS_ALLOWED(wlc);
-
- BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
-
- v1 = R_REG(&wlc->regs->maccontrol);
- v2 = MCTL_WAKE;
- if (hps)
- v2 |= MCTL_HPS;
-
- wlc_mctrl(wlc, MCTL_WAKE | MCTL_HPS, v2);
-
- awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
-
- if (!awake_before)
- wlc_bmac_wait_for_wake(wlc->hw);
-
-}
-
-/*
- * Write this BSS config's MAC address to core.
- * Updates RXE match engine.
- */
-int wlc_set_mac(struct wlc_bsscfg *cfg)
-{
- int err = 0;
- struct wlc_info *wlc = cfg->wlc;
-
- if (cfg == wlc->cfg) {
- /* enter the MAC addr into the RXE match registers */
- wlc_set_addrmatch(wlc, RCM_MAC_OFFSET, cfg->cur_etheraddr);
- }
-
- wlc_ampdu_macaddr_upd(wlc);
-
- return err;
-}
-
-/* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
- * Updates RXE match engine.
- */
-void wlc_set_bssid(struct wlc_bsscfg *cfg)
-{
- struct wlc_info *wlc = cfg->wlc;
-
- /* if primary config, we need to update BSSID in RXE match registers */
- if (cfg == wlc->cfg) {
- wlc_set_addrmatch(wlc, RCM_BSSID_OFFSET, cfg->BSSID);
- }
-#ifdef SUPPORT_HWKEYS
- else if (BSSCFG_STA(cfg) && cfg->BSS) {
- wlc_rcmta_add_bssid(wlc, cfg);
- }
-#endif
-}
-
-/*
- * Suspend the the MAC and update the slot timing
- * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
- */
-void wlc_switch_shortslot(struct wlc_info *wlc, bool shortslot)
-{
- int idx;
- struct wlc_bsscfg *cfg;
-
- /* use the override if it is set */
- if (wlc->shortslot_override != WLC_SHORTSLOT_AUTO)
- shortslot = (wlc->shortslot_override == WLC_SHORTSLOT_ON);
-
- if (wlc->shortslot == shortslot)
- return;
-
- wlc->shortslot = shortslot;
-
- /* update the capability based on current shortslot mode */
- FOREACH_BSS(wlc, idx, cfg) {
- if (!cfg->associated)
- continue;
- cfg->current_bss->capability &=
- ~WLAN_CAPABILITY_SHORT_SLOT_TIME;
- if (wlc->shortslot)
- cfg->current_bss->capability |=
- WLAN_CAPABILITY_SHORT_SLOT_TIME;
- }
-
- wlc_bmac_set_shortslot(wlc->hw, shortslot);
-}
-
-static u8 wlc_local_constraint_qdbm(struct wlc_info *wlc)
-{
- u8 local;
- s16 local_max;
-
- local = WLC_TXPWR_MAX;
- if (wlc->pub->associated &&
- (brcmu_chspec_ctlchan(wlc->chanspec) ==
- brcmu_chspec_ctlchan(wlc->home_chanspec))) {
-
- /* get the local power constraint if we are on the AP's
- * channel [802.11h, 7.3.2.13]
- */
- /* Clamp the value between 0 and WLC_TXPWR_MAX w/o overflowing the target */
- local_max =
- (wlc->txpwr_local_max -
- wlc->txpwr_local_constraint) * WLC_TXPWR_DB_FACTOR;
- if (local_max > 0 && local_max < WLC_TXPWR_MAX)
- return (u8) local_max;
- if (local_max < 0)
- return 0;
- }
-
- return local;
-}
-
-/* propagate home chanspec to all bsscfgs in case bsscfg->current_bss->chanspec is referenced */
-void wlc_set_home_chanspec(struct wlc_info *wlc, chanspec_t chanspec)
-{
- if (wlc->home_chanspec != chanspec) {
- int idx;
- struct wlc_bsscfg *cfg;
-
- wlc->home_chanspec = chanspec;
-
- FOREACH_BSS(wlc, idx, cfg) {
- if (!cfg->associated)
- continue;
-
- cfg->current_bss->chanspec = chanspec;
- }
-
- }
-}
-
-static void wlc_set_phy_chanspec(struct wlc_info *wlc, chanspec_t chanspec)
-{
- /* Save our copy of the chanspec */
- wlc->chanspec = chanspec;
-
- /* Set the chanspec and power limits for this locale after computing
- * any 11h local tx power constraints.
- */
- wlc_channel_set_chanspec(wlc->cmi, chanspec,
- wlc_local_constraint_qdbm(wlc));
-
- if (wlc->stf->ss_algosel_auto)
- wlc_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
- chanspec);
-
- wlc_stf_ss_update(wlc, wlc->band);
-
-}
-
-void wlc_set_chanspec(struct wlc_info *wlc, chanspec_t chanspec)
-{
- uint bandunit;
- bool switchband = false;
- chanspec_t old_chanspec = wlc->chanspec;
-
- if (!wlc_valid_chanspec_db(wlc->cmi, chanspec)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
- wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
- return;
- }
-
- /* Switch bands if necessary */
- if (NBANDS(wlc) > 1) {
- bandunit = CHSPEC_WLCBANDUNIT(chanspec);
- if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
- switchband = true;
- if (wlc->bandlocked) {
- wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
- "band is locked!\n",
- wlc->pub->unit, __func__,
- CHSPEC_CHANNEL(chanspec));
- return;
- }
- /* BMAC_NOTE: should the setband call come after the wlc_bmac_chanspec() ?
- * if the setband updates (wlc_bsinit) use low level calls to inspect and
- * set state, the state inspected may be from the wrong band, or the
- * following wlc_bmac_set_chanspec() may undo the work.
- */
- wlc_setband(wlc, bandunit);
- }
- }
-
- /* sync up phy/radio chanspec */
- wlc_set_phy_chanspec(wlc, chanspec);
-
- /* init antenna selection */
- if (CHSPEC_WLC_BW(old_chanspec) != CHSPEC_WLC_BW(chanspec)) {
- wlc_antsel_init(wlc->asi);
-
- /* Fix the hardware rateset based on bw.
- * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
- */
- wlc_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
- wlc->band->
- mimo_cap_40 ? CHSPEC_WLC_BW(chanspec)
- : 0);
- }
-
- /* update some mac configuration since chanspec changed */
- wlc_ucode_mac_upd(wlc);
-}
-
-ratespec_t wlc_lowest_basic_rspec(struct wlc_info *wlc, wlc_rateset_t *rs)
-{
- ratespec_t lowest_basic_rspec;
- uint i;
-
- /* Use the lowest basic rate */
- lowest_basic_rspec = rs->rates[0] & WLC_RATE_MASK;
- for (i = 0; i < rs->count; i++) {
- if (rs->rates[i] & WLC_RATE_FLAG) {
- lowest_basic_rspec = rs->rates[i] & WLC_RATE_MASK;
- break;
- }
- }
-#if NCONF
- /* pick siso/cdd as default for OFDM (note no basic rate MCSs are supported yet) */
- if (IS_OFDM(lowest_basic_rspec)) {
- lowest_basic_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
- }
-#endif
-
- return lowest_basic_rspec;
-}
-
-/* This function changes the phytxctl for beacon based on current beacon ratespec AND txant
- * setting as per this table:
- * ratespec CCK ant = wlc->stf->txant
- * OFDM ant = 3
- */
-void wlc_beacon_phytxctl_txant_upd(struct wlc_info *wlc, ratespec_t bcn_rspec)
-{
- u16 phyctl;
- u16 phytxant = wlc->stf->phytxant;
- u16 mask = PHY_TXC_ANT_MASK;
-
- /* for non-siso rates or default setting, use the available chains */
- if (WLC_PHY_11N_CAP(wlc->band)) {
- phytxant = wlc_stf_phytxchain_sel(wlc, bcn_rspec);
- }
-
- phyctl = wlc_read_shm(wlc, M_BCN_PCTLWD);
- phyctl = (phyctl & ~mask) | phytxant;
- wlc_write_shm(wlc, M_BCN_PCTLWD, phyctl);
-}
-
-/* centralized protection config change function to simplify debugging, no consistency checking
- * this should be called only on changes to avoid overhead in periodic function
-*/
-void wlc_protection_upd(struct wlc_info *wlc, uint idx, int val)
-{
- BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
-
- switch (idx) {
- case WLC_PROT_G_SPEC:
- wlc->protection->_g = (bool) val;
- break;
- case WLC_PROT_G_OVR:
- wlc->protection->g_override = (s8) val;
- break;
- case WLC_PROT_G_USER:
- wlc->protection->gmode_user = (u8) val;
- break;
- case WLC_PROT_OVERLAP:
- wlc->protection->overlap = (s8) val;
- break;
- case WLC_PROT_N_USER:
- wlc->protection->nmode_user = (s8) val;
- break;
- case WLC_PROT_N_CFG:
- wlc->protection->n_cfg = (s8) val;
- break;
- case WLC_PROT_N_CFG_OVR:
- wlc->protection->n_cfg_override = (s8) val;
- break;
- case WLC_PROT_N_NONGF:
- wlc->protection->nongf = (bool) val;
- break;
- case WLC_PROT_N_NONGF_OVR:
- wlc->protection->nongf_override = (s8) val;
- break;
- case WLC_PROT_N_PAM_OVR:
- wlc->protection->n_pam_override = (s8) val;
- break;
- case WLC_PROT_N_OBSS:
- wlc->protection->n_obss = (bool) val;
- break;
-
- default:
- break;
- }
-
-}
-
-static void wlc_ht_update_sgi_rx(struct wlc_info *wlc, int val)
-{
- wlc->ht_cap.cap_info &= ~(IEEE80211_HT_CAP_SGI_20 |
- IEEE80211_HT_CAP_SGI_40);
- wlc->ht_cap.cap_info |= (val & WLC_N_SGI_20) ?
- IEEE80211_HT_CAP_SGI_20 : 0;
- wlc->ht_cap.cap_info |= (val & WLC_N_SGI_40) ?
- IEEE80211_HT_CAP_SGI_40 : 0;
-
- if (wlc->pub->up) {
- wlc_update_beacon(wlc);
- wlc_update_probe_resp(wlc, true);
- }
-}
-
-static void wlc_ht_update_ldpc(struct wlc_info *wlc, s8 val)
-{
- wlc->stf->ldpc = val;
-
- wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_LDPC_CODING;
- if (wlc->stf->ldpc != OFF)
- wlc->ht_cap.cap_info |= IEEE80211_HT_CAP_LDPC_CODING;
-
- if (wlc->pub->up) {
- wlc_update_beacon(wlc);
- wlc_update_probe_resp(wlc, true);
- wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
- }
-}
-
-/*
- * ucode, hwmac update
- * Channel dependent updates for ucode and hw
- */
-static void wlc_ucode_mac_upd(struct wlc_info *wlc)
-{
- /* enable or disable any active IBSSs depending on whether or not
- * we are on the home channel
- */
- if (wlc->home_chanspec == WLC_BAND_PI_RADIO_CHANSPEC) {
- if (wlc->pub->associated) {
- /* BMAC_NOTE: This is something that should be fixed in ucode inits.
- * I think that the ucode inits set up the bcn templates and shm values
- * with a bogus beacon. This should not be done in the inits. If ucode needs
- * to set up a beacon for testing, the test routines should write it down,
- * not expect the inits to populate a bogus beacon.
- */
- if (WLC_PHY_11N_CAP(wlc->band)) {
- wlc_write_shm(wlc, M_BCN_TXTSF_OFFSET,
- wlc->band->bcntsfoff);
- }
- }
- } else {
- /* disable an active IBSS if we are not on the home channel */
- }
-
- /* update the various promisc bits */
- wlc_mac_bcn_promisc(wlc);
- wlc_mac_promisc(wlc);
-}
-
-static void wlc_bandinit_ordered(struct wlc_info *wlc, chanspec_t chanspec)
-{
- wlc_rateset_t default_rateset;
- uint parkband;
- uint i, band_order[2];
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
- /*
- * We might have been bandlocked during down and the chip power-cycled (hibernate).
- * figure out the right band to park on
- */
- if (wlc->bandlocked || NBANDS(wlc) == 1) {
- parkband = wlc->band->bandunit; /* updated in wlc_bandlock() */
- band_order[0] = band_order[1] = parkband;
- } else {
- /* park on the band of the specified chanspec */
- parkband = CHSPEC_WLCBANDUNIT(chanspec);
-
- /* order so that parkband initialize last */
- band_order[0] = parkband ^ 1;
- band_order[1] = parkband;
- }
-
- /* make each band operational, software state init */
- for (i = 0; i < NBANDS(wlc); i++) {
- uint j = band_order[i];
-
- wlc->band = wlc->bandstate[j];
-
- wlc_default_rateset(wlc, &default_rateset);
-
- /* fill in hw_rate */
- wlc_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
- false, WLC_RATES_CCK_OFDM, WLC_RATE_MASK,
- (bool) N_ENAB(wlc->pub));
-
- /* init basic rate lookup */
- wlc_rate_lookup_init(wlc, &default_rateset);
- }
-
- /* sync up phy/radio chanspec */
- wlc_set_phy_chanspec(wlc, chanspec);
-}
-
-/* band-specific init */
-static void WLBANDINITFN(wlc_bsinit) (struct wlc_info *wlc)
-{
- BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
- wlc->pub->unit, wlc->band->bandunit);
-
- /* write ucode ACK/CTS rate table */
- wlc_set_ratetable(wlc);
-
- /* update some band specific mac configuration */
- wlc_ucode_mac_upd(wlc);
-
- /* init antenna selection */
- wlc_antsel_init(wlc->asi);
-
-}
-
-/* switch to and initialize new band */
-static void WLBANDINITFN(wlc_setband) (struct wlc_info *wlc, uint bandunit)
-{
- int idx;
- struct wlc_bsscfg *cfg;
-
- wlc->band = wlc->bandstate[bandunit];
-
- if (!wlc->pub->up)
- return;
-
- /* wait for at least one beacon before entering sleeping state */
- FOREACH_AS_STA(wlc, idx, cfg)
- cfg->PMawakebcn = true;
- wlc_set_ps_ctrl(wlc);
-
- /* band-specific initializations */
- wlc_bsinit(wlc);
-}
-
-/* Initialize a WME Parameter Info Element with default STA parameters from WMM Spec, Table 12 */
-void wlc_wme_initparams_sta(struct wlc_info *wlc, wme_param_ie_t *pe)
-{
- static const wme_param_ie_t stadef = {
- WME_OUI,
- WME_TYPE,
- WME_SUBTYPE_PARAM_IE,
- WME_VER,
- 0,
- 0,
- {
- {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA,
- cpu_to_le16(EDCF_AC_BE_TXOP_STA)},
- {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA,
- cpu_to_le16(EDCF_AC_BK_TXOP_STA)},
- {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA,
- cpu_to_le16(EDCF_AC_VI_TXOP_STA)},
- {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA,
- cpu_to_le16(EDCF_AC_VO_TXOP_STA)}
- }
- };
- memcpy(pe, &stadef, sizeof(*pe));
-}
-
-void wlc_wme_setparams(struct wlc_info *wlc, u16 aci,
- const struct ieee80211_tx_queue_params *params,
- bool suspend)
-{
- int i;
- shm_acparams_t acp_shm;
- u16 *shm_entry;
-
- /* Only apply params if the core is out of reset and has clocks */
- if (!wlc->clk) {
- wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
- __func__);
- return;
- }
-
- do {
- memset((char *)&acp_shm, 0, sizeof(shm_acparams_t));
- /* fill in shm ac params struct */
- acp_shm.txop = le16_to_cpu(params->txop);
- /* convert from units of 32us to us for ucode */
- wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
- EDCF_TXOP2USEC(acp_shm.txop);
- acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
-
- if (aci == AC_VI && acp_shm.txop == 0
- && acp_shm.aifs < EDCF_AIFSN_MAX)
- acp_shm.aifs++;
-
- if (acp_shm.aifs < EDCF_AIFSN_MIN
- || acp_shm.aifs > EDCF_AIFSN_MAX) {
- wiphy_err(wlc->wiphy, "wl%d: wlc_edcf_setparams: bad "
- "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
- continue;
- }
-
- acp_shm.cwmin = params->cw_min;
- acp_shm.cwmax = params->cw_max;
- acp_shm.cwcur = acp_shm.cwmin;
- acp_shm.bslots =
- R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur;
- acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
- /* Indicate the new params to the ucode */
- acp_shm.status = wlc_read_shm(wlc, (M_EDCF_QINFO +
- wme_shmemacindex(aci) *
- M_EDCF_QLEN +
- M_EDCF_STATUS_OFF));
- acp_shm.status |= WME_STATUS_NEWAC;
-
- /* Fill in shm acparam table */
- shm_entry = (u16 *) &acp_shm;
- for (i = 0; i < (int)sizeof(shm_acparams_t); i += 2)
- wlc_write_shm(wlc,
- M_EDCF_QINFO +
- wme_shmemacindex(aci) * M_EDCF_QLEN + i,
- *shm_entry++);
-
- } while (0);
-
- if (suspend)
- wlc_suspend_mac_and_wait(wlc);
-
- if (suspend)
- wlc_enable_mac(wlc);
-
-}
-
-void wlc_edcf_setparams(struct wlc_info *wlc, bool suspend)
-{
- u16 aci;
- int i_ac;
- edcf_acparam_t *edcf_acp;
-
- struct ieee80211_tx_queue_params txq_pars;
- struct ieee80211_tx_queue_params *params = &txq_pars;
-
- /*
- * AP uses AC params from wme_param_ie_ap.
- * AP advertises AC params from wme_param_ie.
- * STA uses AC params from wme_param_ie.
- */
-
- edcf_acp = (edcf_acparam_t *) &wlc->wme_param_ie.acparam[0];
-
- for (i_ac = 0; i_ac < AC_COUNT; i_ac++, edcf_acp++) {
- /* find out which ac this set of params applies to */
- aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
-
- /* fill in shm ac params struct */
- params->txop = edcf_acp->TXOP;
- params->aifs = edcf_acp->ACI;
-
- /* CWmin = 2^(ECWmin) - 1 */
- params->cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
- /* CWmax = 2^(ECWmax) - 1 */
- params->cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
- >> EDCF_ECWMAX_SHIFT);
- wlc_wme_setparams(wlc, aci, params, suspend);
- }
-
- if (suspend)
- wlc_suspend_mac_and_wait(wlc);
-
- if (AP_ENAB(wlc->pub) && WME_ENAB(wlc->pub)) {
- wlc_update_beacon(wlc);
- wlc_update_probe_resp(wlc, false);
- }
-
- if (suspend)
- wlc_enable_mac(wlc);
-
-}
-
-bool wlc_timers_init(struct wlc_info *wlc, int unit)
-{
- wlc->wdtimer = brcms_init_timer(wlc->wl, wlc_watchdog_by_timer,
- wlc, "watchdog");
- if (!wlc->wdtimer) {
- wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
- "failed\n", unit);
- goto fail;
- }
-
- wlc->radio_timer = brcms_init_timer(wlc->wl, wlc_radio_timer,
- wlc, "radio");
- if (!wlc->radio_timer) {
- wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
- "failed\n", unit);
- goto fail;
- }
-
- return true;
-
- fail:
- return false;
-}
-
-/*
- * Initialize wlc_info default values ...
- * may get overrides later in this function
- */
-void wlc_info_init(struct wlc_info *wlc, int unit)
-{
- int i;
- /* Assume the device is there until proven otherwise */
- wlc->device_present = true;
-
- /* Save our copy of the chanspec */
- wlc->chanspec = CH20MHZ_CHSPEC(1);
-
- /* various 802.11g modes */
- wlc->shortslot = false;
- wlc->shortslot_override = WLC_SHORTSLOT_AUTO;
-
- wlc_protection_upd(wlc, WLC_PROT_G_OVR, WLC_PROTECTION_AUTO);
- wlc_protection_upd(wlc, WLC_PROT_G_SPEC, false);
-
- wlc_protection_upd(wlc, WLC_PROT_N_CFG_OVR, WLC_PROTECTION_AUTO);
- wlc_protection_upd(wlc, WLC_PROT_N_CFG, WLC_N_PROTECTION_OFF);
- wlc_protection_upd(wlc, WLC_PROT_N_NONGF_OVR, WLC_PROTECTION_AUTO);
- wlc_protection_upd(wlc, WLC_PROT_N_NONGF, false);
- wlc_protection_upd(wlc, WLC_PROT_N_PAM_OVR, AUTO);
-
- wlc_protection_upd(wlc, WLC_PROT_OVERLAP, WLC_PROTECTION_CTL_OVERLAP);
-
- /* 802.11g draft 4.0 NonERP elt advertisement */
- wlc->include_legacy_erp = true;
-
- wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
- wlc->stf->txant = ANT_TX_DEF;
-
- wlc->prb_resp_timeout = WLC_PRB_RESP_TIMEOUT;
-
- wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
- for (i = 0; i < NFIFO; i++)
- wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
- wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
-
- /* default rate fallback retry limits */
- wlc->SFBL = RETRY_SHORT_FB;
- wlc->LFBL = RETRY_LONG_FB;
-
- /* default mac retry limits */
- wlc->SRL = RETRY_SHORT_DEF;
- wlc->LRL = RETRY_LONG_DEF;
-
- /* Set flag to indicate that hw keys should be used when available. */
- wlc->wsec_swkeys = false;
-
- /* init the 4 static WEP default keys */
- for (i = 0; i < WSEC_MAX_DEFAULT_KEYS; i++) {
- wlc->wsec_keys[i] = wlc->wsec_def_keys[i];
- wlc->wsec_keys[i]->idx = (u8) i;
- }
-
- /* WME QoS mode is Auto by default */
- wlc->pub->_wme = AUTO;
-
-#ifdef BCMSDIODEV_ENABLED
- wlc->pub->_priofc = true; /* enable priority flow control for sdio dongle */
-#endif
-
- wlc->pub->_ampdu = AMPDU_AGG_HOST;
- wlc->pub->bcmerror = 0;
- wlc->pub->_coex = ON;
-
- /* initialize mpc delay */
- wlc->mpc_delay_off = wlc->mpc_dlycnt = WLC_MPC_MIN_DELAYCNT;
-}
-
-static bool wlc_state_bmac_sync(struct wlc_info *wlc)
-{
- wlc_bmac_state_t state_bmac;
-
- if (wlc_bmac_state_get(wlc->hw, &state_bmac) != 0)
- return false;
-
- wlc->machwcap = state_bmac.machwcap;
- wlc_protection_upd(wlc, WLC_PROT_N_PAM_OVR,
- (s8) state_bmac.preamble_ovr);
-
- return true;
-}
-
-static uint wlc_attach_module(struct wlc_info *wlc)
-{
- uint err = 0;
- uint unit;
- unit = wlc->pub->unit;
-
- wlc->asi = wlc_antsel_attach(wlc);
- if (wlc->asi == NULL) {
- wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_antsel_attach "
- "failed\n", unit);
- err = 44;
- goto fail;
- }
-
- wlc->ampdu = wlc_ampdu_attach(wlc);
- if (wlc->ampdu == NULL) {
- wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_ampdu_attach "
- "failed\n", unit);
- err = 50;
- goto fail;
- }
-
- if ((wlc_stf_attach(wlc) != 0)) {
- wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_stf_attach "
- "failed\n", unit);
- err = 68;
- goto fail;
- }
- fail:
- return err;
-}
-
-struct wlc_pub *wlc_pub(void *wlc)
-{
- return ((struct wlc_info *) wlc)->pub;
-}
-
-#define CHIP_SUPPORTS_11N(wlc) 1
-
-/*
- * The common driver entry routine. Error codes should be unique
- */
-void *wlc_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit,
- bool piomode, void *regsva, uint bustype, void *btparam,
- uint *perr)
-{
- struct wlc_info *wlc;
- uint err = 0;
- uint j;
- struct wlc_pub *pub;
- uint n_disabled;
-
- /* allocate struct wlc_info state and its substructures */
- wlc = (struct wlc_info *) wlc_attach_malloc(unit, &err, device);
- if (wlc == NULL)
- goto fail;
- wlc->wiphy = wl->wiphy;
- pub = wlc->pub;
-
-#if defined(BCMDBG)
- wlc_info_dbg = wlc;
-#endif
-
- wlc->band = wlc->bandstate[0];
- wlc->core = wlc->corestate;
- wlc->wl = wl;
- pub->unit = unit;
- pub->_piomode = piomode;
- wlc->bandinit_pending = false;
-
- /* populate struct wlc_info with default values */
- wlc_info_init(wlc, unit);
-
- /* update sta/ap related parameters */
- wlc_ap_upd(wlc);
-
- /* 11n_disable nvram */
- n_disabled = getintvar(pub->vars, "11n_disable");
-
- /*
- * low level attach steps(all hw accesses go
- * inside, no more in rest of the attach)
- */
- err = wlc_bmac_attach(wlc, vendor, device, unit, piomode, regsva,
- bustype, btparam);
- if (err)
- goto fail;
-
- /* for some states, due to different info pointer(e,g, wlc, wlc_hw) or master/slave split,
- * HIGH driver(both monolithic and HIGH_ONLY) needs to sync states FROM BMAC portion driver
- */
- if (!wlc_state_bmac_sync(wlc)) {
- err = 20;
- goto fail;
- }
-
- pub->phy_11ncapable = WLC_PHY_11N_CAP(wlc->band);
-
- /* propagate *vars* from BMAC driver to high driver */
- wlc_bmac_copyfrom_vars(wlc->hw, &pub->vars, &wlc->vars_size);
-
-
- /* set maximum allowed duty cycle */
- wlc->tx_duty_cycle_ofdm =
- (u16) getintvar(pub->vars, "tx_duty_cycle_ofdm");
- wlc->tx_duty_cycle_cck =
- (u16) getintvar(pub->vars, "tx_duty_cycle_cck");
-
- wlc_stf_phy_chain_calc(wlc);
-
- /* txchain 1: txant 0, txchain 2: txant 1 */
- if (WLCISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
- wlc->stf->txant = wlc->stf->hw_txchain - 1;
-
- /* push to BMAC driver */
- wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
- wlc->stf->hw_rxchain);
-
- /* pull up some info resulting from the low attach */
- {
- int i;
- for (i = 0; i < NFIFO; i++)
- wlc->core->txavail[i] = wlc->hw->txavail[i];
- }
-
- wlc_bmac_hw_etheraddr(wlc->hw, wlc->perm_etheraddr);
-
- memcpy(&pub->cur_etheraddr, &wlc->perm_etheraddr, ETH_ALEN);
-
- for (j = 0; j < NBANDS(wlc); j++) {
- /* Use band 1 for single band 11a */
- if (IS_SINGLEBAND_5G(wlc->deviceid))
- j = BAND_5G_INDEX;
-
- wlc->band = wlc->bandstate[j];
-
- if (!wlc_attach_stf_ant_init(wlc)) {
- err = 24;
- goto fail;
- }
-
- /* default contention windows size limits */
- wlc->band->CWmin = APHY_CWMIN;
- wlc->band->CWmax = PHY_CWMAX;
-
- /* init gmode value */
- if (BAND_2G(wlc->band->bandtype)) {
- wlc->band->gmode = GMODE_AUTO;
- wlc_protection_upd(wlc, WLC_PROT_G_USER,
- wlc->band->gmode);
- }
-
- /* init _n_enab supported mode */
- if (WLC_PHY_11N_CAP(wlc->band) && CHIP_SUPPORTS_11N(wlc)) {
- if (n_disabled & WLFEATURE_DISABLE_11N) {
- pub->_n_enab = OFF;
- wlc_protection_upd(wlc, WLC_PROT_N_USER, OFF);
- } else {
- pub->_n_enab = SUPPORT_11N;
- wlc_protection_upd(wlc, WLC_PROT_N_USER,
- ((pub->_n_enab ==
- SUPPORT_11N) ? WL_11N_2x2 :
- WL_11N_3x3));
- }
- }
-
- /* init per-band default rateset, depend on band->gmode */
- wlc_default_rateset(wlc, &wlc->band->defrateset);
-
- /* fill in hw_rateset (used early by WLC_SET_RATESET) */
- wlc_rateset_filter(&wlc->band->defrateset,
- &wlc->band->hw_rateset, false,
- WLC_RATES_CCK_OFDM, WLC_RATE_MASK,
- (bool) N_ENAB(wlc->pub));
- }
-
- /* update antenna config due to wlc->stf->txant/txchain/ant_rx_ovr change */
- wlc_stf_phy_txant_upd(wlc);
-
- /* attach each modules */
- err = wlc_attach_module(wlc);
- if (err != 0)
- goto fail;
-
- if (!wlc_timers_init(wlc, unit)) {
- wiphy_err(wl->wiphy, "wl%d: %s: wlc_init_timer failed\n", unit,
- __func__);
- err = 32;
- goto fail;
- }
-
- /* depend on rateset, gmode */
- wlc->cmi = wlc_channel_mgr_attach(wlc);
- if (!wlc->cmi) {
- wiphy_err(wl->wiphy, "wl%d: %s: wlc_channel_mgr_attach failed"
- "\n", unit, __func__);
- err = 33;
- goto fail;
- }
-
- /* init default when all parameters are ready, i.e. ->rateset */
- wlc_bss_default_init(wlc);
-
- /*
- * Complete the wlc default state initializations..
- */
-
- /* allocate our initial queue */
- wlc->pkt_queue = wlc_txq_alloc(wlc);
- if (wlc->pkt_queue == NULL) {
- wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
- unit, __func__);
- err = 100;
- goto fail;
- }
-
- wlc->bsscfg[0] = wlc->cfg;
- wlc->cfg->_idx = 0;
- wlc->cfg->wlc = wlc;
- pub->txmaxpkts = MAXTXPKTS;
-
- wlc_wme_initparams_sta(wlc, &wlc->wme_param_ie);
-
- wlc->mimoft = FT_HT;
- wlc->ht_cap.cap_info = HT_CAP;
- if (HT_ENAB(wlc->pub))
- wlc->stf->ldpc = AUTO;
-
- wlc->mimo_40txbw = AUTO;
- wlc->ofdm_40txbw = AUTO;
- wlc->cck_40txbw = AUTO;
- wlc_update_mimo_band_bwcap(wlc, WLC_N_BW_20IN2G_40IN5G);
-
- /* Set default values of SGI */
- if (WLC_SGI_CAP_PHY(wlc)) {
- wlc_ht_update_sgi_rx(wlc, (WLC_N_SGI_20 | WLC_N_SGI_40));
- wlc->sgi_tx = AUTO;
- } else if (WLCISSSLPNPHY(wlc->band)) {
- wlc_ht_update_sgi_rx(wlc, (WLC_N_SGI_20 | WLC_N_SGI_40));
- wlc->sgi_tx = AUTO;
- } else {
- wlc_ht_update_sgi_rx(wlc, 0);
- wlc->sgi_tx = OFF;
- }
-
- /* *******nvram 11n config overrides Start ********* */
-
- /* apply the sgi override from nvram conf */
- if (n_disabled & WLFEATURE_DISABLE_11N_SGI_TX)
- wlc->sgi_tx = OFF;
-
- if (n_disabled & WLFEATURE_DISABLE_11N_SGI_RX)
- wlc_ht_update_sgi_rx(wlc, 0);
-
- /* apply the stbc override from nvram conf */
- if (n_disabled & WLFEATURE_DISABLE_11N_STBC_TX) {
- wlc->bandstate[BAND_2G_INDEX]->band_stf_stbc_tx = OFF;
- wlc->bandstate[BAND_5G_INDEX]->band_stf_stbc_tx = OFF;
- wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_TX_STBC;
- }
- if (n_disabled & WLFEATURE_DISABLE_11N_STBC_RX)
- wlc_stf_stbc_rx_set(wlc, HT_CAP_RX_STBC_NO);
-
- /* apply the GF override from nvram conf */
- if (n_disabled & WLFEATURE_DISABLE_11N_GF)
- wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_GRN_FLD;
-
- /* initialize radio_mpc_disable according to wlc->mpc */
- wlc_radio_mpc_upd(wlc);
-
- if ((wlc->pub->sih->chip) == BCM43235_CHIP_ID) {
- if ((getintvar(wlc->pub->vars, "aa2g") == 7) ||
- (getintvar(wlc->pub->vars, "aa5g") == 7)) {
- wlc_bmac_antsel_set(wlc->hw, 1);
- }
- } else {
- wlc_bmac_antsel_set(wlc->hw, wlc->asi->antsel_avail);
- }
-
- if (perr)
- *perr = 0;
-
- return (void *)wlc;
-
- fail:
- wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
- unit, __func__, err);
- if (wlc)
- wlc_detach(wlc);
-
- if (perr)
- *perr = err;
- return NULL;
-}
-
-static void wlc_attach_antgain_init(struct wlc_info *wlc)
-{
- uint unit;
- unit = wlc->pub->unit;
-
- if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
- /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
- wlc->band->antgain = 8;
- } else if (wlc->band->antgain == -1) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
- " srom, using 2dB\n", unit, __func__);
- wlc->band->antgain = 8;
- } else {
- s8 gain, fract;
- /* Older sroms specified gain in whole dbm only. In order
- * be able to specify qdbm granularity and remain backward compatible
- * the whole dbms are now encoded in only low 6 bits and remaining qdbms
- * are encoded in the hi 2 bits. 6 bit signed number ranges from
- * -32 - 31. Examples: 0x1 = 1 db,
- * 0xc1 = 1.75 db (1 + 3 quarters),
- * 0x3f = -1 (-1 + 0 quarters),
- * 0x7f = -.75 (-1 in low 6 bits + 1 quarters in hi 2 bits) = -3 qdbm.
- * 0xbf = -.50 (-1 in low 6 bits + 2 quarters in hi 2 bits) = -2 qdbm.
- */
- gain = wlc->band->antgain & 0x3f;
- gain <<= 2; /* Sign extend */
- gain >>= 2;
- fract = (wlc->band->antgain & 0xc0) >> 6;
- wlc->band->antgain = 4 * gain + fract;
- }
-}
-
-static bool wlc_attach_stf_ant_init(struct wlc_info *wlc)
-{
- int aa;
- uint unit;
- char *vars;
- int bandtype;
-
- unit = wlc->pub->unit;
- vars = wlc->pub->vars;
- bandtype = wlc->band->bandtype;
-
- /* get antennas available */
- aa = (s8) getintvar(vars, (BAND_5G(bandtype) ? "aa5g" : "aa2g"));
- if (aa == 0)
- aa = (s8) getintvar(vars,
- (BAND_5G(bandtype) ? "aa1" : "aa0"));
- if ((aa < 1) || (aa > 15)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
- " srom (0x%x), using 3\n", unit, __func__, aa);
- aa = 3;
- }
-
- /* reset the defaults if we have a single antenna */
- if (aa == 1) {
- wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
- wlc->stf->txant = ANT_TX_FORCE_0;
- } else if (aa == 2) {
- wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
- wlc->stf->txant = ANT_TX_FORCE_1;
- } else {
- }
-
- /* Compute Antenna Gain */
- wlc->band->antgain =
- (s8) getintvar(vars, (BAND_5G(bandtype) ? "ag1" : "ag0"));
- wlc_attach_antgain_init(wlc);
-
- return true;
-}
-
-
-static void wlc_timers_deinit(struct wlc_info *wlc)
-{
- /* free timer state */
- if (wlc->wdtimer) {
- brcms_free_timer(wlc->wl, wlc->wdtimer);
- wlc->wdtimer = NULL;
- }
- if (wlc->radio_timer) {
- brcms_free_timer(wlc->wl, wlc->radio_timer);
- wlc->radio_timer = NULL;
- }
-}
-
-static void wlc_detach_module(struct wlc_info *wlc)
-{
- if (wlc->asi) {
- wlc_antsel_detach(wlc->asi);
- wlc->asi = NULL;
- }
-
- if (wlc->ampdu) {
- wlc_ampdu_detach(wlc->ampdu);
- wlc->ampdu = NULL;
- }
-
- wlc_stf_detach(wlc);
-}
-
-/*
- * Return a count of the number of driver callbacks still pending.
- *
- * General policy is that wlc_detach can only dealloc/free software states. It can NOT
- * touch hardware registers since the d11core may be in reset and clock may not be available.
- * One exception is sb register access, which is possible if crystal is turned on
- * After "down" state, driver should avoid software timer with the exception of radio_monitor.
- */
-uint wlc_detach(struct wlc_info *wlc)
-{
- uint callbacks = 0;
-
- if (wlc == NULL)
- return 0;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-
- callbacks += wlc_bmac_detach(wlc);
-
- /* delete software timers */
- if (!wlc_radio_monitor_stop(wlc))
- callbacks++;
-
- wlc_channel_mgr_detach(wlc->cmi);
-
- wlc_timers_deinit(wlc);
-
- wlc_detach_module(wlc);
-
-
- while (wlc->tx_queues != NULL)
- wlc_txq_free(wlc, wlc->tx_queues);
-
- wlc_detach_mfree(wlc);
- return callbacks;
-}
-
-/* update state that depends on the current value of "ap" */
-void wlc_ap_upd(struct wlc_info *wlc)
-{
- if (AP_ENAB(wlc->pub))
- wlc->PLCPHdr_override = WLC_PLCP_AUTO; /* AP: short not allowed, but not enforced */
- else
- wlc->PLCPHdr_override = WLC_PLCP_SHORT; /* STA-BSS; short capable */
-
- /* fixup mpc */
- wlc->mpc = true;
-}
-
-/* read hwdisable state and propagate to wlc flag */
-static void wlc_radio_hwdisable_upd(struct wlc_info *wlc)
-{
- if (wlc->pub->wlfeatureflag & WL_SWFL_NOHWRADIO || wlc->pub->hw_off)
- return;
-
- if (wlc_bmac_radio_read_hwdisabled(wlc->hw)) {
- mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
- } else {
- mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
- }
-}
-
-/* return true if Minimum Power Consumption should be entered, false otherwise */
-bool wlc_is_non_delay_mpc(struct wlc_info *wlc)
-{
- return false;
-}
-
-bool wlc_ismpc(struct wlc_info *wlc)
-{
- return (wlc->mpc_delay_off == 0) && (wlc_is_non_delay_mpc(wlc));
-}
-
-void wlc_radio_mpc_upd(struct wlc_info *wlc)
-{
- bool mpc_radio, radio_state;
-
- /*
- * Clear the WL_RADIO_MPC_DISABLE bit when mpc feature is disabled
- * in case the WL_RADIO_MPC_DISABLE bit was set. Stop the radio
- * monitor also when WL_RADIO_MPC_DISABLE is the only reason that
- * the radio is going down.
- */
- if (!wlc->mpc) {
- if (!wlc->pub->radio_disabled)
- return;
- mboolclr(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE);
- wlc_radio_upd(wlc);
- if (!wlc->pub->radio_disabled)
- wlc_radio_monitor_stop(wlc);
- return;
- }
-
- /*
- * sync ismpc logic with WL_RADIO_MPC_DISABLE bit in wlc->pub->radio_disabled
- * to go ON, always call radio_upd synchronously
- * to go OFF, postpone radio_upd to later when context is safe(e.g. watchdog)
- */
- radio_state =
- (mboolisset(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE) ? OFF :
- ON);
- mpc_radio = (wlc_ismpc(wlc) == true) ? OFF : ON;
-
- if (radio_state == ON && mpc_radio == OFF)
- wlc->mpc_delay_off = wlc->mpc_dlycnt;
- else if (radio_state == OFF && mpc_radio == ON) {
- mboolclr(wlc->pub->radio_disabled, WL_RADIO_MPC_DISABLE);
- wlc_radio_upd(wlc);
- if (wlc->mpc_offcnt < WLC_MPC_THRESHOLD) {
- wlc->mpc_dlycnt = WLC_MPC_MAX_DELAYCNT;
- } else
- wlc->mpc_dlycnt = WLC_MPC_MIN_DELAYCNT;
- wlc->mpc_dur += OSL_SYSUPTIME() - wlc->mpc_laston_ts;
- }
- /* Below logic is meant to capture the transition from mpc off to mpc on for reasons
- * other than wlc->mpc_delay_off keeping the mpc off. In that case reset
- * wlc->mpc_delay_off to wlc->mpc_dlycnt, so that we restart the countdown of mpc_delay_off
- */
- if ((wlc->prev_non_delay_mpc == false) &&
- (wlc_is_non_delay_mpc(wlc) == true) && wlc->mpc_delay_off) {
- wlc->mpc_delay_off = wlc->mpc_dlycnt;
- }
- wlc->prev_non_delay_mpc = wlc_is_non_delay_mpc(wlc);
-}
-
-/*
- * centralized radio disable/enable function,
- * invoke radio enable/disable after updating hwradio status
- */
-static void wlc_radio_upd(struct wlc_info *wlc)
-{
- if (wlc->pub->radio_disabled) {
- wlc_radio_disable(wlc);
- } else {
- wlc_radio_enable(wlc);
- }
-}
-
-/* maintain LED behavior in down state */
-static void wlc_down_led_upd(struct wlc_info *wlc)
-{
- /* maintain LEDs while in down state, turn on sbclk if not available yet */
- /* turn on sbclk if necessary */
- if (!AP_ENAB(wlc->pub)) {
- wlc_pllreq(wlc, true, WLC_PLLREQ_FLIP);
-
- wlc_pllreq(wlc, false, WLC_PLLREQ_FLIP);
- }
-}
-
-/* update hwradio status and return it */
-bool wlc_check_radio_disabled(struct wlc_info *wlc)
-{
- wlc_radio_hwdisable_upd(wlc);
-
- return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ? true : false;
-}
-
-void wlc_radio_disable(struct wlc_info *wlc)
-{
- if (!wlc->pub->up) {
- wlc_down_led_upd(wlc);
- return;
- }
-
- wlc_radio_monitor_start(wlc);
- brcms_down(wlc->wl);
-}
-
-static void wlc_radio_enable(struct wlc_info *wlc)
-{
- if (wlc->pub->up)
- return;
-
- if (DEVICEREMOVED(wlc))
- return;
-
- brcms_up(wlc->wl);
-}
-
-/* periodical query hw radio button while driver is "down" */
-static void wlc_radio_timer(void *arg)
-{
- struct wlc_info *wlc = (struct wlc_info *) arg;
-
- if (DEVICEREMOVED(wlc)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
- __func__);
- brcms_down(wlc->wl);
- return;
- }
-
- /* cap mpc off count */
- if (wlc->mpc_offcnt < WLC_MPC_MAX_DELAYCNT)
- wlc->mpc_offcnt++;
-
- wlc_radio_hwdisable_upd(wlc);
- wlc_radio_upd(wlc);
-}
-
-static bool wlc_radio_monitor_start(struct wlc_info *wlc)
-{
- /* Don't start the timer if HWRADIO feature is disabled */
- if (wlc->radio_monitor || (wlc->pub->wlfeatureflag & WL_SWFL_NOHWRADIO))
- return true;
-
- wlc->radio_monitor = true;
- wlc_pllreq(wlc, true, WLC_PLLREQ_RADIO_MON);
- brcms_add_timer(wlc->wl, wlc->radio_timer, TIMER_INTERVAL_RADIOCHK,
- true);
- return true;
-}
-
-bool wlc_radio_monitor_stop(struct wlc_info *wlc)
-{
- if (!wlc->radio_monitor)
- return true;
-
- wlc->radio_monitor = false;
- wlc_pllreq(wlc, false, WLC_PLLREQ_RADIO_MON);
- return brcms_del_timer(wlc->wl, wlc->radio_timer);
-}
-
-static void wlc_watchdog_by_timer(void *arg)
-{
- wlc_watchdog(arg);
-}
-
-/* common watchdog code */
-static void wlc_watchdog(void *arg)
-{
- struct wlc_info *wlc = (struct wlc_info *) arg;
- int i;
- struct wlc_bsscfg *cfg;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-
- if (!wlc->pub->up)
- return;
-
- if (DEVICEREMOVED(wlc)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
- __func__);
- brcms_down(wlc->wl);
- return;
- }
-
- /* increment second count */
- wlc->pub->now++;
-
- /* delay radio disable */
- if (wlc->mpc_delay_off) {
- if (--wlc->mpc_delay_off == 0) {
- mboolset(wlc->pub->radio_disabled,
- WL_RADIO_MPC_DISABLE);
- if (wlc->mpc && wlc_ismpc(wlc))
- wlc->mpc_offcnt = 0;
- wlc->mpc_laston_ts = OSL_SYSUPTIME();
- }
- }
-
- /* mpc sync */
- wlc_radio_mpc_upd(wlc);
- /* radio sync: sw/hw/mpc --> radio_disable/radio_enable */
- wlc_radio_hwdisable_upd(wlc);
- wlc_radio_upd(wlc);
- /* if radio is disable, driver may be down, quit here */
- if (wlc->pub->radio_disabled)
- return;
-
- wlc_bmac_watchdog(wlc);
-
- /* occasionally sample mac stat counters to detect 16-bit counter wrap */
- if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
- wlc_statsupd(wlc);
-
- /* Manage TKIP countermeasures timers */
- FOREACH_BSS(wlc, i, cfg) {
- if (cfg->tk_cm_dt) {
- cfg->tk_cm_dt--;
- }
- if (cfg->tk_cm_bt) {
- cfg->tk_cm_bt--;
- }
- }
-
- /* Call any registered watchdog handlers */
- for (i = 0; i < WLC_MAXMODULES; i++) {
- if (wlc->modulecb[i].watchdog_fn)
- wlc->modulecb[i].watchdog_fn(wlc->modulecb[i].hdl);
- }
-
- if (WLCISNPHY(wlc->band) && !wlc->pub->tempsense_disable &&
- ((wlc->pub->now - wlc->tempsense_lasttime) >=
- WLC_TEMPSENSE_PERIOD)) {
- wlc->tempsense_lasttime = wlc->pub->now;
- wlc_tempsense_upd(wlc);
- }
-}
-
-/* make interface operational */
-int wlc_up(struct wlc_info *wlc)
-{
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-
- /* HW is turned off so don't try to access it */
- if (wlc->pub->hw_off || DEVICEREMOVED(wlc))
- return -ENOMEDIUM;
-
- if (!wlc->pub->hw_up) {
- wlc_bmac_hw_up(wlc->hw);
- wlc->pub->hw_up = true;
- }
-
- if ((wlc->pub->boardflags & BFL_FEM)
- && (wlc->pub->sih->chip == BCM4313_CHIP_ID)) {
- if (wlc->pub->boardrev >= 0x1250
- && (wlc->pub->boardflags & BFL_FEM_BT)) {
- wlc_mhf(wlc, MHF5, MHF5_4313_GPIOCTRL,
- MHF5_4313_GPIOCTRL, WLC_BAND_ALL);
- } else {
- wlc_mhf(wlc, MHF4, MHF4_EXTPA_ENABLE, MHF4_EXTPA_ENABLE,
- WLC_BAND_ALL);
- }
- }
-
- /*
- * Need to read the hwradio status here to cover the case where the system
- * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
- * if radio is disabled, abort up, lower power, start radio timer and return 0(for NDIS)
- * don't call radio_update to avoid looping wlc_up.
- *
- * wlc_bmac_up_prep() returns either 0 or -BCME_RADIOOFF only
- */
- if (!wlc->pub->radio_disabled) {
- int status = wlc_bmac_up_prep(wlc->hw);
- if (status == -ENOMEDIUM) {
- if (!mboolisset
- (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
- int idx;
- struct wlc_bsscfg *bsscfg;
- mboolset(wlc->pub->radio_disabled,
- WL_RADIO_HW_DISABLE);
-
- FOREACH_BSS(wlc, idx, bsscfg) {
- if (!BSSCFG_STA(bsscfg)
- || !bsscfg->enable || !bsscfg->BSS)
- continue;
- wiphy_err(wlc->wiphy, "wl%d.%d: wlc_up"
- ": rfdisable -> "
- "wlc_bsscfg_disable()\n",
- wlc->pub->unit, idx);
- }
- }
- }
- }
-
- if (wlc->pub->radio_disabled) {
- wlc_radio_monitor_start(wlc);
- return 0;
- }
-
- /* wlc_bmac_up_prep has done wlc_corereset(). so clk is on, set it */
- wlc->clk = true;
-
- wlc_radio_monitor_stop(wlc);
-
- /* Set EDCF hostflags */
- if (EDCF_ENAB(wlc->pub)) {
- wlc_mhf(wlc, MHF1, MHF1_EDCF, MHF1_EDCF, WLC_BAND_ALL);
- } else {
- wlc_mhf(wlc, MHF1, MHF1_EDCF, 0, WLC_BAND_ALL);
- }
-
- if (WLC_WAR16165(wlc))
- wlc_mhf(wlc, MHF2, MHF2_PCISLOWCLKWAR, MHF2_PCISLOWCLKWAR,
- WLC_BAND_ALL);
-
- brcms_init(wlc->wl);
- wlc->pub->up = true;
-
- if (wlc->bandinit_pending) {
- wlc_suspend_mac_and_wait(wlc);
- wlc_set_chanspec(wlc, wlc->default_bss->chanspec);
- wlc->bandinit_pending = false;
- wlc_enable_mac(wlc);
- }
-
- wlc_bmac_up_finish(wlc->hw);
-
- /* other software states up after ISR is running */
- /* start APs that were to be brought up but are not up yet */
- /* if (AP_ENAB(wlc->pub)) wlc_restart_ap(wlc->ap); */
-
- /* Program the TX wme params with the current settings */
- wlc_wme_retries_write(wlc);
-
- /* start one second watchdog timer */
- brcms_add_timer(wlc->wl, wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
- wlc->WDarmed = true;
-
- /* ensure antenna config is up to date */
- wlc_stf_phy_txant_upd(wlc);
- /* ensure LDPC config is in sync */
- wlc_ht_update_ldpc(wlc, wlc->stf->ldpc);
-
- return 0;
-}
-
-/* Initialize the base precedence map for dequeueing from txq based on WME settings */
-static void wlc_tx_prec_map_init(struct wlc_info *wlc)
-{
- wlc->tx_prec_map = WLC_PREC_BMP_ALL;
- memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16));
-
- /* For non-WME, both fifos have overlapping MAXPRIO. So just disable all precedences
- * if either is full.
- */
- if (!EDCF_ENAB(wlc->pub)) {
- wlc->fifo2prec_map[TX_DATA_FIFO] = WLC_PREC_BMP_ALL;
- wlc->fifo2prec_map[TX_CTL_FIFO] = WLC_PREC_BMP_ALL;
- } else {
- wlc->fifo2prec_map[TX_AC_BK_FIFO] = WLC_PREC_BMP_AC_BK;
- wlc->fifo2prec_map[TX_AC_BE_FIFO] = WLC_PREC_BMP_AC_BE;
- wlc->fifo2prec_map[TX_AC_VI_FIFO] = WLC_PREC_BMP_AC_VI;
- wlc->fifo2prec_map[TX_AC_VO_FIFO] = WLC_PREC_BMP_AC_VO;
- }
-}
-
-static uint wlc_down_del_timer(struct wlc_info *wlc)
-{
- uint callbacks = 0;
-
- return callbacks;
-}
-
-/*
- * Mark the interface nonoperational, stop the software mechanisms,
- * disable the hardware, free any transient buffer state.
- * Return a count of the number of driver callbacks still pending.
- */
-uint wlc_down(struct wlc_info *wlc)
-{
-
- uint callbacks = 0;
- int i;
- bool dev_gone = false;
- struct wlc_txq_info *qi;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-
- /* check if we are already in the going down path */
- if (wlc->going_down) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
- "\n", wlc->pub->unit, __func__);
- return 0;
- }
- if (!wlc->pub->up)
- return callbacks;
-
- /* in between, mpc could try to bring down again.. */
- wlc->going_down = true;
-
- callbacks += wlc_bmac_down_prep(wlc->hw);
-
- dev_gone = DEVICEREMOVED(wlc);
-
- /* Call any registered down handlers */
- for (i = 0; i < WLC_MAXMODULES; i++) {
- if (wlc->modulecb[i].down_fn)
- callbacks +=
- wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
- }
-
- /* cancel the watchdog timer */
- if (wlc->WDarmed) {
- if (!brcms_del_timer(wlc->wl, wlc->wdtimer))
- callbacks++;
- wlc->WDarmed = false;
- }
- /* cancel all other timers */
- callbacks += wlc_down_del_timer(wlc);
-
- wlc->pub->up = false;
-
- wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
-
- /* clear txq flow control */
- wlc_txflowcontrol_reset(wlc);
-
- /* flush tx queues */
- for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
- brcmu_pktq_flush(&qi->q, true, NULL, NULL);
- }
-
- callbacks += wlc_bmac_down_finish(wlc->hw);
-
- /* wlc_bmac_down_finish has done wlc_coredisable(). so clk is off */
- wlc->clk = false;
-
- wlc->going_down = false;
- return callbacks;
-}
-
-/* Set the current gmode configuration */
-int wlc_set_gmode(struct wlc_info *wlc, u8 gmode, bool config)
-{
- int ret = 0;
- uint i;
- wlc_rateset_t rs;
- /* Default to 54g Auto */
- s8 shortslot = WLC_SHORTSLOT_AUTO; /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
- bool shortslot_restrict = false; /* Restrict association to stations that support shortslot
- */
- bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
- int preamble = WLC_PLCP_LONG; /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
- bool preamble_restrict = false; /* Restrict association to stations that support short
- * preambles
- */
- struct wlcband *band;
-
- /* if N-support is enabled, allow Gmode set as long as requested
- * Gmode is not GMODE_LEGACY_B
- */
- if (N_ENAB(wlc->pub) && gmode == GMODE_LEGACY_B)
- return -ENOTSUPP;
-
- /* verify that we are dealing with 2G band and grab the band pointer */
- if (wlc->band->bandtype == WLC_BAND_2G)
- band = wlc->band;
- else if ((NBANDS(wlc) > 1) &&
- (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == WLC_BAND_2G))
- band = wlc->bandstate[OTHERBANDUNIT(wlc)];
- else
- return -EINVAL;
-
- /* Legacy or bust when no OFDM is supported by regulatory */
- if ((wlc_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
- WLC_NO_OFDM) && (gmode != GMODE_LEGACY_B))
- return -EINVAL;
-
- /* update configuration value */
- if (config == true)
- wlc_protection_upd(wlc, WLC_PROT_G_USER, gmode);
-
- /* Clear supported rates filter */
- memset(&wlc->sup_rates_override, 0, sizeof(wlc_rateset_t));
-
- /* Clear rateset override */
- memset(&rs, 0, sizeof(wlc_rateset_t));
-
- switch (gmode) {
- case GMODE_LEGACY_B:
- shortslot = WLC_SHORTSLOT_OFF;
- wlc_rateset_copy(&gphy_legacy_rates, &rs);
-
- break;
-
- case GMODE_LRS:
- if (AP_ENAB(wlc->pub))
- wlc_rateset_copy(&cck_rates, &wlc->sup_rates_override);
- break;
-
- case GMODE_AUTO:
- /* Accept defaults */
- break;
-
- case GMODE_ONLY:
- ofdm_basic = true;
- preamble = WLC_PLCP_SHORT;
- preamble_restrict = true;
- break;
-
- case GMODE_PERFORMANCE:
- if (AP_ENAB(wlc->pub)) /* Put all rates into the Supported Rates element */
- wlc_rateset_copy(&cck_ofdm_rates,
- &wlc->sup_rates_override);
-
- shortslot = WLC_SHORTSLOT_ON;
- shortslot_restrict = true;
- ofdm_basic = true;
- preamble = WLC_PLCP_SHORT;
- preamble_restrict = true;
- break;
-
- default:
- /* Error */
- wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
- wlc->pub->unit, __func__, gmode);
- return -ENOTSUPP;
- }
-
- /*
- * If we are switching to gmode == GMODE_LEGACY_B,
- * clean up rate info that may refer to OFDM rates.
- */
- if ((gmode == GMODE_LEGACY_B) && (band->gmode != GMODE_LEGACY_B)) {
- band->gmode = gmode;
- if (band->rspec_override && !IS_CCK(band->rspec_override)) {
- band->rspec_override = 0;
- wlc_reprate_init(wlc);
- }
- if (band->mrspec_override && !IS_CCK(band->mrspec_override)) {
- band->mrspec_override = 0;
- }
- }
-
- band->gmode = gmode;
-
- wlc->shortslot_override = shortslot;
-
- if (AP_ENAB(wlc->pub)) {
- /* wlc->ap->shortslot_restrict = shortslot_restrict; */
- wlc->PLCPHdr_override =
- (preamble !=
- WLC_PLCP_LONG) ? WLC_PLCP_SHORT : WLC_PLCP_AUTO;
- }
-
- if ((AP_ENAB(wlc->pub) && preamble != WLC_PLCP_LONG)
- || preamble == WLC_PLCP_SHORT)
- wlc->default_bss->capability |= WLAN_CAPABILITY_SHORT_PREAMBLE;
- else
- wlc->default_bss->capability &= ~WLAN_CAPABILITY_SHORT_PREAMBLE;
-
- /* Update shortslot capability bit for AP and IBSS */
- if ((AP_ENAB(wlc->pub) && shortslot == WLC_SHORTSLOT_AUTO) ||
- shortslot == WLC_SHORTSLOT_ON)
- wlc->default_bss->capability |= WLAN_CAPABILITY_SHORT_SLOT_TIME;
- else
- wlc->default_bss->capability &=
- ~WLAN_CAPABILITY_SHORT_SLOT_TIME;
-
- /* Use the default 11g rateset */
- if (!rs.count)
- wlc_rateset_copy(&cck_ofdm_rates, &rs);
-
- if (ofdm_basic) {
- for (i = 0; i < rs.count; i++) {
- if (rs.rates[i] == WLC_RATE_6M
- || rs.rates[i] == WLC_RATE_12M
- || rs.rates[i] == WLC_RATE_24M)
- rs.rates[i] |= WLC_RATE_FLAG;
- }
- }
-
- /* Set default bss rateset */
- wlc->default_bss->rateset.count = rs.count;
- memcpy(wlc->default_bss->rateset.rates, rs.rates,
- sizeof(wlc->default_bss->rateset.rates));
-
- return ret;
-}
-
-static int wlc_nmode_validate(struct wlc_info *wlc, s32 nmode)
-{
- int err = 0;
-
- switch (nmode) {
-
- case OFF:
- break;
-
- case AUTO:
- case WL_11N_2x2:
- case WL_11N_3x3:
- if (!(WLC_PHY_11N_CAP(wlc->band)))
- err = -EINVAL;
- break;
-
- default:
- err = -EINVAL;
- break;
- }
-
- return err;
-}
-
-int wlc_set_nmode(struct wlc_info *wlc, s32 nmode)
-{
- uint i;
- int err;
-
- err = wlc_nmode_validate(wlc, nmode);
- if (err)
- return err;
-
- switch (nmode) {
- case OFF:
- wlc->pub->_n_enab = OFF;
- wlc->default_bss->flags &= ~WLC_BSS_HT;
- /* delete the mcs rates from the default and hw ratesets */
- wlc_rateset_mcs_clear(&wlc->default_bss->rateset);
- for (i = 0; i < NBANDS(wlc); i++) {
- memset(wlc->bandstate[i]->hw_rateset.mcs, 0,
- MCSSET_LEN);
- if (IS_MCS(wlc->band->rspec_override)) {
- wlc->bandstate[i]->rspec_override = 0;
- wlc_reprate_init(wlc);
- }
- if (IS_MCS(wlc->band->mrspec_override))
- wlc->bandstate[i]->mrspec_override = 0;
- }
- break;
-
- case AUTO:
- if (wlc->stf->txstreams == WL_11N_3x3)
- nmode = WL_11N_3x3;
- else
- nmode = WL_11N_2x2;
- case WL_11N_2x2:
- case WL_11N_3x3:
- /* force GMODE_AUTO if NMODE is ON */
- wlc_set_gmode(wlc, GMODE_AUTO, true);
- if (nmode == WL_11N_3x3)
- wlc->pub->_n_enab = SUPPORT_HT;
- else
- wlc->pub->_n_enab = SUPPORT_11N;
- wlc->default_bss->flags |= WLC_BSS_HT;
- /* add the mcs rates to the default and hw ratesets */
- wlc_rateset_mcs_build(&wlc->default_bss->rateset,
- wlc->stf->txstreams);
- for (i = 0; i < NBANDS(wlc); i++)
- memcpy(wlc->bandstate[i]->hw_rateset.mcs,
- wlc->default_bss->rateset.mcs, MCSSET_LEN);
- break;
-
- default:
- break;
- }
-
- return err;
-}
-
-static int wlc_set_rateset(struct wlc_info *wlc, wlc_rateset_t *rs_arg)
-{
- wlc_rateset_t rs, new;
- uint bandunit;
-
- memcpy(&rs, rs_arg, sizeof(wlc_rateset_t));
-
- /* check for bad count value */
- if ((rs.count == 0) || (rs.count > WLC_NUMRATES))
- return -EINVAL;
-
- /* try the current band */
- bandunit = wlc->band->bandunit;
- memcpy(&new, &rs, sizeof(wlc_rateset_t));
- if (wlc_rate_hwrs_filter_sort_validate
- (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
- wlc->stf->txstreams))
- goto good;
-
- /* try the other band */
- if (IS_MBAND_UNLOCKED(wlc)) {
- bandunit = OTHERBANDUNIT(wlc);
- memcpy(&new, &rs, sizeof(wlc_rateset_t));
- if (wlc_rate_hwrs_filter_sort_validate(&new,
- &wlc->
- bandstate[bandunit]->
- hw_rateset, true,
- wlc->stf->txstreams))
- goto good;
- }
-
- return -EBADE;
-
- good:
- /* apply new rateset */
- memcpy(&wlc->default_bss->rateset, &new, sizeof(wlc_rateset_t));
- memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
- sizeof(wlc_rateset_t));
- return 0;
-}
-
-/* simplified integer set interface for common ioctl handler */
-int wlc_set(struct wlc_info *wlc, int cmd, int arg)
-{
- return wlc_ioctl(wlc, cmd, (void *)&arg, sizeof(arg), NULL);
-}
-
-/* simplified integer get interface for common ioctl handler */
-int wlc_get(struct wlc_info *wlc, int cmd, int *arg)
-{
- return wlc_ioctl(wlc, cmd, arg, sizeof(int), NULL);
-}
-
-static void wlc_ofdm_rateset_war(struct wlc_info *wlc)
-{
- u8 r;
- bool war = false;
-
- if (wlc->cfg->associated)
- r = wlc->cfg->current_bss->rateset.rates[0];
- else
- r = wlc->default_bss->rateset.rates[0];
-
- wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
-
- return;
-}
-
-int
-wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
- struct wlc_if *wlcif)
-{
- return _wlc_ioctl(wlc, cmd, arg, len, wlcif);
-}
-
-/* common ioctl handler. return: 0=ok, -1=error, positive=particular error */
-static int
-_wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
- struct wlc_if *wlcif)
-{
- int val, *pval;
- bool bool_val;
- int bcmerror;
- d11regs_t *regs;
- struct scb *nextscb;
- bool ta_ok;
- uint band;
- struct wlc_bsscfg *bsscfg;
- wlc_bss_info_t *current_bss;
-
- /* update bsscfg pointer */
- bsscfg = wlc->cfg;
- current_bss = bsscfg->current_bss;
-
- /* initialize the following to get rid of compiler warning */
- nextscb = NULL;
- ta_ok = false;
- band = 0;
-
- /* If the device is turned off, then it's not "removed" */
- if (!wlc->pub->hw_off && DEVICEREMOVED(wlc)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
- __func__);
- brcms_down(wlc->wl);
- return -EBADE;
- }
-
- /* default argument is generic integer */
- pval = arg ? (int *)arg:NULL;
-
- /* This will prevent the misaligned access */
- if (pval && (u32) len >= sizeof(val))
- memcpy(&val, pval, sizeof(val));
- else
- val = 0;
-
- /* bool conversion to avoid duplication below */
- bool_val = val != 0;
- bcmerror = 0;
- regs = wlc->regs;
-
- if ((arg == NULL) || (len <= 0)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Command %d needs arguments\n",
- wlc->pub->unit, __func__, cmd);
- bcmerror = -EINVAL;
- goto done;
- }
-
- switch (cmd) {
-
- case WLC_SET_CHANNEL:{
- chanspec_t chspec = CH20MHZ_CHSPEC(val);
-
- if (val < 0 || val > MAXCHANNEL) {
- bcmerror = -EINVAL;
- break;
- }
-
- if (!wlc_valid_chanspec_db(wlc->cmi, chspec)) {
- bcmerror = -EINVAL;
- break;
- }
-
- if (!wlc->pub->up && IS_MBAND_UNLOCKED(wlc)) {
- if (wlc->band->bandunit !=
- CHSPEC_WLCBANDUNIT(chspec))
- wlc->bandinit_pending = true;
- else
- wlc->bandinit_pending = false;
- }
-
- wlc->default_bss->chanspec = chspec;
- /* wlc_BSSinit() will sanitize the rateset before using it.. */
- if (wlc->pub->up &&
- (WLC_BAND_PI_RADIO_CHANSPEC != chspec)) {
- wlc_set_home_chanspec(wlc, chspec);
- wlc_suspend_mac_and_wait(wlc);
- wlc_set_chanspec(wlc, chspec);
- wlc_enable_mac(wlc);
- }
- break;
- }
-
- case WLC_SET_SRL:
- if (val >= 1 && val <= RETRY_SHORT_MAX) {
- int ac;
- wlc->SRL = (u16) val;
-
- wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
-
- for (ac = 0; ac < AC_COUNT; ac++) {
- WLC_WME_RETRY_SHORT_SET(wlc, ac, wlc->SRL);
- }
- wlc_wme_retries_write(wlc);
- } else
- bcmerror = -EINVAL;
- break;
-
- case WLC_SET_LRL:
- if (val >= 1 && val <= 255) {
- int ac;
- wlc->LRL = (u16) val;
-
- wlc_bmac_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
-
- for (ac = 0; ac < AC_COUNT; ac++) {
- WLC_WME_RETRY_LONG_SET(wlc, ac, wlc->LRL);
- }
- wlc_wme_retries_write(wlc);
- } else
- bcmerror = -EINVAL;
- break;
-
- case WLC_GET_CURR_RATESET:{
- wl_rateset_t *ret_rs = (wl_rateset_t *) arg;
- wlc_rateset_t *rs;
-
- if (wlc->pub->associated)
- rs = ¤t_bss->rateset;
- else
- rs = &wlc->default_bss->rateset;
-
- if (len < (int)(rs->count + sizeof(rs->count))) {
- bcmerror = -EOVERFLOW;
- break;
- }
-
- /* Copy only legacy rateset section */
- ret_rs->count = rs->count;
- memcpy(&ret_rs->rates, &rs->rates, rs->count);
- break;
- }
-
- case WLC_SET_RATESET:{
- wlc_rateset_t rs;
- wl_rateset_t *in_rs = (wl_rateset_t *) arg;
-
- if (len < (int)(in_rs->count + sizeof(in_rs->count))) {
- bcmerror = -EOVERFLOW;
- break;
- }
-
- if (in_rs->count > WLC_NUMRATES) {
- bcmerror = -ENOBUFS;
- break;
- }
-
- memset(&rs, 0, sizeof(wlc_rateset_t));
-
- /* Copy only legacy rateset section */
- rs.count = in_rs->count;
- memcpy(&rs.rates, &in_rs->rates, rs.count);
-
- /* merge rateset coming in with the current mcsset */
- if (N_ENAB(wlc->pub)) {
- if (bsscfg->associated)
- memcpy(rs.mcs,
- ¤t_bss->rateset.mcs[0],
- MCSSET_LEN);
- else
- memcpy(rs.mcs,
- &wlc->default_bss->rateset.mcs[0],
- MCSSET_LEN);
- }
-
- bcmerror = wlc_set_rateset(wlc, &rs);
-
- if (!bcmerror)
- wlc_ofdm_rateset_war(wlc);
-
- break;
- }
-
- case WLC_SET_BCNPRD:
- /* range [1, 0xffff] */
- if (val >= DOT11_MIN_BEACON_PERIOD
- && val <= DOT11_MAX_BEACON_PERIOD) {
- wlc->default_bss->beacon_period = (u16) val;
- } else
- bcmerror = -EINVAL;
- break;
-
- case WLC_GET_PHYLIST:
- {
- unsigned char *cp = arg;
- if (len < 3) {
- bcmerror = -EOVERFLOW;
- break;
- }
-
- if (WLCISNPHY(wlc->band)) {
- *cp++ = 'n';
- } else if (WLCISLCNPHY(wlc->band)) {
- *cp++ = 'c';
- } else if (WLCISSSLPNPHY(wlc->band)) {
- *cp++ = 's';
- }
- *cp = '\0';
- break;
- }
-
- case WLC_SET_SHORTSLOT_OVERRIDE:
- if ((val != WLC_SHORTSLOT_AUTO) &&
- (val != WLC_SHORTSLOT_OFF) && (val != WLC_SHORTSLOT_ON)) {
- bcmerror = -EINVAL;
- break;
- }
-
- wlc->shortslot_override = (s8) val;
-
- /* shortslot is an 11g feature, so no more work if we are
- * currently on the 5G band
- */
- if (BAND_5G(wlc->band->bandtype))
- break;
-
- if (wlc->pub->up && wlc->pub->associated) {
- /* let watchdog or beacon processing update shortslot */
- } else if (wlc->pub->up) {
- /* unassociated shortslot is off */
- wlc_switch_shortslot(wlc, false);
- } else {
- /* driver is down, so just update the wlc_info value */
- if (wlc->shortslot_override == WLC_SHORTSLOT_AUTO) {
- wlc->shortslot = false;
- } else {
- wlc->shortslot =
- (wlc->shortslot_override ==
- WLC_SHORTSLOT_ON);
- }
- }
-
- break;
-
- }
- done:
-
- if (bcmerror)
- wlc->pub->bcmerror = bcmerror;
-
- return bcmerror;
-}
-
-/*
- * register watchdog and down handlers.
- */
-int wlc_module_register(struct wlc_pub *pub,
- const char *name, void *hdl,
- watchdog_fn_t w_fn, down_fn_t d_fn)
-{
- struct wlc_info *wlc = (struct wlc_info *) pub->wlc;
- int i;
-
- /* find an empty entry and just add, no duplication check! */
- for (i = 0; i < WLC_MAXMODULES; i++) {
- if (wlc->modulecb[i].name[0] == '\0') {
- strncpy(wlc->modulecb[i].name, name,
- sizeof(wlc->modulecb[i].name) - 1);
- wlc->modulecb[i].hdl = hdl;
- wlc->modulecb[i].watchdog_fn = w_fn;
- wlc->modulecb[i].down_fn = d_fn;
- return 0;
- }
- }
-
- return -ENOSR;
-}
-
-/* unregister module callbacks */
-int wlc_module_unregister(struct wlc_pub *pub, const char *name, void *hdl)
-{
- struct wlc_info *wlc = (struct wlc_info *) pub->wlc;
- int i;
-
- if (wlc == NULL)
- return -ENODATA;
-
- for (i = 0; i < WLC_MAXMODULES; i++) {
- if (!strcmp(wlc->modulecb[i].name, name) &&
- (wlc->modulecb[i].hdl == hdl)) {
- memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
- return 0;
- }
- }
-
- /* table not found! */
- return -ENODATA;
-}
-
-/* Write WME tunable parameters for retransmit/max rate from wlc struct to ucode */
-static void wlc_wme_retries_write(struct wlc_info *wlc)
-{
- int ac;
-
- /* Need clock to do this */
- if (!wlc->clk)
- return;
-
- for (ac = 0; ac < AC_COUNT; ac++) {
- wlc_write_shm(wlc, M_AC_TXLMT_ADDR(ac), wlc->wme_retries[ac]);
- }
-}
-
-#ifdef BCMDBG
-static const char *supr_reason[] = {
- "None", "PMQ Entry", "Flush request",
- "Previous frag failure", "Channel mismatch",
- "Lifetime Expiry", "Underflow"
-};
-
-static void wlc_print_txs_status(u16 s)
-{
- printk(KERN_DEBUG "[15:12] %d frame attempts\n",
- (s & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT);
- printk(KERN_DEBUG " [11:8] %d rts attempts\n",
- (s & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT);
- printk(KERN_DEBUG " [7] %d PM mode indicated\n",
- ((s & TX_STATUS_PMINDCTD) ? 1 : 0));
- printk(KERN_DEBUG " [6] %d intermediate status\n",
- ((s & TX_STATUS_INTERMEDIATE) ? 1 : 0));
- printk(KERN_DEBUG " [5] %d AMPDU\n",
- (s & TX_STATUS_AMPDU) ? 1 : 0);
- printk(KERN_DEBUG " [4:2] %d Frame Suppressed Reason (%s)\n",
- ((s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT),
- supr_reason[(s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT]);
- printk(KERN_DEBUG " [1] %d acked\n",
- ((s & TX_STATUS_ACK_RCV) ? 1 : 0));
-}
-#endif /* BCMDBG */
-
-void wlc_print_txstatus(tx_status_t *txs)
-{
-#if defined(BCMDBG)
- u16 s = txs->status;
- u16 ackphyrxsh = txs->ackphyrxsh;
-
- printk(KERN_DEBUG "\ntxpkt (MPDU) Complete\n");
-
- printk(KERN_DEBUG "FrameID: %04x ", txs->frameid);
- printk(KERN_DEBUG "TxStatus: %04x", s);
- printk(KERN_DEBUG "\n");
-
- wlc_print_txs_status(s);
-
- printk(KERN_DEBUG "LastTxTime: %04x ", txs->lasttxtime);
- printk(KERN_DEBUG "Seq: %04x ", txs->sequence);
- printk(KERN_DEBUG "PHYTxStatus: %04x ", txs->phyerr);
- printk(KERN_DEBUG "RxAckRSSI: %04x ",
- (ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT);
- printk(KERN_DEBUG "RxAckSQ: %04x",
- (ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
- printk(KERN_DEBUG "\n");
-#endif /* defined(BCMDBG) */
-}
-
-void wlc_statsupd(struct wlc_info *wlc)
-{
- int i;
- macstat_t macstats;
-#ifdef BCMDBG
- u16 delta;
- u16 rxf0ovfl;
- u16 txfunfl[NFIFO];
-#endif /* BCMDBG */
-
- /* if driver down, make no sense to update stats */
- if (!wlc->pub->up)
- return;
-
-#ifdef BCMDBG
- /* save last rx fifo 0 overflow count */
- rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
-
- /* save last tx fifo underflow count */
- for (i = 0; i < NFIFO; i++)
- txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
-#endif /* BCMDBG */
-
- /* Read mac stats from contiguous shared memory */
- wlc_bmac_copyfrom_shm(wlc->hw, M_UCODE_MACSTAT,
- &macstats, sizeof(macstat_t));
-
-#ifdef BCMDBG
- /* check for rx fifo 0 overflow */
- delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
- if (delta)
- wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
- wlc->pub->unit, delta);
-
- /* check for tx fifo underflows */
- for (i = 0; i < NFIFO; i++) {
- delta =
- (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
- txfunfl[i]);
- if (delta)
- wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
- "\n", wlc->pub->unit, delta, i);
- }
-#endif /* BCMDBG */
-
- /* merge counters from dma module */
- for (i = 0; i < NFIFO; i++) {
- if (wlc->hw->di[i]) {
- dma_counterreset(wlc->hw->di[i]);
- }
- }
-}
-
-bool wlc_chipmatch(u16 vendor, u16 device)
-{
- if (vendor != PCI_VENDOR_ID_BROADCOM) {
- pr_err("wlc_chipmatch: unknown vendor id %04x\n", vendor);
- return false;
- }
-
- if (device == BCM43224_D11N_ID_VEN1)
- return true;
- if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
- return true;
- if (device == BCM4313_D11N2G_ID)
- return true;
- if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
- return true;
-
- pr_err("wlc_chipmatch: unknown device id %04x\n", device);
- return false;
-}
-
-#if defined(BCMDBG)
-void wlc_print_txdesc(d11txh_t *txh)
-{
- u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
- u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
- u16 mfc = le16_to_cpu(txh->MacFrameControl);
- u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
- u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
- u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
- u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
- u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
- u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
- u16 mainrates = le16_to_cpu(txh->MainRates);
- u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
- u8 *iv = txh->IV;
- u8 *ra = txh->TxFrameRA;
- u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
- u8 *rtspfb = txh->RTSPLCPFallback;
- u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
- u8 *fragpfb = txh->FragPLCPFallback;
- u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
- u16 mmodelen = le16_to_cpu(txh->MModeLen);
- u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
- u16 tfid = le16_to_cpu(txh->TxFrameID);
- u16 txs = le16_to_cpu(txh->TxStatus);
- u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
- u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
- u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
- u16 mmbyte = le16_to_cpu(txh->MinMBytes);
-
- u8 *rtsph = txh->RTSPhyHeader;
- struct ieee80211_rts rts = txh->rts_frame;
- char hexbuf[256];
-
- /* add plcp header along with txh descriptor */
- printk(KERN_DEBUG "Raw TxDesc + plcp header:\n");
- print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
- txh, sizeof(d11txh_t) + 48);
-
- printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl);
- printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch);
- printk(KERN_DEBUG "FC: %04x ", mfc);
- printk(KERN_DEBUG "FES Time: %04x\n", tfest);
- printk(KERN_DEBUG "PhyCtl: %04x%s ", ptcw,
- (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
- printk(KERN_DEBUG "PhyCtl_1: %04x ", ptcw_1);
- printk(KERN_DEBUG "PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
- printk(KERN_DEBUG "PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
- printk(KERN_DEBUG "PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
- printk(KERN_DEBUG "MainRates: %04x ", mainrates);
- printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft);
- printk(KERN_DEBUG "\n");
-
- brcmu_format_hex(hexbuf, iv, sizeof(txh->IV));
- printk(KERN_DEBUG "SecIV: %s\n", hexbuf);
- brcmu_format_hex(hexbuf, ra, sizeof(txh->TxFrameRA));
- printk(KERN_DEBUG "RA: %s\n", hexbuf);
-
- printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb);
- brcmu_format_hex(hexbuf, rtspfb, sizeof(txh->RTSPLCPFallback));
- printk(KERN_DEBUG "RTS PLCP: %s ", hexbuf);
- printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb);
- brcmu_format_hex(hexbuf, fragpfb, sizeof(txh->FragPLCPFallback));
- printk(KERN_DEBUG "PLCP: %s ", hexbuf);
- printk(KERN_DEBUG "DUR: %04x", fragdfb);
- printk(KERN_DEBUG "\n");
-
- printk(KERN_DEBUG "MModeLen: %04x ", mmodelen);
- printk(KERN_DEBUG "MModeFbrLen: %04x\n", mmodefbrlen);
-
- printk(KERN_DEBUG "FrameID: %04x\n", tfid);
- printk(KERN_DEBUG "TxStatus: %04x\n", txs);
-
- printk(KERN_DEBUG "MaxNumMpdu: %04x\n", mnmpdu);
- printk(KERN_DEBUG "MaxAggbyte: %04x\n", mabyte);
- printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f);
- printk(KERN_DEBUG "MinByte: %04x\n", mmbyte);
-
- brcmu_format_hex(hexbuf, rtsph, sizeof(txh->RTSPhyHeader));
- printk(KERN_DEBUG "RTS PLCP: %s ", hexbuf);
- brcmu_format_hex(hexbuf, (u8 *) &rts, sizeof(txh->rts_frame));
- printk(KERN_DEBUG "RTS Frame: %s", hexbuf);
- printk(KERN_DEBUG "\n");
-}
-#endif /* defined(BCMDBG) */
-
-#if defined(BCMDBG)
-void wlc_print_rxh(d11rxhdr_t *rxh)
-{
- u16 len = rxh->RxFrameSize;
- u16 phystatus_0 = rxh->PhyRxStatus_0;
- u16 phystatus_1 = rxh->PhyRxStatus_1;
- u16 phystatus_2 = rxh->PhyRxStatus_2;
- u16 phystatus_3 = rxh->PhyRxStatus_3;
- u16 macstatus1 = rxh->RxStatus1;
- u16 macstatus2 = rxh->RxStatus2;
- char flagstr[64];
- char lenbuf[20];
- static const struct brcmu_bit_desc macstat_flags[] = {
- {RXS_FCSERR, "FCSErr"},
- {RXS_RESPFRAMETX, "Reply"},
- {RXS_PBPRES, "PADDING"},
- {RXS_DECATMPT, "DeCr"},
- {RXS_DECERR, "DeCrErr"},
- {RXS_BCNSENT, "Bcn"},
- {0, NULL}
- };
-
- printk(KERN_DEBUG "Raw RxDesc:\n");
- print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh, sizeof(d11rxhdr_t));
-
- brcmu_format_flags(macstat_flags, macstatus1, flagstr, 64);
-
- snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
-
- printk(KERN_DEBUG "RxFrameSize: %6s (%d)%s\n", lenbuf, len,
- (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
- printk(KERN_DEBUG "RxPHYStatus: %04x %04x %04x %04x\n",
- phystatus_0, phystatus_1, phystatus_2, phystatus_3);
- printk(KERN_DEBUG "RxMACStatus: %x %s\n", macstatus1, flagstr);
- printk(KERN_DEBUG "RXMACaggtype: %x\n",
- (macstatus2 & RXS_AGGTYPE_MASK));
- printk(KERN_DEBUG "RxTSFTime: %04x\n", rxh->RxTSFTime);
-}
-#endif /* defined(BCMDBG) */
-
-static u16 wlc_rate_shm_offset(struct wlc_info *wlc, u8 rate)
-{
- return wlc_bmac_rate_shm_offset(wlc->hw, rate);
-}
-
-/* Callback for device removed */
-
-/*
- * Attempts to queue a packet onto a multiple-precedence queue,
- * if necessary evicting a lower precedence packet from the queue.
- *
- * 'prec' is the precedence number that has already been mapped
- * from the packet priority.
- *
- * Returns true if packet consumed (queued), false if not.
- */
-bool
-wlc_prec_enq(struct wlc_info *wlc, struct pktq *q, void *pkt, int prec)
-{
- return wlc_prec_enq_head(wlc, q, pkt, prec, false);
-}
-
-bool
-wlc_prec_enq_head(struct wlc_info *wlc, struct pktq *q, struct sk_buff *pkt,
- int prec, bool head)
-{
- struct sk_buff *p;
- int eprec = -1; /* precedence to evict from */
-
- /* Determine precedence from which to evict packet, if any */
- if (pktq_pfull(q, prec))
- eprec = prec;
- else if (pktq_full(q)) {
- p = brcmu_pktq_peek_tail(q, &eprec);
- if (eprec > prec) {
- wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
- "\n", __func__, eprec, prec);
- return false;
- }
- }
-
- /* Evict if needed */
- if (eprec >= 0) {
- bool discard_oldest;
-
- discard_oldest = AC_BITMAP_TST(wlc->wme_dp, eprec);
-
- /* Refuse newer packet unless configured to discard oldest */
- if (eprec == prec && !discard_oldest) {
- wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
- "\n", __func__, prec);
- return false;
- }
-
- /* Evict packet according to discard policy */
- p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
- brcmu_pktq_pdeq_tail(q, eprec);
- brcmu_pkt_buf_free_skb(p);
- }
-
- /* Enqueue */
- if (head)
- p = brcmu_pktq_penq_head(q, prec, pkt);
- else
- p = brcmu_pktq_penq(q, prec, pkt);
-
- return true;
-}
-
-void wlc_txq_enq(void *ctx, struct scb *scb, struct sk_buff *sdu,
- uint prec)
-{
- struct wlc_info *wlc = (struct wlc_info *) ctx;
- struct wlc_txq_info *qi = wlc->pkt_queue; /* Check me */
- struct pktq *q = &qi->q;
- int prio;
-
- prio = sdu->priority;
-
- if (!wlc_prec_enq(wlc, q, sdu, prec)) {
- if (!EDCF_ENAB(wlc->pub)
- || (wlc->pub->wlfeatureflag & WL_SWFL_FLOWCONTROL))
- wiphy_err(wlc->wiphy, "wl%d: wlc_txq_enq: txq overflow"
- "\n", wlc->pub->unit);
-
- /*
- * XXX we might hit this condtion in case
- * packet flooding from mac80211 stack
- */
- brcmu_pkt_buf_free_skb(sdu);
- }
-
- /* Check if flow control needs to be turned on after enqueuing the packet
- * Don't turn on flow control if EDCF is enabled. Driver would make the decision on what
- * to drop instead of relying on stack to make the right decision
- */
- if (!EDCF_ENAB(wlc->pub)
- || (wlc->pub->wlfeatureflag & WL_SWFL_FLOWCONTROL)) {
- if (pktq_len(q) >= wlc->pub->tunables->datahiwat) {
- wlc_txflowcontrol(wlc, qi, ON, ALLPRIO);
- }
- } else if (wlc->pub->_priofc) {
- if (pktq_plen(q, wlc_prio2prec_map[prio]) >=
- wlc->pub->tunables->datahiwat) {
- wlc_txflowcontrol(wlc, qi, ON, prio);
- }
- }
-}
-
-bool
-wlc_sendpkt_mac80211(struct wlc_info *wlc, struct sk_buff *sdu,
- struct ieee80211_hw *hw)
-{
- u8 prio;
- uint fifo;
- void *pkt;
- struct scb *scb = &global_scb;
- struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data);
-
- /* 802.11 standard requires management traffic to go at highest priority */
- prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority :
- MAXPRIO;
- fifo = prio2fifo[prio];
- pkt = sdu;
- if (unlikely
- (wlc_d11hdrs_mac80211(wlc, hw, pkt, scb, 0, 1, fifo, 0, NULL, 0)))
- return -EINVAL;
- wlc_txq_enq(wlc, scb, pkt, WLC_PRIO_TO_PREC(prio));
- wlc_send_q(wlc);
- return 0;
-}
-
-void wlc_send_q(struct wlc_info *wlc)
-{
- struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
- int prec;
- u16 prec_map;
- int err = 0, i, count;
- uint fifo;
- struct wlc_txq_info *qi = wlc->pkt_queue;
- struct pktq *q = &qi->q;
- struct ieee80211_tx_info *tx_info;
-
- if (in_send_q)
- return;
- else
- in_send_q = true;
-
- prec_map = wlc->tx_prec_map;
-
- /* Send all the enq'd pkts that we can.
- * Dequeue packets with precedence with empty HW fifo only
- */
- while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) {
- tx_info = IEEE80211_SKB_CB(pkt[0]);
- if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
- err = wlc_sendampdu(wlc->ampdu, qi, pkt, prec);
- } else {
- count = 1;
- err = wlc_prep_pdu(wlc, pkt[0], &fifo);
- if (!err) {
- for (i = 0; i < count; i++) {
- wlc_txfifo(wlc, fifo, pkt[i], true, 1);
- }
- }
- }
-
- if (err == -EBUSY) {
- brcmu_pktq_penq_head(q, prec, pkt[0]);
- /* If send failed due to any other reason than a change in
- * HW FIFO condition, quit. Otherwise, read the new prec_map!
- */
- if (prec_map == wlc->tx_prec_map)
- break;
- prec_map = wlc->tx_prec_map;
- }
- }
-
- /* Check if flow control needs to be turned off after sending the packet */
- if (!EDCF_ENAB(wlc->pub)
- || (wlc->pub->wlfeatureflag & WL_SWFL_FLOWCONTROL)) {
- if (wlc_txflowcontrol_prio_isset(wlc, qi, ALLPRIO)
- && (pktq_len(q) < wlc->pub->tunables->datahiwat / 2)) {
- wlc_txflowcontrol(wlc, qi, OFF, ALLPRIO);
- }
- } else if (wlc->pub->_priofc) {
- int prio;
- for (prio = MAXPRIO; prio >= 0; prio--) {
- if (wlc_txflowcontrol_prio_isset(wlc, qi, prio) &&
- (pktq_plen(q, wlc_prio2prec_map[prio]) <
- wlc->pub->tunables->datahiwat / 2)) {
- wlc_txflowcontrol(wlc, qi, OFF, prio);
- }
- }
- }
- in_send_q = false;
-}
-
-/*
- * bcmc_fid_generate:
- * Generate frame ID for a BCMC packet. The frag field is not used
- * for MC frames so is used as part of the sequence number.
- */
-static inline u16
-bcmc_fid_generate(struct wlc_info *wlc, struct wlc_bsscfg *bsscfg,
- d11txh_t *txh)
-{
- u16 frameid;
-
- frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
- TXFID_QUEUE_MASK);
- frameid |=
- (((wlc->
- mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
- TX_BCMC_FIFO;
-
- return frameid;
-}
-
-void
-wlc_txfifo(struct wlc_info *wlc, uint fifo, struct sk_buff *p, bool commit,
- s8 txpktpend)
-{
- u16 frameid = INVALIDFID;
- d11txh_t *txh;
-
- txh = (d11txh_t *) (p->data);
-
- /* When a BC/MC frame is being committed to the BCMC fifo via DMA (NOT PIO), update
- * ucode or BSS info as appropriate.
- */
- if (fifo == TX_BCMC_FIFO) {
- frameid = le16_to_cpu(txh->TxFrameID);
-
- }
-
- if (WLC_WAR16165(wlc))
- wlc_war16165(wlc, true);
-
-
- /* Bump up pending count for if not using rpc. If rpc is used, this will be handled
- * in wlc_bmac_txfifo()
- */
- if (commit) {
- TXPKTPENDINC(wlc, fifo, txpktpend);
- BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n",
- txpktpend, TXPKTPENDGET(wlc, fifo));
- }
-
- /* Commit BCMC sequence number in the SHM frame ID location */
- if (frameid != INVALIDFID)
- BCMCFID(wlc, frameid);
-
- if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0) {
- wiphy_err(wlc->wiphy, "wlc_txfifo: fatal, toss frames !!!\n");
- }
-}
-
-void
-wlc_compute_plcp(struct wlc_info *wlc, ratespec_t rspec, uint length, u8 *plcp)
-{
- if (IS_MCS(rspec)) {
- wlc_compute_mimo_plcp(rspec, length, plcp);
- } else if (IS_OFDM(rspec)) {
- wlc_compute_ofdm_plcp(rspec, length, plcp);
- } else {
- wlc_compute_cck_plcp(wlc, rspec, length, plcp);
- }
- return;
-}
-
-/* Rate: 802.11 rate code, length: PSDU length in octets */
-static void wlc_compute_mimo_plcp(ratespec_t rspec, uint length, u8 *plcp)
-{
- u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
- plcp[0] = mcs;
- if (RSPEC_IS40MHZ(rspec) || (mcs == 32))
- plcp[0] |= MIMO_PLCP_40MHZ;
- WLC_SET_MIMO_PLCP_LEN(plcp, length);
- plcp[3] = RSPEC_MIMOPLCP3(rspec); /* rspec already holds this byte */
- plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
- plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
- plcp[5] = 0;
-}
-
-/* Rate: 802.11 rate code, length: PSDU length in octets */
-static void
-wlc_compute_ofdm_plcp(ratespec_t rspec, u32 length, u8 *plcp)
-{
- u8 rate_signal;
- u32 tmp = 0;
- int rate = RSPEC2RATE(rspec);
-
- /* encode rate per 802.11a-1999 sec 17.3.4.1, with lsb transmitted first */
- rate_signal = rate_info[rate] & WLC_RATE_MASK;
- memset(plcp, 0, D11_PHY_HDR_LEN);
- D11A_PHY_HDR_SRATE((ofdm_phy_hdr_t *) plcp, rate_signal);
-
- tmp = (length & 0xfff) << 5;
- plcp[2] |= (tmp >> 16) & 0xff;
- plcp[1] |= (tmp >> 8) & 0xff;
- plcp[0] |= tmp & 0xff;
-
- return;
-}
-
-/*
- * Compute PLCP, but only requires actual rate and length of pkt.
- * Rate is given in the driver standard multiple of 500 kbps.
- * le is set for 11 Mbps rate if necessary.
- * Broken out for PRQ.
- */
-
-static void wlc_cck_plcp_set(struct wlc_info *wlc, int rate_500, uint length,
- u8 *plcp)
-{
- u16 usec = 0;
- u8 le = 0;
-
- switch (rate_500) {
- case WLC_RATE_1M:
- usec = length << 3;
- break;
- case WLC_RATE_2M:
- usec = length << 2;
- break;
- case WLC_RATE_5M5:
- usec = (length << 4) / 11;
- if ((length << 4) - (usec * 11) > 0)
- usec++;
- break;
- case WLC_RATE_11M:
- usec = (length << 3) / 11;
- if ((length << 3) - (usec * 11) > 0) {
- usec++;
- if ((usec * 11) - (length << 3) >= 8)
- le = D11B_PLCP_SIGNAL_LE;
- }
- break;
-
- default:
- wiphy_err(wlc->wiphy, "wlc_cck_plcp_set: unsupported rate %d"
- "\n", rate_500);
- rate_500 = WLC_RATE_1M;
- usec = length << 3;
- break;
- }
- /* PLCP signal byte */
- plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
- /* PLCP service byte */
- plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
- /* PLCP length u16, little endian */
- plcp[2] = usec & 0xff;
- plcp[3] = (usec >> 8) & 0xff;
- /* PLCP CRC16 */
- plcp[4] = 0;
- plcp[5] = 0;
-}
-
-/* Rate: 802.11 rate code, length: PSDU length in octets */
-static void wlc_compute_cck_plcp(struct wlc_info *wlc, ratespec_t rspec,
- uint length, u8 *plcp)
-{
- int rate = RSPEC2RATE(rspec);
-
- wlc_cck_plcp_set(wlc, rate, length, plcp);
-}
-
-/* wlc_compute_frame_dur()
- *
- * Calculate the 802.11 MAC header DUR field for MPDU
- * DUR for a single frame = 1 SIFS + 1 ACK
- * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
- *
- * rate MPDU rate in unit of 500kbps
- * next_frag_len next MPDU length in bytes
- * preamble_type use short/GF or long/MM PLCP header
- */
-static u16
-wlc_compute_frame_dur(struct wlc_info *wlc, ratespec_t rate, u8 preamble_type,
- uint next_frag_len)
-{
- u16 dur, sifs;
-
- sifs = SIFS(wlc->band);
-
- dur = sifs;
- dur += (u16) wlc_calc_ack_time(wlc, rate, preamble_type);
-
- if (next_frag_len) {
- /* Double the current DUR to get 2 SIFS + 2 ACKs */
- dur *= 2;
- /* add another SIFS and the frag time */
- dur += sifs;
- dur +=
- (u16) wlc_calc_frame_time(wlc, rate, preamble_type,
- next_frag_len);
- }
- return dur;
-}
-
-/* wlc_compute_rtscts_dur()
- *
- * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
- * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
- * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
- *
- * cts cts-to-self or rts/cts
- * rts_rate rts or cts rate in unit of 500kbps
- * rate next MPDU rate in unit of 500kbps
- * frame_len next MPDU frame length in bytes
- */
-u16
-wlc_compute_rtscts_dur(struct wlc_info *wlc, bool cts_only, ratespec_t rts_rate,
- ratespec_t frame_rate, u8 rts_preamble_type,
- u8 frame_preamble_type, uint frame_len, bool ba)
-{
- u16 dur, sifs;
-
- sifs = SIFS(wlc->band);
-
- if (!cts_only) { /* RTS/CTS */
- dur = 3 * sifs;
- dur +=
- (u16) wlc_calc_cts_time(wlc, rts_rate,
- rts_preamble_type);
- } else { /* CTS-TO-SELF */
- dur = 2 * sifs;
- }
-
- dur +=
- (u16) wlc_calc_frame_time(wlc, frame_rate, frame_preamble_type,
- frame_len);
- if (ba)
- dur +=
- (u16) wlc_calc_ba_time(wlc, frame_rate,
- WLC_SHORT_PREAMBLE);
- else
- dur +=
- (u16) wlc_calc_ack_time(wlc, frame_rate,
- frame_preamble_type);
- return dur;
-}
-
-u16 wlc_phytxctl1_calc(struct wlc_info *wlc, ratespec_t rspec)
-{
- u16 phyctl1 = 0;
- u16 bw;
-
- if (WLCISLCNPHY(wlc->band)) {
- bw = PHY_TXC1_BW_20MHZ;
- } else {
- bw = RSPEC_GET_BW(rspec);
- /* 10Mhz is not supported yet */
- if (bw < PHY_TXC1_BW_20MHZ) {
- wiphy_err(wlc->wiphy, "wlc_phytxctl1_calc: bw %d is "
- "not supported yet, set to 20L\n", bw);
- bw = PHY_TXC1_BW_20MHZ;
- }
- }
-
- if (IS_MCS(rspec)) {
- uint mcs = rspec & RSPEC_RATE_MASK;
-
- /* bw, stf, coding-type is part of RSPEC_PHYTXBYTE2 returns */
- phyctl1 = RSPEC_PHYTXBYTE2(rspec);
- /* set the upper byte of phyctl1 */
- phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
- } else if (IS_CCK(rspec) && !WLCISLCNPHY(wlc->band)
- && !WLCISSSLPNPHY(wlc->band)) {
- /* In CCK mode LPPHY overloads OFDM Modulation bits with CCK Data Rate */
- /* Eventually MIMOPHY would also be converted to this format */
- /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
- phyctl1 = (bw | (RSPEC_STF(rspec) << PHY_TXC1_MODE_SHIFT));
- } else { /* legacy OFDM/CCK */
- s16 phycfg;
- /* get the phyctl byte from rate phycfg table */
- phycfg = wlc_rate_legacy_phyctl(RSPEC2RATE(rspec));
- if (phycfg == -1) {
- wiphy_err(wlc->wiphy, "wlc_phytxctl1_calc: wrong "
- "legacy OFDM/CCK rate\n");
- phycfg = 0;
- }
- /* set the upper byte of phyctl1 */
- phyctl1 =
- (bw | (phycfg << 8) |
- (RSPEC_STF(rspec) << PHY_TXC1_MODE_SHIFT));
- }
- return phyctl1;
-}
-
-ratespec_t
-wlc_rspec_to_rts_rspec(struct wlc_info *wlc, ratespec_t rspec, bool use_rspec,
- u16 mimo_ctlchbw)
-{
- ratespec_t rts_rspec = 0;
-
- if (use_rspec) {
- /* use frame rate as rts rate */
- rts_rspec = rspec;
-
- } else if (wlc->band->gmode && wlc->protection->_g && !IS_CCK(rspec)) {
- /* Use 11Mbps as the g protection RTS target rate and fallback.
- * Use the WLC_BASIC_RATE() lookup to find the best basic rate under the
- * target in case 11 Mbps is not Basic.
- * 6 and 9 Mbps are not usually selected by rate selection, but even
- * if the OFDM rate we are protecting is 6 or 9 Mbps, 11 is more robust.
- */
- rts_rspec = WLC_BASIC_RATE(wlc, WLC_RATE_11M);
- } else {
- /* calculate RTS rate and fallback rate based on the frame rate
- * RTS must be sent at a basic rate since it is a
- * control frame, sec 9.6 of 802.11 spec
- */
- rts_rspec = WLC_BASIC_RATE(wlc, rspec);
- }
-
- if (WLC_PHY_11N_CAP(wlc->band)) {
- /* set rts txbw to correct side band */
- rts_rspec &= ~RSPEC_BW_MASK;
-
- /* if rspec/rspec_fallback is 40MHz, then send RTS on both 20MHz channel
- * (DUP), otherwise send RTS on control channel
- */
- if (RSPEC_IS40MHZ(rspec) && !IS_CCK(rts_rspec))
- rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
- else
- rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
-
- /* pick siso/cdd as default for ofdm */
- if (IS_OFDM(rts_rspec)) {
- rts_rspec &= ~RSPEC_STF_MASK;
- rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
- }
- }
- return rts_rspec;
-}
-
-/*
- * Add d11txh_t, cck_phy_hdr_t.
- *
- * 'p' data must start with 802.11 MAC header
- * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
- *
- * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
- *
- */
-static u16
-wlc_d11hdrs_mac80211(struct wlc_info *wlc, struct ieee80211_hw *hw,
- struct sk_buff *p, struct scb *scb, uint frag,
- uint nfrags, uint queue, uint next_frag_len,
- wsec_key_t *key, ratespec_t rspec_override)
-{
- struct ieee80211_hdr *h;
- d11txh_t *txh;
- u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
- int len, phylen, rts_phylen;
- u16 mch, phyctl, xfts, mainrates;
- u16 seq = 0, mcl = 0, status = 0, frameid = 0;
- ratespec_t rspec[2] = { WLC_RATE_1M, WLC_RATE_1M }, rts_rspec[2] = {
- WLC_RATE_1M, WLC_RATE_1M};
- bool use_rts = false;
- bool use_cts = false;
- bool use_rifs = false;
- bool short_preamble[2] = { false, false };
- u8 preamble_type[2] = { WLC_LONG_PREAMBLE, WLC_LONG_PREAMBLE };
- u8 rts_preamble_type[2] = { WLC_LONG_PREAMBLE, WLC_LONG_PREAMBLE };
- u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
- struct ieee80211_rts *rts = NULL;
- bool qos;
- uint ac;
- u32 rate_val[2];
- bool hwtkmic = false;
- u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
-#define ANTCFG_NONE 0xFF
- u8 antcfg = ANTCFG_NONE;
- u8 fbantcfg = ANTCFG_NONE;
- uint phyctl1_stf = 0;
- u16 durid = 0;
- struct ieee80211_tx_rate *txrate[2];
- int k;
- struct ieee80211_tx_info *tx_info;
- bool is_mcs[2];
- u16 mimo_txbw;
- u8 mimo_preamble_type;
-
- /* locate 802.11 MAC header */
- h = (struct ieee80211_hdr *)(p->data);
- qos = ieee80211_is_data_qos(h->frame_control);
-
- /* compute length of frame in bytes for use in PLCP computations */
- len = brcmu_pkttotlen(p);
- phylen = len + FCS_LEN;
-
- /* If WEP enabled, add room in phylen for the additional bytes of
- * ICV which MAC generates. We do NOT add the additional bytes to
- * the packet itself, thus phylen = packet length + ICV_LEN + FCS_LEN
- * in this case
- */
- if (key) {
- phylen += key->icv_len;
- }
-
- /* Get tx_info */
- tx_info = IEEE80211_SKB_CB(p);
-
- /* add PLCP */
- plcp = skb_push(p, D11_PHY_HDR_LEN);
-
- /* add Broadcom tx descriptor header */
- txh = (d11txh_t *) skb_push(p, D11_TXH_LEN);
- memset(txh, 0, D11_TXH_LEN);
-
- /* setup frameid */
- if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
- /* non-AP STA should never use BCMC queue */
- if (queue == TX_BCMC_FIFO) {
- wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
- "TX_BCMC!\n", WLCWLUNIT(wlc), __func__);
- frameid = bcmc_fid_generate(wlc, NULL, txh);
- } else {
- /* Increment the counter for first fragment */
- if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
- SCB_SEQNUM(scb, p->priority)++;
- }
-
- /* extract fragment number from frame first */
- seq = le16_to_cpu(seq) & FRAGNUM_MASK;
- seq |= (SCB_SEQNUM(scb, p->priority) << SEQNUM_SHIFT);
- h->seq_ctrl = cpu_to_le16(seq);
-
- frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
- (queue & TXFID_QUEUE_MASK);
- }
- }
- frameid |= queue & TXFID_QUEUE_MASK;
-
- /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
- if (SCB_PS(scb) || ieee80211_is_beacon(h->frame_control))
- mcl |= TXC_IGNOREPMQ;
-
- txrate[0] = tx_info->control.rates;
- txrate[1] = txrate[0] + 1;
-
- /* if rate control algorithm didn't give us a fallback rate, use the primary rate */
- if (txrate[1]->idx < 0) {
- txrate[1] = txrate[0];
- }
-
- for (k = 0; k < hw->max_rates; k++) {
- is_mcs[k] =
- txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
- if (!is_mcs[k]) {
- if ((txrate[k]->idx >= 0)
- && (txrate[k]->idx <
- hw->wiphy->bands[tx_info->band]->n_bitrates)) {
- rate_val[k] =
- hw->wiphy->bands[tx_info->band]->
- bitrates[txrate[k]->idx].hw_value;
- short_preamble[k] =
- txrate[k]->
- flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
- true : false;
- } else {
- rate_val[k] = WLC_RATE_1M;
- }
- } else {
- rate_val[k] = txrate[k]->idx;
- }
- /* Currently only support same setting for primay and fallback rates.
- * Unify flags for each rate into a single value for the frame
- */
- use_rts |=
- txrate[k]->
- flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
- use_cts |=
- txrate[k]->
- flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
-
- if (is_mcs[k])
- rate_val[k] |= NRATE_MCS_INUSE;
-
- rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band, rate_val[k]);
-
- /* (1) RATE: determine and validate primary rate and fallback rates */
- if (!RSPEC_ACTIVE(rspec[k])) {
- rspec[k] = WLC_RATE_1M;
- } else {
- if (!is_multicast_ether_addr(h->addr1)) {
- /* set tx antenna config */
- wlc_antsel_antcfg_get(wlc->asi, false, false, 0,
- 0, &antcfg, &fbantcfg);
- }
- }
- }
-
- phyctl1_stf = wlc->stf->ss_opmode;
-
- if (N_ENAB(wlc->pub)) {
- for (k = 0; k < hw->max_rates; k++) {
- /* apply siso/cdd to single stream mcs's or ofdm if rspec is auto selected */
- if (((IS_MCS(rspec[k]) &&
- IS_SINGLE_STREAM(rspec[k] & RSPEC_RATE_MASK)) ||
- IS_OFDM(rspec[k]))
- && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
- || !(rspec[k] & RSPEC_OVERRIDE))) {
- rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
-
- /* For SISO MCS use STBC if possible */
- if (IS_MCS(rspec[k])
- && WLC_STF_SS_STBC_TX(wlc, scb)) {
- u8 stc;
-
- stc = 1; /* Nss for single stream is always 1 */
- rspec[k] |=
- (PHY_TXC1_MODE_STBC <<
- RSPEC_STF_SHIFT) | (stc <<
- RSPEC_STC_SHIFT);
- } else
- rspec[k] |=
- (phyctl1_stf << RSPEC_STF_SHIFT);
- }
-
- /* Is the phy configured to use 40MHZ frames? If so then pick the desired txbw */
- if (CHSPEC_WLC_BW(wlc->chanspec) == WLC_40_MHZ) {
- /* default txbw is 20in40 SB */
- mimo_ctlchbw = mimo_txbw =
- CHSPEC_SB_UPPER(WLC_BAND_PI_RADIO_CHANSPEC)
- ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
-
- if (IS_MCS(rspec[k])) {
- /* mcs 32 must be 40b/w DUP */
- if ((rspec[k] & RSPEC_RATE_MASK) == 32) {
- mimo_txbw =
- PHY_TXC1_BW_40MHZ_DUP;
- /* use override */
- } else if (wlc->mimo_40txbw != AUTO)
- mimo_txbw = wlc->mimo_40txbw;
- /* else check if dst is using 40 Mhz */
- else if (scb->flags & SCB_IS40)
- mimo_txbw = PHY_TXC1_BW_40MHZ;
- } else if (IS_OFDM(rspec[k])) {
- if (wlc->ofdm_40txbw != AUTO)
- mimo_txbw = wlc->ofdm_40txbw;
- } else {
- if (wlc->cck_40txbw != AUTO)
- mimo_txbw = wlc->cck_40txbw;
- }
- } else {
- /* mcs32 is 40 b/w only.
- * This is possible for probe packets on a STA during SCAN
- */
- if ((rspec[k] & RSPEC_RATE_MASK) == 32) {
- /* mcs 0 */
- rspec[k] = RSPEC_MIMORATE;
- }
- mimo_txbw = PHY_TXC1_BW_20MHZ;
- }
-
- /* Set channel width */
- rspec[k] &= ~RSPEC_BW_MASK;
- if ((k == 0) || ((k > 0) && IS_MCS(rspec[k])))
- rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
- else
- rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
-
- /* Set Short GI */
-#ifdef NOSGIYET
- if (IS_MCS(rspec[k])
- && (txrate[k]->flags & IEEE80211_TX_RC_SHORT_GI))
- rspec[k] |= RSPEC_SHORT_GI;
- else if (!(txrate[k]->flags & IEEE80211_TX_RC_SHORT_GI))
- rspec[k] &= ~RSPEC_SHORT_GI;
-#else
- rspec[k] &= ~RSPEC_SHORT_GI;
-#endif
-
- mimo_preamble_type = WLC_MM_PREAMBLE;
- if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
- mimo_preamble_type = WLC_GF_PREAMBLE;
-
- if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
- && (!IS_MCS(rspec[k]))) {
- wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
- "RC_MCS != IS_MCS(rspec)\n",
- WLCWLUNIT(wlc), __func__);
- }
-
- if (IS_MCS(rspec[k])) {
- preamble_type[k] = mimo_preamble_type;
-
- /* if SGI is selected, then forced mm for single stream */
- if ((rspec[k] & RSPEC_SHORT_GI)
- && IS_SINGLE_STREAM(rspec[k] &
- RSPEC_RATE_MASK)) {
- preamble_type[k] = WLC_MM_PREAMBLE;
- }
- }
-
- /* should be better conditionalized */
- if (!IS_MCS(rspec[0])
- && (tx_info->control.rates[0].
- flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
- preamble_type[k] = WLC_SHORT_PREAMBLE;
- }
- } else {
- for (k = 0; k < hw->max_rates; k++) {
- /* Set ctrlchbw as 20Mhz */
- rspec[k] &= ~RSPEC_BW_MASK;
- rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
-
- /* for nphy, stf of ofdm frames must follow policies */
- if (WLCISNPHY(wlc->band) && IS_OFDM(rspec[k])) {
- rspec[k] &= ~RSPEC_STF_MASK;
- rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
- }
- }
- }
-
- /* Reset these for use with AMPDU's */
- txrate[0]->count = 0;
- txrate[1]->count = 0;
-
- /* (2) PROTECTION, may change rspec */
- if ((ieee80211_is_data(h->frame_control) ||
- ieee80211_is_mgmt(h->frame_control)) &&
- (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
- use_rts = true;
-
- /* (3) PLCP: determine PLCP header and MAC duration, fill d11txh_t */
- wlc_compute_plcp(wlc, rspec[0], phylen, plcp);
- wlc_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
- memcpy(&txh->FragPLCPFallback,
- plcp_fallback, sizeof(txh->FragPLCPFallback));
-
- /* Length field now put in CCK FBR CRC field */
- if (IS_CCK(rspec[1])) {
- txh->FragPLCPFallback[4] = phylen & 0xff;
- txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
- }
-
- /* MIMO-RATE: need validation ?? */
- mainrates =
- IS_OFDM(rspec[0]) ? D11A_PHY_HDR_GRATE((ofdm_phy_hdr_t *) plcp) :
- plcp[0];
-
- /* DUR field for main rate */
- if (!ieee80211_is_pspoll(h->frame_control) &&
- !is_multicast_ether_addr(h->addr1) && !use_rifs) {
- durid =
- wlc_compute_frame_dur(wlc, rspec[0], preamble_type[0],
- next_frag_len);
- h->duration_id = cpu_to_le16(durid);
- } else if (use_rifs) {
- /* NAV protect to end of next max packet size */
- durid =
- (u16) wlc_calc_frame_time(wlc, rspec[0],
- preamble_type[0],
- DOT11_MAX_FRAG_LEN);
- durid += RIFS_11N_TIME;
- h->duration_id = cpu_to_le16(durid);
- }
-
- /* DUR field for fallback rate */
- if (ieee80211_is_pspoll(h->frame_control))
- txh->FragDurFallback = h->duration_id;
- else if (is_multicast_ether_addr(h->addr1) || use_rifs)
- txh->FragDurFallback = 0;
- else {
- durid = wlc_compute_frame_dur(wlc, rspec[1],
- preamble_type[1], next_frag_len);
- txh->FragDurFallback = cpu_to_le16(durid);
- }
-
- /* (4) MAC-HDR: MacTxControlLow */
- if (frag == 0)
- mcl |= TXC_STARTMSDU;
-
- if (!is_multicast_ether_addr(h->addr1))
- mcl |= TXC_IMMEDACK;
-
- if (BAND_5G(wlc->band->bandtype))
- mcl |= TXC_FREQBAND_5G;
-
- if (CHSPEC_IS40(WLC_BAND_PI_RADIO_CHANSPEC))
- mcl |= TXC_BW_40;
-
- /* set AMIC bit if using hardware TKIP MIC */
- if (hwtkmic)
- mcl |= TXC_AMIC;
-
- txh->MacTxControlLow = cpu_to_le16(mcl);
-
- /* MacTxControlHigh */
- mch = 0;
-
- /* Set fallback rate preamble type */
- if ((preamble_type[1] == WLC_SHORT_PREAMBLE) ||
- (preamble_type[1] == WLC_GF_PREAMBLE)) {
- if (RSPEC2RATE(rspec[1]) != WLC_RATE_1M)
- mch |= TXC_PREAMBLE_DATA_FB_SHORT;
- }
-
- /* MacFrameControl */
- memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
- txh->TxFesTimeNormal = cpu_to_le16(0);
-
- txh->TxFesTimeFallback = cpu_to_le16(0);
-
- /* TxFrameRA */
- memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
-
- /* TxFrameID */
- txh->TxFrameID = cpu_to_le16(frameid);
-
- /* TxStatus, Note the case of recreating the first frag of a suppressed frame
- * then we may need to reset the retry cnt's via the status reg
- */
- txh->TxStatus = cpu_to_le16(status);
-
- /* extra fields for ucode AMPDU aggregation, the new fields are added to
- * the END of previous structure so that it's compatible in driver.
- */
- txh->MaxNMpdus = cpu_to_le16(0);
- txh->MaxABytes_MRT = cpu_to_le16(0);
- txh->MaxABytes_FBR = cpu_to_le16(0);
- txh->MinMBytes = cpu_to_le16(0);
-
- /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration, furnish d11txh_t */
- /* RTS PLCP header and RTS frame */
- if (use_rts || use_cts) {
- if (use_rts && use_cts)
- use_cts = false;
-
- for (k = 0; k < 2; k++) {
- rts_rspec[k] = wlc_rspec_to_rts_rspec(wlc, rspec[k],
- false,
- mimo_ctlchbw);
- }
-
- if (!IS_OFDM(rts_rspec[0]) &&
- !((RSPEC2RATE(rts_rspec[0]) == WLC_RATE_1M) ||
- (wlc->PLCPHdr_override == WLC_PLCP_LONG))) {
- rts_preamble_type[0] = WLC_SHORT_PREAMBLE;
- mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
- }
-
- if (!IS_OFDM(rts_rspec[1]) &&
- !((RSPEC2RATE(rts_rspec[1]) == WLC_RATE_1M) ||
- (wlc->PLCPHdr_override == WLC_PLCP_LONG))) {
- rts_preamble_type[1] = WLC_SHORT_PREAMBLE;
- mch |= TXC_PREAMBLE_RTS_FB_SHORT;
- }
-
- /* RTS/CTS additions to MacTxControlLow */
- if (use_cts) {
- txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
- } else {
- txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
- txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
- }
-
- /* RTS PLCP header */
- rts_plcp = txh->RTSPhyHeader;
- if (use_cts)
- rts_phylen = DOT11_CTS_LEN + FCS_LEN;
- else
- rts_phylen = DOT11_RTS_LEN + FCS_LEN;
-
- wlc_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
-
- /* fallback rate version of RTS PLCP header */
- wlc_compute_plcp(wlc, rts_rspec[1], rts_phylen,
- rts_plcp_fallback);
- memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
- sizeof(txh->RTSPLCPFallback));
-
- /* RTS frame fields... */
- rts = (struct ieee80211_rts *)&txh->rts_frame;
-
- durid = wlc_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
- rspec[0], rts_preamble_type[0],
- preamble_type[0], phylen, false);
- rts->duration = cpu_to_le16(durid);
- /* fallback rate version of RTS DUR field */
- durid = wlc_compute_rtscts_dur(wlc, use_cts,
- rts_rspec[1], rspec[1],
- rts_preamble_type[1],
- preamble_type[1], phylen, false);
- txh->RTSDurFallback = cpu_to_le16(durid);
-
- if (use_cts) {
- rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
- IEEE80211_STYPE_CTS);
-
- memcpy(&rts->ra, &h->addr2, ETH_ALEN);
- } else {
- rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
- IEEE80211_STYPE_RTS);
-
- memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
- }
-
- /* mainrate
- * low 8 bits: main frag rate/mcs,
- * high 8 bits: rts/cts rate/mcs
- */
- mainrates |= (IS_OFDM(rts_rspec[0]) ?
- D11A_PHY_HDR_GRATE((ofdm_phy_hdr_t *) rts_plcp) :
- rts_plcp[0]) << 8;
- } else {
- memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
- memset((char *)&txh->rts_frame, 0,
- sizeof(struct ieee80211_rts));
- memset((char *)txh->RTSPLCPFallback, 0,
- sizeof(txh->RTSPLCPFallback));
- txh->RTSDurFallback = 0;
- }
-
-#ifdef SUPPORT_40MHZ
- /* add null delimiter count */
- if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && IS_MCS(rspec)) {
- txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
- wlc_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
- }
-#endif
-
- /* Now that RTS/RTS FB preamble types are updated, write the final value */
- txh->MacTxControlHigh = cpu_to_le16(mch);
-
- /* MainRates (both the rts and frag plcp rates have been calculated now) */
- txh->MainRates = cpu_to_le16(mainrates);
-
- /* XtraFrameTypes */
- xfts = FRAMETYPE(rspec[1], wlc->mimoft);
- xfts |= (FRAMETYPE(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
- xfts |= (FRAMETYPE(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
- xfts |=
- CHSPEC_CHANNEL(WLC_BAND_PI_RADIO_CHANSPEC) << XFTS_CHANNEL_SHIFT;
- txh->XtraFrameTypes = cpu_to_le16(xfts);
-
- /* PhyTxControlWord */
- phyctl = FRAMETYPE(rspec[0], wlc->mimoft);
- if ((preamble_type[0] == WLC_SHORT_PREAMBLE) ||
- (preamble_type[0] == WLC_GF_PREAMBLE)) {
- if (RSPEC2RATE(rspec[0]) != WLC_RATE_1M)
- phyctl |= PHY_TXC_SHORT_HDR;
- }
-
- /* phytxant is properly bit shifted */
- phyctl |= wlc_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
- txh->PhyTxControlWord = cpu_to_le16(phyctl);
-
- /* PhyTxControlWord_1 */
- if (WLC_PHY_11N_CAP(wlc->band)) {
- u16 phyctl1 = 0;
-
- phyctl1 = wlc_phytxctl1_calc(wlc, rspec[0]);
- txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
- phyctl1 = wlc_phytxctl1_calc(wlc, rspec[1]);
- txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
-
- if (use_rts || use_cts) {
- phyctl1 = wlc_phytxctl1_calc(wlc, rts_rspec[0]);
- txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
- phyctl1 = wlc_phytxctl1_calc(wlc, rts_rspec[1]);
- txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
- }
-
- /*
- * For mcs frames, if mixedmode(overloaded with long preamble) is going to be set,
- * fill in non-zero MModeLen and/or MModeFbrLen
- * it will be unnecessary if they are separated
- */
- if (IS_MCS(rspec[0]) && (preamble_type[0] == WLC_MM_PREAMBLE)) {
- u16 mmodelen =
- wlc_calc_lsig_len(wlc, rspec[0], phylen);
- txh->MModeLen = cpu_to_le16(mmodelen);
- }
-
- if (IS_MCS(rspec[1]) && (preamble_type[1] == WLC_MM_PREAMBLE)) {
- u16 mmodefbrlen =
- wlc_calc_lsig_len(wlc, rspec[1], phylen);
- txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
- }
- }
-
- ac = skb_get_queue_mapping(p);
- if (SCB_WME(scb) && qos && wlc->edcf_txop[ac]) {
- uint frag_dur, dur, dur_fallback;
-
- /* WME: Update TXOP threshold */
- if ((!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) && (frag == 0)) {
- frag_dur =
- wlc_calc_frame_time(wlc, rspec[0], preamble_type[0],
- phylen);
-
- if (rts) {
- /* 1 RTS or CTS-to-self frame */
- dur =
- wlc_calc_cts_time(wlc, rts_rspec[0],
- rts_preamble_type[0]);
- dur_fallback =
- wlc_calc_cts_time(wlc, rts_rspec[1],
- rts_preamble_type[1]);
- /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
- dur += le16_to_cpu(rts->duration);
- dur_fallback +=
- le16_to_cpu(txh->RTSDurFallback);
- } else if (use_rifs) {
- dur = frag_dur;
- dur_fallback = 0;
- } else {
- /* frame + SIFS + ACK */
- dur = frag_dur;
- dur +=
- wlc_compute_frame_dur(wlc, rspec[0],
- preamble_type[0], 0);
-
- dur_fallback =
- wlc_calc_frame_time(wlc, rspec[1],
- preamble_type[1],
- phylen);
- dur_fallback +=
- wlc_compute_frame_dur(wlc, rspec[1],
- preamble_type[1], 0);
- }
- /* NEED to set TxFesTimeNormal (hard) */
- txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
- /* NEED to set fallback rate version of TxFesTimeNormal (hard) */
- txh->TxFesTimeFallback =
- cpu_to_le16((u16) dur_fallback);
-
- /* update txop byte threshold (txop minus intraframe overhead) */
- if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
- {
- uint newfragthresh;
-
- newfragthresh =
- wlc_calc_frame_len(wlc, rspec[0],
- preamble_type[0],
- (wlc->
- edcf_txop[ac] -
- (dur -
- frag_dur)));
- /* range bound the fragthreshold */
- if (newfragthresh < DOT11_MIN_FRAG_LEN)
- newfragthresh =
- DOT11_MIN_FRAG_LEN;
- else if (newfragthresh >
- wlc->usr_fragthresh)
- newfragthresh =
- wlc->usr_fragthresh;
- /* update the fragthresh and do txc update */
- if (wlc->fragthresh[queue] !=
- (u16) newfragthresh) {
- wlc->fragthresh[queue] =
- (u16) newfragthresh;
- }
- }
- } else
- wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
- "for rate %d\n",
- wlc->pub->unit, fifo_names[queue],
- RSPEC2RATE(rspec[0]));
-
- if (dur > wlc->edcf_txop[ac])
- wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
- "exceeded phylen %d/%d dur %d/%d\n",
- wlc->pub->unit, __func__,
- fifo_names[queue],
- phylen, wlc->fragthresh[queue],
- dur, wlc->edcf_txop[ac]);
- }
- }
-
- return 0;
-}
-
-void wlc_tbtt(struct wlc_info *wlc, d11regs_t *regs)
-{
- struct wlc_bsscfg *cfg = wlc->cfg;
-
- if (!cfg->BSS) {
- /* DirFrmQ is now valid...defer setting until end of ATIM window */
- wlc->qvalid |= MCMD_DIRFRMQVAL;
- }
-}
-
-static void wlc_war16165(struct wlc_info *wlc, bool tx)
-{
- if (tx) {
- /* the post-increment is used in STAY_AWAKE macro */
- if (wlc->txpend16165war++ == 0)
- wlc_set_ps_ctrl(wlc);
- } else {
- wlc->txpend16165war--;
- if (wlc->txpend16165war == 0)
- wlc_set_ps_ctrl(wlc);
- }
-}
-
-/* process an individual tx_status_t */
-/* WLC_HIGH_API */
-bool
-wlc_dotxstatus(struct wlc_info *wlc, tx_status_t *txs, u32 frm_tx2)
-{
- struct sk_buff *p;
- uint queue;
- d11txh_t *txh;
- struct scb *scb = NULL;
- bool free_pdu;
- int tx_rts, tx_frame_count, tx_rts_count;
- uint totlen, supr_status;
- bool lastframe;
- struct ieee80211_hdr *h;
- u16 mcl;
- struct ieee80211_tx_info *tx_info;
- struct ieee80211_tx_rate *txrate;
- int i;
-
- (void)(frm_tx2); /* Compiler reference to avoid unused variable warning */
-
- /* discard intermediate indications for ucode with one legitimate case:
- * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
- * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
- * transmission count)
- */
- if (!(txs->status & TX_STATUS_AMPDU)
- && (txs->status & TX_STATUS_INTERMEDIATE)) {
- wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
- __func__);
- return false;
- }
-
- queue = txs->frameid & TXFID_QUEUE_MASK;
- if (queue >= NFIFO) {
- p = NULL;
- goto fatal;
- }
-
- p = GETNEXTTXP(wlc, queue);
- if (WLC_WAR16165(wlc))
- wlc_war16165(wlc, false);
- if (p == NULL)
- goto fatal;
-
- txh = (d11txh_t *) (p->data);
- mcl = le16_to_cpu(txh->MacTxControlLow);
-
- if (txs->phyerr) {
- if (WL_ERROR_ON()) {
- wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
- txs->phyerr, txh->MainRates);
- wlc_print_txdesc(txh);
- }
- wlc_print_txstatus(txs);
- }
-
- if (txs->frameid != cpu_to_le16(txh->TxFrameID))
- goto fatal;
- tx_info = IEEE80211_SKB_CB(p);
- h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
-
- if (tx_info->control.sta)
- scb = (struct scb *)tx_info->control.sta->drv_priv;
-
- if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
- wlc_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
- return false;
- }
-
- supr_status = txs->status & TX_STATUS_SUPR_MASK;
- if (supr_status == TX_STATUS_SUPR_BADCH)
- BCMMSG(wlc->wiphy,
- "%s: Pkt tx suppressed, possibly channel %d\n",
- __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
-
- tx_rts = cpu_to_le16(txh->MacTxControlLow) & TXC_SENDRTS;
- tx_frame_count =
- (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
- tx_rts_count =
- (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
-
- lastframe = !ieee80211_has_morefrags(h->frame_control);
-
- if (!lastframe) {
- wiphy_err(wlc->wiphy, "Not last frame!\n");
- } else {
- u16 sfbl, lfbl;
- ieee80211_tx_info_clear_status(tx_info);
- if (queue < AC_COUNT) {
- sfbl = WLC_WME_RETRY_SFB_GET(wlc, wme_fifo2ac[queue]);
- lfbl = WLC_WME_RETRY_LFB_GET(wlc, wme_fifo2ac[queue]);
- } else {
- sfbl = wlc->SFBL;
- lfbl = wlc->LFBL;
- }
-
- txrate = tx_info->status.rates;
- /* FIXME: this should use a combination of sfbl, lfbl depending on frame length and RTS setting */
- if ((tx_frame_count > sfbl) && (txrate[1].idx >= 0)) {
- /* rate selection requested a fallback rate and we used it */
- txrate->count = lfbl;
- txrate[1].count = tx_frame_count - lfbl;
- } else {
- /* rate selection did not request fallback rate, or we didn't need it */
- txrate->count = tx_frame_count;
- /* rc80211_minstrel.c:minstrel_tx_status() expects unused rates to be marked with idx = -1 */
- txrate[1].idx = -1;
- txrate[1].count = 0;
- }
-
- /* clear the rest of the rates */
- for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
- txrate[i].idx = -1;
- txrate[i].count = 0;
- }
-
- if (txs->status & TX_STATUS_ACK_RCV)
- tx_info->flags |= IEEE80211_TX_STAT_ACK;
- }
-
- totlen = brcmu_pkttotlen(p);
- free_pdu = true;
-
- wlc_txfifo_complete(wlc, queue, 1);
-
- if (lastframe) {
- p->next = NULL;
- p->prev = NULL;
- /* remove PLCP & Broadcom tx descriptor header */
- skb_pull(p, D11_PHY_HDR_LEN);
- skb_pull(p, D11_TXH_LEN);
- ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
- } else {
- wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
- "tx_status\n", __func__);
- }
-
- return false;
-
- fatal:
- if (p)
- brcmu_pkt_buf_free_skb(p);
-
- return true;
-
-}
-
-void
-wlc_txfifo_complete(struct wlc_info *wlc, uint fifo, s8 txpktpend)
-{
- TXPKTPENDDEC(wlc, fifo, txpktpend);
- BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend,
- TXPKTPENDGET(wlc, fifo));
-
- /* There is more room; mark precedences related to this FIFO sendable */
- WLC_TX_FIFO_ENAB(wlc, fifo);
-
- /* Clear MHF2_TXBCMC_NOW flag if BCMC fifo has drained */
- if (AP_ENAB(wlc->pub) &&
- !TXPKTPENDGET(wlc, TX_BCMC_FIFO)) {
- wlc_mhf(wlc, MHF2, MHF2_TXBCMC_NOW, 0, WLC_BAND_AUTO);
- }
-
- /* figure out which bsscfg is being worked on... */
-}
-
-/* Update beacon listen interval in shared memory */
-void wlc_bcn_li_upd(struct wlc_info *wlc)
-{
- if (AP_ENAB(wlc->pub))
- return;
-
- /* wake up every DTIM is the default */
- if (wlc->bcn_li_dtim == 1)
- wlc_write_shm(wlc, M_BCN_LI, 0);
- else
- wlc_write_shm(wlc, M_BCN_LI,
- (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
-}
-
-/*
- * recover 64bit TSF value from the 16bit TSF value in the rx header
- * given the assumption that the TSF passed in header is within 65ms
- * of the current tsf.
- *
- * 6 5 4 4 3 2 1
- * 3.......6.......8.......0.......2.......4.......6.......8......0
- * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
- *
- * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
- * tsf_l is filled in by wlc_bmac_recv, which is done earlier in the
- * receive call sequence after rx interrupt. Only the higher 16 bits
- * are used. Finally, the tsf_h is read from the tsf register.
- */
-static u64 wlc_recover_tsf64(struct wlc_info *wlc, struct wlc_d11rxhdr *rxh)
-{
- u32 tsf_h, tsf_l;
- u16 rx_tsf_0_15, rx_tsf_16_31;
-
- wlc_bmac_read_tsf(wlc->hw, &tsf_l, &tsf_h);
-
- rx_tsf_16_31 = (u16)(tsf_l >> 16);
- rx_tsf_0_15 = rxh->rxhdr.RxTSFTime;
-
- /*
- * a greater tsf time indicates the low 16 bits of
- * tsf_l wrapped, so decrement the high 16 bits.
- */
- if ((u16)tsf_l < rx_tsf_0_15) {
- rx_tsf_16_31 -= 1;
- if (rx_tsf_16_31 == 0xffff)
- tsf_h -= 1;
- }
-
- return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
-}
-
-static void
-prep_mac80211_status(struct wlc_info *wlc, d11rxhdr_t *rxh, struct sk_buff *p,
- struct ieee80211_rx_status *rx_status)
-{
- wlc_d11rxhdr_t *wlc_rxh = (wlc_d11rxhdr_t *) rxh;
- int preamble;
- int channel;
- ratespec_t rspec;
- unsigned char *plcp;
-
- /* fill in TSF and flag its presence */
- rx_status->mactime = wlc_recover_tsf64(wlc, wlc_rxh);
- rx_status->flag |= RX_FLAG_MACTIME_MPDU;
-
- channel = WLC_CHAN_CHANNEL(rxh->RxChan);
-
- if (channel > 14) {
- rx_status->band = IEEE80211_BAND_5GHZ;
- rx_status->freq = ieee80211_ofdm_chan_to_freq(
- WF_CHAN_FACTOR_5_G/2, channel);
-
- } else {
- rx_status->band = IEEE80211_BAND_2GHZ;
- rx_status->freq = ieee80211_dsss_chan_to_freq(channel);
- }
-
- rx_status->signal = wlc_rxh->rssi; /* signal */
-
- /* noise */
- /* qual */
- rx_status->antenna = (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0; /* ant */
-
- plcp = p->data;
-
- rspec = wlc_compute_rspec(rxh, plcp);
- if (IS_MCS(rspec)) {
- rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
- rx_status->flag |= RX_FLAG_HT;
- if (RSPEC_IS40MHZ(rspec))
- rx_status->flag |= RX_FLAG_40MHZ;
- } else {
- switch (RSPEC2RATE(rspec)) {
- case WLC_RATE_1M:
- rx_status->rate_idx = 0;
- break;
- case WLC_RATE_2M:
- rx_status->rate_idx = 1;
- break;
- case WLC_RATE_5M5:
- rx_status->rate_idx = 2;
- break;
- case WLC_RATE_11M:
- rx_status->rate_idx = 3;
- break;
- case WLC_RATE_6M:
- rx_status->rate_idx = 4;
- break;
- case WLC_RATE_9M:
- rx_status->rate_idx = 5;
- break;
- case WLC_RATE_12M:
- rx_status->rate_idx = 6;
- break;
- case WLC_RATE_18M:
- rx_status->rate_idx = 7;
- break;
- case WLC_RATE_24M:
- rx_status->rate_idx = 8;
- break;
- case WLC_RATE_36M:
- rx_status->rate_idx = 9;
- break;
- case WLC_RATE_48M:
- rx_status->rate_idx = 10;
- break;
- case WLC_RATE_54M:
- rx_status->rate_idx = 11;
- break;
- default:
- wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
- }
-
- /* Determine short preamble and rate_idx */
- preamble = 0;
- if (IS_CCK(rspec)) {
- if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
- rx_status->flag |= RX_FLAG_SHORTPRE;
- } else if (IS_OFDM(rspec)) {
- rx_status->flag |= RX_FLAG_SHORTPRE;
- } else {
- wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
- __func__);
- }
- }
-
- if (PLCP3_ISSGI(plcp[3]))
- rx_status->flag |= RX_FLAG_SHORT_GI;
-
- if (rxh->RxStatus1 & RXS_DECERR) {
- rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
- wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
- __func__);
- }
- if (rxh->RxStatus1 & RXS_FCSERR) {
- rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
- wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
- __func__);
- }
-}
-
-static void
-wlc_recvctl(struct wlc_info *wlc, d11rxhdr_t *rxh, struct sk_buff *p)
-{
- int len_mpdu;
- struct ieee80211_rx_status rx_status;
-
- memset(&rx_status, 0, sizeof(rx_status));
- prep_mac80211_status(wlc, rxh, p, &rx_status);
-
- /* mac header+body length, exclude CRC and plcp header */
- len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
- skb_pull(p, D11_PHY_HDR_LEN);
- __skb_trim(p, len_mpdu);
-
- memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
- ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
- return;
-}
-
-/* Process received frames */
-/*
- * Return true if more frames need to be processed. false otherwise.
- * Param 'bound' indicates max. # frames to process before break out.
- */
-/* WLC_HIGH_API */
-void wlc_recv(struct wlc_info *wlc, struct sk_buff *p)
-{
- d11rxhdr_t *rxh;
- struct ieee80211_hdr *h;
- uint len;
- bool is_amsdu;
-
- BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
-
- /* frame starts with rxhdr */
- rxh = (d11rxhdr_t *) (p->data);
-
- /* strip off rxhdr */
- skb_pull(p, WL_HWRXOFF);
-
- /* fixup rx header endianness */
- rxh->RxFrameSize = le16_to_cpu(rxh->RxFrameSize);
- rxh->PhyRxStatus_0 = le16_to_cpu(rxh->PhyRxStatus_0);
- rxh->PhyRxStatus_1 = le16_to_cpu(rxh->PhyRxStatus_1);
- rxh->PhyRxStatus_2 = le16_to_cpu(rxh->PhyRxStatus_2);
- rxh->PhyRxStatus_3 = le16_to_cpu(rxh->PhyRxStatus_3);
- rxh->PhyRxStatus_4 = le16_to_cpu(rxh->PhyRxStatus_4);
- rxh->PhyRxStatus_5 = le16_to_cpu(rxh->PhyRxStatus_5);
- rxh->RxStatus1 = le16_to_cpu(rxh->RxStatus1);
- rxh->RxStatus2 = le16_to_cpu(rxh->RxStatus2);
- rxh->RxTSFTime = le16_to_cpu(rxh->RxTSFTime);
- rxh->RxChan = le16_to_cpu(rxh->RxChan);
-
- /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
- if (rxh->RxStatus1 & RXS_PBPRES) {
- if (p->len < 2) {
- wiphy_err(wlc->wiphy, "wl%d: wlc_recv: rcvd runt of "
- "len %d\n", wlc->pub->unit, p->len);
- goto toss;
- }
- skb_pull(p, 2);
- }
-
- h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
- len = p->len;
-
- if (rxh->RxStatus1 & RXS_FCSERR) {
- if (wlc->pub->mac80211_state & MAC80211_PROMISC_BCNS) {
- wiphy_err(wlc->wiphy, "FCSERR while scanning******* -"
- " tossing\n");
- goto toss;
- } else {
- wiphy_err(wlc->wiphy, "RCSERR!!!\n");
- goto toss;
- }
- }
-
- /* check received pkt has at least frame control field */
- if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control)) {
- goto toss;
- }
-
- is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
-
- /* explicitly test bad src address to avoid sending bad deauth */
- if (!is_amsdu) {
- /* CTS and ACK CTL frames are w/o a2 */
-
- if (ieee80211_is_data(h->frame_control) ||
- ieee80211_is_mgmt(h->frame_control)) {
- if ((is_zero_ether_addr(h->addr2) ||
- is_multicast_ether_addr(h->addr2))) {
- wiphy_err(wlc->wiphy, "wl%d: %s: dropping a "
- "frame with invalid src mac address,"
- " a2: %pM\n",
- wlc->pub->unit, __func__, h->addr2);
- goto toss;
- }
- }
- }
-
- /* due to sheer numbers, toss out probe reqs for now */
- if (ieee80211_is_probe_req(h->frame_control))
- goto toss;
-
- if (is_amsdu)
- goto toss;
-
- wlc_recvctl(wlc, rxh, p);
- return;
-
- toss:
- brcmu_pkt_buf_free_skb(p);
-}
-
-/* calculate frame duration for Mixed-mode L-SIG spoofing, return
- * number of bytes goes in the length field
- *
- * Formula given by HT PHY Spec v 1.13
- * len = 3(nsyms + nstream + 3) - 3
- */
-u16
-wlc_calc_lsig_len(struct wlc_info *wlc, ratespec_t ratespec, uint mac_len)
-{
- uint nsyms, len = 0, kNdps;
-
- BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
- wlc->pub->unit, RSPEC2RATE(ratespec), mac_len);
-
- if (IS_MCS(ratespec)) {
- uint mcs = ratespec & RSPEC_RATE_MASK;
- /* MCS_TXS(mcs) returns num tx streams - 1 */
- int tot_streams = (MCS_TXS(mcs) + 1) + RSPEC_STC(ratespec);
-
- /* the payload duration calculation matches that of regular ofdm */
- /* 1000Ndbps = kbps * 4 */
- kNdps =
- MCS_RATE(mcs, RSPEC_IS40MHZ(ratespec),
- RSPEC_ISSGI(ratespec)) * 4;
-
- if (RSPEC_STC(ratespec) == 0)
- /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
- nsyms =
- CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
- APHY_TAIL_NBITS) * 1000, kNdps);
- else
- /* STBC needs to have even number of symbols */
- nsyms =
- 2 *
- CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
- APHY_TAIL_NBITS) * 1000, 2 * kNdps);
-
- nsyms += (tot_streams + 3); /* (+3) account for HT-SIG(2) and HT-STF(1) */
- /* 3 bytes/symbol @ legacy 6Mbps rate */
- len = (3 * nsyms) - 3; /* (-3) excluding service bits and tail bits */
- }
-
- return (u16) len;
-}
-
-/* calculate frame duration of a given rate and length, return time in usec unit */
-uint
-wlc_calc_frame_time(struct wlc_info *wlc, ratespec_t ratespec, u8 preamble_type,
- uint mac_len)
-{
- uint nsyms, dur = 0, Ndps, kNdps;
- uint rate = RSPEC2RATE(ratespec);
-
- if (rate == 0) {
- wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
- wlc->pub->unit);
- rate = WLC_RATE_1M;
- }
-
- BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
- wlc->pub->unit, ratespec, preamble_type, mac_len);
-
- if (IS_MCS(ratespec)) {
- uint mcs = ratespec & RSPEC_RATE_MASK;
- int tot_streams = MCS_TXS(mcs) + RSPEC_STC(ratespec);
-
- dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
- if (preamble_type == WLC_MM_PREAMBLE)
- dur += PREN_MM_EXT;
- /* 1000Ndbps = kbps * 4 */
- kNdps =
- MCS_RATE(mcs, RSPEC_IS40MHZ(ratespec),
- RSPEC_ISSGI(ratespec)) * 4;
-
- if (RSPEC_STC(ratespec) == 0)
- /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
- nsyms =
- CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
- APHY_TAIL_NBITS) * 1000, kNdps);
- else
- /* STBC needs to have even number of symbols */
- nsyms =
- 2 *
- CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
- APHY_TAIL_NBITS) * 1000, 2 * kNdps);
-
- dur += APHY_SYMBOL_TIME * nsyms;
- if (BAND_2G(wlc->band->bandtype))
- dur += DOT11_OFDM_SIGNAL_EXTENSION;
- } else if (IS_OFDM(rate)) {
- dur = APHY_PREAMBLE_TIME;
- dur += APHY_SIGNAL_TIME;
- /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
- Ndps = rate * 2;
- /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
- nsyms =
- CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
- Ndps);
- dur += APHY_SYMBOL_TIME * nsyms;
- if (BAND_2G(wlc->band->bandtype))
- dur += DOT11_OFDM_SIGNAL_EXTENSION;
- } else {
- /* calc # bits * 2 so factor of 2 in rate (1/2 mbps) will divide out */
- mac_len = mac_len * 8 * 2;
- /* calc ceiling of bits/rate = microseconds of air time */
- dur = (mac_len + rate - 1) / rate;
- if (preamble_type & WLC_SHORT_PREAMBLE)
- dur += BPHY_PLCP_SHORT_TIME;
- else
- dur += BPHY_PLCP_TIME;
- }
- return dur;
-}
-
-/* The opposite of wlc_calc_frame_time */
-static uint
-wlc_calc_frame_len(struct wlc_info *wlc, ratespec_t ratespec, u8 preamble_type,
- uint dur)
-{
- uint nsyms, mac_len, Ndps, kNdps;
- uint rate = RSPEC2RATE(ratespec);
-
- BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
- wlc->pub->unit, ratespec, preamble_type, dur);
-
- if (IS_MCS(ratespec)) {
- uint mcs = ratespec & RSPEC_RATE_MASK;
- int tot_streams = MCS_TXS(mcs) + RSPEC_STC(ratespec);
- dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
- /* payload calculation matches that of regular ofdm */
- if (BAND_2G(wlc->band->bandtype))
- dur -= DOT11_OFDM_SIGNAL_EXTENSION;
- /* kNdbps = kbps * 4 */
- kNdps =
- MCS_RATE(mcs, RSPEC_IS40MHZ(ratespec),
- RSPEC_ISSGI(ratespec)) * 4;
- nsyms = dur / APHY_SYMBOL_TIME;
- mac_len =
- ((nsyms * kNdps) -
- ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
- } else if (IS_OFDM(ratespec)) {
- dur -= APHY_PREAMBLE_TIME;
- dur -= APHY_SIGNAL_TIME;
- /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
- Ndps = rate * 2;
- nsyms = dur / APHY_SYMBOL_TIME;
- mac_len =
- ((nsyms * Ndps) -
- (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
- } else {
- if (preamble_type & WLC_SHORT_PREAMBLE)
- dur -= BPHY_PLCP_SHORT_TIME;
- else
- dur -= BPHY_PLCP_TIME;
- mac_len = dur * rate;
- /* divide out factor of 2 in rate (1/2 mbps) */
- mac_len = mac_len / 8 / 2;
- }
- return mac_len;
-}
-
-static uint
-wlc_calc_ba_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
-{
- BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
- "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
- /* Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that is less than
- * or equal to the rate of the immediately previous frame in the FES
- */
- rspec = WLC_BASIC_RATE(wlc, rspec);
- /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
- return wlc_calc_frame_time(wlc, rspec, preamble_type,
- (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
- FCS_LEN));
-}
-
-static uint
-wlc_calc_ack_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
-{
- uint dur = 0;
-
- BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
- wlc->pub->unit, rspec, preamble_type);
- /* Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that is less than
- * or equal to the rate of the immediately previous frame in the FES
- */
- rspec = WLC_BASIC_RATE(wlc, rspec);
- /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
- dur =
- wlc_calc_frame_time(wlc, rspec, preamble_type,
- (DOT11_ACK_LEN + FCS_LEN));
- return dur;
-}
-
-static uint
-wlc_calc_cts_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
-{
- BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
- wlc->pub->unit, rspec, preamble_type);
- return wlc_calc_ack_time(wlc, rspec, preamble_type);
-}
-
-/* derive wlc->band->basic_rate[] table from 'rateset' */
-void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset)
-{
- u8 rate;
- u8 mandatory;
- u8 cck_basic = 0;
- u8 ofdm_basic = 0;
- u8 *br = wlc->band->basic_rate;
- uint i;
-
- /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
- memset(br, 0, WLC_MAXRATE + 1);
-
- /* For each basic rate in the rates list, make an entry in the
- * best basic lookup.
- */
- for (i = 0; i < rateset->count; i++) {
- /* only make an entry for a basic rate */
- if (!(rateset->rates[i] & WLC_RATE_FLAG))
- continue;
-
- /* mask off basic bit */
- rate = (rateset->rates[i] & WLC_RATE_MASK);
-
- if (rate > WLC_MAXRATE) {
- wiphy_err(wlc->wiphy, "wlc_rate_lookup_init: invalid "
- "rate 0x%X in rate set\n",
- rateset->rates[i]);
- continue;
- }
-
- br[rate] = rate;
- }
-
- /* The rate lookup table now has non-zero entries for each
- * basic rate, equal to the basic rate: br[basicN] = basicN
- *
- * To look up the best basic rate corresponding to any
- * particular rate, code can use the basic_rate table
- * like this
- *
- * basic_rate = wlc->band->basic_rate[tx_rate]
- *
- * Make sure there is a best basic rate entry for
- * every rate by walking up the table from low rates
- * to high, filling in holes in the lookup table
- */
-
- for (i = 0; i < wlc->band->hw_rateset.count; i++) {
- rate = wlc->band->hw_rateset.rates[i];
-
- if (br[rate] != 0) {
- /* This rate is a basic rate.
- * Keep track of the best basic rate so far by
- * modulation type.
- */
- if (IS_OFDM(rate))
- ofdm_basic = rate;
- else
- cck_basic = rate;
-
- continue;
- }
-
- /* This rate is not a basic rate so figure out the
- * best basic rate less than this rate and fill in
- * the hole in the table
- */
-
- br[rate] = IS_OFDM(rate) ? ofdm_basic : cck_basic;
-
- if (br[rate] != 0)
- continue;
-
- if (IS_OFDM(rate)) {
- /* In 11g and 11a, the OFDM mandatory rates are 6, 12, and 24 Mbps */
- if (rate >= WLC_RATE_24M)
- mandatory = WLC_RATE_24M;
- else if (rate >= WLC_RATE_12M)
- mandatory = WLC_RATE_12M;
- else
- mandatory = WLC_RATE_6M;
- } else {
- /* In 11b, all the CCK rates are mandatory 1 - 11 Mbps */
- mandatory = rate;
- }
-
- br[rate] = mandatory;
- }
-}
-
-static void wlc_write_rate_shm(struct wlc_info *wlc, u8 rate, u8 basic_rate)
-{
- u8 phy_rate, index;
- u8 basic_phy_rate, basic_index;
- u16 dir_table, basic_table;
- u16 basic_ptr;
-
- /* Shared memory address for the table we are reading */
- dir_table = IS_OFDM(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
-
- /* Shared memory address for the table we are writing */
- basic_table = IS_OFDM(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
-
- /*
- * for a given rate, the LS-nibble of the PLCP SIGNAL field is
- * the index into the rate table.
- */
- phy_rate = rate_info[rate] & WLC_RATE_MASK;
- basic_phy_rate = rate_info[basic_rate] & WLC_RATE_MASK;
- index = phy_rate & 0xf;
- basic_index = basic_phy_rate & 0xf;
-
- /* Find the SHM pointer to the ACK rate entry by looking in the
- * Direct-map Table
- */
- basic_ptr = wlc_read_shm(wlc, (dir_table + basic_index * 2));
-
- /* Update the SHM BSS-basic-rate-set mapping table with the pointer
- * to the correct basic rate for the given incoming rate
- */
- wlc_write_shm(wlc, (basic_table + index * 2), basic_ptr);
-}
-
-static const wlc_rateset_t *wlc_rateset_get_hwrs(struct wlc_info *wlc)
-{
- const wlc_rateset_t *rs_dflt;
-
- if (WLC_PHY_11N_CAP(wlc->band)) {
- if (BAND_5G(wlc->band->bandtype))
- rs_dflt = &ofdm_mimo_rates;
- else
- rs_dflt = &cck_ofdm_mimo_rates;
- } else if (wlc->band->gmode)
- rs_dflt = &cck_ofdm_rates;
- else
- rs_dflt = &cck_rates;
-
- return rs_dflt;
-}
-
-void wlc_set_ratetable(struct wlc_info *wlc)
-{
- const wlc_rateset_t *rs_dflt;
- wlc_rateset_t rs;
- u8 rate, basic_rate;
- uint i;
-
- rs_dflt = wlc_rateset_get_hwrs(wlc);
-
- wlc_rateset_copy(rs_dflt, &rs);
- wlc_rateset_mcs_upd(&rs, wlc->stf->txstreams);
-
- /* walk the phy rate table and update SHM basic rate lookup table */
- for (i = 0; i < rs.count; i++) {
- rate = rs.rates[i] & WLC_RATE_MASK;
-
- /* for a given rate WLC_BASIC_RATE returns the rate at
- * which a response ACK/CTS should be sent.
- */
- basic_rate = WLC_BASIC_RATE(wlc, rate);
- if (basic_rate == 0) {
- /* This should only happen if we are using a
- * restricted rateset.
- */
- basic_rate = rs.rates[0] & WLC_RATE_MASK;
- }
-
- wlc_write_rate_shm(wlc, rate, basic_rate);
- }
-}
-
-/*
- * Return true if the specified rate is supported by the specified band.
- * WLC_BAND_AUTO indicates the current band.
- */
-bool wlc_valid_rate(struct wlc_info *wlc, ratespec_t rspec, int band,
- bool verbose)
-{
- wlc_rateset_t *hw_rateset;
- uint i;
-
- if ((band == WLC_BAND_AUTO) || (band == wlc->band->bandtype)) {
- hw_rateset = &wlc->band->hw_rateset;
- } else if (NBANDS(wlc) > 1) {
- hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
- } else {
- /* other band specified and we are a single band device */
- return false;
- }
-
- /* check if this is a mimo rate */
- if (IS_MCS(rspec)) {
- if (!VALID_MCS((rspec & RSPEC_RATE_MASK)))
- goto error;
-
- return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
- }
-
- for (i = 0; i < hw_rateset->count; i++)
- if (hw_rateset->rates[i] == RSPEC2RATE(rspec))
- return true;
- error:
- if (verbose) {
- wiphy_err(wlc->wiphy, "wl%d: wlc_valid_rate: rate spec 0x%x "
- "not in hw_rateset\n", wlc->pub->unit, rspec);
- }
-
- return false;
-}
-
-static void wlc_update_mimo_band_bwcap(struct wlc_info *wlc, u8 bwcap)
-{
- uint i;
- struct wlcband *band;
-
- for (i = 0; i < NBANDS(wlc); i++) {
- if (IS_SINGLEBAND_5G(wlc->deviceid))
- i = BAND_5G_INDEX;
- band = wlc->bandstate[i];
- if (band->bandtype == WLC_BAND_5G) {
- if ((bwcap == WLC_N_BW_40ALL)
- || (bwcap == WLC_N_BW_20IN2G_40IN5G))
- band->mimo_cap_40 = true;
- else
- band->mimo_cap_40 = false;
- } else {
- if (bwcap == WLC_N_BW_40ALL)
- band->mimo_cap_40 = true;
- else
- band->mimo_cap_40 = false;
- }
- }
-}
-
-void wlc_mod_prb_rsp_rate_table(struct wlc_info *wlc, uint frame_len)
-{
- const wlc_rateset_t *rs_dflt;
- wlc_rateset_t rs;
- u8 rate;
- u16 entry_ptr;
- u8 plcp[D11_PHY_HDR_LEN];
- u16 dur, sifs;
- uint i;
-
- sifs = SIFS(wlc->band);
-
- rs_dflt = wlc_rateset_get_hwrs(wlc);
-
- wlc_rateset_copy(rs_dflt, &rs);
- wlc_rateset_mcs_upd(&rs, wlc->stf->txstreams);
-
- /* walk the phy rate table and update MAC core SHM basic rate table entries */
- for (i = 0; i < rs.count; i++) {
- rate = rs.rates[i] & WLC_RATE_MASK;
-
- entry_ptr = wlc_rate_shm_offset(wlc, rate);
-
- /* Calculate the Probe Response PLCP for the given rate */
- wlc_compute_plcp(wlc, rate, frame_len, plcp);
-
- /* Calculate the duration of the Probe Response frame plus SIFS for the MAC */
- dur =
- (u16) wlc_calc_frame_time(wlc, rate, WLC_LONG_PREAMBLE,
- frame_len);
- dur += sifs;
-
- /* Update the SHM Rate Table entry Probe Response values */
- wlc_write_shm(wlc, entry_ptr + M_RT_PRS_PLCP_POS,
- (u16) (plcp[0] + (plcp[1] << 8)));
- wlc_write_shm(wlc, entry_ptr + M_RT_PRS_PLCP_POS + 2,
- (u16) (plcp[2] + (plcp[3] << 8)));
- wlc_write_shm(wlc, entry_ptr + M_RT_PRS_DUR_POS, dur);
- }
-}
-
-/* Max buffering needed for beacon template/prb resp template is 142 bytes.
- *
- * PLCP header is 6 bytes.
- * 802.11 A3 header is 24 bytes.
- * Max beacon frame body template length is 112 bytes.
- * Max probe resp frame body template length is 110 bytes.
- *
- * *len on input contains the max length of the packet available.
- *
- * The *len value is set to the number of bytes in buf used, and starts with the PLCP
- * and included up to, but not including, the 4 byte FCS.
- */
-static void
-wlc_bcn_prb_template(struct wlc_info *wlc, u16 type, ratespec_t bcn_rspec,
- struct wlc_bsscfg *cfg, u16 *buf, int *len)
-{
- static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
- cck_phy_hdr_t *plcp;
- struct ieee80211_mgmt *h;
- int hdr_len, body_len;
-
- if (MBSS_BCN_ENAB(cfg) && type == IEEE80211_STYPE_BEACON)
- hdr_len = DOT11_MAC_HDR_LEN;
- else
- hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
- body_len = *len - hdr_len; /* calc buffer size provided for frame body */
-
- *len = hdr_len + body_len; /* return actual size */
-
- /* format PHY and MAC headers */
- memset((char *)buf, 0, hdr_len);
-
- plcp = (cck_phy_hdr_t *) buf;
-
- /* PLCP for Probe Response frames are filled in from core's rate table */
- if (type == IEEE80211_STYPE_BEACON && !MBSS_BCN_ENAB(cfg)) {
- /* fill in PLCP */
- wlc_compute_plcp(wlc, bcn_rspec,
- (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
- (u8 *) plcp);
-
- }
- /* "Regular" and 16 MBSS but not for 4 MBSS */
- /* Update the phytxctl for the beacon based on the rspec */
- if (!SOFTBCN_ENAB(cfg))
- wlc_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
-
- if (MBSS_BCN_ENAB(cfg) && type == IEEE80211_STYPE_BEACON)
- h = (struct ieee80211_mgmt *)&plcp[0];
- else
- h = (struct ieee80211_mgmt *)&plcp[1];
-
- /* fill in 802.11 header */
- h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
-
- /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
- /* A1 filled in by MAC for prb resp, broadcast for bcn */
- if (type == IEEE80211_STYPE_BEACON)
- memcpy(&h->da, ðer_bcast, ETH_ALEN);
- memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
- memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
-
- /* SEQ filled in by MAC */
-
- return;
-}
-
-int wlc_get_header_len()
-{
- return TXOFF;
-}
-
-/* Update a beacon for a particular BSS
- * For MBSS, this updates the software template and sets "latest" to the index of the
- * template updated.
- * Otherwise, it updates the hardware template.
- */
-void wlc_bss_update_beacon(struct wlc_info *wlc, struct wlc_bsscfg *cfg)
-{
- int len = BCN_TMPL_LEN;
-
- /* Clear the soft intmask */
- wlc->defmacintmask &= ~MI_BCNTPL;
-
- if (!cfg->up) { /* Only allow updates on an UP bss */
- return;
- }
-
- /* Optimize: Some of if/else could be combined */
- if (!MBSS_BCN_ENAB(cfg) && HWBCN_ENAB(cfg)) {
- /* Hardware beaconing for this config */
- u16 bcn[BCN_TMPL_LEN / 2];
- u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD;
- d11regs_t *regs = wlc->regs;
-
- /* Check if both templates are in use, if so sched. an interrupt
- * that will call back into this routine
- */
- if ((R_REG(®s->maccommand) & both_valid) == both_valid) {
- /* clear any previous status */
- W_REG(®s->macintstatus, MI_BCNTPL);
- }
- /* Check that after scheduling the interrupt both of the
- * templates are still busy. if not clear the int. & remask
- */
- if ((R_REG(®s->maccommand) & both_valid) == both_valid) {
- wlc->defmacintmask |= MI_BCNTPL;
- return;
- }
-
- wlc->bcn_rspec =
- wlc_lowest_basic_rspec(wlc, &cfg->current_bss->rateset);
- /* update the template and ucode shm */
- wlc_bcn_prb_template(wlc, IEEE80211_STYPE_BEACON,
- wlc->bcn_rspec, cfg, bcn, &len);
- wlc_write_hw_bcntemplates(wlc, bcn, len, false);
- }
-}
-
-/*
- * Update all beacons for the system.
- */
-void wlc_update_beacon(struct wlc_info *wlc)
-{
- int idx;
- struct wlc_bsscfg *bsscfg;
-
- /* update AP or IBSS beacons */
- FOREACH_BSS(wlc, idx, bsscfg) {
- if (bsscfg->up && (BSSCFG_AP(bsscfg) || !bsscfg->BSS))
- wlc_bss_update_beacon(wlc, bsscfg);
- }
-}
-
-/* Write ssid into shared memory */
-void wlc_shm_ssid_upd(struct wlc_info *wlc, struct wlc_bsscfg *cfg)
-{
- u8 *ssidptr = cfg->SSID;
- u16 base = M_SSID;
- u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
-
- /* padding the ssid with zero and copy it into shm */
- memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
- memcpy(ssidbuf, ssidptr, cfg->SSID_len);
-
- wlc_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
-
- if (!MBSS_BCN_ENAB(cfg))
- wlc_write_shm(wlc, M_SSIDLEN, (u16) cfg->SSID_len);
-}
-
-void wlc_update_probe_resp(struct wlc_info *wlc, bool suspend)
-{
- int idx;
- struct wlc_bsscfg *bsscfg;
-
- /* update AP or IBSS probe responses */
- FOREACH_BSS(wlc, idx, bsscfg) {
- if (bsscfg->up && (BSSCFG_AP(bsscfg) || !bsscfg->BSS))
- wlc_bss_update_probe_resp(wlc, bsscfg, suspend);
- }
-}
-
-void
-wlc_bss_update_probe_resp(struct wlc_info *wlc, struct wlc_bsscfg *cfg,
- bool suspend)
-{
- u16 prb_resp[BCN_TMPL_LEN / 2];
- int len = BCN_TMPL_LEN;
-
- /* write the probe response to hardware, or save in the config structure */
- if (!MBSS_PRB_ENAB(cfg)) {
-
- /* create the probe response template */
- wlc_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0, cfg,
- prb_resp, &len);
-
- if (suspend)
- wlc_suspend_mac_and_wait(wlc);
-
- /* write the probe response into the template region */
- wlc_bmac_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
- (len + 3) & ~3, prb_resp);
-
- /* write the length of the probe response frame (+PLCP/-FCS) */
- wlc_write_shm(wlc, M_PRB_RESP_FRM_LEN, (u16) len);
-
- /* write the SSID and SSID length */
- wlc_shm_ssid_upd(wlc, cfg);
-
- /*
- * Write PLCP headers and durations for probe response frames at all rates.
- * Use the actual frame length covered by the PLCP header for the call to
- * wlc_mod_prb_rsp_rate_table() by subtracting the PLCP len and adding the FCS.
- */
- len += (-D11_PHY_HDR_LEN + FCS_LEN);
- wlc_mod_prb_rsp_rate_table(wlc, (u16) len);
-
- if (suspend)
- wlc_enable_mac(wlc);
- } else { /* Generating probe resp in sw; update local template */
- /* error: No software probe response support without MBSS */
- }
-}
-
-/* prepares pdu for transmission. returns BCM error codes */
-int wlc_prep_pdu(struct wlc_info *wlc, struct sk_buff *pdu, uint *fifop)
-{
- uint fifo;
- d11txh_t *txh;
- struct ieee80211_hdr *h;
- struct scb *scb;
-
- txh = (d11txh_t *) (pdu->data);
- h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
-
- /* get the pkt queue info. This was put at wlc_sendctl or wlc_send for PDU */
- fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
-
- scb = NULL;
-
- *fifop = fifo;
-
- /* return if insufficient dma resources */
- if (TXAVAIL(wlc, fifo) < MAX_DMA_SEGS) {
- /* Mark precedences related to this FIFO, unsendable */
- WLC_TX_FIFO_CLEAR(wlc, fifo);
- return -EBUSY;
- }
- return 0;
-}
-
-/* init tx reported rate mechanism */
-void wlc_reprate_init(struct wlc_info *wlc)
-{
- int i;
- struct wlc_bsscfg *bsscfg;
-
- FOREACH_BSS(wlc, i, bsscfg) {
- wlc_bsscfg_reprate_init(bsscfg);
- }
-}
-
-/* per bsscfg init tx reported rate mechanism */
-void wlc_bsscfg_reprate_init(struct wlc_bsscfg *bsscfg)
-{
- bsscfg->txrspecidx = 0;
- memset((char *)bsscfg->txrspec, 0, sizeof(bsscfg->txrspec));
-}
-
-void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs)
-{
- wlc_rateset_default(rs, NULL, wlc->band->phytype, wlc->band->bandtype,
- false, WLC_RATE_MASK_FULL, (bool) N_ENAB(wlc->pub),
- CHSPEC_WLC_BW(wlc->default_bss->chanspec),
- wlc->stf->txstreams);
-}
-
-static void wlc_bss_default_init(struct wlc_info *wlc)
-{
- chanspec_t chanspec;
- struct wlcband *band;
- wlc_bss_info_t *bi = wlc->default_bss;
-
- /* init default and target BSS with some sane initial values */
- memset((char *)(bi), 0, sizeof(wlc_bss_info_t));
- bi->beacon_period = ISSIM_ENAB(wlc->pub->sih) ? BEACON_INTERVAL_DEF_QT :
- BEACON_INTERVAL_DEFAULT;
- bi->dtim_period = ISSIM_ENAB(wlc->pub->sih) ? DTIM_INTERVAL_DEF_QT :
- DTIM_INTERVAL_DEFAULT;
-
- /* fill the default channel as the first valid channel
- * starting from the 2G channels
- */
- chanspec = CH20MHZ_CHSPEC(1);
- wlc->home_chanspec = bi->chanspec = chanspec;
-
- /* find the band of our default channel */
- band = wlc->band;
- if (NBANDS(wlc) > 1 && band->bandunit != CHSPEC_WLCBANDUNIT(chanspec))
- band = wlc->bandstate[OTHERBANDUNIT(wlc)];
-
- /* init bss rates to the band specific default rate set */
- wlc_rateset_default(&bi->rateset, NULL, band->phytype, band->bandtype,
- false, WLC_RATE_MASK_FULL, (bool) N_ENAB(wlc->pub),
- CHSPEC_WLC_BW(chanspec), wlc->stf->txstreams);
-
- if (N_ENAB(wlc->pub))
- bi->flags |= WLC_BSS_HT;
-}
-
-static ratespec_t
-mac80211_wlc_set_nrate(struct wlc_info *wlc, struct wlcband *cur_band,
- u32 int_val)
-{
- u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
- u8 rate = int_val & NRATE_RATE_MASK;
- ratespec_t rspec;
- bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
- bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
- bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
- == NRATE_OVERRIDE_MCS_ONLY);
- int bcmerror = 0;
-
- if (!ismcs) {
- return (ratespec_t) rate;
- }
-
- /* validate the combination of rate/mcs/stf is allowed */
- if (N_ENAB(wlc->pub) && ismcs) {
- /* mcs only allowed when nmode */
- if (stf > PHY_TXC1_MODE_SDM) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = -EINVAL;
- goto done;
- }
-
- /* mcs 32 is a special case, DUP mode 40 only */
- if (rate == 32) {
- if (!CHSPEC_IS40(wlc->home_chanspec) ||
- ((stf != PHY_TXC1_MODE_SISO)
- && (stf != PHY_TXC1_MODE_CDD))) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
- "32\n", WLCWLUNIT(wlc), __func__);
- bcmerror = -EINVAL;
- goto done;
- }
- /* mcs > 7 must use stf SDM */
- } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
- /* mcs > 7 must use stf SDM */
- if (stf != PHY_TXC1_MODE_SDM) {
- BCMMSG(wlc->wiphy, "wl%d: enabling "
- "SDM mode for mcs %d\n",
- WLCWLUNIT(wlc), rate);
- stf = PHY_TXC1_MODE_SDM;
- }
- } else {
- /* MCS 0-7 may use SISO, CDD, and for phy_rev >= 3 STBC */
- if ((stf > PHY_TXC1_MODE_STBC) ||
- (!WLC_STBC_CAP_PHY(wlc)
- && (stf == PHY_TXC1_MODE_STBC))) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
- "\n", WLCWLUNIT(wlc), __func__);
- bcmerror = -EINVAL;
- goto done;
- }
- }
- } else if (IS_OFDM(rate)) {
- if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = -EINVAL;
- goto done;
- }
- } else if (IS_CCK(rate)) {
- if ((cur_band->bandtype != WLC_BAND_2G)
- || (stf != PHY_TXC1_MODE_SISO)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = -EINVAL;
- goto done;
- }
- } else {
- wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = -EINVAL;
- goto done;
- }
- /* make sure multiple antennae are available for non-siso rates */
- if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
- wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
- "request\n", WLCWLUNIT(wlc), __func__);
- bcmerror = -EINVAL;
- goto done;
- }
-
- rspec = rate;
- if (ismcs) {
- rspec |= RSPEC_MIMORATE;
- /* For STBC populate the STC field of the ratespec */
- if (stf == PHY_TXC1_MODE_STBC) {
- u8 stc;
- stc = 1; /* Nss for single stream is always 1 */
- rspec |= (stc << RSPEC_STC_SHIFT);
- }
- }
-
- rspec |= (stf << RSPEC_STF_SHIFT);
-
- if (override_mcs_only)
- rspec |= RSPEC_OVERRIDE_MCS_ONLY;
-
- if (issgi)
- rspec |= RSPEC_SHORT_GI;
-
- if ((rate != 0)
- && !wlc_valid_rate(wlc, rspec, cur_band->bandtype, true)) {
- return rate;
- }
-
- return rspec;
-done:
- return rate;
-}
-
-/* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
-static int
-wlc_duty_cycle_set(struct wlc_info *wlc, int duty_cycle, bool isOFDM,
- bool writeToShm)
-{
- int idle_busy_ratio_x_16 = 0;
- uint offset =
- isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
- M_TX_IDLE_BUSY_RATIO_X_16_CCK;
- if (duty_cycle > 100 || duty_cycle < 0) {
- wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
- wlc->pub->unit);
- return -EINVAL;
- }
- if (duty_cycle)
- idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
- /* Only write to shared memory when wl is up */
- if (writeToShm)
- wlc_write_shm(wlc, offset, (u16) idle_busy_ratio_x_16);
-
- if (isOFDM)
- wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
- else
- wlc->tx_duty_cycle_cck = (u16) duty_cycle;
-
- return 0;
-}
-
-/* Read a single u16 from shared memory.
- * SHM 'offset' needs to be an even address
- */
-u16 wlc_read_shm(struct wlc_info *wlc, uint offset)
-{
- return wlc_bmac_read_shm(wlc->hw, offset);
-}
-
-/* Write a single u16 to shared memory.
- * SHM 'offset' needs to be an even address
- */
-void wlc_write_shm(struct wlc_info *wlc, uint offset, u16 v)
-{
- wlc_bmac_write_shm(wlc->hw, offset, v);
-}
-
-/* Copy a buffer to shared memory.
- * SHM 'offset' needs to be an even address and
- * Buffer length 'len' must be an even number of bytes
- */
-void wlc_copyto_shm(struct wlc_info *wlc, uint offset, const void *buf, int len)
-{
- /* offset and len need to be even */
- if (len <= 0 || (offset & 1) || (len & 1))
- return;
-
- wlc_bmac_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
-
-}
-
-/* wrapper BMAC functions to for HIGH driver access */
-void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val)
-{
- wlc_bmac_mctrl(wlc->hw, mask, val);
-}
-
-void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val, int bands)
-{
- wlc_bmac_mhf(wlc->hw, idx, mask, val, bands);
-}
-
-int wlc_xmtfifo_sz_get(struct wlc_info *wlc, uint fifo, uint *blocks)
-{
- return wlc_bmac_xmtfifo_sz_get(wlc->hw, fifo, blocks);
-}
-
-void wlc_write_template_ram(struct wlc_info *wlc, int offset, int len,
- void *buf)
-{
- wlc_bmac_write_template_ram(wlc->hw, offset, len, buf);
-}
-
-void wlc_write_hw_bcntemplates(struct wlc_info *wlc, void *bcn, int len,
- bool both)
-{
- wlc_bmac_write_hw_bcntemplates(wlc->hw, bcn, len, both);
-}
-
-void
-wlc_set_addrmatch(struct wlc_info *wlc, int match_reg_offset,
- const u8 *addr)
-{
- wlc_bmac_set_addrmatch(wlc->hw, match_reg_offset, addr);
- if (match_reg_offset == RCM_BSSID_OFFSET)
- memcpy(wlc->cfg->BSSID, addr, ETH_ALEN);
-}
-
-void wlc_pllreq(struct wlc_info *wlc, bool set, mbool req_bit)
-{
- wlc_bmac_pllreq(wlc->hw, set, req_bit);
-}
-
-void wlc_reset_bmac_done(struct wlc_info *wlc)
-{
-}
-
-/* check for the particular priority flow control bit being set */
-bool
-wlc_txflowcontrol_prio_isset(struct wlc_info *wlc, struct wlc_txq_info *q,
- int prio)
-{
- uint prio_mask;
-
- if (prio == ALLPRIO) {
- prio_mask = TXQ_STOP_FOR_PRIOFC_MASK;
- } else {
- prio_mask = NBITVAL(prio);
- }
-
- return (q->stopped & prio_mask) == prio_mask;
-}
-
-/* propagate the flow control to all interfaces using the given tx queue */
-void wlc_txflowcontrol(struct wlc_info *wlc, struct wlc_txq_info *qi,
- bool on, int prio)
-{
- uint prio_bits;
- uint cur_bits;
-
- BCMMSG(wlc->wiphy, "flow control kicks in\n");
-
- if (prio == ALLPRIO) {
- prio_bits = TXQ_STOP_FOR_PRIOFC_MASK;
- } else {
- prio_bits = NBITVAL(prio);
- }
-
- cur_bits = qi->stopped & prio_bits;
-
- /* Check for the case of no change and return early
- * Otherwise update the bit and continue
- */
- if (on) {
- if (cur_bits == prio_bits) {
- return;
- }
- mboolset(qi->stopped, prio_bits);
- } else {
- if (cur_bits == 0) {
- return;
- }
- mboolclr(qi->stopped, prio_bits);
- }
-
- /* If there is a flow control override we will not change the external
- * flow control state.
- */
- if (qi->stopped & ~TXQ_STOP_FOR_PRIOFC_MASK) {
- return;
- }
-
- wlc_txflowcontrol_signal(wlc, qi, on, prio);
-}
-
-void
-wlc_txflowcontrol_override(struct wlc_info *wlc, struct wlc_txq_info *qi,
- bool on, uint override)
-{
- uint prev_override;
-
- prev_override = (qi->stopped & ~TXQ_STOP_FOR_PRIOFC_MASK);
-
- /* Update the flow control bits and do an early return if there is
- * no change in the external flow control state.
- */
- if (on) {
- mboolset(qi->stopped, override);
- /* if there was a previous override bit on, then setting this
- * makes no difference.
- */
- if (prev_override) {
- return;
- }
-
- wlc_txflowcontrol_signal(wlc, qi, ON, ALLPRIO);
- } else {
- mboolclr(qi->stopped, override);
- /* clearing an override bit will only make a difference for
- * flow control if it was the only bit set. For any other
- * override setting, just return
- */
- if (prev_override != override) {
- return;
- }
-
- if (qi->stopped == 0) {
- wlc_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
- } else {
- int prio;
-
- for (prio = MAXPRIO; prio >= 0; prio--) {
- if (!mboolisset(qi->stopped, NBITVAL(prio)))
- wlc_txflowcontrol_signal(wlc, qi, OFF,
- prio);
- }
- }
- }
-}
-
-static void wlc_txflowcontrol_reset(struct wlc_info *wlc)
-{
- struct wlc_txq_info *qi;
-
- for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
- if (qi->stopped) {
- wlc_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
- qi->stopped = 0;
- }
- }
-}
-
-static void
-wlc_txflowcontrol_signal(struct wlc_info *wlc, struct wlc_txq_info *qi, bool on,
- int prio)
-{
-#ifdef NON_FUNCTIONAL
- /* wlcif_list is never filled so this function is not functional */
- struct wlc_if *wlcif;
-
- for (wlcif = wlc->wlcif_list; wlcif != NULL; wlcif = wlcif->next) {
- if (wlcif->qi == qi && wlcif->flags & WLC_IF_LINKED)
- brcms_txflowcontrol(wlc->wl, wlcif->wlif, on, prio);
- }
-#endif
-}
-
-static struct wlc_txq_info *wlc_txq_alloc(struct wlc_info *wlc)
-{
- struct wlc_txq_info *qi, *p;
-
- qi = kzalloc(sizeof(struct wlc_txq_info), GFP_ATOMIC);
- if (qi != NULL) {
- /*
- * Have enough room for control packets along with HI watermark
- * Also, add room to txq for total psq packets if all the SCBs
- * leave PS mode. The watermark for flowcontrol to OS packets
- * will remain the same
- */
- brcmu_pktq_init(&qi->q, WLC_PREC_COUNT,
- (2 * wlc->pub->tunables->datahiwat) + PKTQ_LEN_DEFAULT
- + wlc->pub->psq_pkts_total);
-
- /* add this queue to the the global list */
- p = wlc->tx_queues;
- if (p == NULL) {
- wlc->tx_queues = qi;
- } else {
- while (p->next != NULL)
- p = p->next;
- p->next = qi;
- }
- }
- return qi;
-}
-
-static void wlc_txq_free(struct wlc_info *wlc, struct wlc_txq_info *qi)
-{
- struct wlc_txq_info *p;
-
- if (qi == NULL)
- return;
-
- /* remove the queue from the linked list */
- p = wlc->tx_queues;
- if (p == qi)
- wlc->tx_queues = p->next;
- else {
- while (p != NULL && p->next != qi)
- p = p->next;
- if (p != NULL)
- p->next = p->next->next;
- }
-
- kfree(qi);
-}
-
-/*
- * Flag 'scan in progress' to withhold dynamic phy calibration
- */
-void wlc_scan_start(struct wlc_info *wlc)
-{
- wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
-}
-
-void wlc_scan_stop(struct wlc_info *wlc)
-{
- wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
-}
-
-void wlc_associate_upd(struct wlc_info *wlc, bool state)
-{
- wlc->pub->associated = state;
- wlc->cfg->associated = state;
-}
-
-/*
- * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
- * AMPDU traffic, packets pending in hardware have to be invalidated so that
- * when later on hardware releases them, they can be handled appropriately.
- */
-void wlc_inval_dma_pkts(struct wlc_hw_info *hw,
- struct ieee80211_sta *sta,
- void (*dma_callback_fn))
-{
- struct dma_pub *dmah;
- int i;
- for (i = 0; i < NFIFO; i++) {
- dmah = hw->di[i];
- if (dmah != NULL)
- dma_walk_packets(dmah, dma_callback_fn, sta);
- }
-}
-
-int wlc_get_curband(struct wlc_info *wlc)
-{
- return wlc->band->bandunit;
-}
-
-void wlc_wait_for_tx_completion(struct wlc_info *wlc, bool drop)
-{
- /* flush packet queue when requested */
- if (drop)
- brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
-
- /* wait for queue and DMA fifos to run dry */
- while (!pktq_empty(&wlc->pkt_queue->q) ||
- TXPKTPENDTOT(wlc) > 0) {
- brcms_msleep(wlc->wl, 1);
- }
-}
-
-int wlc_set_par(struct wlc_info *wlc, enum wlc_par_id par_id, int int_val)
-{
- int err = 0;
-
- switch (par_id) {
- case IOV_BCN_LI_BCN:
- wlc->bcn_li_bcn = (u8) int_val;
- if (wlc->pub->up)
- wlc_bcn_li_upd(wlc);
- break;
- /* As long as override is false, this only sets the *user*
- targets. User can twiddle this all he wants with no harm.
- wlc_phy_txpower_set() explicitly sets override to false if
- not internal or test.
- */
- case IOV_QTXPOWER:{
- u8 qdbm;
- bool override;
-
- /* Remove override bit and clip to max qdbm value */
- qdbm = (u8)min_t(u32, (int_val & ~WL_TXPWR_OVERRIDE), 0xff);
- /* Extract override setting */
- override = (int_val & WL_TXPWR_OVERRIDE) ? true : false;
- err =
- wlc_phy_txpower_set(wlc->band->pi, qdbm, override);
- break;
- }
- case IOV_MPC:
- wlc->mpc = (bool)int_val;
- wlc_radio_mpc_upd(wlc);
- break;
- default:
- err = -ENOTSUPP;
- }
- return err;
-}
-
-int wlc_get_par(struct wlc_info *wlc, enum wlc_par_id par_id, int *ret_int_ptr)
-{
- int err = 0;
-
- switch (par_id) {
- case IOV_BCN_LI_BCN:
- *ret_int_ptr = wlc->bcn_li_bcn;
- break;
- case IOV_QTXPOWER: {
- uint qdbm;
- bool override;
-
- err = wlc_phy_txpower_get(wlc->band->pi, &qdbm,
- &override);
- if (err != 0)
- return err;
-
- /* Return qdbm units */
- *ret_int_ptr =
- qdbm | (override ? WL_TXPWR_OVERRIDE : 0);
- break;
- }
- case IOV_MPC:
- *ret_int_ptr = (s32) wlc->mpc;
- break;
- default:
- err = -ENOTSUPP;
- }
- return err;
-}
-
-/*
- * Search the name=value vars for a specific one and return its value.
- * Returns NULL if not found.
- */
-char *getvar(char *vars, const char *name)
-{
- char *s;
- int len;
-
- if (!name)
- return NULL;
-
- len = strlen(name);
- if (len == 0)
- return NULL;
-
- /* first look in vars[] */
- for (s = vars; s && *s;) {
- if ((memcmp(s, name, len) == 0) && (s[len] == '='))
- return &s[len + 1];
-
- while (*s++)
- ;
- }
- /* nothing found */
- return NULL;
-}
-
-/*
- * Search the vars for a specific one and return its value as
- * an integer. Returns 0 if not found.
- */
-int getintvar(char *vars, const char *name)
-{
- char *val;
-
- val = getvar(vars, name);
- if (val == NULL)
- return 0;
-
- return simple_strtoul(val, NULL, 0);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_MAIN_H_
-#define _BRCM_MAIN_H_
-
-#define MA_WINDOW_SZ 8 /* moving average window size */
-#define WL_HWRXOFF 38 /* chip rx buffer offset */
-#define INVCHANNEL 255 /* invalid channel */
-#define MAXCOREREV 28 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
-#define WLC_MAXMODULES 22 /* max # wlc_module_register() calls */
-
-#define SEQNUM_SHIFT 4
-#define AMPDU_DELIMITER_LEN 4
-#define SEQNUM_MAX 0x1000
-
-#define APHY_CWMIN 15
-#define PHY_CWMAX 1023
-
-#define EDCF_AIFSN_MIN 1
-#define FRAGNUM_MASK 0xF
-
-#define WLC_BITSCNT(x) brcmu_bitcount((u8 *)&(x), sizeof(u8))
-
-/* Maximum wait time for a MAC suspend */
-#define WLC_MAX_MAC_SUSPEND 83000 /* uS: 83mS is max packet time (64KB ampdu @ 6Mbps) */
-
-/* Probe Response timeout - responses for probe requests older that this are tossed, zero to disable
- */
-#define WLC_PRB_RESP_TIMEOUT 0 /* Disable probe response timeout */
-
-/* transmit buffer max headroom for protocol headers */
-#define TXOFF (D11_TXH_LEN + D11_PHY_HDR_LEN)
-
-#define AC_COUNT 4
-
-/* Macros for doing definition and get/set of bitfields
- * Usage example, e.g. a three-bit field (bits 4-6):
- * #define <NAME>_M BITFIELD_MASK(3)
- * #define <NAME>_S 4
- * ...
- * regval = R_REG(osh, ®s->regfoo);
- * field = GFIELD(regval, <NAME>);
- * regval = SFIELD(regval, <NAME>, 1);
- * W_REG(osh, ®s->regfoo, regval);
- */
-#define BITFIELD_MASK(width) \
- (((unsigned)1 << (width)) - 1)
-#define GFIELD(val, field) \
- (((val) >> field ## _S) & field ## _M)
-#define SFIELD(val, field, bits) \
- (((val) & (~(field ## _M << field ## _S))) | \
- ((unsigned)(bits) << field ## _S))
-
-/* For managing scan result lists */
-struct wlc_bss_list {
- uint count;
- bool beacon; /* set for beacon, cleared for probe response */
- wlc_bss_info_t *ptrs[MAXBSS];
-};
-
-#define SW_TIMER_MAC_STAT_UPD 30 /* periodic MAC stats update */
-
-/* Double check that unsupported cores are not enabled */
-#if CONF_MSK(D11CONF, 0x4f) || CONF_GE(D11CONF, MAXCOREREV)
-#error "Configuration for D11CONF includes unsupported versions."
-#endif /* Bad versions */
-
-#define VALID_COREREV(corerev) CONF_HAS(D11CONF, corerev)
-
-/* values for shortslot_override */
-#define WLC_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
-#define WLC_SHORTSLOT_OFF 0 /* Turn off short slot */
-#define WLC_SHORTSLOT_ON 1 /* Turn on short slot */
-
-/* value for short/long and mixmode/greenfield preamble */
-
-#define WLC_LONG_PREAMBLE (0)
-#define WLC_SHORT_PREAMBLE (1 << 0)
-#define WLC_GF_PREAMBLE (1 << 1)
-#define WLC_MM_PREAMBLE (1 << 2)
-#define WLC_IS_MIMO_PREAMBLE(_pre) (((_pre) == WLC_GF_PREAMBLE) || ((_pre) == WLC_MM_PREAMBLE))
-
-/* values for barker_preamble */
-#define WLC_BARKER_SHORT_ALLOWED 0 /* Short pre-amble allowed */
-
-/* A fifo is full. Clear precedences related to that FIFO */
-#define WLC_TX_FIFO_CLEAR(wlc, fifo) ((wlc)->tx_prec_map &= ~(wlc)->fifo2prec_map[fifo])
-
-/* Fifo is NOT full. Enable precedences for that FIFO */
-#define WLC_TX_FIFO_ENAB(wlc, fifo) ((wlc)->tx_prec_map |= (wlc)->fifo2prec_map[fifo])
-
-/* TxFrameID */
-/* seq and frag bits: SEQNUM_SHIFT, FRAGNUM_MASK (802.11.h) */
-/* rate epoch bits: TXFID_RATE_SHIFT, TXFID_RATE_MASK ((wlc_rate.c) */
-#define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
-#define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
-#define TXFID_SEQ_SHIFT 5 /* Number of bit shifts */
-#define TXFID_RATE_PROBE_MASK 0x8000 /* Bit 15 for rate probe */
-#define TXFID_RATE_MASK 0x0018 /* Mask for bits 3 and 4 */
-#define TXFID_RATE_SHIFT 3 /* Shift 3 bits for rate mask */
-
-/* promote boardrev */
-#define BOARDREV_PROMOTABLE 0xFF /* from */
-#define BOARDREV_PROMOTED 1 /* to */
-
-/* if wpa is in use then portopen is true when the group key is plumbed otherwise it is always true
- */
-#define WSEC_ENABLED(wsec) ((wsec) & (WEP_ENABLED | TKIP_ENABLED | AES_ENABLED))
-#define WLC_SW_KEYS(wlc, bsscfg) ((((wlc)->wsec_swkeys) || \
- ((bsscfg)->wsec & WSEC_SWFLAG)))
-
-#define WLC_PORTOPEN(cfg) \
- (((cfg)->WPA_auth != WPA_AUTH_DISABLED && WSEC_ENABLED((cfg)->wsec)) ? \
- (cfg)->wsec_portopen : true)
-
-#define PS_ALLOWED(wlc) wlc_ps_allowed(wlc)
-
-#define DATA_BLOCK_TX_SUPR (1 << 4)
-
-/* 802.1D Priority to TX FIFO number for wme */
-extern const u8 prio2fifo[];
-
-/* Ucode MCTL_WAKE override bits */
-#define WLC_WAKE_OVERRIDE_CLKCTL 0x01
-#define WLC_WAKE_OVERRIDE_PHYREG 0x02
-#define WLC_WAKE_OVERRIDE_MACSUSPEND 0x04
-#define WLC_WAKE_OVERRIDE_TXFIFO 0x08
-#define WLC_WAKE_OVERRIDE_FORCEFAST 0x10
-
-/* stuff pulled in from wlc.c */
-
-/* Interrupt bit error summary. Don't include I_RU: we refill DMA at other
- * times; and if we run out, constant I_RU interrupts may cause lockup. We
- * will still get error counts from rx0ovfl.
- */
-#define I_ERRORS (I_PC | I_PD | I_DE | I_RO | I_XU)
-/* default software intmasks */
-#define DEF_RXINTMASK (I_RI) /* enable rx int on rxfifo only */
-#define DEF_MACINTMASK (MI_TXSTOP | MI_TBTT | MI_ATIMWINEND | MI_PMQ | \
- MI_PHYTXERR | MI_DMAINT | MI_TFS | MI_BG_NOISE | \
- MI_CCA | MI_TO | MI_GP0 | MI_RFDISABLE | MI_PWRUP)
-
-#define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
-#define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
-#define RETRY_LONG_DEF 4 /* Default Long retry count */
-#define RETRY_SHORT_FB 3 /* Short retry count for fallback rate */
-#define RETRY_LONG_FB 2 /* Long retry count for fallback rate */
-
-#define MAXTXPKTS 6 /* max # pkts pending */
-
-/* frameburst */
-#define MAXTXFRAMEBURST 8 /* vanilla xpress mode: max frames/burst */
-#define MAXFRAMEBURST_TXOP 10000 /* Frameburst TXOP in usec */
-
-/* Per-AC retry limit register definitions; uses bcmdefs.h bitfield macros */
-#define EDCF_SHORT_S 0
-#define EDCF_SFB_S 4
-#define EDCF_LONG_S 8
-#define EDCF_LFB_S 12
-#define EDCF_SHORT_M BITFIELD_MASK(4)
-#define EDCF_SFB_M BITFIELD_MASK(4)
-#define EDCF_LONG_M BITFIELD_MASK(4)
-#define EDCF_LFB_M BITFIELD_MASK(4)
-
-#define NFIFO 6 /* # tx/rx fifopairs */
-
-#define WLC_WME_RETRY_SHORT_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_SHORT)
-#define WLC_WME_RETRY_SFB_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_SFB)
-#define WLC_WME_RETRY_LONG_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_LONG)
-#define WLC_WME_RETRY_LFB_GET(wlc, ac) GFIELD(wlc->wme_retries[ac], EDCF_LFB)
-
-#define WLC_WME_RETRY_SHORT_SET(wlc, ac, val) \
- (wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], EDCF_SHORT, val))
-#define WLC_WME_RETRY_SFB_SET(wlc, ac, val) \
- (wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], EDCF_SFB, val))
-#define WLC_WME_RETRY_LONG_SET(wlc, ac, val) \
- (wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], EDCF_LONG, val))
-#define WLC_WME_RETRY_LFB_SET(wlc, ac, val) \
- (wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac], EDCF_LFB, val))
-
-/* PLL requests */
-#define WLC_PLLREQ_SHARED 0x1 /* pll is shared on old chips */
-#define WLC_PLLREQ_RADIO_MON 0x2 /* hold pll for radio monitor register checking */
-#define WLC_PLLREQ_FLIP 0x4 /* hold/release pll for some short operation */
-
-/*
- * Macros to check if AP or STA is active.
- * AP Active means more than just configured: driver and BSS are "up";
- * that is, we are beaconing/responding as an AP (aps_associated).
- * STA Active similarly means the driver is up and a configured STA BSS
- * is up: either associated (stas_associated) or trying.
- *
- * Macro definitions vary as per AP/STA ifdefs, allowing references to
- * ifdef'd structure fields and constant values (0) for optimization.
- * Make sure to enclose blocks of code such that any routines they
- * reference can also be unused and optimized out by the linker.
- */
-/* NOTE: References structure fields defined in wlc.h */
-#define AP_ACTIVE(wlc) (0)
-
-/*
- * Detect Card removed.
- * Even checking an sbconfig register read will not false trigger when the core is in reset.
- * it breaks CF address mechanism. Accessing gphy phyversion will cause SB error if aphy
- * is in reset on 4306B0-DB. Need a simple accessible reg with fixed 0/1 pattern
- * (some platforms return all 0).
- * If clocks are present, call the sb routine which will figure out if the device is removed.
- */
-#define DEVICEREMOVED(wlc) \
- ((wlc->hw->clk) ? \
- ((R_REG(&wlc->hw->regs->maccontrol) & \
- (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN) : \
- (ai_deviceremoved(wlc->hw->sih)))
-
-#define WLCWLUNIT(wlc) ((wlc)->pub->unit)
-
-struct wlc_protection {
- bool _g; /* use g spec protection, driver internal */
- s8 g_override; /* override for use of g spec protection */
- u8 gmode_user; /* user config gmode, operating band->gmode is different */
- s8 overlap; /* Overlap BSS/IBSS protection for both 11g and 11n */
- s8 nmode_user; /* user config nmode, operating pub->nmode is different */
- s8 n_cfg; /* use OFDM protection on MIMO frames */
- s8 n_cfg_override; /* override for use of N protection */
- bool nongf; /* non-GF present protection */
- s8 nongf_override; /* override for use of GF protection */
- s8 n_pam_override; /* override for preamble: MM or GF */
- bool n_obss; /* indicated OBSS Non-HT STA present */
-};
-
-/* anything affects the single/dual streams/antenna operation */
-struct wlc_stf {
- u8 hw_txchain; /* HW txchain bitmap cfg */
- u8 txchain; /* txchain bitmap being used */
- u8 txstreams; /* number of txchains being used */
-
- u8 hw_rxchain; /* HW rxchain bitmap cfg */
- u8 rxchain; /* rxchain bitmap being used */
- u8 rxstreams; /* number of rxchains being used */
-
- u8 ant_rx_ovr; /* rx antenna override */
- s8 txant; /* userTx antenna setting */
- u16 phytxant; /* phyTx antenna setting in txheader */
-
- u8 ss_opmode; /* singlestream Operational mode, 0:siso; 1:cdd */
- bool ss_algosel_auto; /* if true, use wlc->stf->ss_algo_channel; */
- /* else use wlc->band->stf->ss_mode_band; */
- u16 ss_algo_channel; /* ss based on per-channel algo: 0: SISO, 1: CDD 2: STBC */
- u8 no_cddstbc; /* stf override, 1: no CDD (or STBC) allowed */
-
- u8 rxchain_restore_delay; /* delay time to restore default rxchain */
-
- s8 ldpc; /* AUTO/ON/OFF ldpc cap supported */
- u8 txcore[MAX_STREAMS_SUPPORTED + 1]; /* bitmap of selected core for each Nsts */
- s8 spatial_policy;
-};
-
-#define WLC_STF_SS_STBC_TX(wlc, scb) \
- (((wlc)->stf->txstreams > 1) && (((wlc)->band->band_stf_stbc_tx == ON) || \
- (SCB_STBC_CAP((scb)) && \
- (wlc)->band->band_stf_stbc_tx == AUTO && \
- isset(&((wlc)->stf->ss_algo_channel), PHY_TXC1_MODE_STBC))))
-
-#define WLC_STBC_CAP_PHY(wlc) (WLCISNPHY(wlc->band) && NREV_GE(wlc->band->phyrev, 3))
-
-#define WLC_SGI_CAP_PHY(wlc) ((WLCISNPHY(wlc->band) && NREV_GE(wlc->band->phyrev, 3)) || \
- WLCISLCNPHY(wlc->band))
-
-#define WLC_CHAN_PHYTYPE(x) (((x) & RXS_CHAN_PHYTYPE_MASK) >> RXS_CHAN_PHYTYPE_SHIFT)
-#define WLC_CHAN_CHANNEL(x) (((x) & RXS_CHAN_ID_MASK) >> RXS_CHAN_ID_SHIFT)
-#define WLC_RX_CHANNEL(rxh) (WLC_CHAN_CHANNEL((rxh)->RxChan))
-
-/* wlc_bss_info flag bit values */
-#define WLC_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
-
-/* Flags used in wlc_txq_info.stopped */
-#define TXQ_STOP_FOR_PRIOFC_MASK 0x000000FF /* per prio flow control bits */
-#define TXQ_STOP_FOR_PKT_DRAIN 0x00000100 /* stop txq enqueue for packet drain */
-#define TXQ_STOP_FOR_AMPDU_FLOW_CNTRL 0x00000200 /* stop txq enqueue for ampdu flow control */
-
-#define WLC_HT_WEP_RESTRICT 0x01 /* restrict HT with WEP */
-#define WLC_HT_TKIP_RESTRICT 0x02 /* restrict HT with TKIP */
-
-/*
- * core state (mac)
- */
-struct wlccore {
- uint coreidx; /* # sb enumerated core */
-
- /* fifo */
- uint *txavail[NFIFO]; /* # tx descriptors available */
- s16 txpktpend[NFIFO]; /* tx admission control */
-
- macstat_t *macstat_snapshot; /* mac hw prev read values */
-};
-
-/*
- * band state (phy+ana+radio)
- */
-struct wlcband {
- int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */
- uint bandunit; /* bandstate[] index */
-
- u16 phytype; /* phytype */
- u16 phyrev;
- u16 radioid;
- u16 radiorev;
- wlc_phy_t *pi; /* pointer to phy specific information */
- bool abgphy_encore;
-
- u8 gmode; /* currently active gmode */
-
- struct scb *hwrs_scb; /* permanent scb for hw rateset */
-
- wlc_rateset_t defrateset; /* band-specific copy of default_bss.rateset */
-
- ratespec_t rspec_override; /* 802.11 rate override */
- ratespec_t mrspec_override; /* multicast rate override */
- u8 band_stf_ss_mode; /* Configured STF type, 0:siso; 1:cdd */
- s8 band_stf_stbc_tx; /* STBC TX 0:off; 1:force on; -1:auto */
- wlc_rateset_t hw_rateset; /* rates supported by chip (phy-specific) */
- u8 basic_rate[WLC_MAXRATE + 1]; /* basic rates indexed by rate */
- bool mimo_cap_40; /* 40 MHz cap enabled on this band */
- s8 antgain; /* antenna gain from srom */
-
- u16 CWmin; /* The minimum size of contention window, in unit of aSlotTime */
- u16 CWmax; /* The maximum size of contention window, in unit of aSlotTime */
- u16 bcntsfoff; /* beacon tsf offset */
-};
-
-/* tx completion callback takes 3 args */
-typedef void (*pkcb_fn_t) (struct wlc_info *wlc, uint txstatus, void *arg);
-
-struct pkt_cb {
- pkcb_fn_t fn; /* function to call when tx frame completes */
- void *arg; /* void arg for fn */
- u8 nextidx; /* index of next call back if threading */
- bool entered; /* recursion check */
-};
-
-/* module control blocks */
-struct modulecb {
- char name[32]; /* module name : NULL indicates empty array member */
- const struct brcmu_iovar *iovars; /* iovar table */
- void *hdl; /* handle passed when handler 'doiovar' is called */
- watchdog_fn_t watchdog_fn; /* watchdog handler */
- iovar_fn_t iovar_fn; /* iovar handler */
- down_fn_t down_fn; /* down handler. Note: the int returned
- * by the down function is a count of the
- * number of timers that could not be
- * freed.
- */
-};
-
-/* dump control blocks */
-struct dumpcb_s {
- const char *name; /* dump name */
- dump_fn_t dump_fn; /* 'wl dump' handler */
- void *dump_fn_arg;
- struct dumpcb_s *next;
-};
-
-struct edcf_acparam {
- u8 ACI;
- u8 ECW;
- u16 TXOP;
-} __attribute__((packed));
-typedef struct edcf_acparam edcf_acparam_t;
-
-struct wme_param_ie {
- u8 oui[3];
- u8 type;
- u8 subtype;
- u8 version;
- u8 qosinfo;
- u8 rsvd;
- edcf_acparam_t acparam[AC_COUNT];
-} __attribute__((packed));
-typedef struct wme_param_ie wme_param_ie_t;
-
-/* virtual interface */
-struct wlc_if {
- struct wlc_if *next;
- u8 type; /* WLC_IFTYPE_BSS or WLC_IFTYPE_WDS */
- u8 index; /* assigned in wl_add_if(), index of the wlif if any,
- * not necessarily corresponding to bsscfg._idx or
- * AID2PVBMAP(scb).
- */
- u8 flags; /* flags for the interface */
- struct brcms_if *wlif; /* pointer to wlif */
- struct wlc_txq_info *qi; /* pointer to associated tx queue */
- union {
- struct scb *scb; /* pointer to scb if WLC_IFTYPE_WDS */
- struct wlc_bsscfg *bsscfg; /* pointer to bsscfg if WLC_IFTYPE_BSS */
- } u;
-};
-
-/* flags for the interface, this interface is linked to a brcms_if */
-#define WLC_IF_LINKED 0x02
-
-struct wlc_hwband {
- int bandtype; /* WLC_BAND_2G, WLC_BAND_5G */
- uint bandunit; /* bandstate[] index */
- u16 mhfs[MHFMAX]; /* MHF array shadow */
- u8 bandhw_stf_ss_mode; /* HW configured STF type, 0:siso; 1:cdd */
- u16 CWmin;
- u16 CWmax;
- u32 core_flags;
-
- u16 phytype; /* phytype */
- u16 phyrev;
- u16 radioid;
- u16 radiorev;
- wlc_phy_t *pi; /* pointer to phy specific information */
- bool abgphy_encore;
-};
-
-struct wlc_hw_info {
- bool _piomode; /* true if pio mode */
- struct wlc_info *wlc;
-
- /* fifo */
- struct dma_pub *di[NFIFO]; /* dma handles, per fifo */
-
- uint unit; /* device instance number */
-
- /* version info */
- u16 vendorid; /* PCI vendor id */
- u16 deviceid; /* PCI device id */
- uint corerev; /* core revision */
- u8 sromrev; /* version # of the srom */
- u16 boardrev; /* version # of particular board */
- u32 boardflags; /* Board specific flags from srom */
- u32 boardflags2; /* More board flags if sromrev >= 4 */
- u32 machwcap; /* MAC capabilities */
- u32 machwcap_backup; /* backup of machwcap */
- u16 ucode_dbgsel; /* dbgsel for ucode debug(config gpio) */
-
- struct si_pub *sih; /* SI handle (cookie for siutils calls) */
- char *vars; /* "environment" name=value */
- uint vars_size; /* size of vars, free vars on detach */
- d11regs_t *regs; /* pointer to device registers */
- void *physhim; /* phy shim layer handler */
- void *phy_sh; /* pointer to shared phy state */
- struct wlc_hwband *band;/* pointer to active per-band state */
- struct wlc_hwband *bandstate[MAXBANDS];/* band state per phy/radio */
- u16 bmac_phytxant; /* cache of high phytxant state */
- bool shortslot; /* currently using 11g ShortSlot timing */
- u16 SRL; /* 802.11 dot11ShortRetryLimit */
- u16 LRL; /* 802.11 dot11LongRetryLimit */
- u16 SFBL; /* Short Frame Rate Fallback Limit */
- u16 LFBL; /* Long Frame Rate Fallback Limit */
-
- bool up; /* d11 hardware up and running */
- uint now; /* # elapsed seconds */
- uint _nbands; /* # bands supported */
- chanspec_t chanspec; /* bmac chanspec shadow */
-
- uint *txavail[NFIFO]; /* # tx descriptors available */
- u16 *xmtfifo_sz; /* fifo size in 256B for each xmt fifo */
-
- mbool pllreq; /* pll requests to keep PLL on */
-
- u8 suspended_fifos; /* Which TX fifo to remain awake for */
- u32 maccontrol; /* Cached value of maccontrol */
- uint mac_suspend_depth; /* current depth of mac_suspend levels */
- u32 wake_override; /* Various conditions to force MAC to WAKE mode */
- u32 mute_override; /* Prevent ucode from sending beacons */
- u8 etheraddr[ETH_ALEN]; /* currently configured ethernet address */
- u32 led_gpio_mask; /* LED GPIO Mask */
- bool noreset; /* true= do not reset hw, used by WLC_OUT */
- bool forcefastclk; /* true if the h/w is forcing the use of fast clk */
- bool clk; /* core is out of reset and has clock */
- bool sbclk; /* sb has clock */
- struct bmac_pmq *bmac_pmq; /* bmac PM states derived from ucode PMQ */
- bool phyclk; /* phy is out of reset and has clock */
- bool dma_lpbk; /* core is in DMA loopback */
-
- bool ucode_loaded; /* true after ucode downloaded */
-
-
- u8 hw_stf_ss_opmode; /* STF single stream operation mode */
- u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic
- * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
- */
- u32 antsel_avail; /*
- * put struct antsel_info here if more info is
- * needed
- */
-};
-
-/* TX Queue information
- *
- * Each flow of traffic out of the device has a TX Queue with independent
- * flow control. Several interfaces may be associated with a single TX Queue
- * if they belong to the same flow of traffic from the device. For multi-channel
- * operation there are independent TX Queues for each channel.
- */
-struct wlc_txq_info {
- struct wlc_txq_info *next;
- struct pktq q;
- uint stopped; /* tx flow control bits */
-};
-
-/*
- * Principal common (os-independent) software data structure.
- */
-struct wlc_info {
- struct wlc_pub *pub; /* pointer to wlc public state */
- struct brcms_info *wl; /* pointer to os-specific private state */
- d11regs_t *regs; /* pointer to device registers */
-
- struct wlc_hw_info *hw; /* HW related state used primarily by BMAC */
-
- /* clock */
- int clkreq_override; /* setting for clkreq for PCIE : Auto, 0, 1 */
- u16 fastpwrup_dly; /* time in us needed to bring up d11 fast clock */
-
- /* interrupt */
- u32 macintstatus; /* bit channel between isr and dpc */
- u32 macintmask; /* sw runtime master macintmask value */
- u32 defmacintmask; /* default "on" macintmask value */
-
- /* up and down */
- bool device_present; /* (removable) device is present */
-
- bool clk; /* core is out of reset and has clock */
-
- /* multiband */
- struct wlccore *core; /* pointer to active io core */
- struct wlcband *band; /* pointer to active per-band state */
- struct wlccore *corestate; /* per-core state (one per hw core) */
- /* per-band state (one per phy/radio): */
- struct wlcband *bandstate[MAXBANDS];
-
- bool war16165; /* PCI slow clock 16165 war flag */
-
- bool tx_suspended; /* data fifos need to remain suspended */
-
- uint txpend16165war;
-
- /* packet queue */
- uint qvalid; /* DirFrmQValid and BcMcFrmQValid */
-
- /* Regulatory power limits */
- s8 txpwr_local_max; /* regulatory local txpwr max */
- u8 txpwr_local_constraint; /* local power contraint in dB */
-
-
- struct ampdu_info *ampdu; /* ampdu module handler */
- struct antsel_info *asi; /* antsel module handler */
- wlc_cm_info_t *cmi; /* channel manager module handler */
-
- uint vars_size; /* size of vars, free vars on detach */
-
- u16 vendorid; /* PCI vendor id */
- u16 deviceid; /* PCI device id */
- uint ucode_rev; /* microcode revision */
-
- u32 machwcap; /* MAC capabilities, BMAC shadow */
-
- u8 perm_etheraddr[ETH_ALEN]; /* original sprom local ethernet address */
-
- bool bandlocked; /* disable auto multi-band switching */
- bool bandinit_pending; /* track band init in auto band */
-
- bool radio_monitor; /* radio timer is running */
- bool going_down; /* down path intermediate variable */
-
- bool mpc; /* enable minimum power consumption */
- u8 mpc_dlycnt; /* # of watchdog cnt before turn disable radio */
- u8 mpc_offcnt; /* # of watchdog cnt that radio is disabled */
- u8 mpc_delay_off; /* delay radio disable by # of watchdog cnt */
- u8 prev_non_delay_mpc; /* prev state wlc_is_non_delay_mpc */
-
- /* timer for watchdog routine */
- struct brcms_timer *wdtimer;
- /* timer for hw radio button monitor routine */
- struct brcms_timer *radio_timer;
-
- /* promiscuous */
- bool monitor; /* monitor (MPDU sniffing) mode */
- bool bcnmisc_ibss; /* bcns promisc mode override for IBSS */
- bool bcnmisc_scan; /* bcns promisc mode override for scan */
- bool bcnmisc_monitor; /* bcns promisc mode override for monitor */
-
- /* driver feature */
- bool _rifs; /* enable per-packet rifs */
- s8 sgi_tx; /* sgi tx */
-
- /* AP-STA synchronization, power save */
- u8 bcn_li_bcn; /* beacon listen interval in # beacons */
- u8 bcn_li_dtim; /* beacon listen interval in # dtims */
-
- bool WDarmed; /* watchdog timer is armed */
- u32 WDlast; /* last time wlc_watchdog() was called */
-
- /* WME */
- ac_bitmap_t wme_dp; /* Discard (oldest first) policy per AC */
- u16 edcf_txop[AC_COUNT]; /* current txop for each ac */
- wme_param_ie_t wme_param_ie; /* WME parameter info element, which on STA
- * contains parameters in use locally, and on
- * AP contains parameters advertised to STA
- * in beacons and assoc responses.
- */
- u16 wme_retries[AC_COUNT]; /* per-AC retry limits */
-
- u16 tx_prec_map; /* Precedence map based on HW FIFO space */
- u16 fifo2prec_map[NFIFO]; /* pointer to fifo2_prec map based on WME */
-
- /*
- * BSS Configurations set of BSS configurations, idx 0 is default and
- * always valid
- */
- struct wlc_bsscfg *bsscfg[WLC_MAXBSSCFG];
- struct wlc_bsscfg *cfg; /* the primary bsscfg (can be AP or STA) */
-
- /* tx queue */
- struct wlc_txq_info *tx_queues; /* common TX Queue list */
-
- /* security */
- wsec_key_t *wsec_keys[WSEC_MAX_KEYS]; /* dynamic key storage */
- wsec_key_t *wsec_def_keys[WLC_DEFAULT_KEYS]; /* default key storage */
- bool wsec_swkeys; /* indicates that all keys should be
- * treated as sw keys (used for debugging)
- */
- struct modulecb *modulecb;
-
- u8 mimoft; /* SIGN or 11N */
- s8 cck_40txbw; /* 11N, cck tx b/w override when in 40MHZ mode */
- s8 ofdm_40txbw; /* 11N, ofdm tx b/w override when in 40MHZ mode */
- s8 mimo_40txbw; /* 11N, mimo tx b/w override when in 40MHZ mode */
- /* HT CAP IE being advertised by this node: */
- struct ieee80211_ht_cap ht_cap;
-
- wlc_bss_info_t *default_bss; /* configured BSS parameters */
-
- u16 mc_fid_counter; /* BC/MC FIFO frame ID counter */
-
- char country_default[WLC_CNTRY_BUF_SZ]; /* saved country for leaving 802.11d
- * auto-country mode
- */
- char autocountry_default[WLC_CNTRY_BUF_SZ]; /* initial country for 802.11d
- * auto-country mode
- */
- u16 prb_resp_timeout; /* do not send prb resp if request older than this,
- * 0 = disable
- */
-
- wlc_rateset_t sup_rates_override; /* use only these rates in 11g supported rates if
- * specifed
- */
-
- chanspec_t home_chanspec; /* shared home chanspec */
-
- /* PHY parameters */
- chanspec_t chanspec; /* target operational channel */
- u16 usr_fragthresh; /* user configured fragmentation threshold */
- u16 fragthresh[NFIFO]; /* per-fifo fragmentation thresholds */
- u16 RTSThresh; /* 802.11 dot11RTSThreshold */
- u16 SRL; /* 802.11 dot11ShortRetryLimit */
- u16 LRL; /* 802.11 dot11LongRetryLimit */
- u16 SFBL; /* Short Frame Rate Fallback Limit */
- u16 LFBL; /* Long Frame Rate Fallback Limit */
-
- /* network config */
- bool shortslot; /* currently using 11g ShortSlot timing */
- s8 shortslot_override; /* 11g ShortSlot override */
- bool include_legacy_erp; /* include Legacy ERP info elt ID 47 as well as g ID 42 */
-
- struct wlc_protection *protection;
- s8 PLCPHdr_override; /* 802.11b Preamble Type override */
-
- struct wlc_stf *stf;
-
- ratespec_t bcn_rspec; /* save bcn ratespec purpose */
-
- uint tempsense_lasttime;
-
- u16 tx_duty_cycle_ofdm; /* maximum allowed duty cycle for OFDM */
- u16 tx_duty_cycle_cck; /* maximum allowed duty cycle for CCK */
-
- u16 next_bsscfg_ID;
-
- struct wlc_txq_info *pkt_queue; /* txq for transmit packets */
- u32 mpc_dur; /* total time (ms) in mpc mode except for the
- * portion since radio is turned off last time
- */
- u32 mpc_laston_ts; /* timestamp (ms) when radio is turned off last
- * time
- */
- struct wiphy *wiphy;
-};
-
-/* antsel module specific state */
-struct antsel_info {
- struct wlc_info *wlc; /* pointer to main wlc structure */
- struct wlc_pub *pub; /* pointer to public fn */
- u8 antsel_type; /* Type of boardlevel mimo antenna switch-logic
- * 0 = N/A, 1 = 2x4 board, 2 = 2x3 CB2 board
- */
- u8 antsel_antswitch; /* board level antenna switch type */
- bool antsel_avail; /* Ant selection availability (SROM based) */
- wlc_antselcfg_t antcfg_11n; /* antenna configuration */
- wlc_antselcfg_t antcfg_cur; /* current antenna config (auto) */
-};
-
-#define CHANNEL_BANDUNIT(wlc, ch) (((ch) <= CH_MAX_2G_CHANNEL) ? BAND_2G_INDEX : BAND_5G_INDEX)
-#define OTHERBANDUNIT(wlc) ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
-
-#define IS_MBAND_UNLOCKED(wlc) \
- ((NBANDS(wlc) > 1) && !(wlc)->bandlocked)
-
-#define WLC_BAND_PI_RADIO_CHANSPEC wlc_phy_chanspec_get(wlc->band->pi)
-
-/* sum the individual fifo tx pending packet counts */
-#define TXPKTPENDTOT(wlc) ((wlc)->core->txpktpend[0] + (wlc)->core->txpktpend[1] + \
- (wlc)->core->txpktpend[2] + (wlc)->core->txpktpend[3])
-#define TXPKTPENDGET(wlc, fifo) ((wlc)->core->txpktpend[(fifo)])
-#define TXPKTPENDINC(wlc, fifo, val) ((wlc)->core->txpktpend[(fifo)] += (val))
-#define TXPKTPENDDEC(wlc, fifo, val) ((wlc)->core->txpktpend[(fifo)] -= (val))
-#define TXPKTPENDCLR(wlc, fifo) ((wlc)->core->txpktpend[(fifo)] = 0)
-#define TXAVAIL(wlc, fifo) (*(wlc)->core->txavail[(fifo)])
-#define GETNEXTTXP(wlc, _queue) \
- dma_getnexttxp((wlc)->hw->di[(_queue)], DMA_RANGE_TRANSMITTED)
-
-#define WLC_IS_MATCH_SSID(wlc, ssid1, ssid2, len1, len2) \
- ((len1 == len2) && !memcmp(ssid1, ssid2, len1))
-
-extern void wlc_fatal_error(struct wlc_info *wlc);
-extern void wlc_bmac_rpc_watchdog(struct wlc_info *wlc);
-extern void wlc_recv(struct wlc_info *wlc, struct sk_buff *p);
-extern bool wlc_dotxstatus(struct wlc_info *wlc, tx_status_t *txs, u32 frm_tx2);
-extern void wlc_txfifo(struct wlc_info *wlc, uint fifo, struct sk_buff *p,
- bool commit, s8 txpktpend);
-extern void wlc_txfifo_complete(struct wlc_info *wlc, uint fifo, s8 txpktpend);
-extern void wlc_txq_enq(void *ctx, struct scb *scb, struct sk_buff *sdu,
- uint prec);
-extern void wlc_info_init(struct wlc_info *wlc, int unit);
-extern void wlc_print_txstatus(tx_status_t *txs);
-extern int wlc_xmtfifo_sz_get(struct wlc_info *wlc, uint fifo, uint *blocks);
-extern void wlc_write_template_ram(struct wlc_info *wlc, int offset, int len,
- void *buf);
-extern void wlc_write_hw_bcntemplates(struct wlc_info *wlc, void *bcn, int len,
- bool both);
-extern void wlc_pllreq(struct wlc_info *wlc, bool set, mbool req_bit);
-extern void wlc_reset_bmac_done(struct wlc_info *wlc);
-
-#if defined(BCMDBG)
-extern void wlc_print_rxh(d11rxhdr_t *rxh);
-extern void wlc_print_hdrs(struct wlc_info *wlc, const char *prefix, u8 *frame,
- d11txh_t *txh, d11rxhdr_t *rxh, uint len);
-extern void wlc_print_txdesc(d11txh_t *txh);
-#else
-#define wlc_print_txdesc(a)
-#endif
-#if defined(BCMDBG)
-extern void wlc_print_dot11_mac_hdr(u8 *buf, int len);
-#endif
-
-extern void wlc_setxband(struct wlc_hw_info *wlc_hw, uint bandunit);
-extern void wlc_coredisable(struct wlc_hw_info *wlc_hw);
-
-extern bool wlc_valid_rate(struct wlc_info *wlc, ratespec_t rate, int band,
- bool verbose);
-extern void wlc_ap_upd(struct wlc_info *wlc);
-
-/* helper functions */
-extern void wlc_shm_ssid_upd(struct wlc_info *wlc, struct wlc_bsscfg *cfg);
-extern int wlc_set_gmode(struct wlc_info *wlc, u8 gmode, bool config);
-
-extern void wlc_mac_bcn_promisc_change(struct wlc_info *wlc, bool promisc);
-extern void wlc_mac_bcn_promisc(struct wlc_info *wlc);
-extern void wlc_mac_promisc(struct wlc_info *wlc);
-extern void wlc_txflowcontrol(struct wlc_info *wlc, struct wlc_txq_info *qi,
- bool on, int prio);
-extern void wlc_txflowcontrol_override(struct wlc_info *wlc,
- struct wlc_txq_info *qi,
- bool on, uint override);
-extern bool wlc_txflowcontrol_prio_isset(struct wlc_info *wlc,
- struct wlc_txq_info *qi, int prio);
-extern void wlc_send_q(struct wlc_info *wlc);
-extern int wlc_prep_pdu(struct wlc_info *wlc, struct sk_buff *pdu, uint *fifo);
-
-extern u16 wlc_calc_lsig_len(struct wlc_info *wlc, ratespec_t ratespec,
- uint mac_len);
-extern ratespec_t wlc_rspec_to_rts_rspec(struct wlc_info *wlc, ratespec_t rspec,
- bool use_rspec, u16 mimo_ctlchbw);
-extern u16 wlc_compute_rtscts_dur(struct wlc_info *wlc, bool cts_only,
- ratespec_t rts_rate, ratespec_t frame_rate,
- u8 rts_preamble_type,
- u8 frame_preamble_type, uint frame_len,
- bool ba);
-
-extern void wlc_tbtt(struct wlc_info *wlc, d11regs_t *regs);
-extern void wlc_inval_dma_pkts(struct wlc_hw_info *hw,
- struct ieee80211_sta *sta,
- void (*dma_callback_fn));
-
-#if defined(BCMDBG)
-extern void wlc_dump_ie(struct wlc_info *wlc, struct brcmu_tlv *ie,
- struct brcmu_strbuf *b);
-#endif
-
-extern void wlc_reprate_init(struct wlc_info *wlc);
-extern void wlc_bsscfg_reprate_init(struct wlc_bsscfg *bsscfg);
-
-/* Shared memory access */
-extern void wlc_write_shm(struct wlc_info *wlc, uint offset, u16 v);
-extern u16 wlc_read_shm(struct wlc_info *wlc, uint offset);
-extern void wlc_copyto_shm(struct wlc_info *wlc, uint offset, const void *buf,
- int len);
-
-extern void wlc_update_beacon(struct wlc_info *wlc);
-extern void wlc_bss_update_beacon(struct wlc_info *wlc,
- struct wlc_bsscfg *bsscfg);
-
-extern void wlc_update_probe_resp(struct wlc_info *wlc, bool suspend);
-extern void wlc_bss_update_probe_resp(struct wlc_info *wlc,
- struct wlc_bsscfg *cfg, bool suspend);
-
-extern bool wlc_ismpc(struct wlc_info *wlc);
-extern bool wlc_is_non_delay_mpc(struct wlc_info *wlc);
-extern void wlc_radio_mpc_upd(struct wlc_info *wlc);
-extern bool wlc_prec_enq(struct wlc_info *wlc, struct pktq *q, void *pkt,
- int prec);
-extern bool wlc_prec_enq_head(struct wlc_info *wlc, struct pktq *q,
- struct sk_buff *pkt, int prec, bool head);
-extern u16 wlc_phytxctl1_calc(struct wlc_info *wlc, ratespec_t rspec);
-extern void wlc_compute_plcp(struct wlc_info *wlc, ratespec_t rate, uint length,
- u8 *plcp);
-extern uint wlc_calc_frame_time(struct wlc_info *wlc, ratespec_t ratespec,
- u8 preamble_type, uint mac_len);
-
-extern void wlc_set_chanspec(struct wlc_info *wlc, chanspec_t chanspec);
-
-extern bool wlc_timers_init(struct wlc_info *wlc, int unit);
-
-#if defined(BCMDBG)
-extern void wlc_print_ies(struct wlc_info *wlc, u8 *ies, uint ies_len);
-#endif
-
-extern int wlc_set_nmode(struct wlc_info *wlc, s32 nmode);
-extern void wlc_mimops_action_ht_send(struct wlc_info *wlc,
- struct wlc_bsscfg *bsscfg,
- u8 mimops_mode);
-
-extern void wlc_switch_shortslot(struct wlc_info *wlc, bool shortslot);
-extern void wlc_set_bssid(struct wlc_bsscfg *cfg);
-extern void wlc_edcf_setparams(struct wlc_info *wlc, bool suspend);
-
-extern void wlc_set_ratetable(struct wlc_info *wlc);
-extern int wlc_set_mac(struct wlc_bsscfg *cfg);
-extern void wlc_beacon_phytxctl_txant_upd(struct wlc_info *wlc,
- ratespec_t bcn_rate);
-extern void wlc_mod_prb_rsp_rate_table(struct wlc_info *wlc, uint frame_len);
-extern ratespec_t wlc_lowest_basic_rspec(struct wlc_info *wlc,
- wlc_rateset_t *rs);
-extern void wlc_radio_disable(struct wlc_info *wlc);
-extern void wlc_bcn_li_upd(struct wlc_info *wlc);
-extern void wlc_set_home_chanspec(struct wlc_info *wlc, chanspec_t chanspec);
-extern bool wlc_ps_allowed(struct wlc_info *wlc);
-extern bool wlc_stay_awake(struct wlc_info *wlc);
-extern void wlc_wme_initparams_sta(struct wlc_info *wlc, wme_param_ie_t *pe);
-
-#endif /* _BRCM_MAIN_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * This is "two-way" interface, acting as the SHIM layer between WL and PHY layer.
- * WL driver can optinally call this translation layer to do some preprocessing, then reach PHY.
- * On the PHY->WL driver direction, all calls go through this layer since PHY doesn't have the
- * access to wlc_hw pointer.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <bcmdefs.h>
-#include <brcmu_utils.h>
-#include <brcmu_wifi.h>
-#include <aiutils.h>
-#include <chipcommon.h>
-#include "bcmdma.h"
-#include <wlc_pmu.h>
-
-#include "wlc_types.h"
-#include "wlc_cfg.h"
-#include "d11.h"
-#include "wlc_rate.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "phy/wlc_phy_hal.h"
-#include "wlc_channel.h"
-#include "bcmsrom.h"
-#include "wlc_key.h"
-#include "wlc_bmac.h"
-#include "wlc_phy_hal.h"
-#include "wlc_main.h"
-#include "wlc_phy_shim.h"
-#include "brcms_mac80211.h"
-
-/* PHY SHIM module specific state */
-struct wlc_phy_shim_info {
- struct wlc_hw_info *wlc_hw; /* pointer to main wlc_hw structure */
- void *wlc; /* pointer to main wlc structure */
- void *wl; /* pointer to os-specific private state */
-};
-
-wlc_phy_shim_info_t *wlc_phy_shim_attach(struct wlc_hw_info *wlc_hw,
- void *wl, void *wlc) {
- wlc_phy_shim_info_t *physhim = NULL;
-
- physhim = kzalloc(sizeof(wlc_phy_shim_info_t), GFP_ATOMIC);
- if (!physhim) {
- wiphy_err(wlc_hw->wlc->wiphy,
- "wl%d: wlc_phy_shim_attach: out of mem\n",
- wlc_hw->unit);
- return NULL;
- }
- physhim->wlc_hw = wlc_hw;
- physhim->wlc = wlc;
- physhim->wl = wl;
-
- return physhim;
-}
-
-void wlc_phy_shim_detach(wlc_phy_shim_info_t *physhim)
-{
- kfree(physhim);
-}
-
-struct wlapi_timer *wlapi_init_timer(wlc_phy_shim_info_t *physhim,
- void (*fn) (void *arg), void *arg,
- const char *name)
-{
- return (struct wlapi_timer *)
- brcms_init_timer(physhim->wl, fn, arg, name);
-}
-
-void wlapi_free_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t)
-{
- brcms_free_timer(physhim->wl, (struct brcms_timer *)t);
-}
-
-void
-wlapi_add_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t, uint ms,
- int periodic)
-{
- brcms_add_timer(physhim->wl, (struct brcms_timer *)t, ms, periodic);
-}
-
-bool wlapi_del_timer(wlc_phy_shim_info_t *physhim, struct wlapi_timer *t)
-{
- return brcms_del_timer(physhim->wl, (struct brcms_timer *)t);
-}
-
-void wlapi_intrson(wlc_phy_shim_info_t *physhim)
-{
- brcms_intrson(physhim->wl);
-}
-
-u32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim)
-{
- return brcms_intrsoff(physhim->wl);
-}
-
-void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim, u32 macintmask)
-{
- brcms_intrsrestore(physhim->wl, macintmask);
-}
-
-void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset, u16 v)
-{
- wlc_bmac_write_shm(physhim->wlc_hw, offset, v);
-}
-
-u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset)
-{
- return wlc_bmac_read_shm(physhim->wlc_hw, offset);
-}
-
-void
-wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx, u16 mask,
- u16 val, int bands)
-{
- wlc_bmac_mhf(physhim->wlc_hw, idx, mask, val, bands);
-}
-
-void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, u32 flags)
-{
- wlc_bmac_corereset(physhim->wlc_hw, flags);
-}
-
-void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim)
-{
- wlc_suspend_mac_and_wait(physhim->wlc);
-}
-
-void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode)
-{
- wlc_bmac_switch_macfreq(physhim->wlc_hw, spurmode);
-}
-
-void wlapi_enable_mac(wlc_phy_shim_info_t *physhim)
-{
- wlc_enable_mac(physhim->wlc);
-}
-
-void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, u32 mask, u32 val)
-{
- wlc_bmac_mctrl(physhim->wlc_hw, mask, val);
-}
-
-void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim)
-{
- wlc_bmac_phy_reset(physhim->wlc_hw);
-}
-
-void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw)
-{
- wlc_bmac_bw_set(physhim->wlc_hw, bw);
-}
-
-u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim)
-{
- return wlc_bmac_get_txant(physhim->wlc_hw);
-}
-
-void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk)
-{
- wlc_bmac_phyclk_fgc(physhim->wlc_hw, clk);
-}
-
-void wlapi_bmac_macphyclk_set(wlc_phy_shim_info_t *physhim, bool clk)
-{
- wlc_bmac_macphyclk_set(physhim->wlc_hw, clk);
-}
-
-void wlapi_bmac_core_phypll_ctl(wlc_phy_shim_info_t *physhim, bool on)
-{
- wlc_bmac_core_phypll_ctl(physhim->wlc_hw, on);
-}
-
-void wlapi_bmac_core_phypll_reset(wlc_phy_shim_info_t *physhim)
-{
- wlc_bmac_core_phypll_reset(physhim->wlc_hw);
-}
-
-void wlapi_bmac_ucode_wake_override_phyreg_set(wlc_phy_shim_info_t *physhim)
-{
- wlc_ucode_wake_override_set(physhim->wlc_hw, WLC_WAKE_OVERRIDE_PHYREG);
-}
-
-void wlapi_bmac_ucode_wake_override_phyreg_clear(wlc_phy_shim_info_t *physhim)
-{
- wlc_ucode_wake_override_clear(physhim->wlc_hw,
- WLC_WAKE_OVERRIDE_PHYREG);
-}
-
-void
-wlapi_bmac_write_template_ram(wlc_phy_shim_info_t *physhim, int offset,
- int len, void *buf)
-{
- wlc_bmac_write_template_ram(physhim->wlc_hw, offset, len, buf);
-}
-
-u16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim, u8 rate)
-{
- return wlc_bmac_rate_shm_offset(physhim->wlc_hw, rate);
-}
-
-void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim)
-{
-}
-
-void
-wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint offset, void *buf,
- int len, u32 sel)
-{
- wlc_bmac_copyfrom_objmem(physhim->wlc_hw, offset, buf, len, sel);
-}
-
-void
-wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint offset, const void *buf,
- int l, u32 sel)
-{
- wlc_bmac_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-/*
- * phy_shim.h: stuff defined in phy_shim.c and included only by the phy
- */
-
-#ifndef _BRCM_PHY_SHIM_H_
-#define _BRCM_PHY_SHIM_H_
-
-#define RADAR_TYPE_NONE 0 /* Radar type None */
-#define RADAR_TYPE_ETSI_1 1 /* ETSI 1 Radar type */
-#define RADAR_TYPE_ETSI_2 2 /* ETSI 2 Radar type */
-#define RADAR_TYPE_ETSI_3 3 /* ETSI 3 Radar type */
-#define RADAR_TYPE_ITU_E 4 /* ITU E Radar type */
-#define RADAR_TYPE_ITU_K 5 /* ITU K Radar type */
-#define RADAR_TYPE_UNCLASSIFIED 6 /* Unclassified Radar type */
-#define RADAR_TYPE_BIN5 7 /* long pulse radar type */
-#define RADAR_TYPE_STG2 8 /* staggered-2 radar */
-#define RADAR_TYPE_STG3 9 /* staggered-3 radar */
-#define RADAR_TYPE_FRA 10 /* French radar */
-
-/* French radar pulse widths */
-#define FRA_T1_20MHZ 52770
-#define FRA_T2_20MHZ 61538
-#define FRA_T3_20MHZ 66002
-#define FRA_T1_40MHZ 105541
-#define FRA_T2_40MHZ 123077
-#define FRA_T3_40MHZ 132004
-#define FRA_ERR_20MHZ 60
-#define FRA_ERR_40MHZ 120
-
-#define ANTSEL_NA 0 /* No boardlevel selection available */
-#define ANTSEL_2x4 1 /* 2x4 boardlevel selection available */
-#define ANTSEL_2x3 2 /* 2x3 CB2 boardlevel selection available */
-
-/* Rx Antenna diversity control values */
-#define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
-#define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
-#define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
-#define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */
-#define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
-#define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */
-
-#define WL_ANT_RX_MAX 2 /* max 2 receive antennas */
-#define WL_ANT_HT_RX_MAX 3 /* max 3 receive antennas/cores */
-#define WL_ANT_IDX_1 0 /* antenna index 1 */
-#define WL_ANT_IDX_2 1 /* antenna index 2 */
-
-/* values for n_preamble_type */
-#define WLC_N_PREAMBLE_MIXEDMODE 0
-#define WLC_N_PREAMBLE_GF 1
-#define WLC_N_PREAMBLE_GF_BRCM 2
-
-#define WL_TX_POWER_RATES_LEGACY 45
-#define WL_TX_POWER_MCS20_FIRST 12
-#define WL_TX_POWER_MCS20_NUM 16
-#define WL_TX_POWER_MCS40_FIRST 28
-#define WL_TX_POWER_MCS40_NUM 17
-
-
-#define WL_TX_POWER_RATES 101
-#define WL_TX_POWER_CCK_FIRST 0
-#define WL_TX_POWER_CCK_NUM 4
-#define WL_TX_POWER_OFDM_FIRST 4 /* Index for first 20MHz OFDM SISO rate */
-#define WL_TX_POWER_OFDM20_CDD_FIRST 12 /* Index for first 20MHz OFDM CDD rate */
-#define WL_TX_POWER_OFDM40_SISO_FIRST 52 /* Index for first 40MHz OFDM SISO rate */
-#define WL_TX_POWER_OFDM40_CDD_FIRST 60 /* Index for first 40MHz OFDM CDD rate */
-#define WL_TX_POWER_OFDM_NUM 8
-#define WL_TX_POWER_MCS20_SISO_FIRST 20 /* Index for first 20MHz MCS SISO rate */
-#define WL_TX_POWER_MCS20_CDD_FIRST 28 /* Index for first 20MHz MCS CDD rate */
-#define WL_TX_POWER_MCS20_STBC_FIRST 36 /* Index for first 20MHz MCS STBC rate */
-#define WL_TX_POWER_MCS20_SDM_FIRST 44 /* Index for first 20MHz MCS SDM rate */
-#define WL_TX_POWER_MCS40_SISO_FIRST 68 /* Index for first 40MHz MCS SISO rate */
-#define WL_TX_POWER_MCS40_CDD_FIRST 76 /* Index for first 40MHz MCS CDD rate */
-#define WL_TX_POWER_MCS40_STBC_FIRST 84 /* Index for first 40MHz MCS STBC rate */
-#define WL_TX_POWER_MCS40_SDM_FIRST 92 /* Index for first 40MHz MCS SDM rate */
-#define WL_TX_POWER_MCS_1_STREAM_NUM 8
-#define WL_TX_POWER_MCS_2_STREAM_NUM 8
-#define WL_TX_POWER_MCS_32 100 /* Index for 40MHz rate MCS 32 */
-#define WL_TX_POWER_MCS_32_NUM 1
-
-/* sslpnphy specifics */
-#define WL_TX_POWER_MCS20_SISO_FIRST_SSN 12 /* Index for first 20MHz MCS SISO rate */
-
-/* tx_power_t.flags bits */
-#define WL_TX_POWER_F_ENABLED 1
-#define WL_TX_POWER_F_HW 2
-#define WL_TX_POWER_F_MIMO 4
-#define WL_TX_POWER_F_SISO 8
-
-/* values to force tx/rx chain */
-#define WLC_N_TXRX_CHAIN0 0
-#define WLC_N_TXRX_CHAIN1 1
-
-/* Forward declarations */
-struct wlc_hw_info;
-typedef struct wlc_phy_shim_info wlc_phy_shim_info_t;
-
-extern wlc_phy_shim_info_t *wlc_phy_shim_attach(struct wlc_hw_info *wlc_hw,
- void *wl, void *wlc);
-extern void wlc_phy_shim_detach(wlc_phy_shim_info_t *physhim);
-
-/* PHY to WL utility functions */
-struct wlapi_timer;
-extern struct wlapi_timer *wlapi_init_timer(wlc_phy_shim_info_t *physhim,
- void (*fn) (void *arg), void *arg,
- const char *name);
-extern void wlapi_free_timer(wlc_phy_shim_info_t *physhim,
- struct wlapi_timer *t);
-extern void wlapi_add_timer(wlc_phy_shim_info_t *physhim,
- struct wlapi_timer *t, uint ms, int periodic);
-extern bool wlapi_del_timer(wlc_phy_shim_info_t *physhim,
- struct wlapi_timer *t);
-extern void wlapi_intrson(wlc_phy_shim_info_t *physhim);
-extern u32 wlapi_intrsoff(wlc_phy_shim_info_t *physhim);
-extern void wlapi_intrsrestore(wlc_phy_shim_info_t *physhim,
- u32 macintmask);
-
-extern void wlapi_bmac_write_shm(wlc_phy_shim_info_t *physhim, uint offset,
- u16 v);
-extern u16 wlapi_bmac_read_shm(wlc_phy_shim_info_t *physhim, uint offset);
-extern void wlapi_bmac_mhf(wlc_phy_shim_info_t *physhim, u8 idx,
- u16 mask, u16 val, int bands);
-extern void wlapi_bmac_corereset(wlc_phy_shim_info_t *physhim, u32 flags);
-extern void wlapi_suspend_mac_and_wait(wlc_phy_shim_info_t *physhim);
-extern void wlapi_switch_macfreq(wlc_phy_shim_info_t *physhim, u8 spurmode);
-extern void wlapi_enable_mac(wlc_phy_shim_info_t *physhim);
-extern void wlapi_bmac_mctrl(wlc_phy_shim_info_t *physhim, u32 mask,
- u32 val);
-extern void wlapi_bmac_phy_reset(wlc_phy_shim_info_t *physhim);
-extern void wlapi_bmac_bw_set(wlc_phy_shim_info_t *physhim, u16 bw);
-extern void wlapi_bmac_phyclk_fgc(wlc_phy_shim_info_t *physhim, bool clk);
-extern void wlapi_bmac_macphyclk_set(wlc_phy_shim_info_t *physhim, bool clk);
-extern void wlapi_bmac_core_phypll_ctl(wlc_phy_shim_info_t *physhim, bool on);
-extern void wlapi_bmac_core_phypll_reset(wlc_phy_shim_info_t *physhim);
-extern void wlapi_bmac_ucode_wake_override_phyreg_set(wlc_phy_shim_info_t *
- physhim);
-extern void wlapi_bmac_ucode_wake_override_phyreg_clear(wlc_phy_shim_info_t *
- physhim);
-extern void wlapi_bmac_write_template_ram(wlc_phy_shim_info_t *physhim, int o,
- int len, void *buf);
-extern u16 wlapi_bmac_rate_shm_offset(wlc_phy_shim_info_t *physhim,
- u8 rate);
-extern void wlapi_ucode_sample_init(wlc_phy_shim_info_t *physhim);
-extern void wlapi_copyfrom_objmem(wlc_phy_shim_info_t *physhim, uint,
- void *buf, int, u32 sel);
-extern void wlapi_copyto_objmem(wlc_phy_shim_info_t *physhim, uint,
- const void *buf, int, u32);
-
-extern void wlapi_high_update_phy_mode(wlc_phy_shim_info_t *physhim,
- u32 phy_mode);
-extern u16 wlapi_bmac_get_txant(wlc_phy_shim_info_t *physhim);
-#endif /* _BRCM_PHY_SHIM_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2011 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-
-#include <bcmdevs.h>
-#include "wlc_types.h"
-#include <chipcommon.h>
-#include <brcmu_utils.h>
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "wlc_pmu.h"
-
-/*
- * d11 slow to fast clock transition time in slow clock cycles
- */
-#define D11SCC_SLOW2FAST_TRANSITION 2
-
-/*
- * external LPO crystal frequency
- */
-#define EXT_ILP_HZ 32768
-
-/*
- * Duration for ILP clock frequency measurment in milliseconds
- *
- * remark: 1000 must be an integer multiple of this duration
- */
-#define ILP_CALC_DUR 10
-
-/*
- * FVCO frequency
- */
-#define FVCO_880 880000 /* 880MHz */
-#define FVCO_1760 1760000 /* 1760MHz */
-#define FVCO_1440 1440000 /* 1440MHz */
-#define FVCO_960 960000 /* 960MHz */
-
-/*
- * PMU crystal table indices for 1440MHz fvco
- */
-#define PMU1_XTALTAB0_1440_12000K 0
-#define PMU1_XTALTAB0_1440_13000K 1
-#define PMU1_XTALTAB0_1440_14400K 2
-#define PMU1_XTALTAB0_1440_15360K 3
-#define PMU1_XTALTAB0_1440_16200K 4
-#define PMU1_XTALTAB0_1440_16800K 5
-#define PMU1_XTALTAB0_1440_19200K 6
-#define PMU1_XTALTAB0_1440_19800K 7
-#define PMU1_XTALTAB0_1440_20000K 8
-#define PMU1_XTALTAB0_1440_25000K 9
-#define PMU1_XTALTAB0_1440_26000K 10
-#define PMU1_XTALTAB0_1440_30000K 11
-#define PMU1_XTALTAB0_1440_37400K 12
-#define PMU1_XTALTAB0_1440_38400K 13
-#define PMU1_XTALTAB0_1440_40000K 14
-#define PMU1_XTALTAB0_1440_48000K 15
-
-/*
- * PMU crystal table indices for 960MHz fvco
- */
-#define PMU1_XTALTAB0_960_12000K 0
-#define PMU1_XTALTAB0_960_13000K 1
-#define PMU1_XTALTAB0_960_14400K 2
-#define PMU1_XTALTAB0_960_15360K 3
-#define PMU1_XTALTAB0_960_16200K 4
-#define PMU1_XTALTAB0_960_16800K 5
-#define PMU1_XTALTAB0_960_19200K 6
-#define PMU1_XTALTAB0_960_19800K 7
-#define PMU1_XTALTAB0_960_20000K 8
-#define PMU1_XTALTAB0_960_25000K 9
-#define PMU1_XTALTAB0_960_26000K 10
-#define PMU1_XTALTAB0_960_30000K 11
-#define PMU1_XTALTAB0_960_37400K 12
-#define PMU1_XTALTAB0_960_38400K 13
-#define PMU1_XTALTAB0_960_40000K 14
-#define PMU1_XTALTAB0_960_48000K 15
-
-/*
- * PMU crystal table indices for 880MHz fvco
- */
-#define PMU1_XTALTAB0_880_12000K 0
-#define PMU1_XTALTAB0_880_13000K 1
-#define PMU1_XTALTAB0_880_14400K 2
-#define PMU1_XTALTAB0_880_15360K 3
-#define PMU1_XTALTAB0_880_16200K 4
-#define PMU1_XTALTAB0_880_16800K 5
-#define PMU1_XTALTAB0_880_19200K 6
-#define PMU1_XTALTAB0_880_19800K 7
-#define PMU1_XTALTAB0_880_20000K 8
-#define PMU1_XTALTAB0_880_24000K 9
-#define PMU1_XTALTAB0_880_25000K 10
-#define PMU1_XTALTAB0_880_26000K 11
-#define PMU1_XTALTAB0_880_30000K 12
-#define PMU1_XTALTAB0_880_37400K 13
-#define PMU1_XTALTAB0_880_38400K 14
-#define PMU1_XTALTAB0_880_40000K 15
-
-/*
- * crystal frequency values
- */
-#define XTAL_FREQ_24000MHZ 24000
-#define XTAL_FREQ_30000MHZ 30000
-#define XTAL_FREQ_37400MHZ 37400
-#define XTAL_FREQ_48000MHZ 48000
-
-/*
- * Resource dependancies mask change action
- *
- * @RES_DEPEND_SET: Override the dependancies mask
- * @RES_DEPEND_ADD: Add to the dependancies mask
- * @RES_DEPEND_REMOVE: Remove from the dependancies mask
- */
-#define RES_DEPEND_SET 0
-#define RES_DEPEND_ADD 1
-#define RES_DEPEND_REMOVE -1
-
-/* Fields in pmucontrol */
-#define PCTL_ILP_DIV_MASK 0xffff0000
-#define PCTL_ILP_DIV_SHIFT 16
-#define PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */
-#define PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */
-#define PCTL_HT_REQ_EN 0x00000100
-#define PCTL_ALP_REQ_EN 0x00000080
-#define PCTL_XTALFREQ_MASK 0x0000007c
-#define PCTL_XTALFREQ_SHIFT 2
-#define PCTL_ILP_DIV_EN 0x00000002
-#define PCTL_LPO_SEL 0x00000001
-
-/* Fields in clkstretch */
-#define CSTRETCH_HT 0xffff0000
-#define CSTRETCH_ALP 0x0000ffff
-
-/* d11 slow to fast clock transition time in slow clock cycles */
-#define D11SCC_SLOW2FAST_TRANSITION 2
-
-/* ILP clock */
-#define ILP_CLOCK 32000
-
-/* ALP clock on pre-PMU chips */
-#define ALP_CLOCK 20000000
-
-/* HT clock */
-#define HT_CLOCK 80000000
-
-#define OTPS_READY 0x00001000
-
-/* pmustatus */
-#define PST_EXTLPOAVAIL 0x0100
-#define PST_WDRESET 0x0080
-#define PST_INTPEND 0x0040
-#define PST_SBCLKST 0x0030
-#define PST_SBCLKST_ILP 0x0010
-#define PST_SBCLKST_ALP 0x0020
-#define PST_SBCLKST_HT 0x0030
-#define PST_ALPAVAIL 0x0008
-#define PST_HTAVAIL 0x0004
-#define PST_RESINIT 0x0003
-
-/* PMU Resource Request Timer registers */
-/* This is based on PmuRev0 */
-#define PRRT_TIME_MASK 0x03ff
-#define PRRT_INTEN 0x0400
-#define PRRT_REQ_ACTIVE 0x0800
-#define PRRT_ALP_REQ 0x1000
-#define PRRT_HT_REQ 0x2000
-
-/* PMU resource bit position */
-#define PMURES_BIT(bit) (1 << (bit))
-
-/* PMU resource number limit */
-#define PMURES_MAX_RESNUM 30
-
-/* PMU chip control0 register */
-#define PMU_CHIPCTL0 0
-
-/* PMU chip control1 register */
-#define PMU_CHIPCTL1 1
-#define PMU_CC1_RXC_DLL_BYPASS 0x00010000
-
-#define PMU_CC1_IF_TYPE_MASK 0x00000030
-#define PMU_CC1_IF_TYPE_RMII 0x00000000
-#define PMU_CC1_IF_TYPE_MII 0x00000010
-#define PMU_CC1_IF_TYPE_RGMII 0x00000020
-
-#define PMU_CC1_SW_TYPE_MASK 0x000000c0
-#define PMU_CC1_SW_TYPE_EPHY 0x00000000
-#define PMU_CC1_SW_TYPE_EPHYMII 0x00000040
-#define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080
-#define PMU_CC1_SW_TYPE_RGMII 0x000000c0
-
-/* PMU corerev and chip specific PLL controls.
- * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number
- * to differentiate different PLLs controlled by the same PMU rev.
- */
-/* pllcontrol registers */
-/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
-#define PMU0_PLL0_PLLCTL0 0
-#define PMU0_PLL0_PC0_PDIV_MASK 1
-#define PMU0_PLL0_PC0_PDIV_FREQ 25000
-#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
-#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
-#define PMU0_PLL0_PC0_DIV_ARM_BASE 8
-
-/* PC0_DIV_ARM for PLLOUT_ARM */
-#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
-#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
-#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
-#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
-#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
-#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
-#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
-#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
-
-/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
-#define PMU0_PLL0_PLLCTL1 1
-#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
-#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
-#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
-#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
-#define PMU0_PLL0_PC1_STOP_MOD 0x00000040
-
-/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
-#define PMU0_PLL0_PLLCTL2 2
-#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
-#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
-
-/* pllcontrol registers */
-/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
-#define PMU1_PLL0_PLLCTL0 0
-#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
-#define PMU1_PLL0_PC0_P1DIV_SHIFT 20
-#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
-#define PMU1_PLL0_PC0_P2DIV_SHIFT 24
-
-/* m<x>div */
-#define PMU1_PLL0_PLLCTL1 1
-#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
-#define PMU1_PLL0_PC1_M1DIV_SHIFT 0
-#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
-#define PMU1_PLL0_PC1_M2DIV_SHIFT 8
-#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
-#define PMU1_PLL0_PC1_M3DIV_SHIFT 16
-#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
-#define PMU1_PLL0_PC1_M4DIV_SHIFT 24
-
-#define PMU1_PLL0_CHIPCTL0 0
-#define PMU1_PLL0_CHIPCTL1 1
-#define PMU1_PLL0_CHIPCTL2 2
-
-#define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8
-#define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
-#define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT)
-
-/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
-#define PMU1_PLL0_PLLCTL2 2
-#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
-#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
-#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
-#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
-#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
-#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
-#define PMU1_PLL0_PC2_NDIV_MODE_MASH 1
-#define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */
-#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
-#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
-
-/* ndiv_frac */
-#define PMU1_PLL0_PLLCTL3 3
-#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
-#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
-
-/* pll_ctrl */
-#define PMU1_PLL0_PLLCTL4 4
-
-/* pll_ctrl, vco_rng, clkdrive_ch<x> */
-#define PMU1_PLL0_PLLCTL5 5
-#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
-#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
-
-/* PMU rev 2 control words */
-#define PMU2_PHY_PLL_PLLCTL 4
-#define PMU2_SI_PLL_PLLCTL 10
-
-/* PMU rev 2 */
-/* pllcontrol registers */
-/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */
-#define PMU2_PLL_PLLCTL0 0
-#define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000
-#define PMU2_PLL_PC0_P1DIV_SHIFT 20
-#define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000
-#define PMU2_PLL_PC0_P2DIV_SHIFT 24
-
-/* m<x>div */
-#define PMU2_PLL_PLLCTL1 1
-#define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff
-#define PMU2_PLL_PC1_M1DIV_SHIFT 0
-#define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00
-#define PMU2_PLL_PC1_M2DIV_SHIFT 8
-#define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000
-#define PMU2_PLL_PC1_M3DIV_SHIFT 16
-#define PMU2_PLL_PC1_M4DIV_MASK 0xff000000
-#define PMU2_PLL_PC1_M4DIV_SHIFT 24
-
-/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
-#define PMU2_PLL_PLLCTL2 2
-#define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff
-#define PMU2_PLL_PC2_M5DIV_SHIFT 0
-#define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00
-#define PMU2_PLL_PC2_M6DIV_SHIFT 8
-#define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000
-#define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17
-#define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000
-#define PMU2_PLL_PC2_NDIV_INT_SHIFT 20
-
-/* ndiv_frac */
-#define PMU2_PLL_PLLCTL3 3
-#define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff
-#define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0
-
-/* pll_ctrl */
-#define PMU2_PLL_PLLCTL4 4
-
-/* pll_ctrl, vco_rng, clkdrive_ch<x> */
-#define PMU2_PLL_PLLCTL5 5
-#define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00
-#define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8
-#define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000
-#define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12
-#define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000
-#define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16
-#define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000
-#define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20
-#define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000
-#define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24
-#define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000
-#define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28
-
-/* PMU rev 5 (& 6) */
-#define PMU5_PLL_P1P2_OFF 0
-#define PMU5_PLL_P1_MASK 0x0f000000
-#define PMU5_PLL_P1_SHIFT 24
-#define PMU5_PLL_P2_MASK 0x00f00000
-#define PMU5_PLL_P2_SHIFT 20
-#define PMU5_PLL_M14_OFF 1
-#define PMU5_PLL_MDIV_MASK 0x000000ff
-#define PMU5_PLL_MDIV_WIDTH 8
-#define PMU5_PLL_NM5_OFF 2
-#define PMU5_PLL_NDIV_MASK 0xfff00000
-#define PMU5_PLL_NDIV_SHIFT 20
-#define PMU5_PLL_NDIV_MODE_MASK 0x000e0000
-#define PMU5_PLL_NDIV_MODE_SHIFT 17
-#define PMU5_PLL_FMAB_OFF 3
-#define PMU5_PLL_MRAT_MASK 0xf0000000
-#define PMU5_PLL_MRAT_SHIFT 28
-#define PMU5_PLL_ABRAT_MASK 0x08000000
-#define PMU5_PLL_ABRAT_SHIFT 27
-#define PMU5_PLL_FDIV_MASK 0x07ffffff
-#define PMU5_PLL_PLLCTL_OFF 4
-#define PMU5_PLL_PCHI_OFF 5
-#define PMU5_PLL_PCHI_MASK 0x0000003f
-
-/* pmu XtalFreqRatio */
-#define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
-#define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000
-#define PMU_XTALFREQ_REG_MEASURE_SHIFT 31
-
-/* Divider allocation in 4716/47162/5356/5357 */
-#define PMU5_MAINPLL_CPU 1
-#define PMU5_MAINPLL_MEM 2
-#define PMU5_MAINPLL_SI 3
-
-#define PMU7_PLL_PLLCTL7 7
-#define PMU7_PLL_PLLCTL8 8
-#define PMU7_PLL_PLLCTL11 11
-
-/* PLL usage in 4716/47162 */
-#define PMU4716_MAINPLL_PLL0 12
-
-/* PLL usage in 5356/5357 */
-#define PMU5356_MAINPLL_PLL0 0
-#define PMU5357_MAINPLL_PLL0 0
-
-/* 4328 resources */
-#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
-#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
-#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
-#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
-#define RES4328_ILP_REQUEST 4 /* 0x00010 */
-#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
-#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
-#define RES4328_ROM_SWITCH 7 /* 0x00080 */
-#define RES4328_PA_REF_LDO 8 /* 0x00100 */
-#define RES4328_RADIO_LDO 9 /* 0x00200 */
-#define RES4328_AFE_LDO 10 /* 0x00400 */
-#define RES4328_PLL_LDO 11 /* 0x00800 */
-#define RES4328_BG_FILTBYP 12 /* 0x01000 */
-#define RES4328_TX_FILTBYP 13 /* 0x02000 */
-#define RES4328_RX_FILTBYP 14 /* 0x04000 */
-#define RES4328_XTAL_PU 15 /* 0x08000 */
-#define RES4328_XTAL_EN 16 /* 0x10000 */
-#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
-#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
-#define RES4328_BB_PLL_PU 19 /* 0x80000 */
-
-/* 4325 A0/A1 resources */
-#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
-#define RES4325_CBUCK_BURST 1 /* 0x00000002 */
-#define RES4325_CBUCK_PWM 2 /* 0x00000004 */
-#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
-#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
-#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
-#define RES4325_ILP_REQUEST 6 /* 0x00000040 */
-#define RES4325_ABUCK_BURST 7 /* 0x00000080 */
-#define RES4325_ABUCK_PWM 8 /* 0x00000100 */
-#define RES4325_LNLDO1_PU 9 /* 0x00000200 */
-#define RES4325_OTP_PU 10 /* 0x00000400 */
-#define RES4325_LNLDO3_PU 11 /* 0x00000800 */
-#define RES4325_LNLDO4_PU 12 /* 0x00001000 */
-#define RES4325_XTAL_PU 13 /* 0x00002000 */
-#define RES4325_ALP_AVAIL 14 /* 0x00004000 */
-#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
-#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
-#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
-#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
-#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
-#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
-#define RES4325_HT_AVAIL 21 /* 0x00200000 */
-
-/* 4325 B0/C0 resources */
-#define RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */
-#define RES4325B0_CBUCK_BURST 2 /* 0x00000004 */
-#define RES4325B0_CBUCK_PWM 3 /* 0x00000008 */
-#define RES4325B0_CLDO_PU 4 /* 0x00000010 */
-
-/* 4325 C1 resources */
-#define RES4325C1_LNLDO2_PU 12 /* 0x00001000 */
-
-#define RES4329_RESERVED0 0 /* 0x00000001 */
-#define RES4329_CBUCK_LPOM 1 /* 0x00000002 */
-#define RES4329_CBUCK_BURST 2 /* 0x00000004 */
-#define RES4329_CBUCK_PWM 3 /* 0x00000008 */
-#define RES4329_CLDO_PU 4 /* 0x00000010 */
-#define RES4329_PALDO_PU 5 /* 0x00000020 */
-#define RES4329_ILP_REQUEST 6 /* 0x00000040 */
-#define RES4329_RESERVED7 7 /* 0x00000080 */
-#define RES4329_RESERVED8 8 /* 0x00000100 */
-#define RES4329_LNLDO1_PU 9 /* 0x00000200 */
-#define RES4329_OTP_PU 10 /* 0x00000400 */
-#define RES4329_RESERVED11 11 /* 0x00000800 */
-#define RES4329_LNLDO2_PU 12 /* 0x00001000 */
-#define RES4329_XTAL_PU 13 /* 0x00002000 */
-#define RES4329_ALP_AVAIL 14 /* 0x00004000 */
-#define RES4329_RX_PWRSW_PU 15 /* 0x00008000 */
-#define RES4329_TX_PWRSW_PU 16 /* 0x00010000 */
-#define RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */
-#define RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */
-#define RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */
-#define RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */
-#define RES4329_HT_AVAIL 21 /* 0x00200000 */
-
-/* 4315 resources */
-#define RES4315_CBUCK_LPOM 1 /* 0x00000002 */
-#define RES4315_CBUCK_BURST 2 /* 0x00000004 */
-#define RES4315_CBUCK_PWM 3 /* 0x00000008 */
-#define RES4315_CLDO_PU 4 /* 0x00000010 */
-#define RES4315_PALDO_PU 5 /* 0x00000020 */
-#define RES4315_ILP_REQUEST 6 /* 0x00000040 */
-#define RES4315_LNLDO1_PU 9 /* 0x00000200 */
-#define RES4315_OTP_PU 10 /* 0x00000400 */
-#define RES4315_LNLDO2_PU 12 /* 0x00001000 */
-#define RES4315_XTAL_PU 13 /* 0x00002000 */
-#define RES4315_ALP_AVAIL 14 /* 0x00004000 */
-#define RES4315_RX_PWRSW_PU 15 /* 0x00008000 */
-#define RES4315_TX_PWRSW_PU 16 /* 0x00010000 */
-#define RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */
-#define RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */
-#define RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */
-#define RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */
-#define RES4315_HT_AVAIL 21 /* 0x00200000 */
-
-/* 4319 resources */
-#define RES4319_CBUCK_LPOM 1 /* 0x00000002 */
-#define RES4319_CBUCK_BURST 2 /* 0x00000004 */
-#define RES4319_CBUCK_PWM 3 /* 0x00000008 */
-#define RES4319_CLDO_PU 4 /* 0x00000010 */
-#define RES4319_PALDO_PU 5 /* 0x00000020 */
-#define RES4319_ILP_REQUEST 6 /* 0x00000040 */
-#define RES4319_LNLDO1_PU 9 /* 0x00000200 */
-#define RES4319_OTP_PU 10 /* 0x00000400 */
-#define RES4319_LNLDO2_PU 12 /* 0x00001000 */
-#define RES4319_XTAL_PU 13 /* 0x00002000 */
-#define RES4319_ALP_AVAIL 14 /* 0x00004000 */
-#define RES4319_RX_PWRSW_PU 15 /* 0x00008000 */
-#define RES4319_TX_PWRSW_PU 16 /* 0x00010000 */
-#define RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */
-#define RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */
-#define RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */
-#define RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */
-#define RES4319_HT_AVAIL 21 /* 0x00200000 */
-
-#define CCTL_4319USB_XTAL_SEL_MASK 0x00180000
-#define CCTL_4319USB_XTAL_SEL_SHIFT 19
-#define CCTL_4319USB_48MHZ_PLL_SEL 1
-#define CCTL_4319USB_24MHZ_PLL_SEL 2
-
-/* PMU resources for 4336 */
-#define RES4336_CBUCK_LPOM 0
-#define RES4336_CBUCK_BURST 1
-#define RES4336_CBUCK_LP_PWM 2
-#define RES4336_CBUCK_PWM 3
-#define RES4336_CLDO_PU 4
-#define RES4336_DIS_INT_RESET_PD 5
-#define RES4336_ILP_REQUEST 6
-#define RES4336_LNLDO_PU 7
-#define RES4336_LDO3P3_PU 8
-#define RES4336_OTP_PU 9
-#define RES4336_XTAL_PU 10
-#define RES4336_ALP_AVAIL 11
-#define RES4336_RADIO_PU 12
-#define RES4336_BG_PU 13
-#define RES4336_VREG1p4_PU_PU 14
-#define RES4336_AFE_PWRSW_PU 15
-#define RES4336_RX_PWRSW_PU 16
-#define RES4336_TX_PWRSW_PU 17
-#define RES4336_BB_PWRSW_PU 18
-#define RES4336_SYNTH_PWRSW_PU 19
-#define RES4336_MISC_PWRSW_PU 20
-#define RES4336_LOGEN_PWRSW_PU 21
-#define RES4336_BBPLL_PWRSW_PU 22
-#define RES4336_MACPHY_CLKAVAIL 23
-#define RES4336_HT_AVAIL 24
-#define RES4336_RSVD 25
-
-/* 4330 resources */
-#define RES4330_CBUCK_LPOM 0
-#define RES4330_CBUCK_BURST 1
-#define RES4330_CBUCK_LP_PWM 2
-#define RES4330_CBUCK_PWM 3
-#define RES4330_CLDO_PU 4
-#define RES4330_DIS_INT_RESET_PD 5
-#define RES4330_ILP_REQUEST 6
-#define RES4330_LNLDO_PU 7
-#define RES4330_LDO3P3_PU 8
-#define RES4330_OTP_PU 9
-#define RES4330_XTAL_PU 10
-#define RES4330_ALP_AVAIL 11
-#define RES4330_RADIO_PU 12
-#define RES4330_BG_PU 13
-#define RES4330_VREG1p4_PU_PU 14
-#define RES4330_AFE_PWRSW_PU 15
-#define RES4330_RX_PWRSW_PU 16
-#define RES4330_TX_PWRSW_PU 17
-#define RES4330_BB_PWRSW_PU 18
-#define RES4330_SYNTH_PWRSW_PU 19
-#define RES4330_MISC_PWRSW_PU 20
-#define RES4330_LOGEN_PWRSW_PU 21
-#define RES4330_BBPLL_PWRSW_PU 22
-#define RES4330_MACPHY_CLKAVAIL 23
-#define RES4330_HT_AVAIL 24
-#define RES4330_5gRX_PWRSW_PU 25
-#define RES4330_5gTX_PWRSW_PU 26
-#define RES4330_5g_LOGEN_PWRSW_PU 27
-
-/* 4313 resources */
-#define RES4313_BB_PU_RSRC 0
-#define RES4313_ILP_REQ_RSRC 1
-#define RES4313_XTAL_PU_RSRC 2
-#define RES4313_ALP_AVAIL_RSRC 3
-#define RES4313_RADIO_PU_RSRC 4
-#define RES4313_BG_PU_RSRC 5
-#define RES4313_VREG1P4_PU_RSRC 6
-#define RES4313_AFE_PWRSW_RSRC 7
-#define RES4313_RX_PWRSW_RSRC 8
-#define RES4313_TX_PWRSW_RSRC 9
-#define RES4313_BB_PWRSW_RSRC 10
-#define RES4313_SYNTH_PWRSW_RSRC 11
-#define RES4313_MISC_PWRSW_RSRC 12
-#define RES4313_BB_PLL_PWRSW_RSRC 13
-#define RES4313_HT_AVAIL_RSRC 14
-#define RES4313_MACPHY_CLK_AVAIL_RSRC 15
-
-/* PMU resource up transition time in ILP cycles */
-#define PMURES_UP_TRANSITION 2
-
-/* Setup resource up/down timers */
-typedef struct {
- u8 resnum;
- u16 updown;
-} pmu_res_updown_t;
-
-/* Change resource dependancies masks */
-typedef struct {
- u32 res_mask; /* resources (chip specific) */
- s8 action; /* action */
- u32 depend_mask; /* changes to the dependancies mask */
- /* action is taken when filter is NULL or return true: */
- bool(*filter) (struct si_pub *sih);
-} pmu_res_depend_t;
-
-/* setup pll and query clock speed */
-typedef struct {
- u16 fref;
- u8 xf;
- u8 p1div;
- u8 p2div;
- u8 ndiv_int;
- u32 ndiv_frac;
-} pmu1_xtaltab0_t;
-
-/*
- * prototypes used in resource tables
- */
-static bool si_pmu_res_depfltr_bb(struct si_pub *sih);
-static bool si_pmu_res_depfltr_ncb(struct si_pub *sih);
-static bool si_pmu_res_depfltr_paldo(struct si_pub *sih);
-static bool si_pmu_res_depfltr_npaldo(struct si_pub *sih);
-
-static const pmu_res_updown_t bcm4328a0_res_updown[] = {
- {
- RES4328_EXT_SWITCHER_PWM, 0x0101}, {
- RES4328_BB_SWITCHER_PWM, 0x1f01}, {
- RES4328_BB_SWITCHER_BURST, 0x010f}, {
- RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, {
- RES4328_ILP_REQUEST, 0x0202}, {
- RES4328_RADIO_SWITCHER_PWM, 0x0f01}, {
- RES4328_RADIO_SWITCHER_BURST, 0x0f01}, {
- RES4328_ROM_SWITCH, 0x0101}, {
- RES4328_PA_REF_LDO, 0x0f01}, {
- RES4328_RADIO_LDO, 0x0f01}, {
- RES4328_AFE_LDO, 0x0f01}, {
- RES4328_PLL_LDO, 0x0f01}, {
- RES4328_BG_FILTBYP, 0x0101}, {
- RES4328_TX_FILTBYP, 0x0101}, {
- RES4328_RX_FILTBYP, 0x0101}, {
- RES4328_XTAL_PU, 0x0101}, {
- RES4328_XTAL_EN, 0xa001}, {
- RES4328_BB_PLL_FILTBYP, 0x0101}, {
- RES4328_RF_PLL_FILTBYP, 0x0101}, {
- RES4328_BB_PLL_PU, 0x0701}
-};
-
-static const pmu_res_depend_t bcm4328a0_res_depend[] = {
- /* Adjust ILP request resource not to force ext/BB switchers into burst mode */
- {
- PMURES_BIT(RES4328_ILP_REQUEST),
- RES_DEPEND_SET,
- PMURES_BIT(RES4328_EXT_SWITCHER_PWM) |
- PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL}
-};
-
-static const pmu_res_updown_t bcm4325a0_res_updown_qt[] = {
- {
- RES4325_HT_AVAIL, 0x0300}, {
- RES4325_BBPLL_PWRSW_PU, 0x0101}, {
- RES4325_RFPLL_PWRSW_PU, 0x0101}, {
- RES4325_ALP_AVAIL, 0x0100}, {
- RES4325_XTAL_PU, 0x1000}, {
- RES4325_LNLDO1_PU, 0x0800}, {
- RES4325_CLDO_CBUCK_PWM, 0x0101}, {
- RES4325_CBUCK_PWM, 0x0803}
-};
-
-static const pmu_res_updown_t bcm4325a0_res_updown[] = {
- {
- RES4325_XTAL_PU, 0x1501}
-};
-
-static const pmu_res_depend_t bcm4325a0_res_depend[] = {
- /* Adjust OTP PU resource dependencies - remove BB BURST */
- {
- PMURES_BIT(RES4325_OTP_PU),
- RES_DEPEND_REMOVE,
- PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL},
- /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */
- {
- PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4325_BUCK_BOOST_BURST) |
- PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb},
- /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
- {
- PMURES_BIT(RES4325_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4325_RX_PWRSW_PU) |
- PMURES_BIT(RES4325_TX_PWRSW_PU) |
- PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL},
- /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
- {
- PMURES_BIT(RES4325_ILP_REQUEST) |
- PMURES_BIT(RES4325_ABUCK_BURST) |
- PMURES_BIT(RES4325_ABUCK_PWM) |
- PMURES_BIT(RES4325_LNLDO1_PU) |
- PMURES_BIT(RES4325C1_LNLDO2_PU) |
- PMURES_BIT(RES4325_XTAL_PU) |
- PMURES_BIT(RES4325_ALP_AVAIL) |
- PMURES_BIT(RES4325_RX_PWRSW_PU) |
- PMURES_BIT(RES4325_TX_PWRSW_PU) |
- PMURES_BIT(RES4325_RFPLL_PWRSW_PU) |
- PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4325_AFE_PWRSW_PU) |
- PMURES_BIT(RES4325_BBPLL_PWRSW_PU) |
- PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE,
- PMURES_BIT(RES4325B0_CBUCK_LPOM) |
- PMURES_BIT(RES4325B0_CBUCK_BURST) |
- PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb}
-};
-
-static const pmu_res_updown_t bcm4315a0_res_updown_qt[] = {
- {
- RES4315_HT_AVAIL, 0x0101}, {
- RES4315_XTAL_PU, 0x0100}, {
- RES4315_LNLDO1_PU, 0x0100}, {
- RES4315_PALDO_PU, 0x0100}, {
- RES4315_CLDO_PU, 0x0100}, {
- RES4315_CBUCK_PWM, 0x0100}, {
- RES4315_CBUCK_BURST, 0x0100}, {
- RES4315_CBUCK_LPOM, 0x0100}
-};
-
-static const pmu_res_updown_t bcm4315a0_res_updown[] = {
- {
- RES4315_XTAL_PU, 0x2501}
-};
-
-static const pmu_res_depend_t bcm4315a0_res_depend[] = {
- /* Adjust OTP PU resource dependencies - not need PALDO unless write */
- {
- PMURES_BIT(RES4315_OTP_PU),
- RES_DEPEND_REMOVE,
- PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo},
- /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */
- {
- PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo},
- /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
- {
- PMURES_BIT(RES4315_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4315_RX_PWRSW_PU) |
- PMURES_BIT(RES4315_TX_PWRSW_PU) |
- PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL},
- /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
- {
- PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) |
- PMURES_BIT(RES4315_LNLDO1_PU) |
- PMURES_BIT(RES4315_OTP_PU) |
- PMURES_BIT(RES4315_LNLDO2_PU) |
- PMURES_BIT(RES4315_XTAL_PU) |
- PMURES_BIT(RES4315_ALP_AVAIL) |
- PMURES_BIT(RES4315_RX_PWRSW_PU) |
- PMURES_BIT(RES4315_TX_PWRSW_PU) |
- PMURES_BIT(RES4315_RFPLL_PWRSW_PU) |
- PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4315_AFE_PWRSW_PU) |
- PMURES_BIT(RES4315_BBPLL_PWRSW_PU) |
- PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE,
- PMURES_BIT(RES4315_CBUCK_LPOM) |
- PMURES_BIT(RES4315_CBUCK_BURST) |
- PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb}
-};
-
- /* 4329 specific. needs to come back this issue later */
-static const pmu_res_updown_t bcm4329_res_updown[] = {
- {
- RES4329_XTAL_PU, 0x1501}
-};
-
-static const pmu_res_depend_t bcm4329_res_depend[] = {
- /* Adjust HT Avail resource dependencies */
- {
- PMURES_BIT(RES4329_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4329_CBUCK_LPOM) |
- PMURES_BIT(RES4329_CBUCK_BURST) |
- PMURES_BIT(RES4329_CBUCK_PWM) |
- PMURES_BIT(RES4329_CLDO_PU) |
- PMURES_BIT(RES4329_PALDO_PU) |
- PMURES_BIT(RES4329_LNLDO1_PU) |
- PMURES_BIT(RES4329_XTAL_PU) |
- PMURES_BIT(RES4329_ALP_AVAIL) |
- PMURES_BIT(RES4329_RX_PWRSW_PU) |
- PMURES_BIT(RES4329_TX_PWRSW_PU) |
- PMURES_BIT(RES4329_RFPLL_PWRSW_PU) |
- PMURES_BIT(RES4329_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4329_AFE_PWRSW_PU) |
- PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL}
-};
-
-static const pmu_res_updown_t bcm4319a0_res_updown_qt[] = {
- {
- RES4319_HT_AVAIL, 0x0101}, {
- RES4319_XTAL_PU, 0x0100}, {
- RES4319_LNLDO1_PU, 0x0100}, {
- RES4319_PALDO_PU, 0x0100}, {
- RES4319_CLDO_PU, 0x0100}, {
- RES4319_CBUCK_PWM, 0x0100}, {
- RES4319_CBUCK_BURST, 0x0100}, {
- RES4319_CBUCK_LPOM, 0x0100}
-};
-
-static const pmu_res_updown_t bcm4319a0_res_updown[] = {
- {
- RES4319_XTAL_PU, 0x3f01}
-};
-
-static const pmu_res_depend_t bcm4319a0_res_depend[] = {
- /* Adjust OTP PU resource dependencies - not need PALDO unless write */
- {
- PMURES_BIT(RES4319_OTP_PU),
- RES_DEPEND_REMOVE,
- PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo},
- /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */
- {
- PMURES_BIT(RES4319_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo},
- /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
- {
- PMURES_BIT(RES4319_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4319_RX_PWRSW_PU) |
- PMURES_BIT(RES4319_TX_PWRSW_PU) |
- PMURES_BIT(RES4319_RFPLL_PWRSW_PU) |
- PMURES_BIT(RES4319_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL}
-};
-
-static const pmu_res_updown_t bcm4336a0_res_updown_qt[] = {
- {
- RES4336_HT_AVAIL, 0x0101}, {
- RES4336_XTAL_PU, 0x0100}, {
- RES4336_CLDO_PU, 0x0100}, {
- RES4336_CBUCK_PWM, 0x0100}, {
- RES4336_CBUCK_BURST, 0x0100}, {
- RES4336_CBUCK_LPOM, 0x0100}
-};
-
-static const pmu_res_updown_t bcm4336a0_res_updown[] = {
- {
- RES4336_HT_AVAIL, 0x0D01}
-};
-
-static const pmu_res_depend_t bcm4336a0_res_depend[] = {
- /* Just a dummy entry for now */
- {
- PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL}
-};
-
-static const pmu_res_updown_t bcm4330a0_res_updown_qt[] = {
- {
- RES4330_HT_AVAIL, 0x0101}, {
- RES4330_XTAL_PU, 0x0100}, {
- RES4330_CLDO_PU, 0x0100}, {
- RES4330_CBUCK_PWM, 0x0100}, {
- RES4330_CBUCK_BURST, 0x0100}, {
- RES4330_CBUCK_LPOM, 0x0100}
-};
-
-static const pmu_res_updown_t bcm4330a0_res_updown[] = {
- {
- RES4330_HT_AVAIL, 0x0e02}
-};
-
-static const pmu_res_depend_t bcm4330a0_res_depend[] = {
- /* Just a dummy entry for now */
- {
- PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL}
-};
-
-/* the following table is based on 1440Mhz fvco */
-static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = {
- {
- 12000, 1, 1, 1, 0x78, 0x0}, {
- 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, {
- 14400, 3, 1, 1, 0x64, 0x0}, {
- 15360, 4, 1, 1, 0x5D, 0xC00000}, {
- 16200, 5, 1, 1, 0x58, 0xE38E38}, {
- 16800, 6, 1, 1, 0x55, 0xB6DB6D}, {
- 19200, 7, 1, 1, 0x4B, 0}, {
- 19800, 8, 1, 1, 0x48, 0xBA2E8B}, {
- 20000, 9, 1, 1, 0x48, 0x0}, {
- 25000, 10, 1, 1, 0x39, 0x999999}, {
- 26000, 11, 1, 1, 0x37, 0x627627}, {
- 30000, 12, 1, 1, 0x30, 0x0}, {
- 37400, 13, 2, 1, 0x4D, 0x15E76}, {
- 38400, 13, 2, 1, 0x4B, 0x0}, {
- 40000, 14, 2, 1, 0x48, 0x0}, {
- 48000, 15, 2, 1, 0x3c, 0x0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = {
- {
- 12000, 1, 1, 1, 0x50, 0x0}, {
- 13000, 2, 1, 1, 0x49, 0xD89D89}, {
- 14400, 3, 1, 1, 0x42, 0xAAAAAA}, {
- 15360, 4, 1, 1, 0x3E, 0x800000}, {
- 16200, 5, 1, 1, 0x39, 0x425ED0}, {
- 16800, 6, 1, 1, 0x39, 0x249249}, {
- 19200, 7, 1, 1, 0x32, 0x0}, {
- 19800, 8, 1, 1, 0x30, 0x7C1F07}, {
- 20000, 9, 1, 1, 0x30, 0x0}, {
- 25000, 10, 1, 1, 0x26, 0x666666}, {
- 26000, 11, 1, 1, 0x24, 0xEC4EC4}, {
- 30000, 12, 1, 1, 0x20, 0x0}, {
- 37400, 13, 2, 1, 0x33, 0x563EF9}, {
- 38400, 14, 2, 1, 0x32, 0x0}, {
- 40000, 15, 2, 1, 0x30, 0x0}, {
- 48000, 16, 2, 1, 0x28, 0x0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = {
- {
- 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
- 13000, 2, 1, 6, 0xb, 0x483483}, {
- 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
- 15360, 4, 1, 5, 0xb, 0x755555}, {
- 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
- 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
- 19200, 7, 1, 4, 0xb, 0x755555}, {
- 19800, 8, 1, 11, 0x4, 0xA57EB}, {
- 20000, 9, 1, 11, 0x4, 0x0}, {
- 24000, 10, 3, 11, 0xa, 0x0}, {
- 25000, 11, 5, 16, 0xb, 0x0}, {
- 26000, 12, 1, 1, 0x21, 0xD89D89}, {
- 30000, 13, 3, 8, 0xb, 0x0}, {
- 37400, 14, 3, 1, 0x46, 0x969696}, {
- 38400, 15, 1, 1, 0x16, 0xEAAAAA}, {
- 40000, 16, 1, 2, 0xb, 0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-/* the following table is based on 880Mhz fvco */
-static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = {
- {
- 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
- 13000, 2, 1, 6, 0xb, 0x483483}, {
- 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
- 15360, 4, 1, 5, 0xb, 0x755555}, {
- 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
- 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
- 19200, 7, 1, 4, 0xb, 0x755555}, {
- 19800, 8, 1, 11, 0x4, 0xA57EB}, {
- 20000, 9, 1, 11, 0x4, 0x0}, {
- 24000, 10, 3, 11, 0xa, 0x0}, {
- 25000, 11, 5, 16, 0xb, 0x0}, {
- 26000, 12, 1, 2, 0x10, 0xEC4EC4}, {
- 30000, 13, 3, 8, 0xb, 0x0}, {
- 33600, 14, 1, 2, 0xd, 0x186186}, {
- 38400, 15, 1, 2, 0xb, 0x755555}, {
- 40000, 16, 1, 2, 0xb, 0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-/* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
-static bool si_pmu_res_depfltr_bb(struct si_pub *sih)
-{
- return (sih->boardflags & BFL_BUCKBOOST) != 0;
-}
-
-/* true if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
-static bool si_pmu_res_depfltr_ncb(struct si_pub *sih)
-{
-
- return (sih->boardflags & BFL_NOCBUCK) != 0;
-}
-
-/* true if the power topology uses the PALDO */
-static bool si_pmu_res_depfltr_paldo(struct si_pub *sih)
-{
- return (sih->boardflags & BFL_PALDO) != 0;
-}
-
-/* true if the power topology doesn't use the PALDO */
-static bool si_pmu_res_depfltr_npaldo(struct si_pub *sih)
-{
- return (sih->boardflags & BFL_PALDO) == 0;
-}
-
-/* Return dependancies (direct or all/indirect) for the given resources */
-static u32
-si_pmu_res_deps(struct si_pub *sih, chipcregs_t *cc, u32 rsrcs,
- bool all)
-{
- u32 deps = 0;
- u32 i;
-
- for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
- if (!(rsrcs & PMURES_BIT(i)))
- continue;
- W_REG(&cc->res_table_sel, i);
- deps |= R_REG(&cc->res_dep_mask);
- }
-
- return !all ? deps : (deps
- ? (deps |
- si_pmu_res_deps(sih, cc, deps,
- true)) : 0);
-}
-
-/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
-static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
-{
- u32 min_mask = 0, max_mask = 0;
- uint rsrcs;
- char *val;
-
- /* # resources */
- rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
-
- /* determine min/max rsrc masks */
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- /* ??? */
- break;
-
- case BCM4329_CHIP_ID:
- /* 4329 spedific issue. Needs to come back this issue later */
- /* Down to save the power. */
- min_mask =
- PMURES_BIT(RES4329_CBUCK_LPOM) |
- PMURES_BIT(RES4329_CLDO_PU);
- /* Allow (but don't require) PLL to turn on */
- max_mask = 0x3ff63e;
- break;
- case BCM4319_CHIP_ID:
- /* We only need a few resources to be kept on all the time */
- min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
- PMURES_BIT(RES4319_CLDO_PU);
-
- /* Allow everything else to be turned on upon requests */
- max_mask = ~(~0 << rsrcs);
- break;
- case BCM4336_CHIP_ID:
- /* Down to save the power. */
- min_mask =
- PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU)
- | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU)
- | PMURES_BIT(RES4336_DIS_INT_RESET_PD);
- /* Allow (but don't require) PLL to turn on */
- max_mask = 0x1ffffff;
- break;
-
- case BCM4330_CHIP_ID:
- /* Down to save the power. */
- min_mask =
- PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU)
- | PMURES_BIT(RES4330_DIS_INT_RESET_PD) |
- PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU);
- /* Allow (but don't require) PLL to turn on */
- max_mask = 0xfffffff;
- break;
-
- case BCM4313_CHIP_ID:
- min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
- PMURES_BIT(RES4313_XTAL_PU_RSRC) |
- PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
- PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
- max_mask = 0xffff;
- break;
- default:
- break;
- }
-
- /* Apply nvram override to min mask */
- val = getvar(NULL, "rmin");
- if (val != NULL) {
- min_mask = (u32) simple_strtoul(val, NULL, 0);
- }
- /* Apply nvram override to max mask */
- val = getvar(NULL, "rmax");
- if (val != NULL) {
- max_mask = (u32) simple_strtoul(val, NULL, 0);
- }
-
- *pmin = min_mask;
- *pmax = max_mask;
-}
-
-/* Return up time in ILP cycles for the given resource. */
-static uint
-si_pmu_res_uptime(struct si_pub *sih, chipcregs_t *cc, u8 rsrc) {
- u32 deps;
- uint up, i, dup, dmax;
- u32 min_mask = 0, max_mask = 0;
-
- /* uptime of resource 'rsrc' */
- W_REG(&cc->res_table_sel, rsrc);
- up = (R_REG(&cc->res_updn_timer) >> 8) & 0xff;
-
- /* direct dependancies of resource 'rsrc' */
- deps = si_pmu_res_deps(sih, cc, PMURES_BIT(rsrc), false);
- for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
- if (!(deps & PMURES_BIT(i)))
- continue;
- deps &= ~si_pmu_res_deps(sih, cc, PMURES_BIT(i), true);
- }
- si_pmu_res_masks(sih, &min_mask, &max_mask);
- deps &= ~min_mask;
-
- /* max uptime of direct dependancies */
- dmax = 0;
- for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
- if (!(deps & PMURES_BIT(i)))
- continue;
- dup = si_pmu_res_uptime(sih, cc, (u8) i);
- if (dmax < dup)
- dmax = dup;
- }
-
- return up + dmax + PMURES_UP_TRANSITION;
-}
-
-static void
-si_pmu_spuravoid_pllupdate(struct si_pub *sih, chipcregs_t *cc, u8 spuravoid)
-{
- u32 tmp = 0;
- u8 phypll_offset = 0;
- u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
- u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
-
- switch (sih->chip) {
- case BCM5357_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
-
- /*
- * BCM5357 needs to touch PLL1_PLLCTL[02],
- * so offset PLL0_PLLCTL[02] by 6
- */
- phypll_offset = (sih->chip == BCM5357_CHIP_ID) ? 6 : 0;
-
- /* RMW only the P1 divider */
- W_REG(&cc->pllcontrol_addr,
- PMU1_PLL0_PLLCTL0 + phypll_offset);
- tmp = R_REG(&cc->pllcontrol_data);
- tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK));
- tmp |=
- (bcm5357_bcm43236_p1div[spuravoid] <<
- PMU1_PLL0_PC0_P1DIV_SHIFT);
- W_REG(&cc->pllcontrol_data, tmp);
-
- /* RMW only the int feedback divider */
- W_REG(&cc->pllcontrol_addr,
- PMU1_PLL0_PLLCTL2 + phypll_offset);
- tmp = R_REG(&cc->pllcontrol_data);
- tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK);
- tmp |=
- (bcm5357_bcm43236_ndiv[spuravoid]) <<
- PMU1_PLL0_PC2_NDIV_INT_SHIFT;
- W_REG(&cc->pllcontrol_data, tmp);
-
- tmp = 1 << 10;
- break;
-
- case BCM4331_CHIP_ID:
- if (spuravoid == 2) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11500014);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x0FC00a08);
- } else if (spuravoid == 1) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11500014);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x0F600a08);
- } else {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100014);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x03000a08);
- }
- tmp = 1 << 10;
- break;
-
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM6362_CHIP_ID:
- if (spuravoid == 1) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11500010);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x000C0C06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x0F600a08);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x2001E920);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888815);
- } else {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100010);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x000c0c06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x03000a08);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x200005c0);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888815);
- }
- tmp = 1 << 10;
- break;
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100008);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x0c000c06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x03000a08);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x200005c0);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888855);
-
- tmp = 1 << 10;
- break;
-
- case BCM4716_CHIP_ID:
- case BCM4748_CHIP_ID:
- case BCM47162_CHIP_ID:
- if (spuravoid == 1) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11500060);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x080C0C06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x0F600000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x2001E924);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888815);
- } else {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100060);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x080c0c06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x03000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x200005c0);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888815);
- }
-
- tmp = 3 << 9;
- break;
-
- case BCM4319_CHIP_ID:
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100070);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x1014140a);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888854);
-
- if (spuravoid == 1) {
- /* spur_avoid ON, so enable 41/82/164Mhz clock mode */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x05201828);
- } else {
- /* enable 40/80/160Mhz clock mode */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x05001828);
- }
- break;
- case BCM4336_CHIP_ID:
- /* Looks like these are only for default xtal freq 26MHz */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x02100020);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x0C0C0C0C);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x01240C0C);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x202C2820);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888825);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- if (spuravoid == 1)
- W_REG(&cc->pllcontrol_data, 0x00EC4EC4);
- else
- W_REG(&cc->pllcontrol_data, 0x00762762);
-
- tmp = PCTL_PLL_PLLCTL_UPD;
- break;
-
- default:
- /* bail out */
- return;
- }
-
- tmp |= R_REG(&cc->pmucontrol);
- W_REG(&cc->pmucontrol, tmp);
-}
-
-/* select default xtal frequency for each chip */
-static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(struct si_pub *sih)
-{
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- /* Default to 38400Khz */
- return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K];
- case BCM4319_CHIP_ID:
- /* Default to 30000Khz */
- return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K];
- case BCM4336_CHIP_ID:
- /* Default to 26000Khz */
- return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K];
- case BCM4330_CHIP_ID:
- /* Default to 37400Khz */
- if (CST4330_CHIPMODE_SDIOD(sih->chipst))
- return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K];
- else
- return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K];
- default:
- break;
- }
- return NULL;
-}
-
-/* select xtal table for each chip */
-static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(struct si_pub *sih)
-{
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- return pmu1_xtaltab0_880_4329;
- case BCM4319_CHIP_ID:
- return pmu1_xtaltab0_1440;
- case BCM4336_CHIP_ID:
- return pmu1_xtaltab0_960;
- case BCM4330_CHIP_ID:
- if (CST4330_CHIPMODE_SDIOD(sih->chipst))
- return pmu1_xtaltab0_960;
- else
- return pmu1_xtaltab0_1440;
- default:
- break;
- }
- return NULL;
-}
-
-/* query alp/xtal clock frequency */
-static u32
-si_pmu1_alpclk0(struct si_pub *sih, chipcregs_t *cc)
-{
- const pmu1_xtaltab0_t *xt;
- u32 xf;
-
- /* Find the frequency in the table */
- xf = (R_REG(&cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
- PCTL_XTALFREQ_SHIFT;
- for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
- if (xt->xf == xf)
- break;
- /* Could not find it so assign a default value */
- if (xt == NULL || xt->fref == 0)
- xt = si_pmu1_xtaldef0(sih);
- return xt->fref * 1000;
-}
-
-/* select default pll fvco for each chip */
-static u32 si_pmu1_pllfvco0(struct si_pub *sih)
-{
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- return FVCO_880;
- case BCM4319_CHIP_ID:
- return FVCO_1440;
- case BCM4336_CHIP_ID:
- return FVCO_960;
- case BCM4330_CHIP_ID:
- if (CST4330_CHIPMODE_SDIOD(sih->chipst))
- return FVCO_960;
- else
- return FVCO_1440;
- default:
- break;
- }
- return 0;
-}
-
-static void si_pmu_set_4330_plldivs(struct si_pub *sih)
-{
- u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
- u32 m1div, m2div, m3div, m4div, m5div, m6div;
- u32 pllc1, pllc2;
-
- m2div = m3div = m4div = m6div = FVCO / 80;
- m5div = FVCO / 160;
-
- if (CST4330_CHIPMODE_SDIOD(sih->chipst))
- m1div = FVCO / 80;
- else
- m1div = FVCO / 90;
- pllc1 =
- (m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div <<
- PMU1_PLL0_PC1_M2DIV_SHIFT) |
- (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div <<
- PMU1_PLL0_PC1_M4DIV_SHIFT);
- si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1);
-
- pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
- pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK);
- pllc2 |=
- ((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) |
- (m6div << PMU1_PLL0_PC2_M6DIV_SHIFT));
- si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2);
-}
-
-/* Set up PLL registers in the PMU as per the crystal speed.
- * XtalFreq field in pmucontrol register being 0 indicates the PLL
- * is not programmed and the h/w default is assumed to work, in which
- * case the xtal frequency is unknown to the s/w so we need to call
- * si_pmu1_xtaldef0() wherever it is needed to return a default value.
- */
-static void si_pmu1_pllinit0(struct si_pub *sih, chipcregs_t *cc, u32 xtal)
-{
- const pmu1_xtaltab0_t *xt;
- u32 tmp;
- u32 buf_strength = 0;
- u8 ndiv_mode = 1;
-
- /* Use h/w default PLL config */
- if (xtal == 0) {
- return;
- }
-
- /* Find the frequency in the table */
- for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
- if (xt->fref == xtal)
- break;
-
- /* Check current PLL state, bail out if it has been programmed or
- * we don't know how to program it.
- */
- if (xt == NULL || xt->fref == 0) {
- return;
- }
- /* for 4319 bootloader already programs the PLL but bootloader does not
- * program the PLL4 and PLL5. So Skip this check for 4319
- */
- if ((((R_REG(&cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
- PCTL_XTALFREQ_SHIFT) == xt->xf) &&
- !((sih->chip == BCM4319_CHIP_ID)
- || (sih->chip == BCM4330_CHIP_ID)))
- return;
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- /* Change the BBPLL drive strength to 8 for all channels */
- buf_strength = 0x888888;
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
- PMURES_BIT(RES4329_HT_AVAIL)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
- PMURES_BIT(RES4329_HT_AVAIL)));
- SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
- PMU_MAX_TRANSITION_DLY);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- if (xt->fref == 38400)
- tmp = 0x200024C0;
- else if (xt->fref == 37400)
- tmp = 0x20004500;
- else if (xt->fref == 26000)
- tmp = 0x200024C0;
- else
- tmp = 0x200005C0; /* Chip Dflt Settings */
- W_REG(&cc->pllcontrol_data, tmp);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- tmp =
- R_REG(&cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK;
- if ((xt->fref == 38400) || (xt->fref == 37400)
- || (xt->fref == 26000))
- tmp |= 0x15;
- else
- tmp |= 0x25; /* Chip Dflt Settings */
- W_REG(&cc->pllcontrol_data, tmp);
- break;
-
- case BCM4319_CHIP_ID:
- /* Change the BBPLL drive strength to 2 for all channels */
- buf_strength = 0x222222;
-
- /* Make sure the PLL is off */
- /* WAR65104: Disable the HT_AVAIL resource first and then
- * after a delay (more than downtime for HT_AVAIL) remove the
- * BBPLL resource; backplane clock moves to ALP from HT.
- */
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4319_HT_AVAIL)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4319_HT_AVAIL)));
-
- udelay(100);
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
-
- udelay(100);
- SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
- PMU_MAX_TRANSITION_DLY);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- tmp = 0x200005c0;
- W_REG(&cc->pllcontrol_data, tmp);
- break;
-
- case BCM4336_CHIP_ID:
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4336_HT_AVAIL) |
- PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4336_HT_AVAIL) |
- PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
- udelay(100);
- SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
- PMU_MAX_TRANSITION_DLY);
- break;
-
- case BCM4330_CHIP_ID:
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4330_HT_AVAIL) |
- PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4330_HT_AVAIL) |
- PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
- udelay(100);
- SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
- PMU_MAX_TRANSITION_DLY);
- break;
-
- default:
- break;
- }
-
- /* Write p1div and p2div to pllcontrol[0] */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- tmp = R_REG(&cc->pllcontrol_data) &
- ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK);
- tmp |=
- ((xt->
- p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
- ((xt->
- p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK);
- W_REG(&cc->pllcontrol_data, tmp);
-
- if ((sih->chip == BCM4330_CHIP_ID))
- si_pmu_set_4330_plldivs(sih);
-
- if ((sih->chip == BCM4329_CHIP_ID)
- && (sih->chiprev == 0)) {
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- tmp = R_REG(&cc->pllcontrol_data);
- tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK);
- tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL;
- W_REG(&cc->pllcontrol_data, tmp);
- }
- if ((sih->chip == BCM4319_CHIP_ID) ||
- (sih->chip == BCM4336_CHIP_ID) ||
- (sih->chip == BCM4330_CHIP_ID))
- ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB;
- else
- ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH;
-
- /* Write ndiv_int and ndiv_mode to pllcontrol[2] */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- tmp = R_REG(&cc->pllcontrol_data) &
- ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK);
- tmp |=
- ((xt->
- ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) &
- PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode <<
- PMU1_PLL0_PC2_NDIV_MODE_SHIFT) &
- PMU1_PLL0_PC2_NDIV_MODE_MASK);
- W_REG(&cc->pllcontrol_data, tmp);
-
- /* Write ndiv_frac to pllcontrol[3] */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- tmp = R_REG(&cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
- tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) &
- PMU1_PLL0_PC3_NDIV_FRAC_MASK);
- W_REG(&cc->pllcontrol_data, tmp);
-
- /* Write clock driving strength to pllcontrol[5] */
- if (buf_strength) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- tmp =
- R_REG(&cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
- tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT);
- W_REG(&cc->pllcontrol_data, tmp);
- }
-
- /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs
- * to be updated.
- */
- if ((sih->chip == BCM4319_CHIP_ID)
- && (xt->fref != XTAL_FREQ_30000MHZ)) {
- W_REG(&cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
- tmp =
- R_REG(&cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK;
- if (xt->fref == XTAL_FREQ_24000MHZ) {
- tmp |=
- (CCTL_4319USB_24MHZ_PLL_SEL <<
- CCTL_4319USB_XTAL_SEL_SHIFT);
- } else if (xt->fref == XTAL_FREQ_48000MHZ) {
- tmp |=
- (CCTL_4319USB_48MHZ_PLL_SEL <<
- CCTL_4319USB_XTAL_SEL_SHIFT);
- }
- W_REG(&cc->chipcontrol_data, tmp);
- }
-
- /* Flush deferred pll control registers writes */
- if (sih->pmurev >= 2)
- OR_REG(&cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
-
- /* Write XtalFreq. Set the divisor also. */
- tmp = R_REG(&cc->pmucontrol) &
- ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK);
- tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) &
- PCTL_ILP_DIV_MASK) |
- ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
-
- if ((sih->chip == BCM4329_CHIP_ID)
- && sih->chiprev == 0) {
- /* clear the htstretch before clearing HTReqEn */
- AND_REG(&cc->clkstretch, ~CSTRETCH_HT);
- tmp &= ~PCTL_HT_REQ_EN;
- }
-
- W_REG(&cc->pmucontrol, tmp);
-}
-
-u32 si_pmu_ilp_clock(struct si_pub *sih)
-{
- static u32 ilpcycles_per_sec;
-
- if (ISSIM_ENAB(sih) || !PMUCTL_ENAB(sih))
- return ILP_CLOCK;
-
- if (ilpcycles_per_sec == 0) {
- u32 start, end, delta;
- u32 origidx = ai_coreidx(sih);
- chipcregs_t *cc = ai_setcoreidx(sih, SI_CC_IDX);
- start = R_REG(&cc->pmutimer);
- mdelay(ILP_CALC_DUR);
- end = R_REG(&cc->pmutimer);
- delta = end - start;
- ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
- ai_setcoreidx(sih, origidx);
- }
-
- return ilpcycles_per_sec;
-}
-
-void si_pmu_set_ldo_voltage(struct si_pub *sih, u8 ldo, u8 voltage)
-{
- u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
- u8 addr = 0;
-
- switch (sih->chip) {
- case BCM4336_CHIP_ID:
- switch (ldo) {
- case SET_LDO_VOLTAGE_CLDO_PWM:
- addr = 4;
- rc_shift = 1;
- mask = 0xf;
- break;
- case SET_LDO_VOLTAGE_CLDO_BURST:
- addr = 4;
- rc_shift = 5;
- mask = 0xf;
- break;
- case SET_LDO_VOLTAGE_LNLDO1:
- addr = 4;
- rc_shift = 17;
- mask = 0xf;
- break;
- default:
- return;
- }
- break;
- case BCM4330_CHIP_ID:
- switch (ldo) {
- case SET_LDO_VOLTAGE_CBUCK_PWM:
- addr = 3;
- rc_shift = 0;
- mask = 0x1f;
- break;
- default:
- return;
- }
- break;
- default:
- return;
- }
-
- shift = sr_cntl_shift + rc_shift;
-
- ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
- ~0, addr);
- ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
- mask << shift, (voltage & mask) << shift);
-}
-
-u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
-{
- uint delay = PMU_MAX_TRANSITION_DLY;
- chipcregs_t *cc;
- uint origidx;
-#ifdef BCMDBG
- char chn[8];
- chn[0] = 0; /* to suppress compile error */
-#endif
-
- /* Remember original core before switch to chipc */
- origidx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- case BCM4313_CHIP_ID:
- delay = ISSIM_ENAB(sih) ? 70 : 3700;
- break;
- case BCM4329_CHIP_ID:
- if (ISSIM_ENAB(sih))
- delay = 70;
- else {
- u32 ilp = si_pmu_ilp_clock(sih);
- delay =
- (si_pmu_res_uptime(sih, cc, RES4329_HT_AVAIL) +
- D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
- 1) / ilp);
- delay = (11 * delay) / 10;
- }
- break;
- case BCM4319_CHIP_ID:
- delay = ISSIM_ENAB(sih) ? 70 : 3700;
- break;
- case BCM4336_CHIP_ID:
- if (ISSIM_ENAB(sih))
- delay = 70;
- else {
- u32 ilp = si_pmu_ilp_clock(sih);
- delay =
- (si_pmu_res_uptime(sih, cc, RES4336_HT_AVAIL) +
- D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
- 1) / ilp);
- delay = (11 * delay) / 10;
- }
- break;
- case BCM4330_CHIP_ID:
- if (ISSIM_ENAB(sih))
- delay = 70;
- else {
- u32 ilp = si_pmu_ilp_clock(sih);
- delay =
- (si_pmu_res_uptime(sih, cc, RES4330_HT_AVAIL) +
- D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
- 1) / ilp);
- delay = (11 * delay) / 10;
- }
- break;
- default:
- break;
- }
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
-
- return (u16) delay;
-}
-
-void si_pmu_sprom_enable(struct si_pub *sih, bool enable)
-{
- chipcregs_t *cc;
- uint origidx;
-
- /* Remember original core before switch to chipc */
- origidx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
-}
-
-/* Read/write a chipcontrol reg */
-u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
-{
- ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
- reg);
- return ai_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_data), mask, val);
-}
-
-/* Read/write a regcontrol reg */
-u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
-{
- ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
- reg);
- return ai_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, regcontrol_data), mask, val);
-}
-
-/* Read/write a pllcontrol reg */
-u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val)
-{
- ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
- reg);
- return ai_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, pllcontrol_data), mask, val);
-}
-
-/* PMU PLL update */
-void si_pmu_pllupd(struct si_pub *sih)
-{
- ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
- PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
-}
-
-/* query alp/xtal clock frequency */
-u32 si_pmu_alp_clock(struct si_pub *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 clock = ALP_CLOCK;
-
- /* bail out with default */
- if (!PMUCTL_ENAB(sih))
- return clock;
-
- /* Remember original core before switch to chipc */
- origidx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- case BCM4716_CHIP_ID:
- case BCM4748_CHIP_ID:
- case BCM47162_CHIP_ID:
- case BCM4313_CHIP_ID:
- case BCM5357_CHIP_ID:
- /* always 20Mhz */
- clock = 20000 * 1000;
- break;
- case BCM4329_CHIP_ID:
- case BCM4319_CHIP_ID:
- case BCM4336_CHIP_ID:
- case BCM4330_CHIP_ID:
-
- clock = si_pmu1_alpclk0(sih, cc);
- break;
- case BCM5356_CHIP_ID:
- /* always 25Mhz */
- clock = 25000 * 1000;
- break;
- default:
- break;
- }
-
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
- return clock;
-}
-
-void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
-{
- chipcregs_t *cc;
- uint origidx, intr_val;
- u32 tmp = 0;
-
- /* Remember original core before switch to chipc */
- cc = (chipcregs_t *) ai_switch_core(sih, CC_CORE_ID, &origidx,
- &intr_val);
-
- /* force the HT off */
- if (sih->chip == BCM4336_CHIP_ID) {
- tmp = R_REG(&cc->max_res_mask);
- tmp &= ~RES4336_HT_AVAIL;
- W_REG(&cc->max_res_mask, tmp);
- /* wait for the ht to really go away */
- SPINWAIT(((R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL) == 0),
- 10000);
- }
-
- /* update the pll changes */
- si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
-
- /* enable HT back on */
- if (sih->chip == BCM4336_CHIP_ID) {
- tmp = R_REG(&cc->max_res_mask);
- tmp |= RES4336_HT_AVAIL;
- W_REG(&cc->max_res_mask, tmp);
- }
-
- /* Return to original core */
- ai_restore_core(sih, origidx, intr_val);
-}
-
-/* initialize PMU */
-void si_pmu_init(struct si_pub *sih)
-{
- chipcregs_t *cc;
- uint origidx;
-
- /* Remember original core before switch to chipc */
- origidx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- if (sih->pmurev == 1)
- AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
- else if (sih->pmurev >= 2)
- OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT);
-
- if ((sih->chip == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
- /* Fix for 4329b0 bad LPOM state. */
- W_REG(&cc->regcontrol_addr, 2);
- OR_REG(&cc->regcontrol_data, 0x100);
-
- W_REG(&cc->regcontrol_addr, 3);
- OR_REG(&cc->regcontrol_data, 0x4);
- }
-
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
-}
-
-/* initialize PMU chip controls and other chip level stuff */
-void si_pmu_chip_init(struct si_pub *sih)
-{
- uint origidx;
-
- /* Gate off SPROM clock and chip select signals */
- si_pmu_sprom_enable(sih, false);
-
- /* Remember original core */
- origidx = ai_coreidx(sih);
-
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
-}
-
-/* initialize PMU switch/regulators */
-void si_pmu_swreg_init(struct si_pub *sih)
-{
- switch (sih->chip) {
- case BCM4336_CHIP_ID:
- /* Reduce CLDO PWM output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
- /* Reduce CLDO BURST output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_BURST,
- 0xe);
- /* Reduce LNLDO1 output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_LNLDO1, 0xe);
- if (sih->chiprev == 0)
- si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
- break;
-
- case BCM4330_CHIP_ID:
- /* CBUCK Voltage is 1.8 by default and set that to 1.5 */
- si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
- break;
- default:
- break;
- }
-}
-
-/* initialize PLL */
-void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
-{
- chipcregs_t *cc;
- uint origidx;
-
- /* Remember original core before switch to chipc */
- origidx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- if (xtalfreq == 0)
- xtalfreq = 38400;
- si_pmu1_pllinit0(sih, cc, xtalfreq);
- break;
- case BCM4313_CHIP_ID:
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- /* ??? */
- break;
- case BCM4319_CHIP_ID:
- case BCM4336_CHIP_ID:
- case BCM4330_CHIP_ID:
- si_pmu1_pllinit0(sih, cc, xtalfreq);
- break;
- default:
- break;
- }
-
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
-}
-
-/* initialize PMU resources */
-void si_pmu_res_init(struct si_pub *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- const pmu_res_updown_t *pmu_res_updown_table = NULL;
- uint pmu_res_updown_table_sz = 0;
- const pmu_res_depend_t *pmu_res_depend_table = NULL;
- uint pmu_res_depend_table_sz = 0;
- u32 min_mask = 0, max_mask = 0;
- char name[8], *val;
- uint i, rsrcs;
-
- /* Remember original core before switch to chipc */
- origidx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- /* Optimize resources up/down timers */
- if (ISSIM_ENAB(sih)) {
- pmu_res_updown_table = NULL;
- pmu_res_updown_table_sz = 0;
- } else {
- pmu_res_updown_table = bcm4329_res_updown;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4329_res_updown);
- }
- /* Optimize resources dependencies */
- pmu_res_depend_table = bcm4329_res_depend;
- pmu_res_depend_table_sz = ARRAY_SIZE(bcm4329_res_depend);
- break;
-
- case BCM4319_CHIP_ID:
- /* Optimize resources up/down timers */
- if (ISSIM_ENAB(sih)) {
- pmu_res_updown_table = bcm4319a0_res_updown_qt;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4319a0_res_updown_qt);
- } else {
- pmu_res_updown_table = bcm4319a0_res_updown;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4319a0_res_updown);
- }
- /* Optimize resources dependancies masks */
- pmu_res_depend_table = bcm4319a0_res_depend;
- pmu_res_depend_table_sz = ARRAY_SIZE(bcm4319a0_res_depend);
- break;
-
- case BCM4336_CHIP_ID:
- /* Optimize resources up/down timers */
- if (ISSIM_ENAB(sih)) {
- pmu_res_updown_table = bcm4336a0_res_updown_qt;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4336a0_res_updown_qt);
- } else {
- pmu_res_updown_table = bcm4336a0_res_updown;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4336a0_res_updown);
- }
- /* Optimize resources dependancies masks */
- pmu_res_depend_table = bcm4336a0_res_depend;
- pmu_res_depend_table_sz = ARRAY_SIZE(bcm4336a0_res_depend);
- break;
-
- case BCM4330_CHIP_ID:
- /* Optimize resources up/down timers */
- if (ISSIM_ENAB(sih)) {
- pmu_res_updown_table = bcm4330a0_res_updown_qt;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4330a0_res_updown_qt);
- } else {
- pmu_res_updown_table = bcm4330a0_res_updown;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4330a0_res_updown);
- }
- /* Optimize resources dependancies masks */
- pmu_res_depend_table = bcm4330a0_res_depend;
- pmu_res_depend_table_sz = ARRAY_SIZE(bcm4330a0_res_depend);
- break;
-
- default:
- break;
- }
-
- /* # resources */
- rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
-
- /* Program up/down timers */
- while (pmu_res_updown_table_sz--) {
- W_REG(&cc->res_table_sel,
- pmu_res_updown_table[pmu_res_updown_table_sz].resnum);
- W_REG(&cc->res_updn_timer,
- pmu_res_updown_table[pmu_res_updown_table_sz].updown);
- }
- /* Apply nvram overrides to up/down timers */
- for (i = 0; i < rsrcs; i++) {
- snprintf(name, sizeof(name), "r%dt", i);
- val = getvar(NULL, name);
- if (val == NULL)
- continue;
- W_REG(&cc->res_table_sel, (u32) i);
- W_REG(&cc->res_updn_timer,
- (u32) simple_strtoul(val, NULL, 0));
- }
-
- /* Program resource dependencies table */
- while (pmu_res_depend_table_sz--) {
- if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL
- && !(pmu_res_depend_table[pmu_res_depend_table_sz].
- filter) (sih))
- continue;
- for (i = 0; i < rsrcs; i++) {
- if ((pmu_res_depend_table[pmu_res_depend_table_sz].
- res_mask & PMURES_BIT(i)) == 0)
- continue;
- W_REG(&cc->res_table_sel, i);
- switch (pmu_res_depend_table[pmu_res_depend_table_sz].
- action) {
- case RES_DEPEND_SET:
- W_REG(&cc->res_dep_mask,
- pmu_res_depend_table
- [pmu_res_depend_table_sz].depend_mask);
- break;
- case RES_DEPEND_ADD:
- OR_REG(&cc->res_dep_mask,
- pmu_res_depend_table
- [pmu_res_depend_table_sz].depend_mask);
- break;
- case RES_DEPEND_REMOVE:
- AND_REG(&cc->res_dep_mask,
- ~pmu_res_depend_table
- [pmu_res_depend_table_sz].depend_mask);
- break;
- default:
- break;
- }
- }
- }
- /* Apply nvram overrides to dependancies masks */
- for (i = 0; i < rsrcs; i++) {
- snprintf(name, sizeof(name), "r%dd", i);
- val = getvar(NULL, name);
- if (val == NULL)
- continue;
- W_REG(&cc->res_table_sel, (u32) i);
- W_REG(&cc->res_dep_mask,
- (u32) simple_strtoul(val, NULL, 0));
- }
-
- /* Determine min/max rsrc masks */
- si_pmu_res_masks(sih, &min_mask, &max_mask);
-
- /* It is required to program max_mask first and then min_mask */
-
- /* Program max resource mask */
-
- if (max_mask)
- W_REG(&cc->max_res_mask, max_mask);
-
- /* Program min resource mask */
-
- if (min_mask)
- W_REG(&cc->min_res_mask, min_mask);
-
- /* Add some delay; allow resources to come up and settle. */
- mdelay(2);
-
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
-}
-
-u32 si_pmu_measure_alpclk(struct si_pub *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 alp_khz;
-
- if (sih->pmurev < 10)
- return 0;
-
- /* Remember original core before switch to chipc */
- origidx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) {
- u32 ilp_ctr, alp_hz;
-
- /*
- * Enable the reg to measure the freq,
- * in case it was disabled before
- */
- W_REG(&cc->pmu_xtalfreq,
- 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
-
- /* Delay for well over 4 ILP clocks */
- udelay(1000);
-
- /* Read the latched number of ALP ticks per 4 ILP ticks */
- ilp_ctr =
- R_REG(&cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
-
- /*
- * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
- * bit to save power
- */
- W_REG(&cc->pmu_xtalfreq, 0);
-
- /* Calculate ALP frequency */
- alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
-
- /*
- * Round to nearest 100KHz, and at
- * the same time convert to KHz
- */
- alp_khz = (alp_hz + 50000) / 100000 * 100;
- } else
- alp_khz = 0;
-
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
-
- return alp_khz;
-}
-
-bool si_pmu_is_otp_powered(struct si_pub *sih)
-{
- uint idx;
- chipcregs_t *cc;
- bool st;
-
- /* Remember original core before switch to chipc */
- idx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- st = (R_REG(&cc->res_state) & PMURES_BIT(RES4329_OTP_PU))
- != 0;
- break;
- case BCM4319_CHIP_ID:
- st = (R_REG(&cc->res_state) & PMURES_BIT(RES4319_OTP_PU))
- != 0;
- break;
- case BCM4336_CHIP_ID:
- st = (R_REG(&cc->res_state) & PMURES_BIT(RES4336_OTP_PU))
- != 0;
- break;
- case BCM4330_CHIP_ID:
- st = (R_REG(&cc->res_state) & PMURES_BIT(RES4330_OTP_PU))
- != 0;
- break;
-
- /* These chip doesn't use PMU bit to power up/down OTP. OTP always on.
- * Use OTP_INIT command to reset/refresh state.
- */
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43238_CHIP_ID:
- st = true;
- break;
- default:
- st = true;
- break;
- }
-
- /* Return to original core */
- ai_setcoreidx(sih, idx);
- return st;
-}
-
-/* power up/down OTP through PMU resources */
-void si_pmu_otp_power(struct si_pub *sih, bool on)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
-
- /* Don't do anything if OTP is disabled */
- if (ai_is_otp_disabled(sih))
- return;
-
- /* Remember original core before switch to chipc */
- origidx = ai_coreidx(sih);
- cc = ai_setcoreidx(sih, SI_CC_IDX);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- rsrcs = PMURES_BIT(RES4329_OTP_PU);
- break;
- case BCM4319_CHIP_ID:
- rsrcs = PMURES_BIT(RES4319_OTP_PU);
- break;
- case BCM4336_CHIP_ID:
- rsrcs = PMURES_BIT(RES4336_OTP_PU);
- break;
- case BCM4330_CHIP_ID:
- rsrcs = PMURES_BIT(RES4330_OTP_PU);
- break;
- default:
- break;
- }
-
- if (rsrcs != 0) {
- u32 otps;
-
- /* Figure out the dependancies (exclude min_res_mask) */
- u32 deps = si_pmu_res_deps(sih, cc, rsrcs, true);
- u32 min_mask = 0, max_mask = 0;
- si_pmu_res_masks(sih, &min_mask, &max_mask);
- deps &= ~min_mask;
- /* Turn on/off the power */
- if (on) {
- OR_REG(&cc->min_res_mask, (rsrcs | deps));
- SPINWAIT(!(R_REG(&cc->res_state) & rsrcs),
- PMU_MAX_TRANSITION_DLY);
- } else {
- AND_REG(&cc->min_res_mask, ~(rsrcs | deps));
- }
-
- SPINWAIT((((otps = R_REG(&cc->otpstatus)) & OTPS_READY) !=
- (on ? OTPS_READY : 0)), 100);
- }
-
- /* Return to original core */
- ai_setcoreidx(sih, origidx);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-
-#ifndef _BRCM_PMU_H_
-#define _BRCM_PMU_H_
-
-#include <linux/types.h>
-
-#include <aiutils.h>
-
-/*
- * LDO selections used in si_pmu_set_ldo_voltage
- */
-#define SET_LDO_VOLTAGE_LDO1 1
-#define SET_LDO_VOLTAGE_LDO2 2
-#define SET_LDO_VOLTAGE_LDO3 3
-#define SET_LDO_VOLTAGE_PAREF 4
-#define SET_LDO_VOLTAGE_CLDO_PWM 5
-#define SET_LDO_VOLTAGE_CLDO_BURST 6
-#define SET_LDO_VOLTAGE_CBUCK_PWM 7
-#define SET_LDO_VOLTAGE_CBUCK_BURST 8
-#define SET_LDO_VOLTAGE_LNLDO1 9
-#define SET_LDO_VOLTAGE_LNLDO2_SEL 10
-
-extern void si_pmu_set_ldo_voltage(struct si_pub *sih, u8 ldo, u8 voltage);
-extern u16 si_pmu_fast_pwrup_delay(struct si_pub *sih);
-extern void si_pmu_sprom_enable(struct si_pub *sih, bool enable);
-extern u32 si_pmu_chipcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
-extern u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
-extern u32 si_pmu_ilp_clock(struct si_pub *sih);
-extern u32 si_pmu_alp_clock(struct si_pub *sih);
-extern void si_pmu_pllupd(struct si_pub *sih);
-extern void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid);
-extern u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
-extern void si_pmu_init(struct si_pub *sih);
-extern void si_pmu_chip_init(struct si_pub *sih);
-extern void si_pmu_pll_init(struct si_pub *sih, u32 xtalfreq);
-extern void si_pmu_res_init(struct si_pub *sih);
-extern void si_pmu_swreg_init(struct si_pub *sih);
-extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
-extern bool si_pmu_is_otp_powered(struct si_pub *sih);
-extern void si_pmu_otp_power(struct si_pub *sih, bool on);
-
-#endif /* _BRCM_PMU_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_PUB_H_
-#define _BRCM_PUB_H_
-
-#include "wlc_types.h" /* forward structure declarations */
-#include "brcmu_wifi.h" /* for chanspec_t */
-
-#define WLC_NUMRATES 16 /* max # of rates in a rateset */
-#define MAXMULTILIST 32 /* max # multicast addresses */
-#define D11_PHY_HDR_LEN 6 /* Phy header length - 6 bytes */
-
-/* phy types */
-#define PHY_TYPE_A 0 /* Phy type A */
-#define PHY_TYPE_G 2 /* Phy type G */
-#define PHY_TYPE_N 4 /* Phy type N */
-#define PHY_TYPE_LP 5 /* Phy type Low Power A/B/G */
-#define PHY_TYPE_SSN 6 /* Phy type Single Stream N */
-#define PHY_TYPE_LCN 8 /* Phy type Single Stream N */
-#define PHY_TYPE_LCNXN 9 /* Phy type 2-stream N */
-#define PHY_TYPE_HT 7 /* Phy type 3-Stream N */
-
-/* bw */
-#define WLC_10_MHZ 10 /* 10Mhz nphy channel bandwidth */
-#define WLC_20_MHZ 20 /* 20Mhz nphy channel bandwidth */
-#define WLC_40_MHZ 40 /* 40Mhz nphy channel bandwidth */
-
-#define CHSPEC_WLC_BW(chanspec) (CHSPEC_IS40(chanspec) ? WLC_40_MHZ : \
- CHSPEC_IS20(chanspec) ? WLC_20_MHZ : \
- WLC_10_MHZ)
-
-#define WLC_RSSI_MINVAL -200 /* Low value, e.g. for forcing roam */
-#define WLC_RSSI_NO_SIGNAL -91 /* NDIS RSSI link quality cutoffs */
-#define WLC_RSSI_VERY_LOW -80 /* Very low quality cutoffs */
-#define WLC_RSSI_LOW -70 /* Low quality cutoffs */
-#define WLC_RSSI_GOOD -68 /* Good quality cutoffs */
-#define WLC_RSSI_VERY_GOOD -58 /* Very good quality cutoffs */
-#define WLC_RSSI_EXCELLENT -57 /* Excellent quality cutoffs */
-
-#define WLC_PHYTYPE(_x) (_x) /* macro to perform WLC PHY -> D11 PHY TYPE, currently 1:1 */
-
-#define MA_WINDOW_SZ 8 /* moving average window size */
-
-#define WLC_SNR_INVALID 0 /* invalid SNR value */
-
-/* a large TX Power as an init value to factor out of min() calculations,
- * keep low enough to fit in an s8, units are .25 dBm
- */
-#define WLC_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
-
-/* rate related definitions */
-#define WLC_RATE_FLAG 0x80 /* Flag to indicate it is a basic rate */
-#define WLC_RATE_MASK 0x7f /* Rate value mask w/o basic rate flag */
-
-/* legacy rx Antenna diversity for SISO rates */
-#define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
-#define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
-#define ANT_RX_DIV_START_1 2 /* Choose starting with 1 */
-#define ANT_RX_DIV_START_0 3 /* Choose starting with 0 */
-#define ANT_RX_DIV_ENABLE 3 /* APHY bbConfig Enable RX Diversity */
-#define ANT_RX_DIV_DEF ANT_RX_DIV_START_0 /* default antdiv setting */
-
-/* legacy rx Antenna diversity for SISO rates */
-#define ANT_TX_FORCE_0 0 /* Tx on antenna 0, "legacy term Main" */
-#define ANT_TX_FORCE_1 1 /* Tx on antenna 1, "legacy term Aux" */
-#define ANT_TX_LAST_RX 3 /* Tx on phy's last good Rx antenna */
-#define ANT_TX_DEF 3 /* driver's default tx antenna setting */
-
-#define TXCORE_POLICY_ALL 0x1 /* use all available core for transmit */
-
-/* Tx Chain values */
-#define TXCHAIN_DEF 0x1 /* def bitmap of txchain */
-#define TXCHAIN_DEF_NPHY 0x3 /* default bitmap of tx chains for nphy */
-#define TXCHAIN_DEF_HTPHY 0x7 /* default bitmap of tx chains for nphy */
-#define RXCHAIN_DEF 0x1 /* def bitmap of rxchain */
-#define RXCHAIN_DEF_NPHY 0x3 /* default bitmap of rx chains for nphy */
-#define RXCHAIN_DEF_HTPHY 0x7 /* default bitmap of rx chains for nphy */
-#define ANTSWITCH_NONE 0 /* no antenna switch */
-#define ANTSWITCH_TYPE_1 1 /* antenna switch on 4321CB2, 2of3 */
-#define ANTSWITCH_TYPE_2 2 /* antenna switch on 4321MPCI, 2of3 */
-#define ANTSWITCH_TYPE_3 3 /* antenna switch on 4322, 2of3 */
-
-#define RXBUFSZ PKTBUFSZ
-#ifndef AIDMAPSZ
-#define AIDMAPSZ (roundup(MAXSCB, NBBY)/NBBY) /* aid bitmap size in bytes */
-#endif /* AIDMAPSZ */
-
-#define MAX_STREAMS_SUPPORTED 4 /* max number of streams supported */
-
-#define WL_SPURAVOID_OFF 0
-#define WL_SPURAVOID_ON1 1
-#define WL_SPURAVOID_ON2 2
-
-struct ieee80211_tx_queue_params;
-
-typedef struct wlc_tunables {
- int ntxd; /* size of tx descriptor table */
- int nrxd; /* size of rx descriptor table */
- int rxbufsz; /* size of rx buffers to post */
- int nrxbufpost; /* # of rx buffers to post */
- int maxscb; /* # of SCBs supported */
- int ampdunummpdu; /* max number of mpdu in an ampdu */
- int maxpktcb; /* max # of packet callbacks */
- int maxucodebss; /* max # of BSS handled in ucode bcn/prb */
- int maxucodebss4; /* max # of BSS handled in sw bcn/prb */
- int maxbss; /* max # of bss info elements in scan list */
- int datahiwat; /* data msg txq hiwat mark */
- int ampdudatahiwat; /* AMPDU msg txq hiwat mark */
- int rxbnd; /* max # of rx bufs to process before deferring to dpc */
- int txsbnd; /* max # tx status to process in wlc_txstatus() */
- int memreserved; /* memory reserved for BMAC's USB dma rx */
-} wlc_tunables_t;
-
-typedef struct wlc_rateset {
- uint count; /* number of rates in rates[] */
- u8 rates[WLC_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
- u8 htphy_membership; /* HT PHY Membership */
- u8 mcs[MCSSET_LEN]; /* supported mcs index bit map */
-} wlc_rateset_t;
-
-struct rsn_parms {
- u8 flags; /* misc booleans (e.g., supported) */
- u8 multicast; /* multicast cipher */
- u8 ucount; /* count of unicast ciphers */
- u8 unicast[4]; /* unicast ciphers */
- u8 acount; /* count of auth modes */
- u8 auth[4]; /* Authentication modes */
- u8 PAD[4]; /* padding for future growth */
-};
-
-/*
- * 32 SSID chars, max of 4 chars for each SSID char "\xFF", plus NULL.
- */
-#define SSID_FMT_BUF_LEN ((4 * IEEE80211_MAX_SSID_LEN) + 1)
-
-#define RSN_FLAGS_SUPPORTED 0x1 /* Flag for rsn_params */
-#define RSN_FLAGS_PREAUTH 0x2 /* Flag for WPA2 rsn_params */
-
-/* All the HT-specific default advertised capabilities (including AMPDU)
- * should be grouped here at one place
- */
-#define AMPDU_DEF_MPDU_DENSITY 6 /* default mpdu density (110 ==> 4us) */
-
-/* defaults for the HT (MIMO) bss */
-#define HT_CAP (IEEE80211_HT_CAP_SM_PS |\
- IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_GRN_FLD |\
- IEEE80211_HT_CAP_MAX_AMSDU | IEEE80211_HT_CAP_DSSSCCK40)
-
-/* wlc internal bss_info */
-typedef struct wlc_bss_info {
- u8 BSSID[ETH_ALEN]; /* network BSSID */
- u16 flags; /* flags for internal attributes */
- u8 SSID_len; /* the length of SSID */
- u8 SSID[32]; /* SSID string */
- s16 RSSI; /* receive signal strength (in dBm) */
- s16 SNR; /* receive signal SNR in dB */
- u16 beacon_period; /* units are Kusec */
- u16 atim_window; /* units are Kusec */
- chanspec_t chanspec; /* Channel num, bw, ctrl_sb and band */
- s8 infra; /* 0=IBSS, 1=infrastructure, 2=unknown */
- wlc_rateset_t rateset; /* supported rates */
- u8 dtim_period; /* DTIM period */
- s8 phy_noise; /* noise right after tx (in dBm) */
- u16 capability; /* Capability information */
- u8 wme_qosinfo; /* QoS Info from WME IE; valid if WLC_BSS_WME flag set */
- struct rsn_parms wpa;
- struct rsn_parms wpa2;
- u16 qbss_load_aac; /* qbss load available admission capacity */
- /* qbss_load_chan_free <- (0xff - channel_utilization of qbss_load_ie_t) */
- u8 qbss_load_chan_free; /* indicates how free the channel is */
- u8 mcipher; /* multicast cipher */
- u8 wpacfg; /* wpa config index */
-} wlc_bss_info_t;
-
-/* forward declarations */
-struct wlc_if;
-
-/* wlc_ioctl error codes */
-#define WLC_ENOIOCTL 1 /* No such Ioctl */
-#define WLC_EINVAL 2 /* Invalid value */
-#define WLC_ETOOSMALL 3 /* Value too small */
-#define WLC_ETOOBIG 4 /* Value too big */
-#define WLC_ERANGE 5 /* Out of range */
-#define WLC_EDOWN 6 /* Down */
-#define WLC_EUP 7 /* Up */
-#define WLC_ENOMEM 8 /* No Memory */
-#define WLC_EBUSY 9 /* Busy */
-
-/* IOVar flags for common error checks */
-#define IOVF_MFG (1<<3) /* flag for mfgtest iovars */
-#define IOVF_WHL (1<<4) /* value must be whole (0-max) */
-#define IOVF_NTRL (1<<5) /* value must be natural (1-max) */
-
-#define IOVF_SET_UP (1<<6) /* set requires driver be up */
-#define IOVF_SET_DOWN (1<<7) /* set requires driver be down */
-#define IOVF_SET_CLK (1<<8) /* set requires core clock */
-#define IOVF_SET_BAND (1<<9) /* set requires fixed band */
-
-#define IOVF_GET_UP (1<<10) /* get requires driver be up */
-#define IOVF_GET_DOWN (1<<11) /* get requires driver be down */
-#define IOVF_GET_CLK (1<<12) /* get requires core clock */
-#define IOVF_GET_BAND (1<<13) /* get requires fixed band */
-#define IOVF_OPEN_ALLOW (1<<14) /* set allowed iovar for opensrc */
-
-/* watchdog down and dump callback function proto's */
-typedef int (*watchdog_fn_t) (void *handle);
-typedef int (*down_fn_t) (void *handle);
-typedef int (*dump_fn_t) (void *handle, struct brcmu_strbuf *b);
-
-/* IOVar handler
- *
- * handle - a pointer value registered with the function
- * vi - iovar_info that was looked up
- * actionid - action ID, calculated by IOV_GVAL() and IOV_SVAL() based on varid.
- * name - the actual iovar name
- * params/plen - parameters and length for a get, input only.
- * arg/len - buffer and length for value to be set or retrieved, input or output.
- * vsize - value size, valid for integer type only.
- * wlcif - interface context (wlc_if pointer)
- *
- * All pointers may point into the same buffer.
- */
-typedef int (*iovar_fn_t) (void *handle, const struct brcmu_iovar *vi,
- u32 actionid, const char *name, void *params,
- uint plen, void *arg, int alen, int vsize,
- struct wlc_if *wlcif);
-
-#define MAC80211_PROMISC_BCNS (1 << 0)
-#define MAC80211_SCAN (1 << 1)
-
-/*
- * Public portion of "common" os-independent state structure.
- * The wlc handle points at this.
- */
-struct wlc_pub {
- void *wlc;
-
- struct ieee80211_hw *ieee_hw;
- struct scb *global_scb;
- scb_ampdu_t *global_ampdu;
- uint mac80211_state;
- uint unit; /* device instance number */
- uint corerev; /* core revision */
- struct si_pub *sih; /* SI handle (cookie for siutils calls) */
- char *vars; /* "environment" name=value */
- bool up; /* interface up and running */
- bool hw_off; /* HW is off */
- wlc_tunables_t *tunables; /* tunables: ntxd, nrxd, maxscb, etc. */
- bool hw_up; /* one time hw up/down(from boot or hibernation) */
- bool _piomode; /* true if pio mode *//* BMAC_NOTE: NEED In both */
- uint _nbands; /* # bands supported */
- uint now; /* # elapsed seconds */
-
- bool promisc; /* promiscuous destination address */
- bool delayed_down; /* down delayed */
- bool _ap; /* AP mode enabled */
- bool _apsta; /* simultaneous AP/STA mode enabled */
- bool _assoc_recreate; /* association recreation on up transitions */
- int _wme; /* WME QoS mode */
- u8 _mbss; /* MBSS mode on */
- bool allmulti; /* enable all multicasts */
- bool associated; /* true:part of [I]BSS, false: not */
- /* (union of stas_associated, aps_associated) */
- bool phytest_on; /* whether a PHY test is running */
- bool bf_preempt_4306; /* True to enable 'darwin' mode */
- bool _ampdu; /* ampdu enabled or not */
- bool _cac; /* 802.11e CAC enabled */
- u8 _n_enab; /* bitmap of 11N + HT support */
- bool _n_reqd; /* N support required for clients */
-
- s8 _coex; /* 20/40 MHz BSS Management AUTO, ENAB, DISABLE */
- bool _priofc; /* Priority-based flowcontrol */
-
- u8 cur_etheraddr[ETH_ALEN]; /* our local ethernet address */
-
- u8 *multicast; /* ptr to list of multicast addresses */
- uint nmulticast; /* # enabled multicast addresses */
-
- u32 wlfeatureflag; /* Flags to control sw features from registry */
- int psq_pkts_total; /* total num of ps pkts */
-
- u16 txmaxpkts; /* max number of large pkts allowed to be pending */
-
- /* s/w decryption counters */
- u32 swdecrypt; /* s/w decrypt attempts */
-
- int bcmerror; /* last bcm error */
-
- mbool radio_disabled; /* bit vector for radio disabled reasons */
- bool radio_active; /* radio on/off state */
- u16 roam_time_thresh; /* Max. # secs. of not hearing beacons
- * before roaming.
- */
- bool align_wd_tbtt; /* Align watchdog with tbtt indication
- * handling. This flag is cleared by default
- * and is set by per port code explicitly and
- * you need to make sure the OSL_SYSUPTIME()
- * is implemented properly in osl of that port
- * when it enables this Power Save feature.
- */
-
- u16 boardrev; /* version # of particular board */
- u8 sromrev; /* version # of the srom */
- char srom_ccode[WLC_CNTRY_BUF_SZ]; /* Country Code in SROM */
- u32 boardflags; /* Board specific flags from srom */
- u32 boardflags2; /* More board flags if sromrev >= 4 */
- bool tempsense_disable; /* disable periodic tempsense check */
- bool phy_11ncapable; /* the PHY/HW is capable of 802.11N */
- bool _ampdumac; /* mac assist ampdu enabled or not */
-
- struct wl_cnt *_cnt; /* low-level counters in driver */
-};
-
-/* wl_monitor rx status per packet */
-typedef struct wl_rxsts {
- uint pkterror; /* error flags per pkt */
- uint phytype; /* 802.11 A/B/G ... */
- uint channel; /* channel */
- uint datarate; /* rate in 500kbps */
- uint antenna; /* antenna pkts received on */
- uint pktlength; /* pkt length minus bcm phy hdr */
- u32 mactime; /* time stamp from mac, count per 1us */
- uint sq; /* signal quality */
- s32 signal; /* in dbm */
- s32 noise; /* in dbm */
- uint preamble; /* Unknown, short, long */
- uint encoding; /* Unknown, CCK, PBCC, OFDM */
- uint nfrmtype; /* special 802.11n frames(AMPDU, AMSDU) */
- struct brcms_if *wlif; /* wl interface */
-} wl_rxsts_t;
-
-/* status per error RX pkt */
-#define WL_RXS_CRC_ERROR 0x00000001 /* CRC Error in packet */
-#define WL_RXS_RUNT_ERROR 0x00000002 /* Runt packet */
-#define WL_RXS_ALIGN_ERROR 0x00000004 /* Misaligned packet */
-#define WL_RXS_OVERSIZE_ERROR 0x00000008 /* packet bigger than RX_LENGTH (usually 1518) */
-#define WL_RXS_WEP_ICV_ERROR 0x00000010 /* Integrity Check Value error */
-#define WL_RXS_WEP_ENCRYPTED 0x00000020 /* Encrypted with WEP */
-#define WL_RXS_PLCP_SHORT 0x00000040 /* Short PLCP error */
-#define WL_RXS_DECRYPT_ERR 0x00000080 /* Decryption error */
-#define WL_RXS_OTHER_ERR 0x80000000 /* Other errors */
-
-/* phy type */
-#define WL_RXS_PHY_A 0x00000000 /* A phy type */
-#define WL_RXS_PHY_B 0x00000001 /* B phy type */
-#define WL_RXS_PHY_G 0x00000002 /* G phy type */
-#define WL_RXS_PHY_N 0x00000004 /* N phy type */
-
-/* encoding */
-#define WL_RXS_ENCODING_CCK 0x00000000 /* CCK encoding */
-#define WL_RXS_ENCODING_OFDM 0x00000001 /* OFDM encoding */
-
-/* preamble */
-#define WL_RXS_UNUSED_STUB 0x0 /* stub to match with wlc_ethereal.h */
-#define WL_RXS_PREAMBLE_SHORT 0x00000001 /* Short preamble */
-#define WL_RXS_PREAMBLE_LONG 0x00000002 /* Long preamble */
-#define WL_RXS_PREAMBLE_MIMO_MM 0x00000003 /* MIMO mixed mode preamble */
-#define WL_RXS_PREAMBLE_MIMO_GF 0x00000004 /* MIMO green field preamble */
-
-#define WL_RXS_NFRM_AMPDU_FIRST 0x00000001 /* first MPDU in A-MPDU */
-#define WL_RXS_NFRM_AMPDU_SUB 0x00000002 /* subsequent MPDU(s) in A-MPDU */
-#define WL_RXS_NFRM_AMSDU_FIRST 0x00000004 /* first MSDU in A-MSDU */
-#define WL_RXS_NFRM_AMSDU_SUB 0x00000008 /* subsequent MSDU(s) in A-MSDU */
-
-enum wlc_par_id {
- IOV_MPC = 1,
- IOV_RTSTHRESH,
- IOV_QTXPOWER,
- IOV_BCN_LI_BCN /* Beacon listen interval in # of beacons */
-};
-
-/* forward declare and use the struct notation so we don't have to
- * have it defined if not necessary.
- */
-struct wlc_info;
-struct wlc_hw_info;
-struct wlc_bsscfg;
-struct wlc_if;
-
-/***********************************************
- * Feature-related macros to optimize out code *
- * *********************************************
- */
-
-/* AP Support (versus STA) */
-#define AP_ENAB(pub) (0)
-
-/* Macro to check if APSTA mode enabled */
-#define APSTA_ENAB(pub) (0)
-
-/* Some useful combinations */
-#define STA_ONLY(pub) (!AP_ENAB(pub))
-#define AP_ONLY(pub) (AP_ENAB(pub) && !APSTA_ENAB(pub))
-
-#define ENAB_1x1 0x01
-#define ENAB_2x2 0x02
-#define ENAB_3x3 0x04
-#define ENAB_4x4 0x08
-#define SUPPORT_11N (ENAB_1x1|ENAB_2x2)
-#define SUPPORT_HT (ENAB_1x1|ENAB_2x2|ENAB_3x3)
-/* WL11N Support */
-#if ((defined(NCONF) && (NCONF != 0)) || (defined(LCNCONF) && (LCNCONF != 0)) || \
- (defined(HTCONF) && (HTCONF != 0)) || (defined(SSLPNCONF) && (SSLPNCONF != 0)))
-#define N_ENAB(pub) ((pub)->_n_enab & SUPPORT_11N)
-#define N_REQD(pub) ((pub)->_n_reqd)
-#else
-#define N_ENAB(pub) 0
-#define N_REQD(pub) 0
-#endif
-
-#if (defined(HTCONF) && (HTCONF != 0))
-#define HT_ENAB(pub) (((pub)->_n_enab & SUPPORT_HT) == SUPPORT_HT)
-#else
-#define HT_ENAB(pub) 0
-#endif
-
-#define AMPDU_AGG_HOST 1
-#define AMPDU_ENAB(pub) ((pub)->_ampdu)
-
-#define EDCF_ENAB(pub) (WME_ENAB(pub))
-#define QOS_ENAB(pub) (WME_ENAB(pub) || N_ENAB(pub))
-
-#define MONITOR_ENAB(wlc) ((wlc)->monitor)
-
-#define PROMISC_ENAB(wlc) ((wlc)->promisc)
-
-#define WLC_PREC_COUNT 16 /* Max precedence level implemented */
-
-/* pri is priority encoded in the packet. This maps the Packet priority to
- * enqueue precedence as defined in wlc_prec_map
- */
-extern const u8 wlc_prio2prec_map[];
-#define WLC_PRIO_TO_PREC(pri) wlc_prio2prec_map[(pri) & 7]
-
-/* This maps priority to one precedence higher - Used by PS-Poll response packets to
- * simulate enqueue-at-head operation, but still maintain the order on the queue
- */
-#define WLC_PRIO_TO_HI_PREC(pri) min(WLC_PRIO_TO_PREC(pri) + 1, WLC_PREC_COUNT - 1)
-
-extern const u8 wme_fifo2ac[];
-#define WME_PRIO2AC(prio) wme_fifo2ac[prio2fifo[(prio)]]
-
-/* Mask to describe all precedence levels */
-#define WLC_PREC_BMP_ALL MAXBITVAL(WLC_PREC_COUNT)
-
-/* Define a bitmap of precedences comprised by each AC */
-#define WLC_PREC_BMP_AC_BE (NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_BE)) | \
- NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_BE)) | \
- NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_EE)) | \
- NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_EE)))
-#define WLC_PREC_BMP_AC_BK (NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_BK)) | \
- NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_BK)) | \
- NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_NONE)) | \
- NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_NONE)))
-#define WLC_PREC_BMP_AC_VI (NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_CL)) | \
- NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_CL)) | \
- NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_VI)) | \
- NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_VI)))
-#define WLC_PREC_BMP_AC_VO (NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_VO)) | \
- NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_VO)) | \
- NBITVAL(WLC_PRIO_TO_PREC(PRIO_8021D_NC)) | \
- NBITVAL(WLC_PRIO_TO_HI_PREC(PRIO_8021D_NC)))
-
-/* WME Support */
-#define WME_ENAB(pub) ((pub)->_wme != OFF)
-#define WME_AUTO(wlc) ((wlc)->pub->_wme == AUTO)
-
-#define WLC_USE_COREFLAGS 0xffffffff /* invalid core flags, use the saved coreflags */
-
-
-/* network protection config */
-#define WLC_PROT_G_SPEC 1 /* SPEC g protection */
-#define WLC_PROT_G_OVR 2 /* SPEC g prot override */
-#define WLC_PROT_G_USER 3 /* gmode specified by user */
-#define WLC_PROT_OVERLAP 4 /* overlap */
-#define WLC_PROT_N_USER 10 /* nmode specified by user */
-#define WLC_PROT_N_CFG 11 /* n protection */
-#define WLC_PROT_N_CFG_OVR 12 /* n protection override */
-#define WLC_PROT_N_NONGF 13 /* non-GF protection */
-#define WLC_PROT_N_NONGF_OVR 14 /* non-GF protection override */
-#define WLC_PROT_N_PAM_OVR 15 /* n preamble override */
-#define WLC_PROT_N_OBSS 16 /* non-HT OBSS present */
-
-/*
- * 54g modes (basic bits may still be overridden)
- *
- * GMODE_LEGACY_B Rateset: 1b, 2b, 5.5, 11
- * Preamble: Long
- * Shortslot: Off
- * GMODE_AUTO Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
- * Extended Rateset: 6, 9, 12, 48
- * Preamble: Long
- * Shortslot: Auto
- * GMODE_ONLY Rateset: 1b, 2b, 5.5b, 11b, 18, 24b, 36, 54
- * Extended Rateset: 6b, 9, 12b, 48
- * Preamble: Short required
- * Shortslot: Auto
- * GMODE_B_DEFERRED Rateset: 1b, 2b, 5.5b, 11b, 18, 24, 36, 54
- * Extended Rateset: 6, 9, 12, 48
- * Preamble: Long
- * Shortslot: On
- * GMODE_PERFORMANCE Rateset: 1b, 2b, 5.5b, 6b, 9, 11b, 12b, 18, 24b, 36, 48, 54
- * Preamble: Short required
- * Shortslot: On and required
- * GMODE_LRS Rateset: 1b, 2b, 5.5b, 11b
- * Extended Rateset: 6, 9, 12, 18, 24, 36, 48, 54
- * Preamble: Long
- * Shortslot: Auto
- */
-#define GMODE_LEGACY_B 0
-#define GMODE_AUTO 1
-#define GMODE_ONLY 2
-#define GMODE_B_DEFERRED 3
-#define GMODE_PERFORMANCE 4
-#define GMODE_LRS 5
-#define GMODE_MAX 6
-
-/* values for PLCPHdr_override */
-#define WLC_PLCP_AUTO -1
-#define WLC_PLCP_SHORT 0
-#define WLC_PLCP_LONG 1
-
-/* values for g_protection_override and n_protection_override */
-#define WLC_PROTECTION_AUTO -1
-#define WLC_PROTECTION_OFF 0
-#define WLC_PROTECTION_ON 1
-#define WLC_PROTECTION_MMHDR_ONLY 2
-#define WLC_PROTECTION_CTS_ONLY 3
-
-/* values for g_protection_control and n_protection_control */
-#define WLC_PROTECTION_CTL_OFF 0
-#define WLC_PROTECTION_CTL_LOCAL 1
-#define WLC_PROTECTION_CTL_OVERLAP 2
-
-/* values for n_protection */
-#define WLC_N_PROTECTION_OFF 0
-#define WLC_N_PROTECTION_OPTIONAL 1
-#define WLC_N_PROTECTION_20IN40 2
-#define WLC_N_PROTECTION_MIXEDMODE 3
-
-/* values for band specific 40MHz capabilities */
-#define WLC_N_BW_20ALL 0
-#define WLC_N_BW_40ALL 1
-#define WLC_N_BW_20IN2G_40IN5G 2
-
-/* bitflags for SGI support (sgi_rx iovar) */
-#define WLC_N_SGI_20 0x01
-#define WLC_N_SGI_40 0x02
-
-/* defines used by the nrate iovar */
-#define NRATE_MCS_INUSE 0x00000080 /* MSC in use,indicates b0-6 holds an mcs */
-#define NRATE_RATE_MASK 0x0000007f /* rate/mcs value */
-#define NRATE_STF_MASK 0x0000ff00 /* stf mode mask: siso, cdd, stbc, sdm */
-#define NRATE_STF_SHIFT 8 /* stf mode shift */
-#define NRATE_OVERRIDE 0x80000000 /* bit indicates override both rate & mode */
-#define NRATE_OVERRIDE_MCS_ONLY 0x40000000 /* bit indicate to override mcs only */
-#define NRATE_SGI_MASK 0x00800000 /* sgi mode */
-#define NRATE_SGI_SHIFT 23 /* sgi mode */
-#define NRATE_LDPC_CODING 0x00400000 /* bit indicates adv coding in use */
-#define NRATE_LDPC_SHIFT 22 /* ldpc shift */
-
-#define NRATE_STF_SISO 0 /* stf mode SISO */
-#define NRATE_STF_CDD 1 /* stf mode CDD */
-#define NRATE_STF_STBC 2 /* stf mode STBC */
-#define NRATE_STF_SDM 3 /* stf mode SDM */
-
-#define ANT_SELCFG_MAX 4 /* max number of antenna configurations */
-
-#define HIGHEST_SINGLE_STREAM_MCS 7 /* MCS values greater than this enable multiple streams */
-
-typedef struct {
- u8 ant_config[ANT_SELCFG_MAX]; /* antenna configuration */
- u8 num_antcfg; /* number of available antenna configurations */
-} wlc_antselcfg_t;
-
-/* common functions for every port */
-extern void *wlc_attach(struct brcms_info *wl, u16 vendor, u16 device,
- uint unit, bool piomode, void *regsva, uint bustype,
- void *btparam, uint *perr);
-extern uint wlc_detach(struct wlc_info *wlc);
-extern int wlc_up(struct wlc_info *wlc);
-extern uint wlc_down(struct wlc_info *wlc);
-
-extern int wlc_set(struct wlc_info *wlc, int cmd, int arg);
-extern int wlc_get(struct wlc_info *wlc, int cmd, int *arg);
-extern bool wlc_chipmatch(u16 vendor, u16 device);
-extern void wlc_init(struct wlc_info *wlc);
-extern void wlc_reset(struct wlc_info *wlc);
-
-extern void wlc_intrson(struct wlc_info *wlc);
-extern u32 wlc_intrsoff(struct wlc_info *wlc);
-extern void wlc_intrsrestore(struct wlc_info *wlc, u32 macintmask);
-extern bool wlc_intrsupd(struct wlc_info *wlc);
-extern bool wlc_isr(struct wlc_info *wlc, bool *wantdpc);
-extern bool wlc_dpc(struct wlc_info *wlc, bool bounded);
-extern bool wlc_sendpkt_mac80211(struct wlc_info *wlc, struct sk_buff *sdu,
- struct ieee80211_hw *hw);
-extern int wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
- struct wlc_if *wlcif);
-extern bool wlc_aggregatable(struct wlc_info *wlc, u8 tid);
-
-/* helper functions */
-extern void wlc_statsupd(struct wlc_info *wlc);
-extern void wlc_protection_upd(struct wlc_info *wlc, uint idx, int val);
-extern int wlc_get_header_len(void);
-extern void wlc_mac_bcn_promisc_change(struct wlc_info *wlc, bool promisc);
-extern void wlc_set_addrmatch(struct wlc_info *wlc, int match_reg_offset,
- const u8 *addr);
-extern void wlc_wme_setparams(struct wlc_info *wlc, u16 aci,
- const struct ieee80211_tx_queue_params *arg,
- bool suspend);
-extern struct wlc_pub *wlc_pub(void *wlc);
-
-/* common functions for every port */
-extern void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val,
- int bands);
-extern void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset);
-extern void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs);
-
-struct ieee80211_sta;
-extern void wlc_ampdu_flush(struct wlc_info *wlc, struct ieee80211_sta *sta,
- u16 tid);
-extern int wlc_set_par(struct wlc_info *wlc, enum wlc_par_id par_id, int val);
-extern int wlc_get_par(struct wlc_info *wlc, enum wlc_par_id par_id, int *ret_int_ptr);
-extern char *getvar(char *vars, const char *name);
-extern int getintvar(char *vars, const char *name);
-
-/* wlc_phy.c helper functions */
-extern void wlc_set_ps_ctrl(struct wlc_info *wlc);
-extern void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val);
-
-extern int wlc_module_register(struct wlc_pub *pub,
- const char *name, void *hdl,
- watchdog_fn_t watchdog_fn, down_fn_t down_fn);
-extern int wlc_module_unregister(struct wlc_pub *pub, const char *name,
- void *hdl);
-extern void wlc_suspend_mac_and_wait(struct wlc_info *wlc);
-extern void wlc_enable_mac(struct wlc_info *wlc);
-extern void wlc_associate_upd(struct wlc_info *wlc, bool state);
-extern void wlc_scan_start(struct wlc_info *wlc);
-extern void wlc_scan_stop(struct wlc_info *wlc);
-extern int wlc_get_curband(struct wlc_info *wlc);
-extern void wlc_wait_for_tx_completion(struct wlc_info *wlc, bool drop);
-
-/* helper functions */
-extern bool wlc_check_radio_disabled(struct wlc_info *wlc);
-extern bool wlc_radio_monitor_stop(struct wlc_info *wlc);
-
-#define MAXBANDS 2 /* Maximum #of bands */
-/* bandstate array indices */
-#define BAND_2G_INDEX 0 /* wlc->bandstate[x] index */
-#define BAND_5G_INDEX 1 /* wlc->bandstate[x] index */
-
-#define BAND_2G_NAME "2.4G"
-#define BAND_5G_NAME "5G"
-
-/* BMAC RPC: 7 u32 params: pkttotlen, fifo, commit, fid, txpktpend, pktflag, rpc_id */
-#define WLC_RPCTX_PARAMS 32
-
-#endif /* _BRCM_PUB_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <bcmdefs.h>
-#include <brcmu_utils.h>
-#include <aiutils.h>
-#include "bcmdma.h"
-
-#include "wlc_types.h"
-#include "d11.h"
-#include "wlc_cfg.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "wlc_rate.h"
-
-/* Rate info per rate: It tells whether a rate is ofdm or not and its phy_rate value */
-const u8 rate_info[WLC_MAXRATE + 1] = {
- /* 0 1 2 3 4 5 6 7 8 9 */
-/* 0 */ 0x00, 0x00, 0x0a, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 10 */ 0x00, 0x37, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x00,
-/* 20 */ 0x00, 0x00, 0x6e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, 0x00, 0x00,
-/* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00,
-/* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 70 */ 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-/* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00,
-/* 100 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8c
-};
-
-/* rates are in units of Kbps */
-const mcs_info_t mcs_table[MCS_TABLE_SIZE] = {
- /* MCS 0: SS 1, MOD: BPSK, CR 1/2 */
- {6500, 13500, CEIL(6500 * 10, 9), CEIL(13500 * 10, 9), 0x00,
- WLC_RATE_6M},
- /* MCS 1: SS 1, MOD: QPSK, CR 1/2 */
- {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x08,
- WLC_RATE_12M},
- /* MCS 2: SS 1, MOD: QPSK, CR 3/4 */
- {19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x0A,
- WLC_RATE_18M},
- /* MCS 3: SS 1, MOD: 16QAM, CR 1/2 */
- {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x10,
- WLC_RATE_24M},
- /* MCS 4: SS 1, MOD: 16QAM, CR 3/4 */
- {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x12,
- WLC_RATE_36M},
- /* MCS 5: SS 1, MOD: 64QAM, CR 2/3 */
- {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x19,
- WLC_RATE_48M},
- /* MCS 6: SS 1, MOD: 64QAM, CR 3/4 */
- {58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x1A,
- WLC_RATE_54M},
- /* MCS 7: SS 1, MOD: 64QAM, CR 5/6 */
- {65000, 135000, CEIL(65000 * 10, 9), CEIL(135000 * 10, 9), 0x1C,
- WLC_RATE_54M},
- /* MCS 8: SS 2, MOD: BPSK, CR 1/2 */
- {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x40,
- WLC_RATE_6M},
- /* MCS 9: SS 2, MOD: QPSK, CR 1/2 */
- {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x48,
- WLC_RATE_12M},
- /* MCS 10: SS 2, MOD: QPSK, CR 3/4 */
- {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x4A,
- WLC_RATE_18M},
- /* MCS 11: SS 2, MOD: 16QAM, CR 1/2 */
- {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x50,
- WLC_RATE_24M},
- /* MCS 12: SS 2, MOD: 16QAM, CR 3/4 */
- {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0x52,
- WLC_RATE_36M},
- /* MCS 13: SS 2, MOD: 64QAM, CR 2/3 */
- {104000, 216000, CEIL(104000 * 10, 9), CEIL(216000 * 10, 9), 0x59,
- WLC_RATE_48M},
- /* MCS 14: SS 2, MOD: 64QAM, CR 3/4 */
- {117000, 243000, CEIL(117000 * 10, 9), CEIL(243000 * 10, 9), 0x5A,
- WLC_RATE_54M},
- /* MCS 15: SS 2, MOD: 64QAM, CR 5/6 */
- {130000, 270000, CEIL(130000 * 10, 9), CEIL(270000 * 10, 9), 0x5C,
- WLC_RATE_54M},
- /* MCS 16: SS 3, MOD: BPSK, CR 1/2 */
- {19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x80,
- WLC_RATE_6M},
- /* MCS 17: SS 3, MOD: QPSK, CR 1/2 */
- {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x88,
- WLC_RATE_12M},
- /* MCS 18: SS 3, MOD: QPSK, CR 3/4 */
- {58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x8A,
- WLC_RATE_18M},
- /* MCS 19: SS 3, MOD: 16QAM, CR 1/2 */
- {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0x90,
- WLC_RATE_24M},
- /* MCS 20: SS 3, MOD: 16QAM, CR 3/4 */
- {117000, 243000, CEIL(117000 * 10, 9), CEIL(243000 * 10, 9), 0x92,
- WLC_RATE_36M},
- /* MCS 21: SS 3, MOD: 64QAM, CR 2/3 */
- {156000, 324000, CEIL(156000 * 10, 9), CEIL(324000 * 10, 9), 0x99,
- WLC_RATE_48M},
- /* MCS 22: SS 3, MOD: 64QAM, CR 3/4 */
- {175500, 364500, CEIL(175500 * 10, 9), CEIL(364500 * 10, 9), 0x9A,
- WLC_RATE_54M},
- /* MCS 23: SS 3, MOD: 64QAM, CR 5/6 */
- {195000, 405000, CEIL(195000 * 10, 9), CEIL(405000 * 10, 9), 0x9B,
- WLC_RATE_54M},
- /* MCS 24: SS 4, MOD: BPSK, CR 1/2 */
- {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0xC0,
- WLC_RATE_6M},
- /* MCS 25: SS 4, MOD: QPSK, CR 1/2 */
- {52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0xC8,
- WLC_RATE_12M},
- /* MCS 26: SS 4, MOD: QPSK, CR 3/4 */
- {78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0xCA,
- WLC_RATE_18M},
- /* MCS 27: SS 4, MOD: 16QAM, CR 1/2 */
- {104000, 216000, CEIL(104000 * 10, 9), CEIL(216000 * 10, 9), 0xD0,
- WLC_RATE_24M},
- /* MCS 28: SS 4, MOD: 16QAM, CR 3/4 */
- {156000, 324000, CEIL(156000 * 10, 9), CEIL(324000 * 10, 9), 0xD2,
- WLC_RATE_36M},
- /* MCS 29: SS 4, MOD: 64QAM, CR 2/3 */
- {208000, 432000, CEIL(208000 * 10, 9), CEIL(432000 * 10, 9), 0xD9,
- WLC_RATE_48M},
- /* MCS 30: SS 4, MOD: 64QAM, CR 3/4 */
- {234000, 486000, CEIL(234000 * 10, 9), CEIL(486000 * 10, 9), 0xDA,
- WLC_RATE_54M},
- /* MCS 31: SS 4, MOD: 64QAM, CR 5/6 */
- {260000, 540000, CEIL(260000 * 10, 9), CEIL(540000 * 10, 9), 0xDB,
- WLC_RATE_54M},
- /* MCS 32: SS 1, MOD: BPSK, CR 1/2 */
- {0, 6000, 0, CEIL(6000 * 10, 9), 0x00, WLC_RATE_6M},
-};
-
-/* phycfg for legacy OFDM frames: code rate, modulation scheme, spatial streams
- * Number of spatial streams: always 1
- * other fields: refer to table 78 of section 17.3.2.2 of the original .11a standard
- */
-typedef struct legacy_phycfg {
- u32 rate_ofdm; /* ofdm mac rate */
- u8 tx_phy_ctl3; /* phy ctl byte 3, code rate, modulation type, # of streams */
-} legacy_phycfg_t;
-
-#define LEGACY_PHYCFG_TABLE_SIZE 12 /* Number of legacy_rate_cfg entries in the table */
-
-/* In CCK mode LPPHY overloads OFDM Modulation bits with CCK Data Rate */
-/* Eventually MIMOPHY would also be converted to this format */
-/* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
-static const legacy_phycfg_t legacy_phycfg_table[LEGACY_PHYCFG_TABLE_SIZE] = {
- {WLC_RATE_1M, 0x00}, /* CCK 1Mbps, data rate 0 */
- {WLC_RATE_2M, 0x08}, /* CCK 2Mbps, data rate 1 */
- {WLC_RATE_5M5, 0x10}, /* CCK 5.5Mbps, data rate 2 */
- {WLC_RATE_11M, 0x18}, /* CCK 11Mbps, data rate 3 */
- {WLC_RATE_6M, 0x00}, /* OFDM 6Mbps, code rate 1/2, BPSK, 1 spatial stream */
- {WLC_RATE_9M, 0x02}, /* OFDM 9Mbps, code rate 3/4, BPSK, 1 spatial stream */
- {WLC_RATE_12M, 0x08}, /* OFDM 12Mbps, code rate 1/2, QPSK, 1 spatial stream */
- {WLC_RATE_18M, 0x0A}, /* OFDM 18Mbps, code rate 3/4, QPSK, 1 spatial stream */
- {WLC_RATE_24M, 0x10}, /* OFDM 24Mbps, code rate 1/2, 16-QAM, 1 spatial stream */
- {WLC_RATE_36M, 0x12}, /* OFDM 36Mbps, code rate 3/4, 16-QAM, 1 spatial stream */
- {WLC_RATE_48M, 0x19}, /* OFDM 48Mbps, code rate 2/3, 64-QAM, 1 spatial stream */
- {WLC_RATE_54M, 0x1A}, /* OFDM 54Mbps, code rate 3/4, 64-QAM, 1 spatial stream */
-};
-
-/* Hardware rates (also encodes default basic rates) */
-
-const wlc_rateset_t cck_ofdm_mimo_rates = {
- 12,
- { /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48, 54 Mbps */
- 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
- 0x6c},
- 0x00,
- {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-const wlc_rateset_t ofdm_mimo_rates = {
- 8,
- { /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
- 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
- 0x00,
- {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-/* Default ratesets that include MCS32 for 40BW channels */
-const wlc_rateset_t cck_ofdm_40bw_mimo_rates = {
- 12,
- { /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48, 54 Mbps */
- 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
- 0x6c},
- 0x00,
- {0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-const wlc_rateset_t ofdm_40bw_mimo_rates = {
- 8,
- { /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
- 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
- 0x00,
- {0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-const wlc_rateset_t cck_ofdm_rates = {
- 12,
- { /* 1b, 2b, 5.5b, 6, 9, 11b, 12, 18, 24, 36, 48, 54 Mbps */
- 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
- 0x6c},
- 0x00,
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-const wlc_rateset_t gphy_legacy_rates = {
- 4,
- { /* 1b, 2b, 5.5b, 11b Mbps */
- 0x82, 0x84, 0x8b, 0x96},
- 0x00,
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-const wlc_rateset_t ofdm_rates = {
- 8,
- { /* 6b, 9, 12b, 18, 24b, 36, 48, 54 Mbps */
- 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
- 0x00,
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-const wlc_rateset_t cck_rates = {
- 4,
- { /* 1b, 2b, 5.5, 11 Mbps */
- 0x82, 0x84, 0x0b, 0x16},
- 0x00,
- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00}
-};
-
-static bool wlc_rateset_valid(wlc_rateset_t *rs, bool check_brate);
-
-/* check if rateset is valid.
- * if check_brate is true, rateset without a basic rate is considered NOT valid.
- */
-static bool wlc_rateset_valid(wlc_rateset_t *rs, bool check_brate)
-{
- uint idx;
-
- if (!rs->count)
- return false;
-
- if (!check_brate)
- return true;
-
- /* error if no basic rates */
- for (idx = 0; idx < rs->count; idx++) {
- if (rs->rates[idx] & WLC_RATE_FLAG)
- return true;
- }
- return false;
-}
-
-void wlc_rateset_mcs_upd(wlc_rateset_t *rs, u8 txstreams)
-{
- int i;
- for (i = txstreams; i < MAX_STREAMS_SUPPORTED; i++)
- rs->mcs[i] = 0;
-}
-
-/* filter based on hardware rateset, and sort filtered rateset with basic bit(s) preserved,
- * and check if resulting rateset is valid.
-*/
-bool
-wlc_rate_hwrs_filter_sort_validate(wlc_rateset_t *rs,
- const wlc_rateset_t *hw_rs,
- bool check_brate, u8 txstreams)
-{
- u8 rateset[WLC_MAXRATE + 1];
- u8 r;
- uint count;
- uint i;
-
- memset(rateset, 0, sizeof(rateset));
- count = rs->count;
-
- for (i = 0; i < count; i++) {
- /* mask off "basic rate" bit, WLC_RATE_FLAG */
- r = (int)rs->rates[i] & WLC_RATE_MASK;
- if ((r > WLC_MAXRATE) || (rate_info[r] == 0)) {
- continue;
- }
- rateset[r] = rs->rates[i]; /* preserve basic bit! */
- }
-
- /* fill out the rates in order, looking at only supported rates */
- count = 0;
- for (i = 0; i < hw_rs->count; i++) {
- r = hw_rs->rates[i] & WLC_RATE_MASK;
- if (rateset[r])
- rs->rates[count++] = rateset[r];
- }
-
- rs->count = count;
-
- /* only set the mcs rate bit if the equivalent hw mcs bit is set */
- for (i = 0; i < MCSSET_LEN; i++)
- rs->mcs[i] = (rs->mcs[i] & hw_rs->mcs[i]);
-
- if (wlc_rateset_valid(rs, check_brate))
- return true;
- else
- return false;
-}
-
-/* calculate the rate of a rx'd frame and return it as a ratespec */
-ratespec_t wlc_compute_rspec(d11rxhdr_t *rxh, u8 *plcp)
-{
- int phy_type;
- ratespec_t rspec = PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT;
-
- phy_type =
- ((rxh->RxChan & RXS_CHAN_PHYTYPE_MASK) >> RXS_CHAN_PHYTYPE_SHIFT);
-
- if ((phy_type == PHY_TYPE_N) || (phy_type == PHY_TYPE_SSN) ||
- (phy_type == PHY_TYPE_LCN) || (phy_type == PHY_TYPE_HT)) {
- switch (rxh->PhyRxStatus_0 & PRXS0_FT_MASK) {
- case PRXS0_CCK:
- rspec =
- CCK_PHY2MAC_RATE(((cck_phy_hdr_t *) plcp)->signal);
- break;
- case PRXS0_OFDM:
- rspec =
- OFDM_PHY2MAC_RATE(((ofdm_phy_hdr_t *) plcp)->
- rlpt[0]);
- break;
- case PRXS0_PREN:
- rspec = (plcp[0] & MIMO_PLCP_MCS_MASK) | RSPEC_MIMORATE;
- if (plcp[0] & MIMO_PLCP_40MHZ) {
- /* indicate rspec is for 40 MHz mode */
- rspec &= ~RSPEC_BW_MASK;
- rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
- }
- break;
- case PRXS0_STDN:
- /* fallthru */
- default:
- /* not supported, error condition */
- break;
- }
- if (PLCP3_ISSGI(plcp[3]))
- rspec |= RSPEC_SHORT_GI;
- } else
- if ((phy_type == PHY_TYPE_A) || (rxh->PhyRxStatus_0 & PRXS0_OFDM))
- rspec = OFDM_PHY2MAC_RATE(((ofdm_phy_hdr_t *) plcp)->rlpt[0]);
- else
- rspec = CCK_PHY2MAC_RATE(((cck_phy_hdr_t *) plcp)->signal);
-
- return rspec;
-}
-
-/* copy rateset src to dst as-is (no masking or sorting) */
-void wlc_rateset_copy(const wlc_rateset_t *src, wlc_rateset_t *dst)
-{
- memcpy(dst, src, sizeof(wlc_rateset_t));
-}
-
-/*
- * Copy and selectively filter one rateset to another.
- * 'basic_only' means only copy basic rates.
- * 'rates' indicates cck (11b) and ofdm rates combinations.
- * - 0: cck and ofdm
- * - 1: cck only
- * - 2: ofdm only
- * 'xmask' is the copy mask (typically 0x7f or 0xff).
- */
-void
-wlc_rateset_filter(wlc_rateset_t *src, wlc_rateset_t *dst, bool basic_only,
- u8 rates, uint xmask, bool mcsallow)
-{
- uint i;
- uint r;
- uint count;
-
- count = 0;
- for (i = 0; i < src->count; i++) {
- r = src->rates[i];
- if (basic_only && !(r & WLC_RATE_FLAG))
- continue;
- if ((rates == WLC_RATES_CCK) && IS_OFDM((r & WLC_RATE_MASK)))
- continue;
- if ((rates == WLC_RATES_OFDM) && IS_CCK((r & WLC_RATE_MASK)))
- continue;
- dst->rates[count++] = r & xmask;
- }
- dst->count = count;
- dst->htphy_membership = src->htphy_membership;
-
- if (mcsallow && rates != WLC_RATES_CCK)
- memcpy(&dst->mcs[0], &src->mcs[0], MCSSET_LEN);
- else
- wlc_rateset_mcs_clear(dst);
-}
-
-/* select rateset for a given phy_type and bandtype and filter it, sort it
- * and fill rs_tgt with result
- */
-void
-wlc_rateset_default(wlc_rateset_t *rs_tgt, const wlc_rateset_t *rs_hw,
- uint phy_type, int bandtype, bool cck_only, uint rate_mask,
- bool mcsallow, u8 bw, u8 txstreams)
-{
- const wlc_rateset_t *rs_dflt;
- wlc_rateset_t rs_sel;
- if ((PHYTYPE_IS(phy_type, PHY_TYPE_HT)) ||
- (PHYTYPE_IS(phy_type, PHY_TYPE_N)) ||
- (PHYTYPE_IS(phy_type, PHY_TYPE_LCN)) ||
- (PHYTYPE_IS(phy_type, PHY_TYPE_SSN))) {
- if (BAND_5G(bandtype)) {
- rs_dflt = (bw == WLC_20_MHZ ?
- &ofdm_mimo_rates : &ofdm_40bw_mimo_rates);
- } else {
- rs_dflt = (bw == WLC_20_MHZ ?
- &cck_ofdm_mimo_rates :
- &cck_ofdm_40bw_mimo_rates);
- }
- } else if (PHYTYPE_IS(phy_type, PHY_TYPE_LP)) {
- rs_dflt = (BAND_5G(bandtype)) ? &ofdm_rates : &cck_ofdm_rates;
- } else if (PHYTYPE_IS(phy_type, PHY_TYPE_A)) {
- rs_dflt = &ofdm_rates;
- } else if (PHYTYPE_IS(phy_type, PHY_TYPE_G)) {
- rs_dflt = &cck_ofdm_rates;
- } else {
- /* should not happen, error condition */
- rs_dflt = &cck_rates; /* force cck */
- }
-
- /* if hw rateset is not supplied, assign selected rateset to it */
- if (!rs_hw)
- rs_hw = rs_dflt;
-
- wlc_rateset_copy(rs_dflt, &rs_sel);
- wlc_rateset_mcs_upd(&rs_sel, txstreams);
- wlc_rateset_filter(&rs_sel, rs_tgt, false,
- cck_only ? WLC_RATES_CCK : WLC_RATES_CCK_OFDM,
- rate_mask, mcsallow);
- wlc_rate_hwrs_filter_sort_validate(rs_tgt, rs_hw, false,
- mcsallow ? txstreams : 1);
-}
-
-s16 wlc_rate_legacy_phyctl(uint rate)
-{
- uint i;
- for (i = 0; i < LEGACY_PHYCFG_TABLE_SIZE; i++)
- if (rate == legacy_phycfg_table[i].rate_ofdm)
- return legacy_phycfg_table[i].tx_phy_ctl3;
-
- return -1;
-}
-
-void wlc_rateset_mcs_clear(wlc_rateset_t *rateset)
-{
- uint i;
- for (i = 0; i < MCSSET_LEN; i++)
- rateset->mcs[i] = 0;
-}
-
-void wlc_rateset_mcs_build(wlc_rateset_t *rateset, u8 txstreams)
-{
- memcpy(&rateset->mcs[0], &cck_ofdm_mimo_rates.mcs[0], MCSSET_LEN);
- wlc_rateset_mcs_upd(rateset, txstreams);
-}
-
-/* Based on bandwidth passed, allow/disallow MCS 32 in the rateset */
-void wlc_rateset_bw_mcs_filter(wlc_rateset_t *rateset, u8 bw)
-{
- if (bw == WLC_40_MHZ)
- setbit(rateset->mcs, 32);
- else
- clrbit(rateset->mcs, 32);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _WLC_RATE_H_
-#define _WLC_RATE_H_
-
-extern const u8 rate_info[];
-extern const struct wlc_rateset cck_ofdm_mimo_rates;
-extern const struct wlc_rateset ofdm_mimo_rates;
-extern const struct wlc_rateset cck_ofdm_rates;
-extern const struct wlc_rateset ofdm_rates;
-extern const struct wlc_rateset cck_rates;
-extern const struct wlc_rateset gphy_legacy_rates;
-extern const struct wlc_rateset wlc_lrs_rates;
-extern const struct wlc_rateset rate_limit_1_2;
-
-typedef struct mcs_info {
- u32 phy_rate_20; /* phy rate in kbps [20Mhz] */
- u32 phy_rate_40; /* phy rate in kbps [40Mhz] */
- u32 phy_rate_20_sgi; /* phy rate in kbps [20Mhz] with SGI */
- u32 phy_rate_40_sgi; /* phy rate in kbps [40Mhz] with SGI */
- u8 tx_phy_ctl3; /* phy ctl byte 3, code rate, modulation type, # of streams */
- u8 leg_ofdm; /* matching legacy ofdm rate in 500bkps */
-} mcs_info_t;
-
-#define WLC_MAXMCS 32 /* max valid mcs index */
-#define MCS_TABLE_SIZE 33 /* Number of mcs entries in the table */
-extern const mcs_info_t mcs_table[];
-
-#define MCS_INVALID 0xFF
-#define MCS_CR_MASK 0x07 /* Code Rate bit mask */
-#define MCS_MOD_MASK 0x38 /* Modulation bit shift */
-#define MCS_MOD_SHIFT 3 /* MOdulation bit shift */
-#define MCS_TXS_MASK 0xc0 /* num tx streams - 1 bit mask */
-#define MCS_TXS_SHIFT 6 /* num tx streams - 1 bit shift */
-#define MCS_CR(_mcs) (mcs_table[_mcs].tx_phy_ctl3 & MCS_CR_MASK)
-#define MCS_MOD(_mcs) ((mcs_table[_mcs].tx_phy_ctl3 & MCS_MOD_MASK) >> MCS_MOD_SHIFT)
-#define MCS_TXS(_mcs) ((mcs_table[_mcs].tx_phy_ctl3 & MCS_TXS_MASK) >> MCS_TXS_SHIFT)
-#define MCS_RATE(_mcs, _is40, _sgi) (_sgi ? \
- (_is40 ? mcs_table[_mcs].phy_rate_40_sgi : mcs_table[_mcs].phy_rate_20_sgi) : \
- (_is40 ? mcs_table[_mcs].phy_rate_40 : mcs_table[_mcs].phy_rate_20))
-#define VALID_MCS(_mcs) ((_mcs < MCS_TABLE_SIZE))
-
-/* Macro to use the rate_info table */
-#define WLC_RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */
-
-#define WLC_RATE_500K_TO_BPS(rate) ((rate) * 500000) /* convert 500kbps to bps */
-
-/* rate spec : holds rate and mode specific information required to generate a tx frame. */
-/* Legacy CCK and OFDM information is held in the same manner as was done in the past */
-/* (in the lower byte) the upper 3 bytes primarily hold MIMO specific information */
-typedef u32 ratespec_t;
-
-/* rate spec bit fields */
-#define RSPEC_RATE_MASK 0x0000007F /* Either 500Kbps units or MIMO MCS idx */
-#define RSPEC_MIMORATE 0x08000000 /* mimo MCS is stored in RSPEC_RATE_MASK */
-#define RSPEC_BW_MASK 0x00000700 /* mimo bw mask */
-#define RSPEC_BW_SHIFT 8 /* mimo bw shift */
-#define RSPEC_STF_MASK 0x00003800 /* mimo Space/Time/Frequency mode mask */
-#define RSPEC_STF_SHIFT 11 /* mimo Space/Time/Frequency mode shift */
-#define RSPEC_CT_MASK 0x0000C000 /* mimo coding type mask */
-#define RSPEC_CT_SHIFT 14 /* mimo coding type shift */
-#define RSPEC_STC_MASK 0x00300000 /* mimo num STC streams per PLCP defn. */
-#define RSPEC_STC_SHIFT 20 /* mimo num STC streams per PLCP defn. */
-#define RSPEC_LDPC_CODING 0x00400000 /* mimo bit indicates adv coding in use */
-#define RSPEC_SHORT_GI 0x00800000 /* mimo bit indicates short GI in use */
-#define RSPEC_OVERRIDE 0x80000000 /* bit indicates override both rate & mode */
-#define RSPEC_OVERRIDE_MCS_ONLY 0x40000000 /* bit indicates override rate only */
-
-#define WLC_HTPHY 127 /* HT PHY Membership */
-
-#define RSPEC_ACTIVE(rspec) (rspec & (RSPEC_RATE_MASK | RSPEC_MIMORATE))
-#define RSPEC2RATE(rspec) ((rspec & RSPEC_MIMORATE) ? \
- MCS_RATE((rspec & RSPEC_RATE_MASK), RSPEC_IS40MHZ(rspec), RSPEC_ISSGI(rspec)) : \
- (rspec & RSPEC_RATE_MASK))
-/* return rate in unit of 500Kbps -- for internal use in wlc_rate_sel.c */
-#define RSPEC2RATE500K(rspec) ((rspec & RSPEC_MIMORATE) ? \
- MCS_RATE((rspec & RSPEC_RATE_MASK), state->is40bw, RSPEC_ISSGI(rspec))/500 : \
- (rspec & RSPEC_RATE_MASK))
-#define CRSPEC2RATE500K(rspec) ((rspec & RSPEC_MIMORATE) ? \
- MCS_RATE((rspec & RSPEC_RATE_MASK), RSPEC_IS40MHZ(rspec), RSPEC_ISSGI(rspec))/500 :\
- (rspec & RSPEC_RATE_MASK))
-
-#define RSPEC2KBPS(rspec) (IS_MCS(rspec) ? RSPEC2RATE(rspec) : RSPEC2RATE(rspec)*500)
-#define RSPEC_PHYTXBYTE2(rspec) ((rspec & 0xff00) >> 8)
-#define RSPEC_GET_BW(rspec) ((rspec & RSPEC_BW_MASK) >> RSPEC_BW_SHIFT)
-#define RSPEC_IS40MHZ(rspec) ((((rspec & RSPEC_BW_MASK) >> RSPEC_BW_SHIFT) == \
- PHY_TXC1_BW_40MHZ) || (((rspec & RSPEC_BW_MASK) >> \
- RSPEC_BW_SHIFT) == PHY_TXC1_BW_40MHZ_DUP))
-#define RSPEC_ISSGI(rspec) ((rspec & RSPEC_SHORT_GI) == RSPEC_SHORT_GI)
-#define RSPEC_MIMOPLCP3(rspec) ((rspec & 0xf00000) >> 16)
-#define PLCP3_ISSGI(plcp) (plcp & (RSPEC_SHORT_GI >> 16))
-#define RSPEC_STC(rspec) ((rspec & RSPEC_STC_MASK) >> RSPEC_STC_SHIFT)
-#define RSPEC_STF(rspec) ((rspec & RSPEC_STF_MASK) >> RSPEC_STF_SHIFT)
-#define PLCP3_ISSTBC(plcp) ((plcp & (RSPEC_STC_MASK) >> 16) == 0x10)
-#define PLCP3_STC_MASK 0x30
-#define PLCP3_STC_SHIFT 4
-
-/* Rate info table; takes a legacy rate or ratespec_t */
-#define IS_MCS(r) (r & RSPEC_MIMORATE)
-#define IS_OFDM(r) (!IS_MCS(r) && (rate_info[(r) & RSPEC_RATE_MASK] & WLC_RATE_FLAG))
-#define IS_CCK(r) (!IS_MCS(r) && ( \
- ((r) & WLC_RATE_MASK) == WLC_RATE_1M || \
- ((r) & WLC_RATE_MASK) == WLC_RATE_2M || \
- ((r) & WLC_RATE_MASK) == WLC_RATE_5M5 || \
- ((r) & WLC_RATE_MASK) == WLC_RATE_11M))
-#define IS_SINGLE_STREAM(mcs) (((mcs) <= HIGHEST_SINGLE_STREAM_MCS) || ((mcs) == 32))
-#define CCK_RSPEC(cck) ((cck) & RSPEC_RATE_MASK)
-#define OFDM_RSPEC(ofdm) (((ofdm) & RSPEC_RATE_MASK) |\
- (PHY_TXC1_MODE_CDD << RSPEC_STF_SHIFT))
-#define LEGACY_RSPEC(rate) (IS_CCK(rate) ? CCK_RSPEC(rate) : OFDM_RSPEC(rate))
-
-#define MCS_RSPEC(mcs) (((mcs) & RSPEC_RATE_MASK) | RSPEC_MIMORATE | \
- (IS_SINGLE_STREAM(mcs) ? (PHY_TXC1_MODE_CDD << RSPEC_STF_SHIFT) : \
- (PHY_TXC1_MODE_SDM << RSPEC_STF_SHIFT)))
-
-/* Convert encoded rate value in plcp header to numerical rates in 500 KHz increments */
-extern const u8 ofdm_rate_lookup[];
-#define OFDM_PHY2MAC_RATE(rlpt) (ofdm_rate_lookup[rlpt & 0x7])
-#define CCK_PHY2MAC_RATE(signal) (signal/5)
-
-/* Rates specified in wlc_rateset_filter() */
-#define WLC_RATES_CCK_OFDM 0
-#define WLC_RATES_CCK 1
-#define WLC_RATES_OFDM 2
-
-/* use the stuct form instead of typedef to fix dependency problems */
-struct wlc_rateset;
-
-/* sanitize, and sort a rateset with the basic bit(s) preserved, validate rateset */
-extern bool wlc_rate_hwrs_filter_sort_validate(struct wlc_rateset *rs,
- const struct wlc_rateset *hw_rs,
- bool check_brate,
- u8 txstreams);
-/* copy rateset src to dst as-is (no masking or sorting) */
-extern void wlc_rateset_copy(const struct wlc_rateset *src,
- struct wlc_rateset *dst);
-
-/* would be nice to have these documented ... */
-extern ratespec_t wlc_compute_rspec(d11rxhdr_t *rxh, u8 *plcp);
-
-extern void wlc_rateset_filter(struct wlc_rateset *src, struct wlc_rateset *dst,
- bool basic_only, u8 rates, uint xmask,
- bool mcsallow);
-extern void wlc_rateset_default(struct wlc_rateset *rs_tgt,
- const struct wlc_rateset *rs_hw, uint phy_type,
- int bandtype, bool cck_only, uint rate_mask,
- bool mcsallow, u8 bw, u8 txstreams);
-extern s16 wlc_rate_legacy_phyctl(uint rate);
-
-extern void wlc_rateset_mcs_upd(struct wlc_rateset *rs, u8 txstreams);
-extern void wlc_rateset_mcs_clear(struct wlc_rateset *rateset);
-extern void wlc_rateset_mcs_build(struct wlc_rateset *rateset, u8 txstreams);
-extern void wlc_rateset_bw_mcs_filter(struct wlc_rateset *rateset, u8 bw);
-
-#endif /* _WLC_RATE_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_SCB_H_
-#define _BRCM_SCB_H_
-
-#include <linux/if_ether.h> /* for ETH_ALEN */
-
-#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
-/* structure to store per-tid state for the ampdu initiator */
-typedef struct scb_ampdu_tid_ini {
- u32 magic;
- u8 tx_in_transit; /* number of pending mpdus in transit in driver */
- u8 tid; /* initiator tid for easy lookup */
- u8 txretry[AMPDU_TX_BA_MAX_WSIZE]; /* tx retry count; indexed by seq modulo */
- struct scb *scb; /* backptr for easy lookup */
-} scb_ampdu_tid_ini_t;
-
-#define AMPDU_MAX_SCB_TID NUMPRIO
-
-typedef struct scb_ampdu {
- struct scb *scb; /* back pointer for easy reference */
- u8 mpdu_density; /* mpdu density */
- u8 max_pdu; /* max pdus allowed in ampdu */
- u8 release; /* # of mpdus released at a time */
- u16 min_len; /* min mpdu len to support the density */
- u32 max_rxlen; /* max ampdu rcv length; 8k, 16k, 32k, 64k */
- struct pktq txq; /* sdu transmit queue pending aggregation */
-
- /* This could easily be a ini[] pointer and we keep this info in wl itself instead
- * of having mac80211 hold it for us. Also could be made dynamic per tid instead of
- * static.
- */
- scb_ampdu_tid_ini_t ini[AMPDU_MAX_SCB_TID]; /* initiator info - per tid (NUMPRIO) */
-} scb_ampdu_t;
-
-#define SCB_MAGIC 0xbeefcafe
-#define INI_MAGIC 0xabcd1234
-
-/* station control block - one per remote MAC address */
-struct scb {
- u32 magic;
- u32 flags; /* various bit flags as defined below */
- u32 flags2; /* various bit flags2 as defined below */
- u8 state; /* current state bitfield of auth/assoc process */
- u8 ea[ETH_ALEN]; /* station address */
- void *fragbuf[NUMPRIO]; /* defragmentation buffer per prio */
- uint fragresid[NUMPRIO]; /* #bytes unused in frag buffer per prio */
-
- u16 seqctl[NUMPRIO]; /* seqctl of last received frame (for dups) */
- u16 seqctl_nonqos; /* seqctl of last received frame (for dups) for
- * non-QoS data and management
- */
- u16 seqnum[NUMPRIO]; /* WME: driver maintained sw seqnum per priority */
-
- scb_ampdu_t scb_ampdu; /* AMPDU state including per tid info */
-};
-
-/* scb flags */
-#define SCB_WMECAP 0x0040 /* may ONLY be set if WME_ENAB(wlc) */
-#define SCB_HTCAP 0x10000 /* HT (MIMO) capable device */
-#define SCB_IS40 0x80000 /* 40MHz capable */
-#define SCB_STBCCAP 0x40000000 /* STBC Capable */
-#define SCB_WME(a) ((a)->flags & SCB_WMECAP)/* implies WME_ENAB */
-#define SCB_SEQNUM(scb, prio) ((scb)->seqnum[(prio)])
-#define SCB_PS(a) NULL
-#define SCB_STBC_CAP(a) ((a)->flags & SCB_STBCCAP)
-#define SCB_AMPDU(a) true
-#endif /* _BRCM_SCB_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <bcmdefs.h>
-#include <brcmu_utils.h>
-#include <aiutils.h>
-#include <brcmu_wifi.h>
-#include "bcmdma.h"
-
-#include "wlc_types.h"
-#include "d11.h"
-#include "wlc_cfg.h"
-#include "wlc_rate.h"
-#include "wlc_scb.h"
-#include "wlc_pub.h"
-#include "wlc_key.h"
-#include "phy/wlc_phy_hal.h"
-#include "wlc_channel.h"
-#include "wlc_main.h"
-#include "wlc_bmac.h"
-#include "wlc_stf.h"
-
-#define MIN_SPATIAL_EXPANSION 0
-#define MAX_SPATIAL_EXPANSION 1
-
-#define WLC_STF_SS_STBC_RX(wlc) (WLCISNPHY(wlc->band) && \
- NREV_GT(wlc->band->phyrev, 3) && NREV_LE(wlc->band->phyrev, 6))
-
-static bool wlc_stf_stbc_tx_set(struct wlc_info *wlc, s32 int_val);
-static int wlc_stf_txcore_set(struct wlc_info *wlc, u8 Nsts, u8 val);
-static int wlc_stf_spatial_policy_set(struct wlc_info *wlc, int val);
-static void wlc_stf_stbc_rx_ht_update(struct wlc_info *wlc, int val);
-
-static void _wlc_stf_phy_txant_upd(struct wlc_info *wlc);
-static u16 _wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec);
-
-#define NSTS_1 1
-#define NSTS_2 2
-#define NSTS_3 3
-#define NSTS_4 4
-const u8 txcore_default[5] = {
- (0), /* bitmap of the core enabled */
- (0x01), /* For Nsts = 1, enable core 1 */
- (0x03), /* For Nsts = 2, enable core 1 & 2 */
- (0x07), /* For Nsts = 3, enable core 1, 2 & 3 */
- (0x0f) /* For Nsts = 4, enable all cores */
-};
-
-static void wlc_stf_stbc_rx_ht_update(struct wlc_info *wlc, int val)
-{
- /* MIMOPHYs rev3-6 cannot receive STBC with only one rx core active */
- if (WLC_STF_SS_STBC_RX(wlc)) {
- if ((wlc->stf->rxstreams == 1) && (val != HT_CAP_RX_STBC_NO))
- return;
- }
-
- wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_RX_STBC;
- wlc->ht_cap.cap_info |= (val << IEEE80211_HT_CAP_RX_STBC_SHIFT);
-
- if (wlc->pub->up) {
- wlc_update_beacon(wlc);
- wlc_update_probe_resp(wlc, true);
- }
-}
-
-/* every WLC_TEMPSENSE_PERIOD seconds temperature check to decide whether to turn on/off txchain */
-void wlc_tempsense_upd(struct wlc_info *wlc)
-{
- wlc_phy_t *pi = wlc->band->pi;
- uint active_chains, txchain;
-
- /* Check if the chip is too hot. Disable one Tx chain, if it is */
- /* high 4 bits are for Rx chain, low 4 bits are for Tx chain */
- active_chains = wlc_phy_stf_chain_active_get(pi);
- txchain = active_chains & 0xf;
-
- if (wlc->stf->txchain == wlc->stf->hw_txchain) {
- if (txchain && (txchain < wlc->stf->hw_txchain)) {
- /* turn off 1 tx chain */
- wlc_stf_txchain_set(wlc, txchain, true);
- }
- } else if (wlc->stf->txchain < wlc->stf->hw_txchain) {
- if (txchain == wlc->stf->hw_txchain) {
- /* turn back on txchain */
- wlc_stf_txchain_set(wlc, txchain, true);
- }
- }
-}
-
-void
-wlc_stf_ss_algo_channel_get(struct wlc_info *wlc, u16 *ss_algo_channel,
- chanspec_t chanspec)
-{
- tx_power_t power;
- u8 siso_mcs_id, cdd_mcs_id, stbc_mcs_id;
-
- /* Clear previous settings */
- *ss_algo_channel = 0;
-
- if (!wlc->pub->up) {
- *ss_algo_channel = (u16) -1;
- return;
- }
-
- wlc_phy_txpower_get_current(wlc->band->pi, &power,
- CHSPEC_CHANNEL(chanspec));
-
- siso_mcs_id = (CHSPEC_IS40(chanspec)) ?
- WL_TX_POWER_MCS40_SISO_FIRST : WL_TX_POWER_MCS20_SISO_FIRST;
- cdd_mcs_id = (CHSPEC_IS40(chanspec)) ?
- WL_TX_POWER_MCS40_CDD_FIRST : WL_TX_POWER_MCS20_CDD_FIRST;
- stbc_mcs_id = (CHSPEC_IS40(chanspec)) ?
- WL_TX_POWER_MCS40_STBC_FIRST : WL_TX_POWER_MCS20_STBC_FIRST;
-
- /* criteria to choose stf mode */
-
- /* the "+3dbm (12 0.25db units)" is to account for the fact that with CDD, tx occurs
- * on both chains
- */
- if (power.target[siso_mcs_id] > (power.target[cdd_mcs_id] + 12))
- setbit(ss_algo_channel, PHY_TXC1_MODE_SISO);
- else
- setbit(ss_algo_channel, PHY_TXC1_MODE_CDD);
-
- /* STBC is ORed into to algo channel as STBC requires per-packet SCB capability check
- * so cannot be default mode of operation. One of SISO, CDD have to be set
- */
- if (power.target[siso_mcs_id] <= (power.target[stbc_mcs_id] + 12))
- setbit(ss_algo_channel, PHY_TXC1_MODE_STBC);
-}
-
-static bool wlc_stf_stbc_tx_set(struct wlc_info *wlc, s32 int_val)
-{
- if ((int_val != AUTO) && (int_val != OFF) && (int_val != ON)) {
- return false;
- }
-
- if ((int_val == ON) && (wlc->stf->txstreams == 1))
- return false;
-
- if ((int_val == OFF) || (wlc->stf->txstreams == 1)
- || !WLC_STBC_CAP_PHY(wlc))
- wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_TX_STBC;
- else
- wlc->ht_cap.cap_info |= IEEE80211_HT_CAP_TX_STBC;
-
- wlc->bandstate[BAND_2G_INDEX]->band_stf_stbc_tx = (s8) int_val;
- wlc->bandstate[BAND_5G_INDEX]->band_stf_stbc_tx = (s8) int_val;
-
- return true;
-}
-
-bool wlc_stf_stbc_rx_set(struct wlc_info *wlc, s32 int_val)
-{
- if ((int_val != HT_CAP_RX_STBC_NO)
- && (int_val != HT_CAP_RX_STBC_ONE_STREAM)) {
- return false;
- }
-
- if (WLC_STF_SS_STBC_RX(wlc)) {
- if ((int_val != HT_CAP_RX_STBC_NO)
- && (wlc->stf->rxstreams == 1))
- return false;
- }
-
- wlc_stf_stbc_rx_ht_update(wlc, int_val);
- return true;
-}
-
-static int wlc_stf_txcore_set(struct wlc_info *wlc, u8 Nsts, u8 core_mask)
-{
- BCMMSG(wlc->wiphy, "wl%d: Nsts %d core_mask %x\n",
- wlc->pub->unit, Nsts, core_mask);
-
- if (WLC_BITSCNT(core_mask) > wlc->stf->txstreams) {
- core_mask = 0;
- }
-
- if ((WLC_BITSCNT(core_mask) == wlc->stf->txstreams) &&
- ((core_mask & ~wlc->stf->txchain)
- || !(core_mask & wlc->stf->txchain))) {
- core_mask = wlc->stf->txchain;
- }
-
- wlc->stf->txcore[Nsts] = core_mask;
- /* Nsts = 1..4, txcore index = 1..4 */
- if (Nsts == 1) {
- /* Needs to update beacon and ucode generated response
- * frames when 1 stream core map changed
- */
- wlc->stf->phytxant = core_mask << PHY_TXC_ANT_SHIFT;
- wlc_bmac_txant_set(wlc->hw, wlc->stf->phytxant);
- if (wlc->clk) {
- wlc_suspend_mac_and_wait(wlc);
- wlc_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec);
- wlc_enable_mac(wlc);
- }
- }
-
- return 0;
-}
-
-static int wlc_stf_spatial_policy_set(struct wlc_info *wlc, int val)
-{
- int i;
- u8 core_mask = 0;
-
- BCMMSG(wlc->wiphy, "wl%d: val %x\n", wlc->pub->unit, val);
-
- wlc->stf->spatial_policy = (s8) val;
- for (i = 1; i <= MAX_STREAMS_SUPPORTED; i++) {
- core_mask = (val == MAX_SPATIAL_EXPANSION) ?
- wlc->stf->txchain : txcore_default[i];
- wlc_stf_txcore_set(wlc, (u8) i, core_mask);
- }
- return 0;
-}
-
-int wlc_stf_txchain_set(struct wlc_info *wlc, s32 int_val, bool force)
-{
- u8 txchain = (u8) int_val;
- u8 txstreams;
- uint i;
-
- if (wlc->stf->txchain == txchain)
- return 0;
-
- if ((txchain & ~wlc->stf->hw_txchain)
- || !(txchain & wlc->stf->hw_txchain))
- return -EINVAL;
-
- /* if nrate override is configured to be non-SISO STF mode, reject reducing txchain to 1 */
- txstreams = (u8) WLC_BITSCNT(txchain);
- if (txstreams > MAX_STREAMS_SUPPORTED)
- return -EINVAL;
-
- if (txstreams == 1) {
- for (i = 0; i < NBANDS(wlc); i++)
- if ((RSPEC_STF(wlc->bandstate[i]->rspec_override) !=
- PHY_TXC1_MODE_SISO)
- || (RSPEC_STF(wlc->bandstate[i]->mrspec_override) !=
- PHY_TXC1_MODE_SISO)) {
- if (!force)
- return -EBADE;
-
- /* over-write the override rspec */
- if (RSPEC_STF(wlc->bandstate[i]->rspec_override)
- != PHY_TXC1_MODE_SISO) {
- wlc->bandstate[i]->rspec_override = 0;
- wiphy_err(wlc->wiphy, "%s(): temp "
- "sense override non-SISO "
- "rspec_override\n",
- __func__);
- }
- if (RSPEC_STF
- (wlc->bandstate[i]->mrspec_override) !=
- PHY_TXC1_MODE_SISO) {
- wlc->bandstate[i]->mrspec_override = 0;
- wiphy_err(wlc->wiphy, "%s(): temp "
- "sense override non-SISO "
- "mrspec_override\n",
- __func__);
- }
- }
- }
-
- wlc->stf->txchain = txchain;
- wlc->stf->txstreams = txstreams;
- wlc_stf_stbc_tx_set(wlc, wlc->band->band_stf_stbc_tx);
- wlc_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
- wlc_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
- wlc->stf->txant =
- (wlc->stf->txstreams == 1) ? ANT_TX_FORCE_0 : ANT_TX_DEF;
- _wlc_stf_phy_txant_upd(wlc);
-
- wlc_phy_stf_chain_set(wlc->band->pi, wlc->stf->txchain,
- wlc->stf->rxchain);
-
- for (i = 1; i <= MAX_STREAMS_SUPPORTED; i++)
- wlc_stf_txcore_set(wlc, (u8) i, txcore_default[i]);
-
- return 0;
-}
-
-/* update wlc->stf->ss_opmode which represents the operational stf_ss mode we're using */
-int wlc_stf_ss_update(struct wlc_info *wlc, struct wlcband *band)
-{
- int ret_code = 0;
- u8 prev_stf_ss;
- u8 upd_stf_ss;
-
- prev_stf_ss = wlc->stf->ss_opmode;
-
- /* NOTE: opmode can only be SISO or CDD as STBC is decided on a per-packet basis */
- if (WLC_STBC_CAP_PHY(wlc) &&
- wlc->stf->ss_algosel_auto
- && (wlc->stf->ss_algo_channel != (u16) -1)) {
- upd_stf_ss = (wlc->stf->no_cddstbc || (wlc->stf->txstreams == 1)
- || isset(&wlc->stf->ss_algo_channel,
- PHY_TXC1_MODE_SISO)) ? PHY_TXC1_MODE_SISO
- : PHY_TXC1_MODE_CDD;
- } else {
- if (wlc->band != band)
- return ret_code;
- upd_stf_ss = (wlc->stf->no_cddstbc
- || (wlc->stf->txstreams ==
- 1)) ? PHY_TXC1_MODE_SISO : band->
- band_stf_ss_mode;
- }
- if (prev_stf_ss != upd_stf_ss) {
- wlc->stf->ss_opmode = upd_stf_ss;
- wlc_bmac_band_stf_ss_set(wlc->hw, upd_stf_ss);
- }
-
- return ret_code;
-}
-
-int wlc_stf_attach(struct wlc_info *wlc)
-{
- wlc->bandstate[BAND_2G_INDEX]->band_stf_ss_mode = PHY_TXC1_MODE_SISO;
- wlc->bandstate[BAND_5G_INDEX]->band_stf_ss_mode = PHY_TXC1_MODE_CDD;
-
- if (WLCISNPHY(wlc->band) &&
- (wlc_phy_txpower_hw_ctrl_get(wlc->band->pi) != PHY_TPC_HW_ON))
- wlc->bandstate[BAND_2G_INDEX]->band_stf_ss_mode =
- PHY_TXC1_MODE_CDD;
- wlc_stf_ss_update(wlc, wlc->bandstate[BAND_2G_INDEX]);
- wlc_stf_ss_update(wlc, wlc->bandstate[BAND_5G_INDEX]);
-
- wlc_stf_stbc_rx_ht_update(wlc, HT_CAP_RX_STBC_NO);
- wlc->bandstate[BAND_2G_INDEX]->band_stf_stbc_tx = OFF;
- wlc->bandstate[BAND_5G_INDEX]->band_stf_stbc_tx = OFF;
-
- if (WLC_STBC_CAP_PHY(wlc)) {
- wlc->stf->ss_algosel_auto = true;
- wlc->stf->ss_algo_channel = (u16) -1; /* Init the default value */
- }
- return 0;
-}
-
-void wlc_stf_detach(struct wlc_info *wlc)
-{
-}
-
-/*
- * Centralized txant update function. call it whenever wlc->stf->txant and/or wlc->stf->txchain
- * change
- *
- * Antennas are controlled by ucode indirectly, which drives PHY or GPIO to
- * achieve various tx/rx antenna selection schemes
- *
- * legacy phy, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7 means auto(last rx)
- * for NREV<3, bit 6 and bit 7 means antenna 0 and 1 respectively, bit6+bit7 means last rx and
- * do tx-antenna selection for SISO transmissions
- * for NREV=3, bit 6 and bit _8_ means antenna 0 and 1 respectively, bit6+bit7 means last rx and
- * do tx-antenna selection for SISO transmissions
- * for NREV>=7, bit 6 and bit 7 mean antenna 0 and 1 respectively, nit6+bit7 means both cores active
-*/
-static void _wlc_stf_phy_txant_upd(struct wlc_info *wlc)
-{
- s8 txant;
-
- txant = (s8) wlc->stf->txant;
- if (WLC_PHY_11N_CAP(wlc->band)) {
- if (txant == ANT_TX_FORCE_0) {
- wlc->stf->phytxant = PHY_TXC_ANT_0;
- } else if (txant == ANT_TX_FORCE_1) {
- wlc->stf->phytxant = PHY_TXC_ANT_1;
-
- if (WLCISNPHY(wlc->band) &&
- NREV_GE(wlc->band->phyrev, 3)
- && NREV_LT(wlc->band->phyrev, 7)) {
- wlc->stf->phytxant = PHY_TXC_ANT_2;
- }
- } else {
- if (WLCISLCNPHY(wlc->band) || WLCISSSLPNPHY(wlc->band))
- wlc->stf->phytxant = PHY_TXC_LCNPHY_ANT_LAST;
- else {
- /* catch out of sync wlc->stf->txcore */
- WARN_ON(wlc->stf->txchain <= 0);
- wlc->stf->phytxant =
- wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
- }
- }
- } else {
- if (txant == ANT_TX_FORCE_0)
- wlc->stf->phytxant = PHY_TXC_OLD_ANT_0;
- else if (txant == ANT_TX_FORCE_1)
- wlc->stf->phytxant = PHY_TXC_OLD_ANT_1;
- else
- wlc->stf->phytxant = PHY_TXC_OLD_ANT_LAST;
- }
-
- wlc_bmac_txant_set(wlc->hw, wlc->stf->phytxant);
-}
-
-void wlc_stf_phy_txant_upd(struct wlc_info *wlc)
-{
- _wlc_stf_phy_txant_upd(wlc);
-}
-
-void wlc_stf_phy_chain_calc(struct wlc_info *wlc)
-{
- /* get available rx/tx chains */
- wlc->stf->hw_txchain = (u8) getintvar(wlc->pub->vars, "txchain");
- wlc->stf->hw_rxchain = (u8) getintvar(wlc->pub->vars, "rxchain");
-
- /* these parameter are intended to be used for all PHY types */
- if (wlc->stf->hw_txchain == 0 || wlc->stf->hw_txchain == 0xf) {
- if (WLCISNPHY(wlc->band)) {
- wlc->stf->hw_txchain = TXCHAIN_DEF_NPHY;
- } else {
- wlc->stf->hw_txchain = TXCHAIN_DEF;
- }
- }
-
- wlc->stf->txchain = wlc->stf->hw_txchain;
- wlc->stf->txstreams = (u8) WLC_BITSCNT(wlc->stf->hw_txchain);
-
- if (wlc->stf->hw_rxchain == 0 || wlc->stf->hw_rxchain == 0xf) {
- if (WLCISNPHY(wlc->band)) {
- wlc->stf->hw_rxchain = RXCHAIN_DEF_NPHY;
- } else {
- wlc->stf->hw_rxchain = RXCHAIN_DEF;
- }
- }
-
- wlc->stf->rxchain = wlc->stf->hw_rxchain;
- wlc->stf->rxstreams = (u8) WLC_BITSCNT(wlc->stf->hw_rxchain);
-
- /* initialize the txcore table */
- memcpy(wlc->stf->txcore, txcore_default, sizeof(wlc->stf->txcore));
-
- /* default spatial_policy */
- wlc->stf->spatial_policy = MIN_SPATIAL_EXPANSION;
- wlc_stf_spatial_policy_set(wlc, MIN_SPATIAL_EXPANSION);
-}
-
-static u16 _wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec)
-{
- u16 phytxant = wlc->stf->phytxant;
-
- if (RSPEC_STF(rspec) != PHY_TXC1_MODE_SISO) {
- phytxant = wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
- } else if (wlc->stf->txant == ANT_TX_DEF)
- phytxant = wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
- phytxant &= PHY_TXC_ANT_MASK;
- return phytxant;
-}
-
-u16 wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec)
-{
- return _wlc_stf_phytxchain_sel(wlc, rspec);
-}
-
-u16 wlc_stf_d11hdrs_phyctl_txant(struct wlc_info *wlc, ratespec_t rspec)
-{
- u16 phytxant = wlc->stf->phytxant;
- u16 mask = PHY_TXC_ANT_MASK;
-
- /* for non-siso rates or default setting, use the available chains */
- if (WLCISNPHY(wlc->band)) {
- phytxant = _wlc_stf_phytxchain_sel(wlc, rspec);
- mask = PHY_TXC_HTANT_MASK;
- }
- phytxant |= phytxant & mask;
- return phytxant;
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_STF_H_
-#define _BRCM_STF_H_
-
-extern int wlc_stf_attach(struct wlc_info *wlc);
-extern void wlc_stf_detach(struct wlc_info *wlc);
-
-extern void wlc_tempsense_upd(struct wlc_info *wlc);
-extern void wlc_stf_ss_algo_channel_get(struct wlc_info *wlc,
- u16 *ss_algo_channel,
- chanspec_t chanspec);
-extern int wlc_stf_ss_update(struct wlc_info *wlc, struct wlcband *band);
-extern void wlc_stf_phy_txant_upd(struct wlc_info *wlc);
-extern int wlc_stf_txchain_set(struct wlc_info *wlc, s32 int_val, bool force);
-extern bool wlc_stf_stbc_rx_set(struct wlc_info *wlc, s32 int_val);
-extern void wlc_stf_phy_txant_upd(struct wlc_info *wlc);
-extern void wlc_stf_phy_chain_calc(struct wlc_info *wlc);
-extern u16 wlc_stf_phytxchain_sel(struct wlc_info *wlc, ratespec_t rspec);
-extern u16 wlc_stf_d11hdrs_phyctl_txant(struct wlc_info *wlc, ratespec_t rspec);
-
-#endif /* _BRCM_STF_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_TYPES_H_
-#define _BRCM_TYPES_H_
-
-/* Bus types */
-#define SI_BUS 0 /* SOC Interconnect */
-#define PCI_BUS 1 /* PCI target */
-#define SDIO_BUS 3 /* SDIO target */
-#define JTAG_BUS 4 /* JTAG */
-#define USB_BUS 5 /* USB (does not support R/W REG) */
-#define SPI_BUS 6 /* gSPI target */
-#define RPC_BUS 7 /* RPC target */
-
-#define WL_CHAN_FREQ_RANGE_2G 0
-#define WL_CHAN_FREQ_RANGE_5GL 1
-#define WL_CHAN_FREQ_RANGE_5GM 2
-#define WL_CHAN_FREQ_RANGE_5GH 3
-
-#define MAX_DMA_SEGS 4
-
-#define BCMMSG(dev, fmt, args...) \
-do { \
- if (brcm_msg_level & LOG_TRACE_VAL) \
- wiphy_err(dev, "%s: " fmt, __func__, ##args); \
-} while (0)
-
-#define WL_ERROR_ON() (brcm_msg_level & LOG_ERROR_VAL)
-
-/* register access macros */
-#ifndef __BIG_ENDIAN
-#ifndef __mips__
-#define R_REG(r) \
- ({\
- sizeof(*(r)) == sizeof(u8) ? \
- readb((volatile u8*)(r)) : \
- sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
- readl((volatile u32*)(r)); \
- })
-#else /* __mips__ */
-#define R_REG(r) \
- ({ \
- __typeof(*(r)) __osl_v; \
- __asm__ __volatile__("sync"); \
- switch (sizeof(*(r))) { \
- case sizeof(u8): \
- __osl_v = readb((volatile u8*)(r)); \
- break; \
- case sizeof(u16): \
- __osl_v = readw((volatile u16*)(r)); \
- break; \
- case sizeof(u32): \
- __osl_v = \
- readl((volatile u32*)(r)); \
- break; \
- } \
- __asm__ __volatile__("sync"); \
- __osl_v; \
- })
-#endif /* __mips__ */
-
-#define W_REG(r, v) do { \
- switch (sizeof(*(r))) { \
- case sizeof(u8): \
- writeb((u8)(v), (volatile u8*)(r)); break; \
- case sizeof(u16): \
- writew((u16)(v), (volatile u16*)(r)); break; \
- case sizeof(u32): \
- writel((u32)(v), (volatile u32*)(r)); break; \
- }; \
- } while (0)
-#else /* __BIG_ENDIAN */
-#define R_REG(r) \
- ({ \
- __typeof(*(r)) __osl_v; \
- switch (sizeof(*(r))) { \
- case sizeof(u8): \
- __osl_v = \
- readb((volatile u8*)((r)^3)); \
- break; \
- case sizeof(u16): \
- __osl_v = \
- readw((volatile u16*)((r)^2)); \
- break; \
- case sizeof(u32): \
- __osl_v = readl((volatile u32*)(r)); \
- break; \
- } \
- __osl_v; \
- })
-
-#define W_REG(r, v) do { \
- switch (sizeof(*(r))) { \
- case sizeof(u8): \
- writeb((u8)(v), \
- (volatile u8*)((r)^3)); break; \
- case sizeof(u16): \
- writew((u16)(v), \
- (volatile u16*)((r)^2)); break; \
- case sizeof(u32): \
- writel((u32)(v), \
- (volatile u32*)(r)); break; \
- } \
- } while (0)
-#endif /* __BIG_ENDIAN */
-
-#ifdef __mips__
-/*
- * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
- * transactions. As a fix, a read after write is performed on certain places
- * in the code. Older chips and the newer 5357 family don't require this fix.
- */
-#define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
-#else
-#define W_REG_FLUSH(r, v) W_REG((r), (v))
-#endif /* __mips__ */
-
-#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
-#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
-
-#define SET_REG(r, mask, val) \
- W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
-
-/* forward declarations */
-struct sk_buff;
-struct brcms_info;
-struct wlc_info;
-struct wlc_hw_info;
-struct wlc_if;
-struct brcms_if;
-struct ampdu_info;
-struct antsel_info;
-struct bmac_pmq;
-struct d11init;
-struct dma_pub;
-struct wlc_bsscfg;
-struct brcmu_strbuf;
-struct si_pub;
-
-/* brcm_msg_level is a bit vector with defs in bcmdefs.h */
-extern u32 brcm_msg_level;
-
-#endif /* _BRCM_TYPES_H_ */
#include <linux/netdevice.h>
#include <linux/sched.h>
#include <linux/printk.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <stdarg.h>
#include <brcmu_utils.h>
-#include <bcmdevs.h>
+#include <brcm_hw_ids.h>
MODULE_AUTHOR("Broadcom Corporation");
MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver utilities.");
#include <linux/ctype.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <bcmdefs.h>
+#include <defs.h>
#include <brcmu_utils.h>
#include <brcmu_wifi.h>
#ifndef _AIDMP_H
#define _AIDMP_H
-#include "bcmdefs.h" /* for PAD macro */
+#include "defs.h" /* for PAD macro */
/* Manufacturer Ids */
#define MFGID_ARM 0x43b
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_DEFS_H_
-#define _BRCM_DEFS_H_
-
-#define SI_BUS 0
-#define PCI_BUS 1
-#define PCMCIA_BUS 2
-#define SDIO_BUS 3
-#define JTAG_BUS 4
-#define USB_BUS 5
-#define SPI_BUS 6
-
-#ifndef OFF
-#define OFF 0
-#endif
-
-#ifndef ON
-#define ON 1 /* ON = 1 */
-#endif
-
-#define AUTO (-1) /* Auto = -1 */
-
-/*
- * Priority definitions according 802.1D
- */
-#define PRIO_8021D_NONE 2
-#define PRIO_8021D_BK 1
-#define PRIO_8021D_BE 0
-#define PRIO_8021D_EE 3
-#define PRIO_8021D_CL 4
-#define PRIO_8021D_VI 5
-#define PRIO_8021D_VO 6
-#define PRIO_8021D_NC 7
-
-#define MAXPRIO 7
-#define NUMPRIO (MAXPRIO + 1)
-
-#define WL_NUMRATES 16 /* max # of rates in a rateset */
-
-typedef struct wl_rateset {
- u32 count; /* # rates in this set */
- u8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
-} wl_rateset_t;
-
-#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NUL */
-
-#define WLC_SET_CHANNEL 30
-#define WLC_SET_SRL 32
-#define WLC_SET_LRL 34
-
-#define WLC_SET_RATESET 72
-#define WLC_SET_BCNPRD 76
-#define WLC_GET_CURR_RATESET 114 /* current rateset */
-#define WLC_GET_PHYLIST 180
-
-/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
-#define WL_RADIO_SW_DISABLE (1<<0)
-#define WL_RADIO_HW_DISABLE (1<<1)
-#define WL_RADIO_MPC_DISABLE (1<<2)
-#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any channel */
-
-/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
-#define WL_TXPWR_OVERRIDE (1U<<31)
-
-/* band types */
-#define WLC_BAND_AUTO 0 /* auto-select */
-#define WLC_BAND_5G 1 /* 5 Ghz */
-#define WLC_BAND_2G 2 /* 2.4 Ghz */
-#define WLC_BAND_ALL 3 /* all bands */
-
-/* Values for PM */
-#define PM_OFF 0
-#define PM_MAX 1
-
-/* Message levels */
-#define LOG_ERROR_VAL 0x00000001
-#define LOG_TRACE_VAL 0x00000002
-
-#define PM_OFF 0
-#define PM_MAX 1
-#define PM_FAST 2
-
-/*
- * Sonics Configuration Space Registers.
- */
-#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
-
-/* cpp contortions to concatenate w/arg prescan */
-#ifndef PAD
-#define _PADLINE(line) pad ## line
-#define _XSTR(line) _PADLINE(line)
-#define PAD _XSTR(__LINE__)
-#endif
-
-#endif /* _BRCM_DEFS_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_HW_IDS_H_
-#define _BRCM_HW_IDS_H_
-
-#define BCM4325_D11DUAL_ID 0x431b
-#define BCM4325_D11G_ID 0x431c
-#define BCM4325_D11A_ID 0x431d
-
-#define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
-#define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
-#define BCM4329_D11NDUAL_ID 0x432e
-
-#define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
-#define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
-#define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
-
-#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
-#define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db */
-
-#define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
-
-#define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
-#define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
-
-#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
-
-/* Chip IDs */
-#define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
-#define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
-
-#define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
-#define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
-#define BCM43421_CHIP_ID 43421 /* 43421 chipcommon chipid */
-#define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
-#define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
-#define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
-#define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
-#define BCM4325_CHIP_ID 0x4325 /* 4325 chipcommon chipid */
-#define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
-#define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
-#define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
-#define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
-
-/* these are router chips */
-#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
-#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
-#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
-#define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
-#define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
-
-/* Package IDs */
-#define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
-#define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
-#define BCM4717_PKG_ID 9 /* 4717 package id */
-#define BCM4718_PKG_ID 10 /* 4718 package id */
-#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
-#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
-#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
-
-/* boardflags */
-#define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
-#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
-#define BFL_FEM 0x00000800 /* Board supports the Front End Module */
-#define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
-#define BFL_NOPA 0x00010000 /* Board has no PA */
-#define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
-#define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
-#define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
-#define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
-#define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
-
-/* boardflags2 */
-#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
-#define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
-#define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
-#define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
-#define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
-#define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
-#define BFL2_LEGACY 0x00000080
-#define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
-#define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
-#define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
-#define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
-#define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
-#define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
-#define BFL2_IPALVLSHIFT_3P3 0x00020000
-#define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
-#define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio "ON"
- * Most drivers will turn it off without this flag
- * to save power.
- */
-
-/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
-#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
-#define BOARD_GPIO_12 0x1000 /* gpio 12 */
-#define BOARD_GPIO_13 0x2000 /* gpio 13 */
-
-#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
-#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
-#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
-
-/* power control defines */
-#define PLL_DELAY 150 /* us pll on delay */
-#define FREF_DELAY 200 /* us fref change delay */
-#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
-
-/* Reference board types */
-#define SPI_BOARD 0x0402
-
-#endif /* _BRCM_HW_IDS_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_SDH_H_
-#define _BRCM_SDH_H_
-
-#include <linux/skbuff.h>
-#define BCMSDH_ERROR_VAL 0x0001 /* Error */
-#define BCMSDH_INFO_VAL 0x0002 /* Info */
-extern const uint bcmsdh_msglevel;
-
-#ifdef BCMDBG
-#define BCMSDH_ERROR(x) \
- do { \
- if ((bcmsdh_msglevel & BCMSDH_ERROR_VAL) && net_ratelimit()) \
- printk x; \
- } while (0)
-#define BCMSDH_INFO(x) \
- do { \
- if ((bcmsdh_msglevel & BCMSDH_INFO_VAL) && net_ratelimit()) \
- printk x; \
- } while (0)
-#else /* BCMDBG */
-#define BCMSDH_ERROR(x)
-#define BCMSDH_INFO(x)
-#endif /* BCMDBG */
-
-#define SDIO_FUNC_0 0
-#define SDIO_FUNC_1 1
-#define SDIO_FUNC_2 2
-
-#define SDIOD_FBR_SIZE 0x100
-
-/* io_en */
-#define SDIO_FUNC_ENABLE_1 0x02
-#define SDIO_FUNC_ENABLE_2 0x04
-
-/* io_rdys */
-#define SDIO_FUNC_READY_1 0x02
-#define SDIO_FUNC_READY_2 0x04
-
-/* intr_status */
-#define INTR_STATUS_FUNC1 0x2
-#define INTR_STATUS_FUNC2 0x4
-
-/* Maximum number of I/O funcs */
-#define SDIOD_MAX_IOFUNCS 7
-
-/* forward declarations */
-typedef struct bcmsdh_info bcmsdh_info_t;
-typedef void (*bcmsdh_cb_fn_t) (void *);
-
-/* Attach and build an interface to the underlying SD host driver.
- * - Allocates resources (structs, arrays, mem, OS handles, etc) needed by bcmsdh.
- * - Returns the bcmsdh handle and virtual address base for register access.
- * The returned handle should be used in all subsequent calls, but the bcmsh
- * implementation may maintain a single "default" handle (e.g. the first or
- * most recent one) to enable single-instance implementations to pass NULL.
- */
-extern bcmsdh_info_t *bcmsdh_attach(void *cfghdl, void **regsva, uint irq);
-
-/* Detach - freeup resources allocated in attach */
-extern int bcmsdh_detach(void *sdh);
-
-/* Query if SD device interrupts are enabled */
-extern bool bcmsdh_intr_query(void *sdh);
-
-/* Enable/disable SD interrupt */
-extern int bcmsdh_intr_enable(void *sdh);
-extern int bcmsdh_intr_disable(void *sdh);
-
-/* Register/deregister device interrupt handler. */
-extern int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
-extern int bcmsdh_intr_dereg(void *sdh);
-
-#if defined(DHD_DEBUG)
-/* Query pending interrupt status from the host controller */
-extern bool bcmsdh_intr_pending(void *sdh);
-#endif
-extern int bcmsdh_claim_host_and_lock(void *sdh);
-extern int bcmsdh_release_host_and_unlock(void *sdh);
-
-/* Register a callback to be called if and when bcmsdh detects
- * device removal. No-op in the case of non-removable/hardwired devices.
- */
-extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
-
-/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
- * fn: function number
- * addr: unmodified SDIO-space address
- * data: data byte to write
- * err: pointer to error code (or NULL)
- */
-extern u8 bcmsdh_cfg_read(void *sdh, uint func, u32 addr, int *err);
-extern void bcmsdh_cfg_write(void *sdh, uint func, u32 addr, u8 data,
- int *err);
-
-/* Read/Write 4bytes from/to cfg space */
-extern u32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, u32 addr,
- int *err);
-extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, u32 addr,
- u32 data, int *err);
-
-/* Read CIS content for specified function.
- * fn: function whose CIS is being requested (0 is common CIS)
- * cis: pointer to memory location to place results
- * length: number of bytes to read
- * Internally, this routine uses the values from the cis base regs (0x9-0xB)
- * to form an SDIO-space address to read the data from.
- */
-extern int bcmsdh_cis_read(void *sdh, uint func, u8 *cis, uint length);
-
-/* Synchronous access to device (client) core registers via CMD53 to F1.
- * addr: backplane address (i.e. >= regsva from attach)
- * size: register width in bytes (2 or 4)
- * data: data for register write
- */
-extern u32 bcmsdh_reg_read(void *sdh, u32 addr, uint size);
-extern u32 bcmsdh_reg_write(void *sdh, u32 addr, uint size, u32 data);
-
-/* Indicate if last reg read/write failed */
-extern bool bcmsdh_regfail(void *sdh);
-
-/* Buffer transfer to/from device (client) core via cmd53.
- * fn: function number
- * addr: backplane address (i.e. >= regsva from attach)
- * flags: backplane width, address increment, sync/async
- * buf: pointer to memory data buffer
- * nbytes: number of bytes to transfer to/from buf
- * pkt: pointer to packet associated with buf (if any)
- * complete: callback function for command completion (async only)
- * handle: handle for completion callback (first arg in callback)
- * Returns 0 or error code.
- * NOTE: Async operation is not currently supported.
- */
-typedef void (*bcmsdh_cmplt_fn_t) (void *handle, int status, bool sync_waiting);
-extern int bcmsdh_send_buf(void *sdh, u32 addr, uint fn, uint flags,
- u8 *buf, uint nbytes, void *pkt,
- bcmsdh_cmplt_fn_t complete, void *handle);
-extern int bcmsdh_recv_buf(void *sdh, u32 addr, uint fn, uint flags,
- u8 *buf, uint nbytes, struct sk_buff *pkt,
- bcmsdh_cmplt_fn_t complete, void *handle);
-
-/* Flags bits */
-#define SDIO_REQ_4BYTE 0x1 /* Four-byte target (backplane) width (vs. two-byte) */
-#define SDIO_REQ_FIXED 0x2 /* Fixed address (FIFO) (vs. incrementing address) */
-#define SDIO_REQ_ASYNC 0x4 /* Async request (vs. sync request) */
-
-/* Pending (non-error) return code */
-#define BCME_PENDING 1
-
-/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
- * rw: read or write (0/1)
- * addr: direct SDIO address
- * buf: pointer to memory data buffer
- * nbytes: number of bytes to transfer to/from buf
- * Returns 0 or error code.
- */
-extern int bcmsdh_rwdata(void *sdh, uint rw, u32 addr, u8 *buf,
- uint nbytes);
-
-/* Issue an abort to the specified function */
-extern int bcmsdh_abort(void *sdh, uint fn);
-
-/* Start SDIO Host Controller communication */
-extern int bcmsdh_start(void *sdh, int stage);
-
-/* Stop SDIO Host Controller communication */
-extern int bcmsdh_stop(void *sdh);
-
-/* Returns the "Device ID" of target device on the SDIO bus. */
-extern int bcmsdh_query_device(void *sdh);
-
-/* Returns the number of IO functions reported by the device */
-extern uint bcmsdh_query_iofnum(void *sdh);
-
-/* Miscellaneous knob tweaker. */
-extern int bcmsdh_iovar_op(void *sdh, const char *name,
- void *params, int plen, void *arg, int len,
- bool set);
-
-/* Reset and reinitialize the device */
-extern int bcmsdh_reset(bcmsdh_info_t *sdh);
-
-/* helper functions */
-
-extern void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh);
-
-/* callback functions */
-typedef struct {
- /* attach to device */
- void *(*attach) (u16 vend_id, u16 dev_id, u16 bus, u16 slot,
- u16 func, uint bustype, void *regsva, void *param);
- /* detach from device */
- void (*detach) (void *ch);
-} bcmsdh_driver_t;
-
-/* platform specific/high level functions */
-extern int bcmsdh_register(bcmsdh_driver_t *driver);
-extern void bcmsdh_unregister(void);
-extern bool bcmsdh_chipmatch(u16 vendor, u16 device);
-extern void bcmsdh_device_remove(void *sdh);
-
-/* Function to pass device-status bits to DHD. */
-extern u32 bcmsdh_get_dstatus(void *sdh);
-
-/* Function to return current window addr */
-extern u32 bcmsdh_cur_sbwad(void *sdh);
-
-/* Function to pass chipid and rev to lower layers for controlling pr's */
-extern void bcmsdh_chipinfo(void *sdh, u32 chip, u32 chiprev);
-
-#endif /* _BRCM_SDH_H_ */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_SOC_H
-#define _BRCM_SOC_H
-
-/* Include the soci specific files */
-#include <aidmp.h>
-
-/*
- * SOC Interconnect Address Map.
- * All regions may not exist on all chips.
- */
-#define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
-#define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
-#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
-#define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
-#define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
-#define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
-
-#ifdef SI_ENUM_BASE_VARIABLE
-#define SI_ENUM_BASE (sii->pub.si_enum_base)
-#else
-#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
-#endif /* SI_ENUM_BASE_VARIABLE */
-
-#define SI_WRAP_BASE 0x18100000 /* Wrapper space base */
-#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
-#define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software
- * convenience and could be changed if we
- * make any larger chips
- */
-
-#define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
-#define SI_FASTRAM_SWAPPED 0x19800000
-
-#define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
-#define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
-#define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
-#define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
-#define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
-#define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
-#define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
-#define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
-#define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
-#define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
-
-#define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
-#define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */
-#define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
-#define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
- * (2 ZettaBytes), low 32 bits
- */
-#define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
- * (2 ZettaBytes), high 32 bits
- */
-
-/* core codes */
-#define NODEV_CORE_ID 0x700 /* Invalid coreid */
-#define CC_CORE_ID 0x800 /* chipcommon core */
-#define ILINE20_CORE_ID 0x801 /* iline20 core */
-#define SRAM_CORE_ID 0x802 /* sram core */
-#define SDRAM_CORE_ID 0x803 /* sdram core */
-#define PCI_CORE_ID 0x804 /* pci core */
-#define MIPS_CORE_ID 0x805 /* mips core */
-#define ENET_CORE_ID 0x806 /* enet mac core */
-#define CODEC_CORE_ID 0x807 /* v90 codec core */
-#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
-#define ADSL_CORE_ID 0x809 /* ADSL core */
-#define ILINE100_CORE_ID 0x80a /* iline100 core */
-#define IPSEC_CORE_ID 0x80b /* ipsec core */
-#define UTOPIA_CORE_ID 0x80c /* utopia core */
-#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
-#define SOCRAM_CORE_ID 0x80e /* internal memory core */
-#define MEMC_CORE_ID 0x80f /* memc sdram core */
-#define OFDM_CORE_ID 0x810 /* OFDM phy core */
-#define EXTIF_CORE_ID 0x811 /* external interface core */
-#define D11_CORE_ID 0x812 /* 802.11 MAC core */
-#define APHY_CORE_ID 0x813 /* 802.11a phy core */
-#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
-#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
-#define MIPS33_CORE_ID 0x816 /* mips3302 core */
-#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
-#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
-#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
-#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
-#define SDIOH_CORE_ID 0x81b /* sdio host core */
-#define ROBO_CORE_ID 0x81c /* roboswitch core */
-#define ATA100_CORE_ID 0x81d /* parallel ATA core */
-#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
-#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
-#define PCIE_CORE_ID 0x820 /* pci express core */
-#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
-#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
-#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
-#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
-#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
-#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
-#define PMU_CORE_ID 0x827 /* PMU core */
-#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
-#define SDIOD_CORE_ID 0x829 /* SDIO device core */
-#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
-#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
-#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
-#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
-#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
-#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
-#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
-#define SC_CORE_ID 0x831 /* shared common core */
-#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
-#define SPIH_CORE_ID 0x833 /* SPI host core */
-#define I2S_CORE_ID 0x834 /* I2S core */
-#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
-#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
-#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
-#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
- * unused address ranges
- */
-
-/* There are TWO constants on all Broadcom chips: SI_ENUM_BASE above,
- * and chipcommon being the first core:
- */
-#define SI_CC_IDX 0
-
-/* SOC Interconnect types (aka chip types) */
-#define SOCI_AI 1
-
-/* Common core control flags */
-#define SICF_BIST_EN 0x8000
-#define SICF_PME_EN 0x4000
-#define SICF_CORE_BITS 0x3ffc
-#define SICF_FGC 0x0002
-#define SICF_CLOCK_EN 0x0001
-
-/* Common core status flags */
-#define SISF_BIST_DONE 0x8000
-#define SISF_BIST_ERROR 0x4000
-#define SISF_GATED_CLK 0x2000
-#define SISF_DMA64 0x1000
-#define SISF_CORE_BITS 0x0fff
-
-/* A register that is common to all cores to
- * communicate w/PMU regarding clock control.
- */
-#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
-
-/* clk_ctl_st register */
-#define CCS_FORCEALP 0x00000001 /* force ALP request */
-#define CCS_FORCEHT 0x00000002 /* force HT request */
-#define CCS_FORCEILP 0x00000004 /* force ILP request */
-#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
-#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
-#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
-#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
-#define CCS_ERSRC_REQ_SHIFT 8
-#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
-#define CCS_HTAVAIL 0x00020000 /* HT is available */
-#define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */
-#define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */
-#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
-#define CCS_ERSRC_STS_SHIFT 24
-
-#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
-#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
-
-/* Not really related to SOC Interconnect, but a couple of software
- * conventions for the use the flash space:
- */
-
-/* Minimum amount of flash we support */
-#define FLASH_MIN 0x00020000 /* Minimum flash size */
-
-/* A boot/binary may have an embedded block that describes its size */
-#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
-#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
-#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
-#define BISZ_TXTST_IDX 1 /* 1: text start */
-#define BISZ_TXTEND_IDX 2 /* 2: text end */
-#define BISZ_DATAST_IDX 3 /* 3: data start */
-#define BISZ_DATAEND_IDX 4 /* 4: data end */
-#define BISZ_BSSST_IDX 5 /* 5: bss start */
-#define BISZ_BSSEND_IDX 6 /* 6: bss end */
-#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
-
-#endif /* _BRCM_SOC_H */
+++ /dev/null
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _BRCM_SROM_H_
-#define _BRCM_SROM_H_
-
-/* Prototypes */
-extern int srom_var_init(struct si_pub *sih, uint bus, void *curmap,
- char **vars, uint *count);
-
-extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
- uint byteoff, uint nbytes, u16 *buf, bool check_crc);
-
-/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
- * and extract from it into name=value pairs
- */
-extern int srom_parsecis(u8 **pcis, uint ciscnt,
- char **vars, uint *count);
-#endif /* _BRCM_SROM_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_HW_IDS_H_
+#define _BRCM_HW_IDS_H_
+
+#define BCM4325_D11DUAL_ID 0x431b
+#define BCM4325_D11G_ID 0x431c
+#define BCM4325_D11A_ID 0x431d
+
+#define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
+#define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
+#define BCM4329_D11NDUAL_ID 0x432e
+
+#define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
+#define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
+#define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
+
+#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
+#define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db */
+
+#define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
+
+#define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
+#define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
+
+#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
+
+/* Chip IDs */
+#define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
+#define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
+
+#define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
+#define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
+#define BCM43421_CHIP_ID 43421 /* 43421 chipcommon chipid */
+#define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
+#define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
+#define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
+#define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
+#define BCM4325_CHIP_ID 0x4325 /* 4325 chipcommon chipid */
+#define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
+#define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
+#define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
+#define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
+
+/* these are router chips */
+#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
+#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
+#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
+#define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
+#define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
+
+/* Package IDs */
+#define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
+#define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
+#define BCM4717_PKG_ID 9 /* 4717 package id */
+#define BCM4718_PKG_ID 10 /* 4718 package id */
+#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
+#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
+#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
+
+/* boardflags */
+#define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
+#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
+#define BFL_FEM 0x00000800 /* Board supports the Front End Module */
+#define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
+#define BFL_NOPA 0x00010000 /* Board has no PA */
+#define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
+#define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
+#define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
+#define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
+#define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
+
+/* boardflags2 */
+#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
+#define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
+#define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
+#define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
+#define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
+#define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
+#define BFL2_LEGACY 0x00000080
+#define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
+#define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
+#define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
+#define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
+#define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
+#define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
+#define BFL2_IPALVLSHIFT_3P3 0x00020000
+#define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
+#define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio "ON"
+ * Most drivers will turn it off without this flag
+ * to save power.
+ */
+
+/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
+#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
+#define BOARD_GPIO_12 0x1000 /* gpio 12 */
+#define BOARD_GPIO_13 0x2000 /* gpio 13 */
+
+#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
+#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
+#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
+
+/* power control defines */
+#define PLL_DELAY 150 /* us pll on delay */
+#define FREF_DELAY 200 /* us fref change delay */
+#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
+
+/* Reference board types */
+#define SPI_BOARD 0x0402
+
+#endif /* _BRCM_HW_IDS_H_ */
#ifndef _SBCHIPC_H
#define _SBCHIPC_H
-#include "bcmdefs.h" /* for PAD macro */
+#include "defs.h" /* for PAD macro */
typedef volatile struct {
u32 chipid; /* 0x0 */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_DEFS_H_
+#define _BRCM_DEFS_H_
+
+#define SI_BUS 0
+#define PCI_BUS 1
+#define PCMCIA_BUS 2
+#define SDIO_BUS 3
+#define JTAG_BUS 4
+#define USB_BUS 5
+#define SPI_BUS 6
+
+#ifndef OFF
+#define OFF 0
+#endif
+
+#ifndef ON
+#define ON 1 /* ON = 1 */
+#endif
+
+#define AUTO (-1) /* Auto = -1 */
+
+/*
+ * Priority definitions according 802.1D
+ */
+#define PRIO_8021D_NONE 2
+#define PRIO_8021D_BK 1
+#define PRIO_8021D_BE 0
+#define PRIO_8021D_EE 3
+#define PRIO_8021D_CL 4
+#define PRIO_8021D_VI 5
+#define PRIO_8021D_VO 6
+#define PRIO_8021D_NC 7
+
+#define MAXPRIO 7
+#define NUMPRIO (MAXPRIO + 1)
+
+#define WL_NUMRATES 16 /* max # of rates in a rateset */
+
+typedef struct wl_rateset {
+ u32 count; /* # rates in this set */
+ u8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
+} wl_rateset_t;
+
+#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NUL */
+
+#define WLC_SET_CHANNEL 30
+#define WLC_SET_SRL 32
+#define WLC_SET_LRL 34
+
+#define WLC_SET_RATESET 72
+#define WLC_SET_BCNPRD 76
+#define WLC_GET_CURR_RATESET 114 /* current rateset */
+#define WLC_GET_PHYLIST 180
+
+/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
+#define WL_RADIO_SW_DISABLE (1<<0)
+#define WL_RADIO_HW_DISABLE (1<<1)
+#define WL_RADIO_MPC_DISABLE (1<<2)
+#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any channel */
+
+/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
+#define WL_TXPWR_OVERRIDE (1U<<31)
+
+/* band types */
+#define WLC_BAND_AUTO 0 /* auto-select */
+#define WLC_BAND_5G 1 /* 5 Ghz */
+#define WLC_BAND_2G 2 /* 2.4 Ghz */
+#define WLC_BAND_ALL 3 /* all bands */
+
+/* Values for PM */
+#define PM_OFF 0
+#define PM_MAX 1
+
+/* Message levels */
+#define LOG_ERROR_VAL 0x00000001
+#define LOG_TRACE_VAL 0x00000002
+
+#define PM_OFF 0
+#define PM_MAX 1
+#define PM_FAST 2
+
+/*
+ * Sonics Configuration Space Registers.
+ */
+#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
+
+/* cpp contortions to concatenate w/arg prescan */
+#ifndef PAD
+#define _PADLINE(line) pad ## line
+#define _XSTR(line) _PADLINE(line)
+#define PAD _XSTR(__LINE__)
+#endif
+
+#endif /* _BRCM_DEFS_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_SDH_H_
+#define _BRCM_SDH_H_
+
+#include <linux/skbuff.h>
+#define BCMSDH_ERROR_VAL 0x0001 /* Error */
+#define BCMSDH_INFO_VAL 0x0002 /* Info */
+extern const uint bcmsdh_msglevel;
+
+#ifdef BCMDBG
+#define BCMSDH_ERROR(x) \
+ do { \
+ if ((bcmsdh_msglevel & BCMSDH_ERROR_VAL) && net_ratelimit()) \
+ printk x; \
+ } while (0)
+#define BCMSDH_INFO(x) \
+ do { \
+ if ((bcmsdh_msglevel & BCMSDH_INFO_VAL) && net_ratelimit()) \
+ printk x; \
+ } while (0)
+#else /* BCMDBG */
+#define BCMSDH_ERROR(x)
+#define BCMSDH_INFO(x)
+#endif /* BCMDBG */
+
+#define SDIO_FUNC_0 0
+#define SDIO_FUNC_1 1
+#define SDIO_FUNC_2 2
+
+#define SDIOD_FBR_SIZE 0x100
+
+/* io_en */
+#define SDIO_FUNC_ENABLE_1 0x02
+#define SDIO_FUNC_ENABLE_2 0x04
+
+/* io_rdys */
+#define SDIO_FUNC_READY_1 0x02
+#define SDIO_FUNC_READY_2 0x04
+
+/* intr_status */
+#define INTR_STATUS_FUNC1 0x2
+#define INTR_STATUS_FUNC2 0x4
+
+/* Maximum number of I/O funcs */
+#define SDIOD_MAX_IOFUNCS 7
+
+/* forward declarations */
+typedef struct bcmsdh_info bcmsdh_info_t;
+typedef void (*bcmsdh_cb_fn_t) (void *);
+
+/* Attach and build an interface to the underlying SD host driver.
+ * - Allocates resources (structs, arrays, mem, OS handles, etc) needed by bcmsdh.
+ * - Returns the bcmsdh handle and virtual address base for register access.
+ * The returned handle should be used in all subsequent calls, but the bcmsh
+ * implementation may maintain a single "default" handle (e.g. the first or
+ * most recent one) to enable single-instance implementations to pass NULL.
+ */
+extern bcmsdh_info_t *bcmsdh_attach(void *cfghdl, void **regsva, uint irq);
+
+/* Detach - freeup resources allocated in attach */
+extern int bcmsdh_detach(void *sdh);
+
+/* Query if SD device interrupts are enabled */
+extern bool bcmsdh_intr_query(void *sdh);
+
+/* Enable/disable SD interrupt */
+extern int bcmsdh_intr_enable(void *sdh);
+extern int bcmsdh_intr_disable(void *sdh);
+
+/* Register/deregister device interrupt handler. */
+extern int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
+extern int bcmsdh_intr_dereg(void *sdh);
+
+#if defined(DHD_DEBUG)
+/* Query pending interrupt status from the host controller */
+extern bool bcmsdh_intr_pending(void *sdh);
+#endif
+extern int bcmsdh_claim_host_and_lock(void *sdh);
+extern int bcmsdh_release_host_and_unlock(void *sdh);
+
+/* Register a callback to be called if and when bcmsdh detects
+ * device removal. No-op in the case of non-removable/hardwired devices.
+ */
+extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
+
+/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
+ * fn: function number
+ * addr: unmodified SDIO-space address
+ * data: data byte to write
+ * err: pointer to error code (or NULL)
+ */
+extern u8 bcmsdh_cfg_read(void *sdh, uint func, u32 addr, int *err);
+extern void bcmsdh_cfg_write(void *sdh, uint func, u32 addr, u8 data,
+ int *err);
+
+/* Read/Write 4bytes from/to cfg space */
+extern u32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, u32 addr,
+ int *err);
+extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, u32 addr,
+ u32 data, int *err);
+
+/* Read CIS content for specified function.
+ * fn: function whose CIS is being requested (0 is common CIS)
+ * cis: pointer to memory location to place results
+ * length: number of bytes to read
+ * Internally, this routine uses the values from the cis base regs (0x9-0xB)
+ * to form an SDIO-space address to read the data from.
+ */
+extern int bcmsdh_cis_read(void *sdh, uint func, u8 *cis, uint length);
+
+/* Synchronous access to device (client) core registers via CMD53 to F1.
+ * addr: backplane address (i.e. >= regsva from attach)
+ * size: register width in bytes (2 or 4)
+ * data: data for register write
+ */
+extern u32 bcmsdh_reg_read(void *sdh, u32 addr, uint size);
+extern u32 bcmsdh_reg_write(void *sdh, u32 addr, uint size, u32 data);
+
+/* Indicate if last reg read/write failed */
+extern bool bcmsdh_regfail(void *sdh);
+
+/* Buffer transfer to/from device (client) core via cmd53.
+ * fn: function number
+ * addr: backplane address (i.e. >= regsva from attach)
+ * flags: backplane width, address increment, sync/async
+ * buf: pointer to memory data buffer
+ * nbytes: number of bytes to transfer to/from buf
+ * pkt: pointer to packet associated with buf (if any)
+ * complete: callback function for command completion (async only)
+ * handle: handle for completion callback (first arg in callback)
+ * Returns 0 or error code.
+ * NOTE: Async operation is not currently supported.
+ */
+typedef void (*bcmsdh_cmplt_fn_t) (void *handle, int status, bool sync_waiting);
+extern int bcmsdh_send_buf(void *sdh, u32 addr, uint fn, uint flags,
+ u8 *buf, uint nbytes, void *pkt,
+ bcmsdh_cmplt_fn_t complete, void *handle);
+extern int bcmsdh_recv_buf(void *sdh, u32 addr, uint fn, uint flags,
+ u8 *buf, uint nbytes, struct sk_buff *pkt,
+ bcmsdh_cmplt_fn_t complete, void *handle);
+
+/* Flags bits */
+#define SDIO_REQ_4BYTE 0x1 /* Four-byte target (backplane) width (vs. two-byte) */
+#define SDIO_REQ_FIXED 0x2 /* Fixed address (FIFO) (vs. incrementing address) */
+#define SDIO_REQ_ASYNC 0x4 /* Async request (vs. sync request) */
+
+/* Pending (non-error) return code */
+#define BCME_PENDING 1
+
+/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
+ * rw: read or write (0/1)
+ * addr: direct SDIO address
+ * buf: pointer to memory data buffer
+ * nbytes: number of bytes to transfer to/from buf
+ * Returns 0 or error code.
+ */
+extern int bcmsdh_rwdata(void *sdh, uint rw, u32 addr, u8 *buf,
+ uint nbytes);
+
+/* Issue an abort to the specified function */
+extern int bcmsdh_abort(void *sdh, uint fn);
+
+/* Start SDIO Host Controller communication */
+extern int bcmsdh_start(void *sdh, int stage);
+
+/* Stop SDIO Host Controller communication */
+extern int bcmsdh_stop(void *sdh);
+
+/* Returns the "Device ID" of target device on the SDIO bus. */
+extern int bcmsdh_query_device(void *sdh);
+
+/* Returns the number of IO functions reported by the device */
+extern uint bcmsdh_query_iofnum(void *sdh);
+
+/* Miscellaneous knob tweaker. */
+extern int bcmsdh_iovar_op(void *sdh, const char *name,
+ void *params, int plen, void *arg, int len,
+ bool set);
+
+/* Reset and reinitialize the device */
+extern int bcmsdh_reset(bcmsdh_info_t *sdh);
+
+/* helper functions */
+
+extern void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh);
+
+/* callback functions */
+typedef struct {
+ /* attach to device */
+ void *(*attach) (u16 vend_id, u16 dev_id, u16 bus, u16 slot,
+ u16 func, uint bustype, void *regsva, void *param);
+ /* detach from device */
+ void (*detach) (void *ch);
+} bcmsdh_driver_t;
+
+/* platform specific/high level functions */
+extern int bcmsdh_register(bcmsdh_driver_t *driver);
+extern void bcmsdh_unregister(void);
+extern bool bcmsdh_chipmatch(u16 vendor, u16 device);
+extern void bcmsdh_device_remove(void *sdh);
+
+/* Function to pass device-status bits to DHD. */
+extern u32 bcmsdh_get_dstatus(void *sdh);
+
+/* Function to return current window addr */
+extern u32 bcmsdh_cur_sbwad(void *sdh);
+
+/* Function to pass chipid and rev to lower layers for controlling pr's */
+extern void bcmsdh_chipinfo(void *sdh, u32 chip, u32 chiprev);
+
+#endif /* _BRCM_SDH_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_SOC_H
+#define _BRCM_SOC_H
+
+/* Include the soci specific files */
+#include <aidmp.h>
+
+/*
+ * SOC Interconnect Address Map.
+ * All regions may not exist on all chips.
+ */
+#define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
+#define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
+#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
+#define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
+#define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
+#define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
+
+#ifdef SI_ENUM_BASE_VARIABLE
+#define SI_ENUM_BASE (sii->pub.si_enum_base)
+#else
+#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
+#endif /* SI_ENUM_BASE_VARIABLE */
+
+#define SI_WRAP_BASE 0x18100000 /* Wrapper space base */
+#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
+#define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software
+ * convenience and could be changed if we
+ * make any larger chips
+ */
+
+#define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
+#define SI_FASTRAM_SWAPPED 0x19800000
+
+#define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
+#define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
+#define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
+#define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
+#define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
+#define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
+#define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
+#define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
+#define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
+#define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
+
+#define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
+#define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */
+#define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
+#define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
+ * (2 ZettaBytes), low 32 bits
+ */
+#define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
+ * (2 ZettaBytes), high 32 bits
+ */
+
+/* core codes */
+#define NODEV_CORE_ID 0x700 /* Invalid coreid */
+#define CC_CORE_ID 0x800 /* chipcommon core */
+#define ILINE20_CORE_ID 0x801 /* iline20 core */
+#define SRAM_CORE_ID 0x802 /* sram core */
+#define SDRAM_CORE_ID 0x803 /* sdram core */
+#define PCI_CORE_ID 0x804 /* pci core */
+#define MIPS_CORE_ID 0x805 /* mips core */
+#define ENET_CORE_ID 0x806 /* enet mac core */
+#define CODEC_CORE_ID 0x807 /* v90 codec core */
+#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
+#define ADSL_CORE_ID 0x809 /* ADSL core */
+#define ILINE100_CORE_ID 0x80a /* iline100 core */
+#define IPSEC_CORE_ID 0x80b /* ipsec core */
+#define UTOPIA_CORE_ID 0x80c /* utopia core */
+#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
+#define SOCRAM_CORE_ID 0x80e /* internal memory core */
+#define MEMC_CORE_ID 0x80f /* memc sdram core */
+#define OFDM_CORE_ID 0x810 /* OFDM phy core */
+#define EXTIF_CORE_ID 0x811 /* external interface core */
+#define D11_CORE_ID 0x812 /* 802.11 MAC core */
+#define APHY_CORE_ID 0x813 /* 802.11a phy core */
+#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
+#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
+#define MIPS33_CORE_ID 0x816 /* mips3302 core */
+#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
+#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
+#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
+#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
+#define SDIOH_CORE_ID 0x81b /* sdio host core */
+#define ROBO_CORE_ID 0x81c /* roboswitch core */
+#define ATA100_CORE_ID 0x81d /* parallel ATA core */
+#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
+#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
+#define PCIE_CORE_ID 0x820 /* pci express core */
+#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
+#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
+#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
+#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
+#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
+#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
+#define PMU_CORE_ID 0x827 /* PMU core */
+#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
+#define SDIOD_CORE_ID 0x829 /* SDIO device core */
+#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
+#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
+#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
+#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
+#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
+#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
+#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
+#define SC_CORE_ID 0x831 /* shared common core */
+#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
+#define SPIH_CORE_ID 0x833 /* SPI host core */
+#define I2S_CORE_ID 0x834 /* I2S core */
+#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
+#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
+#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
+#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
+ * unused address ranges
+ */
+
+/* There are TWO constants on all Broadcom chips: SI_ENUM_BASE above,
+ * and chipcommon being the first core:
+ */
+#define SI_CC_IDX 0
+
+/* SOC Interconnect types (aka chip types) */
+#define SOCI_AI 1
+
+/* Common core control flags */
+#define SICF_BIST_EN 0x8000
+#define SICF_PME_EN 0x4000
+#define SICF_CORE_BITS 0x3ffc
+#define SICF_FGC 0x0002
+#define SICF_CLOCK_EN 0x0001
+
+/* Common core status flags */
+#define SISF_BIST_DONE 0x8000
+#define SISF_BIST_ERROR 0x4000
+#define SISF_GATED_CLK 0x2000
+#define SISF_DMA64 0x1000
+#define SISF_CORE_BITS 0x0fff
+
+/* A register that is common to all cores to
+ * communicate w/PMU regarding clock control.
+ */
+#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
+
+/* clk_ctl_st register */
+#define CCS_FORCEALP 0x00000001 /* force ALP request */
+#define CCS_FORCEHT 0x00000002 /* force HT request */
+#define CCS_FORCEILP 0x00000004 /* force ILP request */
+#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
+#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
+#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
+#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
+#define CCS_ERSRC_REQ_SHIFT 8
+#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
+#define CCS_HTAVAIL 0x00020000 /* HT is available */
+#define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */
+#define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */
+#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
+#define CCS_ERSRC_STS_SHIFT 24
+
+#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
+#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
+
+/* Not really related to SOC Interconnect, but a couple of software
+ * conventions for the use the flash space:
+ */
+
+/* Minimum amount of flash we support */
+#define FLASH_MIN 0x00020000 /* Minimum flash size */
+
+/* A boot/binary may have an embedded block that describes its size */
+#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
+#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
+#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
+#define BISZ_TXTST_IDX 1 /* 1: text start */
+#define BISZ_TXTEND_IDX 2 /* 2: text end */
+#define BISZ_DATAST_IDX 3 /* 3: data start */
+#define BISZ_DATAEND_IDX 4 /* 4: data end */
+#define BISZ_BSSST_IDX 5 /* 5: bss start */
+#define BISZ_BSSEND_IDX 6 /* 6: bss end */
+#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
+
+#endif /* _BRCM_SOC_H */
--- /dev/null
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BRCM_SROM_H_
+#define _BRCM_SROM_H_
+
+/* Prototypes */
+extern int srom_var_init(struct si_pub *sih, uint bus, void *curmap,
+ char **vars, uint *count);
+
+extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
+ uint byteoff, uint nbytes, u16 *buf, bool check_crc);
+
+/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
+ * and extract from it into name=value pairs
+ */
+extern int srom_parsecis(u8 **pcis, uint ciscnt,
+ char **vars, uint *count);
+#endif /* _BRCM_SROM_H_ */
projects / deliverable / linux.git / commitdiff
