aarch64: Add new data cache maintenance operations

This patch adds support to two new system registers (CIPAPA, CIGDPAPA) in
conjunction with DC instruction. This change is part of RME (Realm Management
Extension).

gas/ChangeLog:

2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* testsuite/gas/aarch64/rme.d: Update test.
	* testsuite/gas/aarch64/rme.s: Update test.

opcodes/ChangeLog:

2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
	DC instruction.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2c498a6bceaabdf1c0c4c3a43f044811ef091544..da2f91f7a8cb7091fb6b269ffcb64365810e0086 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * testsuite/gas/aarch64/rme.d: Update test.
+       * testsuite/gas/aarch64/rme.s: Update test.
+
 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 
        * as.h (sprint_value): Delete.

diff --git a/gas/testsuite/gas/aarch64/rme.d b/gas/testsuite/gas/aarch64/rme.d
index 3667e870340f9b54fba4ef778f346a612e9339c2..89bedb85dba4960a578ded986668220dcd03fe41 100644 (file)
--- a/gas/testsuite/gas/aarch64/rme.d
+++ b/gas/testsuite/gas/aarch64/rme.d
@@ -12,3 +12,5 @@ Disassembly of section \.text:
    8:  d53e2180        mrs     x0, gptbr_el3
    c:  d51e21c0        msr     gpccr_el3, x0
   10:  d51e2180        msr     gptbr_el3, x0
+  14:  d50e7e20        dc      cipapa, x0
+  18:  d50e7ea0        dc      cigdpapa, x0

diff --git a/gas/testsuite/gas/aarch64/rme.s b/gas/testsuite/gas/aarch64/rme.s
index 89ee3a8260a908e15fba4d0dd99e2c8cf4fdf77c..b9a915df1d8201ef0bcf04c3ff8a6ed28c226418 100644 (file)
--- a/gas/testsuite/gas/aarch64/rme.s
+++ b/gas/testsuite/gas/aarch64/rme.s
@@ -8,3 +8,7 @@ mrs x0, gptbr_el3
 /* Write to RME system registers.  */
 msr gpccr_el3, x0
 msr gptbr_el3, x0
+
+/* RME data cache maintenance operations.   */
+dc cipapa, x0
+dc cigdpapa, x0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5dc51cd21b0a4a55c388d512bda0bbba74129b54..5bae9d06e6938109d9468f7b23222b277149da86 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
+       DC instruction.
+
 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 
        * aarch64-asm.c (encode_asimd_fcvt): Add initializer for

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 8727def17f450eba72ebcd439fea10be2eb86fb2..b315a82b14eff617d81abbc93fa00d0bb82d3b0c 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4763,6 +4763,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
     { "cisw",       CPENS (0, C7, C14, 2), F_HASXT },
     { "cigsw",      CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
     { "cigdsw",     CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
+    { "cipapa",     CPENS (6, C7, C14, 1), F_HASXT },
+    { "cigdpapa",   CPENS (6, C7, C14, 5), F_HASXT },
     { 0,       CPENS(0,0,0,0), 0 }
 };