* Interrupt Enable Reg OST_OIER
*/
#define OST_OIER (PKUNITY_OST_BASE + 0x001C)
+
/*
- * PWM Pulse Width Control Reg OST_PWMPWCR
- */
-#define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080)
-/*
- * PWM Duty Cycle Control Reg OST_PWMDCCR
- */
-#define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084)
-/*
- * PWM Period Control Reg OST_PWMPCR
+ * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80
+ * PWCR: Pulse Width Control Reg
+ * DCCR: Duty Cycle Control Reg
+ * PCR: Period Control Reg
*/
-#define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088)
+#define OST_PWM_PWCR (0x00)
+#define OST_PWM_DCCR (0x04)
+#define OST_PWM_PCR (0x08)
/*
* Match detected 0 OST_OSSR_M0
struct list_head node;
struct platform_device *pdev;
+ void __iomem *base;
+
const char *label;
struct clk *clk;
int clk_enabled;
* before writing to the registers
*/
clk_enable(pwm->clk);
- OST_PWMPWCR = prescale;
- OST_PWMDCCR = pv - dc;
- OST_PWMPCR = pv;
+
+ writel(prescale, pwm->base + OST_PWM_PWCR);
+ writel(pv - dc, pwm->base + OST_PWM_DCCR);
+ writel(pv, pwm->base + OST_PWM_PCR);
+
clk_disable(pwm->clk);
return 0;
goto err_free_clk;
}
+ pwm->base = ioremap_nocache(r->start, resource_size(r));
+ if (pwm->base == NULL) {
+ dev_err(&pdev->dev, "failed to remap memory resource\n");
+ ret = -EADDRNOTAVAIL;
+ goto err_release_mem;
+ }
+
__add_pwm(pwm);
platform_set_drvdata(pdev, pwm);
return pwm;
+err_release_mem:
+ release_mem_region(r->start, resource_size(r));
err_free_clk:
clk_put(pwm->clk);
err_free:
list_del(&pwm->node);
mutex_unlock(&pwm_lock);
+ iounmap(pwm->base);
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(r->start, resource_size(r));