* mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)".

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 82f08ce2a1d2a14bc2823ec04d6097b15c8bfcf5..d9dad0a990da8d0bd243c4dd7c5761616075c527 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+Mon Dec 16 13:00:15 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)".
+
 Sat Dec 14 22:36:20 1996  Ian Lance Taylor  <ian@cygnus.com>
 
        * mips-dis.c (print_mips16_insn_arg): The base address of a PC

diff --git a/opcodes/mn10200-opc.c b/opcodes/mn10200-opc.c
index 4ab833ee2f21baf5fcb50951a2787b6be8843539..9f420f6872e10c86a996d307e171d1e79adf11f6 100644 (file)
--- a/opcodes/mn10200-opc.c
+++ b/opcodes/mn10200-opc.c
@@ -172,6 +172,7 @@ const struct mn10200_opcode mn10200_opcodes[] = {
 { "mov",       0xc80000,       0xfc0000,       FMT_3, {MEM(IMM16_MEM), DN0}},
 { "mov",       0xf4c00000,     0xfffc0000,     FMT_7, {MEM(IMM24_MEM), DN0}},
 { "mov",       0x7000,         0xf000,         FMT_2, {MEM2(SD8,AN1), AM0}},
+{ "mov",       0x7000,         0xf000,         FMT_2, {MEM(AN1), AM0}},
 { "mov",       0xf7b00000,     0xfff00000,     FMT_6, {MEM2(SD16, AN1), AM0}},
 { "mov",       0xf4f00000,     0xfff00000,     FMT_7, {MEM2(IMM24,AN1), AM0}},
 { "mov",       0xf100,         0xffc0,         FMT_4, {MEM2(DI, AN1), AM0}},
@@ -185,6 +186,7 @@ const struct mn10200_opcode mn10200_opcodes[] = {
 { "mov",       0xc00000,       0xfc0000,       FMT_3, {DN0, MEM(IMM16_MEM)}},
 { "mov",       0xf4400000,     0xfffc0000,     FMT_7, {DN0, MEM(IMM24_MEM)}},
 { "mov",       0x5000,         0xf000,         FMT_2, {AM0, MEM2(SD8, AN1)}},
+{ "mov",       0x5000,         0xf000,         FMT_2, {AM0, MEM(AN1)}},
 { "mov",       0xf7a00000,     0xfff00000,     FMT_6, {AM0, MEM2(SD16, AN1)}},
 { "mov",       0xf4100000,     0xfff00000,     FMT_7, {AM0, MEM2(IMM24,AN1)}},
 { "mov",       0xf180,         0xffc0,         FMT_4, {AM0, MEM2(DI, AN1)}},