drm/i915: HSW FBC WaFbcDisableDpfcClockGating

Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

v2: Ville suggested to enable it back when disabling fbc to avoid wasting
    power.

v3: RMW to preserve other bits (by Ville)
v4: Fix from Ville: sed &/| at RMW
v5: Too far on sed.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Insert missing space that checkpatch spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d48558678e87aa9f8ca6772fd11f2728fa69652b..7af7ae66b3385ece1d108e5b099776e0df5df095 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -987,6 +987,9 @@
                                             _HSW_PIPE_SLICE_CHICKEN_1_A, + \
                                             _HSW_PIPE_SLICE_CHICKEN_1_B)
 
+#define HSW_CLKGATE_DISABLE_PART_1     0x46500
+#define   HSW_DPFC_GATING_DISABLE      (1<<23)
+
 /*
  * GPIO regs
  */

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4e678bad46d32054e80fe89b37b6faaec54e3f7e..d806448f84fa7a8d06075d3185b664ea2dea3041 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -248,6 +248,12 @@ static void ironlake_disable_fbc(struct drm_device *dev)
                                   I915_READ(ILK_DSPCLK_GATE_D) &
                                   ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 
+               if (IS_HASWELL(dev))
+                       /* WaFbcDisableDpfcClockGating */
+                       I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
+                                  I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
+                                  ~HSW_DPFC_GATING_DISABLE);
+
                DRM_DEBUG_KMS("disabled FBC\n");
        }
 }
@@ -285,6 +291,10 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
                /* WaFbcAsynchFlipDisableFbcQueue */
                I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
                           HSW_BYPASS_FBC_QUEUE);
+               /* WaFbcDisableDpfcClockGating */
+               I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
+                          I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
+                          HSW_DPFC_GATING_DISABLE);
        }
 
        I915_WRITE(SNB_DPFC_CTL_SA,