drm/i915: Tune down MCH_SSKPD values warning

Users often can't do anything about this since their vendors stopped
providing BIOS updates. Also we seem to be able to hack around it
with increased latency values, and thus far the only reports have
been for screens with really high resolutions. So tune it down to a
level where only developers can see it.

Also drop some of the end-user fluff.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f81a8f433a5ae4038f9891932c7176a058a8d698..72948a05312c34b1225528c83162c2dcc7d1d9f4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5230,11 +5230,9 @@ static void gen6_check_mch_setup(struct drm_device *dev)
        uint32_t tmp;
 
        tmp = I915_READ(MCH_SSKPD);
-       if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
-               DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
-               DRM_INFO("This can cause pipe underruns and display issues.\n");
-               DRM_INFO("Please upgrade your BIOS to fix this.\n");
-       }
+       if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
+               DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
+                             tmp);
 }
 
 static void gen6_init_clock_gating(struct drm_device *dev)