Fallout from "Reorder more powerpc64 sections for -z relro"

Commit 23283c1b changed the layout of some bss style sections on
powerpc64, but neglected to add a page gap before the third PT_LOAD
segment created by this reording.  Without a page gap we get two
PT_LOAD headers that overlap by one page in memory.  That shouldn't be
allowed because the dynamic loader will load garbage from the first
page of the last segment over the last page of the previous segment.

bfd/
	* elf.c (_bfd_elf_map_sections_to_segments): Do not make a new
	segment for loaded sections after nonloaded sections if the
	sections are on the same page.
ld/testsuite/
	* ld-powerpc/elfv2so.d: Update

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index c06c213b4b3a19684f13783d52e140c0c07825a6..5aa84e02812977037e996f1abac435f71bc447d9 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,9 @@
+2015-07-28  Alan Modra  <amodra@gmail.com>
+
+       * elf.c (_bfd_elf_map_sections_to_segments): Do not make a new
+       segment for loaded sections after nonloaded sections if the
+       sections are on the same page.
+
 2015-07-28  Iain Buclaw  <ibuclaw@gdcproject.org>
 
        * configure.in: Add asprintf and vasprintf to AC_CHECK_DECLS.

diff --git a/bfd/elf.c b/bfd/elf.c
index 977685407a862b6f1c19863609d2e482f9b557af..05ee0255d9182ddfc8fd9babe6b88934d687248c 100644 (file)
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -4220,11 +4220,18 @@ _bfd_elf_map_sections_to_segments (bfd *abfd, struct bfd_link_info *info)
              new_segment = TRUE;
            }
          else if ((last_hdr->flags & (SEC_LOAD | SEC_THREAD_LOCAL)) == 0
-                  && (hdr->flags & (SEC_LOAD | SEC_THREAD_LOCAL)) != 0)
+                  && (hdr->flags & (SEC_LOAD | SEC_THREAD_LOCAL)) != 0
+                  && ((abfd->flags & D_PAGED) == 0
+                      || (((last_hdr->lma + last_size - 1) & -maxpagesize)
+                          != (hdr->lma & -maxpagesize))))
            {
-             /* We don't want to put a loadable section after a
-                nonloadable section in the same segment.
-                Consider .tbss sections as loadable for this purpose.  */
+             /* We don't want to put a loaded section after a
+                nonloaded (ie. bss style) section in the same segment
+                as that will force the non-loaded section to be loaded.
+                Consider .tbss sections as loaded for this purpose.
+                However, like the writable/non-writable case below,
+                if they are on the same page then they must be put
+                in the same segment.  */
              new_segment = TRUE;
            }
          else if ((abfd->flags & D_PAGED) == 0)

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index e42477da7634a4cd0aead7efc19feaf5c54f36e9..d0b5daf42c64313e3611aa838eeeaf8e722b2145 100644 (file)
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-07-28  Alan Modra  <amodra@gmail.com>
+
+       * ld-powerpc/elfv2so.d: Update.
+
 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 
        * config/default.exp (NOPIE_CFLAGS): New.

diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index 906b375adff6ad0909d4df4ab1a2c4d75c52956b..d6f0b7da5b64f9262fd8212c4d003c8914765107 100644 (file)
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -7,33 +7,33 @@
 
 Disassembly of section \.text:
 
-0+320 <.*\.plt_call\.f4>:
+0+300 <.*\.plt_call\.f4>:
 .*:    (f8 41 00 18|18 00 41 f8)       std     r2,24\(r1\)
 .*:    (e9 82 80 38|38 80 82 e9)       ld      r12,-32712\(r2\)
 .*:    (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
 .*:    (4e 80 04 20|20 04 80 4e)       bctr
 
-0+330 <.*\.plt_call\.f3>:
+0+310 <.*\.plt_call\.f3>:
 .*:    (f8 41 00 18|18 00 41 f8)       std     r2,24\(r1\)
 .*:    (e9 82 80 28|28 80 82 e9)       ld      r12,-32728\(r2\)
 .*:    (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
 .*:    (4e 80 04 20|20 04 80 4e)       bctr
 
-0+340 <.*\.plt_call\.f2>:
+0+320 <.*\.plt_call\.f2>:
 .*:    (f8 41 00 18|18 00 41 f8)       std     r2,24\(r1\)
 .*:    (e9 82 80 30|30 80 82 e9)       ld      r12,-32720\(r2\)
 .*:    (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
 .*:    (4e 80 04 20|20 04 80 4e)       bctr
 
-0+350 <.*\.plt_call\.f1>:
+0+330 <.*\.plt_call\.f1>:
 .*:    (f8 41 00 18|18 00 41 f8)       std     r2,24\(r1\)
 .*:    (e9 82 80 40|40 80 82 e9)       ld      r12,-32704\(r2\)
 .*:    (7d 89 03 a6|a6 03 89 7d)       mtctr   r12
 .*:    (4e 80 04 20|20 04 80 4e)       bctr
 
-0+360 <f1>:
+0+340 <f1>:
 .*:    (3c 4c 00 02|02 00 4c 3c)       addis   r2,r12,2
-.*:    (38 42 82 a0|a0 82 42 38)       addi    r2,r2,-32096
+.*:    (38 42 82 c0|c0 82 42 38)       addi    r2,r2,-32064
 .*:    (7c 08 02 a6|a6 02 08 7c)       mflr    r0
 .*:    (f8 21 ff e1|e1 ff 21 f8)       stdu    r1,-32\(r1\)
 .*:    (f8 01 00 30|30 00 01 f8)       std     r0,48\(r1\)
@@ -50,10 +50,10 @@ Disassembly of section \.text:
 .*:    (38 21 00 20|20 00 21 38)       addi    r1,r1,32
 .*:    (7c 08 03 a6|a6 03 08 7c)       mtlr    r0
 .*:    (4e 80 00 20|20 00 80 4e)       blr
-.*:    (00 00 00 00|60 02 01 00)       .*
-.*:    (00 01 02 60|00 00 00 00)       .*
+.*:    (00 00 00 00|80 02 01 00)       .*
+.*:    (00 01 02 80|00 00 00 00)       .*
 
-0+3b0 <__glink_PLTresolve>:
+0+390 <__glink_PLTresolve>:
 .*:    (7c 08 02 a6|a6 02 08 7c)       mflr    r0
 .*:    (42 9f 00 05|05 00 9f 42)       bcl     .*
 .*:    (7d 68 02 a6|a6 02 68 7d)       mflr    r11