ARM: dts: qcom: apq8064 - Add SATA controller support

This patch adds AHCI based SATA controller support to APQ8064.
Tested on IFC6410 board.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>

diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 122bf34d752e5eb7badc04e448be8756f288883e..3d96cb85e2a2e65747a03b4fe061ee36e5421187 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -116,6 +116,15 @@
                        };
                };
 
+               sata_phy0: phy@1b400000 {
+                       status = "okay";
+               };
+
+               sata0: sata@29000000 {
+                       status          = "okay";
+                       target-supply   = <&pm8921_s4>;
+               };
+
                /* OTG */
                usb1_phy: phy@12500000 {
                        status          = "okay";

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 5aac9a58b02b27416eeb95478580198880f22247..1f900c755482a75ff1986ed8ee3824b3752cc914 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -379,6 +379,41 @@
                        usb-phy         = <&usb4_phy>;
                };
 
+               sata_phy0: phy@1b400000 {
+                       compatible      = "qcom,apq8064-sata-phy";
+                       status          = "disabled";
+                       reg             = <0x1b400000 0x200>;
+                       reg-names       = "phy_mem";
+                       clocks          = <&gcc SATA_PHY_CFG_CLK>;
+                       clock-names     = "cfg";
+                       #phy-cells      = <0>;
+               };
+
+               sata0: sata@29000000 {
+                       compatible              = "generic-ahci";
+                       status                  = "disabled";
+                       reg                     = <0x29000000 0x180>;
+                       interrupts              = <GIC_SPI 209 IRQ_TYPE_NONE>;
+
+                       clocks                  = <&gcc SFAB_SATA_S_H_CLK>,
+                                               <&gcc SATA_H_CLK>,
+                                               <&gcc SATA_A_CLK>,
+                                               <&gcc SATA_RXOOB_CLK>,
+                                               <&gcc SATA_PMALIVE_CLK>;
+                       clock-names             = "slave_iface",
+                                               "iface",
+                                               "bus",
+                                               "rxoob",
+                                               "core_pmalive";
+
+                       assigned-clocks         = <&gcc SATA_RXOOB_CLK>,
+                                               <&gcc SATA_PMALIVE_CLK>;
+                       assigned-clock-rates    = <100000000>, <100000000>;
+
+                       phys                    = <&sata_phy0>;
+                       phy-names               = "sata-phy";
+               };
+
                /* Temporary fixed regulator */
                vsdcc_fixed: vsdcc-regulator {
                        compatible = "regulator-fixed";