* itbl-lex.l: Fix indentation mistakes from indent program.
* itbl-ops.h: Add include for ansidecl.h.
Add PARAMS around function arguments.
Add declaration for itbl_have_entries.
* itbl-ops.c: Add PARAMS around function arguments.
* Makefile.in: Add itbl build rules.
Add dependancies for itbl files to mips target.
* as.c: Add itbl support.
Add new option "--insttbl" for dynamically extending instruction set.
* as.h: Declare insttbl_file_name;
the name of file defining extensions to the basic instruction set
* configure.in, configure: Add itbl-parse.o, itbl-lex.o, and
itbl-ops.o to extra_objects for mips configuration.
Add include file link from itbl-cpu.h to
config/itbl-${target_cpu_type}.h.
* config/tc-mips.c: Allow copz instructions.
Add notes for future additions to the itbl support.
Add debug macros.
(macro): Call itbl_assemble to assemble itbl instructions.
See if an unknown register is specified in an itbl entry.
+Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
+
+ * itbl-parse.y: Fix indentation mistakes from indent program.
+ * itbl-lex.l: Fix indentation mistakes from indent program.
+ * itbl-ops.h: Add include for ansidecl.h.
+ Add PARAMS around function arguments.
+ Add declaration for itbl_have_entries.
+ * itbl-ops.c: Add PARAMS around function arguments.
+ * Makefile.in: Add itbl build rules.
+ Add dependancies for itbl files to mips target.
+ * as.c: Add itbl support.
+ Add new option "--insttbl" for dynamically extending instruction set.
+ * as.h: Declare insttbl_file_name;
+ the name of file defining extensions to the basic instruction set
+ * configure.in, configure: Add itbl-parse.o, itbl-lex.o, and
+ itbl-ops.o to extra_objects for mips configuration.
+ Add include file link from itbl-cpu.h to
+ config/itbl-${target_cpu_type}.h.
+ * config/tc-mips.c: Allow copz instructions.
+ Add notes for future additions to the itbl support.
+ Add debug macros.
+ (macro): Call itbl_assemble to assemble itbl instructions.
+ See if an unknown register is specified in an itbl entry.
+
Sat Feb 22 20:53:01 1997 Fred Fish <fnf@cygnus.com>
* doc/internals.texi (CPU backend): Fix typo in md_section_align
description.
INSTALL_XFORM = $(INSTALL) -t='$(program_transform_name)'
INSTALL_XFORM1= $(INSTALL_XFORM) -b=.1
-DISTSTUFF= make-gas.com m68k-parse.c
+DISTSTUFF= make-gas.com m68k-parse.c itbl-parse.y itbl-lex.l itbl-ops.c
AR = ar
AR_FLAGS = qv
TEXI2DVI = texi2dvi
RANLIB = ranlib
CC = @CC@
-CFLAGS = -g
-LDFLAGS =
HLDFLAGS = @HLDFLAGS@
HLDENV = @HLDENV@
RPATH_ENVVAR = @RPATH_ENVVAR@
+CFLAGS = -g
+LDFLAGS =
MAKEOVERRIDES=
fi`
RUNTESTFLAGS=
+# use @target_cpu_type@ for refering to configured target name
+IT_HDRS=itbl-parse.h $(srcdir)/itbl-ops.h itbl-cpu.h
+IT_SRCS=itbl-parse.c itbl-lex.c $(srcdir)/itbl-ops.c
+IT_DEPS=$(srcdir)/itbl-parse.y $(srcdir)/itbl-lex.l $(srcdir)/config/itbl-@target_cpu_type@.h
+IT_OBJS=itbl-parse.o itbl-lex.o itbl-ops.o
+
# Lists of files for various purposes.
REAL_SOURCES = \
$(srcdir)/hash.c \
$(srcdir)/input-file.c \
$(srcdir)/input-scrub.c \
+ $(srcdir)/itbl-ops.c \
$(srcdir)/literal.c \
$(srcdir)/messages.c \
$(srcdir)/output-file.c \
$(srcdir)/frags.h \
$(srcdir)/hash.h \
$(srcdir)/input-file.h \
+ $(srcdir)/itbl-ops.h \
$(srcdir)/listing.h \
$(srcdir)/tc.h \
$(srcdir)/obj.h \
targ-env.h \
targ-cpu.h \
obj-format.h \
- atof-targ.h
+ atof-targ.h \
+ itbl-cpu.h
HEADERS = $(LINKED_HEADERS) $(REAL_HEADERS)
$(OBJS): config.h as.h targ-env.h obj-format.h targ-cpu.h flonum.h expr.h \
struc-symbol.h write.h frags.h hash.h read.h symbols.h tc.h obj.h \
- listing.h bignum.h $(srcdir)/../include/libiberty.h
+ listing.h bignum.h $(IT_HDRS) $(srcdir)/../include/libiberty.h
gasp.new: $(GASPOBJS) ../libiberty/libiberty.a
$(CC) $(ALL_CFLAGS) $(LDFLAGS) -o gasp.new $(GASPOBJS) ../libiberty/libiberty.a $(LOADLIBES)
TARG_CPU_DEP_m68k = $(srcdir)/../include/opcode/m68k.h \
$(srcdir)/config/m68k-parse.h subsegs.h
TARG_CPU_DEP_m88k = $(srcdir)/config/m88k-opcode.h subsegs.h
-TARG_CPU_DEP_mips = $(srcdir)/../include/opcode/mips.h subsegs.h
+TARG_CPU_DEP_mips = $(srcdir)/../include/opcode/mips.h subsegs.h \
+ $(srcdir)/config/itbl-mips.h
TARG_CPU_DEP_ns32k =
TARG_CPU_DEP_ppc = subsegs.h
TARG_CPU_DEP_sh = $(srcdir)/../opcodes/sh-opc.h subsegs.h
stabs.o : stabs.c subsegs.h $(srcdir)/../include/aout/stab_gnu.h
atof-targ.o : atof-targ.c
obj-format.o : obj-format.c
-targ-cpu.o : targ-cpu.c $(TARG_CPU_DEP_@target_cpu_type@)
+targ-cpu.o : targ-cpu.c $(TARG_CPU_DEP_@target_cpu_type@) $(IT_HDRS)
obj-elf.o : $(srcdir)/config/obj-elf.c
$(CC) -c $(ALL_CFLAGS) $(CPPFLAGS) $(INCLUDES) $(srcdir)/config/obj-elf.c
mv -f y.tab.c m68k-parse.c
m68k-parse.o: m68k-parse.c $(srcdir)/config/m68k-parse.h
+
+# The instruction table specification lexical analyzer and parser.
+
+itbl-cpu.h : $(srcdir)/config/itbl-@target_cpu_type@.h
+itbl-parse.h : $(srcdir)/itbl-parse.y
+itbl-parse.c : $(srcdir)/itbl-parse.y
+itbl-lex.c : $(srcdir)/itbl-lex.l
+
+itbl-lex.c: $(srcdir)/itbl-lex.l
+ $(LEX) $(LEXFLAGS) $(srcdir)/itbl-lex.l
+ mv -f lex.yy.c itbl-lex.c
+
+itbl-lex.o: itbl-lex.c
+ $(CC) -Wall -c $(ALL_CFLAGS) $(CPPFLAGS) $(INCLUDES) itbl-lex.c
+
+itbl-parse.c itbl-parse.h: $(srcdir)/itbl-parse.y
+ $(YACC) -d $(YACCFLAGS) $(srcdir)/itbl-parse.y
+ mv -f y.tab.c itbl-parse.c
+ mv -f y.tab.h itbl-parse.h
+
+itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h itbl-cpu.h
+ $(CC) -Wall -c $(ALL_CFLAGS) $(CPPFLAGS) $(INCLUDES) itbl-parse.c
+
+itbl-ops.o: $(srcdir)/itbl-ops.c \
+ $(srcdir)/itbl-ops.h itbl-cpu.h itbl-parse.h
+ $(CC) -c $(ALL_CFLAGS) $(CPPFLAGS) $(INCLUDES) $(srcdir)/itbl-ops.c
+
+# stand-alone assembler & disassembler
+itbl-test-ops.o: $(srcdir)/itbl-ops.c \
+ $(srcdir)/itbl-ops.h itbl-cpu.h itbl-parse.h
+ $(CC) -o itbl-test-ops.o -DSTAND_ALONE -c $(ALL_CFLAGS) $(CPPFLAGS) $(INCLUDES) $(srcdir)/itbl-ops.c
+
+itbl-test.o: $(srcdir)/itbl-test.c $(srcdir)/itbl-ops.h itbl-cpu.h
+ $(CC) -c -DSTAND_ALONE $(ALL_CFLAGS) $(INCLUDES) $(srcdir)/itbl-test.c
+
+IT_TEST_OBJS= itbl-parse.o itbl-lex.o itbl-test-ops.o
+itbl-test: $(IT_TEST_OBJS) itbl-test.o $(LIBDEPS)
+ $(CC) $(ALL_CFLAGS) $(LDFLAGS) -o itbl-test itbl-test.o $(IT_TEST_OBJS) $(LIBS)
+
+# target itbl definitions for configuring coprocessor itbl support.
+# configure should have taken care of this for us...
+itbl-cpu.h: $(srcdir)/config/itbl-@target_cpu_type@.h
+ ln -s $(srcdir)/config/itbl-@target_cpu_type@.h itbl-cpu.h
+
+
# Remake the info files.
doc: $(srcdir)/as.info
DISTCLEAN_HERE = config.status Makefile targ-env.h targ-cpu.h \
targ-cpu.c obj-format.h obj-format.c atof-targ.c TAGS \
+ atof-targ.h itbl-cpu.h \
config-stamp config.h conf config.log config.cache .gdbinit \
testsuite/Makefile testsuite/config.status
/* as.c - GAS main program.
- Copyright (C) 1987, 90, 91, 92, 93, 94, 95, 1996
+ Copyright (C) 1987, 90, 91, 92, 93, 94, 95, 96, 1997
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
*/
#include "ansidecl.h"
-#include "libiberty.h"
#define COMMON
};
static struct defsym_list *defsyms;
+
+/* Keep a record of the itbl files we read in. */
+
+struct itbl_file_list
+{
+ struct itbl_file_list *next;
+ char *name;
+};
+
+static struct itbl_file_list *itbl_files;
\f
void
print_version_id ()
--statistics print various measured statistics from execution\n\
--version print assembler version number and exit\n\
-W suppress warnings\n\
+-t,--itbl INSTTBL extend instruction set to include instrictions\n\
+ matching the specifications defined in file INSTTBL\n\
-w ignored\n\
-X ignored\n\
-Z generate object file even after errors\n");
'v',
#endif
'w', 'X',
+ /* New option for extending instruction set (see also --itbl below) */
+ 't',
'\0'
};
struct option *longopts;
#define OPTION_EMULATION (OPTION_STD_BASE + 6)
{"emulation", required_argument, NULL, OPTION_EMULATION},
#define OPTION_DEFSYM (OPTION_STD_BASE + 7)
- {"defsym", required_argument, NULL, OPTION_DEFSYM}
+ {"defsym", required_argument, NULL, OPTION_DEFSYM},
+#define OPTION_INSTTBL (OPTION_STD_BASE + 8)
+ /* New option for extending instruction set (see also -t above).
+ * The "-t file" or "--itbl file" option extends the basic set
+ * of valid instructions by reading "file", a text file containing
+ * a list of instruction formats. The additional opcodes and their
+ * formats are added to the built-in set of instructions, and
+ * mnemonics for new registers may also be defined. */
+ {"itbl", required_argument, NULL, OPTION_INSTTBL}
};
/* Construct the option lists from the standard list and the
}
break;
+ case OPTION_INSTTBL:
+ case 't':
+ {
+ /* optarg is the name of the file containing the instruction
+ formats, opcodes, register names, etc. */
+ struct itbl_file_list *n;
+
+ n = (struct itbl_file_list *) xmalloc (sizeof *n);
+ n->next = itbl_files;
+ n->name = optarg;
+ itbl_files = n;
+
+ /* Parse the file and add the new instructions to our internal
+ table. If multiple instruction tables are specified, the
+ information from this table gets appended onto the existing
+ internal table. */
+ itbl_files->name = xstrdup (optarg);
+ if (itbl_parse(itbl_files->name) != 0)
+ {
+ fprintf (stderr, "Failed to read instruction table %s\n",
+ itbl_files->name);
+ exit (EXIT_SUCCESS);
+ }
+ }
+ break;
+
case 'J':
flag_signed_overflow_ok = 1;
break;
start_time = get_run_time ();
+
if (debug_memory)
{
#ifdef BFD_ASSEMBLER
symbol_begin ();
frag_init ();
subsegs_begin ();
- parse_args (&argc, &argv);
+ parse_args (&argc, &argv);
read_begin ();
input_scrub_begin ();
expr_begin ();
tc_init_after_args ();
#endif
+ itbl_init ();
+
/* Now that we have fully initialized, and have created the output
file, define any symbols requested by --defsym command line
arguments. */
#endif
if (seen_at_least_1_file ()
- && !((had_warnings () && flag_always_generate_output)
- || had_errors () > 0))
+ && (flag_always_generate_output || had_errors () == 0))
keep_it = 1;
else
keep_it = 0;
output_file_close (out_file_name);
#endif
+ if (had_errors () > 0 && ! flag_always_generate_output)
+ keep_it = 0;
+
if (!keep_it)
unlink (out_file_name);
/* Use xexit instead of return, because under VMS environments they
may not place the same interpretation on the value given. */
- if ((had_warnings () && flag_always_generate_output)
- || had_errors () > 0)
+ if (had_errors () > 0)
xexit (EXIT_FAILURE);
xexit (EXIT_SUCCESS);
}
#endif
#include "opcode/mips.h"
+#include "itbl-ops.h"
+
+#ifdef DEBUG
+#define DBG(x) printf x
+#else
+#define DBG(x)
+#endif
#ifdef OBJ_MAYBE_ELF
/* Clean up namespace so we can include obj-elf.h too. */
/* As with "interlocks" this is used by hardware that has FP
(co-processor) interlocks. */
+/* Itbl support may require additional care here. */
static int cop_interlocks = -1;
/* MIPS PIC level. */
else
interlocks = 0;
+ /* Itbl support may require additional care here. */
if (mips_cpu == 4300)
cop_interlocks = 1;
else
if (mips16)
mips16_ip (str, &insn);
else
+ {
mips_ip (str, &insn);
+ DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
+ str, insn.insn_opcode));
+ }
if (insn_error)
{
delays delay the use of general register rt for one
instruction on the r3000. The r6000 and r4000 use
interlocks. */
+ /* Itbl support may require additional care here. */
know (prev_pinfo & INSN_WRITE_GPR_T);
if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
return 1;
delays delay the use of general register rt for one
instruction on the r3000. The r6000 and r4000 use
interlocks. */
+ /* Itbl support may require additional care here. */
know (prev_pinfo & INSN_WRITE_GPR_T);
if (mips_optimize == 0
|| insn_uses_reg (ip,
knowledge of CP0 handling, and the coprocessors other
than the floating point unit are not distinguished at
all. */
+ /* Itbl support may require additional care here. FIXME!
+ Need to modify this to include knowledge about
+ user specified delays! */
if (prev_pinfo & INSN_WRITE_FPR_T)
{
if (mips_optimize == 0
instruction may set the condition codes, and the
current instruction uses them, we must insert two
NOPS. */
+ /* Itbl support may require additional care here. */
if (mips_optimize == 0
|| ((prev_pinfo & INSN_WRITE_COND_CODE)
&& (pinfo & INSN_READ_COND_CODE)))
(this means it is a floating point comparison
instruction). If this instruction uses the condition
codes, we need to insert a single NOP. */
+ /* Itbl support may require additional care here. */
if (mips_optimize == 0
|| (pinfo & INSN_READ_COND_CODE))
++nops;
/* If the previous instruction was in a noreorder section, then
we don't want to insert the nop after all. */
+ /* Itbl support may require additional care here. */
if (prev_insn_unreordered)
nops = 0;
mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
if (pinfo & INSN_COP)
{
- /* We don't keep enough information to sort these cases out. */
+ /* We don't keep enough information to sort these cases out.
+ The itbl support does keep this information however, although
+ we currently don't support itbl fprmats as part of the cop
+ instruction. May want to add this support in the future. */
}
/* Never set the bit for $0, which is always zero. */
mips_gprmask &=~ 1 << 0;
|| (! mips16
&& mips_isa < 4
&& (prev_pinfo
+ /* Itbl support may require additional care here. */
& (INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
| INSN_WRITE_COND_CODE)))
&& mips_isa < 2
&& (prev_pinfo
& (INSN_LOAD_MEMORY_DELAY
+ /* Itbl support may require additional care here. */
| INSN_COPROC_MEMORY_DELAY)))
/* We can not swap with a branch instruction. */
|| (prev_pinfo
can not swap. */
|| (! mips16
&& mips_isa < 4
+ /* Itbl support may require additional care here. */
&& ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
|| (mips_isa < 2
&& (prev_prev_insn.insn_mo->pinfo
& (INSN_LOAD_MEMORY_DELAY
| INSN_COPROC_MEMORY_DELAY))))
{
+ /* Itbl support may require additional care here. */
++nops;
if ((! mips16
&& mips_isa < 4
&& ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
|| (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
{
+ /* Itbl support may require additional care here. */
if (! prev_prev_insn_unreordered)
++nops;
}
goto ld;
case M_LWC0_AB:
s = "lwc0";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto ld;
case M_LWC1_AB:
s = "lwc1";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto ld;
case M_LWC2_AB:
s = "lwc2";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto ld;
case M_LWC3_AB:
s = "lwc3";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto ld;
case M_LWL_AB:
goto ld;
case M_LDC1_AB:
s = "ldc1";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto ld;
case M_LDC2_AB:
s = "ldc2";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto ld;
case M_LDC3_AB:
s = "ldc3";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto ld;
case M_LDL_AB:
goto st;
case M_SWC0_AB:
s = "swc0";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto st;
case M_SWC1_AB:
s = "swc1";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto st;
case M_SWC2_AB:
s = "swc2";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto st;
case M_SWC3_AB:
s = "swc3";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto st;
case M_SWL_AB:
case M_SDC1_AB:
s = "sdc1";
coproc = 1;
+ /* Itbl support may require additional care here. */
goto st;
case M_SDC2_AB:
s = "sdc2";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto st;
case M_SDC3_AB:
s = "sdc3";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto st;
case M_SDL_AB:
tempreg = AT;
used_at = 1;
ld_st:
+ /* Itbl support may require additional care here. */
if (mask == M_LWC1_AB
|| mask == M_SWC1_AB
|| mask == M_LDC1_AB
* But, the resulting address is the same after relocation so why
* generate the extra instruction?
*/
+ /* Itbl support may require additional care here. */
coproc = 1;
if (mips_isa >= 2)
{
s = "swc1";
fmt = "T,o(b)";
+ /* Itbl support may require additional care here. */
coproc = 1;
goto ldd_std;
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when loading from memory. We set coproc if we must
load $fn+1 first. */
+ /* Itbl support may require additional care here. */
if (! target_big_endian)
coproc = 0;
used_at = 1;
}
+ /* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
coproc ? treg + 1 : treg,
(int) BFD_RELOC_MIPS_GPREL, tempreg);
undesired nop. */
hold_mips_optimize = mips_optimize;
mips_optimize = 2;
+ /* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
coproc ? treg : treg + 1,
(int) BFD_RELOC_MIPS_GPREL, tempreg);
if (p != NULL)
p += 4;
}
+ /* Itbl support may require additional care here. */
macro_build (p, &icnt, &offset_expr, s, fmt,
coproc ? treg + 1 : treg,
(int) BFD_RELOC_LO16, AT);
p += 4;
/* FIXME: How do we handle overflow here? */
offset_expr.X_add_number += 4;
+ /* Itbl support may require additional care here. */
macro_build (p, &icnt, &offset_expr, s, fmt,
coproc ? treg : treg + 1,
(int) BFD_RELOC_LO16, AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
mips_isa < 3 ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
+ /* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
coproc ? treg + 1 : treg,
(int) BFD_RELOC_LO16, AT);
nop. */
hold_mips_optimize = mips_optimize;
mips_optimize = 2;
+ /* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
coproc ? treg : treg + 1,
(int) BFD_RELOC_LO16, AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
mips_isa < 3 ? "addu" : "daddu",
"d,v,t", AT, breg, AT);
+ /* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
coproc ? treg + 1 : treg,
(int) BFD_RELOC_LO16, AT);
nop. */
hold_mips_optimize = mips_optimize;
mips_optimize = 2;
+ /* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &expr1, s, fmt,
coproc ? treg : treg + 1,
(int) BFD_RELOC_LO16, AT);
"d,v,t", AT, breg, AT);
p += 4;
}
+ /* Itbl support may require additional care here. */
macro_build (p, &icnt, &expr1, s, fmt,
coproc ? treg + 1 : treg,
(int) BFD_RELOC_LO16, AT);
nop. */
hold_mips_optimize = mips_optimize;
mips_optimize = 2;
+ /* Itbl support may require additional care here. */
macro_build (p, &icnt, &expr1, s, fmt,
coproc ? treg : treg + 1,
(int) BFD_RELOC_LO16, AT);
used_at = 1;
}
+ /* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
coproc ? treg + 1 : treg,
(int) BFD_RELOC_MIPS_GPREL, tempreg);
offset_expr.X_add_number += 4;
+ /* Itbl support may require additional care here. */
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
coproc ? treg : treg + 1,
(int) BFD_RELOC_MIPS_GPREL, tempreg);
macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg + 1,
(int) BFD_RELOC_LO16, breg);
return;
+
+ /* New code added to support COPZ instructions.
+ This code builds table entries out of the macros in mip_opcodes.
+ R4000 uses interlocks to handle coproc delays.
+ Other chips (like the R3000) require nops to be inserted for delays.
+
+ FIXME: Currently, we require that the user handle delays.
+ In order to fill delay slots for non-interlocked chips,
+ we must have a way to specify delays based on the coprocessor.
+ Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
+ What are the side-effects of the cop instruction?
+ What cache support might we have and what are its effects?
+ Both coprocessor & memory require delays. how long???
+ What registers are read/set/modified?
+
+ If an itbl is provided to interpret cop instructions,
+ this knowledge can be encoded in the itbl spec. */
+
+ case M_COP0:
+ s = "cop0";
+ goto copz;
+ case M_COP1:
+ s = "cop1";
+ goto copz;
+ case M_COP2:
+ s = "cop2";
+ goto copz;
+ case M_COP3:
+ s = "cop3";
+ copz:
+ /* For now we just do C (same as Cz). */
+ macro_build ((char *) NULL, &icnt, &offset_expr, s, "C");
+ return;
+
#ifdef LOSING_COMPILER
default:
+ /* Try and see if this is a new itbl instruction.
+ This code builds table entries out of the macros in mip_opcodes.
+ FIXME: For now we just assemble the expression and pass it's
+ value along as a 32-bit immediate.
+ We may want to have the assembler assemble this value,
+ so that we gain the assembler's knowledge of delay slots,
+ symbols, etc.
+ Would it be more efficient to use mask (id) here? */
+ if (itbl_have_entries
+ && immed_expr = itbl_assemble(ip->insn_mo->name, ""), immed_expr)
+ {
+ s = ip->insn_mo->name;
+ s2 = "cop3";
+ coproc = ITBL_DECODE_PNUM(immed_expr);;
+ macro_build ((char *) NULL, &icnt, &immed_expr, s, "C");
+ return;
+ }
macro2 (ip);
return;
}
break;
default:
+ /* FIXME: Check if this is one of the itbl macros, since they are
+ added dynamically. */
as_bad ("Macro %s not implemented yet", ip->insn_mo->name);
break;
}
s += 4;
regno = KT1;
}
+ else if (itbl_have_entries)
+ {
+ char *p, *n;
+ int r;
+
+ p = s+1; /* advance past '$' */
+ n = itbl_get_field(&p); /* n is name */
+
+ /* See if this is a register defined in an
+ itbl entry */
+ if (r = itbl_get_reg_val(n), r)
+ {
+ /* Get_field advances to the start of the next
+ field, so we need to back rack to the end of
+ the last field. */
+ if (p)
+ s = p-1;
+ else
+ s = strchr(s,'\0');
+ regno = r;
+ }
+ else
+ goto notreg;
+ }
else
goto notreg;
}
/* 'z' only matches $0. */
if (c == 'z' && regno != 0)
break;
+
+ /* Now that we have assembled one operand, we use the args string
+ * to figure out where it goes in the instruction. */
switch (c)
{
case 'r':
is $0. This only matches $0, and is checked
outside the switch. */
break;
+ case 'D':
+ /* Itbl operand; not yet implemented. FIXME ?? */
+ break;
+ /* What about all other operands like 'i',
+ which can be specified in the opcode table? */
}
lastregno = regno;
continue;
#endif
}
\f
+
+void
+mips_init_after_args ()
+{
+ if (itbl_have_entries)
+ {
+ /* initialize opcodes */
+ bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
+ mips_opcodes = (struct mips_opcode*) mips_builtin_opcodes;
+ }
+}
+
+
long
md_pcrel_from (fixP)
fixS *fixP;
;;
esac
+# additional parsers based on cpu-type
+
case ${cpu_type} in
m68k)
case ${extra_objects} in
*) extra_objects="$extra_objects m68k-parse.o" ;;
esac
;;
+
+ mips)
+ echo ${extra_objects} | grep -s "itbl-parse.o"
+ if test $? -ne 0 ; then
+ extra_objects="$extra_objects itbl-parse.o"
+ fi
+
+ echo ${extra_objects} | grep -s "itbl-lex.o"
+ if test $? -ne 0 ; then
+ extra_objects="$extra_objects itbl-lex.o"
+ fi
+
+ echo ${extra_objects} | grep -s "itbl-ops.o"
+ if test $? -ne 0 ; then
+ extra_objects="$extra_objects itbl-ops.o"
+ fi
+ ;;
+
+ *)
+ ;;
+
esac
# See if we really can support this configuration with the emulation code.
files="config/tc-${target_cpu_type}.c config/tc-${target_cpu_type}.h \
config/obj-${obj_format}.h config/obj-${obj_format}.c \
config/te-${te_file}.h config/atof-${atof}.c \
+ config/itbl-${target_cpu_type}.h \
$extra_files"
links="targ-cpu.c targ-cpu.h obj-format.h obj-format.c targ-env.h atof-targ.c \
+ itbl-cpu.h \
$extra_links"
case ${primary_bfd_gas}-${target_cpu_type}-${obj_format} in
*) extra_objects="$extra_objects m68k-parse.o" ;;
esac
;;
+
+ mips)
+ `echo ${extra_objects}` | grep -s "itbl-parse.o"
+ if test $? -ne 0 ; then
+ extra_objects="$extra_objects itbl-parse.o"
+ fi
+
+ `echo ${extra_objects}` | grep -s "itbl-lex.o"
+ if test $? -ne 0 ; then
+ extra_objects="$extra_objects itbl-lex.o"
+ fi
+
+ `echo ${extra_objects}` | grep -s "itbl-ops.o"
+ if test $? -ne 0 ; then
+ extra_objects="$extra_objects itbl-ops.o"
+ fi
+ ;;
+
+ *)
+ ;;
esac
# See if we really can support this configuration with the emulation code.
files="config/tc-${target_cpu_type}.c config/tc-${target_cpu_type}.h \
config/obj-${obj_format}.h config/obj-${obj_format}.c \
config/te-${te_file}.h config/atof-${atof}.c \
+ config/itbl-${target_cpu_type}.h \
$extra_files"
links="targ-cpu.c targ-cpu.h obj-format.h obj-format.c targ-env.h atof-targ.c \
+ itbl-cpu.h \
$extra_links"
case ${primary_bfd_gas}-${target_cpu_type}-${obj_format} in
+
+/* itbl-lex.l
+
+ Copyright (C) 1997 Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
%{
#include <stdio.h>
#include <string.h>
%%
-"creg"|"CREG" {
- return CREG;
- }
-"dreg"|"DREG" {
- return DREG;
- }
-"greg"|"GREG" {
- return GREG;
- }
-"immed"|"IMMED" {
- return IMMED;
- }
-"addr"|"ADDR" {
- return ADDR;
- }
-"insn"|"INSN" {
- return INSN;
- }
+"creg"|"CREG" {
+ return CREG;
+ }
+"dreg"|"DREG" {
+ return DREG;
+ }
+"greg"|"GREG" {
+ return GREG;
+ }
+"immed"|"IMMED" {
+ return IMMED;
+ }
+"addr"|"ADDR" {
+ return ADDR;
+ }
+"insn"|"INSN" {
+ return INSN;
+ }
"p"{DIGIT} {
- yytext[yyleng]=0;
- yylval.processor = strtoul(yytext+1,0,0);
- return PNUM;
- }
-{DIGIT}+ {
- yytext[yyleng]=0;
- yylval.num = strtoul(yytext,0,0);
- return NUM;
- }
-"0x"{HEX}+ {
- yytext[yyleng]=0;
- yylval.num = strtoul(yytext,0,0);
- return NUM;
- }
+ yytext[yyleng] = 0;
+ yylval.processor = strtoul (yytext+1, 0, 0);
+ return PNUM;
+ }
+{DIGIT}+ {
+ yytext[yyleng] = 0;
+ yylval.num = strtoul (yytext, 0, 0);
+ return NUM;
+ }
+"0x"{HEX}+ {
+ yytext[yyleng] = 0;
+ yylval.num = strtoul (yytext, 0, 0);
+ return NUM;
+ }
{ALPHA}{ALNUM}* {
- yytext[yyleng]=0;
- yylval.str = strdup(yytext);
- return ID;
- }
+ yytext[yyleng] = 0;
+ yylval.str = strdup (yytext);
+ return ID;
+ }
";"|"#" {
- int c;
- while ((c = input()) != EOF) {
- if (c == '\n')
- {
- unput(c);
- break;
- }
- }
- }
+ int c;
+ while ((c = input ()) != EOF)
+ {
+ if (c == '\n')
+ {
+ unput (c);
+ break;
+ }
+ }
+ }
"\n" {
- insntbl_line++;
- MDBG(("in lex, NL=%d (x%x)\n",NL,NL));
- return NL;
- }
-" "|"\t" { }
-. {
- MDBG(("char=%x,%d\n",yytext[0],yytext[0]));
- return yytext[0];
- }
+ insntbl_line++;
+ MDBG (("in lex, NL = %d (x%x)\n", NL, NL));
+ return NL;
+ }
+" "|"\t" {
+ }
+. {
+ MDBG (("char = %x, %d\n", yytext[0], yytext[0]));
+ return yytext[0];
+ }
%%
-int yywrap() { return 1; }
+int
+yywrap ()
+ {
+ return 1;
+ }
+/* itbl-ops.c
+
+ Copyright (C) 1997 Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
/*======================================================================*/
/*
- * Herein lies the support for dynamic specification of processor
+ * Herein lies the support for dynamic specification of processor
* instructions and registers. Mnemonics, values, and formats for each
- * instruction and register are specified in an ascii file consisting of
+ * instruction and register are specified in an ascii file consisting of
* table entries. The grammar for the table is defined in the document
* "Processor instruction table specification".
*
- * Instructions use the gnu assembler syntax, with the addition of
+ * Instructions use the gnu assembler syntax, with the addition of
* allowing mnemonics for register.
* Eg. "func $2,reg3,0x100,symbol ; comment"
* func - opcode name
* reg3 - mnemonic for processor's register defined in table
* 0xddd..d - immediate value
* symbol - address of label or external symbol
- *
- * First, itbl_parse reads in the table of register and instruction
+ *
+ * First, itbl_parse reads in the table of register and instruction
* names and formats, and builds a list of entries for each
* processor/type combination. lex and yacc are used to parse
* the entries in the table and call functions defined here to
* add each entry to our list.
- *
- * Then, when assembling or disassembling, these functions are called to
- * 1) get information on a processor's registers and
+ *
+ * Then, when assembling or disassembling, these functions are called to
+ * 1) get information on a processor's registers and
* 2) assemble/disassemble an instruction.
- * To assemble(disassemble) an instruction, the function
- * itbl_assemble(itbl_disassemble) is called to search the list of
- * instruction entries, and if a match is found, uses the format
- * described in the instruction entry structure to complete the action.
- *
+ * To assemble(disassemble) an instruction, the function
+ * itbl_assemble(itbl_disassemble) is called to search the list of
+ * instruction entries, and if a match is found, uses the format
+ * described in the instruction entry structure to complete the action.
+ *
* Eg. Suppose we have a Mips coprocessor "cop3" with data register "d2"
* and we want to define function "pig" which takes two operands.
- *
+ *
* Given the table entries:
* "p3 insn pig 0x1:24-21 dreg:20-16 immed:15-0"
* "p3 dreg d2 0x2"
* and that the instruction encoding for coprocessor pz has encoding:
* #define MIPS_ENCODE_COP_NUM(z) ((0x21|(z<<1))<<25)
* #define ITBL_ENCODE_PNUM(pnum) MIPS_ENCODE_COP_NUM(pnum)
- *
+ *
* a structure to describe the instruction might look something like:
* struct itbl_entry = {
* e_processor processor = e_p3
* uint flags = 0
* struct itbl_range range = 24-21
* struct itbl_field *field = {
- * e_type type = e_dreg
+ * e_type type = e_dreg
* struct itbl_range range = 20-16
* struct itbl_field *next = {
* e_type type = e_immed
* struct itbl_range range = 15-0
* struct itbl_field *next = 0
- * };
- * };
+ * };
+ * };
* struct itbl_entry *next = 0
* };
*
* And the assembler instructions:
* "pig d2,0x100"
* "pig $2,0x100"
- *
+ *
* would both assemble to the hex value:
* "0x4e220100"
- *
- */
+ *
+ */
#include <stdio.h>
#include <stdlib.h>
#define ASSERT(x) assert(x)
#define DBG(x) printf x
#else
-#define ASSERT(x)
+#define ASSERT(x)
#define DBG(x)
#endif
#define min(a,b) (a<b?a:b)
#endif
+int itbl_have_entries = 0;
+
/*======================================================================*/
/* structures for keeping itbl format entries */
-struct itbl_range {
- int sbit; /* mask starting bit position */
- int ebit; /* mask ending bit position */
- };
-
-struct itbl_field {
- e_type type; /* dreg/creg/greg/immed/symb */
- struct itbl_range range; /* field's bitfield range within instruction */
- unsigned long flags; /* field flags */
- struct itbl_field *next; /* next field in list */
- };
-
-
+struct itbl_range
+ {
+ int sbit; /* mask starting bit position */
+ int ebit; /* mask ending bit position */
+ };
+
+struct itbl_field
+ {
+ e_type type; /* dreg/creg/greg/immed/symb */
+ struct itbl_range range; /* field's bitfield range within instruction */
+ unsigned long flags; /* field flags */
+ struct itbl_field *next; /* next field in list */
+ };
+
+
/* These structures define the instructions and registers for a processor.
- * If the type is an instruction, the structure defines the format of an
- * instruction where the fields are the list of operands.
- * The flags field below uses the same values as those defined in the
+ * If the type is an instruction, the structure defines the format of an
+ * instruction where the fields are the list of operands.
+ * The flags field below uses the same values as those defined in the
* gnu assembler and are machine specific. */
-struct itbl_entry {
- e_processor processor; /* processor number */
- e_type type; /* dreg/creg/greg/insn */
- char *name; /* mnemionic name for insn/register */
- unsigned long value; /* opcode/instruction mask/register number */
- unsigned long flags; /* effects of the instruction */
- struct itbl_range range;/* bit range within instruction for value */
- struct itbl_field *fields; /* list of operand definitions (if any) */
- struct itbl_entry *next; /* next entry */
-};
+struct itbl_entry
+ {
+ e_processor processor; /* processor number */
+ e_type type; /* dreg/creg/greg/insn */
+ char *name; /* mnemionic name for insn/register */
+ unsigned long value; /* opcode/instruction mask/register number */
+ unsigned long flags; /* effects of the instruction */
+ struct itbl_range range; /* bit range within instruction for value */
+ struct itbl_field *fields; /* list of operand definitions (if any) */
+ struct itbl_entry *next; /* next entry */
+ };
/* local data and structures */
/* Array of entries for each processor and entry type */
static struct itbl_entry *entries[e_nprocs][e_ntypes] =
{
- { 0, 0, 0, 0, 0, 0 },
- { 0, 0, 0, 0, 0, 0 },
- { 0, 0, 0, 0, 0, 0 },
- { 0, 0, 0, 0, 0, 0 }
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0}
};
/* local prototypes */
-static unsigned long build_opcode(struct itbl_entry *e);
-static e_type get_type(int yytype);
-static e_processor get_processor(int yyproc);
-static struct itbl_entry **get_entries(e_processor processor, e_type type);
-static struct itbl_entry *find_entry_byname(e_processor processor, e_type type,
- char *name);
-static struct itbl_entry *find_entry_byval(e_processor processor, e_type type,
- unsigned long val, struct itbl_range *r);
-static struct itbl_entry *alloc_entry(e_processor processor, e_type type, char *name,
- unsigned long value);
-static unsigned long apply_range(unsigned long value, struct itbl_range r);
-static unsigned long extract_range(unsigned long value, struct itbl_range r);
-static struct itbl_field *alloc_field(e_type type, int sbit, int ebit, unsigned long flags);
+static unsigned long build_opcode PARAMS ((struct itbl_entry *e));
+static e_type get_type PARAMS ((int yytype));
+static e_processor get_processor PARAMS ((int yyproc));
+static struct itbl_entry **get_entries PARAMS ((e_processor processor,
+ e_type type));
+static struct itbl_entry *find_entry_byname PARAMS ((e_processor processor,
+ e_type type, char *name));
+static struct itbl_entry *find_entry_byval PARAMS ((e_processor processor,
+ e_type type, unsigned long val, struct itbl_range *r));
+static struct itbl_entry *alloc_entry PARAMS ((e_processor processor,
+ e_type type, char *name, unsigned long value));
+static unsigned long apply_range PARAMS ((unsigned long value,
+ struct itbl_range r));
+static unsigned long extract_range PARAMS ((unsigned long value,
+ struct itbl_range r));
+static struct itbl_field *alloc_field PARAMS ((e_type type, int sbit,
+ int ebit, unsigned long flags));
/*======================================================================*/
/* Open the table and use lex and yacc to parse the entries.
* Return 1 for failure; 0 for success. */
-int itbl_parse(char* insntbl)
+int
+itbl_parse (char *insntbl)
{
- extern FILE *yyin;
- extern int yyparse(void);
- yyin = fopen(insntbl, "r");
- if (yyin == 0)
- {
- printf("Can't open processor instruction specification file \"%s\"\n",
- insntbl);
- return 1;
- }
- else
- {
- while (yyparse());
- }
- fclose(yyin);
- return 0;
+ extern FILE *yyin;
+ extern int yyparse (void);
+ yyin = fopen (insntbl, "r");
+ if (yyin == 0)
+ {
+ printf ("Can't open processor instruction specification file \"%s\"\n",
+ insntbl);
+ return 1;
+ }
+ else
+ {
+ while (yyparse ());
+ }
+ fclose (yyin);
+ itbl_have_entries = 1;
+ return 0;
}
/* Add a register entry */
-struct itbl_entry *itbl_add_reg(int yyprocessor, int yytype, char *regname,
- int regnum)
+struct itbl_entry *
+itbl_add_reg (int yyprocessor, int yytype, char *regname,
+ int regnum)
{
-#if 0 /* ndef STAND_ALONE */
+#if 0
#include "as.h"
#include "symbols.h"
/* Since register names don't have a prefix, we put them in the symbol table so
they can't be used as symbols. This also simplifies argument parsing as
we can let gas parse registers for us. The recorded register number is
regnum. */
- /* Use symbol_create here instead of symbol_new so we don't try to
+ /* Use symbol_create here instead of symbol_new so we don't try to
output registers into the object file's symbol table. */
- symbol_table_insert (symbol_create (regname, reg_section,
- regnum, &zero_address_frag));
+ symbol_table_insert (symbol_create (regname, reg_section,
+ regnum, &zero_address_frag));
#endif
- return alloc_entry(get_processor(yyprocessor),get_type(yytype),regname,
- (unsigned long)regnum);
+ return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname,
+ (unsigned long) regnum);
}
/* Add an instruction entry */
-struct itbl_entry *itbl_add_insn(int yyprocessor, char *name, unsigned long value,
- int sbit, int ebit, unsigned long flags)
+struct itbl_entry *
+itbl_add_insn (int yyprocessor, char *name, unsigned long value,
+ int sbit, int ebit, unsigned long flags)
{
- struct itbl_entry *e;
- e = alloc_entry(get_processor(yyprocessor),e_insn,name,value);
- if (e)
- {
- e->range.sbit=sbit;
- e->range.ebit=ebit;
- e->flags=flags;
- itbl_num_opcodes++;
- }
- return e;
+ struct itbl_entry *e;
+ e = alloc_entry (get_processor (yyprocessor), e_insn, name, value);
+ if (e)
+ {
+ e->range.sbit = sbit;
+ e->range.ebit = ebit;
+ e->flags = flags;
+ itbl_num_opcodes++;
+ }
+ return e;
}
/* Add an operand to an instruction entry */
-struct itbl_field *itbl_add_operand(struct itbl_entry *e, int yytype, int sbit,
- int ebit, unsigned long flags)
+struct itbl_field *
+itbl_add_operand (struct itbl_entry *e, int yytype, int sbit,
+ int ebit, unsigned long flags)
{
- struct itbl_field *f, **last_f;
- if (!e)
- return 0;
- /* Add to end of fields' list. */
- f = alloc_field(get_type(yytype),sbit,ebit,flags);
- if (f)
- {
- last_f = &e->fields;
- while (*last_f)
- last_f = &(*last_f)->next;
- *last_f = f;
- f->next = 0;
- }
- return f;
+ struct itbl_field *f, **last_f;
+ if (!e)
+ return 0;
+ /* Add to end of fields' list. */
+ f = alloc_field (get_type (yytype), sbit, ebit, flags);
+ if (f)
+ {
+ last_f = &e->fields;
+ while (*last_f)
+ last_f = &(*last_f)->next;
+ *last_f = f;
+ f->next = 0;
+ }
+ return f;
}
#ifndef STAND_ALONE
#include "as.h"
#include "symbols.h"
-static void append_insns_as_macros(void);
+static void append_insns_as_macros (void);
/* initialize for gas */
-void itbl_init(void)
+void
+itbl_init (void)
{
- struct itbl_entry *e, **es;
- e_processor procn;
- e_type type;
+ struct itbl_entry *e, **es;
+ e_processor procn;
+ e_type type;
/* Since register names don't have a prefix, put them in the symbol table so
they can't be used as symbols. This simplifies argument parsing as
we can let gas parse registers for us. */
- /* Use symbol_create instead of symbol_new so we don't try to
+ /* Use symbol_create instead of symbol_new so we don't try to
output registers into the object file's symbol table. */
- for (type=e_regtype0; type<e_nregtypes; type++)
- for (procn=e_p0; procn<e_nprocs; procn++)
- {
- es = get_entries(procn, type);
- for (e=*es; e; e=e->next)
- {
- symbol_table_insert (symbol_create (e->name, reg_section,
- e->value, &zero_address_frag));
- }
- }
- append_insns_as_macros();
+ for (type = e_regtype0; type < e_nregtypes; type++)
+ for (procn = e_p0; procn < e_nprocs; procn++)
+ {
+ es = get_entries (procn, type);
+ for (e = *es; e; e = e->next)
+ {
+ symbol_table_insert (symbol_create (e->name, reg_section,
+ e->value, &zero_address_frag));
+ }
+ }
+ append_insns_as_macros ();
}
-/* Append insns to opcodes table and increase number of opcodes */
-/* Structure of opcodes table: */
-/* struct itbl_opcode
-/* {
-/* const char *name;
-/* const char *args; /* string describing the arguments . */
-/* unsigned long match; /* opcode, or ISA level if pinfo=INSN_MACRO */
-/* unsigned long mask; /* opcode mask, or macro id if pinfo=INSN_MACRO */
-/* unsigned long pinfo; /* insn flags, or INSN_MACRO */
-/* };
-/* examples:
- * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
- * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
+/* Append insns to opcodes table and increase number of opcodes
+ * Structure of opcodes table:
+ * struct itbl_opcode
+ * {
+ * const char *name;
+ * const char *args; - string describing the arguments.
+ * unsigned long match; - opcode, or ISA level if pinfo=INSN_MACRO
+ * unsigned long mask; - opcode mask, or macro id if pinfo=INSN_MACRO
+ * unsigned long pinfo; - insn flags, or INSN_MACRO
+ * };
+ * examples:
+ * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
+ * {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
*/
-static char *form_args(struct itbl_entry *e);
-static void append_insns_as_macros(void)
+
+static char *form_args (struct itbl_entry *e);
+static void
+append_insns_as_macros (void)
{
- struct ITBL_OPCODE_STRUCT *new_opcodes, *o;
- struct itbl_entry *e, **es;
- int n, id, size, new_size, new_num_opcodes;
+ struct ITBL_OPCODE_STRUCT *new_opcodes, *o;
+ struct itbl_entry *e, **es;
+ int n, id, size, new_size, new_num_opcodes;
- ASSERT(itbl_num_opcodes > 0);
- if (!itbl_num_opcodes) /* no new instructions to add! */
- {
- return;
- }
- DBG(("previous num_opcodes=%d\n",ITBL_NUM_OPCODES));
+ ASSERT (itbl_num_opcodes > 0);
+ if (!itbl_num_opcodes) /* no new instructions to add! */
+ {
+ return;
+ }
+ DBG (("previous num_opcodes=%d\n", ITBL_NUM_OPCODES));
- new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes;
- ASSERT(new_num_opcodes >= itbl_num_opcodes);
+ new_num_opcodes = ITBL_NUM_OPCODES + itbl_num_opcodes;
+ ASSERT (new_num_opcodes >= itbl_num_opcodes);
- size = sizeof(struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES;
- ASSERT(size >= 0);
- DBG(("I get=%d\n", size / sizeof(ITBL_OPCODES[0])));
+ size = sizeof (struct ITBL_OPCODE_STRUCT) * ITBL_NUM_OPCODES;
+ ASSERT (size >= 0);
+ DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0])));
- new_size = sizeof(struct ITBL_OPCODE_STRUCT) * new_num_opcodes;
- ASSERT(new_size > size);
+ new_size = sizeof (struct ITBL_OPCODE_STRUCT) * new_num_opcodes;
+ ASSERT (new_size > size);
- /* FIXME since ITBL_OPCODES culd be a static table,
+ /* FIXME since ITBL_OPCODES culd be a static table,
we can't realloc or delete the old memory. */
- new_opcodes = (struct ITBL_OPCODE_STRUCT*)malloc(new_size);
- if (!new_opcodes)
- {
- printf("Unable to allocate memory for new instructions\n");
- return;
- }
- if (size) /* copy prexisting opcodes table */
- memcpy(new_opcodes, ITBL_OPCODES, size);
+ new_opcodes = (struct ITBL_OPCODE_STRUCT *) malloc (new_size);
+ if (!new_opcodes)
+ {
+ printf ("Unable to allocate memory for new instructions\n");
+ return;
+ }
+ if (size) /* copy prexisting opcodes table */
+ memcpy (new_opcodes, ITBL_OPCODES, size);
- /* FIXME! some NUMOPCODES are calculated expressions.
+ /* FIXME! some NUMOPCODES are calculated expressions.
These need to be changed before itbls can be supported. */
- id = ITBL_NUM_MACROS; /* begin the next macro id after the last */
- o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */
- for (n=e_p0; n<e_nprocs; n++)
+ id = ITBL_NUM_MACROS; /* begin the next macro id after the last */
+ o = &new_opcodes[ITBL_NUM_OPCODES]; /* append macro to opcodes list */
+ for (n = e_p0; n < e_nprocs; n++)
+ {
+ es = get_entries (n, e_insn);
+ for (e = *es; e; e = e->next)
{
- es = get_entries(n,e_insn);
- for (e=*es; e; e=e->next)
- {
- /* name, args, mask, match, pinfo
- * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
+ /* name, args, mask, match, pinfo
+ * {"li", "t,i", 0x34000000, 0xffe00000, WR_t },
* {"li", "t,I", 0, (int) M_LI, INSN_MACRO },
* Construct args from itbl_fields.
*/
- o->name = e->name;
- o->args = strdup(form_args(e));
- o->mask = apply_range(e->value,e->range);
- /* FIXME how to catch durring assembly? */
- /* mask to identify this insn */
- o->match = apply_range(e->value,e->range);
- o->pinfo = 0;
+ o->name = e->name;
+ o->args = strdup (form_args (e));
+ o->mask = apply_range (e->value, e->range);
+ /* FIXME how to catch durring assembly? */
+ /* mask to identify this insn */
+ o->match = apply_range (e->value, e->range);
+ o->pinfo = 0;
#ifdef USE_MACROS
- o->mask = id++; /* FIXME how to catch durring assembly? */
- o->match = 0; /* for macros, the insn_isa number */
- o->pinfo = INSN_MACRO;
+ o->mask = id++; /* FIXME how to catch durring assembly? */
+ o->match = 0; /* for macros, the insn_isa number */
+ o->pinfo = INSN_MACRO;
#endif
- /* Don't add instructions which caused an error */
- if (o->args)
- o++;
- else
- new_num_opcodes--;
- }
+ /* Don't add instructions which caused an error */
+ if (o->args)
+ o++;
+ else
+ new_num_opcodes--;
}
- ITBL_OPCODES = new_opcodes;
- ITBL_NUM_OPCODES = new_num_opcodes;
+ }
+ ITBL_OPCODES = new_opcodes;
+ ITBL_NUM_OPCODES = new_num_opcodes;
- /* FIXME
- At this point, we can free the entries, as they should have
+ /* FIXME
+ At this point, we can free the entries, as they should have
been added to the assembler's tables.
Don't free name though, since name is being used by the new
opcodes table.
- Eventually, we should also free the new opcodes table itself on exit.
+ Eventually, we should also free the new opcodes table itself
+ on exit.
*/
}
-static char *form_args(struct itbl_entry *e)
+static char *
+form_args (struct itbl_entry *e)
{
- static char s[31];
- char c=0, *p=s;
- struct itbl_field *f;
+ static char s[31];
+ char c = 0, *p = s;
+ struct itbl_field *f;
- ASSERT(e);
- for (f=e->fields; f; f=f->next)
+ ASSERT (e);
+ for (f = e->fields; f; f = f->next)
+ {
+ switch (f->type)
+ {
+ case e_dreg:
+ c = 'd';
+ break;
+ case e_creg:
+ c = 't';
+ break;
+ case e_greg:
+ c = 's';
+ break;
+ case e_immed:
+ c = 'i';
+ break;
+ case e_addr:
+ c = 'a';
+ break;
+ default:
+ c = 0; /* ignore; unknown field type */
+ }
+ if (c)
{
- switch (f->type)
- {
- case e_dreg: c='d'; break;
- case e_creg: c='t'; break;
- case e_greg: c='s'; break;
- case e_immed: c='i'; break;
- case e_addr: c='a'; break;
- default: c=0; /* ignore; unknown field type */
- }
- if (c)
- {
- if (p!=s)
- *p++=',';
- *p++=c;
- }
+ if (p != s)
+ *p++ = ',';
+ *p++ = c;
}
- *p=0;
- return s;
+ }
+ *p = 0;
+ return s;
}
#endif /* !STAND_ALONE */
/* Get processor's register name from val */
-unsigned long itbl_get_reg_val(char *name)
+unsigned long
+itbl_get_reg_val (char *name)
{
- e_type t;
- e_processor p;
- int r=0;
- for (p=e_p0; p<e_nprocs; p++)
- for (t=e_regtype0; t<e_nregtypes; t++)
- {
- if (r = itbl_get_val(p, t, name), r)
- return r;
- }
- return 0;
+ e_type t;
+ e_processor p;
+ int r = 0;
+ for (p = e_p0; p < e_nprocs; p++)
+ for (t = e_regtype0; t < e_nregtypes; t++)
+ {
+ if (r = itbl_get_val (p, t, name), r)
+ return r;
+ }
+ return 0;
}
-char *itbl_get_name(e_processor processor, e_type type, unsigned long val)
+char *
+itbl_get_name (e_processor processor, e_type type, unsigned long val)
{
- struct itbl_entry *r;
- /* type depends on instruction passed */
- r = find_entry_byval(processor,type,val,0);
- if (r)
- return r->name;
- else
- return 0; /* error; invalid operand */
+ struct itbl_entry *r;
+ /* type depends on instruction passed */
+ r = find_entry_byval (processor, type, val, 0);
+ if (r)
+ return r->name;
+ else
+ return 0; /* error; invalid operand */
}
/* Get processor's register value from name */
-unsigned long itbl_get_val(e_processor processor, e_type type, char *name)
+unsigned long
+itbl_get_val (e_processor processor, e_type type, char *name)
{
- struct itbl_entry *r;
- /* type depends on instruction passed */
- r = find_entry_byname(processor,type,name);
- if (r)
- return r->value;
- else
- return 0; /* error; invalid operand */
+ struct itbl_entry *r;
+ /* type depends on instruction passed */
+ r = find_entry_byname (processor, type, name);
+ if (r)
+ return r->value;
+ else
+ return 0; /* error; invalid operand */
}
* s - operands
* returns - long word for assembled instruction */
-unsigned long itbl_assemble(char *name, char *s)
+unsigned long
+itbl_assemble (char *name, char *s)
{
- unsigned long opcode;
- struct itbl_entry *e;
- struct itbl_field *f;
- char *n;
- int processor;
+ unsigned long opcode;
+ struct itbl_entry *e;
+ struct itbl_field *f;
+ char *n;
+ int processor;
- if (!name || !*name)
- return 0; /* error! must have a opcode name/expr */
+ if (!name || !*name)
+ return 0; /* error! must have a opcode name/expr */
- /* find entry in list of instructions for all processors */
- for (processor=0; processor<e_nprocs; processor++)
- {
- e = find_entry_byname(processor, e_insn, name);
- if (e) break;
- }
- if (!e)
- return 0; /* opcode not in table; invalid instrustion */
- opcode = build_opcode(e);
+ /* find entry in list of instructions for all processors */
+ for (processor = 0; processor < e_nprocs; processor++)
+ {
+ e = find_entry_byname (processor, e_insn, name);
+ if (e)
+ break;
+ }
+ if (!e)
+ return 0; /* opcode not in table; invalid instrustion */
+ opcode = build_opcode (e);
- /* parse opcode's args (if any) */
- for (f=e->fields; f; f=f->next) /* for each arg, ... */
+ /* parse opcode's args (if any) */
+ for (f = e->fields; f; f = f->next) /* for each arg, ... */
+ {
+ struct itbl_entry *r;
+ unsigned long value;
+ if (!s || !*s)
+ return 0; /* error - not enough operands */
+ n = itbl_get_field (&s);
+ /* n should be in form $n or 0xhhh (are symbol names valid?? */
+ switch (f->type)
{
- struct itbl_entry *r;
- unsigned long value;
- if (!s || !*s)
- return 0; /* error - not enough operands */
- n = itbl_get_field(&s);
- /* n should be in form $n or 0xhhh (are symbol names valid?? */
- switch (f->type)
- {
- case e_dreg:
- case e_creg:
- case e_greg:
- /* Accept either a string name
+ case e_dreg:
+ case e_creg:
+ case e_greg:
+ /* Accept either a string name
* or '$' followed by the register number */
- if (*n == '$')
- {
- n++;
- value = strtol(n,0,10);
- /* FIXME! could have "0l"... then what?? */
- if (value == 0 && *n!='0')
- return 0; /* error; invalid operand */
- }
- else
- {
- r = find_entry_byname(e->processor,f->type,n);
- if (r)
- value = r->value;
- else
- return 0; /* error; invalid operand */
- }
- break;
- case e_addr:
- /* use assembler's symbol table to find symbol */
- /* FIXME!! Do we need this?
+ if (*n == '$')
+ {
+ n++;
+ value = strtol (n, 0, 10);
+ /* FIXME! could have "0l"... then what?? */
+ if (value == 0 && *n != '0')
+ return 0; /* error; invalid operand */
+ }
+ else
+ {
+ r = find_entry_byname (e->processor, f->type, n);
+ if (r)
+ value = r->value;
+ else
+ return 0; /* error; invalid operand */
+ }
+ break;
+ case e_addr:
+ /* use assembler's symbol table to find symbol */
+ /* FIXME!! Do we need this?
if so, what about relocs??
my_getExpression (&imm_expr, s);
return 0; /-* error; invalid operand *-/
break;
*/
- /* If not a symbol, fall thru to IMMED */
- case e_immed:
- if (*n=='0' && *(n+1)=='x') /* hex begins 0x... */
- {
- n+=2;
- value = strtol(n,0,16);
- /* FIXME! could have "0xl"... then what?? */
- }
- else
- {
- value = strtol(n,0,10);
- /* FIXME! could have "0l"... then what?? */
- if (value == 0 && *n!='0')
- return 0; /* error; invalid operand */
- }
- break;
- default:
- return 0; /* error; invalid field spec */
- }
- opcode |= apply_range(value,f->range);
+ /* If not a symbol, fall thru to IMMED */
+ case e_immed:
+ if (*n == '0' && *(n + 1) == 'x') /* hex begins 0x... */
+ {
+ n += 2;
+ value = strtol (n, 0, 16);
+ /* FIXME! could have "0xl"... then what?? */
+ }
+ else
+ {
+ value = strtol (n, 0, 10);
+ /* FIXME! could have "0l"... then what?? */
+ if (value == 0 && *n != '0')
+ return 0; /* error; invalid operand */
+ }
+ break;
+ default:
+ return 0; /* error; invalid field spec */
}
- if (s && *s)
- return 0; /* error - too many operands */
- return opcode; /* done! */
+ opcode |= apply_range (value, f->range);
+ }
+ if (s && *s)
+ return 0; /* error - too many operands */
+ return opcode; /* done! */
}
/* Disassemble instruction "insn".
* returns - 1 if succeeded; 0 if failed
*/
-int itbl_disassemble(char *s, unsigned long insn)
+int
+itbl_disassemble (char *s, unsigned long insn)
{
- e_processor processor;
- struct itbl_entry *e;
- struct itbl_field *f;
-
- if (!ITBL_IS_INSN(insn))
- return 0; /* error*/
- processor = get_processor(ITBL_DECODE_PNUM(insn));
-
- /* find entry in list */
- e = find_entry_byval(processor, e_insn, insn, 0);
- if (!e)
- return 0; /* opcode not in table; invalid instrustion */
- strcpy(s, e->name);
-
- /* parse insn's args (if any) */
- for (f=e->fields; f; f=f->next) /* for each arg, ... */
+ e_processor processor;
+ struct itbl_entry *e;
+ struct itbl_field *f;
+
+ if (!ITBL_IS_INSN (insn))
+ return 0; /* error*/
+ processor = get_processor (ITBL_DECODE_PNUM (insn));
+
+ /* find entry in list */
+ e = find_entry_byval (processor, e_insn, insn, 0);
+ if (!e)
+ return 0; /* opcode not in table; invalid instrustion */
+ strcpy (s, e->name);
+
+ /* parse insn's args (if any) */
+ for (f = e->fields; f; f = f->next) /* for each arg, ... */
+ {
+ struct itbl_entry *r;
+ unsigned long value;
+
+ if (f == e->fields) /* first operand is preceeded by tab */
+ strcat (s, "\t");
+ else /* ','s separate following operands */
+ strcat (s, ",");
+ value = extract_range (insn, f->range);
+ /* n should be in form $n or 0xhhh (are symbol names valid?? */
+ switch (f->type)
{
- struct itbl_entry *r;
- unsigned long value;
-
- if (f==e->fields) /* first operand is preceeded by tab */
- strcat(s,"\t");
- else /* ','s separate following operands */
- strcat(s,",");
- value = extract_range(insn, f->range);
- /* n should be in form $n or 0xhhh (are symbol names valid?? */
- switch (f->type)
- {
- case e_dreg:
- case e_creg:
- case e_greg:
- /* Accept either a string name
+ case e_dreg:
+ case e_creg:
+ case e_greg:
+ /* Accept either a string name
* or '$' followed by the register number */
- r = find_entry_byval(e->processor,f->type,value,&f->range);
- if (r)
- strcat(s,r->name);
- else
- sprintf(s,"%s$%d",s,value);
- break;
- case e_addr:
- /* use assembler's symbol table to find symbol */
- /* FIXME!! Do we need this?
+ r = find_entry_byval (e->processor, f->type, value, &f->range);
+ if (r)
+ strcat (s, r->name);
+ else
+ sprintf (s, "%s$%d", s, value);
+ break;
+ case e_addr:
+ /* use assembler's symbol table to find symbol */
+ /* FIXME!! Do we need this?
* if so, what about relocs??
*/
- /* If not a symbol, fall thru to IMMED */
- case e_immed:
- sprintf(s,"%s0x%x",s,value);
- break;
- default:
- return 0; /* error; invalid field spec */
- }
+ /* If not a symbol, fall thru to IMMED */
+ case e_immed:
+ sprintf (s, "%s0x%x", s, value);
+ break;
+ default:
+ return 0; /* error; invalid field spec */
}
- return 1; /* done! */
+ }
+ return 1; /* done! */
}
/*======================================================================*/
/* Calculate instruction's opcode and function values from entry */
-static unsigned long build_opcode(struct itbl_entry *e)
+static unsigned long
+build_opcode (struct itbl_entry *e)
{
- unsigned long opcode;
+ unsigned long opcode;
- opcode = apply_range(e->value,e->range);
- opcode |= ITBL_ENCODE_PNUM(e->processor);
- return opcode;
+ opcode = apply_range (e->value, e->range);
+ opcode |= ITBL_ENCODE_PNUM (e->processor);
+ return opcode;
}
-/* Calculate absolute value given the relative value and bit position range
- * within the instruction.
+/* Calculate absolute value given the relative value and bit position range
+ * within the instruction.
* The range is inclusive where 0 is least significant bit.
* A range of { 24, 20 } will have a mask of
* bit 3 2 1
* mask: 0x01f00000.
*/
-static unsigned long apply_range(unsigned long rval, struct itbl_range r)
+static unsigned long
+apply_range (unsigned long rval, struct itbl_range r)
{
- unsigned long mask;
- unsigned long aval;
- int len = MAX_BITPOS - r.sbit;
-
- ASSERT(r.sbit >= r.ebit);
- ASSERT(MAX_BITPOS >= r.sbit);
- ASSERT(r.ebit >= 0);
-
- /* create mask by truncating 1s by shifting */
- mask = 0xffffffff << len;
- mask = mask >> len;
- mask = mask >> r.ebit;
- mask = mask << r.ebit;
-
- aval = (rval << r.ebit) & mask;
- return aval;
+ unsigned long mask;
+ unsigned long aval;
+ int len = MAX_BITPOS - r.sbit;
+
+ ASSERT (r.sbit >= r.ebit);
+ ASSERT (MAX_BITPOS >= r.sbit);
+ ASSERT (r.ebit >= 0);
+
+ /* create mask by truncating 1s by shifting */
+ mask = 0xffffffff << len;
+ mask = mask >> len;
+ mask = mask >> r.ebit;
+ mask = mask << r.ebit;
+
+ aval = (rval << r.ebit) & mask;
+ return aval;
}
-/* Calculate relative value given the absolute value and bit position range
+/* Calculate relative value given the absolute value and bit position range
* within the instruction. */
-static unsigned long extract_range(unsigned long aval, struct itbl_range r)
+static unsigned long
+extract_range (unsigned long aval, struct itbl_range r)
{
- unsigned long mask;
- unsigned long rval;
- int len = MAX_BITPOS - r.sbit;
-
- /* create mask by truncating 1s by shifting */
- mask = 0xffffffff << len;
- mask = mask >> len;
- mask = mask >> r.ebit;
- mask = mask << r.ebit;
-
- rval = (aval & mask) >> r.ebit;
- return rval;
+ unsigned long mask;
+ unsigned long rval;
+ int len = MAX_BITPOS - r.sbit;
+
+ /* create mask by truncating 1s by shifting */
+ mask = 0xffffffff << len;
+ mask = mask >> len;
+ mask = mask >> r.ebit;
+ mask = mask << r.ebit;
+
+ rval = (aval & mask) >> r.ebit;
+ return rval;
}
-/* Extract processor's assembly instruction field name from s;
+/* Extract processor's assembly instruction field name from s;
* forms are "n args" "n,args" or "n" */
-/* Return next argument from string pointer "s" and advance s.
+/* Return next argument from string pointer "s" and advance s.
* delimiters are " ,\0" */
-char *itbl_get_field(char **S)
+char *
+itbl_get_field (char **S)
{
- static char n[128];
- char *p, *ps, *s;
- int len;
-
- s = *S;
- if (!s || !*s)
- return 0;
- p = s+strlen(s);
- if (ps=strchr(s,','),ps) p = ps;
- if (ps=strchr(s,' '),ps) p = min(p,ps);
- if (ps=strchr(s,'\0'),ps) p = min(p,ps);
- if (p==0)
- return 0; /* error! */
- len = p-s;
- ASSERT(128>len+1);
- strncpy(n,s,len);
- n[len]=0;
- if (s[len]=='\0') s=0; /* no more args */
- else s+=len+1; /* advance to next arg */
-
- *S = s;
- return n;
+ static char n[128];
+ char *p, *ps, *s;
+ int len;
+
+ s = *S;
+ if (!s || !*s)
+ return 0;
+ p = s + strlen (s);
+ if (ps = strchr (s, ','), ps)
+ p = ps;
+ if (ps = strchr (s, ' '), ps)
+ p = min (p, ps);
+ if (ps = strchr (s, '\0'), ps)
+ p = min (p, ps);
+ if (p == 0)
+ return 0; /* error! */
+ len = p - s;
+ ASSERT (128 > len + 1);
+ strncpy (n, s, len);
+ n[len] = 0;
+ if (s[len] == '\0')
+ s = 0; /* no more args */
+ else
+ s += len + 1; /* advance to next arg */
+
+ *S = s;
+ return n;
}
/* Search entries for a given processor and type
* to find one matching the name "n".
* Return a pointer to the entry */
-static struct itbl_entry *find_entry_byname(e_processor processor,
- e_type type, char *n)
+static struct itbl_entry *
+find_entry_byname (e_processor processor,
+ e_type type, char *n)
{
- struct itbl_entry *e, **es;
+ struct itbl_entry *e, **es;
- es = get_entries(processor, type);
- for (e=*es; e; e=e->next) /* for each entry, ... */
- {
- if (!strcmp(e->name,n))
- return e;
- }
- return 0;
+ es = get_entries (processor, type);
+ for (e = *es; e; e = e->next) /* for each entry, ... */
+ {
+ if (!strcmp (e->name, n))
+ return e;
+ }
+ return 0;
}
/* Search entries for a given processor and type
* This function is used for disassembling fields of an instruction.
*/
-static struct itbl_entry *find_entry_byval(e_processor processor, e_type type,
- unsigned long val, struct itbl_range *r)
+static struct itbl_entry *
+find_entry_byval (e_processor processor, e_type type,
+ unsigned long val, struct itbl_range *r)
{
- struct itbl_entry *e, **es;
- unsigned long eval;
+ struct itbl_entry *e, **es;
+ unsigned long eval;
- es = get_entries(processor, type);
- for (e=*es; e; e=e->next) /* for each entry, ... */
- {
- if (processor != e->processor)
- continue;
- /* For insns, we might not know the range of the opcode,
- * so a range of 0 will allow this routine to match against
+ es = get_entries (processor, type);
+ for (e = *es; e; e = e->next) /* for each entry, ... */
+ {
+ if (processor != e->processor)
+ continue;
+ /* For insns, we might not know the range of the opcode,
+ * so a range of 0 will allow this routine to match against
* the range of the entry to be compared with.
* This could cause ambiguities.
* For operands, we get an extracted value and a range.
*/
- /* if range is 0, mask val against the range of the compared entry. */
- if (r==0) /* if no range passed, must be whole 32-bits
+ /* if range is 0, mask val against the range of the compared entry. */
+ if (r == 0) /* if no range passed, must be whole 32-bits
* so create 32-bit value from entry's range */
{
- eval = apply_range(e->value,e->range);
- val &= apply_range(0xffffffff,e->range);
+ eval = apply_range (e->value, e->range);
+ val &= apply_range (0xffffffff, e->range);
}
- else if (r->sbit == e->range.sbit && r->ebit == e->range.ebit
- || e->range.sbit == 0 && e->range.ebit == 0)
+ else if (r->sbit == e->range.sbit && r->ebit == e->range.ebit
+ || e->range.sbit == 0 && e->range.ebit == 0)
{
- eval = apply_range(e->value,*r);
- val = apply_range(val, *r);
- }
- else
- continue;
- if (val==eval)
- return e;
+ eval = apply_range (e->value, *r);
+ val = apply_range (val, *r);
}
- return 0;
+ else
+ continue;
+ if (val == eval)
+ return e;
+ }
+ return 0;
}
/* Return a pointer to the list of entries for a given processor and type. */
-static struct itbl_entry **get_entries(e_processor processor, e_type type)
+static struct itbl_entry **
+get_entries (e_processor processor, e_type type)
{
- return &entries[processor][type];
+ return &entries[processor][type];
}
/* Return an integral value for the processor passed from yyparse. */
-static e_processor get_processor(int yyproc)
+static e_processor
+get_processor (int yyproc)
{
- /* translate from yacc's processor to enum */
- if (yyproc >= e_p0 && yyproc < e_nprocs)
- return (e_processor) yyproc;
- return e_invproc; /* error; invalid processor */
+ /* translate from yacc's processor to enum */
+ if (yyproc >= e_p0 && yyproc < e_nprocs)
+ return (e_processor) yyproc;
+ return e_invproc; /* error; invalid processor */
}
/* Return an integral value for the entry type passed from yyparse. */
-static e_type get_type(int yytype)
+static e_type
+get_type (int yytype)
{
- switch(yytype)
+ switch (yytype)
{
- /* translate from yacc's type to enum */
- case INSN: return e_insn;
- case DREG: return e_dreg;
- case CREG: return e_creg;
- case GREG: return e_greg;
- case ADDR: return e_addr;
- case IMMED: return e_immed;
- default:
- return e_invtype; /* error; invalid type */
+ /* translate from yacc's type to enum */
+ case INSN:
+ return e_insn;
+ case DREG:
+ return e_dreg;
+ case CREG:
+ return e_creg;
+ case GREG:
+ return e_greg;
+ case ADDR:
+ return e_addr;
+ case IMMED:
+ return e_immed;
+ default:
+ return e_invtype; /* error; invalid type */
}
}
/* Allocate and initialize an entry */
-static struct itbl_entry *alloc_entry(e_processor processor, e_type type,
- char *name, unsigned long value)
+static struct itbl_entry *
+alloc_entry (e_processor processor, e_type type,
+ char *name, unsigned long value)
{
- struct itbl_entry *e, **es;
- if (!name) return 0;
- e = (struct itbl_entry*) malloc(sizeof(struct itbl_entry));
- if (e)
- {
- memset(e,0,sizeof(struct itbl_entry));
- e->name = (char *) malloc(sizeof(strlen(name))+1);
- if (e->name) strcpy(e->name,name);
- e->processor = processor;
- e->type = type;
- e->value = value;
- es = get_entries(e->processor,e->type);
- e->next = *es;
- *es = e;
- }
- return e;
+ struct itbl_entry *e, **es;
+ if (!name)
+ return 0;
+ e = (struct itbl_entry *) malloc (sizeof (struct itbl_entry));
+ if (e)
+ {
+ memset (e, 0, sizeof (struct itbl_entry));
+ e->name = (char *) malloc (sizeof (strlen (name)) + 1);
+ if (e->name)
+ strcpy (e->name, name);
+ e->processor = processor;
+ e->type = type;
+ e->value = value;
+ es = get_entries (e->processor, e->type);
+ e->next = *es;
+ *es = e;
+ }
+ return e;
}
/* Allocate and initialize an entry's field */
-static struct itbl_field *alloc_field(e_type type, int sbit, int ebit,
- unsigned long flags)
+static struct itbl_field *
+alloc_field (e_type type, int sbit, int ebit,
+ unsigned long flags)
{
- struct itbl_field *f;
- f = (struct itbl_field*) malloc(sizeof(struct itbl_field));
- if (f)
- {
- memset(f,0,sizeof(struct itbl_field));
- f->type = type;
- f->range.sbit = sbit;
- f->range.ebit = ebit;
- f->flags = flags;
- }
- return f;
+ struct itbl_field *f;
+ f = (struct itbl_field *) malloc (sizeof (struct itbl_field));
+ if (f)
+ {
+ memset (f, 0, sizeof (struct itbl_field));
+ f->type = type;
+ f->range.sbit = sbit;
+ f->range.ebit = ebit;
+ f->flags = flags;
+ }
+ return f;
}
-
+/* itbl-ops.h
+
+ Copyright (C) 1997 Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
/* External functions, constants and defines for itbl support */
+#include "ansidecl.h"
#include "itbl-cpu.h"
-/* Defaults for definitions required by generic code */
+/* Defaults for definitions required by generic code */
#ifndef ITBL_NUMBER_OF_PROCESSORS
#define ITBL_NUMBER_OF_PROCESSORS 1
#endif
-#ifndef ITBL_MAX_BITPOS
+#ifndef ITBL_MAX_BITPOS
#define ITBL_MAX_BITPOS 31
#endif
-#ifndef ITBL_TYPE
+#ifndef ITBL_TYPE
#define ITBL_TYPE unsigned long
#endif
typedef ITBL_TYPE t_insn;
/* types of entries */
-typedef enum
-{
+typedef enum
+ {
e_insn,
e_dreg,
- e_regtype0 = e_dreg,
+ e_regtype0 = e_dreg,
e_creg,
e_greg,
e_addr,
- e_nregtypes = e_greg+1,
+ e_nregtypes = e_greg + 1,
e_immed,
e_ntypes,
- e_invtype /* invalid type */
-} e_type;
+ e_invtype /* invalid type */
+ } e_type;
-typedef enum
-{
+typedef enum
+ {
e_p0,
- e_nprocs=NUMBER_OF_PROCESSORS,
- e_invproc /* invalid processor */
-} e_processor;
+ e_nprocs = NUMBER_OF_PROCESSORS,
+ e_invproc /* invalid processor */
+ } e_processor;
-/* These routines are visible to the main part of the assembler */
+/* 0 means an instruction table was not specified. */
+extern int itbl_have_entries;
-int itbl_parse(char* insntbl);
-void itbl_init(void);
-char *itbl_get_field(char **s);
-unsigned long itbl_assemble(char *name, char *operands);
-int itbl_disassemble(char *str, unsigned long insn);
-int itbl_parse(char *tbl); /* parses insn tbl */
-unsigned long itbl_get_reg_val(char *name);
-unsigned long itbl_get_val(e_processor processor, e_type type, char *name);
-char *itbl_get_name(e_processor processor, e_type type, unsigned long val);
-
-/* These routines are called by the table parser used to build the
- * dynamic list of new processor instructions and registers. */
-
-struct itbl_entry *itbl_add_reg(int yyproc, int yytype, char *regname, int regnum);
-struct itbl_entry *itbl_add_insn(int yyproc, char *name, unsigned long value,
- int sbit, int ebit, unsigned long flags);
-struct itbl_field *itbl_add_operand(struct itbl_entry *e, int yytype,
- int sbit, int ebit, unsigned long flags);
+/* These routines are visible to the main part of the assembler */
+int itbl_parse PARAMS ((char *insntbl));
+void itbl_init PARAMS ((void));
+char *itbl_get_field PARAMS ((char **s));
+unsigned long itbl_assemble PARAMS ((char *name, char *operands));
+int itbl_disassemble PARAMS ((char *str, unsigned long insn));
+int itbl_parse PARAMS ((char *tbl)); /* parses insn tbl */
+unsigned long itbl_get_reg_val PARAMS ((char *name));
+unsigned long itbl_get_val PARAMS ((e_processor processor, e_type type,
+ char *name));
+char *itbl_get_name PARAMS ((e_processor processor, e_type type,
+ unsigned long val));
+
+/* These routines are called by the table parser used to build the
+ dynamic list of new processor instructions and registers. */
+
+struct itbl_entry *itbl_add_reg PARAMS ((int yyproc, int yytype,
+ char *regname, int regnum));
+struct itbl_entry *itbl_add_insn PARAMS ((int yyproc, char *name,
+ unsigned long value, int sbit, int ebit, unsigned long flags));
+struct itbl_field *itbl_add_operand PARAMS ((struct itbl_entry * e, int yytype,
+ int sbit, int ebit, unsigned long flags));
+
+/* itbl-parse.y
+
+ Copyright (C) 1997 Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+
%{
+
/*
Yacc grammar for instruction table entries.
=======================================================================
Original Instruction table specification document:
- MIPS Coprocessor Table Specification
- ====================================
+ MIPS Coprocessor Table Specification
+ ====================================
This document describes the format of the MIPS coprocessor table. The
table specifies a list of valid functions, data registers and control
Examples:
- gas -t cop.tbl test.s -o test.o
- gas -t /usr/local/lib/cop.tbl test.s -o test.o
- gas --itbl d:\gnu\data\cop.tbl test.s -o test.o
+ gas -t cop.tbl test.s -o test.o
+ gas -t /usr/local/lib/cop.tbl test.s -o test.o
+ gas --itbl d:\gnu\data\cop.tbl test.s -o test.o
Only one table may be supplied during a single invocation of
the assembler.
any given coprocessor "z". These instructions are already recognized
by the assembler, and are listed here only for reference.
-Class format instructions
+Class format instructions
-------------------------------------------------
-Class1: op base rt offset
- LWCz rt,offset(base)
- SWCz rt,offset(base)
-Class2: COPz sub rt rd 0
- MTCz rt,rd
- MFCz rt,rd
- CTCz rt,rd
- CFCz rt,rd
-Class3: COPz CO cofun
- COPz cofun
-Class4: COPz BC br offset
- BCzT offset
- BCzF offset
-Class5: COPz sub rt rd 0
- DMFCz rt,rd
- DMTCz rt,rd
-Class6: op base rt offset
- LDCz rt,offset(base)
- SDCz rt,offset(base)
-Class7: COPz BC br offset
- BCzTL offset
- BCzFL offset
+Class1:
+ op base rt offset
+ LWCz rt,offset (base)
+ SWCz rt,offset (base)
+Class2:
+ COPz sub rt rd 0
+ MTCz rt,rd
+ MFCz rt,rd
+ CTCz rt,rd
+ CFCz rt,rd
+Class3:
+ COPz CO cofun
+ COPz cofun
+Class4:
+ COPz BC br offset
+ BCzT offset
+ BCzF offset
+Class5:
+ COPz sub rt rd 0
+ DMFCz rt,rd
+ DMTCz rt,rd
+Class6:
+ op base rt offset
+ LDCz rt,offset (base)
+ SDCz rt,offset (base)
+Class7:
+ COPz BC br offset
+ BCzTL offset
+ BCzFL offset
The coprocessor table defines coprocessor-specific registers that can
be used with all of the above classes of instructions, where
Here is the grammar for the coprocessor table:
- table -> entry*
+ table -> entry*
- entry -> [z entrydef] [comment] '\n'
+ entry -> [z entrydef] [comment] '\n'
- entrydef -> type name val
- entrydef -> 'insn' name val funcdef ; type of entry (instruction)
+ entrydef -> type name val
+ entrydef -> 'insn' name val funcdef ; type of entry (instruction)
- z -> 'p'['0'..'3'] ; processor number
- type -> ['dreg' | 'creg' | 'greg' ] ; type of entry (register)
+ z -> 'p'['0'..'3'] ; processor number
+ type -> ['dreg' | 'creg' | 'greg' ] ; type of entry (register)
; 'dreg', 'creg' or 'greg' specifies a data, control, or general
- ; register mnemonic, respectively
- name -> [ltr|dec]* ; mnemonic of register/function
- val -> [dec|hex] ; register/function number (integer constant)
-
- funcdef -> frange flags fields
- ; bitfield range for opcode
- ; list of fields' formats
- fields -> field*
- field -> [','] ftype frange flags
- flags -> ['*' flagexpr]
- flagexpr -> '[' flagexpr ']'
- flagexpr -> val '|' flagexpr
- ftype -> [ type | 'immed' | 'addr' ]
+ ; register mnemonic, respectively
+ name -> [ltr|dec]* ; mnemonic of register/function
+ val -> [dec|hex] ; register/function number (integer constant)
+
+ funcdef -> frange flags fields
+ ; bitfield range for opcode
+ ; list of fields' formats
+ fields -> field*
+ field -> [','] ftype frange flags
+ flags -> ['*' flagexpr]
+ flagexpr -> '[' flagexpr ']'
+ flagexpr -> val '|' flagexpr
+ ftype -> [ type | 'immed' | 'addr' ]
; 'immed' specifies an immediate value; see grammar for "val" above
- ; 'addr' specifies a C identifier; name of symbol to be resolved at
- ; link time
- frange -> ':' val '-' val ; starting to ending bit positions, where
- ; where 0 is least significant bit
- frange -> (null) ; default range of 31-0 will be assumed
+ ; 'addr' specifies a C identifier; name of symbol to be resolved at
+ ; link time
+ frange -> ':' val '-' val ; starting to ending bit positions, where
+ ; where 0 is least significant bit
+ frange -> (null) ; default range of 31-0 will be assumed
- comment -> [';'|'#'] [char]*
- char -> any printable character
- ltr -> ['a'..'z'|'A'..'Z']
- dec -> ['0'..'9']* ; value in decimal
- hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']* ; value in hexidecimal
+ comment -> [';'|'#'] [char]*
+ char -> any printable character
+ ltr -> ['a'..'z'|'A'..'Z']
+ dec -> ['0'..'9']* ; value in decimal
+ hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']* ; value in hexidecimal
Examples
The table:
- p1 dreg d1 1 ; data register "d1" for COP1 has value 1
- p1 creg c3 3 ; ctrl register "c3" for COP1 has value 3
- p3 func fill 0x1f:24-20 ; function "fill" for COP3 has value 31 and
- ; no fields
+ p1 dreg d1 1 ; data register "d1" for COP1 has value 1
+ p1 creg c3 3 ; ctrl register "c3" for COP1 has value 3
+ p3 func fill 0x1f:24-20 ; function "fill" for COP3 has value 31 and
+ ; no fields
will allow the assembler to accept the following coprocessor instructions:
- LWC1 d1,0x100($2)
- fill
+ LWC1 d1,0x100 ($2)
+ fill
Here, the general purpose register "$2", and instruction "LWC1", are standard
mnemonics built-in to the MIPS assembler.
The table:
- p3 dreg d3 3 ; data register "d3" for COP3 has value 3
- p3 creg c2 22 ; control register "c2" for COP3 has value 22
- p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
- ; function "fee" for COP3 has value 31, and 3 fields
- ; consisting of a data register, a control register,
- ; and an immediate value.
+ p3 dreg d3 3 ; data register "d3" for COP3 has value 3
+ p3 creg c2 22 ; control register "c2" for COP3 has value 22
+ p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
+ ; function "fee" for COP3 has value 31, and 3 fields
+ ; consisting of a data register, a control register,
+ ; and an immediate value.
will allow the assembler to accept the following coprocessor instruction:
- fee d3,c2,0x1
+ fee d3,c2,0x1
and will emit the object code:
- 31-26 25 24-20 19-18 17-13 12-8 7-0
- COPz CO fun dreg creg immed
- 010011 1 11111 00 00011 10110 00000001
+ 31-26 25 24-20 19-18 17-13 12-8 7-0
+ COPz CO fun dreg creg immed
+ 010011 1 11111 00 00011 10110 00000001
- 0x4ff07601
+ 0x4ff07601
Example 3:
The table:
- p3 dreg d3 3 ; data register "d3" for COP3 has value 3
- p3 creg c2 22 ; control register "c2" for COP3 has value 22
- p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
+ p3 dreg d3 3 ; data register "d3" for COP3 has value 3
+ p3 creg c2 22 ; control register "c2" for COP3 has value 22
+ p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
will allow the assembler to accept the following coprocessor
instruction:
- fuu d3,c2
+ fuu d3,c2
and will emit the object code:
- 31-26 25 24-20 19-18 17-13 12-8 7-0
- COPz CO fun dreg creg
- 010011 1 11111 00 00011 10110 00000001
+ 31-26 25 24-20 19-18 17-13 12-8 7-0
+ COPz CO fun dreg creg
+ 010011 1 11111 00 00011 10110 00000001
- 0x4ff07601
+ 0x4ff07601
In this way, the programmer can force arbitrary bits of an instruction
to have predefined values.
May decide to modify the syntax to allow commas separate multiple
ranges within an instruction (range','range).
-Changes in grammar: The number of parms argument to the function entry
+Changes in grammar:
+ The number of parms argument to the function entry
was deleted from the original format such that we now count the fields.
----
static int sbit, ebit;
static struct itbl_entry *insn=0;
extern int insntbl_line;
-int yyparse(void);
-int yylex(void);
+int yyparse (void);
+int yylex (void);
%}
-%union {
+%union
+ {
char *str;
int num;
int processor;
unsigned long val;
- }
+ }
-%token DREG CREG GREG IMMED ADDR INSN NUM ID NL PNUM
-%type <val> value flags flagexpr
-%type <num> number NUM ftype regtype pnum PNUM
-%type <str> ID name
+%token DREG CREG GREG IMMED ADDR INSN NUM ID NL PNUM
+%type <val> value flags flagexpr
+%type <num> number NUM ftype regtype pnum PNUM
+%type <str> ID name
%start insntbl
%%
-insntbl: entrys
+insntbl:
+ entrys
;
-entrys: entry entrys
+entrys:
+ entry entrys
|
;
-entry: pnum regtype name value NL
- {
- DBG(("line %d: entry pnum=%d type=%d name=%s value=x%x\n",
- insntbl_line, $1, $2, $3, $4));
- itbl_add_reg($1, $2, $3, $4);
- }
+entry:
+ pnum regtype name value NL
+ {
+ DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n",
+ insntbl_line, $1, $2, $3, $4));
+ itbl_add_reg ($1, $2, $3, $4);
+ }
| pnum INSN name value range flags
- {
- DBG(("line %d: entry pnum=%d type=INSN name=%s value=x%x",
- insntbl_line, $1, $3, $4));
- DBG((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, $6));
- insn=itbl_add_insn($1, $3, $4, sbit, ebit, $6);
- }
+ {
+ DBG (("line %d: entry pnum=%d type=INSN name=%s value=x%x",
+ insntbl_line, $1, $3, $4));
+ DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, $6));
+ insn=itbl_add_insn ($1, $3, $4, sbit, ebit, $6);
+ }
fieldspecs NL
| NL
| error NL
;
-fieldspecs: ',' fieldspec fieldspecs
+fieldspecs:
+ ',' fieldspec fieldspecs
| fieldspec fieldspecs
|
;
-ftype: regtype
- {
- DBGL2(("ftype\n"));
- $$ = $1;
- }
+ftype:
+ regtype
+ {
+ DBGL2 (("ftype\n"));
+ $$ = $1;
+ }
| ADDR
- {
- DBGL2(("addr\n"));
- $$ = ADDR;
- }
+ {
+ DBGL2 (("addr\n"));
+ $$ = ADDR;
+ }
| IMMED
- {
- DBGL2(("immed\n"));
- $$ = IMMED;
- }
+ {
+ DBGL2 (("immed\n"));
+ $$ = IMMED;
+ }
;
-fieldspec: ftype range flags
- {
- DBG(("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n",
- insntbl_line, $1, sbit, ebit, $3));
- itbl_add_operand(insn, $1, sbit, ebit, $3);
- }
+fieldspec:
+ ftype range flags
+ {
+ DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n",
+ insntbl_line, $1, sbit, ebit, $3));
+ itbl_add_operand (insn, $1, sbit, ebit, $3);
+ }
;
-flagexpr: NUM '|' flagexpr
- {
- $$ = $1 | $3;
- }
+flagexpr:
+ NUM '|' flagexpr
+ {
+ $$ = $1 | $3;
+ }
| '[' flagexpr ']'
- {
- $$ = $2;
- }
+ {
+ $$ = $2;
+ }
| NUM
- {
- $$ = $1;
- }
+ {
+ $$ = $1;
+ }
;
-flags: '*' flagexpr
- {
- DBGL2(("flags=%d\n", $2));
- $$ = $2;
- }
+flags:
+ '*' flagexpr
+ {
+ DBGL2 (("flags=%d\n", $2));
+ $$ = $2;
+ }
|
- {
- $$ = 0;
- }
+ {
+ $$ = 0;
+ }
;
-range: ':' NUM '-' NUM
- {
- DBGL2(("range %d %d\n", $2, $4));
- sbit = $2;
- ebit = $4;
- }
+range:
+ ':' NUM '-' NUM
+ {
+ DBGL2 (("range %d %d\n", $2, $4));
+ sbit = $2;
+ ebit = $4;
+ }
|
- {
- sbit = 31;
- ebit = 0;
- }
+ {
+ sbit = 31;
+ ebit = 0;
+ }
;
-
-pnum: PNUM
- {
- DBGL2(("pnum=%d\n",$1));
- $$ = $1;
- }
+
+pnum:
+ PNUM
+ {
+ DBGL2 (("pnum=%d\n",$1));
+ $$ = $1;
+ }
;
-regtype: DREG
- {
- DBGL2(("dreg\n"));
- $$ = DREG;
- }
+regtype:
+ DREG
+ {
+ DBGL2 (("dreg\n"));
+ $$ = DREG;
+ }
| CREG
- {
- DBGL2(("creg\n"));
- $$ = CREG;
- }
+ {
+ DBGL2 (("creg\n"));
+ $$ = CREG;
+ }
| GREG
- {
- DBGL2(("greg\n"));
- $$ = GREG;
- }
+ {
+ DBGL2 (("greg\n"));
+ $$ = GREG;
+ }
;
-name: ID
- {
- DBGL2(("name=%s\n",$1));
- $$ = $1;
- }
+name:
+ ID
+ {
+ DBGL2 (("name=%s\n",$1));
+ $$ = $1;
+ }
;
-number: NUM
- {
- DBGL2(("num=%d\n",$1));
- $$ = $1;
- }
+number:
+ NUM
+ {
+ DBGL2 (("num=%d\n",$1));
+ $$ = $1;
+ }
;
-value: NUM
- {
- DBGL2(("val=x%x\n",$1));
- $$ = $1;
- }
+value:
+ NUM
+ {
+ DBGL2 (("val=x%x\n",$1));
+ $$ = $1;
+ }
;
%%
-void yyerror(char *msg)
+void
+yyerror (char *msg)
{
- printf("line %d: %s\n", insntbl_line, msg);
+ printf ("line %d: %s\n", insntbl_line, msg);
}
-
projects / deliverable / binutils-gdb.git / commitdiff
