/* tc-arm.c -- Assemble for the ARM
- Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
Free Software Foundation, Inc.
Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
Modified by David Taylor (dtaylor@armltd.co.uk)
struct reg_map all_reg_maps[] =
{
{rn_table, 15, NULL, N_("ARM register expected")},
- {cp_table, 15, NULL, N_("Bad or missing co-processor number")},
- {cn_table, 15, NULL, N_("Co-processor register expected")},
+ {cp_table, 15, NULL, N_("bad or missing co-processor number")},
+ {cn_table, 15, NULL, N_("co-processor register expected")},
{fn_table, 7, NULL, N_("FPA register expected")},
{mav_mvf_table, 15, NULL, N_("Maverick MVF register expected")},
{mav_mvd_table, 15, NULL, N_("Maverick MVD register expected")},
static void build_reg_hsh PARAMS ((struct reg_map *));
static void insert_reg_alias PARAMS ((char *, int, struct hash_control *));
static int create_register_alias PARAMS ((char *, char *));
-static void output_inst PARAMS ((void));
+static void output_inst PARAMS ((const char *));
static int accum0_required_here PARAMS ((char **));
static int ld_mode_required_here PARAMS ((char **));
static void do_branch25 PARAMS ((char *));
{"bkpt", 0xbe00, 2, ARM_EXT_V5T, do_t_bkpt},
};
-#define BAD_ARGS _("Bad arguments to instruction")
+#define BAD_ARGS _("bad arguments to instruction")
#define BAD_PC _("r15 not allowed here")
-#define BAD_COND _("Instruction is not conditional")
+#define BAD_COND _("instruction is not conditional")
#define ERR_NO_ACCUM _("acc0 expected")
static struct hash_control * arm_ops_hsh = NULL;
{
if (next_literal_pool_place >= MAX_LITERAL_POOL_SIZE)
{
- inst.error = _("Literal Pool Overflow");
+ inst.error = _("literal pool overflow");
return FAIL;
}
s_req (a)
int a ATTRIBUTE_UNUSED;
{
- as_bad (_("Invalid syntax for .req directive."));
+ as_bad (_("invalid syntax for .req directive"));
}
static void
temp = get_absolute_expression ();
if (temp > max_alignment)
- as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
+ as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
else if (temp < 0)
{
- as_bad (_("Alignment negative. 0 assumed."));
+ as_bad (_("alignment negative. 0 assumed."));
temp = 0;
}
if (*input_line_pointer != ',')
{
*end_name = 0;
- as_bad (_("Expected comma after name \"%s\""), name);
+ as_bad (_("expected comma after name \"%s\""), name);
*end_name = delim;
ignore_rest_of_line ();
return;
static void
end_of_line (str)
- char * str;
+ char *str;
{
skip_whitespace (str);
- if (* str != '\0')
- inst.error = _("Garbage following instruction");
+ if (*str != '\0' && !inst.error)
+ inst.error = _("garbage following instruction");
}
static int
/* In the few cases where we might be able to accept something else
this error can be overridden. */
- sprintf (buff, _("Register expected, not '%.100s'"), start);
+ sprintf (buff, _("register expected, not '%.100s'"), start);
inst.error = buff;
return FAIL;
processor = processor * 10 + *(*str)++ - '0';
if (processor > 15)
{
- inst.error = _("Illegal co-processor number");
+ inst.error = _("illegal co-processor number");
return FAIL;
}
}
}
else
{
- inst.error = _("Bad or missing co-processor number");
+ inst.error = _("bad or missing co-processor number");
return FAIL;
}
}
/* In the few cases where we might be able to accept something else
this error can be overridden. */
- inst.error = _("Co-processor register expected");
+ inst.error = _("co-processor register expected");
/* Restore the start point. */
*str = start;
/* In the few cases where we might be able to accept something else
this error can be overridden. */
- inst.error = _("Floating point register expected");
+ inst.error = _("floating point register expected");
/* Restore the start point. */
*str = start;
skip = 8;
else
{
- inst.error = _("{C|S}PSR expected");
+ inst.error = _("CPSR or SPSR expected");
return;
}
if (value == (unsigned) FAIL)
{
- inst.error = _("Invalid constant");
+ inst.error = _("invalid constant");
return;
}
/* Unpredictable result if rd or rn is R15. */
if (rd == REG_PC || rn == REG_PC)
as_tsktsk
- (_("Warning: Instruction unpredictable when using r15"));
+ (_("Warning: instruction unpredictable when using r15"));
if (skip_past_comma (& str) == FAIL
|| cp_reg_required_here (& str, 0) == FAIL)
/* inst.instruction has now been zapped with Rd and the addressing mode. */
if (rd & 1) /* Unpredictable result if Rd is odd. */
{
- inst.error = _("Destination register must be even");
+ inst.error = _("destination register must be even");
return;
}
return 0;
}
+static int in_my_get_expression = 0;
+
static int
my_get_expression (ep, str)
expressionS * ep;
save_in = input_line_pointer;
input_line_pointer = *str;
+ in_my_get_expression = 1;
seg = expression (ep);
+ in_my_get_expression = 0;
+
+ if (ep->X_op == O_illegal)
+ {
+ /* We found a bad expression in md_operand(). */
+ *str = input_line_pointer;
+ input_line_pointer = save_in;
+ return 1;
+ }
#ifdef OBJ_AOUT
if (seg != absolute_section
|| (ep->X_op_symbol
&& walk_no_bignums (ep->X_op_symbol)))))
{
- inst.error = _("Invalid constant");
+ inst.error = _("invalid constant");
*str = input_line_pointer;
input_line_pointer = save_in;
return 1;
return 0;
}
+/* We handle all bad expressions here, so that we can report the faulty
+ instruction in the error message. */
+void
+md_operand(expr)
+ expressionS *expr;
+{
+ if (in_my_get_expression)
+ {
+ expr->X_op = O_illegal;
+ if (inst.error == NULL)
+ inst.error = _("bad expression");
+ }
+}
+
/* UNRESTRICT should be one if <shift> <register> is permitted for this
instruction. */
if (p == * str)
{
- inst.error = _("Shift expression expected");
+ inst.error = _("shift expression expected");
return FAIL;
}
if (shift == NULL)
{
- inst.error = _("Shift expression expected");
+ inst.error = _("shift expression expected");
return FAIL;
}
about this though. */
if (num == 0)
{
- as_warn (_("Shift of 0 ignored."));
+ as_warn (_("shift of 0 ignored."));
shift = & shift_names[0];
assert (shift->properties->index == SHIFT_LSL);
}
else
{
- inst.error = _("Invalid immediate shift");
+ inst.error = _("invalid immediate shift");
return FAIL;
}
}
if (expr.X_op != O_constant)
{
- inst.error = _("Constant expression expected");
+ inst.error = _("constant expression expected");
return FAIL;
}
|| (expr.X_add_number & 1) != 0
|| ((unsigned) inst.reloc.exp.X_add_number) > 255)
{
- inst.error = _("Invalid constant");
+ inst.error = _("invalid constant");
return FAIL;
}
inst.instruction |= INST_IMMEDIATE;
inst.reloc.exp.X_add_number))
== FAIL)
{
- inst.error = _("Invalid constant");
+ inst.error = _("invalid constant");
return FAIL;
}
}
}
(*str)++;
- inst.error = _("Register or shift expression expected");
+ inst.error = _("register or shift expression expected");
return FAIL;
}
}
return SUCCESS;
}
- inst.error = _("Invalid floating point immediate expression");
+ inst.error = _("invalid floating point immediate expression");
return FAIL;
}
inst.error =
- _("Floating point register or immediate expression expected");
+ _("floating point register or immediate expression expected");
return FAIL;
}
}
if (skip_past_comma (&str) == FAIL)
{
- inst.error = _("Address expected");
+ inst.error = _("address expected");
return;
}
}
else if (*str == '=')
{
+ if ((inst.instruction & LOAD_BIT) == 0)
+ {
+ inst.error = _("invalid pseudo operation");
+ return;
+ }
+
/* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
str++;
if (inst.reloc.exp.X_op != O_constant
&& inst.reloc.exp.X_op != O_symbol)
{
- inst.error = _("Constant expression expected");
+ inst.error = _("constant expression expected");
return;
}
if (skip_past_comma (& str) == FAIL)
{
- inst.error = _("Address expected");
+ inst.error = _("address expected");
return;
}
if (skip_past_comma (& str) == FAIL)
{
- inst.error = _("Address expected");
+ inst.error = _("address expected");
return;
}
}
else if (*str == '=')
{
+ if ((inst.instruction & LOAD_BIT) == 0)
+ {
+ inst.error = _("invalid pseudo operation");
+ return;
+ }
+
/* XXX Does this work correctly for half-word/byte ops? */
/* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
str++;
if (inst.reloc.exp.X_op != O_constant
&& inst.reloc.exp.X_op != O_symbol)
{
- inst.error = _("Constant expression expected");
+ inst.error = _("constant expression expected");
return;
}
if (reg <= cur_reg)
{
- inst.error = _("Bad range in register list");
+ inst.error = _("bad range in register list");
return FAIL;
}
{
if (range & (1 << i))
as_tsktsk
- (_("Warning: Duplicated register (r%d) in register list"),
+ (_("Warning: duplicated register (r%d) in register list"),
i);
else
range |= 1 << i;
}
if (range & (1 << reg))
- as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
+ as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
reg);
else if (reg <= cur_reg)
- as_tsktsk (_("Warning: Register range not in ascending order"));
+ as_tsktsk (_("Warning: register range not in ascending order"));
range |= 1 << reg;
cur_reg = reg;
if (*str++ != '}')
{
- inst.error = _("Missing `}'");
+ inst.error = _("missing `}'");
return FAIL;
}
}
regno &= -regno;
regno = (1 << regno) - 1;
as_tsktsk
- (_("Warning: Duplicated register (r%d) in register list"),
+ (_("Warning: duplicated register (r%d) in register list"),
regno);
}
/* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
if (reg == REG_PC)
- as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
+ as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
end_of_line (str);
}
if (inst.reloc.exp.X_op != O_constant)
{
- inst.error = _("Constant value required for number of registers");
+ inst.error = _("constant value required for number of registers");
return;
}
if (reg == REG_PC)
{
inst.error =
- _("R15 not allowed as base register with write-back");
+ _("r15 not allowed as base register with write-back");
return;
}
}
if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
{
- inst.error = _("Invalid immediate for shift");
+ inst.error = _("invalid immediate for shift");
return;
}
}
else if (*str == '=')
{
+ if (load_store != THUMB_LOAD)
+ {
+ inst.error = _("invalid pseudo operation");
+ return;
+ }
+
/* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
str++;
}
else if (Rb == REG_PC && load_store != THUMB_LOAD)
{
- inst.error = _("R15 based store not allowed");
+ inst.error = _("r15 based store not allowed");
return;
}
else if (Ro != FAIL)
{
- inst.error = _("Invalid base register for register offset");
+ inst.error = _("invalid base register for register offset");
return;
}
if (offset & ~(0x1f << size))
{
- inst.error = _("Invalid offset");
+ inst.error = _("invalid offset");
return;
}
inst.instruction |= (offset >> size) << 6;
return;
if (*str != '!')
- as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
+ as_warn (_("inserted missing '!': load/store multiple always writes back base register"));
else
str++;
{
/* This really doesn't seem worth it. */
inst.reloc.type = BFD_RELOC_NONE;
- inst.error = _("Expression too complex");
+ inst.error = _("expression too complex");
return;
}
|| *str++ != ']')
{
if (! inst.error)
- inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
+ inst.error = _("syntax: ldrs[b] Rd, [Rb, Ro]");
return;
}
{
/* This really doesn't seem worth it. */
inst.reloc.type = BFD_RELOC_NONE;
- inst.error = _("Expression too complex");
+ inst.error = _("expression too complex");
return;
}
const struct reg_entry *r;
if ((map->htab = hash_new ()) == NULL)
- as_fatal (_("Virtual memory exhausted"));
+ as_fatal (_("virtual memory exhausted"));
for (r = map->names; r->name != NULL; r++)
insert_reg (r, map->htab);
|| (arm_cond_hsh = hash_new ()) == NULL
|| (arm_shift_hsh = hash_new ()) == NULL
|| (arm_psr_hsh = hash_new ()) == NULL)
- as_fatal (_("Virtual memory exhausted"));
+ as_fatal (_("virtual memory exhausted"));
build_arm_ops_hsh ();
for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
default:
*sizeP = 0;
- return _("Bad call to MD_ATOF()");
+ return _("bad call to MD_ATOF()");
}
t = atof_ieee (input_line_pointer, type, words);
else
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
+ _("unable to compute ADRL instructions for PC offset of 0x%lx"),
value);
break;
}
{
if (((unsigned long) value) > 0xff)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid swi expression"));
+ _("invalid swi expression"));
newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
newval |= value;
md_number_to_chars (buf, newval, THUMB_SIZE);
{
if (((unsigned long) value) > 0x00ffffff)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid swi expression"));
+ _("invalid swi expression"));
newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
newval |= value;
md_number_to_chars (buf, newval, INSN_SIZE);
case BFD_RELOC_ARM_MULTI:
if (((unsigned long) value) > 0xffff)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid expression in load/store multiple"));
+ _("invalid expression in load/store multiple"));
newval = value | md_chars_to_number (buf, INSN_SIZE);
md_number_to_chars (buf, newval, INSN_SIZE);
break;
if (! fixP->fx_done)
#endif
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("gas can't handle same-section branch dest >= 0x04000000"));
+ _("GAS can't handle same-section branch dest >= 0x04000000"));
}
value >>= 2;
value += diff;
if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch out of range"));
+ _("branch out of range"));
newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
}
md_number_to_chars (buf, newval, THUMB_SIZE);
value += diff;
if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch out of range"));
+ _("branch out of range"));
newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
}
md_number_to_chars (buf, newval, THUMB_SIZE);
value += diff;
if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch with link out of range"));
+ _("branch with link out of range"));
newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
sign = value >= 0;
if (value < -1023 || value > 1023 || (value & 3))
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Illegal value for co-processor offset"));
+ _("illegal value for co-processor offset"));
if (value < 0)
value = -value;
newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, target not word aligned (0x%08X)"),
+ _("invalid offset, target not word aligned (0x%08X)"),
(unsigned int) (fixP->fx_frag->fr_address
+ fixP->fx_where + value));
if ((value + 2) & ~0x3fe)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"), value);
/* Round up, since pc will be rounded down. */
newval |= (value + 2) >> 2;
case 9: /* SP load/store. */
if (value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"), value);
newval |= value >> 2;
break;
case 6: /* Word load/store. */
if (value & ~0x7c)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"), value);
newval |= value << 4; /* 6 - 2. */
break;
case 7: /* Byte load/store. */
if (value & ~0x1f)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"), value);
newval |= value << 6;
break;
case 8: /* Halfword load/store. */
if (value & ~0x3e)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
+ _("invalid offset, value too big (0x%08lX)"), value);
newval |= value << 5; /* 6 - 1. */
break;
{
if (value & ~0x1fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate for stack address calculation"));
+ _("invalid immediate for stack address calculation"));
newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
newval |= value >> 2;
}
if (subtract ||
value & ~0x3fc)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate for address calculation (value = 0x%08lX)"),
+ _("invalid immediate for address calculation (value = 0x%08lX)"),
(unsigned long) value);
newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
newval |= rd << 8;
{
if (value & ~0xff)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid 8bit immediate"));
+ _("invalid 8bit immediate"));
newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
newval |= (rd << 8) | value;
}
{
if (value & ~0x7)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid 3bit immediate"));
+ _("invalid 3bit immediate"));
newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
newval |= rd | (rs << 3) | (value << 6);
}
case 0x05: /* 8bit immediate CMP. */
if (value < 0 || value > 255)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate: %ld is too large"),
+ _("invalid immediate: %ld is too large"),
(long) value);
newval |= value;
break;
/* 5bit shift value (0..31). */
if (value < 0 || value > 31)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Illegal Thumb shift value: %ld"), (long) value);
+ _("illegal Thumb shift value: %ld"), (long) value);
newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
newval |= value << 6;
md_number_to_chars (buf, newval, THUMB_SIZE);
case BFD_RELOC_NONE:
default:
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
+ _("bad relocation fixup type (%d)"), fixP->fx_r_type);
}
}
/* If this is called then the a literal has been referenced across
a section boundary - possibly due to an implicit dump. */
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Literal referenced across section boundary (Implicit dump?)"));
+ _("literal referenced across section boundary (Implicit dump?)"));
return NULL;
#ifdef OBJ_ELF
case BFD_RELOC_ARM_IMMEDIATE:
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
+ _("internal relocation (type %d) not fixed up (IMMEDIATE)"),
fixp->fx_r_type);
return NULL;
case BFD_RELOC_ARM_OFFSET_IMM:
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
+ _("internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
fixp->fx_r_type);
return NULL;
default: type = _("<unknown>"); break;
}
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Cannot represent %s relocation in this object file format"),
+ _("cannot represent %s relocation in this object file format"),
type);
return NULL;
}
if (reloc->howto == NULL)
{
as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Can not represent %s relocation in this object file format"),
+ _("cannot represent %s relocation in this object file format"),
bfd_get_reloc_code_name (code));
return NULL;
}
}
static void
-output_inst PARAMS ((void))
+output_inst (str)
+ const char *str;
{
char * to = NULL;
if (inst.error)
{
- as_bad (inst.error);
+ as_bad ("%s -- `%s'", inst.error, str);
return;
}
if (p == str)
{
- as_bad (_("No operator -- statement `%s'\n"), str);
+ as_bad (_("no operator -- statement `%s'\n"), str);
return;
}
/* Check that this instruction is supported for this CPU. */
if (thumb_mode == 1 && (opcode->variant & cpu_variant) == 0)
{
- as_bad (_("selected processor does not support this opcode"));
+ as_bad (_("selected processor does not support `%s'"), str);
return;
}
inst.instruction = opcode->value;
inst.size = opcode->size;
(*opcode->parms) (p);
- output_inst ();
+ output_inst (str);
return;
}
}
/* Check that this instruction is supported for this CPU. */
if ((opcode->variant & cpu_variant) == 0)
{
- as_bad (_("selected processor does not support this opcode"));
+ as_bad (_("selected processor does not support `%s'"), str);
return;
}
inst.instruction = opcode->value;
inst.size = INSN_SIZE;
(*opcode->parms) (p);
- output_inst ();
+ output_inst (str);
return;
}
}
return 1;
}
- as_bad (_("Unrecognised APCS switch -m%s"), arg);
+ as_bad (_("unrecognised APCS switch -m%s"), arg);
return 0;
}
cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
break;
default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
+ as_bad (_("invalid architecture variant -m%s"), arg);
break;
}
break;
case 'm': cpu_variant |= ARM_EXT_V3M; break;
case 0: break;
default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
+ as_bad (_("invalid architecture variant -m%s"), arg);
break;
}
break;
case 't': cpu_variant |= ARM_EXT_V4T; break;
case 0: break;
default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
+ as_bad (_("invalid architecture variant -m%s"), arg);
break;
}
break;
case 'e': cpu_variant |= ARM_EXT_V5E; break;
case 0: break;
default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
+ as_bad (_("invalid architecture variant -m%s"), arg);
break;
}
break;
default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
+ as_bad (_("invalid architecture variant -m%s"), arg);
break;
}
break;
default:
bad:
- as_bad (_("Invalid processor variant -m%s"), arg);
+ as_bad (_("invalid processor variant -m%s"), arg);
return 0;
}
}
projects / deliverable / binutils-gdb.git / commitdiff
