drm/i915: Enable the overlay right after primary and cursor planes

Again follow the same sequence for all generations, because doing
otherwise just doesn't make sense.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 532a4fa67bb2fadd506d0e27eb6446c0441ab3d3..bf8fe819cfbd6d57569a050a30308fd87bc17d13 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3622,11 +3622,11 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
        intel_enable_plane(dev_priv, plane, pipe);
        intel_crtc_update_cursor(crtc, true);
 
-       intel_update_fbc(dev);
-
        /* Give the overlay scaler a chance to enable if it's on this pipe */
        intel_crtc_dpms_overlay(intel_crtc, true);
 
+       intel_update_fbc(dev);
+
        mutex_unlock(&dev_priv->dpio_lock);
 }
 
@@ -3664,11 +3664,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
        if (IS_G4X(dev))
                g4x_fixup_plane(dev_priv, pipe);
 
-       intel_update_fbc(dev);
-
        /* Give the overlay scaler a chance to enable if it's on this pipe */
        intel_crtc_dpms_overlay(intel_crtc, true);
 
+       intel_update_fbc(dev);
+
        for_each_encoder_on_crtc(dev, crtc, encoder)
                encoder->enable(encoder);
 }