drm/i915/skl: Implement WaDisableVFUnitClockGating
authorDamien Lespiau <damien.lespiau@intel.com>
Thu, 26 Feb 2015 18:20:39 +0000 (18:20 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 10 Apr 2015 06:55:59 +0000 (08:55 +0200)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index 9966d3294a02eceec1fadc251798d49ac411a57e..b01da4ebcebe1779bbf052ae77d1f4e61534af05 100644 (file)
@@ -6102,6 +6102,7 @@ enum skl_disp_power_wells {
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE                        (1 << 7)
 
 #define GEN6_UCGCTL2                           0x9404
+# define GEN6_VFUNIT_CLOCK_GATE_DISABLE                        (1 << 31)
 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE               (1 << 30)
 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE               (1 << 22)
 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE               (1 << 13)
index d76d6ab3775fab096865df5e3fd08c569d1378b5..67e1e61c50e7d380ca985bc7ad2222e1c55f9c39 100644 (file)
@@ -75,6 +75,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
                I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
                           GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+               /* WaDisableVFUnitClockGating:skl */
+               I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
+                          GEN6_VFUNIT_CLOCK_GATE_DISABLE);
        }
 
        if (INTEL_REVID(dev) <= SKL_REVID_D0) {
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