* ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,

	VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
	(powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
	vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
	vupklsh>: Use VXVA_MASK.
	<vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
	<mfvscr>: Use VXVAVB_MASK.
	<mtvscr>: Use VXVDVA_MASK.
	<vspltb>: Use VXUIMM4_MASK.
	<vsplth>: Use VXUIMM3_MASK.
	<vspltw>: Use VXUIMM2_MASK.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f54008040e792f7b8803d9491b92755e69a258bd..c89d7a12e323e3240fd24d82ac751080671b2dd4 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2012-08-28  Peter Bergner  <bergner@vnet.ibm.com>
+
+       * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
+       VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
+       (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
+       vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
+       vupklsh>: Use VXVA_MASK.
+       <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
+       <mfvscr>: Use VXVAVB_MASK.
+       <mtvscr>: Use VXVDVA_MASK.
+       <vspltb>: Use VXUIMM4_MASK.
+       <vsplth>: Use VXUIMM3_MASK.
+       <vspltw>: Use VXUIMM2_MASK.
+
 2012-08-24  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
        * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index e2824eff4a820b40e869893caf146d952a45ac69..57c075d7e9cfcaa2bbfb3c537e010babc801cf5b 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -610,6 +610,8 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The SR field in an X form instruction.  */
 #define SR SPRG + 1
+  /* The 4-bit UIMM field in a VX form instruction.  */
+#define UIMM4 SR
   { 0xf, 16, NULL, NULL, 0 },
 
   /* The STRM field in an X AltiVec form instruction.  */
@@ -680,8 +682,12 @@ const struct powerpc_operand powerpc_operands[] =
 #define DCTL UIMM
   { 0x1f, 16, NULL, NULL, 0 },
 
+  /* The 3-bit UIMM field in a VX form instruction.  */
+#define UIMM3 UIMM + 1
+  { 0x7, 16, NULL, NULL, 0 },
+
   /* The SHB field in a VA form instruction.  */
-#define SHB UIMM + 1
+#define SHB UIMM3 + 1
   { 0xf, 6, NULL, NULL, 0 },
 
   /* The other UIMM field in a half word EVX form instruction.  */
@@ -826,6 +832,8 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The UIM field in an XX2 form instruction.  */
 #define UIM DMEX + 1
+  /* The 2-bit UIMM field in a VX form instruction.  */
+#define UIMM2 UIM
   { 0x3, 16, NULL, NULL, 0 },
 
 #define ERAT_T UIM + 1
@@ -2313,6 +2321,27 @@ extract_vleil (unsigned long insn,
 /* The mask for an VX form instruction.  */
 #define VX_MASK        VX(0x3f, 0x7ff)
 
+/* A VX_MASK with the VA field fixed.  */
+#define VXVA_MASK (VX_MASK | (0x1f << 16))
+
+/* A VX_MASK with the VB field fixed.  */
+#define VXVB_MASK (VX_MASK | (0x1f << 11))
+
+/* A VX_MASK with the VA and VB fields fixed.  */
+#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11))
+
+/* A VX_MASK with the VD and VA fields fixed.  */
+#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16))
+
+/* A VX_MASK with a UIMM4 field.  */
+#define VXUIMM4_MASK (VX_MASK | (0x1 << 20))
+
+/* A VX_MASK with a UIMM3 field.  */
+#define VXUIMM3_MASK (VX_MASK | (0x3 << 19))
+
+/* A VX_MASK with a UIMM2 field.  */
+#define VXUIMM2_MASK (VX_MASK | (0x7 << 18))
+
 /* A VA form instruction.  */
 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
 
@@ -2867,7 +2896,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vmaxsb",     VX (4, 258),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vslb",       VX (4, 260),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vmulosb",    VX (4, 264),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrefp",      VX (4, 266),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vrefp",      VX (4, 266),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"vmrglb",     VX (4, 268),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vpkshus",    VX (4, 270),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"ps_nabs",    XRC(4, 136,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
@@ -2879,7 +2908,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vmaxsh",     VX (4, 322),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vslh",       VX (4, 324),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vmulosh",    VX (4, 328),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrsqrtefp",  VX (4, 330),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vrsqrtefp",  VX (4, 330),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"vmrglh",     VX (4, 332),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vpkswus",    VX (4, 334),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"mulchw",     XRC(4, 168,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
@@ -2891,14 +2920,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vaddcuw",    VX (4, 384),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vmaxsw",     VX (4, 386),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vslw",       VX (4, 388),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vexptefp",   VX (4, 394),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vexptefp",   VX (4, 394),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"vmrglw",     VX (4, 396),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vpkshss",    VX (4, 398),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"macchwsu",   XO (4, 204,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"macchwsu.",  XO (4, 204,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"vsl",                VX (4, 452),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vcmpgefp",   VXR(4, 454,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vlogefp",    VX (4, 458),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vlogefp",    VX (4, 458),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"vpkswss",    VX (4, 462),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"macchws",    XO (4, 236,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"macchws.",   XO (4, 236,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
@@ -2918,13 +2947,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vmuleub",    VX (4, 520),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"evneg",      VX (4, 521),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
 {"evextsb",    VX (4, 522),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vrfin",      VX (4, 522),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vrfin",      VX (4, 522),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"evextsh",    VX (4, 523),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
 {"evrndw",     VX (4, 524),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vspltb",     VX (4, 524),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
+{"vspltb",     VX (4, 524),    VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM4}},
 {"evcntlzw",   VX (4, 525),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
 {"evcntlsw",   VX (4, 526),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA}},
-{"vupkhsb",    VX (4, 526),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vupkhsb",    VX (4, 526),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"brinc",      VX (4, 527),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
 {"ps_abs",     XRC(4, 264,0),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
 {"ps_abs.",    XRC(4, 264,1),  XRA_MASK,    PPCPS,     PPCNONE,        {FRT, FRB}},
@@ -2964,9 +2993,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vsrh",       VX (4, 580),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vcmpgtuh",   VXR(4, 582,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vmuleuh",    VX (4, 584),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"vrfiz",      VX (4, 586),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
-{"vsplth",     VX (4, 588),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vupkhsh",    VX (4, 590),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vrfiz",      VX (4, 586),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vsplth",     VX (4, 588),    VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM3}},
+{"vupkhsh",    VX (4, 590),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"nget",       APU(4, 300,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
 {"evsel",      EVSEL(4,79),    EVSEL_MASK,  PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB, CRFS}},
 {"ncget",      APU(4, 316,0),  APU_RA_MASK, PPC405,    PPCNONE,        {RT, FSL}},
@@ -2981,12 +3010,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vcmpgtuw",   VXR(4, 646,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"evfsmul",    VX (4, 648),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
 {"evfsdiv",    VX (4, 649),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vrfip",      VX (4, 650),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vrfip",      VX (4, 650),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"evfscmpgt",  VX (4, 652),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"vspltw",     VX (4, 652),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
+{"vspltw",     VX (4, 652),    VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM2}},
 {"evfscmplt",  VX (4, 653),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
 {"evfscmpeq",  VX (4, 654),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"vupklsb",    VX (4, 654),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vupklsb",    VX (4, 654),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"evfscfui",   VX (4, 656),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
 {"evfscfsi",   VX (4, 657),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
 {"evfscfuf",   VX (4, 658),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RB}},
@@ -3011,11 +3040,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vcmpgtfp",   VXR(4, 710,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"efsmul",     VX (4, 712),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
 {"efsdiv",     VX (4, 713),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vrfim",      VX (4, 714),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vrfim",      VX (4, 714),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"efscmpgt",   VX (4, 716),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
 {"efscmplt",   VX (4, 717),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
 {"efscmpeq",   VX (4, 718),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {CRFD, RA, RB}},
-{"vupklsh",    VX (4, 718),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vupklsh",    VX (4, 718),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"efscfd",     VX (4, 719),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
 {"efscfui",    VX (4, 720),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
 {"efscfsi",    VX (4, 721),    VX_MASK,     PPCEFS|PPCVLE, PPCNONE,    {RS, RB}},
@@ -3075,7 +3104,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"evlhhesplat",        VX (4, 777),    VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
 {"vcfux",      VX (4, 778),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
 {"evlhhousplatx",VX(4, 780),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
-{"vspltisb",   VX (4, 780),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
+{"vspltisb",   VX (4, 780),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
 {"evlhhousplat",VX (4, 781),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, EVUIMM_2, RA}},
 {"evlhhossplatx",VX(4, 782),   VX_MASK,     PPCSPE|PPCVLE, PPCNONE,    {RS, RA, RB}},
 {"vpkpx",      VX (4, 782),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
@@ -3114,8 +3143,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vcmpgtsh",   VXR(4, 838,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vmulesh",    VX (4, 840),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vcfsx",      VX (4, 842),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vspltish",   VX (4, 844),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
-{"vupkhpx",    VX (4, 846),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vspltish",   VX (4, 844),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
+{"vupkhpx",    VX (4, 846),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"mullhw",     XRC(4, 424,0),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"mullhw.",    XRC(4, 424,1),  X_MASK,      MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"maclhw",     XO (4, 428,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
@@ -3127,12 +3156,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"vsraw",      VX (4, 900),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vcmpgtsw",   VXR(4, 902,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vctuxs",     VX (4, 906),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vspltisw",   VX (4, 908),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
+{"vspltisw",   VX (4, 908),    VXVB_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, SIMM}},
 {"maclhwsu",   XO (4, 460,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"maclhwsu.",  XO (4, 460,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"vcmpbfp",    VXR(4, 966,0),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vctsxs",     VX (4, 970),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB, UIMM}},
-{"vupklpx",    VX (4, 974),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
+{"vupklpx",    VX (4, 974),    VXVA_MASK,   PPCVEC|PPCVLE, PPCNONE,    {VD, VB}},
 {"maclhws",    XO (4, 492,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"maclhws.",   XO (4, 492,0,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"nmaclhws",   XO (4, 494,0,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
@@ -3310,13 +3339,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"nmacchwso",  XO (4, 238,1,0),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"nmacchwso.", XO (4, 238,1,1),XO_MASK,     MULHW|PPCVLE, PPCNONE,     {RT, RA, RB}},
 {"vsububs",    VX (4,1536),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"mfvscr",     VX (4,1540),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD}},
+{"mfvscr",     VX (4,1540),    VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE,    {VD}},
 {"vcmpgtub.",  VXR(4, 518,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"udi8fcm.",   APU(4, 771,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"udi8fcm",    APU(4, 771,1),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},
 {"vsum4ubs",   VX (4,1544),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vsubuhs",    VX (4,1600),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
-{"mtvscr",     VX (4,1604),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VB}},
+{"mtvscr",     VX (4,1604),    VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE,    {VB}},
 {"vcmpgtuh.",  VXR(4, 582,1),  VXR_MASK,    PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"vsum4shs",   VX (4,1608),    VX_MASK,     PPCVEC|PPCVLE, PPCNONE,    {VD, VA, VB}},
 {"udi9fcm.",   APU(4, 804,0),  APU_MASK,    PPC440,    PPC476,         {URT, URA, URB}},