From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Wed, 19 Jul 2017 07:56:55 +0000 (+0200)
Subject: [ARC] Add SJLI instruction.
X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=7179e0e6b2e0ed7b220af8836a88ef308faf5898;p=deliverable%2Fbinutils-gdb.git

[ARC] Add SJLI instruction.

include/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (SJLI): Add.

opcode/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (extract_uimm12_20): New function.
	(UIMM12_20): New operand.
	(SIMM3_5_S): Adjust.
	* arc-tbl.h (sjli): Add new instruction.
---

diff --git a/include/ChangeLog b/include/ChangeLog
index a31f62eea4..da1ce10a43 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* opcode/arc.h (SJLI): Add.
+
 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 	    John Eric Martin  <John.Martin@emmicro-us.com>
 
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 69b26303a2..cd8b1a8880 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -76,6 +76,7 @@ typedef enum
   PMU,
   POP,
   PUSH,
+  SJLI,
   STORE,
   SUB,
   ULTRAIP,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e789003512..d14b325215 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* arc-opc.c (extract_uimm12_20): New function.
+	(UIMM12_20): New operand.
+	(SIMM3_5_S): Adjust.
+	* arc-tbl.h (sjli): Add new instruction.
+
 2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
 	    John Eric Martin  <John.Martin@emmicro-us.com>
 
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 7f934ce5b5..f39704d384 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1269,6 +1269,18 @@ extract_nps_misc_imm_offset (unsigned long long  insn,
   return ((insn >> 8) & 0x1f) * 4;
 }
 
+static long long int
+extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
+		   bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = 0;
+
+  value |= ((insn >> 6) & 0x003f) << 0;
+  value |= ((insn >> 0) & 0x003f) << 6;
+
+  return value;
+}
+
 /* Include the generic extract/insert functions.  Order is important
    as some of the functions present in the .h may be disabled via
    defines.  */
@@ -1934,8 +1946,12 @@ const struct arc_operand arc_operands[] =
   {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
    insert_simm12_20, extract_simm12_20},
 
+  /* UIMM12_20 mask = 00000000000000000000111111222222.  */
+#define UIMM12_20	(SIMM12_20R + 1)
+  {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20},
+
   /* SIMM3_5_S mask = 0000011100000000.  */
-#define SIMM3_5_S	(SIMM12_20R + 1)
+#define SIMM3_5_S	(UIMM12_20 + 1)
   {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
    insert_simm3s, extract_simm3s},
 
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 07ff304acc..ab51f0d7dd 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -14535,6 +14535,9 @@
 /* sfxtr<.f><.cc> b,b,limm 00110bbb11101001FBBB1111100QQQQQ.  */
 { "sfxtr", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
 
+/* sjli u12 00101RRR101000001RRRuuuuuuUUUUUU.  */
+{ "sjli", 0x28A08000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, SJLI, CD1, { UIMM12_20 }, { 0 }},
+
 /* sleep c 00100001001011110000CCCCCC111111.  */
 { "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { RC }, { 0 }},