From: Maciej W. Rozycki Date: Sat, 29 May 2021 01:26:32 +0000 (+0200) Subject: MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=9573a461da18d73c5e34b68e40d31e4ab7abb000;p=deliverable%2Fbinutils-gdb.git MIPS/opcodes: Accurately record coprocessor opcode CPU/ISA membership Adjust opcode table entries for coprocessor instructions that have been removed from certain ISA levels or CPU implementations as follows: - remove CP0 memory access instructions from MIPS II up as the LWC0 and SWC0 opcodes have been reused for the LL and SC instructions respectively[1]; strictly speaking LWC0 and SWC0 have never really been defined in the first place[2], but let's keep them for now in case an odd implementation did, - remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as they have been removed as from those ISAs, - remove CP0 control register move instructions from MIPS32 up, as they have been removed as from that ISA[5], - remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it has been removed as from those ISAs in favour to ERET, - remove CP2 instructions from Vr5400 CPUs as their encodings have been reused for the multimedia instruction set extensions[8] and no CP2 registers exist[9], - remove CP3 memory access instructions from MIPS III up as coprocessor 3 has been removed as from that ISA[10][11] and from MIPS32 up as the LWC3 opcode has been reused for the PREF instruction and consequently all the four memory access instructions removed from the ISA (though the COP3 opcode has been retained)[12]. Update the testsuite accordingly. References: [1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding - MIPS II Architecture", p. A-178 [2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12 [3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS Technologies, Inc., January 29, 1997, Section 14.25 "CP0 Instructions", Subsection "Branch on Coprocessor 0", p. 285 [4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0 Encoding of rs Field", p. 242 [5] same [6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000 Opcode Bit Encoding", p. A-182 [8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 1.2.3 "CPU Instruction Set Overview", p. 9 [9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2", NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000, Section 19.2 "Multimedia Instruction Format", p. 681 [10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc., Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3 and CP3 load/store", p. A-176 [11] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture", p. A-179 [12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding of the Opcode Field", p. 241 opcodes/ * mips-opc.c (mips_builtin_opcodes): Update exclusion list for "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", "cop2", and "cop3" entries. gas/ * testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3 instruction removal. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index e5c2ecf80f..127dfc1480 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2021-05-29 Maciej W. Rozycki + + * testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3 + instruction removal. + * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise. + 2021-05-29 Maciej W. Rozycki * testsuite/gas/mips/cp0b.d: New test. diff --git a/gas/testsuite/gas/mips/mips32@isa-override-1.d b/gas/testsuite/gas/mips/mips32@isa-override-1.d index 75a8f0a063..27a42fd2e5 100644 --- a/gas/testsuite/gas/mips/mips32@isa-override-1.d +++ b/gas/testsuite/gas/mips/mips32@isa-override-1.d @@ -2,4 +2,49 @@ #name: MIPS ISA override code generation #as: -32 #source: isa-override-1.s -#dump: mips2@isa-override-1.d + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\) +[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\) +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at +[0-9a-f]+ <[^>]*> d4820000 ldc1 \$f2,0\(a0\) +[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0 +[0-9a-f]+ <[^>]*> 44811800 mtc1 at,\$f3 +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 44811000 mtc1 at,\$f2 +[0-9a-f]+ <[^>]*> dc820000 0xdc820000 +[0-9a-f]+ <[^>]*> 340189ab li at,0x89ab +[0-9a-f]+ <[^>]*> 00010c38 0x10c38 +[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at +[0-9a-f]+ <[^>]*> 3c029000 lui v0,0x9000 +[0-9a-f]+ <[^>]*> 00021438 0x21438 +[0-9a-f]+ <[^>]*> 34428000 ori v0,v0,0x8000 +[0-9a-f]+ <[^>]*> 00021438 0x21438 +[0-9a-f]+ <[^>]*> d4820000 ldc1 \$f2,0\(a0\) +[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0 +[0-9a-f]+ <[^>]*> 00010c38 0x10c38 +[0-9a-f]+ <[^>]*> 342189ab ori at,at,0x89ab +[0-9a-f]+ <[^>]*> 00010c38 0x10c38 +[0-9a-f]+ <[^>]*> 44a11000 0x44a11000 +[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\) +[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\) +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at +[0-9a-f]+ <[^>]*> d4820000 ldc1 \$f2,0\(a0\) +[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0 +[0-9a-f]+ <[^>]*> 44811800 mtc1 at,\$f3 +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 44811000 mtc1 at,\$f2 +[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\) +[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\) +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at +[0-9a-f]+ <[^>]*> d4820000 ldc1 \$f2,0\(a0\) +[0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0 +[0-9a-f]+ <[^>]*> 44811800 mtc1 at,\$f3 +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 44811000 mtc1 at,\$f2 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips32r2@isa-override-1.d b/gas/testsuite/gas/mips/mips32r2@isa-override-1.d index 0dc753adc2..77b6d3a71e 100644 --- a/gas/testsuite/gas/mips/mips32r2@isa-override-1.d +++ b/gas/testsuite/gas/mips/mips32r2@isa-override-1.d @@ -15,7 +15,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> 44811000 mtc1 at,\$f2 [0-9a-f]+ <[^>]*> 3c013ff0 lui at,0x3ff0 [0-9a-f]+ <[^>]*> 44e11000 mthc1 at,\$f2 -[0-9a-f]+ <[^>]*> dc820000 ldc3 \$2,0\(a0\) +[0-9a-f]+ <[^>]*> dc820000 0xdc820000 [0-9a-f]+ <[^>]*> 340189ab li at,0x89ab [0-9a-f]+ <[^>]*> 00010c38 0x10c38 [0-9a-f]+ <[^>]*> 00411025 or v0,v0,at diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 955c4b3b53..7f31e4e48d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2021-05-29 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Update exclusion list for + "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", + "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", + "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", + "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", + "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", + "cop2", and "cop3" entries. + 2021-05-29 Maciej W. Rozycki * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index a80e98164b..d396596535 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1276,10 +1276,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */ {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, -{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 }, +{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE }, +{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, I3_32|EE }, +{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE }, {"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 }, {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, @@ -1314,8 +1314,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"lw", "t,o(b)", 0x8c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lw", "s,-a(+R)", 0xec080000, 0xfc180000, WR_1|LM, RD_pc, I37, 0, 0 }, {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, I2 }, +{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, I2 }, {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, @@ -1323,10 +1323,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, /* lwc1 */ {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, -{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 }, +{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, +{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, I3_32|EE }, +{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE }, {"lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 }, {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 }, {"lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */ @@ -1854,10 +1854,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"sdc2", "E,+:(d)", 0x49e00000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, -{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 }, +{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE }, +{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, I3_32|EE }, +{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE }, {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, @@ -1980,8 +1980,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, {"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, {"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, -{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, I2 }, +{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, I2 }, {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, @@ -1989,10 +1989,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"swc2", "E,+:(d)", 0x49600000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, -{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 }, +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, +{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, I3_32|EE }, +{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE }, {"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 }, {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 }, {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */ @@ -2106,41 +2106,41 @@ const struct mips_opcode mips_builtin_opcodes[] = /* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the mfhc0 and mthc0 XPA instructions, so they have been placed here to allow the XPA instructions to take precedence. */ -{"cfc0", "t,g", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{"cfc0", "t,g", 0x40400000, 0xffe007ff, WR_1|RD_C0|LC, 0, I1, 0, I32 }, +{"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I32 }, /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format instructions so they are here for the latters to take precedence. */ {"bc2eqz", "E,p", 0x49200000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 }, -{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|I37 }, {"bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, N54|IOCT|IOCTP|IOCT2|I37 }, {"bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, {"bc2nez", "E,p", 0x49a00000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 }, -{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|I37 }, {"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, N54|IOCT|IOCTP|IOCT2|I37 }, {"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, -{"cfc2", "t,g", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{"cfc2", "t,g", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, {"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, {"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, {"cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LC, 0, EE, 0, 0 }, -{"ctc2", "t,g", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{"ctc2", "t,g", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, {"ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, {"ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, {"ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, EE, 0, 0 }, {"dmfc2", "t,i", 0x48200000, 0xffe00000, WR_1|RD_C2|LC, 0, IOCT, 0, 0 }, -{"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LC, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, +{"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LC, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE }, {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, WR_1|RD_C2|LC, 0, I64, 0, IOCT|IOCTP|IOCT2 }, {"dmtc2", "t,i", 0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, IOCT, 0, 0 }, -{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, +{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I3, 0, N54|IOCT|IOCTP|IOCT2|EE }, {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I64, 0, IOCT|IOCTP|IOCT2 }, -{"mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{"mfc2", "t,G", 0x48000000, 0xffe007ff, WR_1|RD_C2|LC, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, WR_1|RD_C2|LC, 0, I32, 0, IOCT|IOCTP|IOCT2 }, {"mfhc2", "t,G", 0x48600000, 0xffe007ff, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, {"mfhc2", "t,i", 0x48600000, 0xffe00000, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, -{"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, +{"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2 }, {"mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, @@ -2153,16 +2153,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X instructions, so they are here for the latters to take precedence. */ -{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, -{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE }, +{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE }, +{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE }, +{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE }, +{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE }, +{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I3_33|EE }, +{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE }, +{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, I3_33|EE }, +{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, I3_33|EE }, +{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, I3_33|EE }, /* Conflicts with the 4650's "mul" instruction. Nobody's using the 4010 any more, so move this insn out of the way. If the object @@ -2450,10 +2450,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, /* Move bc0* after mftr and mttr to avoid opcode collision. */ -{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, -{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 }, +{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I4_32 }, +{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 }, +{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I4_32 }, /* ST Microelectronics Loongson-2E and -2F. */ {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, @@ -3396,7 +3396,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, /* RFE conflicts with the new Virt spec instruction tlbgp. */ -{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, 0 }, +{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, I3_32 }, /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the @@ -3404,12 +3404,12 @@ const struct mips_opcode mips_builtin_opcodes[] = disassembler recognizes more specific versions first. */ {"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, {"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1, 0, 0 }, -{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, N54|IOCT|IOCTP|IOCT2 }, +{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, I3_33 }, {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2 }, +{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, I3_33 }, }; #define MIPS_NUM_OPCODES \