From: Peter Bergner <bergner@linux.ibm.com>
Date: Mon, 11 May 2020 00:00:19 +0000 (+0930)
Subject: Power10 Copy/Paste Extensions
X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=afef4fe97598e78acfaa8dc7cf06eebff442dedb;p=deliverable%2Fbinutils-gdb.git

Power10 Copy/Paste Extensions

opcodes/
	* opcodes/ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
	(L1OPT): Define.
	(powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
gas/
	* testsuite/gas/ppc/power10.d: Add paste. tests.
	* testsuite/gas/ppc/power10.s: Likewise.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 14b4c6fdf8..2f1caa7133 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
+
+	* testsuite/gas/ppc/power10.d: Add paste. tests.
+	* testsuite/gas/ppc/power10.s: Likewise.
+
 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 
 	* testsuite/gas/ppc/power10.s: New test.
diff --git a/gas/testsuite/gas/ppc/power10.d b/gas/testsuite/gas/ppc/power10.d
index 5d8198da5a..3fc4b4fb43 100644
--- a/gas/testsuite/gas/ppc/power10.d
+++ b/gas/testsuite/gas/ppc/power10.d
@@ -10,4 +10,7 @@ Disassembly of section \.text:
 .*:	(7d 40 06 a4|a4 06 40 7d) 	slbiag  r10
 .*:	(7d 40 06 a4|a4 06 40 7d) 	slbiag  r10
 .*:	(7d 41 06 a4|a4 06 41 7d) 	slbiag  r10,1
+.*:	(7c 2a 5f 0d|0d 5f 2a 7c) 	paste\.  r10,r11
+.*:	(7c 2a 5f 0d|0d 5f 2a 7c) 	paste\.  r10,r11
+.*:	(7c 0a 5f 0d|0d 5f 0a 7c) 	paste\.  r10,r11,0
 #pass
diff --git a/gas/testsuite/gas/ppc/power10.s b/gas/testsuite/gas/ppc/power10.s
index 9e7daf5618..116487c276 100644
--- a/gas/testsuite/gas/ppc/power10.s
+++ b/gas/testsuite/gas/ppc/power10.s
@@ -3,3 +3,6 @@ _start:
 	slbiag	10
 	slbiag	10,0
 	slbiag	10,1
+	paste.  10,11
+	paste.  10,11,1
+	paste.  10,11,0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 35aba3ded6..4493cb3465 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
+
+	* ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
+	(L1OPT): Define.
+	(powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
+
 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 
 	* ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 537171861c..8057f4a9d5 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -771,6 +771,29 @@ extract_fxm (uint64_t insn,
   return mask;
 }
 
+/* L field in the paste. instruction.  */
+
+static uint64_t
+insert_l1opt (uint64_t insn,
+	    int64_t value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 1) << 21);
+}
+
+static int64_t
+extract_l1opt (uint64_t insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid)
+{
+  /* Return a value of 1 for a missing optional operand.  */
+  if (*invalid < 0)
+    return 1;
+
+  return (insn >> 21) & 1;
+}
+
 static uint64_t
 insert_li20 (uint64_t insn,
 	     int64_t value,
@@ -2256,8 +2279,13 @@ const struct powerpc_operand powerpc_operands[] =
 #define HTM_R LOPT
   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
+  /* The optional L field in the paste. instruction. This is similar to LOPT
+     above, but with a default value of 1.  */
+#define L1OPT LOPT + 1
+  { 0x1, 21, insert_l1opt, extract_l1opt, PPC_OPERAND_OPTIONAL },
+
   /* The optional (for 32-bit) L field in cmp[l][i] instructions.  */
-#define L32OPT LOPT + 1
+#define L32OPT L1OPT + 1
   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
 
   /* The L field in dcbf instruction.  */
@@ -7123,7 +7151,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"extswsli",	XS(31,445,0),	XS_MASK,     POWER9,	0,		{RA, RS, SH6}},
 {"extswsli.",	XS(31,445,1),	XS_MASK,     POWER9,	0,		{RA, RS, SH6}},
 
-{"paste.",	XRCL(31,902,1,1),XRT_MASK,   POWER9,	0,		{RA0, RB}},
+{"paste.",	XRC(31,902,1),	XLRT_MASK,   POWER10,	0,		{RA0, RB, L1OPT}},
+{"paste.",	XRCL(31,902,1,1),XRT_MASK,   POWER9,	POWER10,	{RA0, RB}},
 
 {"stvlxl",	X(31,903),	X_MASK,	     CELL,	0,		{VS, RA0, RB}},
 {"stdfcmux",	APU(31,903,0),	APU_MASK,    PPC405,	0,		{FCRT, RA, RB}},