From: Chris Demetriou Date: Wed, 6 Mar 2002 06:21:17 +0000 (+0000) Subject: 2002-03-05 Chris Demetriou X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=d35d4f709fbc3d254fca5ec67aaeb820bf6a43e2;p=deliverable%2Fbinutils-gdb.git 2002-03-05 Chris Demetriou * sim-main.h (status_UX, status_SX, status_KX, status_TS) (status_PX, status_MX, status_CU0, status_CU1, status_CU2) (status_CU3): New definitions. * sim-main.h (ExceptionCause): Add new values for MIPS32 and MIPS64: MDMX, MCheck, CacheErr. Update comments for DebugBreakPoint and NMIReset to note their status in MIPS32 and MIPS64. (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) (SignalExceptionCacheErr): New exception macros. --- diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 3bcc294859..25ce89ce86 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,16 @@ +2002-03-05 Chris Demetriou + + * sim-main.h (status_UX, status_SX, status_KX, status_TS) + (status_PX, status_MX, status_CU0, status_CU1, status_CU2) + (status_CU3): New definitions. + + * sim-main.h (ExceptionCause): Add new values for MIPS32 + and MIPS64: MDMX, MCheck, CacheErr. Update comments + for DebugBreakPoint and NMIReset to note their status in + MIPS32 and MIPS64. + (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) + (SignalExceptionCacheErr): New exception macros. + 2002-03-05 Chris Demetriou * mips.igen (check_fpu): Enable check for coprocessor 1 usability. diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 1870c965cd..256dd1f7c9 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -534,6 +534,18 @@ struct sim_state { #define status_NMI (1 << 20) /* NMI */ #define status_NMI (1 << 20) /* NMI */ +/* Status bits used by MIPS32/MIPS64. */ +#define status_UX (1 << 5) /* 64-bit user addrs */ +#define status_SX (1 << 6) /* 64-bit supervisor addrs */ +#define status_KX (1 << 7) /* 64-bit kernel addrs */ +#define status_TS (1 << 21) /* TLB shutdown has occurred */ +#define status_PX (1 << 23) /* Enable 64 bit operations */ +#define status_MX (1 << 24) /* Enable MDMX resources */ +#define status_CU0 (1 << 28) /* Coprocessor 0 usable */ +#define status_CU1 (1 << 29) /* Coprocessor 1 usable */ +#define status_CU2 (1 << 30) /* Coprocessor 2 usable */ +#define status_CU3 (1 << 31) /* Coprocessor 3 usable */ + #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */ #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */ #define cause_CE_mask 0x30000000 /* Coprocessor exception */ @@ -611,9 +623,12 @@ enum ExceptionCause { IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */ Trap = 13, FPE = 15, - DebugBreakPoint = 16, + DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */ + MDMX = 22, Watch = 23, - NMIReset = 31, + MCheck = 24, + CacheErr = 30, + NMIReset = 31, /* Reserved in MIPS32/MIPS64. */ /* The following exception code is actually private to the simulator @@ -660,6 +675,10 @@ void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exceptio #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID) #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID) #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification) +#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX) +#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch) +#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck) +#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr) /* Co-processor accesses */