x86/Intel: fix fallout from earlier template folding
[deliverable/binutils-gdb.git] / gas / testsuite / gas / i386 /
2018-03-22  Jan Beulichx86/Intel: fix fallout from earlier template folding
2018-03-22  Jan Beulichx86: fold a few XOP templates
2018-03-09  H.J. Lux86: Encode EVEX instructions with VEX128 if possible
2018-03-09  H.J. Lux86: Strip whitespace in check_VecOperations
2018-03-09  H.J. Lux86: Optimize with EVEX128 encoding for AVX512VL
2018-03-08  H.J. Lux86-64: Also optimize "clr reg64"
2018-03-08  H.J. Lux86: Remove support for old (<= 2.8.1) versions of gcc
2018-03-08  Jan Beulichx86: correct operand size match checks for BMI/BMI2...
2018-03-08  Jan Beulichx86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_...
2018-03-08  Jan Beulichx86: extend SSE check to PCLMULQDQ, AES, and GFNI insns
2018-03-08  Jan Beulichx86/Intel: correct disassembly of fsub*/fdiv*
2018-03-08  Jan Beulichx86: adjust 4-XMM-register-group related warning
2018-03-08  Jan Beulichx86: bogus VMOVD with 64-bit operands should only allow...
2018-03-07  H.J. Lux86: Rewrite NOP generation for fill and alignment
2018-03-01  H.J. Lux86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128
2018-02-27  H.J. Lugas: Rename .nop directive to .nops
2018-02-27  H.J. Lux86: Add -O[2|s] assembler command-line options
2018-02-22  H.J. Lux86: Add {rex} pseudo prefix
2018-02-17  H.J. LuAdd .nop assembler directive
2018-02-13  H.J. Lux86-64: Generate branch with PLT32 relocation
2018-01-23  Igor TsimbalistEnable Intel PCONFIG instruction.
2018-01-23  Igor TsimbalistEnable Intel WBNOINVD instruction.
2018-01-17  Igor TsimbalistReplace CET bit with IBT and SHSTK bits.
2018-01-11  Igor TsimbalistRemove VL variants for 4FMAPS and 4VNNIW insns.
2018-01-10  Jan Beulichx86: fix Disp8 handling for scalar AVX512_4FMAPS insns
2018-01-10  Jan Beulichx86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants
2018-01-08  H.J. Lux86: Properly encode vmovd with 64-bit memeory
2018-01-03  Alan ModraUpdate year range in copyright notice of binutils files
2017-12-18  Jan Beulichx86: fold RegXMM/RegYMM/RegZMM into RegSIMD
2017-12-17  H.J. Lux86: Check pseudo prefix without instruction
2017-11-30  Jan Beulichx86/Intel: issue diagnostics for redundant segment...
2017-11-30  Jan BeulichRevert "x86: Update segment register check in Intel...
2017-11-26  H.J. Lugas: Update x86 sse-noavx tests
2017-11-24  Jan Beulichx86: reject further invalid AVX-512 masking constructs
2017-11-24  Jan Beulichx86: don't omit disambiguating suffixes from "fi*"
2017-11-23  Igor TsimbalistAdd Disp8MemShift for AVX512 VAES instructions.
2017-11-23  Jan Beulichx86: fix AVX-512 16-bit addressing
2017-11-23  Jan Beulichx86-64: always use unsigned 32-bit reloc for 32-bit...
2017-11-23  Jan Beulichx86: correct UDn
2017-11-23  Jan Beulichx86/Intel: don't report multiple errors for a single...
2017-11-22  H.J. Lux86: Add tests for -n option of x86 assembler
2017-11-20  Alan Modramingw gas testsuite fix
2017-11-16  Jan Beulichx86: ignore high register select bit(s) in 32- and...
2017-11-16  Jan Beulichix86/Intel: don't require memory operand size specifier...
2017-11-16  H.J. Lui386: Replace .code64/.code32 with .byte
2017-11-15  Jan Beulichx86: use correct register names
2017-11-15  Jan Beulichx86: drop VEXI4_Fixup()
2017-11-15  Jan Beulichx86-64: don't allow use of %axl as accumulator
2017-11-14  Jan Beulichx86: add disassembler support for XOP VPCOM* pseudo-ops
2017-11-14  Jan Beulichx86: add support for AVX-512 VPCMP*{B,W} pseudo-ops
2017-11-14  Jan Beulichx86: string insns don't allow displacements
2017-11-13  Jan Beulichx86: don't default variable shift count insns to 8...
2017-11-13  Jan Beulichx86/Intel: don't mistake riz/eiz as base register
2017-11-13  Jan Beulichx86-64/Intel: issue diagnostic for out of range displac...
2017-11-07  Alan Modrabundle_lock message tidy
2017-11-07  Alan Modrareadelf ngettext fixes
2017-10-26  H.J. Lux86: Check invalid XMM register in AVX512 gathers
2017-10-24  H.J. Lui386: Support .code64 directive only with 64-bit bfd
2017-10-23  Igor TsimbalistEnable Intel AVX512_BITALG instructions.
2017-10-23  Igor TsimbalistEnable Intel AVX512_VNNI instructions.
2017-10-23  Igor TsimbalistEnable Intel VPCLMULQDQ instruction.
2017-10-23  Igor TsimbalistEnable Intel VAES instructions.
2017-10-23  Igor TsimbalistEnable Intel GFNI instructions.
2017-10-23  Igor TsimbalistEnable Intel AVX512_VBMI2 instructions.
2017-09-09  H.J. Lux86: Remove restriction on NOTRACK prefix position
2017-08-01  H.J. Lux86: Update segment register check in Intel syntax
2017-07-21  Alexandre OlivaThis patch introduces support for specifing views in...
2017-07-05  Borislav PetkovX86: Disassemble primary opcode map's group 2 ModRM...
2017-06-21  H.J. Lux86: CET v2.0: Update incssp and setssbsy
2017-06-21  H.J. Lux86: CET v2.0: Rename savessp to saveprevssp
2017-06-21  H.J. Lux86: CET v2.0: Update NOTRACK prefix
2017-06-15  H.J. Lui386-dis: Add 2 tests with invalid bnd register
2017-05-23  H.J. Lux86: Update notrackbad tests for non-ELF targets
2017-05-22  H.J. Lux86: Add NOTRACK prefix support
2017-03-09  H.J. LuX86: Add pseudo prefixes to control encoding
2017-03-06  H.J. LuAdd support for Intel CET instructions
2017-03-06  H.J. LuUpdate x86-64-mpx-inval-2 test for COFF
2017-02-28  Jan Beulichx86: fix handling of 64-bit operand size VPCMPESTR...
2017-02-24  Jan Beulichx86: also correctly support TEST opcode aliases
2017-02-23  Jan Beulichx86: extend 64-bit invalid MPX insn forms testcase
2017-01-12  Igor TsimbalistEnable Intel AVX512_VPOPCNTDQ instructions
2017-01-02  Alan ModraUpdate year range in copyright notice of all files.
2016-11-28  Amit PawarX86: Ignore REX_B bit for 32-bit XOP instructions
2016-11-09  H.J. LuX86: Remove the .s suffix from EVEX vpextrw
2016-11-09  H.J. LuX86: Update opcode-suffix.d
2016-11-07  H.J. LuX86: Properly handle bad FPU opcode
2016-11-03  H.J. LuX86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
2016-11-02  Igor TsimbalistEnable Intel AVX512_4VNNIW instructions
2016-11-02  Igor TsimbalistEnable Intel AVX512_4FMAPS instructions
2016-10-21  H.J. LuX86: Remove pcommit instruction
2016-10-20  H.J. LuCheck invalid mask registers
2016-09-07  H.J. LuX86: Allow additional ISAs for IAMCU in assembler
2016-08-24  H.J. LuX86: Add ptwrite instruction
2016-08-19  Nick CliftonPlace .shstrtab section after .symtab and .strtab,...
2016-07-05  Jan Beulichx86: fix register check in check_qword_reg()
2016-07-01  Jan Beulichx86-64/MPX: relax no-RIP-relative-addressing testcase
2016-07-01  Jan Beulichx86-64/MPX: bndmk, bndldx, and bndstx don't allow RIP...
2016-07-01  Jan Beulichx86/MPX: fix address size handling
2016-07-01  Jan Beulichx86/Intel: don't accept bogus instructions
2016-07-01  Jan Beulichx86: allow suffix-less movzw and 64-bit movzb
next
This page took 0.11159 seconds and 7 git commands to generate.